diff --git a/Documentation/ABI/testing/sysfs-driver-wktmr-brcmstb b/Documentation/ABI/testing/sysfs-driver-wktmr-brcmstb
new file mode 100644
index 000000000000..e563f8b8d969
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-wktmr-brcmstb
@@ -0,0 +1,12 @@
+What:		/sys/bus/platform/drivers/brcm-waketimer/<MMIO-address>.waketimer/timeout
+Date:		November 21, 2014
+KernelVersion:	3.14
+Contact:	Brian Norris <norris@broadcom.com>
+Description:	The control file for the wakeup timer. This integer value
+		represents the number of seconds between a suspend operation
+		(e.g., S3 suspend-to-RAM) and the time at which the wakeup
+		timer should fire.
+
+		Values are -1 (default) or any non-negative integer. Units are
+		in seconds. The special value of -1 means the timer should not
+		wake up the system.
diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
new file mode 100644
index 000000000000..fe4299df8ecf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -0,0 +1,106 @@
+ARM Broadcom STB platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
+SoC shall have the following DT organization:
+
+Required root node properties:
+    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
+
+example:
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    model = "Broadcom STB (bcm7445)";
+    compatible = "brcm,bcm7445", "brcm,brcmstb";
+
+Further, syscon nodes that map platform-specific registers used for general
+system control is required:
+
+    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
+    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+
+hif-cpubiuctrl node
+-------------------
+
+Required properties:
+    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
+
+Optional properties:
+    - brcm,write-pairing: boolean property, when present indicates
+      that write pairing should be enabled for this chip
+
+example:
+    rdb {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "simple-bus";
+        ranges = <0 0x00 0xf0000000 0x1000000>;
+
+        sun_top_ctrl: syscon@404000 {
+            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
+            reg = <0x404000 0x51c>;
+        };
+
+        hif_cpubiuctrl: syscon@3e2400 {
+            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
+            reg = <0x3e2400 0x5b4>;
+            brcm,write-pairing;
+        };
+
+        hif_continuation: syscon@452000 {
+            compatible = "brcm,bcm7445-hif-continuation", "syscon";
+            reg = <0x452000 0x100>;
+        };
+    };
+
+Lastly, nodes that allow for support of SMP initialization and reboot are
+required:
+
+smpboot
+-------
+Required properties:
+
+    - compatible
+        The string "brcm,brcmstb-smpboot".
+
+    - syscon-cpu
+        A phandle / integer array property which lets the BSP know the location
+        of certain CPU power-on registers.
+
+        The layout of the property is as follows:
+            o a phandle to the "hif_cpubiuctrl" syscon node
+            o offset to the base CPU power zone register
+            o offset to the base CPU reset register
+
+    - syscon-cont
+        A phandle pointing to the syscon node which describes the CPU boot
+        continuation registers.
+            o a phandle to the "hif_continuation" syscon node
+
+example:
+    smpboot {
+        compatible = "brcm,brcmstb-smpboot";
+        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+        syscon-cont = <&hif_continuation>;
+    };
+
+reboot
+-------
+Required properties
+
+    - compatible
+        The string property "brcm,brcmstb-reboot".
+
+    - syscon
+        A phandle / integer array that points to the syscon node which describes
+        the general system reset registers.
+            o a phandle to "sun_top_ctrl"
+            o offset to the "reset source enable" register
+            o offset to the "software master reset" register
+
+example:
+    reboot {
+        compatible = "brcm,brcmstb-reboot";
+        syscon = <&sun_top_ctrl 0x304 0x308>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91304353eea4..0cd1e25ff478 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
 			    "arm,cortex-r4"
 			    "arm,cortex-r5"
 			    "arm,cortex-r7"
+			    "brcm,brahma-b15"
 			    "faraday,fa526"
 			    "intel,sa110"
 			    "intel,sa1100"
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index bae0d87a38b2..d1f0b98c8f3c 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -16,6 +16,7 @@ Main node required properties:
 	"arm,cortex-a9-gic"
 	"arm,cortex-a7-gic"
 	"arm,arm11mp-gic"
+	"brcm,brahma-b15-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
diff --git a/Documentation/devicetree/bindings/brcmstb/pm.txt b/Documentation/devicetree/bindings/brcmstb/pm.txt
new file mode 100644
index 000000000000..b558a5f8067e
--- /dev/null
+++ b/Documentation/devicetree/bindings/brcmstb/pm.txt
@@ -0,0 +1,132 @@
+** Broadcom STB Power Management
+
+Broadcom STB power management involves several hardware components which are
+documented here.
+
+* Always-On control block (AON CTRL)
+
+This hardware provides control registers for the "always-on" (even in low-power
+modes) hardware, such as the Power Management State Machine (PMSM).
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-aon-ctrl"
+- reg            : the register start and length for the AON CTRL block
+
+Example:
+
+aon-ctrl@f0410000 {
+	compatible = "brcm,brcmstb-aon-ctrl";
+	reg = <0xf0410000 0x400>;
+};
+
+* Memory controllers
+
+A Broadcom STB SoC typically has a number of independent memory controllers,
+each of which may have several associated hardware blocks, which are versioned
+independently (control registers, DDR PHYs, etc.). One might consider
+describing these controllers as a parent "memory controllers" block, which
+contains N sub-nodes (one for each controller in the system), each of which is
+associated with a number of hardware register resources (e.g., its PHY). See
+the example device tree snippet below.
+
+* MEMC (MEMory Controller)
+
+Represents a single memory controller instance.
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
+
+Should contain subnodes for any of the following relevant hardware resources:
+
+* DDR PHY control
+
+Control registers for this memory controller's DDR PHY.
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-ddr-phy-v225.1" or
+                   "brcm,brcmstb-ddr-phy-v240.1"
+- reg            : the DDR PHY register range
+
+* DDR SHIMPHY
+
+Control registers for this memory controller's DDR SHIMPHY.
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
+- reg            : the DDR SHIMPHY register range
+
+* MEMC DDR control
+
+Sequencer DRAM parameters and control registers. Used for Self-Refresh
+Power-Down (SRPD), among other things.
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-memc-ddr"
+- reg            : the MEMC DDR register range
+
+Example:
+
+memory_controllers {
+	ranges;
+	compatible = "simple-bus";
+
+	memc@0 {
+		compatible = "brcm,brcmstb-memc", "simple-bus";
+		ranges;
+
+		ddr-phy@f1106000 {
+			compatible = "brcm,brcmstb-ddr-phy-v240.1";
+			reg = <0xf1106000 0x21c>;
+		};
+
+		shimphy@f1108000 {
+			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+			reg = <0xf1108000 0xe4>;
+		};
+
+		memc-ddr@f1102000 {
+			reg = <0xf1102000 0x800>;
+			compatible = "brcm,brcmstb-memc-ddr";
+		};
+	};
+
+	memc@1 {
+		compatible = "brcm,brcmstb-memc", "simple-bus";
+		ranges;
+
+		ddr-phy@f1186000 {
+			compatible = "brcm,brcmstb-ddr-phy-v240.1";
+			reg = <0xf1186000 0x21c>;
+		};
+
+		shimphy@f1188000 {
+			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+			reg = <0xf1188000 0xe4>;
+		};
+
+		memc-ddr@f1182000 {
+			reg = <0xf1182000 0x800>;
+			compatible = "brcm,brcmstb-memc-ddr";
+		};
+	};
+
+	memc@2 {
+		compatible = "brcm,brcmstb-memc", "simple-bus";
+		ranges;
+
+		ddr-phy@f1206000 {
+			compatible = "brcm,brcmstb-ddr-phy-v240.1";
+			reg = <0xf1206000 0x21c>;
+		};
+
+		shimphy@f1208000 {
+			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+			reg = <0xf1208000 0xe4>;
+		};
+
+		memc-ddr@f1202000 {
+			reg = <0xf1202000 0x800>;
+			compatible = "brcm,brcmstb-memc-ddr";
+		};
+	};
+};
diff --git a/Documentation/devicetree/bindings/brcmstb/waketimer.txt b/Documentation/devicetree/bindings/brcmstb/waketimer.txt
new file mode 100644
index 000000000000..68c4329b6af0
--- /dev/null
+++ b/Documentation/devicetree/bindings/brcmstb/waketimer.txt
@@ -0,0 +1,20 @@
+* Broadcom STB Wake-up Timer
+
+The Broadcom STB wake-up timer provides a high-resolution timer, with the
+ability to wake up the system from low-power suspend/standby modes.
+
+Required properties:
+- compatible     : should contain "brcm,brcmstb-waketimer"
+- reg            : the register start and length for the WKTMR block
+- interrupts     : The TIMER interrupt
+- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
+                    interrupt controller node
+
+Example:
+
+waketimer@f0411580 {
+	compatible = "brcm,brcmstb-waketimer";
+	reg = <0xf0411580 0x14>;
+	interrupts = <0x3>;
+	interrupt-parent = <&aon_pm_l2_intc>;
+};
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
new file mode 100644
index 000000000000..b5e4b521f50f
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -0,0 +1,29 @@
+Broadcom GISB bus Arbiter controller
+
+Required properties:
+
+- compatible: should be "brcm,gisb-arb"
+- reg: specifies the base physical address and size of the registers
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this arbiter gets interrupt line from
+- interrupts: specifies the two interrupts (timeout and TEA) to be used from
+  the parent interrupt controller
+
+Optional properties:
+
+- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
+  masters are valid at the system level
+- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
+  masters. Should match the number of bits set in brcm,gisb-master-mask
+
+Example:
+
+gisb-arb@f0400000 {
+	compatible = "brcm,gisb-arb";
+	reg = <0xf0400000 0x800>;
+	interrupts = <0>, <2>;
+	interrupt-parent = <&sun_l2_intc>;
+
+	brcm,gisb-arb-master-mask = <0x7>;
+	brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
+};
diff --git a/Documentation/devicetree/bindings/clock/brcmstb-clock.txt b/Documentation/devicetree/bindings/clock/brcmstb-clock.txt
new file mode 100644
index 000000000000..74b9a2986fdd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcmstb-clock.txt
@@ -0,0 +1,120 @@
+Device Tree Clock bindings for brcmstb
+
+In addition to the platform bindings provided in-tree, the brcmstb common
+clock driver supports the following clock providers/consumers:
+
+	- CPU clock dividers (provider/consumer)
+	- bcm_clk_gate
+	- bcm_clk_sw
+
+=== CPU clock divider ===
+
+The CPU divider node serves as the sole clock for the CPU complex. It supports
+power-of-2 clock division, with a divider of "1" as the default highest-speed
+setting.
+
+Required properties:
+- compatible : shall be one of the following:
+	"brcm,brcmstb-cpu-clk-div"
+- reg : address and width of the divider configuration register
+- #clock-cells : shall be set to 0
+- clocks : phandle of clock provider which provides the source clock
+	   (this would typically be a "fixed-clock" type PLL)
+- div-table : list of (raw_value,divider) ordered pairs that correspond to the
+	      allowed clock divider settings
+- div-shift-width : least-significant bit position and width of divider value
+
+example:
+	cpupll: cpupll@0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1500000000>;
+	};
+
+	cpuclk: cpu-clk-div@0 {
+		compatible = "brcm,brcmstb-cpu-clk-div";
+		reg = <0xf03e257c 0x4>;
+		#clock-cells = <0>;
+		clocks = <&cpupll>;
+		div-table = <0x00 1 0x11 2 0x12 4 0x13 8 0x14 16>;
+		div-shift-width = <0 5>;
+	};
+
+	cpus {
+		cpu@0 {
+			clocks = <&cpuclk>;
+		};
+	};
+
+
+=== bcm_clk_gate ===
+
+bcm_clk_gate is a clock type very similar to the clk_gate defined in
+drivers/clk/clk-gate.  In fact, some of the code has been copied
+verbatim.  The main difference is that bcm_clk_gate may have a delay
+specified.  
+
+Required properties:
+- compatible: must be "brcm,brcmstb-gate-clk"
+- reg : the register address of the bit that gets set/unset.  The
+	register range will always have a size of four bytes.
+- #clock-cells : see clock-bindings.txt.
+- bit-shift -- the bit position of reg that enables/disables the clock.
+
+Optional properties:
+- clocks : see clock-bindings.txt.
+- clock-names : see clock-bindings.txt.
+- set-bit-to-disable : inverts default gate programming. Setting the bit
+	gates the clock and clearing the bit ungates the clock.
+- brcm,delay : this indicates that there must be a delay after the
+	bit is changed.  The first parameter is the delay in usec
+	after the bit is being set to 0.  The second parameter is the
+	delay in usec after the bit is being set to 1.  So for the
+	example of <0 200>, there must be a delay of 200 usec after
+	setting the bit to 1.  
+- clock-output-names : see clock-bindings.txt.
+- brcm,read-only : specified if a clock can whose enable and 
+	disable actions do nothing as they do not write the
+	register.  This is a boolean.
+- brcm,inhibit-disable : specified if a clock is allowed to
+	enable but not disable; ie the disable action does
+	nothing.  This is a boolean.
+
+example:
+	lc_pll_reseta : lc_pll_reseta@f04e014c {
+		compatible = "brcm,brcmstb-gate-clk";
+		#clock-cells = <0>;
+		reg = <0xf04e014c 0x4>;
+		bit-shift = <0>;
+		set-bit-to-disable;
+		brcm,delay = <0 200>;
+		clocks = <&iso_ck_pll_lc>; 
+		clock-names = "iso_ck_pll_lc"; 
+
+
+=== bcm_clk_sw ===
+
+bcm_clk_sw is a clock type which has no hardware counterpart: it
+is used solely to enable/disable one or more parent clocks in
+unison.  
+
+Required properties:
+- compatible : must be "brcm,brcmstb-sw-clk"
+- #clock-cells : see clock-bindings.txt.
+
+Optional properties:
+- clocks : the list of parent clocks.  
+- clock-names : the names of the parent clocks in the same order
+	as the 'clocks' property.
+
+Example:
+	top_usb21 : top_usb21 {
+		compatible = "brcm,brcmstb-sw-clk";
+		#clock-cells = <0>;
+		clocks = <&usb1_27_mdio_ck>, <&usb1_freerun_ck>, 
+		  <&usb1_gisb_ck>, <&usb1_scb_ck>, <&usb1_108_ck_ahb>, 
+		  <&usb1_108_ck_axi>, <&lc_pll_pst_div_hld_ch1>; 
+		clock-names = "usb1_27_mdio_ck", "usb1_freerun_ck", 
+		  "usb1_gisb_ck", "usb1_scb_ck", "usb1_108_ck_ahb", 
+		  "usb1_108_ck_axi", "lc_pll_pst_div_hld_ch1"; 
+	};
diff --git a/Documentation/devicetree/bindings/clock/divider-clock.txt b/Documentation/devicetree/bindings/clock/divider-clock.txt
new file mode 100644
index 000000000000..e0e341d164e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/divider-clock.txt
@@ -0,0 +1,97 @@
+Binding for simple divider clock.
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent.  By default the value programmed into
+the register is one less than the actual divisor value.  E.g:
+
+register value		actual divisor value
+0			1
+1			2
+2			3
+
+This assumption may be modified by the following optional properties:
+
+index-starts-at-one - valid divisor values start at 1, not the default
+of 0.  E.g:
+register value		actual divisor value
+1			1
+2			2
+3			3
+
+index-power-of-two - valid divisor values are powers of two.  E.g:
+register value		actual divisor value
+0			1
+1			2
+2			4
+
+index-allow-zero - same as index_one, but zero is divide-by-1.  E.g:
+register value		actual divisor value
+0			1
+1			1
+2			2
+
+index-max-at-zero - same as index_one, but zero is 2^width.  E.g. for
+a clk register field of width 2:
+0			4
+1			1
+2			2
+3			3
+
+Additionally a table of valid dividers may be supplied like so:
+
+	table = <4 0>, <8, 1>;
+
+where the first value in the pair is the divider and the second value is
+the programmed register bitfield.
+
+The binding must also provide the register to control the divider and
+the mask for the corresponding control bits.  Optionally the number of
+bits to shift that mask, if necessary.  If the shift value is missing it
+is the same as supplying a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable divider
+- bit-mask : arbitrary bitmask for programming the adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- table : array of integer pairs defining divisors & bitfield values
+- bit-shift : number of bits to shift the bit-mask, defaults to
+  (ffs(mask) - 1) if not present
+- minimum-divider : min divisor for dividing the input clock rate, only
+  needed if the first divisor is offset from the default value
+- maximum-divider : max divisor for dividing the input clock rate, only
+  needed if the max divisor is less than (mask + 1).
+- index-starts-at-one : valid divisor programming starts at 1, not zero
+- index-power-of-two : valid divisor programming must be a power of two
+- index-allow-zero : implies index-one, and programming zero results in
+  divide-by-one
+- hiword-mask : lower half of the register programs the divider, upper
+  half of the register indicates bits that were updated in the lower
+  half
+
+Examples:
+	clock_foo: clock_foo at 4a008100 {
+		compatible = "divider-clock";
+		#clock-cells = <0>;
+		clocks = <&clock_baz>;
+		reg = <0x4a008100 0x4>
+		mask = <0x3>
+		maximum-divider = <3>
+	};
+
+	clock_bar: clock_bar at 4a008108 {
+		#clock-cells = <0>;
+		compatible = "divider-clock";
+		clocks = <&clock_foo>;
+		reg = <0x4a008108 0x4>;
+		mask = <0x1>;
+		shift = <0>;
+		table = < 4 0 >, < 8 1 >;
+	};
diff --git a/Documentation/devicetree/bindings/clock/multiplier-clock.txt b/Documentation/devicetree/bindings/clock/multiplier-clock.txt
new file mode 100644
index 000000000000..ca682ef1fb13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/multiplier-clock.txt
@@ -0,0 +1,84 @@
+Binding for simple multiplier clock.
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped adjustable clock rate multiplier that does not gate and has
+only one input clock or parent.  By default the value programmed into
+the register is one less than the actual multiplier value.  E.g:
+
+register value		actual multiplier value
+0			1
+1			2
+2			3
+
+This assumption may be modified by the following optional properties:
+
+index-starts-at-one - valid multiplier values start at 1, not the default
+of 0.  E.g:
+register value		actual multiplier value
+1			1
+2			2
+3			3
+
+index-power-of-two - valid multiplier values are powers of two.  E.g:
+register value		actual multiplier value
+0			1
+1			2
+2			4
+
+index-allow-zero - same as index_one, but zero is multiply-by-1.  E.g:
+register value		actual multiplier value
+0			1
+1			1
+2			2
+
+Additionally a table of valid multipliers may be supplied like so:
+
+	table = <4 0>, <8, 1>;
+
+where the first value in the pair is the multiplier and the second value is
+the programmed register bitfield.
+
+The binding must also provide the register to control the multiplier and
+the mask for the corresponding control bits.  Optionally the number of
+bits to shift that mask, if necessary.  If the shift value is missing it
+is the same as supplying a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "multiplier-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : base address for register controlling adjustable multiplier
+- bit-mask : arbitrary bitmask for programming the adjustable multiplier
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- table : array of integer pairs defining multipliers & bitfield values
+- bit-shift : number of bits to shift the bit-mask, defaults to
+  (ffs(mask) - 1) if not present
+- index-starts-at-one : valid multiplier programming starts at 1, not zero
+- index-power-of-two : valid multiplier programming must be a power of two
+- index-allow-zero : implies index-one, and programming zero results in
+  multiply-by-one
+- index-max-mult-at-zero : same as index-starts-at-one, but the value
+  of zero implies a multiplier of 2^width of the register field.
+
+Examples:
+	clock_foo: clock_foo at 4a008100 {
+		compatible = "multiplier-clock";
+		#clock-cells = <0>;
+		clocks = <&clock_baz>;
+		reg = <0x4a008100 0x4>
+		mask = <0x3>
+	};
+
+	clock_bar: clock_bar at 4a008108 {
+		#clock-cells = <0>;
+		compatible = "multiplier-clock";
+		clocks = <&clock_foo>;
+		reg = <0x4a008108 0x4>;
+		mask = <0x1>;
+		shift = <0>;
+		table = < 4 0 >, < 8 1 >;
+	};
diff --git a/Documentation/devicetree/bindings/clock/mux-clock.txt b/Documentation/devicetree/bindings/clock/mux-clock.txt
new file mode 100644
index 000000000000..4746f3b5d223
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mux-clock.txt
@@ -0,0 +1,79 @@
+Binding for simple mux clock.
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped multiplexer with multiple input clock signals or
+parents, one of which can be selected as output.  This clock does not
+gate or adjust the parent rate via a divider or multiplier.
+
+By default the "clocks" property lists the parents in the same order
+as they are programmed into the regster.  E.g:
+
+	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
+
+results in programming the register as follows:
+
+register value		selected parent clock
+0			foo_clock
+1			bar_clock
+2			baz_clock
+
+Some clock controller IPs do not allow a value of zero to be programmed
+into the register, instead indexing begins at 1.  The optional property
+"index-starts-at-one" modified the scheme as follows:
+
+register value		selected clock parent
+1			foo_clock
+2			bar_clock
+3			baz_clock
+
+Additionally an optional table of bit and parent pairs may be supplied
+like so:
+
+	table = <&foo_clock 0x0>, <&bar_clock, 0x2>, <&baz_clock, 0x4>;
+
+where the first value in the pair is the parent clock and the second
+value is the bitfield to be programmed into the register.
+
+The binding must provide the register to control the mux and the mask
+for the corresponding control bits.  Optionally the number of bits to
+shift that mask if necessary.  If the shift value is missing it is the
+same as supplying a zero shift.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "mux-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks
+- reg : base address for register controlling adjustable mux
+- bit-mask : arbitrary bitmask for programming the adjustable mux
+
+Optional properties:
+- clock-output-names : From common clock binding.
+- table : array of integer pairs defining parents & bitfield values
+- bit-shift : number of bits to shift the bit-mask, defaults to
+  (ffs(mask) - 1) if not present
+- index-starts-at-one : valid input select programming starts at 1, not
+  zero
+- hiword-mask : lower half of the register programs the mux, upper half
+  of the register indicates bits that were updated in the lower half
+
+Examples:
+	clock: clock at 4a008100 {
+		compatible = "mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
+		reg = <0x4a008100 0x4>
+		mask = <0x3>;
+		index-starts-at-one;
+	};
+
+	clock: clock at 4a008100 {
+		#clock-cells = <0>;
+		compatible = "mux-clock";
+		clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>;
+		reg = <0x4a008100 0x4>;
+		mask = <0x3>;
+		shift = <0>;
+		table = <&clock_foo 1>, <&clock_bar 2>, <&clock_baz 3>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
new file mode 100644
index 000000000000..5eb6b4a971a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
@@ -0,0 +1,85 @@
+Broadcom STB "UPG GIO" GPIO controller
+
+The controller's registers are organized as sets of eight 32-bit
+registers with each set controlling a bank of up to 32 pins.  A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+
+- compatible:
+    Must be "brcm,brcmstb-gpio"
+
+- reg:
+    Define the base and range of the I/O address space containing
+    the brcmstb GPIO controller registers
+
+- #gpio-cells:
+    Should be <2>.  The first cell is the pin number (within the controller's
+    pin space), and the second is used for the following:
+    bit[0]: polarity (0 for active-high, 1 for active-low)
+
+- gpio-controller:
+    Specifies that the node is a GPIO controller.
+
+- brcm,gpio-bank-widths:
+    Number of GPIO lines for each bank.  Number of elements must
+    correspond to number of banks suggested by the 'reg' property.
+
+Optional properties:
+
+- interrupts:
+    The interrupt shared by all GPIO lines for this controller.
+
+- interrupt-parent:
+    phandle of the parent interrupt controller
+
+- interrupts-extended:
+    Alternate form of specifying interrupts and parents that allows for
+    multiple parents.  This takes precedence over 'interrupts' and
+    'interrupt-parent'.  This probably must be used if the wakeup-source
+    property is provided because that may have a different interrupt parent.
+
+- #interrupt-cells:
+    Should be <2>.  The first cell is the GPIO number, the second should specify
+    flags.  The following subset of flags is supported:
+    - bits[3:0] trigger type and level flags
+        1 = low-to-high edge triggered
+        2 = high-to-low edge triggered
+        4 = active high level-sensitive
+        8 = active low level-sensitive
+      Valid combinations are 1, 2, 3, 4, 8.
+    See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+- interrupt-controller:
+    Marks the device node as an interrupt controller
+
+- wakeup-source:
+    GPIOs for this controller can be used as a wakeup source
+
+Example:
+	upg_gio: gpio@f040a700 {
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+		gpio-controller;
+		interrupt-controller;
+		reg = <0xf040a700 0x80>;
+		interrupt-parent = <&irq0_intc>;
+		interrupts = <0x6>;
+		brcm,gpio-bank-widths = <32 32 32 24>;
+	};
+
+	upg_gio_aon: gpio@f04172c0 {
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+		gpio-controller;
+		interrupt-controller;
+		reg = <0xf04172c0 0x40>;
+		interrupt-parent = <&irq0_aon_intc>;
+		interrupts = <0x6>;
+		interrupts-extended = <&irq0_aon_intc 0x6>,
+			<&aon_pm_l2_intc 0x5>;
+		wakeup-source;
+		brcm,gpio-bank-widths = <18 4>;
+	};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt
new file mode 100644
index 000000000000..aeceaceba3c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt
@@ -0,0 +1,28 @@
+Broadcom stb bsc iic master controller
+
+Required properties:
+
+- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c"
+- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz
+		   valid values are 375000, 390000, 187500, 200000
+		   93750, 97500, 46875 and 50000
+- reg: specifies the base physical address and size of the registers
+
+Optional properties :
+
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this one is cascaded from
+- interrupts: specifies the interrupt number, the irq line to be used
+- interrupt-names: Interrupt name string
+
+Example:
+
+bsca: i2c@f0406200 {
+      clock-frequency = <390000>;
+      compatible = "brcm,brcmstb-i2c";
+      interrupt-parent = <&irq0_intc>;
+      reg = <0xf0406200 0x58>;
+      interrupts = <0x18>;
+      interrupt-names = "upg_bsca";
+};
+
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
new file mode 100644
index 000000000000..2f53633db0de
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@@ -0,0 +1,39 @@
+Broadcom BCM7120 Level 2 interrupt controller
+
+Required properties:
+
+- compatible: should be "brcm,bcm7120-l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this one is cascaded from
+- interrupts: specifies the interrupt line(s) in the interrupt-parent domain
+  to be used for cascading
+- brcm,int-map-mask: 32-bits bit mask describing how the interrupts at this level
+  map to their respective parents. Should match exactly the number of interrupts
+  specified in the 'interrupts' property.
+
+Optional properties:
+
+- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
+  wakeup source for system suspend/resume.
+
+- brcm,int-fwd-mask: if present, a 32-bits bit mask describing the interrupts
+  which need to be enabled in this controller to flow to the higher level
+  interrupt controller.
+
+Example:
+
+irq0_intc: interrupt-controller@f0406800 {
+	compatible = "brcm,bcm7120-l2-intc";
+	interrupt-parent = <&intc>;
+	#interrupt-cells = <1>;
+	reg = <0xf0406800 0x8>;
+	interrupt-controller;
+	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+	interrupt-names = "upg_main", "upg_bsc";
+	brcm,int-map-mask = <0xeb8>, <0x140>;
+	brcm,int-fwd-mask = <0x7>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
new file mode 100644
index 000000000000..448273a30a11
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
@@ -0,0 +1,29 @@
+Broadcom Generic Level 2 Interrupt Controller
+
+Required properties:
+
+- compatible: should be "brcm,l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an
+  interrupt source. Should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this controller is cacaded from
+- interrupts: specifies the interrupt line in the interrupt-parent irq space
+  to be used for cascading
+
+Optional properties:
+
+- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
+  wakeup source for system suspend/resume.
+
+Example:
+
+hif_intr2_intc: interrupt-controller@f0441000 {
+	compatible = "brcm,l2-intc";
+	reg = <0xf0441000 0x30>;
+	interrupt-controller;
+	#interrupt-cells = <1>;
+	interrupt-parent = <&intc>;
+	interrupts = <0x0 0x20 0x0>;
+};
diff --git a/Documentation/devicetree/bindings/misc/sram.txt b/Documentation/devicetree/bindings/misc/sram.txt
index 4d0a00e453a8..fc240f40fdef 100644
--- a/Documentation/devicetree/bindings/misc/sram.txt
+++ b/Documentation/devicetree/bindings/misc/sram.txt
@@ -4,7 +4,8 @@ Simple IO memory regions to be managed by the genalloc API.
 
 Required properties:
 
-- compatible : mmio-sram
+- compatible : "mmio-sram" for generic SRAM, or
+               "brcm,boot-sram" for the boot SRAM on Broadcom SoCs
 
 - reg : SRAM iomem address range
 
diff --git a/Documentation/devicetree/bindings/moca/bmoca.txt b/Documentation/devicetree/bindings/moca/bmoca.txt
new file mode 100644
index 000000000000..0bd1af6ffdca
--- /dev/null
+++ b/Documentation/devicetree/bindings/moca/bmoca.txt
@@ -0,0 +1,36 @@
+* Broadcom STB MoCA driver bindings
+
+The Broadcom STB MoCA core driver provides access to the moca core
+for setting various moca properties and loading moca FW
+
+Required properties:
+ compatible     : should contain "brcm,bmoca-instance"
+ reg            : the register start and length for MoCA controller
+ interrupts     : The MoCA interrupt
+ #address-cells : <1>
+ #size-cells    : <1>
+ mac-address	: 6-byte mac address
+ rf-band	: rf band string, possible values "highrf, midrf, wanrf,
+		  ext_d, d_low, d_high, e, f, g
+ hw-rev		: HW revision number
+ enet-id	: phandle to the internal ethernet phy (bcmgenet)
+
+Optional properties:
+ use-dma	: boolean, indicating controller support for DMA
+ i2c-base	: MoCA i2c base register address
+ i2c-addr	: i2c slave address
+ use-spi	: boolean, indicating controller support for spi interface
+
+Example:
+
+	bmoca@f0e00000 {
+		compatible = "brcm,bmoca-instance";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		mac-address = [ 00 10 18 03 25 d7 ];
+		rf-band = "highrf";
+		reg = <0xf0e00000 0x1ffda0>;
+		interrupts = <0x0 0x1d 0x0>;
+		hw-rev = <0x2003>;
+		enet-id = <0x7>;
+	};
diff --git a/Documentation/devicetree/bindings/mtd/brcmstb_nand.txt b/Documentation/devicetree/bindings/mtd/brcmstb_nand.txt
new file mode 100644
index 000000000000..bf75c78da999
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/brcmstb_nand.txt
@@ -0,0 +1,68 @@
+* Broadcom STB NAND Controller
+
+The Broadcom STB NAND controller utilizes the MTD subsystem to provide generic
+access to NAND flash chips.
+
+Required properties:
+- compatible     : should contain "brcm,brcmnand" and an appropriate version
+                   compatibility string, like "brcm,brcmnand-v7.0"
+- reg            : the register start and length for NAND and (if present)
+                   FLASH_DMA blocks
+- reg-names      : a list of the names corresponding to the previous register
+		   ranges. Should contain "nand" and (if FLASH_DMA is
+                   available) "flash-dma".
+- interrupts     : The HIF L2 interrupts for NAND_CLTRDY and (if FLASH_DMA is
+                   available) FLASH_DMA_DONE
+- interrupt-parent: The phandle to the HIF L2 interrupt controller node
+- #address-cells : <1> - subnodes give the chip-select number
+- #size-cells    : <0>
+
+Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes
+to represent enabled chip-selects which (may) contain NAND flash chips. Their
+properties are as follows.
+
+Required properties:
+- compatible        : should contain "brcm,nandcs"
+- reg               : a single integer representing the chip-select number
+                      (e.g., 0, 1, 2, etc.)
+- #address-cells    : see partition.txt
+- #size-cells       : see partition.txt
+
+Optional properties:
+- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this chip-select
+
+Each nandcs device node may optionally contain sub-nodes describing the flash
+partition mapping. See partition.txt for more detail.
+
+Example:
+
+nand@f0442800 {
+	compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
+	reg = <0xF0442800 0x600>,
+	      <0xF0443000 0x100>;
+	reg-names = "nand", "flash-dma";
+	interrupt-parent = <&hif_intr2_intc>;
+	interrupts = <24>, <4>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@1 {
+		compatible = "brcm,nandcs";
+		reg = <1>; // Chip select 1
+		nand-on-flash-bbt;
+
+		// Partitions
+		#address-cells = <1>;  // <2>, for 64-bit offset
+		#size-cells = <1>;     // <2>, for 64-bit length
+		flash0.rootfs@0 {
+			reg = <0 0x10000000>;
+		};
+		flash0@0 {
+			reg = <0 0>; // MTDPART_SIZ_FULL
+		};
+		flash0.kernel@10000000 {
+			reg = <0x10000000 0x400000>;
+		};
+	};
+};
diff --git a/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
new file mode 100644
index 000000000000..9100620cba49
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
@@ -0,0 +1,118 @@
+* Broadcom BCM7xxx Ethernet Controller (GENET)
+
+Required properties:
+- compatible: should be "brcm,genet-v1", "brcm,genet-v2", "brcm,genet-v3",
+  "brcm,genet-v4".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+- mdio bus node: this node should always be present regarless of the PHY
+  configuration of the GENET instance
+- phy-mode: The interface between the SoC and the PHY (a string that
+  of_get_phy_mode() can understand).
+
+MDIO bus node required properties:
+
+- compatible: should be "brcm,genet-v<N>-mdio"
+- reg: address and length relative to the parent node base register address
+- address-cells: address cell for MDIO bus addressing, should be 1
+- size-cells: size of the cells for MDIO bus addressing, should be 0
+
+Optional properties:
+- phy-handle: A phandle to a phy node defining the PHY address (as the reg
+  property, a single integer), used to describe configurations where a PHY
+  (internal or external) is used.
+
+- fixed-link: When the GENET interface is connected to a MoCA hardware block
+  or when operating in a RGMII to RGMII type of connection, or when the
+  MDIO bus is voluntarily disabled, this property should be used to describe
+  the "fixed link", the property is described as follows:
+
+  fixed-link: <a b c d e> where a is emulated phy id - choose any,
+  but unique to the all specified fixed-links, b is duplex - 0 half,
+  1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
+  pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
+
+- clocks: When provided, must be two phandles to the functional clock nodes
+  of the GENET block. The first phandle is the main GENET clock used during
+  normal operation, while the second phandle is the Wake-on-LAN clock.
+
+- clock-names: When provided, names of the functional clock phandles, first
+  name should be "sw_genet" and second should be "sw_genetwol".
+
+Internal Gigabit PHY example:
+
+ethernet@f0b60000 {
+	phy-mode = "internal";
+	phy-handle = <&phy1>;
+	mac-address = [ 00 10 18 36 23 1a ];
+	compatible = "brcm,genet-v4";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	device_type = "ethernet";
+	reg = <0xf0b60000 0xfc4c>;
+	interrupts = <0x0 0x14 0x0 0x0 0x15 0x0>;
+
+	mdio@b60e14 {
+		compatible = "brcm,genet-mdio-v4";
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		reg = <0xb60e14 0x8>;
+
+		phy1: ethernet-phy@1 {
+			device_type = "ethernet-phy";
+			max-speed = <1000>;
+			reg = <0x1>;
+			compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22";
+		};
+	};
+};
+
+MoCA interface / MAC to MAC example:
+
+ethernet@f0b80000 {
+	phy-mode = "moca";
+	fixed-link = <1 0 1000 0 0>;
+	mac-address = [ 00 10 18 36 24 1a ];
+	compatible = "brcm,genet-v4";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	device_type = "ethernet";
+	reg = <0xf0b80000 0xfc4c>;
+	interrupts = <0x0 0x16 0x0 0x0 0x17 0x0>;
+
+	mdio@b80e14 {
+		compatible = "brcm,genet-mdio-v4";
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		reg = <0xb80e14 0x8>;
+	};
+};
+
+
+External MDIO-connected Gigabit PHY/switch:
+
+ethernet@f0ba0000 {
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+	mac-address = [ 00 10 18 36 26 1a ];
+	compatible = "brcm,genet-v4";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	device_type = "ethernet";
+	reg = <0xf0ba0000 0xfc4c>;
+	interrupts = <0x0 0x18 0x0 0x0 0x19 0x0>;
+
+	mdio@ba0e14 {
+		compatible = "brcm,genet-mdio-v4";
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		reg = <0xba0e14 0x8>;
+
+		phy0: ethernet-phy@0 {
+			device_type = "ethernet-phy";
+			max-speed = <1000>;
+			reg = <0x0>;
+			compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22";
+		};
+	};
+};
diff --git a/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt
new file mode 100644
index 000000000000..ac5767552960
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt
@@ -0,0 +1,33 @@
+* Broadcom UniMAC MDIO bus controller
+
+Required properties:
+- compatible: should be "brcm,unimac-mdio"
+- reg: address and length of the regsiter set for the device, first one is the
+  base register, and the second one is optional and for indirect accesses
+- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
+- #size-cells: must be 1
+- #address-cells: must be 0
+
+Optional properties:
+- interrupts: must be two interrupts, one for MDIO done, one for MDIO error
+- interrupt-names: must be "mdio_done" for the first interrupt and "mdio_error"
+  for the second
+
+Child nodes of this MDIO bus controller node are standard Ethernet PHY device
+nodes as described in Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+
+mdio@403c0 {
+	compatible = "brcm,unimac-mdio";
+	reg = <0x403c0 0x8 0x40300 0x18>;
+	reg-names = "mdio", "mdio_indir_rw";
+	#size-cells = <1>;
+	#address-cells = <0>;
+
+	...
+	phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
diff --git a/Documentation/devicetree/bindings/net/broadcom-systemport.txt b/Documentation/devicetree/bindings/net/broadcom-systemport.txt
new file mode 100644
index 000000000000..5a0678d85f64
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-systemport.txt
@@ -0,0 +1,32 @@
+* Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT)
+
+Required properties:
+- compatible: should be one of "brcm,systemport-v1.00" or "brcm,systemport"
+- reg: address and length of the register set for the device.
+- interrupts: interrupt(s) for the device, 1 interrupt is the RX and misc
+  interrupts, the second is the TX queues interrupts. A 3rd optional interupt
+  is used for Wake-on-LAN
+- local-mac-address: Ethernet MAC address (48 bits) of this adapter
+- phy-mode: Should be a string describing the PHY interface to the
+  Ethernet switch/PHY
+- fixed-link: <a b c d e> where a is emulated phy id - choose any,
+  but unique to the all specified fixed-links, b is duplex - 0 half,
+  1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
+  pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
+
+Optional properties:
+- systemport,num-tier2-arb: number of tier 2 arbiters, an integer
+- systemport,num-tier1-arb: number of tier 1 arbiters, an integer
+- systemport,num-txq: number of HW transmit queues, an integer
+- systemport,num-rxq: number of HW receive queues, an integer
+
+Example:
+ethernet@f04a0000 {
+	compatible = "brcm,systemport-v1.00";
+	reg = <0xf04a0000 0x4650>;
+	local-mac-address = [ 00 11 22 33 44 55 ];
+	fixed-link = <0 1 1000 0 0>;
+	phy-mode = "gmii";
+	interrupts = <0x0 0x16 0x0>,
+		<0x0 0x17 0x0>;
+};
diff --git a/Documentation/devicetree/bindings/net/fixed-link.txt b/Documentation/devicetree/bindings/net/fixed-link.txt
new file mode 100644
index 000000000000..e956de1be935
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/fixed-link.txt
@@ -0,0 +1,30 @@
+Fixed link Device Tree binding
+------------------------------
+
+Some Ethernet MACs have a "fixed link", and are not connected to a
+normal MDIO-managed PHY device. For those situations, a Device Tree
+binding allows to describe a "fixed link".
+
+Such a fixed link situation is described by creating a 'fixed-link'
+sub-node of the Ethernet MAC device node, with the following
+properties:
+
+* 'speed' (integer, mandatory), to indicate the link speed. Accepted
+  values are 10, 100 and 1000
+* 'full-duplex' (boolean, optional), to indicate that full duplex is
+  used. When absent, half duplex is assumed.
+* 'pause' (boolean, optional), to indicate that pause should be
+  enabled.
+* 'asym-pause' (boolean, optional), to indicate that asym_pause should
+  be enabled.
+
+Example:
+
+ethernet@0 {
+	...
+	fixed-link {
+	      speed = <1000>;
+	      full-duplex;
+	};
+	...
+};
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index 58307d0931c8..4e00b3bf04de 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -21,6 +21,9 @@ Optional Properties:
   elements.
 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
 
+- broken-turn-around: If set, indicates the PHY device does not correctly
+  release the turn around line low at the end of a MDIO transaction.
+
 Example:
 
 ethernet-phy@0 {
diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pci.txt b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
new file mode 100644
index 000000000000..ceaf949bffe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
@@ -0,0 +1,80 @@
+Brcmstb PCIe Host Controller Device Tree Bindings
+
+Introduction:
+
+The brcmstb host controller closely follows the example set in
+
+	[1] http://devicetree.org/Device_Tree_Usage#PCI_Host_Bridge
+
+The rest of this document explains some added customizations and
+offers an example Brcmstb PCIe host controller DT node.
+
+Required Properties:
+  reg -- the register start address and length for the PCIe block.
+      Additional start,length pairs may be specified for clock addresses.
+  interrupts -- this must be specified but it is used indirectly.  Interrupt
+      zero must be specified; the Brcmstb driver code uses this interrupt
+      to determine the offset used for all interrupts, specifically, those
+      listed in interrupt-map.
+  compatible -- must specify the string "brcm,pci-plat-dev".
+  #address-cells -- the number of address cells for PCI-space.
+  #size-cells -- the number of size cells for PCI-space.
+  ranges -- See [1]; a specification of the outbound windows for the host
+      controller.  Each outbound window is described by a 7-tuple:
+          (3 entries) -- PCIe space start address (0th entry is ignored).
+          (2 entries) -- CPU/System start address
+          (2 entries) -- Size of region.
+      Due to hardware limitations, there may be a maximum of four windows
+      specified.
+  #interrupt-cells -- number of cells used to describe the interrupt.
+  interrupt-map -- See [1]; each interrupt requires 7 entries, and
+      currently all but the fifth entry (order 0) -- the interrupt
+      number -- is ignored.  There must be four interrupts specified
+      for the PCI's INTA, INTB, INTC, and INTD.
+
+Optional Properties:
+  interrupt-names -- names of the interrupts listed in the interrupt map.
+  clocks -- list of clock phandles.  If specified, this should list one
+      clock.
+  clock-names -- the "local" names of the clocks specified in 'clocks'.  Note
+      that if the 'clocks' property is given, 'clock-names' is mandatory,
+      and the name of the clock is expected to be "sw_pcie".
+  brcm,ssc -- (boolean) indicates usage of spread-spectrum clocking.
+  brcm,gen --  (integer) indicates desired generation of link:
+      1 => 2.5 Gbps, 2 => 5.0 Gbps, 3 => 8.0 Gbps.
+  supply-names -- the names of voltage regulators that the root
+      complex should turn off/on/on on suspend/resume/boot.  This
+      is a string list.  
+  supplies -- A collection of phandles to a regulator nodes, see
+	Documentation/devicetree/bindings/regulator/ for specific
+	bindings. The number and order of phandles must match
+	exactly the number of strings in the "supply-names" property.
+
+Example Node:
+
+	pcie@f0460000 {
+		reg = <0x0 0xf0460000 0x0 0x9310>;
+		interrupts = <0x0 0x0 0x4>;
+		compatible = "brcm,pci-plat-dev";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
+			  0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0 0 0 1 &intc 47 3
+				 0 0 0 2 &intc 48 3
+				 0 0 0 3 &intc 49 3
+				 0 0 0 4 &intc 50 3>;
+		interrupt-names = "pcie_0_inta",
+				  "pcie_0_intb",
+				  "pcie_0_intc",
+				  "pcie_0_intd";
+		clocks = <&sw_pcie0>;
+		clock-names = "sw_pcie";
+		brcm,ssc;
+		brcm,gen = <1>;
+		supply-names = "vreg-wifi-pwr";
+		supplies = <&vreg-wifi-pwr>;
+
+	};
diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
new file mode 100644
index 000000000000..d9254a6da5ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
@@ -0,0 +1,20 @@
+Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
+
+Required properties:
+
+- compatible: must be "brcm,bcm7038-pwm"
+- reg: physical base address and length for this controller
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description
+  of the cells format
+- clocks: a phandle to the reference clock for this block which is fed through
+  its internal variable clock frequency generator
+
+
+Example:
+
+	pwm: pwm@f0408000 {
+		compatible = "brcm,bcm7038-pwm";
+		reg = <0xf0408000 0x28>;
+		#pwm-cells = <2>;
+		clocks = <&upg_fixed>;
+	};
diff --git a/Documentation/devicetree/bindings/serial/brcm-broken-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/brcm-broken-dw-apb-uart.txt
new file mode 100644
index 000000000000..75096c0b2ac9
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/brcm-broken-dw-apb-uart.txt
@@ -0,0 +1,26 @@
+* Broadcom buggy variant on Synopsys DW APB UART
+
+This UART variant is for a Synopsys DW APB UART that cannot reset the
+"busy detect" interrupt (IIR == 7).
+
+Required properties:
+- compatible: should be "brcm,buggy-dw-apb-uart"
+- reg: The base address of the UART register bank
+- interrupts: Should be the UART interrupt specifier.
+
+Optional properties:
+- clock-frequency: frequency of the clock input to the UART
+- reg-io-width: UART register width
+- reg-shift: amount by which to shift offsets
+
+
+Example:
+
+serial@f0406b00 {
+	compatible = "brcm,buggy-dw-apb-uart";
+	reg = <0xf0406b00 0x20>;
+	reg-shift = <0x2>;
+	reg-io-width = <0x4>;
+	interrupts = <0x0 0x4b 0x4>;
+	clock-frequency = <0x4d3f640>;
+};
diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-brcmstb-mspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-brcmstb-mspi.txt
new file mode 100644
index 000000000000..37658ed1e8e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/brcm,spi-brcmstb-mspi.txt
@@ -0,0 +1,88 @@
+Broadcom MSPI controller
+
+The Broadcom MSPI controller is a SPI master found on various chips, including
+BRCMSTB (BCM7XXX) and Cygnus.
+
+Required properties:
+
+- #address-cells:
+    Must be <1>, as required by generic SPI binding.
+
+- #size-cells:
+    Must be <0>, also as required by generic SPI binding.
+
+- compatible:
+    Must be "brcm,spi-brcmstb-mspi" or "brcm,spi-brcmstb".
+
+- reg:
+    Define the bases and ranges of the associated I/O address spaces.
+    For historical reasons, the first range should contain the MSPI controller
+    registers, while the others may be for extended interrupt control or an
+    optional Boot SPI (BSPI) portion for accelerating flash reads.  Only
+    the MSPI controller register range is required.
+
+- reg-names:
+    First name does not matter, but must be reserved for the MSPI controller
+    register range as mentioned in 'reg' above, and will typically contain
+    "mspi" or "hif_mspi".
+    Other names include:
+    - "bspi": BSPI register range
+    - "bspi_raf": Linear read BSPI pipe register range
+
+- interrupts + interrupt-parent OR interrupts-extended:
+    The interrupts used by the MSPI controller.
+
+- interrupt-names:
+    Names of interrupts associated with this MSPI controller.
+    - "mspi_done": Indicates that the requested SPI operation is complete.
+
+Optional properties:
+
+- clocks:
+    A phandle to the reference clock for this block.  If not present, will
+    assume a 27 MHz fixed clock (default for UPG).
+
+Examples:
+
+spi@f0416000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clocks = <&upg_fixed>;
+	compatible = "brcm,spi-brcmstb-mspi";
+	reg = <0xf0416000 0x180>;
+	reg-names = "mspi";
+	interrupts = <0x14>;
+	interrupt-parent = <&irq0_aon_intc>;
+	interrupt-names = "mspi_done";
+};
+
+spi@f03e3400 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "brcm,spi-brcmstb";
+	status = "disabled";
+	reg = <0xf03e3400 0x188>,
+		<0xf03e3200 0x50>,
+		<0xf03e3300 0x24>;
+	reg-names = "hif_mspi",
+		"bspi",
+		"bspi_raf";
+	interrupts = <0x0 0x21 0x0>;
+	interrupt-parent = <&intc>;
+	interrupts-extended = <&intc 0x0 0x21 0x0>,
+		<&hif_spi_intr2_intc 0x0>,
+		<&hif_spi_intr2_intc 0x1>,
+		<&hif_spi_intr2_intc 0x2>,
+		<&hif_spi_intr2_intc 0x3>,
+		<&hif_spi_intr2_intc 0x5>,
+		<&hif_spi_intr2_intc 0x6>;
+	interrupt-names = "hif_spi",
+		"spi_lr_fullness_reached",
+		"spi_lr_session_aborted",
+		"spi_lr_impatient",
+		"spi_lr_session_done",
+		"mspi_done",
+		"mspi_halted";
+	clocks = <&sw_spi>;
+	clock-names = "sw_spi";
+};
diff --git a/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt b/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt
new file mode 100644
index 000000000000..880e62366fce
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/brcmstb-thermal.txt
@@ -0,0 +1,20 @@
+* Broadcom STB (BCM7xxx) thermal management
+
+Thermal management core, provided by the AVS TMON hardware block.
+
+Required properties:
+
+- compatible: "brcm,avs-tmon-bcm7445" and/or "brcm,avs-tmon"
+- reg: address range for the AVS TMON registers
+- interrupts: 'TMON' interrupt, for high/low threshold triggers
+- interrupt-names: "tmon"
+
+Example:
+
+	thermal@f04d1500 {
+		compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
+		interrupt-names = "tmon";
+		interrupt-parent = <&avs_host_l2_intc>;
+		reg = <0xf04d1500 0x28>;
+		interrupts = <0x6>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/bdc-udc.txt b/Documentation/devicetree/bindings/usb/bdc-udc.txt
new file mode 100644
index 000000000000..14369b89667e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/bdc-udc.txt
@@ -0,0 +1,16 @@
+USB Device Controller (UDC) for Broadcom Device Controller (BDC)
+
+Required properties:
+
+- compatible: Must be "brcm,bdc-udc-v0.16" or "brcm,bdc-udc"
+
+- reg: Address and length of the register set for the device
+
+- interrupts: Interrupt number for this device
+
+Example:
+	bdc@f0472000 {                                          
+		compatible = "brcm,bdc-udc-v0.16", "brcm,bdc-udc";
+		reg = <0xf0472000 0xfc4>;
+		interrupts = <0x0 0x76 0x0>;
+	};
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt
new file mode 100644
index 000000000000..adb8260803e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt
@@ -0,0 +1,19 @@
+BCM7038 Watchdog timer
+
+Required properties:
+
+- compatible : should be "brcm,bcm7038-wdt"
+- reg : Specifies base physical address and size of the registers.
+
+Optional properties:
+
+- clocks: the clock running the watchdog
+- clock-frequency: the rate of the clock
+
+Example:
+
+watchdog {
+	compatible = "brcm,bcm7038-wdt";
+	clocks = <&upg_fixed>;
+	reg = <0xf040a7e8 0x16>;
+};
diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt
index e42f77d8d4ca..09854fe59307 100644
--- a/Documentation/gpio/consumer.txt
+++ b/Documentation/gpio/consumer.txt
@@ -154,6 +154,7 @@ raw line value:
 	void gpiod_set_raw_value(struct gpio_desc *desc, int value)
 	int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
 	void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
+	int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
 
 The active-low state of a GPIO can also be queried using the following call:
 
diff --git a/Documentation/hwmon/adc128d818 b/Documentation/hwmon/adc128d818
new file mode 100644
index 000000000000..39c95004dabc
--- /dev/null
+++ b/Documentation/hwmon/adc128d818
@@ -0,0 +1,47 @@
+Kernel driver adc128d818
+========================
+
+Supported chips:
+  * Texas Instruments ADC818D818
+    Prefix: 'adc818d818'
+    Addresses scanned: I2C 0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f
+    Datasheet: Publicly available at the TI website
+               http://www.ti.com/
+
+Author: Guenter Roeck
+
+Description
+-----------
+
+This driver implements support for the Texas Instruments ADC128D818.
+It is described as 'ADC System Monitor with Temperature Sensor'.
+
+The ADC128D818 implements one temperature sensor and seven voltage sensors.
+
+Temperatures are measured in degrees Celsius. There is one set of limits.
+When the HOT Temperature Limit is crossed, this will cause an alarm that will
+be reasserted until the temperature drops below the HOT Hysteresis.
+Measurements are guaranteed between -55 and +125 degrees. The temperature
+measurement has a resolution of 0.5 degrees; the limits have a resolution
+of 1 degree.
+
+Voltage sensors (also known as IN sensors) report their values in volts.
+An alarm is triggered if the voltage has crossed a programmable minimum
+or maximum limit. Note that minimum in this case always means 'closest to
+zero'; this is important for negative voltage measurements. All voltage
+inputs can measure voltages between 0 and 2.55 volts, with a resolution
+of 0.625 mV.
+
+If an alarm triggers, it will remain triggered until the hardware register
+is read at least once. This means that the cause for the alarm may
+already have disappeared by the time the alarm is read. The driver
+caches the alarm status for each sensor until it is at least reported
+once, to ensure that alarms are reported to user space.
+
+The ADC128D818 only updates its values approximately once per second;
+reading it more often will do no harm, but will return 'old' values.
+
+In addition to the scanned address list, the chip can also be configured for
+addresses 0x35 to 0x37. Those addresses are not scanned. You have to instantiate
+the driver explicitly if the chip is configured for any of those addresses in
+your system.
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 5d91ba1606bb..38aaefc209ab 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -44,6 +44,7 @@ parameter is applicable:
 	AVR32	AVR32 architecture is enabled.
 	AX25	Appropriate AX.25 support is enabled.
 	BLACKFIN Blackfin architecture is enabled.
+	BRCMSTB	Broadcom STB platform support is enabled.
 	CLK	Common clock infrastructure is enabled.
 	CMA	Contiguous Memory Area support is enabled.
 	DRM	Direct Rendering Management support is enabled.
@@ -503,6 +504,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			embedded devices based on command line input.
 			See Documentation/block/cmdline-partition.txt
 
+	bmem=size[KMG][@offset[KMG]] 	[KNL,BRCM]
+			Set aside a contiguous reserved memory region at the
+			specified location.  Can be provided multiple times,
+			once for each reservation.  Note: there is a default
+			reservation, and manually specifying any region will
+			disable the defaults.  Specifying bmem=0 will disable
+			bmem entirely.
+
 	boot_delay=	Milliseconds to delay each printk during boot.
 			Values larger than 10 seconds (10000) are changed to
 			no delay (0).
@@ -510,6 +519,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 
 	bootmem_debug	[KNL] Enable bootmem allocator debug messages.
 
+	brcm_cma=size[KMG][@offset[KMG]] 	[KNL,BRCM]
+			Set aside a contiguous memory region to be used as a
+			CMA area at the specified location.  Can be provided
+			multiple times, once for each reservation.
+
 	bttv.card=	[HW,V4L] bttv (bt848 + bt878 based grabber cards)
 	bttv.radio=	Most important insmod options are available as
 			kernel args too.
@@ -603,9 +617,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			Also note the kernel might malfunction if you disable
 			some critical bits.
 
-	cma=nn[MG]	[ARM,KNL]
-			Sets the size of kernel global memory area for contiguous
-			memory allocations. For more information, see
+	cma=nn[MG]@[start[MG][-end[MG]]]
+			[ARM,X86,KNL]
+			Sets the size of kernel global memory area for
+			contiguous memory allocations and optionally the
+			placement constraint by the physical address range of
+			memory allocations. A value of 0 disables CMA
+			altogether. For more information, see
 			include/linux/dma-contiguous.h
 
 	cmo_free_hint=	[PPC] Format: { yes | no }
@@ -3120,6 +3138,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			improve throughput, but will also increase the
 			amount of memory reserved for use by the client.
 
+	suspend.pm_test_delay=
+			[SUSPEND]
+			Sets the number of seconds to remain in a suspend test
+			mode before resuming the system (see
+			/sys/power/pm_test). Only available when CONFIG_PM_DEBUG
+			is set. Default value is 5.
+
 	swapaccount=[0|1]
 			[KNL] Enable accounting of swap in memory resource
 			controller if no parameter or 1 is given or disable
diff --git a/Documentation/power/basic-pm-debugging.txt b/Documentation/power/basic-pm-debugging.txt
index edeecd447d23..b96098ccfe69 100644
--- a/Documentation/power/basic-pm-debugging.txt
+++ b/Documentation/power/basic-pm-debugging.txt
@@ -75,12 +75,14 @@ you should do the following:
 # echo platform > /sys/power/disk
 # echo disk > /sys/power/state
 
-Then, the kernel will try to freeze processes, suspend devices, wait 5 seconds,
-resume devices and thaw processes.  If "platform" is written to
+Then, the kernel will try to freeze processes, suspend devices, wait a few
+seconds (5 by default, but configurable by the suspend.pm_test_delay module
+parameter), resume devices and thaw processes.  If "platform" is written to
 /sys/power/pm_test , then after suspending devices the kernel will additionally
 invoke the global control methods (eg. ACPI global control methods) used to
-prepare the platform firmware for hibernation.  Next, it will wait 5 seconds and
-invoke the platform (eg. ACPI) global methods used to cancel hibernation etc.
+prepare the platform firmware for hibernation.  Next, it will wait a
+configurable number of seconds and invoke the platform (eg. ACPI) global
+methods used to cancel hibernation etc.
 
 Writing "none" to /sys/power/pm_test causes the kernel to switch to the normal
 hibernation/suspend operations.  Also, when open for reading, /sys/power/pm_test
diff --git a/Makefile b/Makefile
index 0ed6ce300543..12e116af904b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 14
 SUBLEVEL = 79
-EXTRAVERSION =
+EXTRAVERSION = -1.17
 NAME = Remembering Coco
 
 # *DOCUMENTATION*
@@ -195,7 +195,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/x86/ -e s/x86_64/x86/ \
 # "make" in the configured kernel build directory always uses that.
 # Default value for CROSS_COMPILE is not to prefix executables
 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
-ARCH		?= $(SUBARCH)
+#ARCH		?= $(SUBARCH)
+ARCH		?= arm
 CROSS_COMPILE	?= $(CONFIG_CROSS_COMPILE:"%"=%)
 
 # Architecture as present in compile.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4733d327cfb1..433bccf40c1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -915,6 +915,8 @@ config ARCH_MULTI_V7
 	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 	default y
 	select ARCH_MULTI_V6_V7
+	select ARCH_FLATMEM_ENABLE
+	select ARCH_SPARSEMEM_ENABLE
 	select CPU_V7
 
 config ARCH_MULTI_V6_V7
@@ -1630,7 +1632,7 @@ config ARM_PSCI
 # selected platforms.
 config ARCH_NR_GPIO
 	int
-	default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
+	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA
 	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
 	default 392 if ARCH_U8500
 	default 352 if ARCH_VT8500
@@ -1776,11 +1778,11 @@ config OABI_COMPAT
 config ARCH_HAS_HOLES_MEMORYMODEL
 	bool
 
-config ARCH_SPARSEMEM_ENABLE
+config ARCH_FLATMEM_ENABLE
 	bool
 
-config ARCH_SPARSEMEM_DEFAULT
-	def_bool ARCH_SPARSEMEM_ENABLE
+config ARCH_SPARSEMEM_ENABLE
+	bool
 
 config ARCH_SELECT_MEMORY_MODEL
 	def_bool ARCH_SPARSEMEM_ENABLE
@@ -1922,6 +1924,7 @@ config USE_OF
 	select IRQ_DOMAIN
 	select OF
 	select OF_EARLY_FLATTREE
+	select OF_RESERVED_MEM
 	help
 	  Include support for flattened device tree machine descriptions.
 
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 0531da8e5216..fb939956e744 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -125,6 +125,17 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on Marvell Berlin SoC based platforms.
 
+	config DEBUG_BRCMSTB_UART
+		bool "Use BRCMSTB UART for low-level debug"
+		depends on ARCH_BRCMSTB
+		select DEBUG_UART_8250
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the first serial port on these devices.
+
+		  If you have a Broadcom STB chip and would like early print
+		  messages to appear over the UART, select this option.
+
 	config DEBUG_CLPS711X_UART1
 		bool "Kernel low-level debugging messages via UART1"
 		depends on ARCH_CLPS711X
@@ -1005,7 +1016,7 @@ config DEBUG_UART_8250
 		ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
 
 config DEBUG_UART_PHYS
-	hex "Physical base address of debug UART"
+	hex
 	default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
 	default 0x01c28000 if DEBUG_SUNXI_UART0
 	default 0x01c28400 if DEBUG_SUNXI_UART1
@@ -1049,6 +1060,15 @@ config DEBUG_UART_PHYS
 	default 0xd4018000 if DEBUG_MMP_UART3
 	default 0xe0000000 if ARCH_SPEAR13XX
 	default 0xf0000be0 if ARCH_EBSA110
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM3390A0
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM3390B0
+	default 0xf040b400 if DEBUG_BRCMSTB_UART && BCM7250B0
+	default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7364A0
+	default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7366C0
+	default 0xf0406b00 if DEBUG_BRCMSTB_UART && BCM74371A0
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM7439B0
+	default 0xf040ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
+	default 0xf0406b00 if DEBUG_BRCMSTB_UART
 	default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
 	default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
 				ARCH_ORION5X
@@ -1065,7 +1085,7 @@ config DEBUG_UART_PHYS
 		DEBUG_UART_8250 || DEBUG_UART_PL01X
 
 config DEBUG_UART_VIRT
-	hex "Virtual base address of debug UART"
+	hex
 	default 0xe0010fe0 if ARCH_RPC
 	default 0xf0000be0 if ARCH_EBSA110
 	default 0xf0009000 if DEBUG_CNS3XXX
@@ -1083,6 +1103,15 @@ config DEBUG_UART_VIRT
 	default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
 	default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
 	default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM3390A0
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM3390B0
+	default 0xfc40b400 if DEBUG_BRCMSTB_UART && BCM7250B0
+	default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7364A0
+	default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7366C0
+	default 0xfc406b00 if DEBUG_BRCMSTB_UART && BCM74371A0
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM7439B0
+	default 0xfc40ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
+	default 0xfc406b00 if DEBUG_BRCMSTB_UART
 	default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
 	default 0xfd000000 if ARCH_SPEAR13XX
 	default 0xfd012000 if ARCH_MV78XX0
@@ -1136,7 +1165,7 @@ config DEBUG_UART_8250_WORD
 		ARCH_KEYSTONE || \
 		DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
 		DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
-		DEBUG_BCM_KONA_UART
+		DEBUG_BCM_KONA_UART || DEBUG_BRCMSTB_UART
 
 config DEBUG_UART_8250_FLOW_CONTROL
 	bool "Enable flow control for 8250 UART"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 032030361bef..26bef47b4068 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 	dove-d2plug.dtb \
 	dove-d3plug.dtb \
 	dove-dove-db.dtb
+dtb-$(CONFIG_DREAMBOX_DM9X0) += dreambox-dm900.dtb
 dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos4210-smdkv310.dtb \
diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
new file mode 100644
index 000000000000..9eec2ac1112f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+#include "bcm7445.dtsi"
+
+/ {
+	model = "Broadcom STB (bcm7445), SVMB reference board";
+	compatible = "brcm,bcm7445", "brcm,brcmstb";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00 0x00000000 0x00 0x40000000>,
+		      <0x00 0x40000000 0x00 0x40000000>,
+		      <0x00 0x80000000 0x00 0x40000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
new file mode 100644
index 000000000000..f5e1525baf2d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -0,0 +1,193 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Broadcom STB (bcm7445)";
+	compatible = "brcm,bcm7445", "brcm,brcmstb";
+	interrupt-parent = <&gic>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "brcm,brahma-b15";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,brahma-b15";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			compatible = "brcm,brahma-b15";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			compatible = "brcm,brahma-b15";
+			device_type = "cpu";
+			reg = <3>;
+		};
+	};
+
+	gic: interrupt-controller@ffd00000 {
+		compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
+		reg = <0x00 0xffd01000 0x00 0x1000>,
+		      <0x00 0xffd02000 0x00 0x2000>,
+		      <0x00 0xffd04000 0x00 0x2000>,
+		      <0x00 0xffd06000 0x00 0x2000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	rdb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0 0x00 0xf0000000 0x1000000>;
+
+		serial@406b00 {
+			compatible = "ns16550a";
+			reg = <0x406b00 0x20>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0x4d3f640>;
+		};
+
+		sun_top_ctrl: syscon@404000 {
+			compatible = "brcm,bcm7445-sun-top-ctrl",
+				     "syscon";
+			reg = <0x404000 0x51c>;
+		};
+
+		hif_cpubiuctrl: syscon@3e2400 {
+			compatible = "brcm,bcm7445-hif-cpubiuctrl",
+				     "syscon";
+			reg = <0x3e2400 0x5b4>;
+		};
+
+		hif_continuation: syscon@452000 {
+			compatible = "brcm,bcm7445-hif-continuation",
+				     "syscon";
+			reg = <0x452000 0x100>;
+		};
+
+		sata@45a000 {
+			compatible = "brcm,sata3-ahci";
+			reg = <0x45a000 0xa9c>;
+			phy-enable-ssc-mask = <0x0>;
+			phy-generation = <0x2800>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			phy-base-addr = <0xf0458100>;
+			top-ctrl-base-addr = <0xf0458040>;
+		};
+
+		usb@470200 {
+			reg = <0x470200 0x80>;
+			compatible = "brcm,usb-instance";
+			ioc = <0x1>;
+			#size-cells = <0x1>;
+			#address-cells = <0x1>;
+			ipp = <0x1>;
+			ranges;
+
+			ohci@470400 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0x470400 0x58>;
+				interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			ohci@470600 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0x470600 0x58>;
+				interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		usb@480200 {
+			reg = <0x480200 0x80>;
+			compatible = "brcm,usb-instance";
+			ioc = <0x1>;
+			#size-cells = <0x1>;
+			#address-cells = <0x1>;
+			ipp = <0x1>;
+			ranges;
+
+			ohci@480400 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0x480400 0x58>;
+				interrupts = <GIC_SPI 0x57 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			ohci@480600 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0x480600 0x58>;
+				interrupts = <GIC_SPI 0x58 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+
+	/*
+	 * PCIe has funky address translation that touches beyond the
+	 * RDB range, so we place the node out here.
+	 */
+	pci {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0 0x00 0x00000000 0xffffffff>;
+
+		pcie@f0460000 {
+			#address-cells = <0x3>;
+			#size-cells = <0x2>;
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,pci-plat-dev";
+			reg = <0xf0460000 0x9310>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			device_type = "pci";
+			bus-ranges = <0x0 0xff>;
+			tot-num-pcie = <0x1>;
+			ranges = <0x2000000 0x0 0x00000000 0xc0000000 0x0 0x8000000>,
+				 <0x2000000 0x0 0x08000000 0xc8000000 0x0 0x8000000>,
+				 <0x2000000 0x0 0x10000000 0xd0000000 0x0 0x8000000>,
+				 <0x2000000 0x0 0x18000000 0xd8000000 0x0 0x8000000>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x2f 0x3>,
+					<0x0 0x0 0x0 0x2 0x1 0x30 0x3>,
+					<0x0 0x0 0x0 0x3 0x1 0x31 0x3>,
+					<0x0 0x0 0x0 0x4 0x1 0x32 0x3>;
+		};
+	};
+
+	smpboot {
+		compatible = "brcm,brcmstb-smpboot";
+		syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
+		syscon-cont = <&hif_continuation>;
+	};
+
+	reboot {
+		compatible = "brcm,brcmstb-reboot";
+		syscon = <&sun_top_ctrl 0x304 0x308>;
+	};
+};
diff --git a/arch/arm/boot/dts/dreambox-dm900.dts b/arch/arm/boot/dts/dreambox-dm900.dts
new file mode 100644
index 000000000000..6fb060a307cc
--- /dev/null
+++ b/arch/arm/boot/dts/dreambox-dm900.dts
@@ -0,0 +1,2477 @@
+/dts-v1/;
+
+/ {
+	model = "BCM97252SSFF";
+	compatible = "BCM97252SSFF", "brcm,bcm7439b0", "brcm,brcmstb";
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	interrupt-parent = <0x1>;
+
+	chosen {
+		stdout-path = "/rdb/serial@f040a900:1000000";
+	};
+
+	reserved-memory {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		reserved-nodma@00000000 {
+			reg = <0x0 0x0 0x0 0x1000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			operating-points = <0x1a3ad8 0x0>;
+			clock-frequency = <0x6675dbc0>;
+			device_type = "cpu";
+			enable-method = "brcm,brahma-b15";
+			compatible = "brcm,brahma-b15", "arm,cortex-a15";
+			reg = <0x0>;
+			clock-latency = <0x12c0>;
+			clocks = <0x2>;
+		};
+
+		cpu@1 {
+			clock-frequency = <0x6675dbc0>;
+			device_type = "cpu";
+			enable-method = "brcm,brahma-b15";
+			compatible = "brcm,brahma-b15", "arm,cortex-a15";
+			reg = <0x1>;
+		};
+	};
+
+	timer {
+		compatible = "arm,cortex-a15-timer", "arm,armv7-timer";
+		interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>;
+		always-on;
+	};
+
+	memory {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000 0x0 0x80000000 0x0 0x40000000>;
+	};
+
+	bolt {
+		version = <0x10012>;
+		date = "2016-10-31 21:04:46";
+		user = "cynric@cynric-VirtualBox";
+		tag = "v1.18";
+		board = "BCM97252SSFF";
+		family-id = <0x74390011>;
+		product-id = <0x7252110>;
+		board-id = <0x20>;
+		box = "5";
+		rts = "00000000000000_0000_box5";
+		bootdev = "spi";
+		dt-compat = <0x1>;
+		reset-list = "power_on";
+		reset-history = <0x1>;
+		timer-wdog = <0xf040a780>;
+	};
+
+	interrupt-controller@ffd00000 {
+		compatible = "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <0x3>;
+		reg = <0x0 0xffd01000 0x0 0x1000 0x0 0xffd02000 0x0 0x2000>;
+		reg-names = "dist", "cpu";
+		linux,phandle = <0x1>;
+		phandle = <0x1>;
+	};
+
+	reboot {
+		compatible = "brcm,brcmstb-reboot";
+		syscon = <0x3 0x304 0x308>;
+	};
+
+	smpboot {
+		compatible = "brcm,brcmstb-smpboot";
+		syscon-cpu = <0x4 0x88 0x178>;
+		syscon-cont = <0x5>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+		interrupts = <0x0 0x4 0xf04 0x0 0x5 0xf04 0x0 0x6 0xf04 0x0 0x7 0xf04>;
+		interrupt-names = "cpu_pmuirq_0", "cpu_pmuirq_1", "cpu_pmuirq_2", "cpu_pmuirq_3";
+	};
+
+	nexus-wakeups {
+		interrupts = <0x0 0x1 0x2 0x5 0x8>;
+		interrupt-parent = <0x6>;
+		interrupt-names = "cec", "irr", "kpd", "gpio", "xpt_pmu";
+	};
+
+	nexus-irq0 {
+		interrupts = <0x9 0x6 0x7 0x8 0xa 0x3 0x0 0x1 0x2 0x4 0x5>;
+		interrupt-parent = <0x7>;
+		interrupt-names = "gio", "iica", "iicd", "iice", "irb", "ua", "uarta", "uartb", "uartc", "ub", "uc";
+	};
+
+	nexus-irq0_aon {
+		interrupts = <0x5 0x8 0x3 0x4 0x0 0x1 0x2 0x6 0x7>;
+		interrupt-parent = <0x8>;
+		interrupt-names = "gio", "icap", "iicb", "iicc", "kbd1", "kbd2", "kbd3", "ldk", "spi";
+	};
+
+	aliases {
+		pcie0 = "/pcie@f0460000";
+		pcie1 = "/pcie@f0490000";
+		serial0 = "/rdb/serial@f040a900";
+		serial1 = "/rdb/serial@f040a940";
+		serial2 = "/rdb/serial@f040a980";
+		usbphy0 = "/rdb/usb-phy@f0470200";
+		ehci0_0 = "/rdb/ehci_v2@f0470300";
+		ehci0_1 = "/rdb/ehci_v2@f0470500";
+		ohci0_0 = "/rdb/ohci_v2@f0470400";
+		ohci0_1 = "/rdb/ohci_v2@f0470600";
+		xhci0_0 = "/rdb/xhci_v2@f0471000";
+		bdc0_0 = "/rdb/bdc_v2@f0472000";
+		usb0 = "/rdb/usb@f0470200";
+		eth0 = "/rdb/ethernet@f0b00000";
+		eth1 = "/rdb/ethernet@f0b20000";
+		eth2 = "/rdb/ethernet@f0b40000";
+		upg_gio = "/rdb/gpio@f040a600";
+		upg_gio_aon = "/rdb/gpio@f0417400";
+		sata_phy0 = "/rdb/sata_phy@f0458100";
+		sata0 = "/rdb/sata@f045a000";
+		sdhci0 = "/rdb/sdhci@f03e0100";
+		sdhci1 = "/rdb/sdhci@f03e0300";
+		cpuclkdiv0 = "/rdb/cpu-clk-div@0";
+		sw_gphy = "/rdb/brcmstb-clks/lc_pdh_ch0@f04e0080";
+		watchdog0 = "/rdb/watchdog@f040a7a8";
+		bsp = "/rdb/bsp@f032c800";
+	};
+
+	rdb {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "simple-bus";
+		ranges = <0x0 0x0 0x0 0xffffffff>;
+
+		serial@f040a900 {
+			clock-frequency = <0x4d3f640>;
+			compatible = "ns16550a";
+			reg-io-width = <0x4>;
+			reg-shift = <0x2>;
+			reg = <0xf040a900 0x20>;
+			reg-names = "uart";
+			interrupts = <0x0 0x4b 0x4>;
+			interrupt-names = "uart";
+			current-speed = <0xf4240>;
+		};
+
+		usb-phy@f0470200 {
+			device = "off";
+			reg = <0xf0470200 0x100>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,usb-phy";
+			ioc = <0x1>;
+			ipp = <0x1>;
+			#phy-cells = <0x0>;
+			ranges;
+			has_xhci;
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+			linux,phandle = <0xc>;
+			phandle = <0xc>;
+		};
+
+		ehci_v2@f0470300 {
+			compatible = "brcm,ehci-brcm-v2";
+			reg = <0xf0470300 0xa8>;
+			interrupts = <0x0 0x71 0x0>;
+			interrupt-names = "usb0_ehci_0";
+			phys = <0xc 0x0>;
+			phy-names = "usbphy";
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+		};
+
+		ehci_v2@f0470500 {
+			compatible = "brcm,ehci-brcm-v2";
+			reg = <0xf0470500 0xa8>;
+			interrupts = <0x0 0x72 0x0>;
+			interrupt-names = "usb0_ehci_1";
+			phys = <0xc 0x0>;
+			phy-names = "usbphy";
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+		};
+
+		ohci_v2@f0470400 {
+			compatible = "brcm,ohci-brcm-v2";
+			reg = <0xf0470400 0x58>;
+			interrupts = <0x0 0x73 0x0>;
+			interrupt-names = "usb0_ohci_0";
+			phys = <0xc 0x0>;
+			phy-names = "usbphy";
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+		};
+
+		ohci_v2@f0470600 {
+			compatible = "brcm,ohci-brcm-v2";
+			reg = <0xf0470600 0x58>;
+			interrupts = <0x0 0x74 0x0>;
+			interrupt-names = "usb0_ohci_1";
+			phys = <0xc 0x0>;
+			phy-names = "usbphy";
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+		};
+
+		xhci_v2@f0471000 {
+			compatible = "brcm,xhci-brcm-v2";
+			reg = <0xf0471000 0x1000>;
+			interrupts = <0x0 0x75 0x0>;
+			interrupt-names = "usb0_xhci_0";
+			phys = <0xc 0x1>;
+			phy-names = "usbphy";
+			clocks = <0xd>;
+			clock-names = "sw_usb";
+		};
+
+		bdc_v2@f0472000 {
+			status = "disabled";
+			compatible = "brcm,bdc-udc-v2";
+			reg = <0xf0472000 0xfc4>;
+			interrupts = <0x0 0x76 0x0>;
+			interrupt-names = "usb0_usbd";
+			phys = <0xc 0x0>;
+			phy-names = "usbphy";
+		};
+
+		usb@f0470200 {
+			device = "off";
+			reg = <0xf0470200 0x100>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,usb-instance";
+			ioc = <0x1>;
+			ipp = <0x1>;
+			ranges;
+			interrupts-extended = <0x6 0xa>;
+			clocks = <0xb>;
+			clock-names = "sw_usb";
+
+			ehci@f0470300 {
+				compatible = "brcm,ehci-brcm";
+				reg = <0xf0470300 0xa8>;
+				interrupts = <0x0 0x71 0x0>;
+				interrupt-names = "usb0_ehci_0";
+				clocks = <0xb>;
+				clock-names = "sw_usb";
+			};
+
+			ehci@f0470500 {
+				compatible = "brcm,ehci-brcm";
+				reg = <0xf0470500 0xa8>;
+				interrupts = <0x0 0x72 0x0>;
+				interrupt-names = "usb0_ehci_1";
+				clocks = <0xb>;
+				clock-names = "sw_usb";
+			};
+
+			ohci@f0470400 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0xf0470400 0x58>;
+				interrupts = <0x0 0x73 0x0>;
+				interrupt-names = "usb0_ohci_0";
+				clocks = <0xb>;
+				clock-names = "sw_usb";
+			};
+
+			ohci@f0470600 {
+				compatible = "brcm,ohci-brcm";
+				reg = <0xf0470600 0x58>;
+				interrupts = <0x0 0x74 0x0>;
+				interrupt-names = "usb0_ohci_1";
+				clocks = <0xb>;
+				clock-names = "sw_usb";
+			};
+
+			xhci@f0471000 {
+				compatible = "xhci-platform";
+				reg = <0xf0471000 0x1000>;
+				interrupts = <0x0 0x75 0x0>;
+				interrupt-names = "usb0_xhci_0";
+				clocks = <0xd>;
+				clock-names = "sw_usb";
+			};
+
+			bdc@f0472000 {
+				status = "disabled";
+				compatible = "brcm,bdc-udc-v0.16", "brcm,bdc-udc";
+				reg = <0xf0472000 0xfc4>;
+				interrupts = <0x0 0x76 0x0>;
+				interrupt-names = "usb0_usbd";
+			};
+		};
+
+		ethernet@f0b00000 {
+			phy-mode = "internal";
+			phy-handle = <0xab>;
+			phy-speed = <0x3e8>;
+			phy-id = <0x1>;
+			phy-type = <0x1>;
+			local-mac-address = [ 00 09 34 00 09 00 ];
+			linux,phandle = <0xa9>;
+			phandle = <0xa9>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,genet-v4";
+			device_type = "network";
+			reg = <0xf0b00000 0xfc4c>;
+			interrupts = <0x0 0x54 0x0 0x0 0x55 0x0>;
+			interrupt-parent = <0x1>;
+			interrupts-extended = <0x1 0x0 0x54 0x0 0x1 0x0 0x55 0x0 0x6 0xd>;
+			interrupt-names = "genet_0_a", "genet_0_b", "wol_genet";
+			clocks = <0xe 0xf 0x10>;
+			clock-names = "sw_genet", "sw_geneteee", "sw_genetwol";
+
+			mdio@e14 {
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				compatible = "brcm,genet-mdio-v4";
+				reg = <0xe14 0x8>;
+
+				phy1: ethernet-phy@1 {
+					linux,phandle = <0xab>;
+					phandle = <0xab>;
+					clock-names = "sw_gphy";
+					clocks = <0xaa>;
+					device_type = "ethernet-phy";
+					max-speed = <0x3e8>;
+					reg = <0x1>;
+					compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22";
+				};
+			};
+		};
+
+		ethernet@f0b20000 {
+			status = "disabled";
+			linux,phandle = <0xac>;
+			phandle = <0xac>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,genet-v4";
+			device_type = "network";
+			reg = <0xf0b20000 0xfc4c>;
+			interrupts = <0x0 0x56 0x0 0x0 0x57 0x0>;
+			interrupt-parent = <0x1>;
+			interrupts-extended = <0x1 0x0 0x56 0x0 0x1 0x0 0x57 0x0 0x6 0xe>;
+			interrupt-names = "genet_1_a", "genet_1_b", "wol_genet";
+			clocks = <0x11 0x12 0x13>;
+			clock-names = "sw_genet", "sw_geneteee", "sw_genetwol";
+
+			mdio@e14 {
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				compatible = "brcm,genet-mdio-v4";
+				reg = <0xe14 0x8>;
+			};
+		};
+
+		ethernet@f0b40000 {
+			status = "disabled";
+			linux,phandle = <0xad>;
+			phandle = <0xad>;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,genet-v4";
+			device_type = "network";
+			reg = <0xf0b40000 0xfc4c>;
+			interrupts = <0x0 0x58 0x0 0x0 0x59 0x0>;
+			interrupt-parent = <0x1>;
+			interrupts-extended = <0x1 0x0 0x58 0x0 0x1 0x0 0x59 0x0 0x6 0xf>;
+			interrupt-names = "genet_2_a", "genet_2_b", "wol_genet";
+			clocks = <0x14 0x15 0x16>;
+			clock-names = "sw_genet", "sw_geneteee", "sw_genetwol";
+
+			mdio@e14 {
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				compatible = "brcm,genet-mdio-v4";
+				reg = <0xe14 0x8>;
+			};
+		};
+
+		gpio@f040a600 {
+			#gpio-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			compatible = "brcm,bcm7439-gpio", "brcm,brcmstb-gpio";
+			gpio-controller;
+			interrupt-controller;
+			reg = <0xf040a600 0xa0>;
+			interrupts = <0x9>;
+			interrupt-parent = <0x7>;
+			interrupts-extended = <0x7 0x9 0x6 0x5>;
+			interrupt-names = "upg_gio", "upg_gio_aon_wakeup";
+			wakeup-source;
+			brcm,gpio-bank-widths = <0x20 0x20 0x20 0x10 0x8>;
+		};
+
+		gpio@f0417400 {
+			#gpio-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			compatible = "brcm,bcm7439-gpio", "brcm,brcmstb-gpio";
+			gpio-controller;
+			interrupt-controller;
+			reg = <0xf0417400 0x40>;
+			interrupts = <0x5>;
+			interrupt-parent = <0x8>;
+			interrupts-extended = <0x8 0x5 0x6 0x5>;
+			interrupt-names = "upg_gio_aon", "upg_gio_aon_wakeup";
+			always-on;
+			wakeup-source;
+			brcm,gpio-bank-widths = <0x12 0x4>;
+		};
+
+		sata@f045a000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+			phy-enable-ssc-mask = <0x0>;
+			phy-generation = <0x2800>;
+			reg-names = "ahci", "top-ctrl";
+			reg = <0xf045a000 0xa9c 0xf0458040 0x24>;
+			interrupts = <0x0 0x3b 0x0>;
+			interrupt-names = "sata_0_ahci";
+			phy-base-addr = <0xf0458100>;
+			top-ctrl-base-addr = <0xf0458040>;
+			clocks = <0x17>;
+			clock-names = "sw_sata3";
+
+			sata-port@0 {
+				reg = <0x0>;
+				phys = <0x18>;
+			};
+
+			sata-port@1 {
+				reg = <0x1>;
+				phys = <0x19>;
+			};
+		};
+
+		sata_phy@f0458100 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
+			reg = <0xf0458100 0x1efc>;
+			reg-names = "phy";
+
+			sata-phy@0 {
+				reg = <0x0>;
+				#phy-cells = <0x0>;
+				linux,phandle = <0x18>;
+				phandle = <0x18>;
+			};
+
+			sata-phy@1 {
+				reg = <0x1>;
+				#phy-cells = <0x0>;
+				linux,phandle = <0x19>;
+				phandle = <0x19>;
+			};
+		};
+
+		sdhci@f03e0100 {
+			no-1-8-v;
+			compatible = "brcm,sdhci-brcmstb";
+			reg = <0xf03e0000 0x100 0xf03e0100 0x100>;
+			reg-names = "host", "cfg";
+			interrupts = <0x0 0x24 0x0>;
+			interrupt-names = "sdio0_0";
+			sdhci,auto-cmd12;
+			clocks = <0x1a>;
+			clock-names = "sw_sdio";
+		};
+
+		sdhci@f03e0300 {
+			no-1-8-v;
+			non-removable;
+			bus-width = <0x8>;
+			compatible = "brcm,sdhci-brcmstb";
+			reg = <0xf03e0200 0x100 0xf03e0300 0x100>;
+			reg-names = "host", "cfg";
+			interrupts = <0x0 0x25 0x0>;
+			interrupt-names = "sdio1_0";
+			sdhci,auto-cmd12;
+			clocks = <0x1a>;
+			clock-names = "sw_sdio";
+		};
+
+		cpupll@0 {
+			#clock-cells = <0x0>;
+			clock-frequency = <0x5995f5c0>;
+			compatible = "fixed-clock";
+			linux,phandle = <0x1f>;
+			phandle = <0x1f>;
+		};
+
+		cpu-clk-div@0 {
+			#clock-cells = <0x0>;
+			clocks = <0x1f>;
+			compatible = "brcm,brcmstb-cpu-clk-div";
+			reg = <0xf03e257c 0x4>;
+			div-table = <0x0 0x1>;
+			div-shift-width = <0x0 0x5>;
+		};
+
+		interrupt-controller@f0403000 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf0403000 0x48>;
+			interrupt-controller;
+			interrupts = <0x0 0x3d 0x0>;
+			interrupt-names = "sys";
+			linux,phandle = <0x20>;
+			phandle = <0x20>;
+		};
+
+		interrupt-controller@f03e1000 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf03e1000 0x30>;
+			interrupt-controller;
+			interrupts = <0x0 0x20 0x0>;
+			interrupt-names = "hif";
+			linux,phandle = <0x23>;
+			phandle = <0x23>;
+		};
+
+		interrupt-controller@f0410640 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf0410640 0x30>;
+			interrupt-controller;
+			interrupts = <0x0 0x3f 0x0>;
+			interrupt-names = "sys_pm";
+			brcm,irq-can-wake;
+			linux,phandle = <0x6>;
+			phandle = <0x6>;
+		};
+
+		interrupt-controller@f04d1200 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf04d1200 0x48>;
+			interrupt-controller;
+			interrupts = <0x0 0x1a 0x0>;
+			interrupt-names = "avs";
+			linux,phandle = <0x21>;
+			phandle = <0x21>;
+		};
+
+		gisb-arb@f0400000 {
+			compatible = "brcm,gisb-arb";
+			reg = <0xf0400000 0x800>;
+			interrupts = <0x0 0x2>;
+			interrupt-parent = <0x20>;
+			interrupt-names = "gisb_timeout", "gisb_tea";
+			brcm,gisb-arb-master-mask = <0x9a9fc3>;
+			brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0", "webcpu_0", "jtag_0", "ssp_0", "rdc_0", "hvd_0", "hvd_1", "vice_0", "raaga_0", "pcie_0", "pcie_1", "bbsi_spi";
+		};
+
+		waketimer@f0417580 {
+			compatible = "brcm,brcmstb-waketimer";
+			reg = <0xf0417580 0x14>;
+			interrupts = <0x3>;
+			interrupt-parent = <0x6>;
+			interrupt-names = "timer";
+		};
+
+		thermal@f04d1500 {
+			#thermal-sensor-cells = <0x0>;
+			compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
+			reg = <0xf04d1500 0x28>;
+			interrupts = <0x6>;
+			interrupt-parent = <0x21>;
+			interrupt-names = "tmon";
+			linux,phandle = <0x9d>;
+			phandle = <0x9d>;
+		};
+
+		sram@ffe00000 {
+			compatible = "brcm,boot-sram", "mmio-sram";
+			reg = <0xffe00000 0x10000>;
+		};
+
+		aon-ctrl@f0410000 {
+			compatible = "brcm,brcmstb-aon-ctrl";
+			reg = <0xf0410000 0x200 0xf0410200 0x400>;
+			reg-names = "aon-ctrl", "aon-sram";
+		};
+
+		memory_controllers {
+			ranges;
+			compatible = "simple-bus";
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+
+			memc@0 {
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				compatible = "brcm,brcmstb-memc", "simple-bus";
+				ranges;
+
+				memc-arb@f1101000 {
+					compatible = "brcm,brcmstb-memc-arb";
+					reg = <0xf1101000 0x4d4>;
+					brcm,memc-client-masks = <0xffffffff 0x7ffff3f 0xc0fffe00 0xc7c0fc0f 0xf83fe3c7 0x7 0x700ff00 0xff000000>;
+					brcm,memc-client-names = "xpt_wr_rs", "xpt_wr_xc", "xpt_wr_cdb", "xpt_wr_itb_msg", "xpt_rd_rs", "xpt_rd_xc_rmx_msg", "xpt_rd_xc_rave", "xpt_rd_pb", "xpt_wr_memdma", "xpt_rd_memdma", "genet0_wr", "genet0_rd", "genet1_wr", "genet1_rd", "genet2_wr", "genet2_rd", "moca_mips", "sata", "sata_1", "mcif1_rd", "mcif1_wr", "pcie_1", "bsp", "scpu", "flash_dma", "pcie", "sdio_emmc", "sdio_card", "tpcap", "mcif_rd", "mcif_wr", "uart_dma_rd", "uart_dma_wr", "usb_hi_0", "usb_lo_0", "usb_x_write_0", "usb_x_read_0", "usb_x_ctrl_0", "raaga", "raaga_1", "raaga1", "raaga1_1", "aud_aio", "vice_cme0", "vice_cme1", "vice_fme0", "vice_fme1", "vice_fme2", "vice_sg", "vice_dblk", "vice_cabac0", "vice_cabac1", "vice_arcss0", "vice_vip0_inst0", "vice_vip1_inst0", "vice_vip0_inst1", "vice_vip1_inst1", "hvd0_dblk", "hvd0_dblk1", "hvd0_ilcpu", "hvd0_olcpu", "hvd0_cab", "hvd0_ilsi", "hvd0_ilcpu_p2", "hvd0_ilsi_p2", "hvd1_dblk", "hvd1_dblk1", "hvd1_ilcpu", "hvd1_olcpu", "hvd1_cab", "hvd1_ilsi", "sid", "bvn_mad_pix_fd", "bvn_mad_quant", "bvn_mad_pix_cap", "bvn_mad1_pix_fd", "bvn_mad1_quant", "bvn_mad1_pix_cap", "bvn_mfd0", "bvn_mfd0_1", "bvn_mfd1", "bvn_mfd1_1", "bvn_mfd2", "bvn_mfd2_1", "bvn_vfd0", "bvn_vfd1", "bvn_vfd2", "bvn_vfd3", "bvn_vfd4", "bvn_cap0", "bvn_cap1", "bvn_cap2", "bvn_cap3", "bvn_cap4", "bvn_gfd0", "bvn_gfd1", "bvn_gfd2", "bvn_gfd3", "bvn_mcvp0", "bvn_mcvp1", "bvn_mcvp2", "bvn_rdc", "vec_vbi_enc0", "vec_vbi_enc1", "m2mc_0", "m2mc_1", "m2mc_2", "hvd0_dblk_p2", "hvd0_dblk1_p2", "bvn_mad4_pix_fd", "bvn_mad4_quant", "bvn_mad4_pix_cap", "m2mc1_0", "m2mc1_1", "m2mc1_2", "host_cpu_mcp_r_hi", "host_cpu_mcp_r_lo", "host_cpu_mcp_w_hi", "host_cpu_mcp_w_lo", "v3d_mcp_r_hi", "v3d_mcp_r_lo", "v3d_mcp_w_hi", "v3d_mcp_w_lo", "hvd0_mocomp", "hvd1_mocomp", "vice_pfri", "tracelog", "memc_reserved_0", "zcqs_engine", "msa", "dis0", "dis1", "dram_init_zqcs", "refresh";
+					brcm,memc-max-clients = <0x100>;
+				};
+
+				ddr-phy@f1120000 {
+					compatible = "brcm,brcmstb-ddr-phy-v240.1";
+					reg = <0xf1120000 0x21c>;
+				};
+
+				shimphy@f1108000 {
+					compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+					reg = <0xf1108000 0xe8>;
+				};
+
+				memc-ddr@f1102000 {
+					clock-frequency = <0x3f9920c0>;
+					compatible = "brcm,brcmstb-memc-ddr";
+					reg = <0xf1102000 0x800>;
+				};
+			};
+
+			memc@1 {
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				compatible = "brcm,brcmstb-memc", "simple-bus";
+				ranges;
+
+				memc-arb@f1181000 {
+					compatible = "brcm,brcmstb-memc-arb";
+					reg = <0xf1181000 0x4d4>;
+					brcm,memc-client-masks = <0xfe7ffff 0x7cbff3e 0xc0860600 0xc7c0fc0f 0xf839e3c7 0x7 0x700ff00 0xff000000>;
+					brcm,memc-client-names = "xpt_wr_rs", "xpt_wr_xc", "xpt_wr_cdb", "xpt_wr_itb_msg", "xpt_rd_rs", "xpt_rd_xc_rmx_msg", "xpt_rd_xc_rave", "xpt_rd_pb", "xpt_wr_memdma", "xpt_rd_memdma", "genet0_wr", "genet0_rd", "genet1_wr", "genet1_rd", "genet2_wr", "genet2_rd", "moca_mips", "sata", "sata_1", "pcie_1", "bsp", "scpu", "flash_dma", "pcie", "sdio_emmc", "sdio_card", "usb_hi_0", "usb_lo_0", "usb_x_write_0", "usb_x_read_0", "usb_x_ctrl_0", "raaga", "raaga_1", "raaga1", "raaga1_1", "aud_aio", "vice_cme0", "vice_cme1", "vice_fme0", "vice_fme1", "vice_fme2", "vice_dblk", "vice_arcss0", "vice_vip0_inst0", "vice_vip1_inst0", "vice_vip0_inst1", "vice_vip1_inst1", "hvd0_dblk", "hvd0_dblk1", "hvd1_dblk", "hvd1_dblk1", "sid", "bvn_mad_pix_fd", "bvn_mad_quant", "bvn_mad_pix_cap", "bvn_mad1_pix_fd", "bvn_mad1_quant", "bvn_mad1_pix_cap", "bvn_mfd0", "bvn_mfd0_1", "bvn_mfd1", "bvn_mfd1_1", "bvn_mfd2", "bvn_mfd2_1", "bvn_vfd0", "bvn_vfd1", "bvn_vfd2", "bvn_vfd3", "bvn_vfd4", "bvn_cap0", "bvn_cap1", "bvn_cap2", "bvn_cap3", "bvn_cap4", "bvn_gfd0", "bvn_gfd1", "bvn_gfd2", "bvn_gfd3", "bvn_mcvp0", "bvn_mcvp1", "bvn_mcvp2", "bvn_rdc", "m2mc_0", "m2mc_1", "m2mc_2", "hvd0_dblk_p2", "hvd0_dblk1_p2", "bvn_mad4_pix_fd", "bvn_mad4_quant", "bvn_mad4_pix_cap", "m2mc1_0", "m2mc1_1", "m2mc1_2", "host_cpu_mcp_r_hi", "host_cpu_mcp_r_lo", "host_cpu_mcp_w_hi", "host_cpu_mcp_w_lo", "v3d_mcp_r_hi", "v3d_mcp_r_lo", "v3d_mcp_w_hi", "v3d_mcp_w_lo", "hvd0_mocomp", "hvd1_mocomp", "vice_pfri", "tracelog", "memc_reserved_0", "zcqs_engine", "msa", "dis0", "dis1", "dram_init_zqcs", "refresh";
+					brcm,memc-max-clients = <0x100>;
+				};
+
+				ddr-phy@f11a0000 {
+					compatible = "brcm,brcmstb-ddr-phy-v240.1";
+					reg = <0xf11a0000 0x21c>;
+				};
+
+				shimphy@f1188000 {
+					compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+					reg = <0xf1188000 0xe8>;
+				};
+
+				memc-ddr@f1182000 {
+					clock-frequency = <0x3f9920c0>;
+					compatible = "brcm,brcmstb-memc-ddr";
+					reg = <0xf1182000 0x800>;
+				};
+			};
+		};
+
+		spi@f03e3400 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			compatible = "brcm,spi-brcmstb";
+			reg = <0xf03e3400 0x188 0xf03e3200 0x50 0xf03e3300 0x24>;
+			reg-names = "hif_mspi", "bspi", "bspi_raf";
+			interrupts = <0x0 0x21 0x0>;
+			interrupt-names = "hif_spi";
+			clocks = <0x22>;
+			clock-names = "sw_spi";
+
+			m25p80@0 {
+				#size-cells = <0x2>;
+				#address-cells = <0x2>;
+				compatible = "m25p80";
+				reg = <0x0>;
+				spi-max-frequency = <0x2625a00>;
+				spi-cpol;
+				spi-cpha;
+				use-bspi;
+				m25p,fast-read;
+
+				flash0.bolt@0 {
+					reg = <0x0 0x0 0x0 0x200000>;
+				};
+
+				flash0.nvram@200000 {
+					reg = <0x0 0x200000 0x0 0x20000>;
+				};
+
+				flash0.devtree@220000 {
+					reg = <0x0 0x220000 0x0 0x20000>;
+				};
+
+				flash0.recovery@240000 {
+					reg = <0x0 0x240000 0x0 0xdc0000>;
+				};
+
+				flash0@0 {
+					reg = <0x0 0x0 0x0 0x2000000>;
+				};
+			};
+		};
+
+		nand@f03e2800 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
+			reg-names = "nand", "flash-dma";
+			status = "disabled";
+			reg = <0xf03e2800 0x600 0xf03e3000 0x2c>;
+			interrupts = <0x18 0x4>;
+			interrupt-parent = <0x23>;
+			interrupt-names = "nand_ctlrdy", "flash_dma_done";
+		};
+
+		syscon@f0404000 {
+			compatible = "brcm,brcmstb-sun-top-ctrl", "syscon";
+			reg = <0xf0404000 0x524>;
+			linux,phandle = <0x3>;
+			phandle = <0x3>;
+		};
+
+		syscon@f03e2400 {
+			compatible = "brcm,brcmstb-cpu-biu-ctrl", "syscon";
+			reg = <0xf03e2400 0x400>;
+			brcm,write-pairing;
+			linux,phandle = <0x4>;
+			phandle = <0x4>;
+		};
+
+		syscon@f0452000 {
+			compatible = "brcm,brcmstb-hif-continuation", "syscon";
+			reg = <0xf0452000 0x100>;
+			linux,phandle = <0x5>;
+			phandle = <0x5>;
+		};
+
+		brcmstb-clks {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			reg = <0xf04e0000 0x684 0xf04d1800 0xdc 0xf0410000 0x600>;
+			ranges;
+
+			sw_scb {
+				clock-frequency = <0x19bfcc00>;
+				#clocks-cells = <0x0>;
+				compatible = "fixed-clock";
+			};
+
+			upg_fixed {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x19bfcc0>;
+				linux,phandle = <0x9c>;
+				phandle = <0x9c>;
+			};
+
+			osc_pcie0@f0410074 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf0410074 0x4>;
+				bit-shift = <0x6>;
+				set-bit-to-disable;
+				linux,phandle = <0x82>;
+				phandle = <0x82>;
+			};
+
+			osc_mocaphy@f0410074 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf0410074 0x4>;
+				bit-shift = <0x5>;
+				set-bit-to-disable;
+				linux,phandle = <0x7a>;
+				phandle = <0x7a>;
+			};
+
+			osc_usb0@f0410074 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf0410074 0x4>;
+				bit-shift = <0x4>;
+				set-bit-to-disable;
+				linux,phandle = <0x9b>;
+				phandle = <0x9b>;
+			};
+
+			osc_sata_pcie1@f0410074 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf0410074 0x4>;
+				bit-shift = <0x3>;
+				set-bit-to-disable;
+				linux,phandle = <0x88>;
+				phandle = <0x88>;
+			};
+
+			fixed1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x24>;
+				phandle = <0x24>;
+			};
+
+			hvd_pwrdn_req@f04e0654 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0654 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				brcm,inhibit-disable;
+				brcm,read-only;
+				clocks = <0x24>;
+				clock-names = "fixed1";
+				linux,phandle = <0x25>;
+				phandle = <0x25>;
+			};
+
+			hvd_pdiv@f04e0050 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0050 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x25>;
+				clock-names = "hvd_pwrdn_req";
+				linux,phandle = <0x26>;
+				phandle = <0x26>;
+			};
+
+			hvd_ndiv_int {
+				compatible = "multiplier-clock", "fixed-factor-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0050 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0xc8>;
+				clocks = <0x26>;
+				clock-names = "hvd_pdiv";
+				linux,phandle = <0x27>;
+				phandle = <0x27>;
+			};
+
+			hvd_mdiv_ch4@f04e0048 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0048 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x27>;
+				clock-names = "hvd_ndiv_int";
+				linux,phandle = <0x28>;
+				phandle = <0x28>;
+			};
+
+			hvd_dis_ch4@f04e0048 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0048 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x28>;
+				clock-names = "hvd_mdiv_ch4";
+				linux,phandle = <0x29>;
+				phandle = <0x29>;
+			};
+
+			hvd_pdh_ch4@f04e0048 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0048 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x29>;
+				clock-names = "hvd_dis_ch4";
+				linux,phandle = <0x2a>;
+				phandle = <0x2a>;
+			};
+
+			hif_sdio_card@f04e038c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e038c 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				clocks = <0x2a>;
+				clock-names = "hvd_pdh_ch4";
+				linux,phandle = <0x91>;
+				phandle = <0x91>;
+			};
+
+			hif_sdio_emmc@f04e038c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e038c 0x4>;
+				bit-shift = <0x2>;
+				set-bit-to-disable;
+				clocks = <0x2a>;
+				clock-names = "hvd_pdh_ch4";
+				linux,phandle = <0x92>;
+				phandle = <0x92>;
+			};
+
+			hvd_mdiv_ch3@f04e0044 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0044 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x27>;
+				clock-names = "hvd_ndiv_int";
+				linux,phandle = <0x2b>;
+				phandle = <0x2b>;
+			};
+
+			hvd_dis_ch3@f04e0044 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0044 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x2b>;
+				clock-names = "hvd_mdiv_ch3";
+				linux,phandle = <0x2c>;
+				phandle = <0x2c>;
+			};
+
+			hvd_pdh_ch3@f04e0044 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0044 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x2c>;
+				clock-names = "hvd_dis_ch3";
+				linux,phandle = <0x2d>;
+				phandle = <0x2d>;
+			};
+
+			hif_spi@f04e038c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e038c 0x4>;
+				bit-shift = <0x3>;
+				set-bit-to-disable;
+				clocks = <0x2d>;
+				clock-names = "hvd_pdh_ch3";
+				linux,phandle = <0x22>;
+				phandle = <0x22>;
+			};
+
+			mocamac_54@f04e041c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e041c 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x7b>;
+				phandle = <0x7b>;
+			};
+
+			mocamac_gisb@f04e041c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e041c 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x7c>;
+				phandle = <0x7c>;
+			};
+
+			mocamac_scb@f04e041c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e041c 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x7d>;
+				phandle = <0x7d>;
+			};
+
+			mocaphy_54@f04e0428 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0428 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x7e>;
+				phandle = <0x7e>;
+			};
+
+			mocaphy_gisb@f04e0428 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0428 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x7f>;
+				phandle = <0x7f>;
+			};
+
+			pcie_alwayson@f04e0450 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0450 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				linux,phandle = <0x83>;
+				phandle = <0x83>;
+			};
+
+			pcie_108@f04e0458 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0458 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x84>;
+				phandle = <0x84>;
+			};
+
+			pcie_54@f04e0458 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0458 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x85>;
+				phandle = <0x85>;
+			};
+
+			pcie_gisb@f04e0458 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0458 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x86>;
+				phandle = <0x86>;
+			};
+
+			pcie_scb@f04e0458 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0458 0x4>;
+				bit-shift = <0x3>;
+				linux,phandle = <0x87>;
+				phandle = <0x87>;
+			};
+
+			pcie1_alwayson@f04e04ec {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04ec 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				linux,phandle = <0x89>;
+				phandle = <0x89>;
+			};
+
+			pcie1_54_pcie@f04e04f4 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04f4 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x8a>;
+				phandle = <0x8a>;
+			};
+
+			pcie1_gisb_pcie@f04e04f4 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04f4 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x8b>;
+				phandle = <0x8b>;
+			};
+
+			pcie1_scb_pcie@f04e04f4 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04f4 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x8c>;
+				phandle = <0x8c>;
+			};
+
+			sata3_108_pcie@f04e04f4 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04f4 0x4>;
+				bit-shift = <0x3>;
+				linux,phandle = <0x8d>;
+				phandle = <0x8d>;
+			};
+
+			sata3_54@f04e04fc {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04fc 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x8e>;
+				phandle = <0x8e>;
+			};
+
+			sata3_gisb@f04e04fc {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04fc 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x8f>;
+				phandle = <0x8f>;
+			};
+
+			sata3_scb@f04e04fc {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e04fc 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x90>;
+				phandle = <0x90>;
+			};
+
+			genet0_alwayson@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				linux,phandle = <0x51>;
+				phandle = <0x51>;
+			};
+
+			fixed4 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x2e>;
+				phandle = <0x2e>;
+			};
+
+			net_pwrdn_req@f04e0658 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0658 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				clocks = <0x2e>;
+				clock-names = "fixed4";
+				linux,phandle = <0x2f>;
+				phandle = <0x2f>;
+			};
+
+			net_pdiv@f04e010c {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e010c 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x2f>;
+				clock-names = "net_pwrdn_req";
+				linux,phandle = <0x30>;
+				phandle = <0x30>;
+			};
+
+			net_ndiv_int {
+				compatible = "multiplier-clock", "fixed-factor-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e010c 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0x7d>;
+				clocks = <0x30>;
+				clock-names = "net_pdiv";
+				linux,phandle = <0x31>;
+				phandle = <0x31>;
+			};
+
+			net_mdiv_ch1@f04e0104 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0104 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x31>;
+				clock-names = "net_ndiv_int";
+				linux,phandle = <0x32>;
+				phandle = <0x32>;
+			};
+
+			net_dis_ch1@f04e0104 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0104 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x32>;
+				clock-names = "net_mdiv_ch1";
+				linux,phandle = <0x33>;
+				phandle = <0x33>;
+			};
+
+			net_pdh_ch1@f04e0104 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0104 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x33>;
+				clock-names = "net_dis_ch1";
+				linux,phandle = <0x34>;
+				phandle = <0x34>;
+			};
+
+			genet0_sys_fast@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				clocks = <0x34>;
+				clock-names = "net_pdh_ch1";
+				linux,phandle = <0x52>;
+				phandle = <0x52>;
+			};
+
+			genet0_sys_pm@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x2>;
+				set-bit-to-disable;
+				linux,phandle = <0x53>;
+				phandle = <0x53>;
+			};
+
+			genet0_sys_slow@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x3>;
+				set-bit-to-disable;
+				linux,phandle = <0x54>;
+				phandle = <0x54>;
+			};
+
+			genet1_alwayson@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x4>;
+				set-bit-to-disable;
+				linux,phandle = <0x5f>;
+				phandle = <0x5f>;
+			};
+
+			genet1_sys_fast@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x5>;
+				set-bit-to-disable;
+				clocks = <0x34>;
+				clock-names = "net_pdh_ch1";
+				linux,phandle = <0x60>;
+				phandle = <0x60>;
+			};
+
+			genet1_sys_pm@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x6>;
+				set-bit-to-disable;
+				linux,phandle = <0x61>;
+				phandle = <0x61>;
+			};
+
+			genet1_sys_slow@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x7>;
+				set-bit-to-disable;
+				linux,phandle = <0x62>;
+				phandle = <0x62>;
+			};
+
+			genet2_alwayson@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x8>;
+				set-bit-to-disable;
+				linux,phandle = <0x6b>;
+				phandle = <0x6b>;
+			};
+
+			genet2_sys_fast@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0x9>;
+				set-bit-to-disable;
+				clocks = <0x34>;
+				clock-names = "net_pdh_ch1";
+				linux,phandle = <0x6c>;
+				phandle = <0x6c>;
+			};
+
+			genet2_sys_pm@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				linux,phandle = <0x6d>;
+				phandle = <0x6d>;
+			};
+
+			genet2_sys_slow@f04e0538 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0538 0x4>;
+				bit-shift = <0xb>;
+				set-bit-to-disable;
+				linux,phandle = <0x6e>;
+				phandle = <0x6e>;
+			};
+
+			genet_54@f04e0540 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0540 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x55>;
+				phandle = <0x55>;
+			};
+
+			genet_scb@f04e0540 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0540 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x56>;
+				phandle = <0x56>;
+			};
+
+			genet0_250@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x57>;
+				phandle = <0x57>;
+			};
+
+			genet0_eee@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x77>;
+				phandle = <0x77>;
+			};
+
+			genet0_gisb@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x58>;
+				phandle = <0x58>;
+			};
+
+			genet0_gmii@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x3>;
+				linux,phandle = <0x59>;
+				phandle = <0x59>;
+			};
+
+			genet0_hfb@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x4>;
+				linux,phandle = <0x5a>;
+				phandle = <0x5a>;
+			};
+
+			genet0_l2intr@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x5>;
+				linux,phandle = <0x5b>;
+				phandle = <0x5b>;
+			};
+
+			genet0_scb@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x6>;
+				linux,phandle = <0x5c>;
+				phandle = <0x5c>;
+			};
+
+			genet0_umac_rx@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x7>;
+				linux,phandle = <0x5d>;
+				phandle = <0x5d>;
+			};
+
+			genet0_umac_tx@f04e0544 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0544 0x4>;
+				bit-shift = <0x8>;
+				linux,phandle = <0x5e>;
+				phandle = <0x5e>;
+			};
+
+			net_mdiv_ch0@f04e0100 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0100 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x31>;
+				clock-names = "net_ndiv_int";
+				linux,phandle = <0x35>;
+				phandle = <0x35>;
+			};
+
+			net_dis_ch0@f04e0100 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0100 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x35>;
+				clock-names = "net_mdiv_ch0";
+				linux,phandle = <0x36>;
+				phandle = <0x36>;
+			};
+
+			net_pdh_ch0@f04e0100 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0100 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x36>;
+				clock-names = "net_dis_ch0";
+				linux,phandle = <0x37>;
+				phandle = <0x37>;
+			};
+
+			genet1_250@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x0>;
+				clocks = <0x37>;
+				clock-names = "net_pdh_ch0";
+				linux,phandle = <0x63>;
+				phandle = <0x63>;
+			};
+
+			genet1_eee@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x78>;
+				phandle = <0x78>;
+			};
+
+			genet1_gisb@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x64>;
+				phandle = <0x64>;
+			};
+
+			genet1_gmii@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x3>;
+				linux,phandle = <0x65>;
+				phandle = <0x65>;
+			};
+
+			genet1_hfb@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x4>;
+				linux,phandle = <0x66>;
+				phandle = <0x66>;
+			};
+
+			genet1_l2intr@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x5>;
+				linux,phandle = <0x67>;
+				phandle = <0x67>;
+			};
+
+			genet1_scb@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x6>;
+				linux,phandle = <0x68>;
+				phandle = <0x68>;
+			};
+
+			genet1_umac_rx@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x7>;
+				linux,phandle = <0x69>;
+				phandle = <0x69>;
+			};
+
+			genet1_umac_tx@f04e054c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e054c 0x4>;
+				bit-shift = <0x8>;
+				linux,phandle = <0x6a>;
+				phandle = <0x6a>;
+			};
+
+			genet2_250@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x0>;
+				clocks = <0x37>;
+				clock-names = "net_pdh_ch0";
+				linux,phandle = <0x6f>;
+				phandle = <0x6f>;
+			};
+
+			genet2_eee@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x79>;
+				phandle = <0x79>;
+			};
+
+			genet2_gisb@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x70>;
+				phandle = <0x70>;
+			};
+
+			genet2_gmii@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x3>;
+				linux,phandle = <0x71>;
+				phandle = <0x71>;
+			};
+
+			genet2_hfb@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x4>;
+				linux,phandle = <0x72>;
+				phandle = <0x72>;
+			};
+
+			genet2_l2intr@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x5>;
+				linux,phandle = <0x73>;
+				phandle = <0x73>;
+			};
+
+			genet2_scb@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x6>;
+				linux,phandle = <0x74>;
+				phandle = <0x74>;
+			};
+
+			genet2_umac_rx@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x7>;
+				linux,phandle = <0x75>;
+				phandle = <0x75>;
+			};
+
+			genet2_umac_tx@f04e0554 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0554 0x4>;
+				bit-shift = <0x8>;
+				linux,phandle = <0x76>;
+				phandle = <0x76>;
+			};
+
+			usb0_54_mdio@f04e057c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e057c 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				linux,phandle = <0x93>;
+				phandle = <0x93>;
+			};
+
+			usb0_54@f04e0584 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0584 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x94>;
+				phandle = <0x94>;
+			};
+
+			usb0_gisb@f04e0584 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0584 0x4>;
+				bit-shift = <0x1>;
+				linux,phandle = <0x95>;
+				phandle = <0x95>;
+			};
+
+			usb0_scb@f04e0584 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0584 0x4>;
+				bit-shift = <0x2>;
+				linux,phandle = <0x96>;
+				phandle = <0x96>;
+			};
+
+			usb0_108_ahb@f04e0588 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0588 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x97>;
+				phandle = <0x97>;
+			};
+
+			usb0_108_axi@f04e0590 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0590 0x4>;
+				bit-shift = <0x0>;
+				linux,phandle = <0x98>;
+				phandle = <0x98>;
+			};
+
+			fixed3 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x38>;
+				phandle = <0x38>;
+			};
+
+			moca_pwrdn_req@f04e065c {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e065c 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				clocks = <0x38>;
+				clock-names = "fixed3";
+				linux,phandle = <0x46>;
+				phandle = <0x46>;
+			};
+
+			fixed2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x39>;
+				phandle = <0x39>;
+			};
+
+			lc_pwrdn_req@f04e0668 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0668 0x4>;
+				bit-shift = <0x1>;
+				set-bit-to-disable;
+				clocks = <0x39>;
+				clock-names = "fixed2";
+				linux,phandle = <0x3d>;
+				phandle = <0x3d>;
+			};
+
+			fixed0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x3a>;
+				phandle = <0x3a>;
+			};
+
+			cpu_pdiv@f04e0008 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0008 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x3a>;
+				clock-names = "fixed0";
+				linux,phandle = <0x3b>;
+				phandle = <0x3b>;
+			};
+
+			cpu_ndiv_int {
+				compatible = "multiplier-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0008 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0xa7>;
+				clocks = <0x3b>;
+				clock-names = "cpu_pdiv";
+				linux,phandle = <0x3c>;
+				phandle = <0x3c>;
+			};
+
+			cpu_mdiv_ch0@f04e0000 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0000 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x3c>;
+				clock-names = "cpu_ndiv_int";
+				linux,phandle = <0x2>;
+				phandle = <0x2>;
+			};
+
+			lc_pdiv@f04e0094 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0094 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x3d>;
+				clock-names = "lc_pwrdn_req";
+				linux,phandle = <0x3e>;
+				phandle = <0x3e>;
+			};
+
+			lc_ndiv_int {
+				compatible = "multiplier-clock", "fixed-factor-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0094 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0x64>;
+				clocks = <0x3e>;
+				clock-names = "lc_pdiv";
+				linux,phandle = <0x3f>;
+				phandle = <0x3f>;
+			};
+
+			lc_mdiv_ch0@f04e0080 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0080 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x3f>;
+				clock-names = "lc_ndiv_int";
+				linux,phandle = <0x40>;
+				phandle = <0x40>;
+			};
+
+			lc_dis_ch0@f04e0080 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0080 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x40>;
+				clock-names = "lc_mdiv_ch0";
+				linux,phandle = <0x41>;
+				phandle = <0x41>;
+			};
+
+			lc_pdh_ch0@f04e0080 {
+				linux,phandle = <0xaa>;
+				phandle = <0xaa>;
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0080 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x41>;
+				clock-names = "lc_dis_ch0";
+			};
+
+			lc_mdiv_ch2@f04e0084 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0084 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x3f>;
+				clock-names = "lc_ndiv_int";
+				linux,phandle = <0x42>;
+				phandle = <0x42>;
+			};
+
+			lc_dis_ch2@f04e0084 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0084 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x42>;
+				clock-names = "lc_mdiv_ch2";
+				linux,phandle = <0x43>;
+				phandle = <0x43>;
+			};
+
+			lc_pdh_ch2@f04e0084 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0084 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x43>;
+				clock-names = "lc_dis_ch2";
+				linux,phandle = <0x99>;
+				phandle = <0x99>;
+			};
+
+			lc_mdiv_ch4@f04e0088 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0088 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x3f>;
+				clock-names = "lc_ndiv_int";
+				linux,phandle = <0x44>;
+				phandle = <0x44>;
+			};
+
+			lc_dis_ch4@f04e0088 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0088 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x44>;
+				clock-names = "lc_mdiv_ch4";
+				linux,phandle = <0x45>;
+				phandle = <0x45>;
+			};
+
+			lc_pdh_ch4@f04e0088 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e0088 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x45>;
+				clock-names = "lc_dis_ch4";
+				linux,phandle = <0x9a>;
+				phandle = <0x9a>;
+			};
+
+			moca_pdiv@f04e00d4 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00d4 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x46>;
+				clock-names = "moca_pwrdn_req";
+				linux,phandle = <0x47>;
+				phandle = <0x47>;
+			};
+
+			moca_ndiv_int {
+				compatible = "multiplier-clock", "fixed-factor-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00d4 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0xc8>;
+				clocks = <0x47>;
+				clock-names = "moca_pdiv";
+				linux,phandle = <0x48>;
+				phandle = <0x48>;
+			};
+
+			moca_mdiv_ch0@f04e00c8 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00c8 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x48>;
+				clock-names = "moca_ndiv_int";
+				linux,phandle = <0x1d>;
+				phandle = <0x1d>;
+			};
+
+			moca_dis_ch0@f04e00c8 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00c8 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x1d>;
+				clock-names = "moca_mdiv_ch0";
+				linux,phandle = <0x49>;
+				phandle = <0x49>;
+			};
+
+			moca_pdh_ch0@f04e00c8 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00c8 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x49>;
+				clock-names = "moca_dis_ch0";
+				linux,phandle = <0x80>;
+				phandle = <0x80>;
+			};
+
+			moca_mdiv_ch1@f04e00cc {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00cc 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x48>;
+				clock-names = "moca_ndiv_int";
+				linux,phandle = <0x1e>;
+				phandle = <0x1e>;
+			};
+
+			moca_dis_ch1@f04e00cc {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00cc 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x1e>;
+				clock-names = "moca_mdiv_ch1";
+				linux,phandle = <0x4a>;
+				phandle = <0x4a>;
+			};
+
+			moca_pdh_ch1@f04e00cc {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00cc 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x4a>;
+				clock-names = "moca_dis_ch1";
+				linux,phandle = <0x81>;
+				phandle = <0x81>;
+			};
+
+			moca_mdiv_ch2@f04e00d0 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00d0 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x48>;
+				clock-names = "moca_ndiv_int";
+				linux,phandle = <0x4b>;
+				phandle = <0x4b>;
+			};
+
+			moca_dis_ch2@f04e00d0 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00d0 0x4>;
+				bit-shift = <0x0>;
+				set-bit-to-disable;
+				clocks = <0x4b>;
+				clock-names = "moca_mdiv_ch2";
+				linux,phandle = <0x4c>;
+				phandle = <0x4c>;
+			};
+
+			moca_pdh_ch2@f04e00d0 {
+				compatible = "brcm,brcmstb-gate-clk";
+				#clock-cells = <0x0>;
+				reg = <0xf04e00d0 0x4>;
+				bit-shift = <0xa>;
+				set-bit-to-disable;
+				clocks = <0x4c>;
+				clock-names = "moca_dis_ch2";
+				linux,phandle = <0x1c>;
+				phandle = <0x1c>;
+			};
+
+			fixed7 {
+				compatible = "fixed-clock";
+				#clock-cells = <0x0>;
+				clock-frequency = <0x337f980>;
+				linux,phandle = <0x4d>;
+				phandle = <0x4d>;
+			};
+
+			sys0_pdiv@f04e01bc {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e01bc 0x4>;
+				bit-shift = <0xa>;
+				bit-mask = <0xf>;
+				index-starts-at-one;
+				clocks = <0x4d>;
+				clock-names = "fixed7";
+				linux,phandle = <0x4e>;
+				phandle = <0x4e>;
+			};
+
+			sys0_ndiv_int {
+				compatible = "multiplier-clock", "fixed-factor-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e01bc 0x4>;
+				bit-shift = <0x0>;
+				bit-mask = <0x3ff>;
+				index-max-mult-at-zero;
+				clock-div = <0x1>;
+				clock-mult = <0x48>;
+				clocks = <0x4e>;
+				clock-names = "sys0_pdiv";
+				linux,phandle = <0x4f>;
+				phandle = <0x4f>;
+			};
+
+			sys0_mdiv_ch1@f04e01a8 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e01a8 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x4f>;
+				clock-names = "sys0_ndiv_int";
+				linux,phandle = <0x50>;
+				phandle = <0x50>;
+			};
+
+			sys0_mdiv_ch5@f04e01b8 {
+				compatible = "divider-clock";
+				#clock-cells = <0x0>;
+				reg = <0xf04e01b8 0x4>;
+				bit-shift = <0x1>;
+				bit-mask = <0xff>;
+				index-starts-at-one;
+				clocks = <0x4f>;
+				clock-names = "sys0_ndiv_int";
+			};
+
+			sw_cpu {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x2 0x50>;
+				clock-names = "cpu_mdiv_ch0", "sys0_mdiv_ch1";
+			};
+
+			sw_genet0 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x37 0x50>;
+				clock-names = "genet0_alwayson", "genet0_sys_fast", "genet0_sys_pm", "genet0_sys_slow", "genet_54", "genet_scb", "genet0_250", "genet0_gisb", "genet0_gmii", "genet0_hfb", "genet0_l2intr", "genet0_scb", "genet0_umac_rx", "genet0_umac_tx", "net_pdh_ch0", "sys0_mdiv_ch1";
+				linux,phandle = <0xe>;
+				phandle = <0xe>;
+			};
+
+			sw_genet1 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x50>;
+				clock-names = "genet1_alwayson", "genet1_sys_fast", "genet1_sys_pm", "genet1_sys_slow", "genet1_250", "genet1_gisb", "genet1_gmii", "genet1_hfb", "genet1_l2intr", "genet1_scb", "genet1_umac_rx", "genet1_umac_tx", "sys0_mdiv_ch1";
+				linux,phandle = <0x11>;
+				phandle = <0x11>;
+			};
+
+			sw_genet2 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x50>;
+				clock-names = "genet2_alwayson", "genet2_sys_fast", "genet2_sys_pm", "genet2_sys_slow", "genet2_250", "genet2_gisb", "genet2_gmii", "genet2_hfb", "genet2_l2intr", "genet2_scb", "genet2_umac_rx", "genet2_umac_tx", "sys0_mdiv_ch1";
+				linux,phandle = <0x14>;
+				phandle = <0x14>;
+			};
+
+			sw_geneteee0 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x53 0x77>;
+				clock-names = "genet0_sys_pm", "genet0_eee";
+				linux,phandle = <0xf>;
+				phandle = <0xf>;
+			};
+
+			sw_geneteee1 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x61 0x78>;
+				clock-names = "genet1_sys_pm", "genet1_eee";
+				linux,phandle = <0x12>;
+				phandle = <0x12>;
+			};
+
+			sw_geneteee2 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x6d 0x79>;
+				clock-names = "genet2_sys_pm", "genet2_eee";
+				linux,phandle = <0x15>;
+				phandle = <0x15>;
+			};
+
+			sw_genetwol0 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x51 0x54 0x55 0x5a 0x5b 0x5d>;
+				clock-names = "genet0_alwayson", "genet0_sys_slow", "genet_54", "genet0_hfb", "genet0_l2intr", "genet0_umac_rx";
+				linux,phandle = <0x10>;
+				phandle = <0x10>;
+			};
+
+			sw_genetwol1 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x5f 0x62 0x66 0x67 0x69>;
+				clock-names = "genet1_alwayson", "genet1_sys_slow", "genet1_hfb", "genet1_l2intr", "genet1_umac_rx";
+				linux,phandle = <0x13>;
+				phandle = <0x13>;
+			};
+
+			sw_genetwol2 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x6b 0x6e 0x72 0x73 0x75>;
+				clock-names = "genet2_alwayson", "genet2_sys_slow", "genet2_hfb", "genet2_l2intr", "genet2_umac_rx";
+				linux,phandle = <0x16>;
+				phandle = <0x16>;
+			};
+
+			sw_moca {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x1c 0x50>;
+				clock-names = "osc_mocaphy", "mocamac_54", "mocamac_gisb", "mocamac_scb", "mocaphy_54", "mocaphy_gisb", "moca_pdh_ch0", "moca_pdh_ch1", "moca_pdh_ch2", "sys0_mdiv_ch1";
+				linux,phandle = <0x1b>;
+				phandle = <0x1b>;
+			};
+
+			sw_pcie0 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x82 0x83 0x84 0x85 0x86 0x87 0x50>;
+				clock-names = "osc_pcie0", "pcie_alwayson", "pcie_108", "pcie_54", "pcie_gisb", "pcie_scb", "sys0_mdiv_ch1";
+				linux,phandle = <0x9>;
+				phandle = <0x9>;
+			};
+
+			sw_pcie1 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x50>;
+				clock-names = "osc_sata_pcie1", "pcie1_alwayson", "pcie1_54_pcie", "pcie1_gisb_pcie", "pcie1_scb_pcie", "sata3_108_pcie", "sys0_mdiv_ch1";
+				linux,phandle = <0xa>;
+				phandle = <0xa>;
+			};
+
+			sw_sata3 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x88 0x8e 0x8f 0x90 0x50>;
+				clock-names = "osc_sata_pcie1", "sata3_54", "sata3_gisb", "sata3_scb", "sys0_mdiv_ch1";
+				linux,phandle = <0x17>;
+				phandle = <0x17>;
+			};
+
+			sw_sdio {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x91 0x92>;
+				clock-names = "hif_sdio_card", "hif_sdio_emmc";
+				linux,phandle = <0x1a>;
+				phandle = <0x1a>;
+			};
+
+			sw_usb20 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x50>;
+				clock-names = "usb0_54_mdio", "usb0_54", "usb0_gisb", "usb0_scb", "usb0_108_ahb", "usb0_108_axi", "lc_pdh_ch2", "lc_pdh_ch4", "sys0_mdiv_ch1";
+				linux,phandle = <0xb>;
+				phandle = <0xb>;
+			};
+
+			sw_usb30 {
+				compatible = "brcm,brcmstb-sw-clk";
+				#clock-cells = <0x0>;
+				clocks = <0x9b 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x50>;
+				clock-names = "osc_usb0", "usb0_54_mdio", "usb0_54", "usb0_gisb", "usb0_scb", "usb0_108_ahb", "usb0_108_axi", "lc_pdh_ch2", "lc_pdh_ch4", "sys0_mdiv_ch1";
+				linux,phandle = <0xd>;
+				phandle = <0xd>;
+			};
+		};
+
+		syscon@f0404100 {
+			compatible = "brcm,brcmstb-sun-top-ctrl-pin-mux-ctrl", "syscon";
+			reg = <0xf0404100 0x5c>;
+			linux,phandle = <0x9e>;
+			phandle = <0x9e>;
+		};
+
+		syscon@f040415c {
+			compatible = "brcm,brcmstb-sun-top-ctrl-pin-mux-pad-ctrl", "syscon";
+			reg = <0xf040415c 0x40>;
+			linux,phandle = <0x9f>;
+			phandle = <0x9f>;
+		};
+
+		syscon@f0410700 {
+			compatible = "brcm,brcmstb-aon-pin-ctrl-pin-mux-ctrl", "syscon";
+			reg = <0xf0410700 0xc>;
+			linux,phandle = <0xa0>;
+			phandle = <0xa0>;
+		};
+
+		syscon@f041070c {
+			compatible = "brcm,brcmstb-aon-pin-ctrl-pad-mux-ctrl", "syscon";
+			reg = <0xf041070c 0x8>;
+			linux,phandle = <0xa1>;
+			phandle = <0xa1>;
+		};
+
+		syscon@f1101004 {
+			compatible = "brcm,brcmstb-memc-arb-0-client-info", "syscon";
+			reg = <0xf1101004 0x400>;
+			linux,phandle = <0xa2>;
+			phandle = <0xa2>;
+		};
+
+		syscon@f1181004 {
+			compatible = "brcm,brcmstb-memc-arb-1-client-info", "syscon";
+			reg = <0xf1181004 0x400>;
+			linux,phandle = <0xa3>;
+			phandle = <0xa3>;
+		};
+
+		syscon@f0404080 {
+			compatible = "brcm,brcmstb-sun-top-ctrl-general-ctrl-0", "syscon";
+			reg = <0xf0404080 0x4>;
+			linux,phandle = <0xa4>;
+			phandle = <0xa4>;
+		};
+
+		syscon@f04040a4 {
+			compatible = "brcm,brcmstb-sun-top-ctrl-general-ctrl-no-scan-0", "syscon";
+			reg = <0xf04040a4 0x4>;
+			linux,phandle = <0xa5>;
+			phandle = <0xa5>;
+		};
+
+		syscon@f03e0154 {
+			compatible = "brcm,brcmstb-sdio-0-cfg-sd-pin-sel", "syscon";
+			reg = <0xf03e0154 0x4>;
+			linux,phandle = <0xa6>;
+			phandle = <0xa6>;
+		};
+
+		syscon@f03e0354 {
+			compatible = "brcm,brcmstb-sdio-1-cfg-sd-pin-sel", "syscon";
+			reg = <0xf03e0354 0x4>;
+			linux,phandle = <0xa7>;
+			phandle = <0xa7>;
+		};
+
+		syscon@f03e0400 {
+			compatible = "brcm,brcmstb-sdio-1-boot-main-ctl", "syscon";
+			reg = <0xf03e0400 0x4>;
+			linux,phandle = <0xa8>;
+			phandle = <0xa8>;
+		};
+
+		interrupt-controller@f040a700 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,bcm7120-l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf040a700 0x8>;
+			interrupt-controller;
+			interrupts = <0x0 0x45 0x0 0x0 0x43 0x0>;
+			interrupt-names = "upg_main", "upg_bsc";
+			brcm,int-map-mask = <0x638 0x1c0>;
+			brcm,int-fwd-mask = <0x7>;
+			linux,phandle = <0x7>;
+			phandle = <0x7>;
+		};
+
+		interrupt-controller@f0417380 {
+			#interrupt-cells = <0x1>;
+			compatible = "brcm,bcm7120-l2-intc";
+			interrupt-parent = <0x1>;
+			reg = <0xf0417380 0x8>;
+			interrupt-controller;
+			interrupts = <0x0 0x46 0x0 0x0 0x44 0x0 0x0 0x49 0x0>;
+			interrupt-names = "upg_main_aon", "upg_bsc_aon", "upg_spi";
+			brcm,int-map-mask = <0x167 0x18 0x80>;
+			brcm,int-fwd-mask = <0x0>;
+			brcm,irq-can-wake;
+			linux,phandle = <0x8>;
+			phandle = <0x8>;
+		};
+
+		watchdog@f040a7a8 {
+			clocks = <0x9c>;
+			compatible = "brcm,bcm7038-wdt";
+			reg = <0xf040a7a8 0x14>;
+		};
+
+		bsp@f032c800 {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "brcm,bsp-v2.1.0", "brcm,bsp";
+			reg = <0xf032c800 0x3800>;
+			ranges;
+		};
+
+		spi@f0416000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			clocks = <0x9c>;
+			compatible = "brcm,spi-brcmstb-mspi";
+			reg = <0xf0416000 0x180>;
+			reg-names = "mspi";
+			interrupts = <0x7>;
+			interrupt-parent = <0x8>;
+			interrupt-names = "mspi_done";
+		};
+
+		pwm@f0408000 {
+			#pwm-cells = <0x2>;
+			clocks = <0x9c>;
+			compatible = "brcm,bcm7038-pwm", "brcm,brcmstb-pwm";
+			reg = <0xf0408000 0x28>;
+		};
+
+		pwm@f0409000 {
+			#pwm-cells = <0x2>;
+			clocks = <0x9c>;
+			compatible = "brcm,bcm7038-pwm", "brcm,brcmstb-pwm";
+			reg = <0xf0409000 0x28>;
+		};
+	};
+
+	thermal-zones {
+
+		cpu-thermal {
+			polling-delay = <0x0>;
+			polling-delay-passive = <0x0>;
+			thermal-sensors = <0x9d>;
+
+			trips {
+
+				cpu-alert0 {
+					temperature = <0x17318>;
+					hysteresis = <0x2710>;
+					type = "passive";
+				};
+
+				cpu-alert1 {
+					temperature = <0x1adb0>;
+					hysteresis = <0x2710>;
+					type = "passive";
+				};
+
+				cpu-alert2 {
+					temperature = <0x1e848>;
+					hysteresis = <0x2710>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
+	s3 {
+		syscon-refs = <0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8>;
+	};
+};
diff --git a/arch/arm/configs/brcmstb_defconfig b/arch/arm/configs/brcmstb_defconfig
new file mode 100644
index 000000000000..2d9a25166a14
--- /dev/null
+++ b/arch/arm/configs/brcmstb_defconfig
@@ -0,0 +1,246 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
+CONFIG_HZ_1000=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_CMA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_KEXEC is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_BRCMSTB_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_CRAMFS=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=9
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_EEPROM_93CX6=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_BRCMSTB=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000E=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MPU3050=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_GSPCA=y
+# CONFIG_VGA_ARB is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_NEXUS_API=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_WKTMR=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FUSE_FS=y
+CONFIG_FHANDLE=y
+CONFIG_CGROUPS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_BRCMSTB_UART=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_BDC_UDC=y
+CONFIG_RTC_CLASS=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
diff --git a/arch/arm/configs/brcmstb_hardened_defconfig b/arch/arm/configs/brcmstb_hardened_defconfig
new file mode 100644
index 000000000000..33b535c3f9b0
--- /dev/null
+++ b/arch/arm/configs/brcmstb_hardened_defconfig
@@ -0,0 +1,182 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_PRINTK is not set
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_MODULES=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+# CONFIG_BRCM_MOCA is not set
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_CMA=y
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_BRIDGE=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=9
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_ARM_UNWIND is not set
+CONFIG_SECURITY_DMESG_RESTRICT=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/dm900_defconfig b/arch/arm/configs/dm900_defconfig
new file mode 100644
index 000000000000..fb1e4f78a8fd
--- /dev/null
+++ b/arch/arm/configs/dm900_defconfig
@@ -0,0 +1,4106 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.14.79-1.17 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="arm-linux-"
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION="-dm900"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_XZ is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_HOSTNAME="dm900"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_FHANDLE=y
+# CONFIG_AUDIT is not set
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+# CONFIG_TICK_CPU_ACCOUNTING is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_RCU_USER_QS is not set
+CONFIG_RCU_FANOUT=32
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_NOCB_CPU is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_MEMCG is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR is not set
+CONFIG_CC_STACKPROTECTOR_NONE=y
+# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
+# CONFIG_CC_STACKPROTECTOR_STRONG is not set
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AIX_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM_NODT is not set
+# CONFIG_ARCH_SHMOBILE_LEGACY is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP1 is not set
+
+#
+# Multiple platform selection
+#
+
+#
+# CPU Core family selection
+#
+# CONFIG_ARCH_MULTI_V6 is not set
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MULTI_V6_V7=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+# CONFIG_ARCH_MVEBU is not set
+CONFIG_ARCH_BCM=y
+
+#
+# Broadcom SoC Selection
+#
+# CONFIG_ARCH_BCM_MOBILE is not set
+CONFIG_ARCH_BRCMSTB=y
+# CONFIG_BCM3390A0 is not set
+# CONFIG_BCM3390B0 is not set
+# CONFIG_BCM7250B0 is not set
+# CONFIG_BCM7364A0 is not set
+# CONFIG_BCM7366C0 is not set
+# CONFIG_BCM74371A0 is not set
+CONFIG_BCM7439B0=y
+# CONFIG_BCM7445D0 is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+# CONFIG_MTD_NAND_BRCMSTB is not set
+CONFIG_BRCM_SDIO=y
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM9X0=y
+CONFIG_DREAMBOX_DM900=y
+# CONFIG_DREAMBOX_DM920 is not set
+CONFIG_BRCMSTB=y
+CONFIG_BCM7439=y
+CONFIG_BRCM_GENET_V4=y
+CONFIG_BRCM_GENET_VERSION=4
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN23=y
+CONFIG_BRCM_MOCA_VERS=0x2003
+CONFIG_BRCM_HAS_NAND_MINOR_1=y
+CONFIG_BRCM_HAS_NAND_MAJOR_7=y
+CONFIG_BRCMNAND_MAJOR_VERS=7
+CONFIG_BRCMNAND_MINOR_VERS=1
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_MSPI_64B_WORDS=y
+CONFIG_BRCM_USB_OHCI=y
+CONFIG_BRCM_USB_EHCI=y
+CONFIG_BRCM_USB_XHCI=y
+CONFIG_BRCM_USB_PHY=y
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_HI3xxx is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MSM_DT is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_OMAP3 is not set
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP5 is not set
+# CONFIG_SOC_AM33XX is not set
+# CONFIG_SOC_AM43XX is not set
+# CONFIG_SOC_DRA7XX is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_STI is not set
+# CONFIG_ARCH_SHMOBILE_MULTI is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_SIRF is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VIRT is not set
+# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_ZYNQ is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_LPAE=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_KUSER_HELPERS=y
+CONFIG_CACHE_B15_RAC=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_NR_BANKS=8
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_ARM_ERRATA_775420 is not set
+CONFIG_ARM_ERRATA_798181=y
+# CONFIG_ARM_ERRATA_773022 is not set
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+
+#
+# PCI host controller drivers
+#
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+# CONFIG_MCPM is not set
+# CONFIG_BIG_LITTLE is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ_FIXED=0
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_200 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_500 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+CONFIG_CMA_AREAS=7
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_SECCOMP=y
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_XEN is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_CMDLINE="bmem=640M@384M bmem=384M@2048M console=ttyS0,1000000 root=/dev/mmcblk0p2 rootwait rootfstype=ext4"
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_GENERIC_CPUFREQ_CPU0=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+CONFIG_ARM_BRCMSTB_CPUFREQ=y
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# ARM CPU Idle Drivers
+#
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_KERNEL_MODE_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_PM_SLEEP_DEBUG=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=m
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=m
+# CONFIG_IP_MROUTE is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_ZONES is not set
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=m
+CONFIG_NFT_EXTHDR=m
+CONFIG_NFT_META=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_RBTREE=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_COUNTER=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_NF_TABLES_IPV4=m
+CONFIG_NFT_CHAIN_ROUTE_IPV4=m
+CONFIG_NFT_CHAIN_NAT_IPV4=m
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NF_TABLES_ARP=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_NF_TABLES_IPV6=m
+CONFIG_NFT_CHAIN_ROUTE_IPV6=m
+CONFIG_NFT_CHAIN_NAT_IPV6=m
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_NF_TABLES_BRIDGE=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_OBJCNT is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_BRIDGE_VLAN_FILTERING is not set
+CONFIG_HAVE_NET_DSA=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_6LOWPAN_IPHC=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_FQ_CODEL is not set
+# CONFIG_NET_SCH_FQ is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_PIE is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_MMAP is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_NET_MPLS_GSO is not set
+# CONFIG_HSR is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+CONFIG_HAVE_BPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_CMA=y
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=12
+
+#
+# Bus devices
+#
+CONFIG_BRCMSTB_GISB_ARB=y
+# CONFIG_ARM_CCI is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_OF_SELFTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_MTD=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MG_DISK=m
+CONFIG_MG_DISK_RES=0
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085_I2C is not set
+# CONFIG_BMP085_SPI is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_IMX is not set
+CONFIG_SATA_BRCMSTB=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_RCAR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BCACHE=m
+# CONFIG_BCACHE_DEBUG is not set
+# CONFIG_BCACHE_CLOSURES_DEBUG is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+CONFIG_NET_DSA_BCM_SF2=y
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+CONFIG_SYSTEM_PORT=y
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_SH_ETH is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AT803X_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BCM531XX_PHY=y
+CONFIG_BCM7XXX_PHY=y
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+CONFIG_MDIO_UNIMAC=y
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+CONFIG_ATH_CARDS=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_WOW is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_CARL9170_HWRNG is not set
+# CONFIG_ATH6KL is not set
+CONFIG_AR5523=m
+CONFIG_WIL6210=m
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+# CONFIG_ATH10K_DEBUG is not set
+# CONFIG_ATH10K_DEBUGFS is not set
+# CONFIG_WCN36XX is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMSMAC is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL_CARDS=m
+CONFIG_RTL8192CE=m
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+# CONFIG_RTL8723AE is not set
+# CONFIG_RTL8188EE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+CONFIG_WL_TI=y
+CONFIG_WL1251=m
+# CONFIG_WL1251_SPI is not set
+# CONFIG_WL1251_SDIO is not set
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WILINK_PLATFORM_DATA=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_CW1200=m
+# CONFIG_CW1200_WLAN_SDIO is not set
+# CONFIG_CW1200_WLAN_SPI is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_AS5011 is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_GTCO=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_WACOM=m
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+CONFIG_TOUCHSCREEN_SUR40=m
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_GP2A is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_TILT_POLLED is not set
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+# CONFIG_INPUT_KXTJ9 is not set
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+CONFIG_INPUT_IMS_PCU=m
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_EM is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_SH_SCI is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_ATMEL is not set
+# CONFIG_HW_RANDOM_EXYNOS is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_PCA954x is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_BRCMSTB is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_OF_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers:
+#
+CONFIG_GPIO_BRCMSTB=y
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_EM is not set
+# CONFIG_GPIO_RCAR is not set
+# CONFIG_GPIO_SCH311X is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_VX855 is not set
+# CONFIG_GPIO_GRGPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_AMD8111 is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# LPC GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_GPIO_BCM_KONA is not set
+
+#
+# USB GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_BRCMSTB=y
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
+# CONFIG_THERMAL_EMULATION is not set
+# CONFIG_IMX_THERMAL is not set
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
+
+#
+# Texas Instruments thermal drivers
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=m
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ANATOP is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_V4L2=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_TTPCI_EEPROM=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+
+#
+# Media drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+CONFIG_LIRC=y
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_RC_DEVICES=y
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_TTUSBIR=m
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_IR_GPIO_CIR is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_VIDEO_CPIA2=m
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+CONFIG_VIDEO_USBTV=m
+
+#
+# Analog TV USB devices
+#
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_STK1160_COMMON=m
+CONFIG_VIDEO_STK1160_AC97=y
+CONFIG_VIDEO_STK1160=m
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=m
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+
+#
+# Supported MMC/SDIO adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+CONFIG_RADIO_ADAPTERS=y
+CONFIG_RADIO_TEA575X=m
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_RADIO_SI4713 is not set
+CONFIG_USB_MR800=m
+CONFIG_USB_DSBR=m
+# CONFIG_RADIO_MAXIRADIO is not set
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_USB_KEENE=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_MA901=m
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_RADIO_WL1273 is not set
+
+#
+# Texas Instruments WL128x FM driver (ST based)
+#
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+
+#
+# Media ancillary drivers (tuners, sensors, i2c, frontends)
+#
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_VIDEO_IR_I2C=y
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Audio/Video compression chips
+#
+
+#
+# Miscellaneous helper chips
+#
+
+#
+# Sensors used on soc_camera driver
+#
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_M88TS2022=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_R820T=m
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_M88DS3103=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_AF9033=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_EXYNOS_VIDEO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_LOGO is not set
+# CONFIG_FB_SSD1307 is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_HUION=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LENOVO_TPKBD=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=y
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_FUSBH200_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_ZTE=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_RIO500=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LED=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_IDMOUSE=m
+# CONFIG_USB_FTDI_ELAN is not set
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_EZUSB_FX2=m
+# CONFIG_USB_HSIC_USB3503 is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_USB_PHY is not set
+# CONFIG_USB_OTG_FSM is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_AM335X_PHY_USB is not set
+# CONFIG_SAMSUNG_USB2PHY is not set
+# CONFIG_SAMSUNG_USB3PHY is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_RCAR_PHY is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_BCM_KONA is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_USHC=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LP5562 is not set
+# CONFIG_LEDS_LP8501 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_PCA9685 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_OT200 is not set
+# CONFIG_LEDS_BLINKM is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_CPU is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+CONFIG_R8188EU=m
+CONFIG_88EU_AP_MODE=y
+CONFIG_88EU_P2P=y
+# CONFIG_R8821AE is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+# CONFIG_RTS5208 is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+# CONFIG_I2C_BCM2048 is not set
+# CONFIG_DVB_CXD2099 is not set
+# CONFIG_VIDEO_DT3155 is not set
+# CONFIG_VIDEO_GO7007 is not set
+CONFIG_USB_MSI3101=m
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+# CONFIG_LIRC_SERIAL is not set
+# CONFIG_LIRC_SIR is not set
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+# CONFIG_ANDROID_BINDER_IPC is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_LOGGER is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+CONFIG_SYNC=y
+CONFIG_SW_SYNC=y
+CONFIG_SW_SYNC_USER=y
+CONFIG_ION=y
+# CONFIG_ION_TEST is not set
+# CONFIG_ION_DUMMY is not set
+CONFIG_USB_WPAN_HCD=m
+CONFIG_WIMAX_GDM72XX=m
+# CONFIG_WIMAX_GDM72XX_QOS is not set
+# CONFIG_WIMAX_GDM72XX_K_MODE is not set
+# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set
+CONFIG_WIMAX_GDM72XX_USB=y
+# CONFIG_WIMAX_GDM72XX_SDIO is not set
+# CONFIG_WIMAX_GDM72XX_USB_PM is not set
+# CONFIG_LTE_GDM724X is not set
+CONFIG_NET_VENDOR_SILICOM=y
+# CONFIG_SBYPASS is not set
+# CONFIG_BPCTL is not set
+CONFIG_CED1401=m
+# CONFIG_DGRP is not set
+# CONFIG_LUSTRE_FS is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_DGNC is not set
+# CONFIG_DGAP is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+CONFIG_SOC_BRCMSTB=y
+
+#
+# Broadcom STB SoC drivers
+#
+CONFIG_BRCMSTB_IRQ0_STUB=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_PM=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_XPT_HASH=y
+# CONFIG_BRCMSTB_NEXUS_API is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_QCOM is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_OF=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+# CONFIG_IPACK_BUS is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_FMC is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_POWERCAP is not set
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+
+#
+# Caches
+#
+CONFIG_FSCACHE=m
+# CONFIG_FSCACHE_STATS is not set
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_HFSPLUS_FS_POSIX_ACL=y
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+# CONFIG_F2FS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+# CONFIG_CEPH_FSCACHE is not set
+# CONFIG_CEPH_FS_POSIX_ACL is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+CONFIG_CIFS_SMB2=y
+# CONFIG_CIFS_FSCACHE is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_DEBUG_KERNEL=y
+
+#
+# Memory Debugging
+#
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+
+#
+# Runtime Testing
+#
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_TEST_MODULE is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_PTDUMP is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_BCM_KONA_UART is not set
+CONFIG_DEBUG_BRCMSTB_UART=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_SEMIHOSTING is not set
+# CONFIG_DEBUG_LL_UART_8250 is not set
+# CONFIG_DEBUG_LL_UART_PL01X is not set
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+# CONFIG_DEBUG_UART_PL01X is not set
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0xf040a900
+CONFIG_DEBUG_UART_VIRT=0xfc40a900
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_8250_WORD=y
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UNCOMPRESS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_EARLY_PRINTK=y
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_DEBUG_SET_MODULE_RONX is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRCT10DIF=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=y
+CONFIG_CRC8=m
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_LRU_CACHE=m
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_FONT_SUPPORT=m
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/dm920_defconfig b/arch/arm/configs/dm920_defconfig
new file mode 100644
index 000000000000..6de7f48885b5
--- /dev/null
+++ b/arch/arm/configs/dm920_defconfig
@@ -0,0 +1,4106 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.14.79-1.17 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="arm-linux-"
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION="-dm900"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_XZ is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_HOSTNAME="dm900"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_FHANDLE=y
+# CONFIG_AUDIT is not set
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+# CONFIG_TICK_CPU_ACCOUNTING is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_RCU_USER_QS is not set
+CONFIG_RCU_FANOUT=32
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_NOCB_CPU is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_MEMCG is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR is not set
+CONFIG_CC_STACKPROTECTOR_NONE=y
+# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
+# CONFIG_CC_STACKPROTECTOR_STRONG is not set
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_CMDLINE_PARSER is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AIX_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM_NODT is not set
+# CONFIG_ARCH_SHMOBILE_LEGACY is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP1 is not set
+
+#
+# Multiple platform selection
+#
+
+#
+# CPU Core family selection
+#
+# CONFIG_ARCH_MULTI_V6 is not set
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MULTI_V6_V7=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+# CONFIG_ARCH_MVEBU is not set
+CONFIG_ARCH_BCM=y
+
+#
+# Broadcom SoC Selection
+#
+# CONFIG_ARCH_BCM_MOBILE is not set
+CONFIG_ARCH_BRCMSTB=y
+# CONFIG_BCM3390A0 is not set
+# CONFIG_BCM3390B0 is not set
+# CONFIG_BCM7250B0 is not set
+# CONFIG_BCM7364A0 is not set
+# CONFIG_BCM7366C0 is not set
+# CONFIG_BCM74371A0 is not set
+CONFIG_BCM7439B0=y
+# CONFIG_BCM7445D0 is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+# CONFIG_MTD_NAND_BRCMSTB is not set
+CONFIG_BRCM_SDIO=y
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM9X0=y
+# CONFIG_DREAMBOX_DM900 is not set
+CONFIG_DREAMBOX_DM920=y
+CONFIG_BRCMSTB=y
+CONFIG_BCM7439=y
+CONFIG_BRCM_GENET_V4=y
+CONFIG_BRCM_GENET_VERSION=4
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN23=y
+CONFIG_BRCM_MOCA_VERS=0x2003
+CONFIG_BRCM_HAS_NAND_MINOR_1=y
+CONFIG_BRCM_HAS_NAND_MAJOR_7=y
+CONFIG_BRCMNAND_MAJOR_VERS=7
+CONFIG_BRCMNAND_MINOR_VERS=1
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_MSPI_64B_WORDS=y
+CONFIG_BRCM_USB_OHCI=y
+CONFIG_BRCM_USB_EHCI=y
+CONFIG_BRCM_USB_XHCI=y
+CONFIG_BRCM_USB_PHY=y
+# CONFIG_ARCH_BERLIN is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_HI3xxx is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MSM_DT is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_OMAP3 is not set
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP5 is not set
+# CONFIG_SOC_AM33XX is not set
+# CONFIG_SOC_AM43XX is not set
+# CONFIG_SOC_DRA7XX is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_STI is not set
+# CONFIG_ARCH_SHMOBILE_MULTI is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_SIRF is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VIRT is not set
+# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_ZYNQ is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_LPAE=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_KUSER_HELPERS=y
+CONFIG_CACHE_B15_RAC=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_NR_BANKS=8
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_ARM_ERRATA_775420 is not set
+CONFIG_ARM_ERRATA_798181=y
+# CONFIG_ARM_ERRATA_773022 is not set
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+
+#
+# PCI host controller drivers
+#
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+CONFIG_PCIE_PME=y
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+# CONFIG_MCPM is not set
+# CONFIG_BIG_LITTLE is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ_FIXED=0
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_200 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_500 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_TRANSPARENT_HUGEPAGE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+CONFIG_CMA_AREAS=7
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_SECCOMP=y
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_XEN is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_CMDLINE="bmem=640M@384M bmem=384M@2048M console=ttyS0,1000000 root=/dev/mmcblk0p2 rootwait rootfstype=ext4"
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_GENERIC_CPUFREQ_CPU0=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+CONFIG_ARM_BRCMSTB_CPUFREQ=y
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# ARM CPU Idle Drivers
+#
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+# CONFIG_KERNEL_MODE_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+# CONFIG_PM_WAKELOCKS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_PM_SLEEP_DEBUG=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=m
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=m
+# CONFIG_IP_MROUTE is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_ZONES is not set
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=m
+CONFIG_NFT_EXTHDR=m
+CONFIG_NFT_META=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_RBTREE=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_COUNTER=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_NF_TABLES_IPV4=m
+CONFIG_NFT_CHAIN_ROUTE_IPV4=m
+CONFIG_NFT_CHAIN_NAT_IPV4=m
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NF_TABLES_ARP=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_NF_TABLES_IPV6=m
+CONFIG_NFT_CHAIN_ROUTE_IPV6=m
+CONFIG_NFT_CHAIN_NAT_IPV6=m
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_NF_TABLES_BRIDGE=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_OBJCNT is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_BRIDGE_VLAN_FILTERING is not set
+CONFIG_HAVE_NET_DSA=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_6LOWPAN_IPHC=y
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_FQ_CODEL is not set
+# CONFIG_NET_SCH_FQ is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_PIE is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_MMAP is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_NET_MPLS_GSO is not set
+# CONFIG_HSR is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+CONFIG_HAVE_BPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_CMA=y
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=12
+
+#
+# Bus devices
+#
+CONFIG_BRCMSTB_GISB_ARB=y
+# CONFIG_ARM_CCI is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_OF_SELFTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_MTD=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
+# CONFIG_DRBD_FAULT_INJECTION is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+CONFIG_MG_DISK=m
+CONFIG_MG_DISK_RES=0
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085_I2C is not set
+# CONFIG_BMP085_SPI is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_AHCI_IMX is not set
+CONFIG_SATA_BRCMSTB=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_RCAR is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BCACHE=m
+# CONFIG_BCACHE_DEBUG is not set
+# CONFIG_BCACHE_CLOSURES_DEBUG is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+CONFIG_NET_DSA_BCM_SF2=y
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+CONFIG_SYSTEM_PORT=y
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_SH_ETH is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AT803X_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BCM531XX_PHY=y
+CONFIG_BCM7XXX_PHY=y
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+CONFIG_MDIO_UNIMAC=y
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+CONFIG_ATH_CARDS=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_WOW is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_CARL9170_HWRNG is not set
+# CONFIG_ATH6KL is not set
+CONFIG_AR5523=m
+CONFIG_WIL6210=m
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+# CONFIG_ATH10K_DEBUG is not set
+# CONFIG_ATH10K_DEBUGFS is not set
+# CONFIG_WCN36XX is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMSMAC is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL_CARDS=m
+CONFIG_RTL8192CE=m
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+# CONFIG_RTL8723AE is not set
+# CONFIG_RTL8188EE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+CONFIG_WL_TI=y
+CONFIG_WL1251=m
+# CONFIG_WL1251_SPI is not set
+# CONFIG_WL1251_SDIO is not set
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WILINK_PLATFORM_DATA=y
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_CW1200=m
+# CONFIG_CW1200_WLAN_SDIO is not set
+# CONFIG_CW1200_WLAN_SPI is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_AS5011 is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_GTCO=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_WACOM=m
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+CONFIG_TOUCHSCREEN_SUR40=m
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_ZFORCE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_GP2A is not set
+# CONFIG_INPUT_GPIO_BEEPER is not set
+# CONFIG_INPUT_GPIO_TILT_POLLED is not set
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+# CONFIG_INPUT_KXTJ9 is not set
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+CONFIG_INPUT_IMS_PCU=m
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_EM is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_SH_SCI is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_ST_ASC is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_ATMEL is not set
+# CONFIG_HW_RANDOM_EXYNOS is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_PCA954x is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_BRCMSTB is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_OF_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers:
+#
+CONFIG_GPIO_BRCMSTB=y
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_EM is not set
+# CONFIG_GPIO_RCAR is not set
+# CONFIG_GPIO_SCH311X is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_VX855 is not set
+# CONFIG_GPIO_GRGPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_AMD8111 is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# LPC GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_GPIO_BCM_KONA is not set
+
+#
+# USB GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_BRCMSTB=y
+# CONFIG_POWER_RESET_GPIO is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
+# CONFIG_THERMAL_EMULATION is not set
+# CONFIG_IMX_THERMAL is not set
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
+
+#
+# Texas Instruments thermal drivers
+#
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=m
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_MFD_AS3722 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_VEXPRESS_CONFIG is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_ANATOP is not set
+# CONFIG_REGULATOR_DA9210 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_PFUZE100 is not set
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_RC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_V4L2=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_TTPCI_EEPROM=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+
+#
+# Media drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_RC_MAP=m
+CONFIG_RC_DECODERS=y
+CONFIG_LIRC=y
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_RC_DEVICES=y
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_TTUSBIR=m
+# CONFIG_RC_LOOPBACK is not set
+# CONFIG_IR_GPIO_CIR is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_GL860=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_VIDEO_CPIA2=m
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+CONFIG_VIDEO_USBTV=m
+
+#
+# Analog TV USB devices
+#
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_VIDEO_STK1160_COMMON=m
+CONFIG_VIDEO_STK1160_AC97=y
+CONFIG_VIDEO_STK1160=m
+
+#
+# Analog/digital TV USB devices
+#
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+
+#
+# Digital TV USB devices
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_USB_DRV=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX_RC=m
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+
+#
+# Supported MMC/SDIO adapters
+#
+# CONFIG_SMS_SDIO_DRV is not set
+CONFIG_RADIO_ADAPTERS=y
+CONFIG_RADIO_TEA575X=m
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_RADIO_SI4713 is not set
+CONFIG_USB_MR800=m
+CONFIG_USB_DSBR=m
+# CONFIG_RADIO_MAXIRADIO is not set
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_USB_KEENE=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_MA901=m
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_RADIO_WL1273 is not set
+
+#
+# Texas Instruments WL128x FM driver (ST based)
+#
+CONFIG_MEDIA_COMMON_OPTIONS=y
+
+#
+# common driver options
+#
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+
+#
+# Media ancillary drivers (tuners, sensors, i2c, frontends)
+#
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_VIDEO_IR_I2C=y
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Audio/Video compression chips
+#
+
+#
+# Miscellaneous helper chips
+#
+
+#
+# Sensors used on soc_camera driver
+#
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_M88TS2022=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER_R820T=m
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_M88DS3103=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_AF9033=m
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_EXYNOS_VIDEO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_LOGO is not set
+# CONFIG_FB_SSD1307 is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_HIFACE=m
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+
+#
+# HID support
+#
+CONFIG_HID=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_HUION=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LENOVO_TPKBD=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=y
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_FUSBH200_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_CHIPIDEA is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_ZTE=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_RIO500=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LED=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_IDMOUSE=m
+# CONFIG_USB_FTDI_ELAN is not set
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_EZUSB_FX2=m
+# CONFIG_USB_HSIC_USB3503 is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_USB_PHY is not set
+# CONFIG_USB_OTG_FSM is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_AM335X_PHY_USB is not set
+# CONFIG_SAMSUNG_USB2PHY is not set
+# CONFIG_SAMSUNG_USB3PHY is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_RCAR_PHY is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_BCM_KONA is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_USHC=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LP5562 is not set
+# CONFIG_LEDS_LP8501 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_PCA9685 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_OT200 is not set
+# CONFIG_LEDS_BLINKM is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_CPU is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+CONFIG_R8188EU=m
+CONFIG_88EU_AP_MODE=y
+CONFIG_88EU_P2P=y
+# CONFIG_R8821AE is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+# CONFIG_RTS5208 is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+# CONFIG_I2C_BCM2048 is not set
+# CONFIG_DVB_CXD2099 is not set
+# CONFIG_VIDEO_DT3155 is not set
+# CONFIG_VIDEO_GO7007 is not set
+CONFIG_USB_MSI3101=m
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+# CONFIG_LIRC_SERIAL is not set
+# CONFIG_LIRC_SIR is not set
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+# CONFIG_ANDROID_BINDER_IPC is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_LOGGER is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+CONFIG_SYNC=y
+CONFIG_SW_SYNC=y
+CONFIG_SW_SYNC_USER=y
+CONFIG_ION=y
+# CONFIG_ION_TEST is not set
+# CONFIG_ION_DUMMY is not set
+CONFIG_USB_WPAN_HCD=m
+CONFIG_WIMAX_GDM72XX=m
+# CONFIG_WIMAX_GDM72XX_QOS is not set
+# CONFIG_WIMAX_GDM72XX_K_MODE is not set
+# CONFIG_WIMAX_GDM72XX_WIMAX2 is not set
+CONFIG_WIMAX_GDM72XX_USB=y
+# CONFIG_WIMAX_GDM72XX_SDIO is not set
+# CONFIG_WIMAX_GDM72XX_USB_PM is not set
+# CONFIG_LTE_GDM724X is not set
+CONFIG_NET_VENDOR_SILICOM=y
+# CONFIG_SBYPASS is not set
+# CONFIG_BPCTL is not set
+CONFIG_CED1401=m
+# CONFIG_DGRP is not set
+# CONFIG_LUSTRE_FS is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_DGNC is not set
+# CONFIG_DGAP is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+CONFIG_SOC_BRCMSTB=y
+
+#
+# Broadcom STB SoC drivers
+#
+CONFIG_BRCMSTB_IRQ0_STUB=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_PM=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_XPT_HASH=y
+# CONFIG_BRCMSTB_NEXUS_API is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI570 is not set
+# CONFIG_COMMON_CLK_QCOM is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_OF=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+# CONFIG_IPACK_BUS is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_FMC is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_POWERCAP is not set
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+
+#
+# Caches
+#
+CONFIG_FSCACHE=m
+# CONFIG_FSCACHE_STATS is not set
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_HFSPLUS_FS_POSIX_ACL=y
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+# CONFIG_F2FS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+# CONFIG_NFS_V4_1_MIGRATION is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+# CONFIG_CEPH_FSCACHE is not set
+# CONFIG_CEPH_FS_POSIX_ACL is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+CONFIG_CIFS_SMB2=y
+# CONFIG_CIFS_FSCACHE is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_DEBUG_KERNEL=y
+
+#
+# Memory Debugging
+#
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+
+#
+# Runtime Testing
+#
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_PERCPU_TEST is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_TEST_MODULE is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_PTDUMP is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_BCM_KONA_UART is not set
+CONFIG_DEBUG_BRCMSTB_UART=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_SEMIHOSTING is not set
+# CONFIG_DEBUG_LL_UART_8250 is not set
+# CONFIG_DEBUG_LL_UART_PL01X is not set
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+# CONFIG_DEBUG_UART_PL01X is not set
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0xf040a900
+CONFIG_DEBUG_UART_VIRT=0xfc40a900
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_8250_WORD=y
+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
+CONFIG_DEBUG_UNCOMPRESS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_EARLY_PRINTK=y
+# CONFIG_PID_IN_CONTEXTIDR is not set
+# CONFIG_DEBUG_SET_MODULE_RONX is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRCT10DIF=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZ4HC=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=y
+CONFIG_CRC8=m
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_LRU_CACHE=m
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_FONT_SUPPORT=m
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index cf4823bc111d..1a58a453cec9 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -12,6 +12,7 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
 CONFIG_MACH_BERLIN_BG2CD=y
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 5c2285160575..a087318bbaff 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -23,6 +23,7 @@
 #include <asm/ptrace.h>
 #include <asm/domain.h>
 #include <asm/opcodes-virt.h>
+#include <asm/asm-offsets.h>
 
 #define IOMEM(x)	(x)
 
@@ -174,6 +175,47 @@
 	restore_irqs_notrace \oldcpsr
 	.endm
 
+/*
+ * Get current thread_info.
+ */
+	.macro	get_thread_info, rd
+ ARM(	mov	\rd, sp, lsr #13	)
+ THUMB(	mov	\rd, sp			)
+ THUMB(	lsr	\rd, \rd, #13		)
+	mov	\rd, \rd, lsl #13
+	.endm
+
+/*
+ * Increment/decrement the preempt count.
+ */
+#ifdef CONFIG_PREEMPT_COUNT
+	.macro	inc_preempt_count, ti, tmp
+	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
+	add	\tmp, \tmp, #1			@ increment it
+	str	\tmp, [\ti, #TI_PREEMPT]
+	.endm
+
+	.macro	dec_preempt_count, ti, tmp
+	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
+	sub	\tmp, \tmp, #1			@ decrement it
+	str	\tmp, [\ti, #TI_PREEMPT]
+	.endm
+
+	.macro	dec_preempt_count_ti, ti, tmp
+	get_thread_info \ti
+	dec_preempt_count \ti, \tmp
+	.endm
+#else
+	.macro	inc_preempt_count, ti, tmp
+	.endm
+
+	.macro	dec_preempt_count, ti, tmp
+	.endm
+
+	.macro	dec_preempt_count_ti, ti, tmp
+	.endm
+#endif
+
 #define USER(x...)				\
 9999:	x;					\
 	.pushsection __ex_table,"a";		\
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index b274bde24905..cf81d398ea73 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -5,8 +5,6 @@
 #include <linux/types.h>
 #include <asm/opcodes.h>
 
-#ifdef CONFIG_BUG
-
 /*
  * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling.
  * We need to be careful not to conflict with those used by other modules and
@@ -56,7 +54,6 @@ do {								\
 #endif  /* CONFIG_DEBUG_BUGVERBOSE */
 
 #define HAVE_ARCH_BUG
-#endif  /* CONFIG_BUG */
 
 #include <asm-generic/bug.h>
 
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 8b8b61685a34..2d9b49263c16 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -199,7 +199,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
  */
 #if (defined(CONFIG_CPU_V7) && \
      (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
-	defined(CONFIG_SMP_ON_UP)
+	defined(CONFIG_SMP_ON_UP) || defined(CONFIG_CACHE_B15_RAC)
 #define __flush_icache_preferred	__cpuc_flush_icache_all
 #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
 #define __flush_icache_preferred	__flush_icache_all_v7_smp
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index f89515adac60..2bb8cac28b9e 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -45,7 +45,7 @@ void *return_address(unsigned int);
 
 #else
 
-extern inline void *return_address(unsigned int level)
+static inline void *return_address(unsigned int level)
 {
 	return NULL;
 }
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c81adc08b3fb..11f33b5f9284 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,6 +117,10 @@
 # endif
 #endif
 
+#if defined(CONFIG_CACHE_B15_RAC)
+# define MULTI_CACHE 1
+#endif
+
 #if defined(CONFIG_CPU_V7M)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
@@ -130,22 +134,22 @@
 #endif
 
 #ifndef __ASSEMBLER__
-extern inline void nop_flush_icache_all(void) { }
-extern inline void nop_flush_kern_cache_all(void) { }
-extern inline void nop_flush_kern_cache_louis(void) { }
-extern inline void nop_flush_user_cache_all(void) { }
-extern inline void nop_flush_user_cache_range(unsigned long a,
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_kern_cache_louis(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a,
 		unsigned long b, unsigned int c) { }
 
-extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
-extern inline int nop_coherent_user_range(unsigned long a,
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline int nop_coherent_user_range(unsigned long a,
 		unsigned long b) { return 0; }
-extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
 
-extern inline void nop_dma_flush_range(const void *a, const void *b) { }
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
 
-extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
-extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
 #endif
 
 #ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index fe3ea776dc34..3e9ded5db20e 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
-#define NR_IPI	8
+#define NR_IPI	16
 
 typedef struct {
 	unsigned int __softirq_pending;
diff --git a/arch/arm/include/asm/hardware/cache-b15-rac.h b/arch/arm/include/asm/hardware/cache-b15-rac.h
new file mode 100644
index 000000000000..76b888f53f90
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-b15-rac.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+
+#ifndef __ASSEMBLY__
+
+void b15_flush_kern_cache_all(void);
+void b15_flush_kern_cache_louis(void);
+void b15_flush_icache_all(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 4157aec4e307..3044930c030c 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -115,9 +115,21 @@ struct smp_operations {
 #endif
 };
 
+struct of_cpu_method {
+	const char *method;
+	struct smp_operations *ops;
+};
+
+#define CPU_METHOD_OF_DECLARE(name, _method, _ops)			\
+	static const struct of_cpu_method __cpu_method_of_table_##name	\
+		__used __section(__cpu_method_of_table)			\
+		= { .method = _method, .ops = _ops }
 /*
  * set platform specific SMP operations
  */
 extern void smp_set_ops(struct smp_operations *);
 
+extern int set_ipi_handler(int ipinr, void *handler, char *desc);
+extern void clear_ipi_handler(int ipinr);
+
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/sparsemem.h b/arch/arm/include/asm/sparsemem.h
index 00098615c6f0..73e5e8513751 100644
--- a/arch/arm/include/asm/sparsemem.h
+++ b/arch/arm/include/asm/sparsemem.h
@@ -15,10 +15,11 @@
  * Eg, if you have 2 banks of up to 64MB at 0x80000000, 0x84000000,
  * then MAX_PHYSMEM_BITS is 32, SECTION_SIZE_BITS is 26.
  *
- * Define these in your mach/memory.h.
+ * These can be overridden in your mach/memory.h.
  */
-#if !defined(SECTION_SIZE_BITS) || !defined(MAX_PHYSMEM_BITS)
-#error Sparsemem is not supported on this platform
+#if !defined(MAX_PHYSMEM_BITS) || !defined(SECTION_SIZE_BITS)
+#define MAX_PHYSMEM_BITS	36
+#define SECTION_SIZE_BITS	28
 #endif
 
 #endif
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index f751714d52c1..a5111eab7269 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -18,6 +18,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/smp.h>
 
 #include <asm/cputype.h>
 #include <asm/setup.h>
@@ -36,6 +37,33 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 	return memblock_virt_alloc(size, align);
 }
 
+static void __init relocate_dtb(void)
+{
+	u64 i;
+	phys_addr_t phys_start, phys_end, init_phys;
+	int nid;
+
+	/*
+	 * See if we can move the DTB somewhere below where it is currently.
+	 */
+	for_each_free_mem_range(i, NUMA_NO_NODE, &phys_start, &phys_end, &nid) {
+		u32 dtb_size = be32_to_cpu(initial_boot_params->totalsize);
+		void *virt_new_dtb;
+
+		if ((phys_end - phys_start) < dtb_size)
+			continue;
+
+		virt_new_dtb = (void *)__phys_to_virt(phys_start);
+		init_phys = virt_to_phys(initial_boot_params);
+		pr_info("moving dtb from %pa to %pa\n",
+			&init_phys, &phys_start);
+		memmove(virt_new_dtb, initial_boot_params, dtb_size);
+		initial_boot_params = virt_new_dtb;
+
+		return;
+	}
+}
+
 void __init arm_dt_memblock_reserve(void)
 {
 	u64 *reserve_map, base, size;
@@ -43,6 +71,8 @@ void __init arm_dt_memblock_reserve(void)
 	if (!initial_boot_params)
 		return;
 
+	relocate_dtb();
+
 	/* Reserve the dtb region */
 	memblock_reserve(virt_to_phys(initial_boot_params),
 			 be32_to_cpu(initial_boot_params->totalsize));
@@ -63,6 +93,34 @@ void __init arm_dt_memblock_reserve(void)
 	}
 }
 
+#ifdef CONFIG_SMP
+extern struct of_cpu_method __cpu_method_of_table_begin[];
+extern struct of_cpu_method __cpu_method_of_table_end[];
+
+static int __init set_smp_ops_by_method(struct device_node *node)
+{
+	const char *method;
+	struct of_cpu_method *m = __cpu_method_of_table_begin;
+
+	if (of_property_read_string(node, "enable-method", &method))
+		return 0;
+
+	for (; m < __cpu_method_of_table_end; m++)
+		if (!strcmp(m->method, method)) {
+			smp_set_ops(m->ops);
+			return 1;
+		}
+
+	return 0;
+}
+#else
+static inline int set_smp_ops_by_method(struct device_node *node)
+{
+	return 1;
+}
+#endif
+
+
 /*
  * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
  * and builds the cpu logical map array containing MPIDR values related to
@@ -79,6 +137,7 @@ void __init arm_dt_init_cpu_maps(void)
 	 * read as 0.
 	 */
 	struct device_node *cpu, *cpus;
+	int found_method = 0;
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
@@ -150,8 +209,18 @@ void __init arm_dt_init_cpu_maps(void)
 		}
 
 		tmp_map[i] = hwid;
+
+		if (!found_method)
+			found_method = set_smp_ops_by_method(cpu);
 	}
 
+	/*
+	 * Fallback to an enable-method in the cpus node if nothing found in
+	 * a cpu node.
+	 */
+	if (!found_method)
+		set_smp_ops_by_method(cpus);
+
 	if (!bootcpu_valid) {
 		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
 		return;
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 1879e8dd2acc..5fc897cf409b 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -413,6 +413,11 @@ __und_usr:
 	@
 	adr	r9, BSYM(ret_from_exception)
 
+	@ IRQs must be enabled before attempting to read the instruction from
+	@ user space since that could cause a page/translation fault if the
+	@ page table was modified by another CPU.
+	enable_irq
+
 	tst	r3, #PSR_T_BIT			@ Thumb mode?
 	bne	__und_usr_thumb
 	sub	r4, r2, #4			@ ARM instr at LR - 4
@@ -517,7 +522,7 @@ ENDPROC(__und_usr)
  *  r9  = normal "successful" return address
  *  r10 = this threads thread_info structure
  *  lr  = unrecognised instruction return address
- * IRQs disabled, FIQs enabled.
+ * IRQs enabled, FIQs enabled.
  */
 	@
 	@ Fall-through from Thumb-2 __und_usr
@@ -624,7 +629,6 @@ call_fpe:
 #endif
 
 do_fpe:
-	enable_irq
 	ldr	r4, .LCfp
 	add	r10, r10, #TI_FPSTATE		@ r10 = workspace
 	ldr	pc, [r4]			@ Call FP module USR entry point
@@ -652,8 +656,7 @@ __und_usr_fault_32:
 	b	1f
 __und_usr_fault_16:
 	mov	r1, #2
-1:	enable_irq
-	mov	r0, sp
+1:	mov	r0, sp
 	adr	lr, BSYM(ret_from_exception)
 	b	__und_fault
 ENDPROC(__und_usr_fault_32)
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 88c6babeb0b5..efb208de75ec 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -240,11 +240,6 @@
 	movs	pc, lr				@ return & move spsr_svc into cpsr
 	.endm
 
-	.macro	get_thread_info, rd
-	mov	\rd, sp, lsr #13
-	mov	\rd, \rd, lsl #13
-	.endm
-
 	@
 	@ 32-bit wide "mov pc, reg"
 	@
@@ -310,12 +305,6 @@
 	.endm
 #endif	/* ifdef CONFIG_CPU_V7M / else */
 
-	.macro	get_thread_info, rd
-	mov	\rd, sp
-	lsr	\rd, \rd, #13
-	mov	\rd, \rd, lsl #13
-	.endm
-
 	@
 	@ 32-bit wide "mov pc, reg"
 	@
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f5f381d91556..2b3519ce0748 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -231,6 +231,10 @@ __create_page_tables:
 	ldr	r6, =(_end - 1)
 	orr	r3, r8, r7
 	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
+#ifdef CONFIG_BRCMSTB
+	/* map a 1MB section after the kernel in case the DTB is copied there */
+	add	r6, #4
+#endif
 1:	str	r3, [r0], #1 << PMD_ORDER
 	add	r3, r3, #1 << SECTION_SHIFT
 	cmp	r0, r6
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index a08783823b32..4bb029ea8917 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -18,6 +18,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 
 #if defined(CONFIG_CPU_PJ4)
 #define PJ4(code...)		code
@@ -61,17 +62,18 @@
  * r9  = ret_from_exception
  * lr  = undefined instr exit
  *
- * called from prefetch exception handler with interrupts disabled
+ * called from prefetch exception handler with interrupts enabled
  */
 
 ENTRY(iwmmxt_task_enable)
+	inc_preempt_count r10, r3
 
 	XSC(mrc	p15, 0, r2, c15, c1, 0)
 	PJ4(mrc p15, 0, r2, c1, c0, 2)
 	@ CP0 and CP1 accessible?
 	XSC(tst	r2, #0x3)
 	PJ4(tst	r2, #0xf)
-	movne	pc, lr				@ if so no business here
+	bne	4f				@ if so no business here
 	@ enable access to CP0 and CP1
 	XSC(orr	r2, r2, #0x3)
 	XSC(mcr	p15, 0, r2, c15, c1, 0)
@@ -132,7 +134,7 @@ concan_dump:
 	wstrd	wR15, [r1, #MMX_WR15]
 
 2:	teq	r0, #0				@ anything to load?
-	moveq	pc, lr
+	beq	3f
 
 concan_load:
 
@@ -165,8 +167,14 @@ concan_load:
 	@ clear CUP/MUP (only if r1 != 0)
 	teq	r1, #0
 	mov 	r2, #0
-	moveq	pc, lr
+	beq	3f
 	tmcr	wCon, r2
+
+3:
+#ifdef CONFIG_PREEMPT_COUNT
+	get_thread_info r10
+#endif
+4:	dec_preempt_count r10, r3
 	mov	pc, lr
 
 /*
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
index fafedd86885d..98ea4b7eb406 100644
--- a/arch/arm/kernel/return_address.c
+++ b/arch/arm/kernel/return_address.c
@@ -59,15 +59,6 @@ void *return_address(unsigned int level)
 
 #else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */
 
-#if defined(CONFIG_ARM_UNWIND)
-#warning "TODO: return_address should use unwind tables"
-#endif
-
-void *return_address(unsigned int level)
-{
-	return NULL;
-}
-
 #endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */
 
 EXPORT_SYMBOL_GPL(return_address);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8cd3724714fe..e27e029da955 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -470,30 +470,52 @@ void arch_irq_work_raise(void)
 }
 #endif
 
-static const char *ipi_types[NR_IPI] = {
-#define S(x,s)	[x] = s
-	S(IPI_WAKEUP, "CPU wakeup interrupts"),
-	S(IPI_TIMER, "Timer broadcast interrupts"),
-	S(IPI_RESCHEDULE, "Rescheduling interrupts"),
-	S(IPI_CALL_FUNC, "Function call interrupts"),
-	S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
-	S(IPI_CPU_STOP, "CPU stop interrupts"),
-	S(IPI_IRQ_WORK, "IRQ work interrupts"),
-	S(IPI_COMPLETION, "completion interrupts"),
+struct ipi {
+	const char *desc;
+	void (*handler)(void);
 };
 
+#define IPI_DESC_STRING_IPI_WAKEUP "CPU wakeup interrupts"
+#define IPI_DESC_STRING_IPI_TIMER "Timer broadcast interrupts"
+#define IPI_DESC_STRING_IPI_RESCHEDULE "Rescheduling interrupts"
+#define IPI_DESC_STRING_IPI_CALL_FUNC "Function call interrupts"
+#define IPI_DESC_STRING_IPI_CALL_FUNC_SINGLE "Single function call interrupts"
+#define IPI_DESC_STRING_IPI_CPU_STOP "CPU stop interrupts"
+#define IPI_DESC_STRING_IPI_IRQ_WORK "IRQ work interrupts"
+#define IPI_DESC_STRING_IPI_COMPLETION "completion interrupts"
+
+#define IPI_DESC_STR(x) IPI_DESC_STRING_ ## x
+
+static struct ipi ipi_types[NR_IPI] = {
+#define S(x, f)	[x].desc = IPI_DESC_STR(x), [x].handler = f
+	S(IPI_WAKEUP, NULL),
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+	S(IPI_TIMER, NULL),
+#endif
+	S(IPI_RESCHEDULE, NULL),
+	S(IPI_CALL_FUNC, NULL),
+	S(IPI_CALL_FUNC_SINGLE, NULL),
+	S(IPI_CPU_STOP, NULL),
+#ifdef CONFIG_IRQ_WORK
+	S(IPI_IRQ_WORK, NULL),
+#endif
+	S(IPI_COMPLETION, NULL),
+};
+    
 void show_ipi_list(struct seq_file *p, int prec)
 {
 	unsigned int cpu, i;
 
 	for (i = 0; i < NR_IPI; i++) {
-		seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
+		if (ipi_types[i].desc) {
+			seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
 
-		for_each_online_cpu(cpu)
-			seq_printf(p, "%10u ",
-				   __get_irq_stat(cpu, ipi_irqs[i]));
+			for_each_online_cpu(cpu)
+				seq_printf(p, "%10u ",
+					   __get_irq_stat(cpu, ipi_irqs[i]));
 
-		seq_printf(p, " %s\n", ipi_types[i]);
+			seq_printf(p, " %s\n", ipi_types[i].desc);
+		}
 	}
 }
 
@@ -617,13 +639,50 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
 		break;
 
 	default:
-		printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
-		       cpu, ipinr);
+		if (ipi_types[ipinr].handler) {
+			irq_enter();
+			(*ipi_types[ipinr].handler)();
+			irq_exit();
+		} else
+			pr_crit("CPU%u: Unknown IPI message 0x%x\n",
+				cpu, ipinr);
 		break;
 	}
 	set_irq_regs(old_regs);
 }
 
+/*
+ * set_ipi_handler:
+ * Interface provided for a kernel module to specify an IPI handler function.
+ */
+int set_ipi_handler(int ipinr, void *handler, char *desc)
+{
+	unsigned int cpu = smp_processor_id();
+
+	if (ipi_types[ipinr].handler) {
+		pr_crit("CPU%u: IPI handler 0x%x already registered to %pf\n",
+			cpu, ipinr, ipi_types[ipinr].handler);
+		return -1;
+	}
+
+	ipi_types[ipinr].handler = handler;
+	ipi_types[ipinr].desc = desc;
+
+	return 0;
+}
+EXPORT_SYMBOL(set_ipi_handler);
+
+/*
+ * clear_ipi_handler:
+ * Interface provided for a kernel module to clear an IPI handler function.
+ */
+void clear_ipi_handler(int ipinr)
+{
+	ipi_types[ipinr].handler = NULL;
+	ipi_types[ipinr].desc = NULL;
+}
+EXPORT_SYMBOL(clear_ipi_handler);
+
 void smp_send_reschedule(int cpu)
 {
 	smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 95d063620b76..2e72be4f623e 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -92,15 +92,19 @@ void erratum_a15_798181_init(void)
 	unsigned int midr = read_cpuid_id();
 	unsigned int revidr = read_cpuid(CPUID_REVIDR);
 
-	/* Cortex-A15 r0p0..r3p2 w/o ECO fix affected */
-	if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2 ||
-	    (revidr & 0x210) == 0x210) {
-		return;
-	}
-	if (revidr & 0x10)
-		erratum_a15_798181_handler = erratum_a15_798181_partial;
-	else
+	/* Brahma-B15 r0p0..r0p2 affected
+	 * Cortex-A15 r0p0..r3p2 w/o ECO fix affected */
+	if ((midr & 0xff0ffff0) == 0x420f00f0 && midr <= 0x420f00f2)
 		erratum_a15_798181_handler = erratum_a15_798181_broadcast;
+	else if ((midr & 0xff0ffff0) == 0x410fc0f0 && midr <= 0x413fc0f2 &&
+		 (revidr & 0x210) != 0x210) {
+		if (revidr & 0x10)
+			erratum_a15_798181_handler =
+				erratum_a15_798181_partial;
+		else
+			erratum_a15_798181_handler =
+				erratum_a15_798181_broadcast;
+	}
 }
 #endif
 
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index b1aa6a9b3bd1..600bb791dc06 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -32,6 +32,389 @@ config ARCH_BCM_MOBILE
 	  BCM11130, BCM11140, BCM11351, BCM28145 and
 	  BCM28155 variants.
 
+config ARCH_BRCMSTB
+	bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+	depends on MMU
+	select ARM_GIC
+	select MIGHT_HAVE_PCI
+	select HAVE_SMP
+	select HAVE_ARM_ARCH_TIMER
+	select POWER_RESET_BRCMSTB
+	select BRCMSTB
+	select ARCH_HAS_OPP
+	select ARCH_HAS_CPUFREQ
+	select PM_OPP if PM
+	select ARM_ERRATA_798181 if SMP
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+	select GENERIC_IRQ_CHIP
+	select BRCMSTB_GISB_ARB
+	select SOC_BRCMSTB
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select SOC_BUS
+	select BCM7120_L2_IRQ if !DREAMBOX_DM9X0
+	help
+	  Say Y if you intend to run the kernel on a Broadcom ARM-based STB
+	  chipset.
+
+	  This enables support for Broadcom ARM-based set-top box chipsets,
+	  including the 7445 family of chips.
+
 endmenu
 
 endif
+
+choice
+	prompt "Chipset selection"
+	depends on BRCMSTB
+	help
+	  Select the Broadcom STB chipset you are building for.
+
+config BCM3390A0
+	bool "3390 Ax"
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+
+config BCM3390B0
+	bool "3390 Bx"
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN24
+	select BRCM_MSPI_64B_WORDS
+
+config BCM7250B0
+	bool "7250 Bx"
+	select BCM7250
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7364A0
+	bool "7364 Ax"
+	select BCM7364
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7366C0
+	bool "7366 Cx"
+	select BCM7366
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM74371A0
+	bool "74371 Ax"
+	select BCM74371
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+
+config BCM7439B0
+	bool "7439 Bx"
+	select BCM7439
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7445D0
+	bool "7445 Dx"
+	select BCM7445
+	select BRCM_GENET_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+endchoice
+
+config SPI_BRCMSTB
+	tristate "Broadcom HIF SPI controller support"
+	default y
+	depends on BRCMSTB
+	help
+	  Say Y to enable support for SPI (serial) flash devices.
+
+config BCMGENET
+	tristate "Broadcom STB 10/100/1000 MAC/PHY support"
+	depends on ETHERNET && BRCMSTB
+	default y
+	select CRC32
+	select MII
+	select PHYLIB
+	select FIXED_PHY
+	select BCM7XXX_PHY
+	select BCM531XX_PHY
+	help
+	  Say Y to support the internal 10/100/1000 GENET MAC/PHY on
+	  Broadcom set-top chips.  This driver also supports the datapath
+	  for the onchip MoCA transceiver.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_MOCA
+	tristate "Broadcom MoCA character driver"
+	depends on BRCMSTB && (BRCM_HAS_GENET || BRCM_HAS_MOCA_20_GEN21 || \
+		BRCM_HAS_MOCA_20_GEN22 || BRCM_HAS_MOCA_20_GEN23 ||   \
+		BRCM_HAS_MOCA_20_GEN24) && !BRCM_IKOS
+	default y
+	help
+	  Say Y to build the MoCA control path driver.  This is a simple
+	  character driver that allows the MoCA daemon (mocad) to
+	  initialize and configure the MoCA interface.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_USB
+	tristate "Broadcom STB USB support"
+	depends on BRCMSTB && USB
+	select BRCM_USB_OHCI if USB_OHCI_HCD
+	select BRCM_USB_EHCI if USB_EHCI_HCD
+	select BRCM_USB_XHCI if USB_XHCI_HCD
+	select BRCM_USB_PHY if USB_OHCI_HCD || USB_EHCI_HCD || USB_XHCI_HCD
+	select GENERIC_PHY if BRCM_USB_PHY
+	default y
+	help
+	  Say Y to enable the drivers for the onchip USB controllers.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+
+config MTD_NAND_BRCMSTB
+	tristate "Broadcom NAND controller support"
+	default y
+	depends on OF && OF_MTD
+	select MTD_NAND
+	help
+	  Say Y to enable the onchip NAND controller.
+
+config BRCM_SDIO
+	tristate "Broadcom SDHCI (SDIO) support"
+	depends on BRCMSTB && MMC_SDHCI
+	default y
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  Say Y to enable the driver for the onchip SDIO controller.
+
+	  If you do not plan on using this device, disabling CONFIG_MMC
+	  will save about 75KB.
+
+	  If unsure, say Y.
+
+config DREAMBOX
+	bool "Dreambox"
+	select DVB_CORE
+	select DVB_STV0299
+	select FB_CFB_COPYAREA
+	select FB_CFB_FILLRECT
+	select FB_CFB_IMAGEBLIT
+	select I2C
+	select MEDIA_SUPPORT
+	select SND_PCM
+
+config DREAMBOX_DM9X0
+	bool
+	depends on BCM7439B0
+	depends on DREAMBOX
+
+choice
+	prompt "Dreambox model selection"
+
+config DREAMBOX_DM900
+	bool "Dreambox DM900"
+	select DREAMBOX_DM9X0
+
+config DREAMBOX_DM920
+	bool "Dreambox DM920"
+	select DREAMBOX_DM9X0
+
+endchoice
+
+#####################################################################
+# Hidden options
+#####################################################################
+
+config BRCMSTB
+	bool
+
+config BCM7250
+	bool
+
+config BCM7364
+	bool
+
+config BCM7366
+	bool
+
+config BCM74371
+	bool
+
+config BCM7439
+	bool
+
+config BCM7445
+	bool
+
+config BRCM_GENET_V3
+	bool
+
+config BRCM_GENET_V4
+	bool
+
+config BRCM_GENET_VERSION
+	int
+	default 3 if BRCM_GENET_V3
+	default 4 if BRCM_GENET_V4
+
+# MoCA controller
+config BRCM_HAS_MOCA
+	bool
+
+# Original MoCA 1.1 (gen1 firmware)
+config BRCM_HAS_MOCA_11
+	bool
+	select BRCM_HAS_MOCA
+
+# Cost-reduced MoCA 1.1 with limited TX RAM (gen1 firmware)
+config BRCM_HAS_MOCA_11_LITE
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 1.1 with selected 2.0 features (gen2 firmware)
+config BRCM_HAS_MOCA_11_PLUS
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 2.0 (gen3 firmware for 1.1, gen2x firmware for 2.0)
+config BRCM_HAS_MOCA_20_GEN21
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN22
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN23
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_MOCA_VERS
+	hex
+	default 0x1100 if BRCM_HAS_MOCA_11
+	default 0x1101 if BRCM_HAS_MOCA_11_LITE
+	default 0x1102 if BRCM_HAS_MOCA_11_PLUS
+	default 0x2001 if BRCM_HAS_MOCA_20_GEN21
+	default 0x2002 if BRCM_HAS_MOCA_20_GEN22
+	default 0x2003 if BRCM_HAS_MOCA_20_GEN23
+	default 0x2004 if BRCM_HAS_MOCA_20_GEN24
+
+# select for MoCA on GENET_0
+config BRCM_MOCA_ON_GENET_0
+	bool
+	select BRCM_HAS_GENET_0
+
+# select for MoCA on GENET_1
+config BRCM_MOCA_ON_GENET_1
+	bool
+	select BRCM_HAS_GENET_1
+
+# MoCA is MidRF (default is HighRF)
+config BRCM_HAS_MOCA_MIDRF
+	bool
+
+config BRCM_HAS_NAND_MINOR_0
+	bool
+
+config BRCM_HAS_NAND_MINOR_1
+	bool
+
+config BRCM_HAS_NAND_MINOR_2
+	bool
+
+config BRCM_HAS_NAND_MINOR_3
+	bool
+
+config BRCM_HAS_NAND_MINOR_4
+	bool
+
+config BRCM_HAS_NAND_MAJOR_5
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_6
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_7
+	bool
+	select BRCM_HAS_NAND
+
+config BRCMNAND_MAJOR_VERS
+	int
+	default "7" if BRCM_HAS_NAND_MAJOR_7
+	default "6" if BRCM_HAS_NAND_MAJOR_6
+	default "5" if BRCM_HAS_NAND_MAJOR_5
+
+config BRCMNAND_MINOR_VERS
+	int
+	default "4" if BRCM_HAS_NAND_MINOR_4
+	default "3" if BRCM_HAS_NAND_MINOR_3
+	default "2" if BRCM_HAS_NAND_MINOR_2
+	default "1" if BRCM_HAS_NAND_MINOR_1
+	default "0" if BRCM_HAS_NAND_MINOR_0
+
+config BRCM_HAS_BSPI_V4
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_BSPI_MAJOR_VERS
+	int
+	default "4" if BRCM_HAS_BSPI_V4
+	default "3" if BRCM_HAS_BSPI_V3
+	default "2" if BRCM_HAS_BSPI_V2
+
+# For MSPI prior to v1.5 (first version with a revision register)
+config BRCM_MSPI_LEGACY
+	bool
+
+# MSPI can transfer either 64b or 8b per slot
+config BRCM_MSPI_64B_WORDS
+	bool
+
+config BRCM_USB_OHCI
+       tristate
+
+config BRCM_USB_EHCI
+       tristate
+
+config BRCM_USB_XHCI
+       tristate
+
+config BRCM_USB_PHY
+       tristate
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a0f772..c0704997717b 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -13,3 +13,9 @@
 obj-$(CONFIG_ARCH_BCM_MOBILE)	:= board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o	:=-Wa,-march=armv7-a$(plus_sec)
+
+ifeq ($(CONFIG_ARCH_BRCMSTB),y)
+obj-y				+= brcmstb.o
+obj-$(CONFIG_SMP)		+= platsmp-brcmstb.o
+obj-$(CONFIG_PCI)		+= pci-brcmstb.o
+endif
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
new file mode 100644
index 000000000000..3964ef3c074e
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/console.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-contiguous.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#if defined(CONFIG_BRCMSTB)
+#include <linux/brcmstb/bmem.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/brcmstb/cma_driver.h>
+#endif
+#include <linux/clk/clk-brcmstb.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/soc/brcmstb/brcmstb.h>
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/setup.h>
+
+/***********************************************************************
+ * STB CPU (main application processor)
+ ***********************************************************************/
+
+static const char *brcmstb_match[] __initconst = {
+	"brcm,bcm7445",
+	"brcm,brcmstb",
+	NULL
+};
+
+#if defined(CONFIG_BRCMSTB)
+/*
+ * HACK: The following drivers are still using BDEV macros:
+ * - XPT DMA
+ * - SPI
+ * - NAND
+ * - SDHCI
+ * - MoCA
+ *
+ * Once these drivers have migrated over to using 'of_iomap()' and standard
+ * register accessors, we can eliminate this static mapping.
+ */
+static struct map_desc brcmstb_io_map[] __initdata = {
+	{
+	.virtual = (unsigned long)BRCMSTB_PERIPH_VIRT,
+	.pfn     = __phys_to_pfn(BRCMSTB_PERIPH_PHYS),
+	.length  = BRCMSTB_PERIPH_LENGTH,
+	.type    = MT_DEVICE,
+	},
+};
+
+static void __init brcmstb_map_io(void)
+{
+	iotable_init(brcmstb_io_map, ARRAY_SIZE(brcmstb_io_map));
+}
+
+static void __init brcmstb_reserve(void)
+{
+	brcmstb_memory_reserve();
+	cma_reserve();
+	bmem_reserve();
+}
+
+static void __init brcmstb_init_irq(void)
+{
+	/* Force lazily-disabled IRQs to be masked before suspend */
+	gic_arch_extn.flags |= IRQCHIP_MASK_ON_SUSPEND;
+
+	irqchip_init();
+}
+
+static void __init brcmstb_init_machine(void)
+{
+	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	cma_register();
+	platform_device_register_full(&devinfo);
+}
+
+static void __init brcmstb_init_early(void)
+{
+	brcmstb_biuctrl_init();
+//	add_preferred_console("ttyS", 0, "115200");
+}
+
+static void __init brcmstb_init_time(void)
+{
+	brcmstb_clocks_init();
+	clocksource_of_init();
+}
+#endif /* CONFIG_BRCMSTB */
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+	.dt_compat	= brcmstb_match,
+#if defined(CONFIG_BRCMSTB)
+	.map_io		= brcmstb_map_io,
+	.reserve	= brcmstb_reserve,
+	.init_machine	= brcmstb_init_machine,
+	.init_early	= brcmstb_init_early,
+	.init_irq	= brcmstb_init_irq,
+	.init_time	= brcmstb_init_time,
+#endif
+MACHINE_END
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.h b/arch/arm/mach-bcm/headsmp-brcmstb.h
new file mode 100644
index 000000000000..884a41a2d08c
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HEADSMP_BRCMSTB_H__
+#define __HEADSMP_BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+
+extern void brcmstb_secondary_startup(void);
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* __HEADSMP_BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/pci-brcmstb.c b/arch/arm/mach-bcm/pci-brcmstb.c
new file mode 100644
index 000000000000..2995125dc182
--- /dev/null
+++ b/arch/arm/mach-bcm/pci-brcmstb.c
@@ -0,0 +1,1254 @@
+/*
+ * Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/msi.h>
+#include <linux/printk.h>
+#include <linux/syscore_ops.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/module.h>
+#include <linux/irqdomain.h>
+#include <linux/regulator/consumer.h>
+#include <linux/string.h>
+
+/* Broadcom PCIE Offsets */
+#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY		0x00b8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL		0x00bc
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL		0x00c8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2		0x00dc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1		0x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
+#define PCIE_RC_DL_MDIO_ADDR				0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
+#define PCIE_MISC_MISC_CTRL				0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
+#define PCIE_MISC_RC_BAR1_CONFIG_HI			0x4030
+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
+#define PCIE_MISC_RC_BAR3_CONFIG_HI			0x4040
+#define PCIE_MISC_MSI_BAR_CONFIG_LO			0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI			0x4048
+#define PCIE_MISC_MSI_DATA_CONFIG			0x404c
+#define PCIE_MISC_PCIE_CTRL				0x4064
+#define PCIE_MISC_PCIE_STATUS				0x4068
+#define PCIE_MISC_REVISION				0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
+#define PCIE_INTR2_CPU_BASE				0x4300
+#define PCIE_MSI_INTR2_BASE				0x4500
+#define PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX			0x9000
+#define PCIE_EXT_CFG_PCIE_EXT_CFG_DATA			0x9004
+#define PCIE_RGR1_SW_INIT_1				0x9210
+#define BRCM_NUM_PCI_OUT_WINS		0x4
+#define BRCM_MAX_SCB			0x4
+#define BRCM_INT_PCI_MSI_NR		32
+#define BRCM_PCIE_HW_REV_33		0x0303
+#define BRCM_MSI_TARGET_ADDR_LO		0x0
+#define BRCM_MSI_TARGET_ADDR_HI		0xffffffff
+
+/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
+#define STATUS				0x0
+#define SET				0x4
+#define CLR				0x8
+#define MASK_STATUS			0xc
+#define MASK_SET			0x10
+#define MASK_CLR			0x14
+
+#define PCI_BUSNUM_SHIFT		20
+#define PCI_SLOT_SHIFT			15
+#define PCI_FUNC_SHIFT			12
+
+#define IDX_ADDR(base)		((base) + PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX)
+#define DATA_ADDR(base)		((base) + PCIE_EXT_CFG_PCIE_EXT_CFG_DATA)
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *data);
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 data);
+
+static struct pci_ops brcm_pci_ops = {
+	.read = brcm_pci_read_config,
+	.write = brcm_pci_write_config,
+};
+
+static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys);
+static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+static struct hw_pci brcm_pcie_hw __initdata = {
+	.nr_controllers	= 0,
+	.setup		= brcm_setup_pcie_bridge,
+	.map_irq	= brcm_map_irq,
+	.ops		= &brcm_pci_ops,
+};
+
+struct brcm_msi {
+	struct irq_domain *domain;
+	struct irq_chip irq_chip;
+	struct msi_chip chip;
+	struct mutex lock;
+	int irq;
+	/* intr_base is the base pointer for interrupt status/set/clr regs */
+	void __iomem *intr_base;
+	/* intr_legacy_mask indicates how many bits are MSI interrupts */
+	u32 intr_legacy_mask;
+	/* intr_legacy_offset indicates bit position of MSI_01 */
+	u32 intr_legacy_offset;
+	/* used indicates which MSI interrupts have been alloc'd */
+	unsigned long used;
+	/* working indicates that on boot we have brought up MSI */
+	bool working;
+};
+
+struct brcm_window {
+	u64 pci_addr;
+	u64 size;
+	u64 cpu_addr;
+	u32 info;
+	struct resource pcie_iomem_res;
+};
+
+struct brcm_dev_pwr_supply {
+	struct list_head node;
+	char name[32];
+	struct regulator *regulator;
+};
+
+/* Internal Bus Controller Information.*/
+struct brcm_pcie {
+	struct list_head	list;
+	void __iomem		*base;
+	char			name[8];
+	bool			suspended;
+	struct clk		*clk;
+	struct device_node	*dn;
+	int			pcie_irq[4];
+	int			irq;
+	int			num_out_wins;
+	bool			ssc;
+	int			gen;
+	int			scb_size_vals[BRCM_MAX_SCB];
+	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
+	struct pci_sys_data	*sys;
+	struct device		*dev;
+	struct list_head	pwr_supplies;
+	bool			broken_pcie_irq_map_dt;
+	struct brcm_msi		msi;
+	unsigned		rev;
+};
+
+static struct list_head brcm_pcie;
+static int brcm_num_pci_controllers;
+static int num_memc;
+static void turn_off(void __iomem *base);
+static void enter_l23(struct brcm_pcie *pcie);
+
+
+/***********************************************************************
+ * PCIe Bridge setup
+ ***********************************************************************/
+#if defined(__BIG_ENDIAN)
+#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
+#define MMIO_ENDIAN		2	/* CPU->PCI outbound accesses */
+#else
+#define	DATA_ENDIAN		0
+#define MMIO_ENDIAN		0
+#endif
+
+
+static void remove_pcie(struct brcm_pcie *pcie)
+{
+	struct list_head *pos, *q;
+	struct brcm_pcie *tmp;
+
+	list_for_each_safe(pos, q, &brcm_pcie) {
+		tmp = list_entry(pos, struct brcm_pcie, list);
+		if (tmp == pcie) {
+			list_del(pos);
+			break;
+		}
+	}
+}
+
+
+/* negative return value indicates error */
+static int mdio_read(void __iomem *base, u8 phyad, u8 regad)
+{
+	const int TRYS = 10;
+	u32 data = ((phyad & 0xf) << 16)
+		| (regad & 0x1f)
+		| 0x100000;
+
+	int i = 0;
+
+	__raw_writel(data, base + PCIE_RC_DL_MDIO_ADDR);
+	__raw_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+	data = __raw_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+
+	while (!(data & 0x80000000) && ++i < TRYS) {
+		udelay(10);
+		data = __raw_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+	}
+
+	return (data & 0x80000000) ? (data & 0xffff) : -EIO;
+}
+
+
+/* negative return value indicates error */
+static int mdio_write(void __iomem *base, u8 phyad, u8 regad, u16 wrdata)
+{
+	u32 data = ((phyad & 0xf) << 16) | (regad & 0x1f);
+	const int TRYS = 10;
+	int i = 0;
+	__raw_writel(data, base + PCIE_RC_DL_MDIO_ADDR);
+	__raw_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+	__raw_writel(0x80000000 | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
+
+	data = __raw_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+
+	while ((data & 0x80000000) && ++i < TRYS) {
+		udelay(10);
+		data = __raw_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+	}
+
+	return (data & 0x80000000) ? -EIO : 0;
+}
+
+
+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	u32 reg = __raw_readl(p);
+	reg = (reg & ~mask) | (val << shift);
+	__raw_writel(reg, p);
+}
+
+
+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	wr_fld(p, mask, shift, val);
+	(void) __raw_readl(p);
+}
+
+
+/* configures device for ssc mode; negative return value indicates error */
+static int set_ssc(void __iomem *base)
+{
+	int tmp;
+	u16 wrdata;
+
+	tmp = mdio_write(base, 0, 0x1f, 0x1100);
+	if (tmp < 0)
+		return tmp;
+
+	tmp = mdio_read(base, 0, 2);
+	if (tmp < 0)
+		return tmp;
+
+	wrdata = ((u16)tmp & 0x3fff) | 0xc000;
+	tmp = mdio_write(base, 0, 2, wrdata);
+	if (tmp < 0)
+		return tmp;
+
+	mdelay(1);
+	tmp = mdio_read(base, 0, 1);
+	if (tmp < 0)
+		return tmp;
+
+	return 0;
+}
+
+
+/* returns 0 if in ssc mode, 1 if not, <0 on error */
+static int is_ssc(void __iomem *base)
+{
+	int tmp = mdio_write(base, 0, 0x1f, 0x1100);
+	if (tmp < 0)
+		return tmp;
+	tmp = mdio_read(base, 0, 1);
+	if (tmp < 0)
+		return tmp;
+	return (tmp & 0xc00) == 0xc00 ? 0 : 1;
+}
+
+
+/* limits operation to a specific generation (1, 2, or 3) */
+static void set_gen(void __iomem *base, int gen)
+{
+	wr_fld(base + PCIE_RC_CFG_PCIE_LINK_CAPABILITY, 0xf, 0, gen);
+	wr_fld(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2, 0xf, 0, gen);
+}
+
+
+static void set_pcie_outbound_win(void __iomem *base, unsigned win, u64 start,
+				  u64 len)
+{
+	u32 tmp;
+
+	__raw_writel((u32)(start) + MMIO_ENDIAN,
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO+(win*8));
+	__raw_writel((u32)(start >> 32),
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI+(win*8));
+	tmp = ((((u32)start) >> 20) << 4)
+		| (((((u32)start) + ((u32)len) - 1) >> 20) << 20);
+	__raw_writel(tmp,
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT+(win*4));
+}
+
+
+static int is_pcie_link_up(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	u32 val = __raw_readl(base + PCIE_MISC_PCIE_STATUS);
+	return  ((val & 0x30) == 0x30) ? 1 : 0;
+}
+
+
+static inline struct brcm_msi *to_brcm_msi(struct msi_chip *chip)
+{
+	return container_of(chip, struct brcm_msi, chip);
+}
+
+
+static int brcm_msi_alloc(struct brcm_msi *chip)
+{
+	int msi;
+
+	mutex_lock(&chip->lock);
+	msi = ~chip->used ? ffz(chip->used) : -1;
+
+	if (msi >= 0 && msi < BRCM_INT_PCI_MSI_NR)
+		chip->used |= (1 << msi);
+	else
+		msi = -ENOSPC;
+
+	mutex_unlock(&chip->lock);
+	return msi;
+}
+
+
+static void brcm_msi_free(struct brcm_msi *chip, unsigned long irq)
+{
+	mutex_lock(&chip->lock);
+	chip->used &= ~(1 << irq);
+	mutex_unlock(&chip->lock);
+}
+
+
+static irqreturn_t brcm_pcie_msi_irq(int irq, void *data)
+{
+	struct brcm_pcie *pcie = data;
+	struct brcm_msi *msi = &pcie->msi;
+	unsigned long status;
+
+	status = __raw_readl(msi->intr_base + STATUS) & msi->intr_legacy_mask;
+
+	if (!status)
+		return IRQ_NONE;
+
+	while (status) {
+		unsigned int index = ffs(status) - 1;
+		unsigned int irq;
+
+		/* clear the interrupt */
+		__raw_writel(1 << index, msi->intr_base + CLR);
+		status &= ~(1 << index);
+
+		/* Account for legacy interrupt offset */
+		index -= msi->intr_legacy_offset;
+
+		irq = irq_find_mapping(msi->domain, index);
+		if (irq) {
+			if (msi->used & (1 << index))
+				generic_handle_irq(irq);
+			else
+				dev_info(pcie->dev, "unhandled MSI %d\n",
+					 index);
+		} else {
+			/* Unknown MSI, just clear it */
+			dev_dbg(pcie->dev, "unexpected MSI\n");
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+
+static int brcm_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
+			      struct msi_desc *desc)
+{
+	struct brcm_msi *msi = to_brcm_msi(chip);
+	struct brcm_pcie *pcie = container_of(chip, struct brcm_pcie, msi.chip);
+	struct msi_msg msg;
+	unsigned int irq;
+	int hwirq;
+	u32 data;
+
+	hwirq = brcm_msi_alloc(msi);
+	if (hwirq < 0)
+		return hwirq;
+
+	irq = irq_create_mapping(msi->domain, hwirq);
+	if (!irq) {
+		brcm_msi_free(msi, hwirq);
+		return -EINVAL;
+	}
+
+	irq_set_msi_desc(irq, desc);
+
+	msg.address_lo = BRCM_MSI_TARGET_ADDR_LO;
+	msg.address_hi = BRCM_MSI_TARGET_ADDR_HI;
+	data = __raw_readl(pcie->base + PCIE_MISC_MSI_DATA_CONFIG);
+	msg.data = ((data >> 16) & (data & 0xffff)) | hwirq;
+	wmb(); /* just being cautious */
+	write_msi_msg(irq, &msg);
+
+	return 0;
+}
+
+
+static void brcm_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
+{
+	struct brcm_msi *msi = to_brcm_msi(chip);
+	struct irq_data *d = irq_get_irq_data(irq);
+
+	brcm_msi_free(msi, d->hwirq);
+}
+
+
+static int brcm_msi_map(struct irq_domain *domain, unsigned int irq,
+			irq_hw_number_t hwirq)
+{
+	struct brcm_pcie *pcie = domain->host_data;
+
+	irq_set_chip_and_handler(irq, &pcie->msi.irq_chip, handle_simple_irq);
+	irq_set_chip_data(irq, domain->host_data);
+
+	return 0;
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+	.map = brcm_msi_map,
+};
+
+
+static int brcm_pcie_enable_msi(struct brcm_pcie *pcie, int nr)
+{
+	static const char brcm_msi_name[] = "brcmstb_pcieX_msi";
+	struct brcm_msi *msi = &pcie->msi;
+	u32 data_val;
+	char *name;
+	int err;
+
+	if (!pcie->suspended) {
+		/* We are only here on cold boot */
+		mutex_init(&msi->lock);
+
+		msi->chip.dev = pcie->dev;
+		msi->chip.setup_irq = brcm_msi_setup_irq;
+		msi->chip.teardown_irq = brcm_msi_teardown_irq;
+
+		/* We have multiple RC controllers.  We may have as many
+		 * MSI controllers for them.  We want each to have a
+		 * unique name, so we go to the trouble of having an
+		 * irq_chip per RC (instead of one for all of them). */
+		name = devm_kzalloc(pcie->dev, sizeof(brcm_msi_name),
+				    GFP_KERNEL);
+		if (name) {
+			char *p;
+			strcpy(name, brcm_msi_name);
+			p = strchr(name, 'X');
+			if (p)
+				*p = '0' + nr;
+			msi->irq_chip.name = name;
+		} else {
+			msi->irq_chip.name = brcm_msi_name;
+		}
+
+		msi->irq_chip.irq_enable = unmask_msi_irq;
+		msi->irq_chip.irq_disable = mask_msi_irq;
+		msi->irq_chip.irq_mask = mask_msi_irq;
+		msi->irq_chip.irq_unmask = unmask_msi_irq;
+
+		msi->domain =
+			irq_domain_add_linear(pcie->dn, BRCM_INT_PCI_MSI_NR,
+					      &msi_domain_ops, pcie);
+		if (!msi->domain) {
+			dev_err(pcie->dev,
+				"failed to create IRQ domain for MSI\n");
+			return -ENOMEM;
+		}
+
+		err = devm_request_irq(pcie->dev, msi->irq, brcm_pcie_msi_irq,
+				       IRQF_SHARED, msi->irq_chip.name,
+				       pcie);
+
+		if (err < 0) {
+			dev_err(pcie->dev,
+				"failed to request IRQ (%d) for MSI\n",	err);
+			goto msi_en_err;
+		}
+
+		if (pcie->rev >= BRCM_PCIE_HW_REV_33) {
+			msi->intr_base = pcie->base + PCIE_MSI_INTR2_BASE;
+			/* This version of PCIe hw has only 32 intr bits
+			 * starting at bit position 0. */
+			msi->intr_legacy_mask = 0xffffffff;
+			msi->intr_legacy_offset = 0x0;
+			msi->used = 0x0;
+
+		} else {
+			msi->intr_base = pcie->base + PCIE_INTR2_CPU_BASE;
+			/* This version of PCIe hw has only 8 intr bits starting
+			 * at bit position 24. */
+			msi->intr_legacy_mask = 0xff000000;
+			msi->intr_legacy_offset = 24;
+			msi->used = 0xffffff00;
+		}
+		msi->working = true;
+	}
+
+	/* If we are here, and msi->working is false, it means that we've
+	 * already tried and failed to bring up MSI.  Just return 0
+	 * since there is nothing to be done. */
+	if (!msi->working)
+		return 0;
+
+	if (pcie->rev >= BRCM_PCIE_HW_REV_33) {
+		/* ffe0 -- least sig 5 bits are 0 indicating 32 msgs
+		 * 6540 -- this is our arbitrary unique data value */
+		data_val = 0xffe06540;
+	} else {
+		/* fff8 -- least sig 3 bits are 0 indicating 8 msgs
+		 * 6540 -- this is our arbitrary unique data value */
+		data_val = 0xfff86540;
+	}
+
+	/* Make sure we are not masking MSIs.  Note that MSIs can be masked,
+	 * but that occurs on the PCIe EP device */
+	__raw_writel(0xffffffff & msi->intr_legacy_mask,
+		     msi->intr_base + MASK_CLR);
+
+	/* The 0 bit of BRCM_MSI_TARGET_ADDR_LO is repurposed to MSI enable,
+	 * which we set to 1. */
+	__raw_writel(BRCM_MSI_TARGET_ADDR_LO | 1, pcie->base
+		     + PCIE_MISC_MSI_BAR_CONFIG_LO);
+	__raw_writel(BRCM_MSI_TARGET_ADDR_HI, pcie->base
+		     + PCIE_MISC_MSI_BAR_CONFIG_HI);
+	__raw_writel(data_val, pcie->base + PCIE_MISC_MSI_DATA_CONFIG);
+
+	return 0;
+
+msi_en_err:
+	irq_domain_remove(msi->domain);
+	return err;
+}
+
+
+static void brcm_pcie_setup_early(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	unsigned int scb_size_val;
+	int i;
+
+	/* reset the bridge and the endpoint device */
+	/* field: PCIE_BRIDGE_SW_INIT = 1 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 1);
+	/* field: PCIE_SW_PERST = 1 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 1);
+
+	/* delay 100us */
+	udelay(100);
+
+	/* take the bridge out of reset */
+	/* field: PCIE_BRIDGE_SW_INIT = 0 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 0);
+
+	/* Grab the PCIe hw revision number */
+	pcie->rev = __raw_readl(base + PCIE_MISC_REVISION) & 0xffff;
+
+	/* enable SCB_MAX_BURST_SIZE | CSR_READ_UR_MODE | SCB_ACCESS_EN */
+	__raw_writel(0x81e03000, base + PCIE_MISC_MISC_CTRL);
+
+	for (i = 0; i < pcie->num_out_wins; i++) {
+		struct brcm_window *w = &pcie->out_wins[i];
+		set_pcie_outbound_win(base, i, w->cpu_addr, w->size);
+	}
+
+	/* set up 4GB PCIE->SCB memory window on BAR2 */
+	__raw_writel(0x00000011, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+	/* field: SCB0_SIZE, default = 0xf (1 GB) */
+	scb_size_val = pcie->scb_size_vals[0] ? pcie->scb_size_vals[0] : 0xf;
+	wr_fld(base + PCIE_MISC_MISC_CTRL, 0xf8000000, 27, scb_size_val);
+
+	/* field: SCB1_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 1) {
+		scb_size_val = pcie->scb_size_vals[1]
+			? pcie->scb_size_vals[1] : 0xf;
+		wr_fld(base + PCIE_MISC_MISC_CTRL, 0x07c00000,
+		       22, scb_size_val);
+	}
+
+	/* field: SCB2_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 2) {
+		scb_size_val = pcie->scb_size_vals[2]
+			? pcie->scb_size_vals[2] : 0xf;
+		wr_fld(base + PCIE_MISC_MISC_CTRL, 0x0000001f,
+		       0, scb_size_val);
+	}
+
+	/* disable the PCIE->GISB memory window */
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
+
+	/* disable the PCIE->SCB memory window */
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
+
+	if (!pcie->suspended) {
+		/* clear any interrupts we find on boot */
+		__raw_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
+		(void) __raw_readl(base + PCIE_INTR2_CPU_BASE + CLR);
+	}
+
+	/* Mask all interrupts since we are not handling any yet */
+	__raw_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
+	(void) __raw_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
+
+	if (pcie->gen)
+		set_gen(base, pcie->gen);
+
+	/* take the EP device out of reset */
+	/* field: PCIE_SW_PERST = 0 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 0);
+}
+
+
+static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys)
+{
+	struct brcm_pcie *pcie = sys->private_data;
+	void __iomem *base = pcie->base;
+	const int limit = pcie->suspended ? 1000 : 100;
+	struct clk *clk;
+	unsigned status;
+	static const char *link_speed[4] = { "???", "2.5", "5.0", "8.0" };
+	int i, j, ret;
+	bool ssc_good = false;
+
+	pcie->sys = sys;
+
+	/* Give the RC/EP time to wake up, before trying to configure RC.
+	 * Intermittently check status for link-up, up to a total of 100ms
+	 * when we don't know if the device is there, and up to 1000ms if
+	 * we do know the device is there. */
+	for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie); j += i, i = i*2)
+		mdelay(i + j > limit ? limit - j : i);
+
+	if (!is_pcie_link_up(pcie)) {
+		dev_info(pcie->dev, "link down\n");
+		goto FAIL;
+	}
+
+	/* Attempt to enable MSI if we have an interrupt for it. */
+	if (pcie->msi.irq > 0) {
+		ret = brcm_pcie_enable_msi(pcie, nr);
+		if (ret < 0) {
+			dev_err(pcie->dev, "failed to enable MSI support: %d\n",
+				ret);
+		}
+	}
+
+	/* For config space accesses on the RC, show the right class for
+	 * a PCI-PCI bridge */
+	wr_fld_rb(base + PCIE_RC_CFG_PRIV1_ID_VAL3, 0x00ffffff, 0, 0x060400);
+
+	if (!pcie->suspended)
+		for (i = 0; i < pcie->num_out_wins; i++)
+			pci_add_resource_offset(&sys->resources,
+					&pcie->out_wins[i].pcie_iomem_res,
+					sys->mem_offset);
+
+	status = __raw_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
+
+	if (pcie->ssc) {
+		if (set_ssc(base))
+			dev_err(pcie->dev,
+				"mdio rd/wt fail during ssc config\n");
+		ret = is_ssc(base);
+		if (ret == 0) {
+			ssc_good = true;
+		} else {
+			if (ret < 0)
+				dev_err(pcie->dev,
+					"mdio rd/wt fail during ssc query\n");
+			dev_err(pcie->dev, "failed to enter SSC mode\n");
+		}
+	}
+
+	dev_info(pcie->dev, "link up, %s Gbps x%u %s\n",
+		 link_speed[((status & 0x000f0000) >> 16) & 0x3],
+		 (status & 0x03f00000) >> 20, ssc_good ? "(SSC)" : "(!SSC)");
+
+	/* Enable configuration request retry (see pci_scan_device()) */
+	/* field RC_CRS_EN = 1 */
+	wr_fld(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, 0x00000010, 4, 1);
+
+	/* PCIE->SCB endian mode for BAR */
+	/* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
+	wr_fld_rb(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, 0x0000000c, 2,
+		  DATA_ENDIAN);
+
+	/* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+	 * is enabled =>  setting the CLKREQ_DEBUG_ENABLE field to 1. */
+	wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x00000002, 1, 1);
+
+	return 1;
+FAIL:
+	if (IS_ENABLED(CONFIG_PM))
+		turn_off(base);
+
+	clk = pcie->clk;
+	if (pcie->suspended)
+		clk_disable(clk);
+	else {
+		clk_disable_unprepare(clk);
+		clk_put(clk);
+		remove_pcie(pcie);
+	}
+	return 0;
+
+}
+
+
+/*
+ * syscore device to handle PCIe bus suspend and resume
+ */
+
+static void turn_off(void __iomem *base)
+{
+	/* Reset endpoint device */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 1);
+	/* deassert request for L23 in case it was asserted */
+	wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 0);
+	/* SERDES_IDDQ = 1 */
+	wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x08000000,
+		  27, 1);
+	/* Shutdown PCIe bridge */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 1);
+}
+
+
+static void enter_l23(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	int timeout = 1000;
+	int l23;
+
+	/* assert request for L23 */
+	wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 1);
+	do {
+		/* poll L23 status */
+		l23 = __raw_readl(base + PCIE_MISC_PCIE_STATUS) & (1 << 6);
+	} while (--timeout && !l23);
+
+	if (!timeout)
+		dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+
+static int pcie_suspend(void)
+{
+	struct brcm_pcie *pcie;
+	struct list_head *pos;
+	struct brcm_dev_pwr_supply *supply;
+
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		enter_l23(pcie);
+		turn_off(pcie->base);
+		clk_disable(pcie->clk);
+		list_for_each(pos, &pcie->pwr_supplies) {
+			supply = list_entry(pos, struct brcm_dev_pwr_supply,
+					    node);
+			if (regulator_disable(supply->regulator))
+				pr_debug("Unable to turn off %s supply.\n",
+					 supply->name);
+
+		}
+		pcie->suspended = true;
+	}
+	return 0;
+}
+
+
+static void pcie_resume(void)
+{
+	int i = 0;
+	struct brcm_pcie *pcie;
+	struct list_head *pos;
+	struct brcm_dev_pwr_supply *supply;
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		void __iomem *base;
+
+		base = pcie->base;
+		list_for_each(pos, &pcie->pwr_supplies) {
+			supply = list_entry(pos, struct brcm_dev_pwr_supply,
+					    node);
+			if (regulator_enable(supply->regulator))
+				pr_debug("Unable to turn on %s supply.\n",
+					 supply->name);
+		}
+		clk_enable(pcie->clk);
+
+		/* Take bridge out of reset so we can access the SERDES reg */
+		wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 0);
+
+		/* SERDES_IDDQ = 0 */
+		wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x08000000,
+			  27, 0);
+		/* wait for serdes to be stable */
+		udelay(100);
+
+		brcm_pcie_setup_early(pcie);
+	}
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		brcm_setup_pcie_bridge(i++, pcie->sys);
+		pcie->suspended = false;
+	}
+}
+
+static struct syscore_ops pcie_pm_ops = {
+	.suspend        = pcie_suspend,
+	.resume         = pcie_resume,
+};
+
+
+/***********************************************************************
+ * Read/write PCI configuration registers
+ ***********************************************************************/
+static int cfg_index(int busnr, int devfn, int reg)
+{
+	return ((PCI_SLOT(devfn) & 0x1f) << PCI_SLOT_SHIFT)
+		| ((PCI_FUNC(devfn) & 0x07) << PCI_FUNC_SHIFT)
+		| (busnr << PCI_BUSNUM_SHIFT)
+		| (reg & ~3);
+}
+
+static u32 read_config(void __iomem *base, int cfg_idx)
+{
+	__raw_writel(cfg_idx, IDX_ADDR(base));
+	__raw_readl(IDX_ADDR(base));
+	return __raw_readl(DATA_ADDR(base));
+}
+
+static void write_config(void __iomem *base, int cfg_idx, u32 val)
+{
+	__raw_writel(cfg_idx, IDX_ADDR(base));
+	__raw_readl(IDX_ADDR(base));
+	__raw_writel(val, DATA_ADDR(base));
+	__raw_readl(DATA_ADDR(base));
+}
+
+
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 data)
+{
+	u32 val = 0, mask, shift;
+	struct pci_sys_data *sys = bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	void __iomem *base;
+	bool rc_access;
+	int idx;
+
+	if (!is_pcie_link_up(pcie))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	base = pcie->base;
+	rc_access = sys->busnr == bus->number;
+	idx = cfg_index(bus->number, devfn, where);
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (rc_access && PCI_SLOT(devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (size < 4) {
+		/* partial word - read, modify, write */
+		if (rc_access)
+			val = __raw_readl(base + (where & ~3));
+		else
+			val = read_config(base, idx);
+	}
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+	val = (val & ~mask) | ((data << shift) & mask);
+
+	if (rc_access) {
+		__raw_writel(val, base + (where & ~3));
+		__raw_readl(base + (where & ~3));
+	} else {
+		write_config(base, idx, val);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *data)
+{
+	struct pci_sys_data *sys = bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	u32 val, mask, shift;
+	void __iomem *base;
+	bool rc_access;
+	int idx;
+
+	if (!is_pcie_link_up(pcie))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	base = pcie->base;
+	rc_access = sys->busnr == bus->number;
+	idx = cfg_index(bus->number, devfn, where);
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (rc_access && PCI_SLOT(devfn)) {
+		*data = 0xffffffff;
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+	}
+
+	if (rc_access)
+		val = __raw_readl(base + (where & ~3));
+	else
+		val = read_config(base, idx);
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+	*data = (val & mask) >> shift;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+
+
+/***********************************************************************
+ * PCI slot to IRQ mappings (aka "fixup")
+ ***********************************************************************/
+static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct pci_sys_data *sys = dev->bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+
+	if (pcie) {
+		if (!pcie->broken_pcie_irq_map_dt)
+			return of_irq_parse_and_map_pci(dev, slot, pin);
+		if ((pin - 1) > 3)
+			return 0;
+		return pcie->pcie_irq[pin - 1];
+	}
+	return 0;
+}
+
+
+/***********************************************************************
+ * Per-device initialization
+ ***********************************************************************/
+static void __attribute__((__section__("pci_fixup_early")))
+brcm_pcibios_fixup(struct pci_dev *dev)
+{
+	struct pci_sys_data *sys = dev->bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	int slot = PCI_SLOT(dev->devfn);
+
+	if (pci_is_root_bus(dev->bus)) {
+		/* Set the root pci_dev's device node */
+		if (!dev->dev.of_node)
+			dev->dev.of_node = pcie->dn;
+		/* Set the root bus's msi value */
+		if (IS_ENABLED(CONFIG_PCI_MSI))
+			dev->bus->msi = &pcie->msi.chip;
+	}
+	dev_info(pcie->dev,
+		 "found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
+		 dev->vendor, dev->device, dev->bus->number, pcie->name,
+		 slot, brcm_map_irq(dev, slot, 1));
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
+
+
+/***********************************************************************
+ * PCI Platform Driver
+ ***********************************************************************/
+static int __init brcm_pci_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node, *mdn;
+	const u32 *imap_prop;
+	int len, i, irq_offset, rlen, pna, np, ret;
+	struct brcm_pcie *pcie;
+	struct resource *r;
+	const u32 *ranges, *log2_scb_sizes, *dma_ranges;
+	void __iomem *base;
+	u32 tmp;
+	int supplies;
+	const char *name;
+	struct brcm_dev_pwr_supply *supply;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(struct brcm_pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&pcie->pwr_supplies);
+	supplies = of_property_count_strings(dn, "supply-names");
+	if (supplies <= 0)
+		supplies = 0;
+
+	for (i = 0; i < supplies; i++) {
+		if (of_property_read_string_index(dn, "supply-names", i,
+						  &name))
+			continue;
+		supply = devm_kzalloc(&pdev->dev, sizeof(*supply), GFP_KERNEL);
+		if (!supply)
+			return -ENOMEM;
+		strncpy(supply->name, name, sizeof(supply->name));
+		supply->name[sizeof(supply->name) - 1] = '\0';
+		supply->regulator = devm_regulator_get(&pdev->dev, name);
+		if (IS_ERR(supply->regulator)) {
+			dev_err(&pdev->dev, "Unable to get %s supply, err=%d\n",
+				name, (int)PTR_ERR(supply->regulator));
+			continue;
+		}
+		if (regulator_enable(supply->regulator))
+			dev_err(&pdev->dev, "Unable to enable %s supply.\n",
+				name);
+		list_add_tail(&supply->node, &pcie->pwr_supplies);
+	}
+
+	/* 'num_memc' will be set only by the first controller, and all
+	 * other controllers will use the value set by the first. */
+	if (num_memc == 0)
+		for_each_compatible_node(mdn, NULL, "brcm,brcmstb-memc")
+			if (of_device_is_available(mdn))
+				num_memc++;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r)
+		return -EINVAL;
+
+	base = devm_request_and_ioremap(&pdev->dev, r);
+	if (!base)
+		return -ENOMEM;
+
+	imap_prop = of_get_property(dn, "interrupt-map", &len);
+
+	if (imap_prop == NULL) {
+		dev_err(&pdev->dev, "missing interrupt-map\n");
+		return -EINVAL;
+	}
+
+	if (len == sizeof(u32) * 4 * 7) {
+		/* broken method for getting INT{ABCD} */
+		dev_info(&pdev->dev, "adjusting to legacy (broken) pcie DT\n");
+		pcie->broken_pcie_irq_map_dt = true;
+		irq_offset = irq_of_parse_and_map(dn, 0);
+		for (i = 0; i < 4 && i*4 < len; i++)
+			pcie->pcie_irq[i] = irq_offset
+				+ of_read_number(imap_prop + (i * 7 + 5), 1);
+	}
+
+	snprintf(pcie->name,
+		 sizeof(pcie->name)-1, "PCIe%d", brcm_num_pci_controllers);
+	pcie->suspended = false;
+	pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+	if (IS_ERR(pcie->clk)) {
+		dev_err(&pdev->dev, "could not get clock\n");
+		pcie->clk = NULL;
+	}
+	ret = clk_prepare_enable(pcie->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "could not enable clock\n");
+		return ret;
+	}
+	pcie->dn = dn;
+	pcie->base = base;
+	pcie->dev = &pdev->dev;
+	pcie->dev->of_node = dn;
+	pcie->gen = 0;
+
+	ret = of_property_read_u32(dn, "brcm,gen", &tmp);
+	if (ret == 0) {
+		if (tmp > 0 && tmp < 3)
+			pcie->gen = (int) tmp;
+		else
+			dev_warn(pcie->dev, "bad DT value for prop 'brcm,gen");
+	} else if (ret != -EINVAL) {
+		dev_warn(pcie->dev, "error reading DT prop 'brcm,gen");
+	}
+
+	pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
+
+	/* Get the value for the log2 of the scb sizes.  Subtract 15 from
+	 * each because the target register field has 0==disabled and 1==64KB.
+	 */
+	log2_scb_sizes = of_get_property(dn, "brcm,log2-scb-sizes", &rlen);
+	if (log2_scb_sizes != NULL)
+		for (i = 0; i < rlen/4; i++)
+			pcie->scb_size_vals[i]
+				= (int) of_read_number(log2_scb_sizes + i, 1)
+					- 15;
+
+	/* Look for the dma-ranges property.  If it exists, issue a warning
+	 * as PCIe drivers may not work.  This is because the identity
+	 * mapping between system memory and PCIe space is not preserved,
+	 * and we need Linux to massage the dma_addr_t values it gets
+	 * from dma memory allocation.  This functionality will be added
+	 * in the near future.
+	 */
+	dma_ranges = of_get_property(dn, "dma-ranges", &rlen);
+	if (dma_ranges != NULL)
+		dev_warn(pcie->dev, "no identity map; PCI drivers may fail");
+
+	if (!pcie->broken_pcie_irq_map_dt) {
+		ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
+		if (ret == 0) {
+			dev_warn(pcie->dev, "cannot get pcie interrupt\n");
+			/* keep going, as we don't use this yet */
+		} else {
+			pcie->irq = ret;
+		}
+	}
+
+	ranges = of_get_property(dn, "ranges", &rlen);
+	if (ranges == NULL) {
+		dev_err(pcie->dev, "no ranges property in dev tree.\n");
+		return -EINVAL;
+	}
+	/* set up CPU->PCIE memory windows (max of four) */
+	pna = of_n_addr_cells(dn);
+	np = pna + 5;
+
+	pcie->num_out_wins = rlen / (np * 4);
+
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		ret = irq_of_parse_and_map(pdev->dev.of_node, 1);
+		if (ret == 0)
+			dev_warn(pcie->dev, "cannot get msi intr; MSI disabled\n");
+		else
+			pcie->msi.irq = ret;
+	}
+
+	for (i = 0; i < pcie->num_out_wins; i++) {
+		struct brcm_window *w = &pcie->out_wins[i];
+		w->info = (u32) of_read_ulong(ranges + 0, 1);
+		w->pci_addr = of_read_number(ranges + 1, 2);
+		w->cpu_addr = of_translate_address(dn, ranges + 3);
+		w->size = of_read_number(ranges + pna + 3, 2);
+		ranges += np;
+
+		w->pcie_iomem_res.name	= "External PCIe MEM";
+		w->pcie_iomem_res.flags	= IORESOURCE_MEM;
+		w->pcie_iomem_res.start	= w->cpu_addr;
+		w->pcie_iomem_res.end	= w->cpu_addr + w->size - 1;
+
+		/* Request memory region resources. */
+		if (request_resource(&iomem_resource, &w->pcie_iomem_res)) {
+			dev_err(&pdev->dev,
+				"request PCIe memory resource failed\n");
+			return -EIO;
+		}
+	}
+
+	/*
+	 * Starts PCIe link negotiation immediately at kernel boot time.  The
+	 * RC is supposed to give the endpoint device 100ms to settle down
+	 * before attempting configuration accesses.  So we let the link
+	 * negotiation happen in the background instead of busy-waiting.
+	 */
+	brcm_pcie_setup_early(pcie);
+	list_add_tail(&pcie->list, &brcm_pcie);
+	brcm_num_pci_controllers++;
+
+	return 0;
+}
+
+
+static const struct of_device_id brcm_pci_match[] = {
+	{ .compatible = "brcm,pci-plat-dev" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcm_pci_match);
+
+
+static struct platform_driver __refdata brcm_pci_driver = {
+	.probe = brcm_pci_probe,
+	.driver = {
+		.name = "brcm-pci",
+		.owner = THIS_MODULE,
+		.of_match_table = brcm_pci_match,
+	},
+};
+
+
+int __init brcm_pcibios_init(void)
+{
+	int ret;
+
+	INIT_LIST_HEAD(&brcm_pcie);
+	ret = platform_driver_probe(&brcm_pci_driver, brcm_pci_probe);
+	if (!ret && brcm_num_pci_controllers > 0) {
+		void **private_data;
+		struct brcm_pcie *pcie;
+		int i = 0;
+
+		brcm_pcie_hw.nr_controllers = brcm_num_pci_controllers;
+		if (IS_ENABLED(CONFIG_PM))
+			register_syscore_ops(&pcie_pm_ops);
+
+		private_data = kzalloc(brcm_num_pci_controllers
+				       * sizeof(void *), GFP_KERNEL);
+		if (!private_data)
+			return -ENOMEM;
+		list_for_each_entry(pcie, &brcm_pcie, list)
+			private_data[i++] = pcie;
+		BUG_ON(i != brcm_num_pci_controllers);
+		brcm_pcie_hw.private_data = private_data;
+		pci_common_init(&brcm_pcie_hw);
+		kfree(brcm_pcie_hw.private_data);
+		brcm_pcie_hw.private_data = NULL;
+	}
+	return ret;
+}
+
+
+fs_initcall(brcm_pcibios_init);
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
new file mode 100644
index 000000000000..0be00966a6d4
--- /dev/null
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -0,0 +1,382 @@
+/*
+ * Broadcom STB CPU SMP and hotplug support for ARM
+ *
+ * Copyright (C) 2013-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/mach-types.h>
+#include <asm/smp_plat.h>
+
+#include "headsmp-brcmstb.h"
+
+enum {
+	ZONE_MAN_CLKEN_MASK		= BIT(0),
+	ZONE_MAN_RESET_CNTL_MASK	= BIT(1),
+	ZONE_MAN_MEM_PWR_MASK		= BIT(4),
+	ZONE_RESERVED_1_MASK		= BIT(5),
+	ZONE_MAN_ISO_CNTL_MASK		= BIT(6),
+	ZONE_MANUAL_CONTROL_MASK	= BIT(7),
+	ZONE_PWR_DN_REQ_MASK		= BIT(9),
+	ZONE_PWR_UP_REQ_MASK		= BIT(10),
+	ZONE_BLK_RST_ASSERT_MASK	= BIT(12),
+	ZONE_PWR_OFF_STATE_MASK		= BIT(25),
+	ZONE_PWR_ON_STATE_MASK		= BIT(26),
+	ZONE_DPG_PWR_STATE_MASK		= BIT(28),
+	ZONE_MEM_PWR_STATE_MASK		= BIT(29),
+	ZONE_RESET_STATE_MASK		= BIT(31),
+	CPU0_PWR_ZONE_CTRL_REG		= 1,
+	CPU_RESET_CONFIG_REG		= 2,
+};
+
+static void __iomem *cpubiuctrl_block;
+static void __iomem *hif_cont_block;
+static u32 cpu0_pwr_zone_ctrl_reg;
+static u32 cpu_rst_cfg_reg;
+static u32 hif_cont_reg;
+
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
+ * one or more cache may be disabled, we must flush to ensure coherency. We
+ * cannot use traditionl completion structures or spinlocks as they rely on
+ * coherency.
+ */
+static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
+
+static int per_cpu_sw_state_rd(u32 cpu)
+{
+	sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+	return per_cpu(per_cpu_sw_state, cpu);
+}
+
+/*
+ * BIG WARNING: this function is copy-and-paste inlined into brcmstb_cpu_die(),
+ * to prevent touching the stack there.
+ */
+static void per_cpu_sw_state_wr(u32 cpu, int val)
+{
+	dmb();
+	per_cpu(per_cpu_sw_state, cpu) = val;
+	sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+}
+#else
+static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
+#endif
+
+static void __iomem *pwr_ctrl_get_base(u32 cpu)
+{
+	void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
+	base += (cpu_logical_map(cpu) * 4);
+	return base;
+}
+
+static u32 pwr_ctrl_rd(u32 cpu)
+{
+	void __iomem *base = pwr_ctrl_get_base(cpu);
+	return readl_relaxed(base);
+}
+
+static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask)
+{
+	void __iomem *base = pwr_ctrl_get_base(cpu);
+	writel((readl(base) & mask) | val, base);
+}
+
+static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask)
+{
+	void __iomem *base = pwr_ctrl_get_base(cpu);
+	writel((readl(base) & mask) & ~val, base);
+}
+
+#define POLL_TMOUT_MS 500
+static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask)
+{
+	const unsigned long timeo = jiffies + msecs_to_jiffies(POLL_TMOUT_MS);
+	u32 tmp;
+
+	do {
+		tmp = pwr_ctrl_rd(cpu) & mask;
+		if (!set == !tmp)
+			return 0;
+	} while (time_before(jiffies, timeo));
+
+	tmp = pwr_ctrl_rd(cpu) & mask;
+	if (!set == !tmp)
+		return 0;
+
+	return -ETIMEDOUT;
+}
+
+static void cpu_rst_cfg_set(u32 cpu, int set)
+{
+	u32 val;
+	val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
+	if (set)
+		val |= BIT(cpu_logical_map(cpu));
+	else
+		val &= ~BIT(cpu_logical_map(cpu));
+	writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
+}
+
+static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
+{
+	const int reg_ofs = cpu_logical_map(cpu) * 8;
+	writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
+	writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
+}
+
+static void brcmstb_cpu_boot(u32 cpu)
+{
+	/* Mark this CPU as "up" */
+	per_cpu_sw_state_wr(cpu, 1);
+
+	/*
+	 * Set the reset vector to point to the secondary_startup
+	 * routine
+	 */
+	cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
+
+	/* Unhalt the cpu */
+	cpu_rst_cfg_set(cpu, 0);
+}
+
+static void brcmstb_cpu_power_on(u32 cpu)
+{
+	/*
+	 * The secondary cores power was cut, so we must go through
+	 * power-on initialization.
+	 */
+	pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, 0xffffff00);
+	pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
+	pwr_ctrl_set(cpu, ZONE_RESERVED_1_MASK, -1);
+
+	pwr_ctrl_set(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
+
+	if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_MEM_PWR_STATE_MASK))
+		panic("ZONE_MEM_PWR_STATE_MASK set timeout");
+
+	pwr_ctrl_set(cpu, ZONE_MAN_CLKEN_MASK, -1);
+
+	if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_DPG_PWR_STATE_MASK))
+		panic("ZONE_DPG_PWR_STATE_MASK set timeout");
+
+	pwr_ctrl_clr(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
+	pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
+}
+
+static int brcmstb_cpu_get_power_state(u32 cpu)
+{
+	int tmp = pwr_ctrl_rd(cpu);
+	return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+static void __ref brcmstb_cpu_die(u32 cpu)
+{
+	v7_exit_coherency_flush(all);
+
+	/*
+	 * NOTE: Inlined version of per_cpu_sw_state_wr(). The barriers and
+	 * sev() are superfluous.
+	 *
+	 * FIXME: See SWLINUX-3349. Apparently this call site must not touch
+	 * the stack, as this sometimes returns stale data, causing a
+	 * return-to-garbage error.
+	 */
+	per_cpu(per_cpu_sw_state, cpu) = 0;
+	sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
+
+	/* Sit and wait to die */
+	wfi();
+
+	/* We should never get here... */
+	while (1)
+		;
+}
+
+static int brcmstb_cpu_kill(u32 cpu)
+{
+	/*
+	 * Ordinarily, the hardware forbids power-down of CPU0 (which is good
+	 * because it is the boot CPU), but this is not true when using BPCM
+	 * manual mode.  Consequently, we must avoid turning off CPU0 here to
+	 * ensure that TI2C master reset will work.
+	 */
+	if (cpu == 0) {
+		pr_warn("SMP: refusing to power off CPU0\n");
+		return 1;
+	}
+
+	while (per_cpu_sw_state_rd(cpu))
+		;
+
+	pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
+	pwr_ctrl_clr(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
+	pwr_ctrl_clr(cpu, ZONE_MAN_CLKEN_MASK, -1);
+	pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
+	pwr_ctrl_clr(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
+
+	if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_MEM_PWR_STATE_MASK))
+		panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
+
+	pwr_ctrl_clr(cpu, ZONE_RESERVED_1_MASK, -1);
+
+	if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_DPG_PWR_STATE_MASK))
+		panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
+
+	/* Flush pipeline before resetting CPU */
+	mb();
+
+	/* Assert reset on the CPU */
+	cpu_rst_cfg_set(cpu, 1);
+
+	return 1;
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
+{
+	int rc = 0;
+	char *name;
+	struct device_node *syscon_np = NULL;
+
+	name = "syscon-cpu";
+
+	syscon_np = of_parse_phandle(np, name, 0);
+	if (!syscon_np) {
+		pr_err("can't find phandle %s\n", name);
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+	cpubiuctrl_block = of_iomap(syscon_np, 0);
+	if (!cpubiuctrl_block) {
+		pr_err("iomap failed for cpubiuctrl_block\n");
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+	rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
+					&cpu0_pwr_zone_ctrl_reg);
+	if (rc) {
+		pr_err("failed to read 1st entry from %s property (%d)\n", name,
+			rc);
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+	rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
+					&cpu_rst_cfg_reg);
+	if (rc) {
+		pr_err("failed to read 2nd entry from %s property (%d)\n", name,
+			rc);
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+cleanup:
+	of_node_put(syscon_np);
+	return rc;
+}
+
+static int __init setup_hifcont_regs(struct device_node *np)
+{
+	int rc = 0;
+	char *name;
+	struct device_node *syscon_np = NULL;
+
+	name = "syscon-cont";
+
+	syscon_np = of_parse_phandle(np, name, 0);
+	if (!syscon_np) {
+		pr_err("can't find phandle %s\n", name);
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+	hif_cont_block = of_iomap(syscon_np, 0);
+	if (!hif_cont_block) {
+		pr_err("iomap failed for hif_cont_block\n");
+		rc = -EINVAL;
+		goto cleanup;
+	}
+
+	/* Offset is at top of hif_cont_block */
+	hif_cont_reg = 0;
+
+cleanup:
+	of_node_put(syscon_np);
+	return rc;
+}
+
+static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+	int rc;
+	struct device_node *np;
+	char *name;
+
+	name = "brcm,brcmstb-smpboot";
+	np = of_find_compatible_node(NULL, NULL, name);
+	if (!np) {
+		pr_err("can't find compatible node %s\n", name);
+		return;
+	}
+
+	rc = setup_hifcpubiuctrl_regs(np);
+	if (rc)
+		return;
+
+	rc = setup_hifcont_regs(np);
+	if (rc)
+		return;
+}
+
+static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	/* Missing the brcm,brcmstb-smpboot DT node? */
+	if (!cpubiuctrl_block || !hif_cont_block)
+		return -ENODEV;
+
+	/* Bring up power to the core if necessary */
+	if (brcmstb_cpu_get_power_state(cpu) == 0)
+		brcmstb_cpu_power_on(cpu);
+
+	brcmstb_cpu_boot(cpu);
+
+	return 0;
+}
+
+static struct smp_operations brcmstb_smp_ops __initdata = {
+	.smp_prepare_cpus	= brcmstb_cpu_ctrl_setup,
+	.smp_boot_secondary	= brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_kill		= brcmstb_cpu_kill,
+	.cpu_die		= brcmstb_cpu_die,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
index 0ec9bb48fab9..e96923a3017b 100644
--- a/arch/arm/mach-ep93xx/crunch-bits.S
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
@@ -16,6 +16,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 #include <mach/ep93xx-regs.h>
 
 /*
@@ -62,14 +63,16 @@
  * r9  = ret_from_exception
  * lr  = undefined instr exit
  *
- * called from prefetch exception handler with interrupts disabled
+ * called from prefetch exception handler with interrupts enabled
  */
 ENTRY(crunch_task_enable)
+	inc_preempt_count r10, r3
+
 	ldr	r8, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr
 
 	ldr	r1, [r8, #0x80]
 	tst	r1, #0x00800000			@ access to crunch enabled?
-	movne	pc, lr				@ if so no business here
+	bne	2f				@ if so no business here
 	mov	r3, #0xaa			@ unlock syscon swlock
 	str	r3, [r8, #0xc0]
 	orr	r1, r1, #0x00800000		@ enable access to crunch
@@ -142,7 +145,7 @@ crunch_save:
 
 	teq		r0, #0				@ anything to load?
 	cfldr64eq	mvdx0, [r1, #CRUNCH_MVDX0]	@ mvdx0 was clobbered
-	moveq		pc, lr
+	beq		1f
 
 crunch_load:
 	cfldr64		mvdx0, [r0, #CRUNCH_DSPSC]	@ load status word
@@ -190,6 +193,11 @@ crunch_load:
 	cfldr64		mvdx14, [r0, #CRUNCH_MVDX14]
 	cfldr64		mvdx15, [r0, #CRUNCH_MVDX15]
 
+1:
+#ifdef CONFIG_PREEMPT_COUNT
+	get_thread_info r10
+#endif
+2:	dec_preempt_count r10, r3
 	mov	pc, lr
 
 /*
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 627f16f0e9d1..1f5ee857c3dd 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -30,7 +30,6 @@ diag_reg_offset:
 	.endm
 
 ENTRY(v7_secondary_startup)
-	bl	v7_invalidate_l1
 	set_diag_reg
 	b	secondary_startup
 ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index d86fe33c5f53..209d9fc5c16c 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -15,7 +15,6 @@
  * ready for them to initialise.
  */
 ENTRY(sirfsoc_secondary_startup)
-	bl v7_invalidate_l1
         mrc     p15, 0, r0, c0, c0, 5
         and     r0, r0, #15
         adr     r4, 1f
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index f45dde701d7b..38c7c52d5c64 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -27,7 +27,7 @@
  * Boot code for secondary CPUs.
  *
  * First we turn on L1 cache coherency for our CPU. Then we jump to
- * shmobile_invalidate_start that invalidates the cache and hands over control
+ * secondary_startup that invalidates the cache and hands over control
  * to the common ARM startup code.
  */
 ENTRY(shmobile_boot_scu)
@@ -41,7 +41,7 @@ ENTRY(shmobile_boot_scu)
 	bic	r2, r2, r3		@ Clear bits of our CPU (Run Mode)
 	str	r2, [r0, #8]		@ write back
 
-	b	shmobile_invalidate_start
+	b	secondary_startup
 ENDPROC(shmobile_boot_scu)
 
 	.text
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index e5be5c88644b..e44b3720330b 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,11 +14,6 @@
 #include <linux/init.h>
 #include <asm/memory.h>
 
-ENTRY(shmobile_invalidate_start)
-	bl	v7_invalidate_l1
-	b	secondary_startup
-ENDPROC(shmobile_invalidate_start)
-
 /*
  * Reset vector for secondary CPUs.
  * This will be mapped at address 0 by SBAR register.
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 1da5a72d9642..cab49f311183 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -137,7 +137,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	/* For this particular CPU register boot vector */
-	shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
+	shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
 
 	return apmu_wrap(cpu, apmu_power_on);
 }
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f719ffb..4a7c387f4e22 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -28,7 +28,6 @@
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
 
-extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index b143f946bb79..e615a2586928 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -26,8 +26,3 @@ ENTRY(secondary_trampoline)
 	bx	r1
 
 ENTRY(secondary_trampoline_end)
-
-ENTRY(socfpga_secondary_startup)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 5356a72bc8ce..91e298644498 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -36,15 +36,15 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	if (cpu1start_addr) {
 		memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
 
-		__raw_writel(virt_to_phys(socfpga_secondary_startup),
-			(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
+		writel(virt_to_phys(secondary_startup),
+		       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
 
 		flush_cache_all();
 		smp_wmb();
 		outer_clean_range(0, trampoline_size);
 
 		/* This will release CPU #1 out of reset.*/
-		__raw_writel(0, rst_manager_base_addr + 0x10);
+		writel(0, rst_manager_base_addr + 0x10);
 	}
 
 	return 0;
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 019bb1758662..6e8865527e87 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= cpuidle-tegra30.o
 endif
-obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= tegra114_speedo.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
deleted file mode 100644
index 2072e7322c39..000000000000
--- a/arch/arm/mach-tegra/headsmp.S
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-#include "sleep.h"
-
-        .section ".text.head", "ax"
-
-ENTRY(tegra_secondary_startup)
-        check_cpu_part_num 0xc09, r8, r9
-        bleq    v7_invalidate_l1
-        b       secondary_startup
-ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 146fe8e0ae7c..acc70219d1e4 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -95,7 +95,7 @@ void __init tegra_cpu_reset_handler_init(void)
 	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
 		*((u32 *)cpu_possible_mask);
 	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
-		virt_to_phys((void *)tegra_secondary_startup);
+		virt_to_phys((void *)secondary_startup);
 #endif
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index 76a93434c6ee..0aee0129f8d7 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
 void __tegra_cpu_reset_handler_start(void);
 void __tegra_cpu_reset_handler(void);
 void __tegra_cpu_reset_handler_end(void);
-void tegra_secondary_startup(void);
 
 #ifdef CONFIG_PM_SLEEP
 #define tegra_cpu_lp1_mask \
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index c22c92cea8cb..3040d219570f 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void zynq_secondary_startup(void);
-
 extern int zynq_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index 57a32869f0aa..451520e41f22 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -19,8 +19,3 @@ zynq_secondary_trampoline_jump:
 .globl zynq_secondary_trampoline_end
 zynq_secondary_trampoline_end:
 ENDPROC(zynq_secondary_trampoline)
-
-ENTRY(zynq_secondary_startup)
-	bl	v7_invalidate_l1
-	b	secondary_startup
-ENDPROC(zynq_secondary_startup)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index abc82ef085c1..1f6102abd5b1 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
 }
 EXPORT_SYMBOL(zynq_cpun_start);
 
-static int zynq_boot_secondary(unsigned int cpu,
-						struct task_struct *idle)
+static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
+	return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
 }
 
 /*
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e9c290c21744..f4ab655a6a66 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -853,6 +853,14 @@ config OUTER_CACHE_SYNC
 	  The outer cache has a outer_cache_fns.sync function pointer
 	  that can be used to drain the write buffer of the outer cache.
 
+config CACHE_B15_RAC
+	bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
+	depends on ARCH_BRCMSTB
+	default y
+	help
+	  This option enables the Broadcom Brahma-B15 read-ahead cache
+	  controller. If disabled, the read-ahead cache remains off.
+
 config CACHE_FEROCEON_L2
 	bool "Enable the Feroceon L2 cache controller"
 	depends on ARCH_KIRKWOOD || ARCH_MV78XX0
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f39ce2f841f..d66ff37f0ac4 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_CPU_V7M)		+= proc-v7m.o
 AFLAGS_proc-v6.o	:=-Wa,-march=armv6
 AFLAGS_proc-v7.o	:=-Wa,-march=armv7-a
 
+obj-$(CONFIG_CACHE_B15_RAC)	+= cache-b15-rac.o
 obj-$(CONFIG_CACHE_FEROCEON_L2)	+= cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)	+= cache-xsc3l2.o
diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c
new file mode 100644
index 000000000000..19481c359d0f
--- /dev/null
+++ b/arch/arm/mm/cache-b15-rac.c
@@ -0,0 +1,368 @@
+/*
+ * Broadcom Brahma-B15 CPU read-ahead cache management functions
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of_address.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
+#include <linux/syscore_ops.h>
+#include <linux/reboot.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-b15-rac.h>
+
+extern void v7_flush_kern_cache_all(void);
+extern void v7_flush_kern_cache_louis(void);
+extern void v7_flush_icache_all(void);
+
+/* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */
+#define RAC_CONFIG0_REG			(0x78)
+#define  RACENPREF_MASK			(0x3)
+#define  RACPREFINST_SHIFT		(0)
+#define  RACENINST_SHIFT		(2)
+#define  RACPREFDATA_SHIFT		(4)
+#define  RACENDATA_SHIFT		(6)
+#define  RAC_CPU_SHIFT			(8)
+#define  RACCFG_MASK			(0xff)
+#define RAC_CONFIG1_REG			(0x7c)
+#define RAC_FLUSH_REG			(0x80)
+#define  FLUSH_RAC			(1 << 0)
+
+/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
+#define RAC_DATA_INST_EN_MASK		(1 << RACPREFINST_SHIFT | \
+					 RACENPREF_MASK << RACENINST_SHIFT | \
+					 1 << RACPREFDATA_SHIFT | \
+					 RACENPREF_MASK << RACENDATA_SHIFT)
+
+#define RAC_ENABLED			(1 << 0)
+/* Special state where we want to bypass the spinlock and call directly
+ * into the v7 cache maintenance operations during suspend/resume
+ */
+#define RAC_SUSPENDED			(1 << 1)
+
+static void __iomem *b15_rac_base;
+static DEFINE_SPINLOCK(rac_lock);
+static u32 rac_config0_reg;
+
+/* Initialization flag to avoid checking for b15_rac_base, and to prevent
+ * multi-platform kernels from crashing here as well.
+ */
+static unsigned long b15_rac_flags;
+
+static inline u32 __b15_rac_disable(void)
+{
+	u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+	__raw_writel(0, b15_rac_base + RAC_CONFIG0_REG);
+	dmb();
+	return val;
+}
+
+static inline void __b15_rac_flush(void)
+{
+	u32 reg;
+
+	__raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG);
+	do {
+		/* This dmb() is required to force the Bus Interface Unit
+		 * to clean oustanding writes, and forces an idle cycle
+		 * to be inserted.
+		 */
+		dmb();
+		reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG);
+	} while (reg & FLUSH_RAC);
+}
+
+static inline u32 b15_rac_disable_and_flush(void)
+{
+	u32 reg;
+
+	reg = __b15_rac_disable();
+	__b15_rac_flush();
+	return reg;
+}
+
+static inline void __b15_rac_enable(u32 val)
+{
+	__raw_writel(val, b15_rac_base + RAC_CONFIG0_REG);
+	/* dsb() is required here to be consistent with __flush_icache_all() */
+	dsb();
+}
+
+#define BUILD_RAC_CACHE_OP(name, bar)				\
+void b15_flush_##name(void)					\
+{								\
+	unsigned int do_flush;					\
+	u32 val = 0;						\
+								\
+	if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) {		\
+		v7_flush_##name();				\
+		bar;						\
+		return;						\
+	}							\
+								\
+	spin_lock(&rac_lock);					\
+	do_flush = test_bit(RAC_ENABLED, &b15_rac_flags);	\
+	if (do_flush)						\
+		val = b15_rac_disable_and_flush();		\
+	v7_flush_##name();					\
+	if (!do_flush)						\
+		bar;						\
+	else							\
+		__b15_rac_enable(val);				\
+	spin_unlock(&rac_lock);					\
+}
+
+#define nobarrier
+
+/* The readahead cache present in the Brahma-B15 CPU is a special piece of
+ * hardware after the integrated L2 cache of the B15 CPU complex whose purpose
+ * is to prefetch instruction and/or data with a line size of either 64 bytes
+ * or 256 bytes. The rationale is that the data-bus of the CPU interface is
+ * optimized for 256-bytes transactions, and enabling the readahead cache
+ * provides a significant performance boost we want it enabled (typically
+ * twice the performance for a memcpy benchmark application).
+ *
+ * The readahead cache is transparent for Modified Virtual Addresses
+ * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
+ * DCCIMVAC.
+ *
+ * It is however not transparent for the following cache maintenance
+ * operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely
+ * what we are patching here with our BUILD_RAC_CACHE_OP here.
+ */
+
+BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier);
+BUILD_RAC_CACHE_OP(kern_cache_louis, nobarrier);
+BUILD_RAC_CACHE_OP(icache_all, dsb());
+
+static void b15_rac_enable(void)
+{
+	unsigned int cpu;
+	u32 enable = 0;
+
+	for_each_possible_cpu(cpu)
+		enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT));
+
+	b15_rac_disable_and_flush();
+	__b15_rac_enable(enable);
+}
+
+static int b15_rac_reboot_notifier(struct notifier_block *nb,
+				   unsigned long action,
+				   void *data)
+{
+	/* During kexec, we are not yet migrated on the boot CPU, so we need to
+	 * make sure we are SMP safe here. Once the RAC is disabled, flag it as
+	 * suspended such that the hotplug notifier returns early.
+	 */
+	if (action == SYS_RESTART) {
+		spin_lock(&rac_lock);
+		b15_rac_disable_and_flush();
+		clear_bit(RAC_ENABLED, &b15_rac_flags);
+		set_bit(RAC_SUSPENDED, &b15_rac_flags);
+		spin_unlock(&rac_lock);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block b15_rac_reboot_nb = {
+	.notifier_call	= b15_rac_reboot_notifier,
+};
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void b15_rac_hotplug_start(void)
+{
+	/* Indicate that we are starting a hotplug procedure */
+	clear_bit(RAC_ENABLED, &b15_rac_flags);
+
+	/* Disable the readahead cache and save its value to a global */
+	rac_config0_reg = b15_rac_disable_and_flush();
+}
+
+static void b15_rac_hotplug_end(void)
+{
+	/* And enable it */
+	__b15_rac_enable(rac_config0_reg);
+	set_bit(RAC_ENABLED, &b15_rac_flags);
+}
+
+/* The CPU hotplug case is the most interesting one, we basically need to make
+ * sure that the RAC is disabled for the entire system prior to having a CPU
+ * die, in particular prior to this dying CPU having exited the coherency
+ * domain.
+ *
+ * Once this CPU is marked dead, we can safely re-enable the RAC for the
+ * remaining CPUs in the system which are still online.
+ *
+ * Offlining a CPU is the problematic case, onlining a CPU is not much of an
+ * issue since the CPU and its cache-level hierarchy will start filling with
+ * the RAC disabled, so L1 and L2 only.
+ *
+ * In this function, we should NOT have to verify any unsafe setting/condition
+ * b15_rac_base:
+ *
+ *   It is protected by the RAC_ENABLED flag which is cleared by default, and
+ *   being cleared when initial procedure is done. b15_rac_base had been set at
+ *   that time.
+ *
+ * RAC_ENABLED:
+ *   There is a small timing windows, in b15_rac_init(), between
+ *      register_cpu_notifier(&b15_rac_cpu_nb);
+ *      ...
+ *      set RAC_ENABLED
+ *   However, there is no hotplug activity based on the Linux booting procedure.
+ *
+ * Regarding the notification actions, we will receive CPU_DOWN_PREPARE,
+ * CPU_DOWN_FAILED, CPU_DYING, CPU_DEAD, and CPU_POST_DEAD notification (see
+ * _cpu_down() for detail).
+ *
+ * Since we have to disable RAC for all cores, we keep RAC on as long as as
+ * possible (disable it as late as possible) to gain the cache benefit.
+ *
+ * Thus, CPU_DYING/CPU_DEAD pair are chosen.
+ *
+ * We are choosing not do disable the RAC on a per-CPU basis, here, if we did
+ * we would want to consider disabling it as early as possible to benefit the
+ * other active CPUs.
+ */
+static int b15_rac_cpu_notify(struct notifier_block *self,
+			      unsigned long action, void *hcpu)
+{
+	action &= ~CPU_TASKS_FROZEN;
+
+	if (action != CPU_DYING && action != CPU_DOWN_FAILED &&
+	    action != CPU_DEAD)
+		return NOTIFY_OK;
+
+	/* During kexec/reboot, the RAC is disabled via the reboot notifier
+	 * return early here.
+	 */
+	if (test_bit(RAC_SUSPENDED, &b15_rac_flags))
+		return NOTIFY_DONE;
+
+	spin_lock(&rac_lock);
+	switch (action) {
+	/* called on the dying CPU, exactly what we want */
+	case CPU_DYING:
+		b15_rac_hotplug_start();
+		break;
+
+	/* called on a non-dying CPU, what we want too */
+	case CPU_DOWN_FAILED:
+	case CPU_DEAD:
+		b15_rac_hotplug_end();
+		break;
+	}
+	spin_unlock(&rac_lock);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block b15_rac_cpu_nb = {
+	.notifier_call	= b15_rac_cpu_notify,
+};
+#endif /* CONFIG_HOTPLUG_CPU */
+
+#ifdef CONFIG_PM_SLEEP
+static int b15_rac_suspend(void)
+{
+	/* Suspend the read-ahead cache oeprations, forcing our cache
+	 * implementation to fallback to the regular ARMv7 calls.
+	 *
+	 * We are guaranteed to be running on the boot CPU at this point and
+	 * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy
+	 * here.
+	 */
+	rac_config0_reg = b15_rac_disable_and_flush();
+	set_bit(RAC_SUSPENDED, &b15_rac_flags);
+
+	return 0;
+}
+
+static void b15_rac_resume(void)
+{
+	/* Coming out of a S3 suspend/resume cycle, the read-ahead cache
+	 * register RAC_CONFIG0_REG will be restored to its default value, make
+	 * sure we re-enable it and set the enable flag, we are also guaranteed
+	 * to run on the boot CPU, so not racy again.
+	 */
+	__b15_rac_enable(rac_config0_reg);
+	clear_bit(RAC_SUSPENDED, &b15_rac_flags);
+}
+
+static struct syscore_ops b15_rac_syscore_ops = {
+	.suspend	= b15_rac_suspend,
+	.resume		= b15_rac_resume,
+};
+#endif
+
+static int __init b15_rac_init(void)
+{
+	struct device_node *dn;
+	int ret = 0, cpu;
+	u32 reg, en_mask = 0;
+
+	dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+	if (!dn)
+		return -ENODEV;
+
+	if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
+		goto out;
+
+	b15_rac_base = of_iomap(dn, 0);
+	if (!b15_rac_base) {
+		pr_err("failed to remap BIU control base\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = register_reboot_notifier(&b15_rac_reboot_nb);
+	if (ret) {
+		pr_err("failed to register reboot notifier\n");
+		iounmap(b15_rac_base);
+		goto out;
+	}
+
+#ifdef CONFIG_HOTPLUG_CPU
+	ret = register_cpu_notifier(&b15_rac_cpu_nb);
+	if (ret) {
+		pr_err("failed to register notifier block\n");
+		iounmap(b15_rac_base);
+		unregister_reboot_notifier(&b15_rac_reboot_nb);
+		goto out;
+	}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&b15_rac_syscore_ops);
+#endif
+
+	spin_lock(&rac_lock);
+	reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+	for_each_possible_cpu(cpu)
+		en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT));
+	WARN(reg & en_mask, "Read-ahead cache not previously disabled\n");
+
+	b15_rac_enable();
+	set_bit(RAC_ENABLED, &b15_rac_flags);
+	spin_unlock(&rac_lock);
+
+	pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n",
+		b15_rac_base + RAC_CONFIG0_REG);
+
+out:
+	of_node_put(dn);
+	return ret;
+}
+arch_initcall(b15_rac_init);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 778bcf88ee79..c5e59e5678eb 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -15,6 +15,7 @@
 #include <asm/assembler.h>
 #include <asm/errno.h>
 #include <asm/unwind.h>
+#include <asm/hardware/cache-b15-rac.h>
 
 #include "proc-macros.S"
 
@@ -446,3 +447,23 @@ ENDPROC(v7_dma_unmap_area)
 
 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
 	define_cache_functions v7
+
+	/* The Broadcom Brahma-B15 read-ahead cache requires some modifications
+	 * to the v7_cache_fns, we only override the ones we need
+	 */
+#ifndef CONFIG_CACHE_B15_RAC
+	globl_equ	b15_flush_icache_all,		v7_flush_icache_all
+	globl_equ	b15_flush_kern_cache_all,	v7_flush_kern_cache_all
+	globl_equ	b15_flush_kern_cache_louis,	v7_flush_kern_cache_louis
+#endif
+	globl_equ	b15_flush_user_cache_all,	v7_flush_user_cache_all
+	globl_equ	b15_flush_user_cache_range,	v7_flush_user_cache_range
+	globl_equ	b15_coherent_kern_range,	v7_coherent_kern_range
+	globl_equ	b15_coherent_user_range,	v7_coherent_user_range
+	globl_equ	b15_flush_kern_dcache_area,	v7_flush_kern_dcache_area
+
+	globl_equ	b15_dma_map_area,		v7_dma_map_area
+	globl_equ	b15_dma_unmap_area,		v7_dma_unmap_area
+	globl_equ	b15_dma_flush_range,		v7_dma_flush_range
+
+	define_cache_functions b15
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 4370933f16cd..845769e41332 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -180,36 +180,46 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
 	u64 asid = atomic64_read(&mm->context.id);
 	u64 generation = atomic64_read(&asid_generation);
 
-	if (asid != 0 && is_reserved_asid(asid)) {
+	if (asid != 0) {
 		/*
-		 * Our current ASID was active during a rollover, we can
-		 * continue to use it and this was just a false alarm.
+		 * If our current ASID was active during a rollover, we
+		 * can continue to use it and this was just a false alarm.
 		 */
-		asid = generation | (asid & ~ASID_MASK);
-	} else {
+		if (is_reserved_asid(asid))
+			return generation | (asid & ~ASID_MASK);
+
 		/*
-		 * Allocate a free ASID. If we can't find one, take a
-		 * note of the currently active ASIDs and mark the TLBs
-		 * as requiring flushes. We always count from ASID #1,
-		 * as we reserve ASID #0 to switch via TTBR0 and to
-		 * avoid speculative page table walks from hitting in
-		 * any partial walk caches, which could be populated
-		 * from overlapping level-1 descriptors used to map both
-		 * the module area and the userspace stack.
+		 * We had a valid ASID in a previous life, so try to re-use
+		 * it if possible.,
 		 */
-		asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
-		if (asid == NUM_USER_ASIDS) {
-			generation = atomic64_add_return(ASID_FIRST_VERSION,
-							 &asid_generation);
-			flush_context(cpu);
-			asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
-		}
-		__set_bit(asid, asid_map);
-		cur_idx = asid;
-		asid |= generation;
-		cpumask_clear(mm_cpumask(mm));
+		asid &= ~ASID_MASK;
+		if (!__test_and_set_bit(asid, asid_map))
+			goto bump_gen;
+	}
+
+	/*
+	 * Allocate a free ASID. If we can't find one, take a note of the
+	 * currently active ASIDs and mark the TLBs as requiring flushes.
+	 * We always count from ASID #1, as we reserve ASID #0 to switch
+	 * via TTBR0 and to avoid speculative page table walks from hitting
+	 * in any partial walk caches, which could be populated from
+	 * overlapping level-1 descriptors used to map both the module
+	 * area and the userspace stack.
+	 */
+	asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
+	if (asid == NUM_USER_ASIDS) {
+		generation = atomic64_add_return(ASID_FIRST_VERSION,
+						 &asid_generation);
+		flush_context(cpu);
+		asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
 	}
 
+	__set_bit(asid, asid_map);
+	cur_idx = asid;
+
+bump_gen:
+	asid |= generation;
+	cpumask_clear(mm_cpumask(mm));
 	return asid;
 }
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 887b19e915ee..7aa4683ced64 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -26,6 +26,7 @@
 #include <linux/io.h>
 #include <linux/vmalloc.h>
 #include <linux/sizes.h>
+#include <linux/cma.h>
 
 #include <asm/memory.h>
 #include <asm/highmem.h>
@@ -393,7 +394,7 @@ static int __init atomic_pool_init(void)
 	if (!pages)
 		goto no_pages;
 
-	if (IS_ENABLED(CONFIG_DMA_CMA))
+	if (dev_get_cma_area(NULL))
 		ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
 					      atomic_pool_init);
 	else
@@ -713,7 +714,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 		addr = __alloc_simple_buffer(dev, size, gfp, &page);
 	else if (!(gfp & __GFP_WAIT))
 		addr = __alloc_from_pool(size, &page);
-	else if (!IS_ENABLED(CONFIG_DMA_CMA))
+	else if (!dev_get_cma_area(dev))
 		addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
 	else
 		addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
@@ -802,7 +803,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 		__dma_free_buffer(page, size);
 	} else if (__free_from_pool(cpu_addr, size)) {
 		return;
-	} else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
+	} else if (!dev_get_cma_area(dev)) {
 		__dma_free_remap(cpu_addr, size);
 		__dma_free_buffer(page, size);
 	} else {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 804d61566a53..626fc8b2fd55 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -22,6 +22,7 @@
 #include <linux/memblock.h>
 #include <linux/dma-contiguous.h>
 #include <linux/sizes.h>
+#include <linux/cma.h>
 
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
@@ -122,6 +123,9 @@ void show_mem(unsigned int filter)
 	printk("%d pages of RAM\n", total);
 	printk("%d free pages\n", free);
 	printk("%d reserved pages\n", reserved);
+#ifdef CONFIG_CMA
+	printk("%lu cma reserved pages\n", totalcma_pages);
+#endif
 	printk("%d slab pages\n", slab);
 	printk("%d pages shared\n", shared);
 	printk("%d pages swap cached\n", cached);
@@ -319,10 +323,25 @@ void __init arm_memblock_init(struct meminfo *mi,
 	arm_mm_memblock_reserve();
 	arm_dt_memblock_reserve();
 
+#ifdef CONFIG_BRCMSTB
+	/*
+	 * Moved before platform reserve so that we can find all the
+	 * non-cma, non-bmem reserved areas without implementing interval
+	 * subtraction
+	 */
+	early_init_fdt_scan_reserved_mem();
+
+	/* reserve any platform specific memblock areas */
+	if (mdesc->reserve)
+		mdesc->reserve();
+#else
 	/* reserve any platform specific memblock areas */
 	if (mdesc->reserve)
 		mdesc->reserve();
 
+	early_init_fdt_scan_reserved_mem();
+#endif
+
 	/*
 	 * reserve memory for DMA contigouos allocations,
 	 * must come from DMA area inside low memory
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f15c22e8bcd5..cf625d150ee9 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1028,10 +1028,15 @@ void __init debug_ll_io_init(void)
 static void * __initdata vmalloc_min =
 	(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 
+static bool __initdata brcmstb_did_override_vmalloc;
+
 /*
  * vmalloc=size forces the vmalloc area to be exactly 'size'
  * bytes. This can be used to increase (or decrease) the vmalloc
  * area - the default is 240m.
+ *
+ * NOTE: different default for BRCMSTB with >= 1GiB RAM, see
+ * brcmstb_maybe_increase_vmalloc() below.
  */
 static int __init early_vmalloc(char *arg)
 {
@@ -1052,17 +1057,35 @@ static int __init early_vmalloc(char *arg)
 	}
 
 	vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
+	brcmstb_did_override_vmalloc = true;
 	return 0;
 }
 early_param("vmalloc", early_vmalloc);
 
+static void __init brcmstb_maybe_increase_vmalloc(void)
+{
+#ifdef CONFIG_BRCMSTB
+	if (brcmstb_did_override_vmalloc)
+		return;
+	if (meminfo.bank[0].size > (760 << 20) || meminfo.nr_banks > 1) {
+		vmalloc_min = (void *)(VMALLOC_END - (744 << 20) -
+				VMALLOC_OFFSET);
+	}
+#else
+	return;
+#endif
+}
+
 phys_addr_t arm_lowmem_limit __initdata = 0;
 
 void __init sanity_check_meminfo(void)
 {
 	phys_addr_t memblock_limit = 0;
 	int i, j, highmem = 0;
-	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
+	phys_addr_t vmalloc_limit;
+
+	brcmstb_maybe_increase_vmalloc();
+	vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 1f52915f2b28..f1f3cd255bb5 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -7,7 +7,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
 #define TTB_S		(1 << 1)
 #define TTB_RGN_NC	(0 << 3)
 #define TTB_RGN_OC_WBWA	(1 << 3)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 093eff182d63..f8e8cd6ad209 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -193,6 +193,7 @@ __v7_cr7mp_setup:
 	b	1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
+__v7_b15mp_setup:
 	mov	r10, #0
 1:
 #ifdef CONFIG_SMP
@@ -262,7 +263,7 @@ __v7_pj4b_setup:
 __v7_setup:
 	adr	r12, __v7_setup_stack		@ the local stack
 	stmia	r12, {r0-r5, r7, r9, r11, lr}
-	bl      v7_flush_dcache_louis
+	bl      v7_invalidate_l1
 	ldmia	r12, {r0-r5, r7, r9, r11, lr}
 
 	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
@@ -407,7 +408,7 @@ __v7_setup_stack:
 	/*
 	 * Standard v7 proc info content
 	 */
-.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
 	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -423,7 +424,7 @@ __v7_setup_stack:
 	.long	\proc_fns
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
-	.long	v7_cache_fns
+	.long	\cache_fns
 .endm
 
 #ifndef CONFIG_ARM_LPAE
@@ -492,6 +493,16 @@ __v7_ca15mp_proc_info:
 	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
 	/*
+	 * Broadcom Corporation Brahma-B15 processor.
+	 */
+	.type	__v7_b15mp_proc_info, #object
+__v7_b15mp_proc_info:
+	.long	0x420f00f0
+	.long	0xff0ffff0
+	__v7_proc __v7_b15mp_setup, cache_fns = b15_cache_fns
+	.size	__v7_b15mp_proc_info, . - __v7_b15mp_proc_info
+
+	/*
 	 * Qualcomm Inc. Krait processors.
 	 */
 	.type	__krait_proc_info, #object
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 46e17492fd1f..fe6ca574d093 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -8,9 +8,12 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/init.h>
+#include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
-#include "../kernel/entry-header.S"
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
 
 @ VFP entry point.
 @
@@ -19,15 +22,10 @@
 @  r9  = normal "successful" return address
 @  r10 = this threads thread_info structure
 @  lr  = unrecognised instruction return address
-@  IRQs disabled.
+@  IRQs enabled.
 @
 ENTRY(do_vfp)
-#ifdef CONFIG_PREEMPT_COUNT
-	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
-	add	r11, r4, #1		@ increment it
-	str	r11, [r10, #TI_PREEMPT]
-#endif
-	enable_irq
+	inc_preempt_count r10, r4
  	ldr	r4, .LCvfp
 	ldr	r11, [r10, #TI_CPU]	@ CPU number
 	add	r10, r10, #TI_VFPSTATE	@ r10 = workspace
@@ -35,12 +33,7 @@ ENTRY(do_vfp)
 ENDPROC(do_vfp)
 
 ENTRY(vfp_null_entry)
-#ifdef CONFIG_PREEMPT_COUNT
-	get_thread_info	r10
-	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
-	sub	r11, r4, #1		@ decrement it
-	str	r11, [r10, #TI_PREEMPT]
-#endif
+	dec_preempt_count_ti r10, r4
 	mov	pc, lr
 ENDPROC(vfp_null_entry)
 
@@ -53,12 +46,7 @@ ENDPROC(vfp_null_entry)
 
 	__INIT
 ENTRY(vfp_testing_entry)
-#ifdef CONFIG_PREEMPT_COUNT
-	get_thread_info	r10
-	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
-	sub	r11, r4, #1		@ decrement it
-	str	r11, [r10, #TI_PREEMPT]
-#endif
+	dec_preempt_count_ti r10, r4
 	ldr	r0, VFP_arch_address
 	str	r0, [r0]		@ set to non-zero value
 	mov	pc, r9			@ we have handled the fault
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 3e5d3115a2a6..be807625ed8c 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -14,10 +14,13 @@
  * r10 points at the start of the private FP workspace in the thread structure
  * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
  */
+#include <linux/init.h>
+#include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
 #include <linux/kern_levels.h>
-#include "../kernel/entry-header.S"
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
 
 	.macro	DBGSTR, str
 #ifdef DEBUG
@@ -179,12 +182,7 @@ vfp_hw_state_valid:
 					@ else it's one 32-bit instruction, so
 					@ always subtract 4 from the following
 					@ instruction address.
-#ifdef CONFIG_PREEMPT_COUNT
-	get_thread_info	r10
-	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
-	sub	r11, r4, #1		@ decrement it
-	str	r11, [r10, #TI_PREEMPT]
-#endif
+	dec_preempt_count_ti r10, r4
 	mov	pc, r9			@ we think we have handled things
 
 
@@ -203,12 +201,7 @@ look_for_VFP_exceptions:
 	@ not recognised by VFP
 
 	DBGSTR	"not VFP"
-#ifdef CONFIG_PREEMPT_COUNT
-	get_thread_info	r10
-	ldr	r4, [r10, #TI_PREEMPT]	@ get preempt count
-	sub	r11, r4, #1		@ decrement it
-	str	r11, [r10, #TI_PREEMPT]
-#endif
+	dec_preempt_count_ti r10, r4
 	mov	pc, lr
 
 process_exception:
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 6e239123d6fe..8503a8aa1c8f 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -5,6 +5,7 @@ platforms += ar7
 platforms += ath79
 platforms += bcm47xx
 platforms += bcm63xx
+platforms += brcmstb
 platforms += cavium-octeon
 platforms += cobalt
 platforms += dec
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 95fa1f1d5c8b..a773a112e4e3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -144,6 +144,11 @@ config BCM63XX
 	help
 	 Support for BCM63XX based boards
 
+config BRCMSTB
+	bool "Broadcom BCM7XXX based boards"
+	help
+	  Support for BCM7XXX based boards
+
 config MIPS_COBALT
 	bool "Cobalt Server"
 	select CEVT_R4K
@@ -315,6 +320,7 @@ config MIPS_MALTA
 	select I8259
 	select MIPS_BONITO64
 	select MIPS_CPU_SCACHE
+	select MIPS_L1_CACHE_SHIFT_6
 	select PCI_GT64XXX_PCI0
 	select MIPS_MSC
 	select SWAP_IO_SPACE
@@ -816,6 +822,8 @@ source "arch/mips/netlogic/Kconfig"
 
 endmenu
 
+source "drivers/brcmstb/Kconfig"
+
 config RWSEM_GENERIC_SPINLOCK
 	bool
 	default y
@@ -1113,10 +1121,10 @@ config MIPS_L1_CACHE_SHIFT_7
 
 config MIPS_L1_CACHE_SHIFT
 	int
-	default "4" if MIPS_L1_CACHE_SHIFT_4
-	default "5" if MIPS_L1_CACHE_SHIFT_5
-	default "6" if MIPS_L1_CACHE_SHIFT_6
 	default "7" if MIPS_L1_CACHE_SHIFT_7
+	default "6" if MIPS_L1_CACHE_SHIFT_6
+	default "5" if MIPS_L1_CACHE_SHIFT_5
+	default "4" if MIPS_L1_CACHE_SHIFT_4
 	default "5"
 
 config HAVE_STD_PC_SERIAL_PORT
@@ -1514,12 +1522,14 @@ config CPU_BMIPS4350
 
 config CPU_BMIPS4380
 	bool
+	select MIPS_L1_CACHE_SHIFT_6
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
 
 config CPU_BMIPS5000
 	bool
 	select MIPS_CPU_SCACHE
+	select MIPS_L1_CACHE_SHIFT_7
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
 
@@ -1820,7 +1830,6 @@ config IP22_CPU_SCACHE
 config MIPS_CPU_SCACHE
 	bool
 	select BOARD_SCACHE
-	select MIPS_L1_CACHE_SHIFT_6
 
 config R5000_CPU_SCACHE
 	bool
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index b147e7038ff0..6046ca5692e7 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -64,6 +64,14 @@ config CMDLINE
 	  For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
 	  options.
 
+config CMDLINE_EXTEND
+	bool "Extend bootloader kernel arguments"
+	default y
+	depends on CMDLINE_BOOL
+	help
+	  The command-line arguments provided by the boot loader will be
+	  appended to the default kernel command string.
+
 config CMDLINE_OVERRIDE
 	bool "Built-in command line overrides firmware arguments"
 	default n
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9b8556de9993..20f63791546f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls
 
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
+
 cflags-y += -ffreestanding
 
 #
diff --git a/arch/mips/brcmstb/Makefile b/arch/mips/brcmstb/Makefile
new file mode 100644
index 000000000000..de7fb2beead5
--- /dev/null
+++ b/arch/mips/brcmstb/Makefile
@@ -0,0 +1 @@
+obj-y			+= prom.o bmips.o memory.o irq.o time.o standby.o s3_standby.o
diff --git a/arch/mips/brcmstb/Platform b/arch/mips/brcmstb/Platform
new file mode 100644
index 000000000000..effa0efbd791
--- /dev/null
+++ b/arch/mips/brcmstb/Platform
@@ -0,0 +1,8 @@
+#
+# Broadcom set-top platforms
+#
+platform-$(CONFIG_BRCMSTB)	+= brcmstb/
+cflags-$(CONFIG_BRCMSTB)	+= -I$(srctree)/arch/mips/include/asm/mach-brcmstb
+load-$(CONFIG_BRCMSTB)		+= 0xffffffff80010000
+
+cflags-$(CONFIG_NO_INLINE)	+= -fno-inline
diff --git a/arch/mips/brcmstb/bmips.c b/arch/mips/brcmstb/bmips.c
new file mode 100644
index 000000000000..6a7826354bb4
--- /dev/null
+++ b/arch/mips/brcmstb/bmips.c
@@ -0,0 +1,595 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/compiler.h>
+
+#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
+#include <asm/barrier.h>
+#include <asm/cacheflush.h>
+#include <asm/r4kcache.h>
+#include <asm/asm-offsets.h>
+#include <asm/inst.h>
+#include <asm/fpu.h>
+#include <asm/hazards.h>
+#include <asm/cpu-features.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/***********************************************************************
+ * MIPS features, caches, and bus interface
+ ***********************************************************************/
+
+void brcmstb_cpu_setup(void)
+{
+#if   defined(CONFIG_CPU_BMIPS3300)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* Set BIU to async mode */
+	set_c0_brcm_bus_pll(BIT(22));
+	__sync();
+
+#ifdef BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT
+	/* Enable write gathering */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT, 0x264);
+
+	/* Enable split mode */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_MISB_SPLIT_MODE, 0x1);
+	__sync();
+#endif
+
+	/* put the BIU back in sync mode */
+	clear_c0_brcm_bus_pll(BIT(22));
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_reset(BIT(16));
+
+	/* Flush and enable RAC */
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0x100);
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0xf);
+	DEV_WR_RB(cbr + BMIPS_RAC_ADDRESS_RANGE, 0x0fff0000);
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* CRBMIPS438X-164: CBG workaround */
+	switch (read_c0_prid()) {
+	case 0x2a040:
+	case 0x2a042:
+	case 0x2a044:
+	case 0x2a060:
+		DEV_UNSET(cbr + BMIPS_L2_CONFIG, 0x07000000);
+	}
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_config_0(BIT(21));
+
+	/* XI/ROTR enable */
+	if (cpu_has_rixi) {
+		set_c0_brcm_config_0(BIT(23));
+		set_c0_brcm_cmt_ctrl(BIT(15));
+	}
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+	/* enable RDHWR, BRDHWR */
+	set_c0_brcm_config(BIT(17) | BIT(21));
+
+	/* Disable JTB */
+	__asm__ __volatile__(
+	"	.set	noreorder\n"
+	"	li	$8, 0x5a455048\n"
+	"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
+	"	.word	0x4008b008\n"	/* mfc0	t0, $22, 8 */
+	"	li	$9, 0x00008000\n"
+	"	or	$8, $8, $9\n"
+	"	.word	0x4088b008\n"	/* mtc0	t0, $22, 8 */
+	"	sync\n"
+	"	li	$8, 0x0\n"
+	"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
+	"	.set	reorder\n"
+	: : : "$8", "$9");
+
+	if (cpu_has_rixi) {
+		/* XI enable */
+		set_c0_brcm_config(BIT(27));
+
+		/* enable MIPS32R2 ROR instruction for XI TLB handlers */
+		__asm__ __volatile__(
+		"	li	$8, 0x5a455048\n"
+		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */
+		"	nop; nop; nop\n"
+		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */
+		"	lui	$9, 0x0100\n"
+		"	or	$8, $9\n"
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7344) || \
+	defined(CONFIG_BCM7346)
+		/* SWLINUX-2712: disable "pref 30" on buggy CPUs */
+		"	lui	$9, 0x0800\n"
+		"	or	$8, $9\n"
+#endif
+		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */
+		: : : "$8", "$9");
+	}
+
+#endif
+}
+
+/***********************************************************************
+ * Simulate privileged instructions (RDHWR, MFC0) and unaligned accesses
+ ***********************************************************************/
+
+#define OPCODE 0xfc000000
+#define BASE   0x03e00000
+#define RT     0x001f0000
+#define OFFSET 0x0000ffff
+#define LL     0xc0000000
+#define SC     0xe0000000
+#define SPEC0  0x00000000
+#define SPEC3  0x7c000000
+#define RD     0x0000f800
+#define FUNC   0x0000003f
+#define SYNC   0x0000000f
+#define RDHWR  0x0000003b
+
+#define BRDHWR 0xec000000
+#define OP_MFC0 0x40000000
+
+int brcm_simulate_opcode(struct pt_regs *regs, int rd, int rt)
+{
+	struct thread_info *ti = task_thread_info(current);
+	int opcode = rd << 11 | rt << 16;
+
+	/* PR34054: use alternate RDHWR instruction encoding */
+	if (((opcode & OPCODE) == BRDHWR && (opcode & FUNC) == RDHWR)
+	    || ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR)) {
+
+		if (rd == 29) {
+			regs->regs[rt] = ti->tp_value;
+			atomic_inc(&brcm_rdhwr_count);
+			return 0;
+		}
+	}
+
+	/* emulate MFC0 $15 for optimized memcpy() CPU detection */
+	if ((opcode & OPCODE) == OP_MFC0 &&
+	    (opcode & OFFSET) == (15 << 11)) {
+		regs->regs[rt] = read_c0_prid();
+		return 0;
+	}
+
+	return -1;	/* unhandled */
+}
+
+int brcm_unaligned_fp(void __user *addr, union mips_instruction *insn,
+	struct pt_regs *regs)
+{
+	unsigned int op = insn->i_format.opcode;
+	unsigned int rt = insn->i_format.rt;
+	unsigned int res;
+	int wordlen = 8;
+
+	/* on r4k, only the even slots ($f0, $f2, ...) are used */
+	u8 *fprptr = (u8 *)current + THREAD_FPR0 + (rt >> 1) *
+		(THREAD_FPR2 - THREAD_FPR0);
+
+	if (op == lwc1_op || op == swc1_op) {
+		wordlen = 4;
+#ifdef __LITTLE_ENDIAN
+		/* LE: LSW ($f0) precedes MSW ($f1) */
+		fprptr += (rt & 1) ? 4 : 0;
+#else
+		/* BE: MSW ($f1) precedes LSW ($f0) */
+		fprptr += (rt & 1) ? 0 : 4;
+#endif
+	}
+
+	preempt_disable();
+	if (is_fpu_owner())
+		save_fp(current);
+	else
+		own_fpu(1);
+
+	if (op == lwc1_op || op == ldc1_op) {
+		if (!access_ok(VERIFY_READ, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR load: copy from user struct to kernel saved
+		 * register struct, then restore all FPRs
+		 */
+		__asm__ __volatile__ (
+		"1:	lb	%0, 0(%3)\n"
+		"	sb	%0, 0(%2)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 1b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+
+		restore_fp(current);
+	} else {
+		if (!access_ok(VERIFY_WRITE, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR store: copy from kernel saved register struct
+		 * to user struct
+		 */
+		__asm__ __volatile__ (
+		"2:	lb	%0, 0(%2)\n"
+		"1:	sb	%0, 0(%3)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 2b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+	}
+	preempt_enable();
+
+	atomic_inc(&brcm_unaligned_fp_count);
+	return 0;
+
+sigbus:
+	preempt_enable();
+	return -EINVAL;
+
+fault:
+	preempt_enable();
+	return -EFAULT;
+}
+
+/***********************************************************************
+ * CPU divisor / PLL manipulation
+ ***********************************************************************/
+/*
+ * 0: CP0 COUNT/COMPARE frequency depends on divisor
+ * 1: CP0 COUNT/COMPARE frequency does not depend on divisor
+ */
+static int fixed_counter_freq;
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7344B0) || \
+	defined(CONFIG_BCM7346B0)
+/* SWLINUX-2063: MIPS cannot enter divide-by-N mode */
+#define	BROKEN_MIPS_DIVIDER
+#endif
+
+/* MIPS active standby on 7550 */
+#define CPU_PLL_MODE1		216000
+
+/*
+ * current ADJUSTED base frequency (reflects the current PLL settings)
+ * brcm_cpu_khz (in time.c) always has the ORIGINAL clock frequency and
+ *   is never changed after bootup
+ */
+unsigned long brcm_adj_cpu_khz;
+
+/* multiplier used in brcm_fixup_ticks to scale the # of ticks
+ * 0               - no fixup needed
+ * any other value - factor * 2^16 */
+static unsigned long fixup_ticks_ratio;
+
+/* current CPU divisor, as set by the user */
+static __maybe_unused int cpu_div = 1;
+
+/*
+ * MIPS clockevent code always assumes the original boot-time CP0 clock rate.
+ * This function scales the number of ticks according to the current HW
+ * settings.
+ */
+unsigned long brcm_fixup_ticks(unsigned long delta)
+{
+	unsigned long long tmp = delta;
+
+	if (unlikely(!brcm_adj_cpu_khz))
+		brcm_adj_cpu_khz = brcm_cpu_khz;
+
+	if (likely(!fixup_ticks_ratio))
+		return delta;
+
+	tmp *= fixup_ticks_ratio;
+	tmp >>= 16;
+
+	return (unsigned long)tmp;
+}
+
+static unsigned int orig_udelay_val[NR_CPUS];
+
+struct spd_change {
+	int			old_div;
+	int			new_div;
+	int			old_base;
+	int			new_base;
+};
+
+void brcm_set_cpu_speed(void *arg)
+{
+	struct spd_change *c = arg;
+	uint32_t new_div = (uint32_t)c->new_div;
+	unsigned long __maybe_unused count, compare, delta;
+	signed long sdelta;
+	int cpu = smp_processor_id();
+	uint32_t __maybe_unused tmp0, tmp1, tmp2, tmp3;
+
+	/* scale udelay_val */
+	if (!orig_udelay_val[cpu])
+		orig_udelay_val[cpu] = current_cpu_data.udelay_val;
+
+	if (c->new_base == brcm_cpu_khz)
+		current_cpu_data.udelay_val = orig_udelay_val[cpu] / new_div;
+	else
+		current_cpu_data.udelay_val =
+			(unsigned long long)orig_udelay_val[cpu] *
+			c->new_base / (new_div * c->old_base);
+
+	/* scale any pending timer events */
+	compare = read_c0_compare();
+	count = read_c0_count();
+
+	sdelta = (long)compare - (long)count;
+	if (sdelta > 0) {
+		if (!fixed_counter_freq)
+			delta = ((unsigned long long)sdelta *
+				c->old_div * c->new_base) /
+				(new_div * c->old_base);
+		else
+			delta = ((unsigned long long)sdelta *
+				c->new_base) / c->old_base;
+	write_c0_compare(read_c0_count() + delta);
+	}
+
+	if (cpu != 0)
+		return;
+
+#if defined(CONFIG_BRCM_CPU_PLL)
+	brcm_adj_cpu_khz = c->new_base;
+#if defined(CONFIG_BCM7550)
+	if (brcm_adj_cpu_khz == CPU_PLL_MODE1) {
+		/* 216Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300618);
+	} else {
+		/* 324Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300418);
+	}
+	BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_UPDATE, 1);
+#else
+#error CPU PLL adjustment not supported on this chip
+#endif
+#endif
+
+	if ((brcm_adj_cpu_khz == brcm_cpu_khz) &&
+	    (fixed_counter_freq || new_div == 1)) {
+		fixup_ticks_ratio = 0;
+	} else {
+		fixup_ticks_ratio =
+			((unsigned long long)brcm_adj_cpu_khz << 16) /
+			 (unsigned long long)brcm_cpu_khz;
+		if (!fixed_counter_freq)
+			fixup_ticks_ratio /= new_div;
+	}
+
+	printk(KERN_DEBUG "ratio=%lu adj=%lu freq=%lu new_div=%d\n",
+	       fixup_ticks_ratio, brcm_adj_cpu_khz, brcm_cpu_khz, new_div);
+	new_div = ffs(new_div) - 1;
+
+	/* see BMIPS datasheet, CP0 register $22 */
+
+#if defined(CONFIG_CPU_BMIPS3300)
+	change_c0_brcm_bus_pll(0x07 << 22, (new_div << 23) | (0 << 22));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	change_c0_brcm_mode(0x0f << 4, (1 << 7) | (new_div << 4));
+#elif defined(CONFIG_CPU_BMIPS4380)
+	__asm__ __volatile__(
+	"	.set	push\n"
+	"	.set	noreorder\n"
+	"	.set	nomacro\n"
+	"	.set	mips32\n"
+	/* get kseg1 address for CBA into %3 */
+	"	mfc0	%3, $22, 6\n"
+	"	li	%2, 0xfffc0000\n"
+	"	and	%3, %2\n"
+	"	li	%2, 0xa0000000\n"
+	"	add	%3, %2\n"
+	/* %1 = async bit, %2 = mask out everything but 30:28 */
+	"	lui	%1, 0x1000\n"
+	"	lui	%2, 0x8fff\n"
+	"	beqz	%0, 1f\n"
+	"	ori	%2, 0xffff\n"
+	/* handle SYNC to ASYNC */
+	"	sync\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"	sll	%0, 29\n"
+	"	or	%4, %0\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	b	2f\n"
+	"	nop\n"
+	/* handle ASYNC to SYNC */
+	"1:\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	sync\n"
+	"	and	%4, %2\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"2:\n"
+	"	.set	pop\n"
+	: "+r" (new_div),
+	  "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3));
+#endif
+}
+
+#ifdef CONFIG_BRCM_CPU_DIV
+
+ssize_t brcm_pm_show_cpu_div(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_div);
+}
+
+ssize_t brcm_pm_store_cpu_div(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (val != 1 && val != 2 && val != 4 && val != 8
+#if defined(CONFIG_CPU_BMIPS5000)
+		&& val != 16
+#endif
+			)
+		return -EINVAL;
+
+#if defined(BROKEN_MIPS_DIVIDER)
+	return val == 1 ? count : -EINVAL;
+#endif
+
+	chg.old_div = cpu_div;
+	chg.new_div = val;
+	chg.old_base = brcm_adj_cpu_khz;
+	chg.new_base = brcm_adj_cpu_khz;
+
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+	cpu_div = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_DIV */
+
+#ifdef CONFIG_BRCM_CPU_PLL
+
+static int cpu_pll_mode;
+
+ssize_t brcm_pm_show_cpu_pll(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_pll_mode);
+}
+
+ssize_t brcm_pm_store_cpu_pll(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (cpu_pll_mode == val)
+		return count;
+
+	switch (val) {
+	case 0:
+		chg.new_base = brcm_cpu_khz;
+		break;
+	case 1:
+		chg.new_base = CPU_PLL_MODE1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	chg.old_div = cpu_div;
+	chg.new_div = cpu_div;
+	chg.old_base = brcm_adj_cpu_khz;
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+
+	cpu_pll_mode = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_PLL */
+
+static int bmips_check_caps(void)
+{
+	unsigned long __maybe_unused config;
+#ifdef CONFIG_CPU_BMIPS5000
+	fixed_counter_freq = 1;
+#elif defined(CONFIG_CPU_BMIPS4380)
+	config = read_c0_brcm_config();
+	fixed_counter_freq = !!(config & 0x40);
+#else
+	fixed_counter_freq = 0;
+#endif
+	printk(KERN_INFO "PM: CP0 COUNT/COMPARE frequency %s on divisor\n",
+	       fixed_counter_freq ? "does not depend" : "depends");
+	return 0;
+}
+late_initcall(bmips_check_caps);
diff --git a/arch/mips/brcmstb/irq.c b/arch/mips/brcmstb/irq.c
new file mode 100644
index 000000000000..23b6adf8c847
--- /dev/null
+++ b/arch/mips/brcmstb/irq.c
@@ -0,0 +1,465 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/cpumask.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/version.h>
+
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/irq_cpu.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#ifdef CONFIG_SMP
+static int next_cpu[NR_IRQS + 1] = { [0 ... NR_IRQS] = 0 };
+#define NEXT_CPU(irq) next_cpu[irq]
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE BCHP_HIF_CPU_TP1_INTR1_REG_START
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	if (cpu_online(1)) \
+		L1_WR_##word(TP1_BASE, reg, val); \
+	} while (0)
+
+#else
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE TP0_BASE
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	} while (0)
+
+#define NEXT_CPU(irq) 0
+#endif
+
+#define L1_REG(base, off) ((base) + (off) - BCHP_HIF_CPU_INTR1_REG_START)
+
+#define L1_RD_W0(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg))
+#define L1_RD_W1(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg))
+
+#define L1_WR_W0(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg), val)
+#define L1_WR_W1(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg), val)
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W2_STATUS)
+
+#define L1_RD_W2(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg))
+#define L1_WR_W2(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg), val)
+
+#else
+/* nop on chips with only 64 L1 interrupts */
+#define L1_RD_W2(base, reg)	0
+#define L1_WR_W2(base, reg, val) do { } while (0)
+#endif
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W3_STATUS)
+
+#define L1_RD_W3(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg))
+#define L1_WR_W3(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg), val)
+
+#else
+/* nop on chips with only 96 L1 interrupts */
+#define L1_RD_W3(base, reg)	0
+#define L1_WR_W3(base, reg, val) do { } while (0)
+#endif
+
+/*
+ * For interrupt map, see include/asm-mips/brcmstb/<plat>/bcmintrnum.h
+ */
+
+/***********************************************************************
+ * INTC (aka L1 interrupt) functions
+ ***********************************************************************/
+
+static void brcm_intc_enable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long base = NEXT_CPU(irq) ? TP1_BASE : TP0_BASE;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_W0(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_W1(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_W2(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_W3(base, MASK_CLEAR, (1UL << shift));
+	} else
+		BUG();
+}
+
+static void brcm_intc_disable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_ALL(W0, MASK_SET, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_ALL(W1, MASK_SET, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_ALL(W2, MASK_SET, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_ALL(W3, MASK_SET, (1UL << shift));
+	} else
+		BUG();
+}
+
+#ifdef CONFIG_SMP
+static int brcm_intc_set_affinity(struct irq_data *d,
+	const struct cpumask *dest, bool force)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W0(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W0(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 32 && irq <= 64) {
+		shift = irq - 32 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W1(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W1(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 64 && irq <= 96) {
+		shift = irq - 64 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W2(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W2(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 96 && irq <= 128) {
+		shift = irq - 96 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpu_isset(0, *dest)) {
+			L1_WR_W3(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W3(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	}
+	local_irq_restore(flags);
+	return 0;
+}
+
+static void brcm_intc_cpu_offline(struct irq_data *data)
+{
+	int cpu = smp_processor_id();
+	cpumask_t new_affinity;
+
+	/* This CPU was not present on the affinity mask, don't care */
+	if (!cpumask_test_cpu(cpu, data->affinity))
+		return;
+
+	if (cpumask_weight(data->affinity) > 1) {
+		/* Multiple CPU affinity, remove this CPU from
+		 * the affinity set
+		 */
+		cpumask_copy(&new_affinity, data->affinity);
+		cpumask_clear_cpu(cpu, &new_affinity);
+	} else {
+		/* Put on the lowest numbered online CPU */
+		cpumask_clear(&new_affinity);
+		cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+	}
+	irq_set_affinity_locked(data, &new_affinity, false);
+
+}
+#endif /* CONFIG_SMP */
+
+/*
+ * THT: These INTC disable the interrupt before calling the IRQ handle_irq
+ */
+static struct irq_chip brcm_intc_type = {
+	.name			= "BRCM L1",
+	.irq_ack		= brcm_intc_disable,
+	.irq_mask		= brcm_intc_disable,
+	.irq_mask_ack		= brcm_intc_disable,
+	.irq_unmask		= brcm_intc_enable,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= brcm_intc_set_affinity,
+	.irq_cpu_offline	= brcm_intc_cpu_offline,
+#endif /* CONFIG_SMP */
+	NULL
+};
+
+/*
+ * Move the interrupt to the other TP, to balance load (if affinity permits)
+ */
+static void flip_tp(int irq)
+{
+#ifdef CONFIG_SMP
+	int tp = smp_processor_id();
+	unsigned long local_lev1, remote_lev1;
+	unsigned long mask = 1 << ((irq - 1) & 0x1f);
+
+	if (tp == 0) {
+		local_lev1 = TP0_BASE;
+		remote_lev1 = TP1_BASE;
+	} else {
+		local_lev1 = TP1_BASE;
+		remote_lev1 = TP0_BASE;
+	}
+
+	if (cpumask_test_cpu(tp ^ 1, irq_desc[irq].irq_data.affinity)) {
+		next_cpu[irq] = tp ^ 1;
+		if (irq > 0 && irq <= 32) {
+			L1_WR_W0(local_lev1, MASK_SET, mask);
+			L1_WR_W0(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 32 && irq <= 64) {
+			L1_WR_W1(local_lev1, MASK_SET, mask);
+			L1_WR_W1(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 64 && irq <= 96) {
+			L1_WR_W2(local_lev1, MASK_SET, mask);
+			L1_WR_W2(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 96 && irq <= 128) {
+			L1_WR_W3(local_lev1, MASK_SET, mask);
+			L1_WR_W3(remote_lev1, MASK_CLEAR, mask);
+		}
+	}
+#endif /* CONFIG_SMP */
+}
+
+static void brcm_intc_dispatch(struct pt_regs *regs, unsigned long base)
+{
+	u32 pend, shift;
+
+	pend = L1_RD_W0(base, STATUS) & ~L1_RD_W0(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = L1_RD_W1(base, STATUS) & ~L1_RD_W1(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 32;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W2(base, STATUS) & ~L1_RD_W2(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 64;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W3(base, STATUS) & ~L1_RD_W3(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 96;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+}
+
+/* IRQ2 = L1 interrupt for TP0 */
+static void brcm_mips_int2_dispatch(struct pt_regs *regs)
+{
+	clear_c0_status(STATUSF_IP2);
+	brcm_intc_dispatch(regs, TP0_BASE);
+	set_c0_status(STATUSF_IP2);
+}
+
+#ifdef CONFIG_SMP
+/* IRQ3 = L1 interrupt for TP1 */
+static void brcm_mips_int3_dispatch(struct pt_regs *regs)
+{
+	clear_c0_status(STATUSF_IP3);
+	brcm_intc_dispatch(regs, TP1_BASE);
+	set_c0_status(STATUSF_IP3);
+}
+#endif
+
+/***********************************************************************
+ * IRQ setup / dispatch
+ ***********************************************************************/
+
+void __init arch_init_irq(void)
+{
+	int irq;
+
+	mips_cpu_irq_init();
+
+	L1_WR_ALL(W0, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W1, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W2, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W3, MASK_SET, 0xffffffff);
+
+	clear_c0_status(ST0_IE | ST0_IM);
+
+	/* Set up all L1 IRQs */
+	for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+		irq_set_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#else
+		set_irq_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#endif
+
+#if defined(CONFIG_SMP)
+	/* default affinity: 1 (TP0 only) */
+	cpumask_clear(irq_default_affinity);
+	cpumask_set_cpu(0, irq_default_affinity);
+#endif
+
+	/* enable IRQ2 (this runs on TP0).  IRQ3 enabled during TP1 boot. */
+	set_c0_status(STATUSF_IP2);
+
+	/* enable non-shared UART interrupts in the L2 */
+
+#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
+	/* 3548 style - separate register */
+	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
+	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
+#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
+	/* 7405 style - shared with L2 */
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+#endif
+		);
+#endif
+
+#if defined(BCHP_HIF_INTR2_CPU_MASK_SET)
+	/* mask and clear all HIF L2 interrupts */
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff);
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff);
+#endif
+}
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+	unsigned int pend = ((read_c0_cause() & read_c0_status()) >> 8) & 0xff;
+	unsigned int shift;
+
+	while ((shift = ffs(pend)) != 0) {
+		shift--;
+		pend ^= 1 << shift;
+		if (shift == 2)
+			brcm_mips_int2_dispatch(regs);
+#ifdef CONFIG_SMP
+		else if (unlikely(shift == 3))
+			brcm_mips_int3_dispatch(regs);
+#endif
+		else
+			do_IRQ(MIPS_CPU_IRQ_BASE + shift);
+	}
+}
+
+/***********************************************************************
+ * Power management
+ ***********************************************************************/
+
+static unsigned long brcm_irq_state[NR_IRQS / 32];
+
+void brcm_irq_standby_enter(int wake_irq)
+{
+	/* save the current state, then mask everything */
+	brcm_irq_state[0] = L1_RD_W0(TP0_BASE, MASK_STATUS);
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[1] = L1_RD_W1(TP0_BASE, MASK_STATUS);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[2] = L1_RD_W2(TP0_BASE, MASK_STATUS);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[3] = L1_RD_W3(TP0_BASE, MASK_STATUS);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+
+	/* unmask the wakeup IRQ */
+	if (wake_irq > 0 && wake_irq <= 32)
+		L1_WR_W0(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 1));
+	else if (wake_irq > 32 && wake_irq <= 64)
+		L1_WR_W1(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 33));
+	else if (wake_irq > 64 && wake_irq <= 96)
+		L1_WR_W2(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 65));
+	else if (wake_irq > 96 && wake_irq <= 128)
+		L1_WR_W3(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 97));
+}
+
+void brcm_irq_standby_exit(void)
+{
+	/* restore the saved L1 state */
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W0(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[0]);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W1(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[1]);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W2(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[2]);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W3(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[3]);
+}
diff --git a/arch/mips/brcmstb/memory.c b/arch/mips/brcmstb/memory.c
new file mode 100644
index 000000000000..aaa07487e386
--- /dev/null
+++ b/arch/mips/brcmstb/memory.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (C) 2000-2004 Russell King
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+#include <linux/compiler.h>
+#include <linux/atomic.h>
+#include <linux/printk.h>
+#include <linux/module.h>
+
+#include <asm/page.h>
+#include <asm/pgtable-32.h>
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+#include <asm/tlbflush.h>
+#include <asm/r4kcache.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <spaces.h>
+
+/*
+ * Override default behavior to allow cached access to all valid DRAM ranges
+ */
+int __uncached_access(struct file *file, unsigned long addr)
+{
+	if (file->f_flags & O_SYNC)
+		return 1;
+	if (addr >= BCHP_PHYSICAL_OFFSET && addr < UPPERMEM_START)
+		return 1;
+	if (addr >= PCIE_MEM_START)
+		return 1;
+	return 0;
+}
+
+/***********************************************************************
+ * Wired TLB mappings for upper memory support
+ ***********************************************************************/
+
+#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+
+/* (PFN << 6) | GLOBAL | VALID | DIRTY | cacheability */
+#define ENTRYLO_CACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x03 << 3))
+#define ENTRYLO_UNCACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x02 << 3))
+
+/* GLOBAL | !VALID */
+#define ENTRYLO_INVALID()	(0x01)
+
+struct tlb_entry {
+	unsigned long entrylo0;
+	unsigned long entrylo1;
+	unsigned long entryhi;
+	unsigned long pagemask;
+};
+
+static struct tlb_entry __maybe_unused uppermem_mappings[] = {
+{
+#if defined(CONFIG_BRCM_UPPER_768MB)
+	.entrylo0		= ENTRYLO_CACHED(TLB_UPPERMEM_PA),
+	.entrylo1		= ENTRYLO_INVALID(),
+	.entryhi		= TLB_UPPERMEM_VA,
+	.pagemask		= PM_256M,
+#endif
+},
+};
+
+static inline void __cpuinit brcm_write_tlb_entry(int idx,
+	unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi,
+	unsigned long pagemask)
+{
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	write_c0_entryhi(entryhi);
+	write_c0_pagemask(pagemask);
+	write_c0_index(idx);
+	mtc0_tlbw_hazard();
+	tlb_write_indexed();
+	tlbw_use_hazard();
+}
+
+/*
+ * This function is used instead of add_wired_entry(), because it does not
+ * have any external dependencies and is not marked __init
+ */
+static inline void __cpuinit brcm_add_wired_entry(unsigned long entrylo0,
+	unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask)
+{
+	int i = read_c0_wired();
+	write_c0_wired(i + 1);
+	brcm_write_tlb_entry(i, entrylo0, entrylo1, entryhi, pagemask);
+}
+
+extern void tlb_init(void);
+extern void build_tlb_refill_handler(void);
+
+void __cpuinit brcm_tlb_init(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	if (smp_processor_id() == 0) {
+		int i;
+		struct tlb_entry *e = uppermem_mappings;
+
+		tlb_init();
+		for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++, e++)
+			brcm_add_wired_entry(e->entrylo0, e->entrylo1,
+				e->entryhi, e->pagemask);
+		write_c0_pagemask(PM_DEFAULT_MASK);
+	} else {
+		/* bypass tlb_init() / probe_tlb() for secondary CPU */
+		cpu_data[smp_processor_id()].tlbsize = cpu_data[0].tlbsize;
+		build_tlb_refill_handler();
+	}
+#else
+	tlb_init();
+#endif
+}
+
+/*
+ * Initialize upper memory TLB entries
+ *
+ * On TP1 this must happen before we set up $sp/$gp .  It is always
+ * possible for stacks, task_structs, thread_info's, and other
+ * important structures to be allocated out of upper memory so
+ * this happens early on.
+ */
+asmlinkage void plat_wired_tlb_setup(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	int i, tlbsz;
+
+	/* Flush TLB.  local_flush_tlb_all() is not available yet. */
+	write_c0_entrylo0(0);
+	write_c0_entrylo1(0);
+	write_c0_pagemask(PM_DEFAULT_MASK);
+	write_c0_wired(0);
+
+	tlbsz = (read_c0_config1() >> 25) & 0x3f;
+	for (i = 0; i <= tlbsz; i++) {
+		write_c0_entryhi(UNIQUE_ENTRYHI(i));
+		write_c0_index(i);
+		mtc0_tlbw_hazard();
+		tlb_write_indexed();
+		tlbw_use_hazard();
+	}
+
+	write_c0_wired(0);
+	mtc0_tlbw_hazard();
+
+	for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++) {
+		struct tlb_entry *e = &uppermem_mappings[i];
+		brcm_add_wired_entry(e->entrylo0, e->entrylo1, e->entryhi,
+			e->pagemask);
+	}
+
+	write_c0_pagemask(PM_DEFAULT_MASK);
+#endif
+}
+
+#ifdef CONFIG_BRCM_UPPER_768MB
+
+/***********************************************************************
+ * Special allocator for coherent (uncached) memory
+ * (Required for >256MB upper memory)
+ ***********************************************************************/
+
+#define CONSISTENT_DMA_SIZE	(CONSISTENT_END - CONSISTENT_BASE)
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES	(CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
+/*
+ * These are the page tables (4MB each) covering uncached, DMA consistent
+ * allocations
+ */
+static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+static DEFINE_SPINLOCK(consistent_lock);
+
+struct arm_vm_region {
+	struct list_head	vm_list;
+	unsigned long		vm_start;
+	unsigned long		vm_end;
+	void			*vm_cac_va;
+	int			vm_active;
+};
+
+static struct arm_vm_region consistent_head = {
+	.vm_list	= LIST_HEAD_INIT(consistent_head.vm_list),
+	.vm_start	= CONSISTENT_BASE,
+	.vm_end		= CONSISTENT_END,
+};
+
+static struct arm_vm_region *
+arm_vm_region_alloc(struct arm_vm_region *head, size_t size, gfp_t gfp)
+{
+	unsigned long addr = head->vm_start, end = head->vm_end - size;
+	unsigned long flags;
+	struct arm_vm_region *c, *new;
+
+	new = kmalloc(sizeof(struct arm_vm_region), gfp);
+	if (!new)
+		goto out;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if ((addr + size) < addr)
+			goto nospc;
+		if ((addr + size) <= c->vm_start)
+			goto found;
+		addr = c->vm_end;
+		if (addr > end)
+			goto nospc;
+	}
+
+found:
+	/*
+	 * Insert this entry _before_ the one we found.
+	 */
+	list_add_tail(&new->vm_list, &c->vm_list);
+	new->vm_start = addr;
+	new->vm_end = addr + size;
+	new->vm_active = 1;
+
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	return new;
+
+nospc:
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	kfree(new);
+out:
+	return NULL;
+}
+
+static struct arm_vm_region *arm_vm_region_find(struct arm_vm_region *head,
+	unsigned long addr)
+{
+	struct arm_vm_region *c;
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if (c->vm_active && c->vm_start == addr)
+			goto out;
+	}
+	c = NULL;
+out:
+	return c;
+}
+
+static int __init consistent_init(void)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+	int ret = 0, i = 0;
+	u32 base = CONSISTENT_BASE;
+
+	do {
+		pgd = pgd_offset(&init_mm, base);
+		pud = pud_alloc(&init_mm, pgd, base);
+		if (!pud) {
+			pr_err("%s: no pud tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+		pmd = pmd_alloc(&init_mm, pud, base);
+		if (!pmd) {
+			pr_err("%s: no pmd tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		pte = pte_alloc_kernel(pmd, base);
+		if (!pte) {
+			pr_err("%s: no pte tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		consistent_pte[i++] = pte;
+		base += (1 << PGDIR_SHIFT);
+	} while (base < CONSISTENT_END);
+
+	return ret;
+}
+
+core_initcall(consistent_init);
+
+int brcm_map_coherent(dma_addr_t dma_handle, void *cac_va, size_t size,
+	void **uncac_va, gfp_t gfp)
+{
+	struct arm_vm_region *c;
+	struct page *page;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	c = arm_vm_region_alloc(&consistent_head, size, gfp);
+	if (!c)
+		return -EINVAL;
+
+	c->vm_cac_va = cac_va;
+
+	page = virt_to_page(cac_va);
+	idx = CONSISTENT_PTE_INDEX(c->vm_start);
+	off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("map addr %08lx idx %x off %x pte %p\n",
+		c->vm_start, idx, off, pte);
+
+	do {
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			BUG_ON(idx >= NUM_CONSISTENT_PTES - 1);
+			pte = consistent_pte[++idx];
+		}
+
+		BUG_ON(!pte_none(*pte));
+		set_pte(pte, mk_pte(page, PAGE_KERNEL_UNCACHED));
+		page++;
+		pte++;
+		off++;
+	} while (size -= PAGE_SIZE);
+
+	*uncac_va = (void *)c->vm_start;
+	return 0;
+}
+
+void *brcm_unmap_coherent(void *vaddr)
+{
+	struct arm_vm_region *c;
+	unsigned long flags, addr;
+	void *ret = NULL;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	c = arm_vm_region_find(&consistent_head, (unsigned long)vaddr);
+	if (!c) {
+		spin_unlock_irqrestore(&consistent_lock, flags);
+		pr_err("%s: invalid VA %p\n", __func__, vaddr);
+		return NULL;
+	}
+	c->vm_active = 0;
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	ret = c->vm_cac_va;
+	addr = c->vm_start;
+
+	idx = CONSISTENT_PTE_INDEX(addr);
+	off = CONSISTENT_OFFSET(addr) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("unmap addr %08lx idx %x off %x pte %p\n",
+		addr, idx, off, pte);
+
+	do {
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			BUG_ON(idx >= NUM_CONSISTENT_PTES - 1);
+			pte = consistent_pte[++idx];
+		}
+
+		pte_clear(&init_mm, addr, pte);
+		pte++;
+		off++;
+		addr += PAGE_SIZE;
+	} while (addr < c->vm_end);
+	flush_tlb_kernel_range(c->vm_start, c->vm_end);
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	list_del(&c->vm_list);
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	kfree(c);
+
+	return ret;
+}
+
+#endif /* CONFIG_BRCM_UPPER_768MB */
+
+void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+	unsigned long flags)
+{
+	/* sanity check */
+	if ((offset + size - 1) < offset ||
+	    !size ||
+	    offset > max(KSEG0_SIZE, KSEG1_SIZE))
+		return NULL;
+
+	/* !XKS01, XKS01: uncached access to EBI/registers @ PA 1000_0000 */
+	if (offset >= 0x10000000 &&
+	    (offset + size) <= 0x20000000 &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* !XKS01, XKS01: easy cached access to some DRAM */
+	if ((offset + size) <= KSEG0_SIZE &&
+	    flags == _CACHE_CACHABLE_NONCOHERENT)
+		return (void *)(KSEG0 + offset);
+
+	/* !XKS01 only: easy uncached access to some DRAM */
+	if ((offset + size) <= KSEG1_SIZE &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* anything else gets mapped using page tables */
+	return NULL;
+}
+EXPORT_SYMBOL(plat_ioremap);
+
+int plat_iounmap(const volatile void __iomem *addr)
+{
+	phys_t va = (unsigned long)addr;
+
+	if (va >= KSEG0 && va < (KSEG0 + KSEG0_SIZE))
+		return 1;
+	if (va >= KSEG1 && va < (KSEG1 + KSEG1_SIZE))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(plat_iounmap);
+
+/***********************************************************************
+ * RAM configuration
+ ***********************************************************************/
+
+#define MAGIC0		0xdeadbeef
+#define MAGIC1		0xfeedcafe
+
+static inline unsigned int __init probe_ram_size(void)
+{
+	unsigned long addr = KSEG1, taddr;
+	uint32_t olddata;
+	unsigned long flags;
+	unsigned int i, memsize = 256;
+
+	pr_info("Probing system memory size... ");
+
+	local_irq_save(flags);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	olddata = DEV_RD(addr);
+
+	/*
+	 * Try to figure out where memory wraps around.  If it does not
+	 * wrap, assume 256MB
+	*/
+	for (i = 4; i <= 128; i <<= 1) {
+		taddr = KSEG1 + i * 1048576;
+		DEV_WR(addr, MAGIC0);
+		if (DEV_RD(taddr) == MAGIC0) {
+			DEV_WR(addr, MAGIC1);
+			if (DEV_RD(taddr) == MAGIC1) {
+				memsize = i;
+				break;
+			}
+		}
+	}
+
+	DEV_WR(addr, olddata);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	local_irq_restore(flags);
+
+	pr_cont("found %u MB\n", memsize);
+
+	return memsize;
+}
+
+void __init board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb)
+{
+#if defined(CONFIG_BRCM_OVERRIDE_RAM_SIZE)
+	*dram0_mb = CONFIG_BRCM_FORCED_DRAM0_SIZE;
+#if defined(CONFIG_BRCM_FORCED_DRAM1_SIZE)
+	*dram1_mb = CONFIG_BRCM_FORCED_DRAM1_SIZE;
+#endif
+	pr_info("Using %lu MB + %lu MB RAM (from kernel configuration)\n",
+		*dram0_mb, *dram1_mb);
+#else
+	/* DRAM0_SIZE variable from CFE */
+	if (*dram0_mb) {
+		pr_info("Using %lu MB + %lu MB RAM (from CFE)\n",
+			*dram0_mb, *dram1_mb);
+		return;
+	}
+	*dram0_mb = probe_ram_size();
+#endif
+}
+
+static void __init __brcm_wraparound_check(unsigned long start,
+	unsigned long midpoint, int memc_no)
+{
+	int found = 0, idx = read_c0_wired();
+	unsigned long *a, *b, old_a, va = FIXADDR_TOP - 0x2000;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_UNCACHED(start),
+		ENTRYLO_UNCACHED(midpoint), va, PM_4K);
+
+	a = (unsigned long *)(va);
+	b = (unsigned long *)(va + 0x1000);
+
+	old_a = *a;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	if (*a != old_a)
+		found = 1;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	/* this should always match, but check anyway */
+	if (*a != old_a)
+		found = 1;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_INVALID(), ENTRYLO_INVALID(),
+		UNIQUE_ENTRYHI(idx), PM_4K);
+
+	if (found)
+		panic("DRAM%d wraparound detected at 0x%lx\n",
+			memc_no, midpoint);
+}
+
+void __init brcm_wraparound_check(void)
+{
+	/*
+	 * Find the middle of the DRAM region, compensating for the memory
+	 * hole at the 256MB mark if necessary.  If there is no wraparound
+	 * at the middle address, everything else should be OK.
+	 */
+	if (brcm_dram0_size_mb >= 512)
+		__brcm_wraparound_check(0,
+			(brcm_dram0_size_mb << 19) + 0x10000000, 0);
+	else
+		__brcm_wraparound_check(0, brcm_dram0_size_mb << 19, 0);
+
+	if (brcm_dram1_size_mb)
+		__brcm_wraparound_check(MEMC1_START,
+			brcm_dram1_size_mb << 19, 1);
+}
diff --git a/arch/mips/brcmstb/prom.c b/arch/mips/brcmstb/prom.c
new file mode 100644
index 000000000000..06bb3a5c4bf6
--- /dev/null
+++ b/arch/mips/brcmstb/prom.c
@@ -0,0 +1,594 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/types.h>
+#include <linux/smp.h>
+#include <linux/bmoca.h>
+#include <linux/version.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/compiler.h>
+#include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/bootinfo.h>
+#include <asm/r4kcache.h>
+#include <asm/traps.h>
+#include <asm/cacheflush.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+#include <asm/smp-ops.h>
+#include <asm/reboot.h>
+#include <asm/fw/cfe/cfe_api.h>
+#include <asm/fw/cfe/cfe_error.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <spaces.h>
+
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+#include <linux/initrd.h>
+
+static inline unsigned long __init aon_read_blob_table(unsigned long idx)
+{
+	return BDEV_RD(AON_RAM_BASE + ((16 + idx) << 2));
+}
+
+static inline unsigned long __init aon_read_mac(unsigned long idx)
+{
+	return BDEV_RD(AON_RAM_BASE + ((126 + idx) << 2));
+}
+
+static void __init parse_blob_table(void)
+{
+	unsigned long len;
+	unsigned long ptr;
+	unsigned long i;
+
+	if (aon_read_blob_table(0) != 0x6c6f6f70)
+		return;
+
+	len = aon_read_blob_table(1);
+	if (len > 8) {
+		printk(KERN_ERR "%s: Invalid length (%#lx), ignoring table\n", __func__, len);
+		return;
+	}
+
+	ptr = 2;
+	for (i = 0; i < len; i++) {
+		unsigned long type = aon_read_blob_table(ptr++);
+		unsigned long addr = aon_read_blob_table(ptr++);
+		unsigned long size = aon_read_blob_table(ptr++);
+
+		if (type == 0 || type == 0xFFFFFFFF ||
+		    addr == 0 || addr == 0xFFFFFFFF ||
+		    size == 0 || size == 0xFFFFFFFF) {
+			printk(KERN_ERR "%s: Invalid entry, aborting\n", __func__);
+			break;
+		}
+
+		if (addr >= BRCM_PCI_HOLE_START)
+			addr += BRCM_PCI_HOLE_SIZE;
+
+		if (addr >= PCIE_MEM_START) {
+			printk(KERN_ERR "%s: Invalid address, aborting\n", __func__);
+			break;
+		}
+
+		switch (type) {
+		case 4:
+		#if defined(CONFIG_BLK_DEV_INITRD)
+			initrd_start = (unsigned long)__va(addr);
+			initrd_end = (unsigned long)__va(addr + size);
+		#endif
+			break;
+		case 5:
+			strlcpy(arcs_cmdline, __va(addr), COMMAND_LINE_SIZE);
+			break;
+		}
+	}
+}
+
+static int parse_dreambox_mac_address(u8 *dest)
+{
+	unsigned long mac[2];
+
+	mac[0] = aon_read_mac(0);
+	mac[1] = aon_read_mac(1);
+
+	dest[0] = 0x00;
+	dest[1] = 0x09;
+	dest[2] = 0x34;
+
+	if (mac[0] != 9 || (mac[1] >> 24) != 0x34)
+		mac[1] = 0xaabbcc;
+
+	dest[3] = mac[1] >> 16;
+	dest[4] = mac[1] >> 8;
+	dest[5] = mac[1];
+
+	return 0;
+}
+#endif
+
+unsigned long __initdata cfe_seal;
+unsigned long __initdata cfe_entry;
+unsigned long __initdata cfe_handle;
+
+/***********************************************************************
+ * CFE bootloader queries
+ ***********************************************************************/
+
+static int __init hex(char ch)
+{
+	if (ch >= 'a' && ch <= 'f')
+		return ch-'a'+10;
+	if (ch >= '0' && ch <= '9')
+		return ch-'0';
+	if (ch >= 'A' && ch <= 'F')
+		return ch-'A'+10;
+	return -1;
+}
+
+static int __init hex16(const char *b)
+{
+	int d0, d1;
+
+	d0 = hex(b[0]);
+	d1 = hex(b[1]);
+	if ((d0 == -1) || (d1 == -1))
+		return -1;
+	return (d0 << 4) | d1;
+}
+
+void __init cfe_die(char *fmt, ...)
+{
+	char msg[128];
+	va_list ap;
+	int handle;
+	unsigned int count;
+
+	va_start(ap, fmt);
+	vsprintf(msg, fmt, ap);
+	strcat(msg, "\r\n");
+
+	if (cfe_seal != CFE_EPTSEAL)
+		goto no_cfe;
+
+	/* disable XKS01 so that CFE can access the registers */
+
+#if defined(CONFIG_CPU_BMIPS4380)
+	__write_32bit_c0_register($22, 3,
+		__read_32bit_c0_register($22, 3) & ~BIT(12));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	__write_32bit_c0_register($22, 5,
+		__read_32bit_c0_register($22, 5) & ~BIT(8));
+#endif
+
+	handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+	if (handle < 0)
+		goto no_cfe;
+
+	cfe_write(handle, msg, strlen(msg));
+
+	for (count = 0; count < 0x7fffffff; count++)
+		mb();
+	cfe_exit(0, 1);
+	while (1)
+		;
+
+no_cfe:
+	/* probably won't print anywhere useful */
+	printk(KERN_ERR "%s", msg);
+	BUG();
+
+	va_end(ap);
+}
+
+static inline int __init parse_eth0_hwaddr(const char *buf, u8 *out)
+{
+	int i, t;
+	u8 addr[6];
+
+	for (i = 0; i < 6; i++) {
+		t = hex16(buf);
+		if (t == -1)
+			return -1;
+		addr[i] = t;
+		buf += 3;
+	}
+	memcpy(out, addr, 6);
+
+	return 0;
+}
+
+static inline int __init parse_eth0_mdio_mode(const char *buf,
+	unsigned long *val)
+{
+	if (strcmp(buf, "boot") == 0 || strcmp(buf, "0") == 0)
+		*val = 1;
+	return 0;
+}
+
+static inline int __init parse_ulong(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 0);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_hex(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 16);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_cmdline(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, COMMAND_LINE_SIZE);
+	return 0;
+}
+
+static inline int __init parse_string(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, CFE_STRING_SIZE);
+	return 0;
+}
+
+static char __initdata cfe_buf[COMMAND_LINE_SIZE];
+
+static void __init __maybe_unused cfe_read_configuration(void)
+{
+	int fetched = 0;
+
+	printk(KERN_INFO "Fetching vars from bootloader... ");
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+	parse_dreambox_mac_address(brcm_primary_macaddr);
+#endif
+	if (cfe_seal != CFE_EPTSEAL) {
+		printk(KERN_CONT "none present, using defaults.\n");
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+		parse_eth0_mdio_mode("1", &brcm_eth0_no_mdio);
+		parse_string("RGMII_NO_ID", brcm_eth0_phy);
+		parse_string("probe", brcm_eth0_phyaddr);
+		parse_ulong("1000", &brcm_eth0_speed);
+		parse_ulong("1024", &brcm_dram0_size_mb);
+		parse_ulong("1024", &brcm_dram1_size_mb);
+		parse_ulong("768", &brcm_dram1_linux_mb);
+		parse_string("BCM97435B0", brcm_cfe_boardname);
+		parse_ulong("16", &brcm_mtd_flash_size_mb);
+		parse_string("SPI", brcm_mtd_flash_type);
+		parse_blob_table();
+#endif
+		return;
+	}
+
+#define DPRINTK(...) do { } while (0)
+/* #define DPRINTK(...) printk(__VA_ARGS__) */
+
+#define FETCH(name, fn, arg) do { \
+	if (cfe_getenv(name, cfe_buf, COMMAND_LINE_SIZE) == CFE_OK) { \
+		DPRINTK("Fetch var '%s' = '%s'\n", name, cfe_buf); \
+		fn(cfe_buf, arg); \
+		fetched++; \
+	} else { \
+		DPRINTK("Could not fetch var '%s'\n", name); \
+	} \
+	} while (0)
+
+	FETCH("ETH0_HWADDR", parse_eth0_hwaddr, brcm_primary_macaddr);
+	FETCH("ETH0_MDIO_MODE", parse_eth0_mdio_mode, &brcm_eth0_no_mdio);
+	FETCH("ETH0_PHY", parse_string, brcm_eth0_phy);
+	FETCH("ETH0_PHYADDR", parse_string, brcm_eth0_phyaddr);
+	FETCH("ETH0_SPEED", parse_ulong, &brcm_eth0_speed);
+
+	FETCH("DRAM0_SIZE", parse_ulong, &brcm_dram0_size_mb);
+	FETCH("DRAM1_SIZE", parse_ulong, &brcm_dram1_size_mb);
+	FETCH("CFE_BOARDNAME", parse_string, brcm_cfe_boardname);
+	FETCH("BOOT_FLAGS", parse_cmdline, arcs_cmdline);
+
+	FETCH("LINUX_FFS_STARTAD", parse_hex, &brcm_mtd_rootfs_start);
+	FETCH("LINUX_FFS_SIZE", parse_hex, &brcm_mtd_rootfs_len);
+	FETCH("LINUX_PART_STARTAD", parse_hex, &brcm_mtd_kernel_start);
+	FETCH("LINUX_PART_SIZE", parse_hex, &brcm_mtd_kernel_len);
+	FETCH("OCAP_PART_STARTAD", parse_hex, &brcm_mtd_ocap_start);
+	FETCH("OCAP_PART_SIZE", parse_hex, &brcm_mtd_ocap_len);
+	FETCH("FLASH_SIZE", parse_ulong, &brcm_mtd_flash_size_mb);
+	FETCH("FLASH_TYPE", parse_string, brcm_mtd_flash_type);
+
+	printk(KERN_CONT "found %d vars.\n", fetched);
+}
+
+/***********************************************************************
+ * Early printk
+ ***********************************************************************/
+
+static unsigned long brcm_early_uart;
+
+#define UART_REG(x)		(brcm_early_uart + ((x) << 2))
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+#define BAUD			1000000
+#else
+#define BAUD			115200
+#endif
+
+static void __init init_port(unsigned int baud)
+{
+	unsigned int divisor;
+
+	BDEV_WR(UART_REG(UART_LCR), 0x3);	/* 8n1 */
+	BDEV_WR(UART_REG(UART_IER), 0);		/* no interrupt */
+	BDEV_WR(UART_REG(UART_FCR), 0);		/* no fifo */
+	BDEV_WR(UART_REG(UART_MCR), 0x3);	/* DTR + RTS */
+
+	BDEV_SET(UART_REG(UART_LCR), UART_LCR_DLAB);
+#if defined(CONFIG_BRCM_IKOS)
+	/* Reverse-engineer brcm_base_baud0 from the bootloader's setting */
+
+	divisor = (BDEV_RD(UART_REG(UART_DLM)) << 8) |
+		BDEV_RD(UART_REG(UART_DLL));
+	brcm_base_baud0 = divisor * baud;
+#endif
+	divisor = (brcm_base_baud0 + baud/2) / baud;
+	BDEV_WR(UART_REG(UART_DLL), divisor & 0xff);
+	BDEV_WR(UART_REG(UART_DLM), (divisor >> 8) & 0xff);
+	BDEV_UNSET(UART_REG(UART_LCR), UART_LCR_DLAB);
+}
+
+void prom_putchar(char x)
+{
+	while (!(BDEV_RD(UART_REG(UART_LSR)) & UART_LSR_THRE))
+		;
+	BDEV_WR(UART_REG(UART_TX), x);
+}
+
+static void __init brcm_setup_early_printk(void)
+{
+	char *arg = strstr(arcs_cmdline, "console=");
+	int dev = CONFIG_BRCM_CONSOLE_DEVICE;
+	const unsigned long base[] = {
+		BCHP_UARTA_REG_START, BCHP_UARTB_REG_START,
+#ifdef CONFIG_BRCM_HAS_UARTC
+		BCHP_UARTC_REG_START,
+#endif
+	};
+	unsigned int baud = 0;
+	unsigned int field = 0;
+
+	/*
+	 * quick command line parse to pick the early printk console
+	 * valid formats:
+	 *   console=ttyS0,115200
+	 *   console=0,115200
+	 */
+	while (arg && *arg != '\0' && *arg != ' ') {
+		if ((*arg >= '0') && (*arg <= (field ? '9' : '3'))) {
+			unsigned int digit = *arg - '0';
+			if (field == 0 && digit < ARRAY_SIZE(base)) {
+				dev = digit;
+			} else if (field == 1) {
+				baud *= 10;
+				baud += digit;
+			} else {
+				break;
+			}
+		} else if (*arg == ',') {
+			field++;
+		}
+		arg++;
+	}
+	brcm_early_uart = base[dev];
+	init_port(baud ? baud : BAUD);
+}
+
+/***********************************************************************
+ * Main entry point
+ ***********************************************************************/
+
+void __init prom_init(void)
+{
+	char *ptr;
+
+	cfe_init(cfe_handle, cfe_entry);
+
+	cfe_write(cfe_handle, "Yo!", strlen("Yo!"));
+
+	bchip_check_compat();
+	brcmstb_cpu_setup();
+
+	/* default to SATA (where available) or MTD rootfs */
+#ifdef CONFIG_BRCM_HAS_SATA
+	ROOT_DEV = Root_SDA1;
+#else
+	ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
+#endif
+	root_mountflags &= ~MS_RDONLY;
+
+	bchip_set_features();
+
+#if defined(CONFIG_BRCM_IKOS_DEBUG)
+	strcpy(arcs_cmdline, "debug initcall_debug");
+#elif !defined(CONFIG_BRCM_IKOS)
+	cfe_read_configuration();
+#endif
+	brcm_setup_early_printk();
+
+	/* provide "ubiroot" alias to reduce typing */
+	if (strstr(arcs_cmdline, "ubiroot"))
+		strcat(arcs_cmdline, " ubi.mtd=rootfs rootfstype=ubifs "
+			"root=ubi0:rootfs");
+
+	ptr = strstr(arcs_cmdline, "memc1=");
+	if (ptr)
+		brcm_dram1_linux_mb = memparse(ptr + 6, &ptr) >> 20;
+
+	printk(KERN_INFO "Options: moca=%d sata=%d pcie=%d usb=%d\n",
+		brcm_moca_enabled, brcm_sata_enabled,
+		brcm_pcie_enabled, brcm_usb_enabled);
+
+	bchip_early_setup();
+	board_pinmux_setup();
+
+	board_get_ram_size(&brcm_dram0_size_mb, &brcm_dram1_size_mb);
+
+	do {
+		unsigned long dram0_mb = brcm_dram0_size_mb, mb;
+
+		mb = min(dram0_mb, BRCM_MAX_LOWER_MB);
+		dram0_mb -= mb;
+
+		add_memory_region(0, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+		mb = min(dram0_mb, BRCM_MAX_UPPER_MB);
+		dram0_mb -= mb;
+
+		plat_wired_tlb_setup();
+		add_memory_region(UPPERMEM_START, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+#endif
+
+#if defined(CONFIG_HIGHMEM)
+		add_memory_region(HIGHMEM_START, dram0_mb << 20, BOOT_MEM_RAM);
+		break;
+#endif
+		/*
+		 * We wound up here because the chip's architecture cannot
+		 * make use of all MEMC0 RAM in Linux.  i.e. no suitable
+		 * HIGHMEM or upper memory options are supported by the CPU.
+		 *
+		 * But we can still report the excess memory as a "bonus"
+		 * reserved (bmem) region, so the application can manage it.
+		 */
+		mb = brcm_dram0_size_mb - dram0_mb;	/* Linux memory */
+		if (!brcm_dram1_size_mb) {
+			printk(KERN_INFO "MEMC0 split: %lu MB -> Linux; "
+				"%lu MB -> extra bmem\n", mb, dram0_mb);
+			brcm_dram1_size_mb = dram0_mb;
+			brcm_dram1_start = UPPERMEM_START;
+		}
+	} while (0);
+
+#if defined(CONFIG_HIGHMEM) && defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	if (brcm_dram1_linux_mb > brcm_dram1_size_mb) {
+		printk(KERN_WARNING "warning: 'memc1=%luM' exceeds "
+			"available memory (%lu MB); ignoring\n",
+			brcm_dram1_linux_mb, brcm_dram1_size_mb);
+		brcm_dram1_linux_mb = 0;
+	} else if (brcm_dram1_linux_mb)
+		add_memory_region(MEMC1_START, brcm_dram1_linux_mb << 20,
+			BOOT_MEM_RAM);
+#else
+	if (brcm_dram1_linux_mb) {
+		printk(KERN_WARNING "warning: MEMC1 is not available on this "
+			"system; ignoring\n");
+		brcm_dram1_linux_mb = 0;
+	}
+#endif
+
+	board_ebase_setup = &bmips_ebase_setup;
+	register_bmips_smp_ops();
+}
+
+/***********************************************************************
+ * NMI hook
+ ***********************************************************************/
+
+static void (*nmi_fn)(struct pt_regs *);
+
+static int brcm_nmi_notifier(struct notifier_block *nb,
+	unsigned long val, void *v)
+{
+	nmi_fn(NULL);
+	return 0;
+}
+
+void brcm_set_nmi_handler(void (*fn)(struct pt_regs *))
+{
+	nmi_notifier(brcm_nmi_notifier, 0);
+}
+EXPORT_SYMBOL(brcm_set_nmi_handler);
+
+/***********************************************************************
+ * Miscellaneous utility functions
+ ***********************************************************************/
+
+static char brcm_system_type[64];
+
+const char *get_system_type(void)
+{
+	u32 class = BRCM_CHIP_ID();
+
+	if (class >> 16 == 0)
+		class >>= 8;
+	else
+		class >>= 12;
+
+	snprintf(brcm_system_type, 64, "BCM%04x%02X %s platform",
+		BRCM_CHIP_ID(), BRCM_CHIP_REV() + 0xa0,
+		class == 0x35 ? "DTV" :
+		(class == 0x76 ? "DVD" : "STB"));
+
+	return (const char *)brcm_system_type;
+}
+
+void __init prom_free_prom_memory(void) {}
+
+static void brcm_machine_restart_mips(char *command)
+{
+	/* On ARM the argument needs to be const */
+	brcm_machine_restart(command);
+}
+
+void __init plat_mem_setup(void)
+{
+	_machine_restart = brcm_machine_restart_mips;
+	_machine_halt = brcm_machine_halt;
+	pm_power_off = brcm_machine_halt;
+
+	brcm_wraparound_check();
+	panic_timeout = 180;
+
+#ifdef CONFIG_PCI
+	pcibios_plat_setup = brcmstb_pcibios_setup;
+#endif
+
+//	add_preferred_console("ttyS", CONFIG_BRCM_CONSOLE_DEVICE, "115200");
+}
diff --git a/arch/mips/brcmstb/s3_standby.S b/arch/mips/brcmstb/s3_standby.S
new file mode 100644
index 000000000000..971b43299eb1
--- /dev/null
+++ b/arch/mips/brcmstb/s3_standby.S
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+
+/*
+ * Bootloader parameters for warm boot:
+ *	byte offset	value
+ *	0-3:		magic word
+ *	4-7:		reentry address
+ *	8-11:		m2m descriptors PA
+ *	12-15:		encryption slot
+ *	16-19:		address of hash
+ *	20-35:		hash
+ */
+	.text
+	.set		noreorder
+	.align		5
+	.global		s3_reentry
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_SD
+#else
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_D
+#endif
+
+/*
+ * We do not need stack frame, the entire context gets saved
+ * in a dedicated structure brcm_pm_s3_context
+ * Upon warm reboot the context gets restored from this structure
+ * Parameters:
+ *	a0: options
+ *	a1: dram encoder start function or NULL if not installed
+ *	a2: d-cache line size
+ */
+	LEAF(brcm_pm_s3_standby_asm)
+
+	la	t0, s3_context
+	/* general purpose registers */
+	sw	ra, 0(t0)
+	sw	s0, 4(t0)
+	sw	s1, 8(t0)
+	sw	s2, 12(t0)
+	sw	s3, 16(t0)
+	sw	s4, 20(t0)
+	sw	s5, 24(t0)
+	sw	s6, 28(t0)
+	sw	s7, 32(t0)
+	sw	gp, 36(t0)
+	sw	sp, 40(t0)
+	sw	fp, 44(t0)
+
+	mfc0	t1, CP0_STATUS
+# save cp0 sr
+	sw	t1, 48(t0)
+
+# Write-back gp registers - cache will be gone after wakeup
+# align context area address to the cache line
+	addiu	t1, a2, -1
+	not	t1
+	and	t0, t1
+
+# flush at least 64 bytes
+	addiu	t2, t0, 64
+	and	t2, t1
+
+1:	cache	CACHE_WRITEBACK_CMD, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, a2
+
+	beqz	a1, skip_dram_encode
+	nop
+
+	/*
+	 * Call DRAM encoder start method if it was installed
+	 * Nobody can modify DRAM content by now.
+	 */
+	jal	a1
+	nop
+
+/* NOTE: Uncommenting this block will force hash mismatch
+ * if .data segment is in the authentication region.
+ * Use for CFE secure warm boot testing.
+ */
+#	la	t0, secure_s3_dummy_data
+#	lw	t1, 0(t0)
+#	addi	t1, 1
+#	sw	t1, 0(t0)
+#	cache	CACHE_WRITEBACK_CMD, 0(t0)
+#	nop
+
+skip_dram_encode:
+
+	li	t0, REG(BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# deep power down request
+pd_request:
+	li	t0, REG(BCHP_AON_CTRL_PM_CTRL)
+# SET: pm_deep_standby, pm_warm_boot, pm_enable_pll_pwrdn
+	li	t1, 0x32
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# SET: pm_start_pwrdn
+	li	t1, 0x33
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+s3_reentry:
+
+#ifdef CONFIG_CPU_BMIPS5000
+# clear CRS and JTB
+	li	t0, (0x06 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+
+	li	t0, (0x04 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+#endif
+
+#ifdef CONFIG_CPU_BMIPS4380
+# flush 4-entry call/return stack
+	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:
+#endif
+
+# restore sr
+	sync
+	nop
+
+s3_standby_exit:
+#ifdef CONFIG_BRCM_UPPER_768MB
+#if defined(CONFIG_CPU_BMIPS4380)
+	mfc0	t0, $22, 3
+	li	t1, 0x1ff0
+	li	t2, (1 << 12) | (1 << 9)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 3
+#elif defined(CONFIG_CPU_BMIPS5000)
+	mfc0	t0, $22, 5
+	li	t1, 0x01ff
+	li	t2, (1 << 8) | (1 << 5)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 5
+#endif
+#endif
+	sync
+	nop
+
+	/* setup mmu defaults */
+	mtc0	zero, CP0_WIRED
+	mtc0	zero, CP0_ENTRYHI
+	li	k0, PM_DEFAULT_MASK
+	mtc0	k0, CP0_PAGEMASK
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	li	sp, BMIPS_WARM_RESTART_VEC
+	la	k0, plat_wired_tlb_setup
+	jalr	k0
+	nop
+#endif
+
+# return to caller
+	/* general purpose registers */
+	la	t0, s3_context
+	lw	ra, 0(t0)
+	lw	s0, 4(t0)
+	lw	s1, 8(t0)
+	lw	s2, 12(t0)
+	lw	s3, 16(t0)
+	lw	s4, 20(t0)
+	lw	s5, 24(t0)
+	lw	s6, 28(t0)
+	lw	s7, 32(t0)
+	lw	gp, 36(t0)
+	lw	sp, 40(t0)
+	lw	fp, 44(t0)
+
+# restore cp0 sr
+	lw	t1, 48(t0)
+	mtc0	t1, CP0_STATUS
+
+	li	v0, 1
+	jr	ra
+	nop
+
+
+	END(brcm_pm_s3_standby_asm)
+
+	.align 4
+	.data
+secure_s3_dummy_data:	.word 0
+
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+__dputc:
+
+	li	t1, REG(BCHP_UARTA_REG_START)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+s3_standby_section_end:
+	nop
diff --git a/arch/mips/brcmstb/standby.S b/arch/mips/brcmstb/standby.S
new file mode 100644
index 000000000000..869e9cf7ef48
--- /dev/null
+++ b/arch/mips/brcmstb/standby.S
@@ -0,0 +1,1170 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+#define UPG_USEC_TICKS		(UPGTMR_FREQ / 1000000)
+
+/* debug output - BRCM_STANDBY_VERBOSE */
+#define UART_BASE		BCHP_UARTA_REG_START
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+#define USE_WATCHDOG		0
+
+#if defined(BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK) || \
+ defined(BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK)
+#define PM_CMD_BASE		0x0b
+#else
+#define PM_CMD_BASE		0x03
+#endif
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define PM_USE_MIPS_READY	0x04
+#else
+#define PM_USE_MIPS_READY	0x00
+#endif
+
+#define PM_STANDBY_COMMAND	(PM_CMD_BASE|PM_USE_MIPS_READY)
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+#define VCDL_SAVE_REG		BCHP_MEMC_DDR23_APHY_WL1_0_SPARE0_RW
+#define RELOAD_VCDL		1
+#else
+#define RELOAD_VCDL		0
+#endif
+
+#define PM_WAIT_COUNT		BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT
+#define PM_CONTROL		BCHP_AON_CTRL_PM_CTRL
+#define PM_STATUS		BCHP_AON_CTRL_PM_STATUS
+#define PM_STATUS_bsp_ready	BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK
+
+#define FLAGREG			s5
+
+	.text
+	.set	noreorder
+	.align	5
+
+# a0 is icache line size
+# a1 is the interrupt vector (or general exception base)
+# a2 is the interrupt vector size
+# a3 is brcm_pm_standby_flags
+
+	LEAF(brcm_pm_standby_asm)
+	subu	sp, 64
+	sw	ra, 0(sp)
+	sw	s0, 4(sp)
+	sw	s1, 8(sp)
+	sw	s2, 12(sp)
+	sw	s3, 16(sp)
+	sw	s4, 20(sp)
+	sw	s5, 24(sp)
+	sw	s6, 28(sp)
+	sw	s7, 32(sp)
+
+	move	FLAGREG, a3
+
+	bal	memc_settings_valid
+	nop
+	bnez	v0, standby_exit
+	nop
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+	/*
+	 * Save VCDL values:
+	 * WL0_0_BYTE0 -> bits 07:00
+	 * WL0_0_BYTE1 -> bits 15:08
+	 * WL1_0_BYTE0 -> bits 23:16
+	 * WL1_0_BYTE1 -> bits 31:24
+	 */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t2, t1, 0x1f
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 8
+	or	t2, t1
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 16
+	or	t2, t1
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 24
+	or	t2, t1
+
+	li	t0, REG(VCDL_SAVE_REG)
+	sw	t2, 0(t0)
+	lw	zero, 0(t0)
+#endif
+
+#ifdef CONFIG_CPU_BMIPS5000
+	/*
+	 * reset jump target buffer and call/return stack, to avoid
+	 * unexpected accesses to DRAM
+	 */
+	li	t0, 0x00040000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	li	t0, 0x00060000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop
+#endif
+
+# lock the asm section into the I-cache
+	move	s0, a0
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	0x1c, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+# now lock the interrupt vector
+	move	t0, zero
+2:
+	cache	0x1c, 0(a1)
+	addu	a1, s0
+	addu	t0, s0
+	ble	t0, a2, 2b
+	nop
+
+	bal	dputc
+	li	a0, 's'
+
+/***********************************************************************
+ * Flush memory transactions and put MEMC into standby
+ ***********************************************************************/
+	sync
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x2d43
+2:
+#endif
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR_0_POWER_DOWN_STATUS)
+1:	lw	t1, 0(t0)
+	andi	t1, BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK
+	beqz	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'd'
+
+#endif
+
+/*
+ * enable power down of MEMSYS PLL
+ * 7436 and 7425 only
+ */
+#if defined(CONFIG_BCM7346)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+#if defined(CONFIG_BCM7425)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+# power down request
+2:
+	/* delay if requested by the user: 4 * 30s */
+	li	t0, BRCM_STANDBY_DELAY
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	dputc
+	li	a0, 'w'
+
+	li	v1, 4
+1:	li	a0, (UPGTMR_FREQ * 30)
+	bal	delay
+	addiu	v1, -1
+	bnez	v1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'W'
+
+# power down request
+2:
+	/* set wait count */
+	li	t0, REG(PM_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+	li	t0, REG(PM_CONTROL)
+	li	t1, PM_STANDBY_COMMAND
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+# save cp0 sr
+	move	s2, t0
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+/***********************************************************************
+ * Save wakeup timestamp in AON
+ ***********************************************************************/
+	li	t0, REG(BCHP_WKTMR_COUNTER)
+	lw	a0, 0(t0)	/* WKTMR_COUNTER */
+	lw	a1, 12(t0)	/* WKTMR_PRESCALER_VAL */
+	li	t0, REG(AON_RAM_BASE)
+	sw	a0, 0(t0)
+	sw	a1, 4(t0)
+
+/***********************************************************************
+ * Bring MEMC back up
+ ***********************************************************************/
+	bal	dputc
+	li	a0, 'M'
+
+#if USE_WATCHDOG
+# arm the watchdog timer
+	li	t0, REG(BCHP_TIMER_WDTIMEOUT)
+	li	t1, 3 * UPGTMR_FREQ
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_WDCMD)
+	li	t1, 0xff00
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+	li	t1, 0x00ff
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif
+
+	/*
+	 * Bypass MEMC wakeup if DDR PLL is on
+	 */
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	bnez	t0, 2f
+	nop
+
+	bal	wake_up_memc_0
+	nop
+
+2:
+	bal	dputc
+	li	a0, 'm'
+
+#if defined(CONFIG_BRCM_PWR_HANDSHAKE_V0)
+# disarm the BSP
+	li	t0, REG(BCHP_BSP_GLB_CONTROL_REG_START + 0x38)
+	lw	t1, 0(t0)
+	ori	t1, 0xff00
+	xori	t1, 0xfe00
+	sw	t1, 0(t0)
+
+	bal	dputc
+	li	a0, 'B'
+
+	li	t0, REG(PM_STATUS)
+	li	t2, PM_STATUS_bsp_ready
+1:
+	lw	t1, 0(t0)
+	and	t1, t2
+	bnez	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'b'
+#elif defined(CONFIG_BRCM_PWR_HANDSHAKE_V1)
+	li	t0, REG(BCHP_AON_CTRL_HOST_MISC_CMDS)
+	li	t1, BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif /* CONFIG_BRCM_PWR_HANDSHAKE_V0/V1 */
+
+	li	t0, REG(PM_CONTROL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x4a43
+2:
+#endif
+
+/***********************************************************************
+ * Unlock I$ lines and resume execution
+ ***********************************************************************/
+	sync
+
+rtn_from_wait:
+	bal	dputc
+	li	a0, 'S'
+
+# unlock I$ lines
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	Hit_Invalidate_I, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+	bal	dputc
+	li	a0, 'L'
+
+# restore sr
+	sync
+	nop
+
+	bal	dputc
+	li	a0, 'l'
+	bal	dputc
+	li	a0, 0x0d
+	bal	dputc
+	li	a0, 0x0a
+
+	mtc0	s2, CP0_STATUS
+	nop
+
+	li	v0, 0
+
+standby_exit:
+
+# return to caller
+	lw	s7, 32(sp)
+	lw	s6, 28(sp)
+	lw	s5, 24(sp)
+	lw	s4, 20(sp)
+	lw	s3, 16(sp)
+	lw	s2, 12(sp)
+	lw	s1, 8(sp)
+	lw	s0, 4(sp)
+	lw	ra, 0(sp)
+	addiu	sp, 64
+
+	jr	ra
+	nop
+	END(brcm_pm_standby_asm)
+
+# debug character output
+
+dputc:
+	/* INPUT: char in a0 */
+	/* USES: t1, t2 */
+
+	li	t1, BRCM_STANDBY_VERBOSE
+	and	t1, FLAGREG
+	bnez	t1, 1f
+	nop
+	jr	ra
+	nop
+
+1:
+	li	t1, REG(UART_BASE)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Delay loop
+ ***********************************************************************/
+
+delay:
+# need to reset TIMER1 since it is not normally used
+	li	t2, 0x0
+	li	t1, REG(BCHP_TIMER_TIMER1_CTRL)
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0xbfffffff
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0x3fffffff
+	li	t1, REG(BCHP_TIMER_TIMER1_STAT)
+	lw	t0, 0(t1)
+	and	t0, t2
+	add	t0, a0
+	not	t2
+	and	t2, t0
+	bnez	t2, delay_overflow
+	nop
+
+# wait for timer value (t2) to exceed expiry time (t0)
+1:	lw	t2, 0(t1)
+	sltu	t2, t2, t0
+	bnez	t2, 1b
+	nop
+
+	jr	ra
+	nop
+
+# timer1 overflow (this should never happen)
+delay_overflow:
+	move	t4, ra
+	bal	dputc
+	li	a0, 'O'
+
+	jr	t4
+	nop
+
+/***********************************************************************
+ * MEMC wakeup
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+
+#define SLEEP_1_MILLI_SEC		27000
+
+/***********************************************************************
+ * Delay routine
+ ***********************************************************************/
+LEAF(upg_sleep)
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.MODE  = 1 => count down mode */
+	li	t2, BCHP_TIMER_TIMER0_CTRL_MODE_MASK
+	or	t1, t1, t2
+
+	/* TIMER_TIMER0_CTRL.TIMEOUT_VAL = a0 */
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK
+	li	t3, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT
+
+	not	t2, t2
+	and	t1, t1, t2
+	sll	a0, a0, t3
+	or	t1, t1, a0
+
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER_IS.TMR0TO = 1 => clears this bit, resets time count */
+
+	#li	t2, ~BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+	#and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.ENA = 1 => start counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	or	t1, t1, t2
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	li	t2, BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+
+1:	lw	t1, 0(t0)
+	and	t1, t1, t2
+	beq	zero, t1, 1b
+	nop
+
+	/* TIMER_TIMER0_CTRL.ENA = 0 => stop counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+	li	t2, ~BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	jr	ra
+	nop
+
+END(upg_sleep)
+
+/***********************************************************************
+ * Main MEMC0 recovery function
+ ***********************************************************************/
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+	li	a0, 0
+	bal	set_memc_0_write_dqs_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_write_dq_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN_PLLCLKS_OFF_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	bal	reprogram_ddr_pll
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+/***********************************************************************
+ * VCDL incremental reload
+ * a0 - VCDL register
+ * a1 - maximum value
+ ***********************************************************************/
+reload_vcdl:
+	sll	v0, a1, 8
+	or	a1, v0		# max value to load
+
+	move	v1, zero
+vcdl_loop:
+	addi	v1, 0x0101
+	sw	v1, 0(a0)
+	lw	zero, 0(a0)
+	bne	v1, a1, vcdl_loop
+	nop
+
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Set new DDR PLL frequency divider
+ * Used when suspending with DDR PLL on
+ * a0 - Frequency divider value
+ ***********************************************************************/
+LEAF(set_pll_frequency)
+
+	move	s3, ra
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL)
+	sw	a0, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (27000)
+	bal	upg_sleep
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	jr	s3
+	nop
+END(set_pll_frequency)
+
+/***********************************************************************
+ * DDR PLL reset and reconfiguration
+ ***********************************************************************/
+LEAF(reprogram_ddr_pll)
+
+	move	s6, ra
+
+	/* reset the freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR  */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, (BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* wait for 1ms for stable clock */
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* check for pll lock */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA4)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl0_dq_phase
+	nop
+
+	/* set wl1_dq phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA5)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl1_dq_phase
+	nop
+
+	/* set ch2 phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA6)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set ch6 phase */
+	li	a1, REG(BCHP_MEMC_MISC_0_SCRATCH_0)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set wl0_dqs0 phases */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA0)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs0_phase
+	nop
+
+	/* set wl0_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA1)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs1_phase
+	nop
+
+	/* set wl1_dqs0 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA2)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs2_phase
+	nop
+	/* set wl1_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA3)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs3_phase
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL)
+	lw	v1, 0(v0)
+	ori     v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	xori	v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	sw	v1, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the word slice dll */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 1
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset VCDL values */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 0
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* de-assert reset from DATAPATH_216 and DATAPATH_DDR */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	lw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_216_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from RD_DATAPATH_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_DDR_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/*
+	 * Reload VCDL values:
+	 * WL0_0_BYTE0 <- bits 07:00
+	 * WL0_0_BYTE1 <- bits 15:08
+	 * WL1_0_BYTE0 <- bits 23:16
+	 * WL1_0_BYTE1 <- bits 31:24
+	 */
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	li	t0, REG(VCDL_SAVE_REG)
+	lw	t0, 0(t0)
+	bal	reload_vcdl
+	andi	a1, t0, 0x1f
+
+	srl	a1, t0, 8
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 16
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 24
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	jr	s6
+	nop
+
+END(reprogram_ddr_pll)
+
+LEAF(set_memc_0_write_dqs_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dqs_phase_cntl_direct)
+
+LEAF(set_memc_0_write_dq_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dq_phase_cntl_direct)
+
+LEAF(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH2_CLOCK_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+END(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+LEAF(set_memc_0_deskew_bypass_phase)
+
+	li	t8, REG(BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL)
+	lw	t7, 0(t8)
+
+	li	t6, ~BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_MASK
+	and	t7, t7, t6
+
+	li	t6, BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_SHIFT
+	sll	t5, a0, t6
+	or	t7, t7, t5
+	sw	t7, 0(t8)
+
+	jr	ra
+	nop
+END(set_memc_0_deskew_bypass_phase)
+
+LEAF(set_memc_0_wl0_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl0_dq_phase)
+
+LEAF(set_memc_0_wl1_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl1_dq_phase)
+
+
+LEAF(set_memc_0_dqs0_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs0_phase)
+
+LEAF(set_memc_0_dqs1_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+
+END(set_memc_0_dqs1_phase)
+
+LEAF(set_memc_0_dqs2_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs2_phase)
+
+LEAF(set_memc_0_dqs3_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs3_phase)
+
+LEAF(memc_settings_valid)
+
+	li	t2, 0xdeadbeef
+	li	t1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA7)
+	lw	t0, 0(t1)
+	li	v0, 0
+	beq	t0, t2, 1f
+	nop
+	li	v0, -1
+
+1:	jr	ra
+	nop
+
+END(memc_settings_valid)
+
+#endif /* CONFIG_BRCM_HAS_ANALOG_DDR_PHY */
+
+#ifdef CONFIG_BRCM_HAS_DIGITAL_DDR_PHY
+
+LEAF(memc_settings_valid)
+
+1:	jr	ra
+	li	v0, 0
+
+END(memc_settings_valid)
+
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, 0
+	sw	t1, 0(t0)
+#endif
+
+#ifdef BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS
+	li	t0, REG(BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS)
+#elif defined(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+	li	t0, REG(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+#else
+#error No MEMC phy control register defined
+#endif
+
+1:	lw	t1, 0(t0)
+	andi	t1, 1
+	beqz	t1, 1b
+	nop
+
+# 1 ms delay - needed on 7552/7358 for stable recovery
+	li	a0, (27000)
+	bal	delay
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+#endif /* CONFIG_BRCM_HAS_DIGITAL_DDR_PHY */
+
+	.globl passiveIRQ_end
+passiveIRQ_end:
+	nop
diff --git a/arch/mips/brcmstb/time.c b/arch/mips/brcmstb/time.c
new file mode 100644
index 000000000000..c38f56a744dc
--- /dev/null
+++ b/arch/mips/brcmstb/time.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clocksource.h>
+#include <linux/printk.h>
+#include <linux/spinlock.h>
+
+#include <asm/time.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* MIPS clock measured at boot time.  Value is not changed by PM. */
+unsigned long brcm_cpu_khz;
+
+/* Sampling period for MIPS calibration.  50 = 1/50 of a second. */
+#define SAMPLE_PERIOD		50
+
+/***********************************************************************
+ * UPG clocksource
+ ***********************************************************************/
+
+static cycle_t upg_cs_read(struct clocksource *cs)
+{
+	return BDEV_RD_F(TIMER_TIMER3_STAT, COUNTER_VAL);
+}
+
+static struct clocksource clocksource_upg = {
+	.name		= "upg",
+	.read		= upg_cs_read,
+	.mask		= CLOCKSOURCE_MASK(30),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_upg_clocksource(void)
+{
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0xbfffffff);
+
+	clocksource_upg.rating = 250;
+	clocksource_register_hz(&clocksource_upg, UPGTMR_FREQ);
+}
+
+#ifdef CONFIG_BRCM_HAS_WKTMR
+
+/***********************************************************************
+ * WKTMR clocksource
+ ***********************************************************************/
+
+static DEFINE_SPINLOCK(wktmr_lock);
+
+static cycle_t wktmr_cs_read(struct clocksource *cs)
+{
+	static struct wktmr_time offs = { (uint32_t)-1, (uint32_t)-1 };
+	struct wktmr_time t;
+	unsigned long flags;
+
+	spin_lock_irqsave(&wktmr_lock, flags);
+	wktmr_read(&t);
+	if (offs.pre == (uint32_t)-1 && offs.sec == offs.pre)
+		offs = t;
+	spin_unlock_irqrestore(&wktmr_lock, flags);
+
+	t.sec -= offs.sec;
+	t.pre -= offs.pre;
+	if ((int32_t)t.pre < 0) {
+		t.pre += WKTMR_FREQ;
+		--t.sec;
+	}
+
+	return (t.sec * (cycle_t)WKTMR_FREQ) + t.pre;
+}
+
+static struct clocksource clocksource_wktmr = {
+	.name		= "wktmr",
+	.read		= wktmr_cs_read,
+	.mask		= CLOCKSOURCE_MASK(64),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_wktmr_clocksource(void)
+{
+	clocksource_wktmr.rating = 250;
+	clocksource_register_hz(&clocksource_wktmr, WKTMR_FREQ);
+}
+
+/*
+ * MIPS frequency calibration (WKTMR)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	struct wktmr_time start;
+
+	wktmr_read(&start);
+	write_c0_count(0);
+
+	while (wktmr_elapsed(&start) < (WKTMR_FREQ / SAMPLE_PERIOD))
+		;
+
+	return read_c0_count() * SAMPLE_PERIOD;
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+
+	ts->tv_sec = now.sec;
+	ts->tv_nsec = now.pre * (1000000000/WKTMR_FREQ);
+}
+
+
+#else /* CONFIG_BRCM_HAS_WKTMR */
+
+/*
+ * MIPS frequency calibration (UPG TIMER3)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	unsigned long ret;
+
+	/* reset countdown timer */
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+
+	/* set up for countdown */
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0xc0000000 |
+		(UPGTMR_FREQ / SAMPLE_PERIOD));
+	write_c0_count(0);
+
+	while ((BDEV_RD(BCHP_TIMER_TIMER_IS) & 1) == 0)
+		;
+
+	ret = read_c0_count();
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0);
+
+	return ret * SAMPLE_PERIOD;
+}
+
+#endif /* CONFIG_BRCM_HAS_WKTMR */
+
+/***********************************************************************
+ * Timer setup
+ ***********************************************************************/
+
+void __init plat_time_init(void)
+{
+	unsigned int khz;
+
+	pr_info("Measuring MIPS counter frequency...\n");
+	mips_hpt_frequency = brcm_mips_freq();
+	khz = mips_hpt_frequency / 1000;
+#ifdef CONFIG_CPU_BMIPS5000
+	brcm_cpu_khz = mips_hpt_frequency * 8 / 1000;
+#else
+	brcm_cpu_khz = mips_hpt_frequency * 2 / 1000;
+#endif
+
+	pr_info("Detected MIPS clock frequency: %lu MHz (%u.%03u MHz counter)\n",
+		brcm_cpu_khz / 1000, khz / 1000, khz % 1000);
+
+#ifdef CONFIG_CSRC_WKTMR
+	init_wktmr_clocksource();
+#endif
+#ifdef CONFIG_CSRC_UPG
+	init_upg_clocksource();
+#endif
+}
diff --git a/arch/mips/configs/bcm7228a0_defconfig b/arch/mips/configs/bcm7228a0_defconfig
new file mode 100644
index 000000000000..36c730277355
--- /dev/null
+++ b/arch/mips/configs/bcm7228a0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7228A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7231b0_defconfig b/arch/mips/configs/bcm7231b0_defconfig
new file mode 100644
index 000000000000..2d79a2703e51
--- /dev/null
+++ b/arch/mips/configs/bcm7231b0_defconfig
@@ -0,0 +1,119 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7231B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7344b0_defconfig b/arch/mips/configs/bcm7344b0_defconfig
new file mode 100644
index 000000000000..56cedd3f2ee8
--- /dev/null
+++ b/arch/mips/configs/bcm7344b0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7344B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7346b0_defconfig b/arch/mips/configs/bcm7346b0_defconfig
new file mode 100644
index 000000000000..017814ce2ab3
--- /dev/null
+++ b/arch/mips/configs/bcm7346b0_defconfig
@@ -0,0 +1,119 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7346B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7358a0_defconfig b/arch/mips/configs/bcm7358a0_defconfig
new file mode 100644
index 000000000000..7ad0b68a7c6f
--- /dev/null
+++ b/arch/mips/configs/bcm7358a0_defconfig
@@ -0,0 +1,114 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7358A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7360a0_defconfig b/arch/mips/configs/bcm7360a0_defconfig
new file mode 100644
index 000000000000..c6f162adbd59
--- /dev/null
+++ b/arch/mips/configs/bcm7360a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7360A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7362a0_defconfig b/arch/mips/configs/bcm7362a0_defconfig
new file mode 100644
index 000000000000..604cebd968d7
--- /dev/null
+++ b/arch/mips/configs/bcm7362a0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7362A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7425b0_defconfig b/arch/mips/configs/bcm7425b0_defconfig
new file mode 100644
index 000000000000..2993a8b3657c
--- /dev/null
+++ b/arch/mips/configs/bcm7425b0_defconfig
@@ -0,0 +1,123 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7425B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7429b0_defconfig b/arch/mips/configs/bcm7429b0_defconfig
new file mode 100644
index 000000000000..2f993ca30050
--- /dev/null
+++ b/arch/mips/configs/bcm7429b0_defconfig
@@ -0,0 +1,118 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7429B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7435b0_defconfig b/arch/mips/configs/bcm7435b0_defconfig
new file mode 100644
index 000000000000..a00d39a76171
--- /dev/null
+++ b/arch/mips/configs/bcm7435b0_defconfig
@@ -0,0 +1,121 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7435B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7543a0_defconfig b/arch/mips/configs/bcm7543a0_defconfig
new file mode 100644
index 000000000000..6f324ee0f41d
--- /dev/null
+++ b/arch/mips/configs/bcm7543a0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7543A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7552b0_defconfig b/arch/mips/configs/bcm7552b0_defconfig
new file mode 100644
index 000000000000..73b2f98247e9
--- /dev/null
+++ b/arch/mips/configs/bcm7552b0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7552B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7563a0_defconfig b/arch/mips/configs/bcm7563a0_defconfig
new file mode 100644
index 000000000000..118578f14a7e
--- /dev/null
+++ b/arch/mips/configs/bcm7563a0_defconfig
@@ -0,0 +1,120 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7563A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/bcm7584a0_defconfig b/arch/mips/configs/bcm7584a0_defconfig
new file mode 100644
index 000000000000..ff06487a6378
--- /dev/null
+++ b/arch/mips/configs/bcm7584a0_defconfig
@@ -0,0 +1,119 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7584A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/configs/dm520_defconfig b/arch/mips/configs/dm520_defconfig
new file mode 100644
index 000000000000..779b8f14f821
--- /dev/null
+++ b/arch/mips/configs/dm520_defconfig
@@ -0,0 +1,2885 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4.113-4.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+CONFIG_BRCM_LEGACY=y
+# CONFIG_BCM7228A0 is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+CONFIG_BCM7362A0=y
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+# CONFIG_BCM7435B0 is not set
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM520=y
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+# CONFIG_BRCM_FIXED_MTD_PARTITIONS is not set
+CONFIG_MTD_BRCMNAND=y
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+CONFIG_BRCM_USB=y
+# CONFIG_BRCM_OVERRIDE_USB is not set
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+# CONFIG_BRCM_SCSI_NO_RW10_RETRIES is not set
+CONFIG_BRCM_WLAN_MODULES=y
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS4380=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_GENET_V2=y
+CONFIG_BRCM_GENET_VERSION=2
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_0=y
+CONFIG_BRCM_HAS_NAND_MAJOR_5=y
+CONFIG_BRCMNAND_MAJOR_VERS=5
+CONFIG_BRCMNAND_MINOR_VERS=0
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7362=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS4380=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS4380=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm520"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm520"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTDRAM_ABS_POS=0x0
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_DOCG4 is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_MAC80211_HWSIM is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_BRCMSTB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+CONFIG_TTPCI_EEPROM=m
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_R8712U=m
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6656 is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+CONFIG_LIRC_STAGING=y
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=192M@64M console=ttyS0,1000000 ubi.mtd=rootfs root=ubi0:dreambox-rootfs rootfstype=ubifs rw"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/configs/dm7080_defconfig b/arch/mips/configs/dm7080_defconfig
new file mode 100644
index 000000000000..ebdcf81c6b91
--- /dev/null
+++ b/arch/mips/configs/dm7080_defconfig
@@ -0,0 +1,3227 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4-3.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+# CONFIG_BRCM_LEGACY is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+# CONFIG_BCM7362A0 is not set
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+CONFIG_BCM7435B0=y
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM7080=y
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+# CONFIG_MTD_BRCMNAND is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+CONFIG_BRCM_OVERRIDE_USB=y
+# CONFIG_BRCM_FORCE_USB_PWR_LO is not set
+CONFIG_BRCM_FORCE_USB_PWR_HI=y
+CONFIG_BRCM_FORCE_USB_OC_LO=y
+# CONFIG_BRCM_FORCE_USB_OC_HI is not set
+CONFIG_BRCM_USB_DISABLE_MASK=0x00
+CONFIG_BRCM_SDIO=y
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+CONFIG_BRCM_SCSI_NO_RW10_RETRIES=y
+# CONFIG_BRCM_WLAN_MODULES is not set
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS5000=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_HAS_PCIE=y
+CONFIG_BRCM_GENET_V3=y
+CONFIG_BRCM_GENET_VERSION=3
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN22=y
+CONFIG_BRCM_MOCA_VERS=0x2002
+CONFIG_BRCM_HAS_SATA=y
+CONFIG_BRCM_HAS_SATA3=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_2=y
+CONFIG_BRCM_HAS_NAND_MAJOR_6=y
+CONFIG_BRCMNAND_MAJOR_VERS=6
+CONFIG_BRCMNAND_MINOR_VERS=2
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_FLASH_DMA=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_HAS_EMMC=y
+CONFIG_BRCM_ZSCM_L2=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_XI=y
+CONFIG_BRCM_HAS_DUALCORE=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_2GB_MEMC0=y
+CONFIG_BRCM_HAS_1GB_MEMC1=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_HAS_STANDBY=y
+CONFIG_BRCM_HAS_AON=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_HAS_USB_CAPS=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7435=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=7
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS5000=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS5000=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm7080"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm7080"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PCI_DRIVERS is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+
+#
+# Supported SAA7146 based PCI Adapters
+#
+CONFIG_TTPCI_EEPROM=m
+# CONFIG_DVB_AV7110 is not set
+# CONFIG_DVB_BUDGET_CORE is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+# CONFIG_SMS_SDIO_DRV is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported BT878 Adapters
+#
+
+#
+# Supported Pluto2 Adapters
+#
+# CONFIG_DVB_PLUTO2 is not set
+
+#
+# Supported SDMC DM1105 Adapters
+#
+# CONFIG_DVB_DM1105 is not set
+
+#
+# Supported Earthsoft PT1 Adapters
+#
+# CONFIG_DVB_PT1 is not set
+
+#
+# Supported Mantis Adapters
+#
+# CONFIG_MANTIS_CORE is not set
+
+#
+# Supported nGene Adapters
+#
+# CONFIG_DVB_NGENE is not set
+
+#
+# Supported ddbridge ('Octopus') Adapters
+#
+# CONFIG_DVB_DDBRIDGE is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+# CONFIG_RTS_PSTOR is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_DVB_CXD2099=m
+# CONFIG_VIDEO_DT3155 is not set
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=384M@640M memc1=768M console=ttyS0,1000000 root=/dev/mmcblk0p1 rootwait rootfstype=ext4"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/configs/dm820_defconfig b/arch/mips/configs/dm820_defconfig
new file mode 100644
index 000000000000..0600a942fe79
--- /dev/null
+++ b/arch/mips/configs/dm820_defconfig
@@ -0,0 +1,3227 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 3.4-3.0 Kernel Configuration
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BRCMSTB=y
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_JZ4740 is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+
+#
+# Broadcom STB options
+#
+# CONFIG_BRCM_LEGACY is not set
+# CONFIG_BCM7231B0 is not set
+# CONFIG_BCM7344B0 is not set
+# CONFIG_BCM7346B0 is not set
+# CONFIG_BCM7358A0 is not set
+# CONFIG_BCM7360A0 is not set
+# CONFIG_BCM7362A0 is not set
+# CONFIG_BCM7425B0 is not set
+# CONFIG_BCM7429B0 is not set
+CONFIG_BCM7435B0=y
+# CONFIG_BCM7543A0 is not set
+# CONFIG_BCM7552B0 is not set
+# CONFIG_BCM7563A0 is not set
+# CONFIG_BCM7584A0 is not set
+CONFIG_DREAMBOX=y
+CONFIG_DREAMBOX_DM820=y
+
+#
+# Memory map
+#
+CONFIG_BRCM_UPPER_MEMORY=y
+# CONFIG_BRCM_OVERRIDE_RAM_SIZE is not set
+
+#
+# Onchip peripherals
+#
+CONFIG_BRCM_CONSOLE_DEVICE=0
+CONFIG_BRCM_FLASH=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+# CONFIG_MTD_BRCMNAND is not set
+CONFIG_SPI_BRCMSTB=y
+CONFIG_BCMGENET=y
+
+#
+# BCMGENET options
+#
+# CONFIG_BCMGENET_RX_DESC_THROTTLE is not set
+CONFIG_BCMGENET_NAPI=y
+# CONFIG_BCMGENET_RX_CSUM is not set
+# CONFIG_BCMGENET_TX_CSUM is not set
+# CONFIG_BCMGENET_DUMP_DATA is not set
+# CONFIG_BCMGENET_DUMP_TRACE is not set
+# CONFIG_BRCM_MOCA is not set
+CONFIG_BRCM_USB=y
+CONFIG_BRCM_OVERRIDE_USB=y
+# CONFIG_BRCM_FORCE_USB_PWR_LO is not set
+CONFIG_BRCM_FORCE_USB_PWR_HI=y
+CONFIG_BRCM_FORCE_USB_OC_LO=y
+# CONFIG_BRCM_FORCE_USB_OC_HI is not set
+CONFIG_BRCM_USB_DISABLE_MASK=0x00
+CONFIG_BRCM_SDIO=y
+CONFIG_BRCM_PM=y
+CONFIG_CSRC_WKTMR=y
+# CONFIG_CSRC_UPG is not set
+
+#
+# Miscellaneous options
+#
+CONFIG_BRCM_LIBGCC=y
+CONFIG_BRCM_SCSI_NO_RW10_RETRIES=y
+# CONFIG_BRCM_WLAN_MODULES is not set
+# CONFIG_BRCM_DEBUG_OPTIONS is not set
+CONFIG_BRCM_HAS_BMIPS5000=y
+CONFIG_BRCM_HAS_16550=y
+CONFIG_BRCM_HAS_UARTA=y
+CONFIG_BRCM_UARTA_IS_16550=y
+CONFIG_BRCM_HAS_PCIE=y
+CONFIG_BRCM_GENET_V3=y
+CONFIG_BRCM_GENET_VERSION=3
+CONFIG_BRCM_HAS_GENET=y
+CONFIG_BRCM_HAS_GENET_0=y
+CONFIG_BRCM_HAS_MOCA=y
+CONFIG_BRCM_HAS_MOCA_20_GEN22=y
+CONFIG_BRCM_MOCA_VERS=0x2002
+CONFIG_BRCM_HAS_SATA=y
+CONFIG_BRCM_HAS_SATA3=y
+# CONFIG_BRCM_SATA_75MHZ_PLL is not set
+# CONFIG_BRCM_SATA_SINGLE_PORT is not set
+CONFIG_BRCM_HAS_NOR=y
+CONFIG_BRCM_HAS_NAND_MINOR_2=y
+CONFIG_BRCM_HAS_NAND_MAJOR_6=y
+CONFIG_BRCMNAND_MAJOR_VERS=6
+CONFIG_BRCMNAND_MINOR_VERS=2
+CONFIG_BRCM_HAS_NAND=y
+CONFIG_BRCM_HAS_FLASH_DMA=y
+CONFIG_BRCM_HAS_SPI=y
+CONFIG_BRCM_HAS_BSPI_V4=y
+CONFIG_BRCM_BSPI_MAJOR_VERS=4
+CONFIG_BRCM_HAS_WKTMR=y
+CONFIG_BRCM_HAS_SDIO=y
+CONFIG_BRCM_HAS_SDIO_V1=y
+CONFIG_BRCM_HAS_EMMC=y
+CONFIG_BRCM_ZSCM_L2=y
+CONFIG_BRCM_CPU_DIV=y
+CONFIG_BRCM_HAS_XKS01=y
+CONFIG_BRCM_HAS_XI=y
+CONFIG_BRCM_HAS_DUALCORE=y
+CONFIG_BRCM_HAS_UPPER_MEMORY=y
+CONFIG_BRCM_UPPER_768MB=y
+CONFIG_BRCM_HAS_2GB_MEMC0=y
+CONFIG_BRCM_HAS_1GB_MEMC1=y
+CONFIG_BRCM_HAS_DIGITAL_DDR_PHY=y
+CONFIG_BRCM_HAS_STANDBY=y
+CONFIG_BRCM_HAS_AON=y
+CONFIG_BRCM_PWR_HANDSHAKE=y
+CONFIG_BRCM_PWR_HANDSHAKE_V1=y
+CONFIG_BRCM_HAS_USB_CAPS=y
+CONFIG_BRCM_MIPS_DEFAULTS=y
+CONFIG_BCM7435=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_BOOT_RAW=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CEVT_R4K=y
+CONFIG_CFE=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_MIPS_L1_CACHE_SHIFT=7
+
+#
+# CPU selection
+#
+CONFIG_CPU_BMIPS5000=y
+CONFIG_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS5000=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_CPU_MIPS32=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_BOARD_SCACHE=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_XKS01=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CLEANCACHE=y
+CONFIG_SMP=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+CONFIG_HZ_1000=y
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_USE_OF is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-dm820"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="dm820"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_FORCED_THREADING=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+
+#
+# GCOV-based kernel profiling
+#
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_UNIX_DIAG is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_L2TP=y
+# CONFIG_L2TP_V3 is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+CONFIG_NET_SCH_SFB=m
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+CONFIG_NET_SCH_PLUG=m
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+# CONFIG_NETPRIO_CGROUP is not set
+CONFIG_BQL=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_BT_ATH3K=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_DEFAULT_PS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+CONFIG_CEPH_LIB=m
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+# CONFIG_DMA_SHARED_BUFFER is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_RBD is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2X is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_IPHETH=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_VL600=m
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+CONFIG_AT76C50X_USB=m
+# CONFIG_PRISM54 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_RTL8180 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+CONFIG_ATH5K=m
+# CONFIG_ATH5K_DEBUG is not set
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+# CONFIG_ATH9K_BTCOEX_SUPPORT is not set
+CONFIG_ATH9K=m
+# CONFIG_ATH9K_PCI is not set
+# CONFIG_ATH9K_AHB is not set
+# CONFIG_ATH9K_DFS_CERTIFIED is not set
+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_ATH6KL is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_USB=m
+# CONFIG_P54_PCI is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTL8192CE is not set
+# CONFIG_RTL8192SE is not set
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192CU=m
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_WL1251 is not set
+# CONFIG_WL12XX_MENU is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=m
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_RAMOOPS=m
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_SMB347 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+CONFIG_SENSORS_ADC128D818=y
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_S5M_CORE is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_DVB_CORE=y
+CONFIG_DVB_NET=y
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_RC5_SZ_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_IR_IMON=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_RC_LOOPBACK=m
+# CONFIG_IR_GPIO_CIR is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEOBUF_DVB=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Audio decoders, processors and mixers
+#
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_WM8775=m
+
+#
+# RDS decoders
+#
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_TVP5150=m
+
+#
+# Video and audio decoders
+#
+CONFIG_VIDEO_CX25840=m
+
+#
+# MPEG video encoders
+#
+CONFIG_VIDEO_CX2341X=m
+
+#
+# Video encoders
+#
+
+#
+# Camera sensor devices
+#
+CONFIG_VIDEO_MT9V011=m
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_PVRUSB2_DVB=y
+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+# CONFIG_VIDEO_EM28XX_RC is not set
+CONFIG_VIDEO_TLG2300=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_USBVISION=m
+CONFIG_USB_ET61X251=m
+CONFIG_USB_SN9C102=m
+CONFIG_USB_PWC=m
+# CONFIG_USB_PWC_DEBUG is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_VIDEO_CPIA2 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
+# CONFIG_V4L_PCI_DRIVERS is not set
+# CONFIG_V4L_PLATFORM_DRIVERS is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_CAPTURE_DRIVERS=y
+
+#
+# Supported SAA7146 based PCI Adapters
+#
+CONFIG_TTPCI_EEPROM=m
+# CONFIG_DVB_AV7110 is not set
+# CONFIG_DVB_BUDGET_CORE is not set
+
+#
+# Supported USB Adapters
+#
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_A867=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_FRIIO=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_IT913X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_SMS_SIANO_MDTV=m
+
+#
+# Siano module components
+#
+CONFIG_SMS_USB_DRV=m
+# CONFIG_SMS_SDIO_DRV is not set
+
+#
+# Supported FlexCopII (B2C2) Adapters
+#
+CONFIG_DVB_B2C2_FLEXCOP=m
+# CONFIG_DVB_B2C2_FLEXCOP_PCI is not set
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
+
+#
+# Supported BT878 Adapters
+#
+
+#
+# Supported Pluto2 Adapters
+#
+# CONFIG_DVB_PLUTO2 is not set
+
+#
+# Supported SDMC DM1105 Adapters
+#
+# CONFIG_DVB_DM1105 is not set
+
+#
+# Supported Earthsoft PT1 Adapters
+#
+# CONFIG_DVB_PT1 is not set
+
+#
+# Supported Mantis Adapters
+#
+# CONFIG_MANTIS_CORE is not set
+
+#
+# Supported nGene Adapters
+#
+# CONFIG_DVB_NGENE is not set
+
+#
+# Supported ddbridge ('Octopus') Adapters
+#
+# CONFIG_DVB_DDBRIDGE is not set
+
+#
+# Supported DVB Frontends
+#
+CONFIG_DVB_FE_CUSTOMISE=y
+
+#
+# Customise DVB Frontends
+#
+
+#
+# Multistandard (satellite) frontends
+#
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110x=m
+
+#
+# Multistandard (cable + terrestrial) frontends
+#
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_TDA18271C2DD=m
+
+#
+# DVB-S (satellite) frontends
+#
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STV0299=y
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_TDA10071=m
+
+#
+# DVB-T (terrestrial) frontends
+#
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HD29L2=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_RTL2830=m
+
+#
+# DVB-C (cable) frontends
+#
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# ISDB-T (terrestrial) frontends
+#
+CONFIG_DVB_S921=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_MB86A20S=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_IT913X_FE=m
+CONFIG_DVB_M88RS2000=m
+
+#
+# Tools to develop new frontends
+#
+CONFIG_DVB_DUMMY_FE=m
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_EXYNOS_VIDEO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+CONFIG_SND_SPI=y
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_USB_CAIAQ=m
+# CONFIG_SND_USB_CAIAQ_INPUT is not set
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=m
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WIIMOTE_EXT=y
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_METRO is not set
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
+CONFIG_USB_SERIAL_ZIO=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_OT200 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+# CONFIG_UIO_NETX is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+CONFIG_USBIP_CORE=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_HOST=m
+# CONFIG_USBIP_DEBUG is not set
+# CONFIG_W35UND is not set
+CONFIG_PRISM2_USB=m
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8187SE is not set
+CONFIG_RTL8192U=m
+CONFIG_RTLLIB=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+# CONFIG_RTL8192E is not set
+CONFIG_R8712U=m
+# CONFIG_RTS_PSTOR is not set
+CONFIG_RTS5139=m
+# CONFIG_RTS5139_DEBUG is not set
+CONFIG_TRANZPORT=m
+# CONFIG_IDE_PHISON is not set
+CONFIG_LINE6_USB=m
+# CONFIG_LINE6_USB_DEBUG is not set
+# CONFIG_LINE6_USB_DUMP_CTRL is not set
+# CONFIG_LINE6_USB_DUMP_MIDI is not set
+# CONFIG_LINE6_USB_DUMP_PCM is not set
+# CONFIG_LINE6_USB_RAW is not set
+# CONFIG_LINE6_USB_IMPULSE_RESPONSE is not set
+CONFIG_USB_SERIAL_QUATECH2=m
+CONFIG_USB_SERIAL_QUATECH_USB2=m
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_DX_SEP is not set
+# CONFIG_IIO is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+CONFIG_USB_ENESTORAGE=m
+CONFIG_BCM_WIMAX=m
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+CONFIG_STAGING_MEDIA=y
+CONFIG_DVB_AS102=m
+CONFIG_DVB_CXD2099=m
+# CONFIG_VIDEO_DT3155 is not set
+CONFIG_EASYCAP=m
+# CONFIG_EASYCAP_DEBUG is not set
+# CONFIG_VIDEO_GO7007 is not set
+# CONFIG_SOLO6X10 is not set
+CONFIG_LIRC_STAGING=y
+# CONFIG_LIRC_BT829 is not set
+CONFIG_LIRC_IGORPLUGUSB=m
+CONFIG_LIRC_IMON=m
+CONFIG_LIRC_SASEM=m
+CONFIG_LIRC_SERIAL=m
+CONFIG_LIRC_SERIAL_TRANSMITTER=y
+# CONFIG_LIRC_SIR is not set
+CONFIG_LIRC_TTUSBIR=m
+# CONFIG_LIRC_ZILOG is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_PHONE is not set
+# CONFIG_USB_WPAN_HCD is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Remoteproc drivers (EXPERIMENTAL)
+#
+
+#
+# Rpmsg drivers (EXPERIMENTAL)
+#
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_XFS_FS=y
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
+# CONFIG_NFSD_FAULT_INJECTION is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_CEPH_FS=m
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_INFO=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=384M@640M memc1=768M console=ttyS0,1000000 root=/dev/mmcblk0p1 rootwait rootfstype=ext4"
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_RUNTIME_DEBUG is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=m
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_CRC8=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3f745459fdb5..690e45970a48 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -96,13 +96,21 @@
  */
 #define KUSEG			0x00000000
 #define KSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define KSEG1			KSEG0
+#else
 #define KSEG1			0xa0000000
+#endif
 #define KSEG2			0xc0000000
 #define KSEG3			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define CKSEG1			CKSEG0
+#else
 #define CKSEG1			0xa0000000
+#endif
 #define CKSEG2			0xc0000000
 #define CKSEG3			0xe0000000
 
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 70e1f176f123..0c28771a1c94 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
 #include <asm/mipsregs.h>
 
 	.macro	fpu_save_single thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp,  fcr31
 	swc1	$f0,  THREAD_FPR0(\thread)
 	swc1	$f1,  THREAD_FPR1(\thread)
@@ -47,9 +49,12 @@
 	swc1	$f30, THREAD_FPR30(\thread)
 	swc1	$f31, THREAD_FPR31(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 
 	.macro	fpu_restore_single thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	lwc1	$f0,  THREAD_FPR0(\thread)
 	lwc1	$f1,  THREAD_FPR1(\thread)
@@ -84,6 +89,7 @@
 	lwc1	$f30, THREAD_FPR30(\thread)
 	lwc1	$f31, THREAD_FPR31(\thread)
 	ctc1	\tmp, fcr31
+	.set	pop
 	.endm
 
 	.macro	cpu_save_nonscratch thread
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index cbaccebf5065..30939b02e3ff 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -84,6 +84,7 @@ extern char bmips_smp_int_vec_end;
 extern int bmips_smp_enabled;
 extern int bmips_cpu_offset;
 extern cpumask_t bmips_booted_mask;
+extern unsigned long bmips_tp1_irqs;
 
 extern void bmips_ebase_setup(void);
 extern asmlinkage void plat_wired_tlb_setup(void);
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 76411df3d971..7c04af6b2570 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -140,6 +140,7 @@
 #define PRID_IMP_BMIPS3300_BUG	0x0000
 #define PRID_IMP_BMIPS43XX	0xa000
 #define PRID_IMP_BMIPS5000	0x5a00
+#define PRID_IMP_BMIPS5200	0x5b00
 
 #define PRID_REV_BMIPS4380_LO	0x0040
 #define PRID_REV_BMIPS4380_HI	0x006f
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 429481f9028d..f184ba088532 100644
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
 
 #include <asm/sgidefs.h>
 
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 3321dd5a8872..f77d8f0df8e5 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -206,6 +206,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 		if (!size || last_addr < phys_addr)
 			return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 		/*
 		 * Map uncached objects in the low 512MB of address
 		 * space using KSEG1.
@@ -214,6 +215,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 		    flags == _CACHE_UNCACHED)
 			return (void __iomem *)
 				(unsigned long)CKSEG1ADDR(phys_addr);
+#endif
 	}
 
 	return __ioremap(offset, size, flags);
diff --git a/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
new file mode 100644
index 000000000000..59903c949024
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+
+#if defined(CONFIG_CPU_BMIPS4380)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		64
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS3300)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		16
+#define cpu_icache_line_size()		16
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+#define cpu_has_dc_aliases		0
+#define cpu_has_ic_fills_f_dc		1
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	1
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		32
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		128
+
+#endif
+
+#if defined(CONFIG_BRCM_HAS_XI)
+#define cpu_has_rixi			1
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/dma-coherence.h b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
new file mode 100644
index 000000000000..b63153bf19c6
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+#define __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+
+struct device;
+
+#if defined(CONFIG_PCI)
+
+extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
+extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
+extern unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr);
+
+#else
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+	size_t size)
+{
+	return virt_to_phys(addr);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+	struct page *page)
+{
+	return page_to_phys(page);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
+{
+	return dma_addr;
+}
+
+#endif
+
+extern void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir);
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+	/*
+	 * we fall back to GFP_DMA when the mask isn't all 1s,
+	 * so we can't guarantee allocations that must be
+	 * within a tighter range than GFP_DMA..
+	 */
+	if (mask < DMA_BIT_MASK(24))
+		return 0;
+
+	return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+	return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+					 dma_addr_t dma_addr)
+{
+	return 0;
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+	return 0;
+}
+
+#endif /* __ASM_MACH_BRCMSTB_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/ioremap.h b/arch/mips/include/asm/mach-brcmstb/ioremap.h
new file mode 100644
index 000000000000..bf9ce3dcbe79
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/ioremap.h
@@ -0,0 +1,27 @@
+/*
+ *	include/asm-mips/mach-brcmstb/ioremap.h
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_BRCMSTB_IOREMAP_H
+#define __ASM_MACH_BRCMSTB_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+	return phys_addr;
+}
+
+extern void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+	unsigned long flags);
+extern int plat_iounmap(const volatile void __iomem *addr);
+
+#endif /* __ASM_MACH_BRCMSTB_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/irq.h b/arch/mips/include/asm/mach-brcmstb/irq.h
new file mode 100644
index 000000000000..8d44f845b86e
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/irq.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_IRQ_H
+#define __ASM_MACH_BRCMSTB_IRQ_H
+
+/*
+ * This file has IRQ definitions that DO NOT depend on the BCHP headers
+ * See also: linux/brcmstb/brcmstb.h
+ */
+
+/* IRQs 1-128 are used for HIF L1 */
+#define BRCM_VIRTIRQ_BASE	(1 + 128)
+
+/* virtual (non-L1) IRQs */
+
+#define BRCM_CPUIRQ_BASE	(BRCM_VIRTIRQ_BASE + 0)
+#define BRCM_OTHERIRQ_BASE	(BRCM_VIRTIRQ_BASE + 8)
+
+/* MIPS interrupts 0-7 */
+#define BRCM_IRQ_CPU0		(BRCM_CPUIRQ_BASE + 0)
+#define BRCM_IRQ_CPU1		(BRCM_CPUIRQ_BASE + 1)
+#define BRCM_IRQ_CPU2		(BRCM_CPUIRQ_BASE + 2)
+#define BRCM_IRQ_CPU3		(BRCM_CPUIRQ_BASE + 3)
+#define BRCM_IRQ_CPU4		(BRCM_CPUIRQ_BASE + 4)
+#define BRCM_IRQ_CPU5		(BRCM_CPUIRQ_BASE + 5)
+#define BRCM_IRQ_CPU6		(BRCM_CPUIRQ_BASE + 6)
+#define BRCM_IRQ_CPU7		(BRCM_CPUIRQ_BASE + 7)
+
+#define BRCM_IRQ_IPI0		BRCM_IRQ_CPU0
+#define BRCM_IRQ_IPI1		BRCM_IRQ_CPU1
+#define BRCM_IRQ_HW0		BRCM_IRQ_CPU2
+#define BRCM_IRQ_HW1		BRCM_IRQ_CPU3
+
+/* performance counter */
+
+#define BRCM_IRQ_PERF		(BRCM_OTHERIRQ_BASE + 0)
+
+#define NR_IRQS			160
+#define MIPS_CPU_IRQ_BASE	BRCM_CPUIRQ_BASE
+
+#endif /* __ASM_MACH_BRCMSTB_IRQ_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
new file mode 100644
index 000000000000..3133784a0af7
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
@@ -0,0 +1,36 @@
+/***************************************************************************
+ *     Copyright (c) 2008, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ ***************************************************************************/
+
+#ifndef __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+#define __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+
+	.macro kernel_entry_setup
+
+	# save arguments for CFE callback
+	sw	a0, cfe_handle
+	sw	a2, cfe_entry
+	sw	a3, cfe_seal
+
+	jal	bmips_enable_xks01
+
+	.endm
+
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/mangle-port.h b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
new file mode 100644
index 000000000000..8440103b3ae8
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+#define __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)	(port)
+#define __swizzle_addr_w(port)	(port)
+#define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/spaces.h b/arch/mips/include/asm/mach-brcmstb/spaces.h
new file mode 100644
index 000000000000..23a1bd765788
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/spaces.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+
+#ifndef _ASM_MACH_BRCMSTB_SPACES_H
+#define _ASM_MACH_BRCMSTB_SPACES_H
+
+#include <linux/const.h>
+
+/***********************************************************************
+ * Kernel virtual address space
+ ***********************************************************************/
+
+#if !defined(CONFIG_BRCM_UPPER_MEMORY)
+
+/*
+ * 256MB standard MIPS32 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: lower 256MB, cached mapping
+ * 9000_0000 - 9fff_ffff: EBI/registers, cached mapping (unused)
+ * a000_0000 - afff_ffff: lower 256MB, uncached mapping
+ * b000_0000 - bfff_ffff: EBI/registers, uncached mapping
+ * c000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ */
+
+#define KSEG0_SIZE		_AC(0x20000000, UL)
+#define KSEG1_SIZE		_AC(0x20000000, UL)
+#define MAP_BASE		_AC(0xc0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(0, UL)
+
+#elif defined(CONFIG_BRCM_UPPER_768MB)
+
+/*
+ * 1024MB Broadcom 256+768 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: 256MB RAM @ 0000_0000, cached
+ * 9000_0000 - 9fff_ffff: 256MB EBI/Registers @ 1000_0000, uncached
+ * a000_0000 - cfff_ffff: 768MB RAM @ 2000_0000, cached
+ * d000_0000 - dfff_ffff: TBD
+ * e000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ * ff40_0000 - ff7f_ffff: CONSISTENT region
+ *
+ * PA 5000_0000 and above are accessed through HIGHMEM (BMIPS5000 only).
+ */
+
+#define TLB_UPPERMEM_VA		_AC(0xc0000000, UL)
+#define TLB_UPPERMEM_PA		_AC(0x40000000, UL)
+#define KSEG0_SIZE		_AC(0x40000000, UL)
+#define KSEG1_SIZE		_AC(0x00000000, UL)
+#define MAP_BASE		_AC(0xe0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+/* BASE and END must be 4MB-aligned (PGDIR_SIZE) */
+#define CONSISTENT_BASE		_AC(0xff400000, UL)
+#define CONSISTENT_END		_AC(0xff800000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(768, UL)
+
+#endif /* CONFIG_BRCM_UPPER_MEMORY */
+
+/***********************************************************************
+ * Physical / PCI address space
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_2GB_MEMC0
+
+/*
+ * Physical address map for 2GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 8fff_ffff: MEMC0 (1792MB)
+ * 9000_0000 - cfff_ffff: MEMC1 (1024MB)
+ * d000_0000 - efff_ffff: PCIe MEM BARs (512MB)
+ *
+ * PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 7fff_ffff: MEMC0 (1792MB @ 2000_0000)
+ * 8000_0000 - bfff_ffff: MEMC1 (1024MB @ 9000_0000)
+ */
+
+#define PCI_MEM_START		_AC(0xdeadbeef, UL)
+#define PCI_MEM_SIZE		_AC(0xdeadbeef, UL)
+
+#define PCI_IO_START		_AC(0xffff0000, UL)
+#define PCI_IO_SIZE		_AC(0x00001000, UL)
+
+#define PCIE_MEM_START		_AC(0xd0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x90000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x10000000, UL)
+
+#else /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+/*
+ * Physical address map for <= 1GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 4fff_ffff: MEMC0 (768MB)
+ * 6000_0000 - 7fff_ffff: MEMC1 (512MB)
+ * a000_0000 - bfff_ffff: PCIe MEM BARs (512MB)
+ * d000_0000 - efff_ffff: PCI2.3 MEM BARs (512MB)
+ * f000_0000 - f05f_ffff: PCI2.3 IO BARs (6MB)
+ * f000_0000 - f060_000b: PCI2.3 Configuration access (12B)
+ * f100_0000 - f100_001f: PCIe Configuration access - 7420 only (32B)
+ *
+ * PCI2.3/PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 3fff_ffff: MEMC0 (768MB  @ 2000_0000)
+ * 4000_0000 - 7fff_ffff: MEMC1 (1024MB @ 6000_0000) (not currently implemented)
+ */
+
+#define PCI_MEM_START		_AC(0xd0000000, UL)
+#define PCI_MEM_SIZE		_AC(0x20000000, UL)
+
+/* this is really 6MB long, but 32k ought to be enough for anyone */
+#define PCI_IO_START		_AC(0xf0000000, UL)
+#define PCI_IO_SIZE		_AC(0x00008000, UL)
+#define PCI_IO_ACTUAL_SIZE	_AC(0x00600000, UL)
+
+#define PCI_IO_REG_START	_AC(0xf0600000, UL)
+#define PCI_IO_REG_SIZE		_AC(0x0000000c, UL)
+
+#define PCIE_MEM_START		_AC(0xa0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x60000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x20000000, UL)
+
+#endif /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+#define UPPERMEM_START		_AC(0x20000000, UL)
+#define HIGHMEM_START		(UPPERMEM_START + (BRCM_MAX_UPPER_MB << 20))
+
+#define BRCM_PCI_HOLE_START	_AC(0x10000000, UL)
+#define BRCM_PCI_HOLE_SIZE	_AC(0x10000000, UL)
+
+#define BRCM_MAX_LOWER_MB	_AC(256, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_BRCMSTB_SPACES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/war.h b/arch/mips/include/asm/mach-brcmstb/war.h
new file mode 100644
index 000000000000..ebb8f2b632a4
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_BRCMSTB_WAR_H
+#define __ASM_MIPS_MACH_BRCMSTB_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_BRCMSTB_WAR_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4294bc..d68af87031a3 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1251,7 +1251,7 @@ do {									\
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)					\
+#define _read_32bit_cp1_register(source, gas_hardfloat)					\
 ({									\
 	int __res;							\
 									\
@@ -1260,13 +1260,22 @@ do {									\
 	"	.set	reorder					\n"	\
 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
 	"	# like Octeon.					\n"	\
-	"	.set	mips1					\n"	\
+	"	.set	mips1					\n"     \
+	STR(gas_hardfloat)"					\n"	\
 	"	cfc1	%0,"STR(source)"			\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res));						\
 	__res;								\
 })
 
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#endif
+
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 5e08bcc74897..a7a0fce7512b 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -230,8 +230,16 @@ extern int __virt_addr_valid(const volatile void *kaddr);
 #define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
 				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
+#if defined(CONFIG_BRCM_UPPER_768MB)
+
+/* uncached kseg1 does not exist in this configuration */
+
+#define CAC_ADDR(addr)		({ BUG(); NULL; })
+
+#else
 #define UNCAC_ADDR(addr)	((addr) - PAGE_OFFSET + UNCAC_BASE)
 #define CAC_ADDR(addr)		((addr) - UNCAC_BASE + PAGE_OFFSET)
+#endif
 
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 26c6175e1379..5cb4227dfcb1 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -46,7 +46,7 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
 
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP_UP)		+= smp-up.o
-obj-$(CONFIG_CPU_BMIPS)		+= smp-bmips.o bmips_vec.o
+obj-$(CONFIG_CPU_BMIPS)		+= smp-bmips.o bmips_vec.o bmips_5xxx_init.o
 
 obj-$(CONFIG_MIPS_MT)		+= mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o
diff --git a/arch/mips/kernel/bmips_5xxx_init.S b/arch/mips/kernel/bmips_5xxx_init.S
new file mode 100644
index 000000000000..788ebf9a365d
--- /dev/null
+++ b/arch/mips/kernel/bmips_5xxx_init.S
@@ -0,0 +1,753 @@
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011-2012 by Broadcom Corporation
+ *
+ * Init for bmips 5000.
+ * Used to init second core in dual core 5000's.
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/addrspace.h>
+#include <asm/hazards.h>
+#include <asm/bmips.h>
+
+#ifdef CONFIG_CPU_BMIPS5000
+
+
+#define cacheop(kva, size, linesize, op) 	\
+	.set noreorder			;	\
+	addu		t1, kva, size   ;	\
+        subu		t2, linesize, 1 ;	\
+        not		t2		;	\
+        and		t0, kva, t2     ;	\
+        addiu		t1, t1, -1      ;    	\
+        and		t1, t2          ;	\
+9:	cache		op, 0(t0)       ;	\
+        bne		t0, t1, 9b	;	\
+        addu		t0, linesize    ;	\
+        .set reorder			;
+
+
+
+#define	IS_SHIFT	22
+#define	IL_SHIFT	19
+#define	IA_SHIFT	16
+#define	DS_SHIFT	13
+#define	DL_SHIFT	10
+#define	DA_SHIFT	 7
+#define	IS_MASK		 7
+#define	IL_MASK		 7
+#define	IA_MASK		 7
+#define	DS_MASK		 7
+#define	DL_MASK		 7
+#define	DA_MASK		 7
+#define	ICE_MASK	0x80000000
+#define	DCE_MASK	0x40000000
+
+#define CP0_BRCM_CONFIG0	$22, 0
+#define CP0_BRCM_MODE		$22, 1
+#define	CP0_CONFIG_K0_MASK	7
+
+#define CP0_ICACHE_TAG_LO       $28
+#define CP0_ICACHE_DATA_LO      $28, 1
+#define CP0_DCACHE_TAG_LO       $28, 2
+#define CP0_D_SEC_CACHE_DATA_LO	$28, 3
+#define CP0_ICACHE_TAG_HI       $29
+#define CP0_ICACHE_DATA_HI      $29, 1
+#define CP0_DCACHE_TAG_HI       $29, 2
+
+#define CP0_BRCM_MODE_Luc_MASK		(1 << 11)
+#define	CP0_BRCM_CONFIG0_CWF_MASK	(1 << 20)
+#define	CP0_BRCM_CONFIG0_TSE_MASK	(1 << 19)
+#define CP0_BRCM_MODE_SET_MASK		(1 << 7)
+#define CP0_BRCM_MODE_ClkRATIO_MASK	(7 << 4)
+#define CP0_BRCM_MODE_BrPRED_MASK 	(3 << 24)
+#define CP0_BRCM_MODE_BrPRED_SHIFT	24
+#define CP0_BRCM_MODE_BrHIST_MASK 	(0x1f << 20)
+#define CP0_BRCM_MODE_BrHIST_SHIFT	20
+
+/* ZSC L2 Cache Register Access Register Definitions */
+#define BRCM_ZSC_ALL_REGS_SELECT                0x7 << 24
+
+#define BRCM_ZSC_CONFIG_REG			0 << 3
+#define BRCM_ZSC_REQ_BUFFER_REG			2 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0		4 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG1		6 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2		8 << 3
+
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0		0xa << 3
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1		0xc << 3
+
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0		0xe << 3
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG1		0x10 << 3
+
+#define BRCM_ZSC_CONFIG_LMB1En			1 << (15)
+#define BRCM_ZSC_CONFIG_LMB0En			1 << (14)
+
+/* branch predition values */
+
+#define BRCM_BrPRED_ALL_TAKEN		(0x0)
+#define BRCM_BrPRED_ALL_NOT_TAKEN	(0x1)
+#define BRCM_BrPRED_BHT_ENABLE		(0x2)
+#define BRCM_BrPRED_PREDICT_BACKWARD	(0x3)
+
+
+
+.align 2
+/*
+ * Function: 	size_i_cache
+ * Arguments: 	None
+ * Returns:	v0 = i cache size, v1 = I cache line size
+ * Description: compute the I-cache size and I-cache line size
+ * Trashes:	v0, v1, a0, t0
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(size_i_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, IS_SHIFT
+	and     a0, a0, IS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IL_SHIFT
+	and	a0, a0, IL_MASK
+
+	beqz	a0, no_i_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/*
+	 * Determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IA_SHIFT
+	and	a0, a0, IA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+	b	1f
+	nop
+
+no_i_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr       ra
+	nop
+	.set    reorder
+
+END(size_i_cache)
+
+/*
+ * Function: 	size_d_cache
+ * Arguments: 	None
+ * Returns:	v0 = d cache size, v1 = d cache line size
+ * Description: compute the D-cache size and D-cache line size.
+ * Trashes:	v0, v1, a0, t0
+ *
+ */
+
+LEAF(size_d_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, DS_SHIFT
+	and     a0, a0, DS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+	move	a0, t0
+
+	srl	a0, a0, DL_SHIFT
+	and	a0, a0, DL_MASK
+
+	beqz	a0, no_d_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/* determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, DA_SHIFT
+	and	a0, a0, DA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+
+	b	1f
+	nop
+
+no_d_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr	ra
+	nop
+	.set    reorder
+
+END(size_d_cache)
+
+
+/*
+ * Function: enable_ID
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, initialize I and D-caches, also set
+ *                 hardware delay for d-cache (TP0).
+ * Trashes:	t0
+ *
+ */
+	.global	enable_ID
+	.ent	enable_ID
+	.set    noreorder
+enable_ID:
+	mfc0    t0, CP0_BRCM_CONFIG0
+	or	t0, t0, (ICE_MASK | DCE_MASK)
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+
+	.end	enable_ID
+	.set    reorder
+
+
+/*
+ * Function: l1_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	a0, v0, v1, t0, t1, t2, t8
+ *
+ */
+	.globl	l1_init
+	.ent	l1_init
+	.set    noreorder
+l1_init:
+
+	/* save return address */
+	move    t8, ra
+
+
+	/* initialize I and D cache Data and Tag registers.  */
+	mtc0    zero, CP0_ICACHE_TAG_LO
+	mtc0    zero, CP0_ICACHE_TAG_HI
+	mtc0	zero, CP0_ICACHE_DATA_LO
+	mtc0	zero, CP0_ICACHE_DATA_HI
+	mtc0	zero, CP0_DCACHE_TAG_LO
+	mtc0	zero, CP0_DCACHE_TAG_HI
+
+	/* Enable Caches before Clearing. If the caches are disabled
+	 * then the cache operations to clear the cache will be ignored
+	 */
+
+	jal	enable_ID
+	nop
+
+	jal	size_i_cache	/* v0 = i-cache size, v1 = i-cache line size */
+	nop
+
+	/* run uncached in kseg 1 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	jr	k0
+	nop
+1:
+
+	/*
+	 * set K0 cache mode
+	 */
+
+	mfc0    t0, CP0_CONFIG
+	and     t0, t0, ~CP0_CONFIG_K0_MASK
+	or      t0, t0, 3	/* Write Back mode */
+	mtc0    t0, CP0_CONFIG
+
+	/*
+	 * Initialize  instruction cache.
+	 */
+
+	li	a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_I)
+
+	/*
+	 * Now we can run from I-$, kseg 0
+	 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	xor	k0, k1, k0
+	jr	k0
+	nop
+1:
+	/*
+	 * Initialize  data cache.
+	 */
+
+	jal	size_d_cache	/* v0 = d-cache size, v1 = d-cache line size */
+	nop
+
+
+	li      a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_D)
+
+	jr	t8
+	nop
+
+	.end 	l1_init
+	.set    reorder
+
+
+/*
+ * Function: 	set_other_config
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize other remainder configuration to defaults.
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_other_config)
+	.set noreorder
+
+        /* enable Bus error for I-fetch */
+        mfc0	t0, CP0_CACHEERR, 0
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 0
+
+        /* enable Bus error for Load */
+        mfc0	t0, CP0_CACHEERR, 1
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 1
+
+	/* enable Bus Error for Store */
+        mfc0	t0, CP0_CACHEERR, 2
+	li	t1, 0x4
+	or	t0, t1
+        mtc0	t0, CP0_CACHEERR, 2
+
+	jr	ra
+	nop
+	.set reorder
+END(set_other_config)
+
+/*
+ * Function: 	set_branch_pred
+ * Arguments:	none
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(set_branch_pred)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
+	and	t0, t0, t1
+
+	/* enable Branch prediction */
+	li	t1, BRCM_BrPRED_BHT_ENABLE
+	sll	t1, CP0_BRCM_MODE_BrPRED_SHIFT
+	or	t0, t0, t1
+
+	/* set history count to 8 */
+	li	t1, 8
+	sll	t1, CP0_BRCM_MODE_BrHIST_SHIFT
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_branch_pred)
+
+
+/*
+ * Function: 	set_luc
+ * Arguments:	set link uncached.
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_luc)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_Luc_MASK)
+	and	t0, t0, t1
+
+	/* set Luc */
+        ori	t0, t0, CP0_BRCM_MODE_Luc_MASK
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_luc)
+
+/*
+ * Function: 	set_cwf_tse
+ * Arguments:	set CWF and TSE bits
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_cwf_tse)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_CONFIG0
+	li	t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+	.set    reorder
+END(set_cwf_tse)
+
+/*
+ * Function: 	set_clock_ratio
+ * Arguments:   set clock ratio specified by a0
+ * Returns:	None
+ * Description:
+ * Trashes:	v0, v1, a0, a1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_clock_ratio)
+	.set noreorder
+
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
+	and	t0, t0, t1
+	li	t1, CP0_BRCM_MODE_SET_MASK
+	or	t0, t0, t1
+	or	t0, t0, a0
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_clock_ratio)
+/*
+ * Function: set_zephyr
+ * Arguments:   None
+ * Returns:     None
+ * Description: Set any zephyr bits
+ * Trashes:     t0 & t1
+ *
+ */
+LEAF(set_zephyr)
+        .set    noreorder
+
+        /* enable read/write of CP0 #22 sel. 8 */
+        li      t0, 0x5a455048
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+	.word	0x4008b008      /* mfc0    t0, $22, 8 */
+        li      t1, 0x09008000	/* turn off pref, jtb */
+        or      t0, t0, t1
+	.word	0x4088b008      /* mtc0    t0, $22, 8 */
+        sync
+
+	/* disable read/write of CP0 #22 sel 8 */
+        li      t0, 0x0
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+
+        jr      ra
+        nop
+	.set reorder
+
+END(set_zephyr)
+
+
+/*
+ * Function:    set_llmb
+ * Arguments:   a0=0 disable llmb, a0=1 enables llmb
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ *      pseudo code:
+ *
+ */
+LEAF(set_llmb)
+	.set noreorder
+
+	li	t2, 0x90000000 | BRCM_ZSC_ALL_REGS_SELECT | BRCM_ZSC_CONFIG_REG
+	sync
+	cache	0x7, 0x0(t2)
+	sync
+	mfc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	li	t1, ~(BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	and	t0, t0, t1
+
+	beqz	a0, svlmb
+	nop
+
+enable_lmb:
+	li	t1, (BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	or	t0, t0, t1
+
+svlmb:
+	mtc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	sync
+	cache	0xb, 0x0(t2)
+	sync
+
+	jr      ra
+	nop
+	.set reorder
+
+END(set_llmb)
+/*
+ * Function: 	core_init
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize core related configuration
+ * Trashes:	v0,v1,a0,a1,t8
+ *
+ *	pseudo code:
+ *
+ */
+	.globl	core_init
+	.ent    core_init
+	.set	noreorder
+core_init:
+	move	t8, ra
+
+	/* set Zephyr bits. */
+	bal	set_zephyr
+	nop
+
+#if ENABLE_FPU==1
+	/* initialize the Floating point unit (both TPs) */
+	bal	init_fpu
+	nop
+#endif
+
+	/* set low latency memory bus */
+	li      a0, 1
+	bal     set_llmb
+	nop
+
+	/* set branch prediction (TP0 only) */
+	bal	set_branch_pred
+	nop
+
+	/* set link uncached */
+	bal	set_luc
+	nop
+
+	/* set CWF and TSE */
+	bal     set_cwf_tse
+	nop
+
+	/*
+	 *set clock ratio by setting 1 to 'set'
+	 * and 0 to ClkRatio, (TP0 only)
+	 */
+	li	a0, 0
+	bal	set_clock_ratio
+	nop
+
+	/* set other configuration to defaults */
+	bal	set_other_config
+	nop
+
+	move	ra, t8
+	jr	ra
+	nop
+
+	.set reorder
+	.end	core_init
+
+/*
+ * Function: 	clear_jump_target_buffer
+ * Arguments:   None
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ */
+#define RESET_CALL_RETURN_STACK_THIS_THREAD             (0x06<<16)
+#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD    	(0x04<<16)
+#define JTB_CS_CNTL_MASK				(0xFF<<16)
+
+	.globl  clear_jump_target_buffer
+	.ent    clear_jump_target_buffer
+	.set    noreorder
+clear_jump_target_buffer:
+
+        mfc0    t0, $22, 2
+        nop
+        nop
+
+        li	t1, ~JTB_CS_CNTL_MASK
+        and	t0, t0, t1
+        li	t2, RESET_CALL_RETURN_STACK_THIS_THREAD
+        or	t0, t0, t2
+        mtc0    t0, $22, 2
+        nop
+        nop
+
+        and	t0, t0, t1
+        li	t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
+        or	t0, t0, t2
+        mtc0	t0, $22, 2
+        nop
+        nop
+        jr      ra
+        nop
+
+	.end    clear_jump_target_buffer
+	.set    reorder
+/*
+ * Function: 	bmips_cache_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	v0, v1, t0, t1, t2, t5, t7, t8
+ *
+ */
+	.globl	bmips_5xxx_init
+	.ent	bmips_5xxx_init
+	.set    noreorder
+bmips_5xxx_init:
+
+	/* save return address  and A0 */
+	move    t7, ra
+	move	t5, a0
+
+	jal	l1_init
+	nop
+
+	jal	core_init
+	nop
+
+	jal	clear_jump_target_buffer
+	nop
+
+        mtc0    zero, CP0_CAUSE
+
+	move 	a0, t5
+	jr	t7
+	nop
+
+	.end 	bmips_5xxx_init
+	.set    reorder
+
+
+#endif
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index a5bf73d22fcc..f2ad77905740 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -88,12 +88,13 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 	li	k1, (1 << 19)
 	mfc0	k0, CP0_STATUS
 	and	k0, k1
-	beqz	k0, bmips_smp_entry
+	beqz	k0, soft_reset
 
 #if defined(CONFIG_CPU_BMIPS5000)
 	mfc0	k0, CP0_PRID
 	li	k1, PRID_IMP_BMIPS5000
-	andi	k0, 0xff00
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
+	andi	k0, PRID_IMP_BMIPS5000
 	bne	k0, k1, 1f
 
 	/* if we're not on core 0, this must be the SMP boot signal */
@@ -125,13 +126,48 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
 	.set	mips3
 	eret
 
+#ifdef CONFIG_SMP
+soft_reset:
+
+#if defined(CONFIG_CPU_BMIPS5000)
+	mfc0	k0, CP0_PRID
+	andi	k0, 0xff00
+	li	k1, PRID_IMP_BMIPS5200
+	bne	k0, k1, bmips_smp_entry
+
+        /* if running on TP 1, jump  to  bmips_smp_entry */
+        mfc0    k0, $22
+        li      k1, (1 << 24)
+        and     k1, k0
+        bnez    k1, bmips_smp_entry
+        nop
+
+        /*
+         * running on TP0, can not be core 0 (the boot core).
+         * Check for soft reset.  Indicates a warm boot
+         */
+        mfc0    k0, $12
+        li      k1, (1 << 20)
+        and     k0, k1
+        beqz    k0, bmips_smp_entry
+
+        /*
+         * Warm boot.
+         * Cache init is only done on TP0
+         */
+        la      k0, bmips_5xxx_init
+        jalr    k0
+        nop
+
+        b       bmips_smp_entry
+        nop
+#endif
+
 /***********************************************************************
  * CPU1 reset vector (used for the initial boot only)
  * This is still part of bmips_reset_nmi_vec().
  ***********************************************************************/
 
-#ifdef CONFIG_SMP
-
 bmips_smp_entry:
 
 	/* set up CP0 STATUS; enable FPU */
@@ -166,10 +202,12 @@ bmips_smp_entry:
 2:
 #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
 #if defined(CONFIG_CPU_BMIPS5000)
-	/* set exception vector base */
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
 	li	k1, PRID_IMP_BMIPS5000
+	andi	k0, PRID_IMP_BMIPS5000
 	bne	k0, k1, 3f
 
+	/* set exception vector base */
 	la	k0, ebase
 	lw	k0, 0(k0)
 	mtc0	k0, $15, 1
@@ -208,7 +246,6 @@ bmips_reset_nmi_vec_end:
 END(bmips_reset_nmi_vec)
 
 	.set	pop
-	.previous
 
 /***********************************************************************
  * CPU1 warm restart vector (used for second and subsequent boots).
@@ -264,6 +301,8 @@ LEAF(bmips_enable_xks01)
 #endif /* CONFIG_CPU_BMIPS4380 */
 #if defined(CONFIG_CPU_BMIPS5000)
 	li	t1, PRID_IMP_BMIPS5000
+	/* mask with PRID_IMP_BMIPS5000 to cover both variants */
+	andi	t2, PRID_IMP_BMIPS5000
 	bne	t2, t1, 2f
 
 	mfc0	t0, $22, 5
@@ -281,5 +320,3 @@ LEAF(bmips_enable_xks01)
 	jr	ra
 
 END(bmips_enable_xks01)
-
-	.previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d78bf445a9c..8b061b1b0bc5 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -366,7 +366,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 	case cop1_op:
 		preempt_disable();
 		if (is_fpu_owner())
-			asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+			fcr31 = read_32bit_cp1_register(CP1_STATUS);
 		else
 			fcr31 = current->thread.fpu.fcr31;
 		preempt_enable();
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 50d3f5a8d6bb..01de56622e9a 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -17,6 +17,10 @@
 #include <asm/cevt-r4k.h>
 #include <asm/gic.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 /*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
  * of these routines with SMTC-specific variants.
@@ -30,7 +34,11 @@ static int mips_next_event(unsigned long delta,
 	int res;
 
 	cnt = read_c0_count();
+#ifdef CONFIG_BRCMSTB
+	cnt += brcm_fixup_ticks(delta);
+#else
 	cnt += delta;
+#endif
 	write_c0_compare(cnt);
 	res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
 	return res;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 530f832de02c..329180cd1d12 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -945,6 +945,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 		break;
 	}
 	case PRID_IMP_BMIPS5000:
+	case PRID_IMP_BMIPS5200:
 		c->cputype = CPU_BMIPS5000;
 		__cpu_name[cpu] = "Broadcom BMIPS5000";
 		set_elf_platform(cpu, "bmips5000");
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index d84f6a509502..00b507f8690a 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -408,6 +408,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	.set	mips1
+	SET_HARDFLOAT
 	cfc1	a1, fcr31
 	li	a2, ~(0x3f << 12)
 	and	a2, a1
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 00d20974b3e7..034d2d482f6b 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -15,6 +15,10 @@
 #include <asm/processor.h>
 #include <asm/prom.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 unsigned int vced_count, vcei_count;
 
 static int show_cpuinfo(struct seq_file *m, void *v)
@@ -49,6 +53,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
 		      cpu_data[n].udelay_val / (500000/HZ),
 		      (cpu_data[n].udelay_val / (5000/HZ)) % 100);
+#ifdef CONFIG_BRCMSTB
+	/* for Oprofile opreport */
+	seq_printf(m, "cpu MHz\t\t\t: %lu.%03lu\n", brcm_adj_cpu_khz / 1000,
+		brcm_adj_cpu_khz % 1000);
+#endif
 	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
 	seq_printf(m, "microsecond timers\t: %s\n",
 		      cpu_has_counter ? "yes" : "no");
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 73b0ddf910d4..e19bd238d5cb 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -33,6 +33,8 @@
 	.set	mips3
 
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
@@ -84,6 +86,7 @@ LEAF(_save_fp_context)
 	EX	sw t1, SC_FPC_CSR(a0)
 	jr	ra
 	 li	v0, 0					# success
+	.set	pop
 	END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
@@ -146,8 +149,9 @@ LEAF(_save_fp_context32)
  *  - cp1 status/control register
  */
 LEAF(_restore_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	EX	lw t1, SC_FPC_CSR(a0)
-
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
 #ifdef CONFIG_CPU_MIPS32_R2
@@ -155,7 +159,7 @@ LEAF(_restore_fp_context)
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip loading odd if FR=0
-	 nop
+	nop
 #endif
 	EX	ldc1 $f1, SC_FPREGS+8(a0)
 	EX	ldc1 $f3, SC_FPREGS+24(a0)
@@ -194,6 +198,7 @@ LEAF(_restore_fp_context)
 	ctc1	t1, fcr31
 	jr	ra
 	 li	v0, 0					# success
+	.set	pop
 	END(_restore_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index cc78dd9a17c7..244f89a03d57 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -64,8 +64,11 @@
 	and	t0, t0, t1
 	LONG_S	t0, ST_OFF(t3)
 
+	.set push
+	SET_HARDFLOAT
 	fpu_save_double a0 t0 t1		# c0_status passed in t0
 						# clobbers t1
+	.set pop
 1:
 
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
@@ -126,7 +129,10 @@ LEAF(_save_fp)
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	mfc0	t0, CP0_STATUS
 #endif
+	.set push
+	SET_HARDFLOAT
 	fpu_save_double a0 t0 t1		# clobbers t1
+	.set pop
 	jr	ra
 	END(_save_fp)
 
@@ -137,7 +143,10 @@ LEAF(_restore_fp)
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	mfc0	t0, CP0_STATUS
 #endif
+	.set push
+	SET_HARDFLOAT
 	fpu_restore_double a0 t0 t1		# clobbers t1
+	.set pop
 	jr	ra
 	END(_restore_fp)
 
@@ -151,6 +160,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 #ifdef CONFIG_MIPS_MT_SMTC
 	/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
@@ -290,3 +302,5 @@ LEAF(_init_fpu)
 #endif
 	jr	ra
 	END(_init_fpu)
+
+	.set pop
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 07fc5244aed4..9060ac02938f 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -20,7 +20,13 @@
  * functions.
  */
 void (*_machine_restart)(char *command);
+
+EXPORT_SYMBOL(_machine_restart);
+
 void (*_machine_halt)(void);
+
+EXPORT_SYMBOL(_machine_halt);
+
 void (*pm_power_off)(void);
 
 EXPORT_SYMBOL(pm_power_off);
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index a842154d57dc..ffc70559c9ea 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -35,6 +35,10 @@
 #include <asm/smp-ops.h>
 #include <asm/prom.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
 
 EXPORT_SYMBOL(cpu_data);
@@ -447,7 +451,12 @@ static void __init bootmem_init(void)
 		size = end - start;
 
 		/* Register lowmem ranges */
+#ifdef CONFIG_BRCMSTB
+		/* carve out space for bmem */
+		brcm_free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
+#else
 		free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
+#endif
 		memory_present(0, start, end);
 	}
 
@@ -634,11 +643,18 @@ static void __init arch_mem_init(char **cmdline_p)
 #ifdef CONFIG_CMDLINE_OVERRIDE
 	strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
 #else
+#ifdef CONFIG_CMDLINE_EXTEND
 	if (builtin_cmdline[0]) {
 		strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 		strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
 	}
 	strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+#else
+	if (arcs_cmdline[0])
+		strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
+	else
+		strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+#endif
 #endif
 #else
 	strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index ea4c2dc31692..0866c8ebebe8 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -35,6 +35,7 @@
 #include <asm/bmips.h>
 #include <asm/traps.h>
 #include <asm/barrier.h>
+#include <asm/cpu-features.h>
 
 static int __maybe_unused max_cpus = 1;
 
@@ -42,6 +43,12 @@ static int __maybe_unused max_cpus = 1;
 int bmips_smp_enabled = 1;
 int bmips_cpu_offset;
 cpumask_t bmips_booted_mask;
+unsigned long bmips_tp1_irqs = IE_IRQ1;
+
+#define RESET_FROM_KSEG0		0x80080800
+#define RESET_FROM_KSEG1		0xa0080800
+
+static void bmips_set_reset_vec(int cpu, u32 val);
 
 #ifdef CONFIG_SMP
 
@@ -194,6 +201,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 	pr_info("SMP: Booting CPU%d...\n", cpu);
 
 	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
+		/* kseg1 might not exist if this CPU enabled XKS01 */
+		bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
+
 		switch (current_cpu_type()) {
 		case CPU_BMIPS4350:
 		case CPU_BMIPS4380:
@@ -203,8 +213,9 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 			bmips5000_send_ipi_single(cpu, 0);
 			break;
 		}
-	}
-	else {
+	} else {
+		bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
+
 		switch (current_cpu_type()) {
 		case CPU_BMIPS4350:
 		case CPU_BMIPS4380:
@@ -213,17 +224,7 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
 				set_c0_brcm_cmt_ctrl(0x01);
 			break;
 		case CPU_BMIPS5000:
-			if (cpu & 0x01)
-				write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
-			else {
-				/*
-				 * core N thread 0 was already booted; just
-				 * pulse the NMI line
-				 */
-				bmips_write_zscm_reg(0x210, 0xc0000000);
-				udelay(10);
-				bmips_write_zscm_reg(0x210, 0x00);
-			}
+			write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 			break;
 		}
 		cpumask_set_cpu(cpu, &bmips_booted_mask);
@@ -235,32 +236,14 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
  */
 static void bmips_init_secondary(void)
 {
-	/* move NMI vector to kseg0, in case XKS01 is enabled */
-
-	void __iomem *cbr;
-	unsigned long old_vec;
-	unsigned long relo_vector;
-	int boot_cpu;
-
 	switch (current_cpu_type()) {
 	case CPU_BMIPS4350:
 	case CPU_BMIPS4380:
-		cbr = BMIPS_GET_CBR();
-
-		boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
-		relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
-				  BMIPS_RELO_VECTOR_CONTROL_1;
-
-		old_vec = __raw_readl(cbr + relo_vector);
-		__raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
-
 		clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 		break;
 	case CPU_BMIPS5000:
-		write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
-			(smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
-
 		write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
+		current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
 		break;
 	}
 }
@@ -276,7 +259,7 @@ static void bmips_smp_finish(void)
 	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 
 	irq_enable_hazard();
-	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+	set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
 	irq_enable_hazard();
 }
 
@@ -388,6 +371,8 @@ static int bmips_cpu_disable(void)
 
 	set_cpu_online(cpu, false);
 	cpu_clear(cpu, cpu_callin_map);
+	irq_cpu_offline();
+	clear_c0_status(IE_IRQ5);
 
 	local_flush_tlb_all();
 	local_flush_icache_range(0, ~0);
@@ -412,7 +397,8 @@ void __ref play_dead(void)
 	 * IRQ handlers; this clears ST0_IE and returns immediately.
 	 */
 	clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
-	change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
+	change_c0_status(
+		IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 		IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 	irq_disable_hazard();
 
@@ -469,7 +455,7 @@ struct plat_smp_ops bmips5000_smp_ops = {
 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 {
 	memcpy((void *)dst, start, end - start);
-	dma_cache_wback((unsigned long)start, end - start);
+	dma_cache_wback(dst, end - start);
 	local_flush_icache_range(dst, dst + (end - start));
 	instruction_hazard();
 }
@@ -482,10 +468,61 @@ static inline void bmips_nmi_handler_setup(void)
 		&bmips_smp_int_vec_end);
 }
 
+struct reset_vec_info {
+	int cpu;
+	u32 val;
+};
+
+static void bmips_set_reset_vec_remote(void *vinfo)
+{
+	struct reset_vec_info *info = vinfo;
+	int shift = info->cpu & 0x01 ? 16 : 0;
+	u32 mask = ~(0xffff << shift), val = info->val >> 16;
+
+	preempt_disable();
+	if (smp_processor_id() > 0) {
+		smp_call_function_single(0, &bmips_set_reset_vec_remote,
+					 info, 1);
+	} else {
+		if (info->cpu & 0x02) {
+			/* BMIPS5200 "should" use mask/shift, but it's buggy */
+			bmips_write_zscm_reg(0xa0, (val << 16) | val);
+			bmips_read_zscm_reg(0xa0);
+		} else {
+			write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
+					      (val << shift));
+		}
+	}
+	preempt_enable();
+}
+
+static void bmips_set_reset_vec(int cpu, u32 val)
+{
+	struct reset_vec_info info;
+
+	if (current_cpu_type() == CPU_BMIPS5000) {
+		/* this needs to run from CPU0 (which is always online) */
+		info.cpu = cpu;
+		info.val = val;
+		bmips_set_reset_vec_remote(&info);
+	} else {
+		void __iomem *cbr = BMIPS_GET_CBR();
+
+		if (cpu == 0)
+			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		else {
+			if (current_cpu_type() != CPU_BMIPS4380)
+				return;
+			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		}
+	}
+	__sync();
+	back_to_back_c0_hazard();
+}
+
 void bmips_ebase_setup(void)
 {
 	unsigned long new_ebase = ebase;
-	void __iomem __maybe_unused *cbr;
 
 	BUG_ON(ebase != CKSEG0);
 
@@ -505,15 +542,14 @@ void bmips_ebase_setup(void)
 			&bmips_smp_int_vec, 0x80);
 		__sync();
 		return;
+	case CPU_BMIPS3300:
 	case CPU_BMIPS4380:
 		/*
 		 * 0x8000_0000: reset/NMI (initially in kseg1)
 		 * 0x8000_0400: normal vectors
 		 */
 		new_ebase = 0x80000400;
-		cbr = BMIPS_GET_CBR();
-		__raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
-		__raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 		break;
 	case CPU_BMIPS5000:
 		/*
@@ -521,10 +557,8 @@ void bmips_ebase_setup(void)
 		 * 0x8000_1000: normal vectors
 		 */
 		new_ebase = 0x80001000;
-		write_c0_brcm_bootvec(0xa0088008);
+		bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 		write_c0_ebase(new_ebase);
-		if (max_cpus > 2)
-			bmips_write_zscm_reg(0xa0, 0xa008a008);
 		break;
 	default:
 		return;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 887535c4c93d..bed5a023b254 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -59,6 +59,10 @@
 #include <asm/stacktrace.h>
 #include <asm/uasm.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 extern void check_wait(void);
 extern asmlinkage void rollback_handle_int(void);
 extern asmlinkage void handle_int(void);
@@ -616,6 +620,10 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
 {
 	struct thread_info *ti = task_thread_info(current);
 
+#ifdef CONFIG_BRCMSTB
+	if (brcm_simulate_opcode(regs, rd, rt) == 0)
+		return 0;
+#endif
 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 			1, regs, 0);
 	switch (rd) {
@@ -1850,7 +1858,11 @@ void per_cpu_trap_init(bool is_boot_cpu)
 		/* Boot CPU's cache setup in setup_arch(). */
 		if (!is_boot_cpu)
 			cpu_cache_init();
+#ifdef CONFIG_BRCMSTB
+		brcm_tlb_init();
+#else
 		tlb_init();
+#endif
 #ifdef CONFIG_MIPS_MT_SMTC
 	} else if (!secondaryTC) {
 		/*
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index b897dde93e7a..174888c5036f 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -91,6 +91,10 @@
 #include <asm/fpu.h>
 #include <asm/fpu_emulator.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 #define STR(x)	__STR(x)
 #define __STR(x)  #x
 
@@ -429,7 +433,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	unsigned int res;
 	unsigned long origpc;
 	unsigned long orig31;
-	void __user *fault_addr = NULL;
+	void __user __maybe_unused *fault_addr = NULL;
 
 	origpc = (unsigned long)pc;
 	orig31 = regs->regs[31];
@@ -603,6 +607,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 	case ldc1_op:
 	case swc1_op:
 	case sdc1_op:
+#ifdef CONFIG_BRCMSTB
+		switch (brcm_unaligned_fp(addr, &insn, regs)) {
+		case -EINVAL:
+			goto sigbus;
+		case -EFAULT:
+			goto fault;
+		}
+		compute_return_epc(regs);
+		break;
+#else
 		die_if_kernel("Unaligned FP access in kernel code", regs);
 		BUG_ON(!used_math());
 
@@ -617,6 +631,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
 		if (res == 0)
 			break;
 		return;
+#endif
 
 	/*
 	 * COP2 is available to implementor for application specific use.
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index eeddc58802e1..9e0084e32d3d 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
 obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
+obj-$(CONFIG_BRCM_LIBGCC)       += udivdi3.o
diff --git a/arch/mips/lib/longlong.h b/arch/mips/lib/longlong.h
new file mode 100644
index 000000000000..d7d73982d74c
--- /dev/null
+++ b/arch/mips/lib/longlong.h
@@ -0,0 +1,1350 @@
+/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
+   Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
+
+   This definition file is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either
+   version 2, or (at your option) any later version.
+
+   This definition file is distributed in the hope that it will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+   See the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/* You have to define the following before including this file:
+
+   UWtype -- An unsigned type, default type for operations (typically a "word")
+   UHWtype -- An unsigned type, at least half the size of UWtype.
+   UDWtype -- An unsigned type, at least twice as large a UWtype
+   W_TYPE_SIZE -- size in bits of UWtype
+
+   UQItype -- Unsigned 8 bit type.
+   SItype, USItype -- Signed and unsigned 32 bit types.
+   DItype, UDItype -- Signed and unsigned 64 bit types.
+
+   On a 32 bit machine UWtype should typically be USItype;
+   on a 64 bit machine, UWtype should typically be UDItype.
+*/
+
+#define __BITS4 (W_TYPE_SIZE / 4)
+#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
+#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
+
+#ifndef W_TYPE_SIZE
+#define W_TYPE_SIZE	32
+#define UWtype		USItype
+#define UHWtype		USItype
+#define UDWtype		UDItype
+#endif
+
+/* Define auxiliary asm macros.
+
+   1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
+   UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
+   word product in HIGH_PROD and LOW_PROD.
+
+   2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
+   UDWtype product.  This is just a variant of umul_ppmm.
+
+   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator) divides a UDWtype, composed by the UWtype integers
+   HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
+   in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
+   than DENOMINATOR for correct operation.  If, in addition, the most
+   significant bit of DENOMINATOR must be 1, then the pre-processor symbol
+   UDIV_NEEDS_NORMALIZATION is defined to 1.
+
+   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
+   is rounded towards 0.
+
+   5) count_leading_zeros(count, x) counts the number of zero-bits from the
+   msb to the first nonzero bit in the UWtype X.  This is the number of
+   steps X needs to be shifted left to set the msb.  Undefined for X == 0,
+   unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
+
+   6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
+   from the least significant end.
+
+   7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
+   high_addend_2, low_addend_2) adds two UWtype integers, composed by
+   HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
+   respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
+   (i.e. carry out) is not stored anywhere, and is lost.
+
+   8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
+   high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
+   composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
+   LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
+   and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
+   and is lost.
+
+   If any of these macros are left undefined for a particular CPU,
+   C macros are used.  */
+
+/* The CPUs come in alphabetical order below.
+
+   Please add support for more CPUs here, or improve the current support
+   for the CPUs below!
+   (E.g. WE32100, IBM360.)  */
+
+#if defined (__GNUC__) && !defined (NO_ASM)
+
+/* We sometimes need to clobber "cc" with gcc2, but that would not be
+   understood by gcc1.  Use cpp to avoid major code duplication.  */
+#if __GNUC__ < 2
+#define __CLOBBER_CC
+#define __AND_CLOBBER_CC
+#else /* __GNUC__ >= 2 */
+#define __CLOBBER_CC : "cc"
+#define __AND_CLOBBER_CC , "cc"
+#endif /* __GNUC__ < 2 */
+
+#if defined (__alpha) && W_TYPE_SIZE == 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("umulh %r1,%2,%0"						\
+	     : "=r" ((UDItype) ph)					\
+	     : "%rJ" (__m0),						\
+	       "rI" (__m1));						\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 46
+#ifndef LONGLONG_STANDALONE
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  do { UDItype __r;							\
+    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));				\
+    (r) = __r;								\
+  } while (0)
+extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
+#define UDIV_TIME 220
+#endif /* LONGLONG_STANDALONE */
+#ifdef __alpha_cix__
+#define count_leading_zeros(COUNT,X) \
+  __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
+#define count_trailing_zeros(COUNT,X) \
+  __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
+#define COUNT_LEADING_ZEROS_0 64
+#else
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __a = __clz_tab[__t ^ 0xff] - 1;					\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    (COUNT) = 64 - (__clz_tab[__t] + __a*8);				\
+  } while (0)
+#define count_trailing_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __t = ~__t & -~__t;							\
+    __a = ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    __a <<= 3;								\
+    __t &= -__t;							\
+    __a += ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    (COUNT) = __a;							\
+  } while (0)
+#endif /* __alpha_cix__ */
+#endif /* __alpha */
+
+#if defined (__arc__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+/* Call libgcc routine.  */
+#define umul_ppmm(w1, w0, u, v) \
+do {									\
+  DWunion __w;								\
+  __w.ll = __umulsidi3 (u, v);						\
+  w1 = __w.s.high;							\
+  w0 = __w.s.low;							\
+} while (0)
+#define __umulsidi3 __umulsidi3
+UDItype __umulsidi3 (USItype, USItype);
+#endif
+
+#if defined (__arm__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, a, b) \
+{register USItype __t0, __t1, __t2;					\
+  __asm__ ("%@ Inlined umul_ppmm\n"					\
+	   "	mov	%2, %5, lsr #16\n"				\
+	   "	mov	%0, %6, lsr #16\n"				\
+	   "	bic	%3, %5, %2, lsl #16\n"				\
+	   "	bic	%4, %6, %0, lsl #16\n"				\
+	   "	mul	%1, %3, %4\n"					\
+	   "	mul	%4, %2, %4\n"					\
+	   "	mul	%3, %0, %3\n"					\
+	   "	mul	%0, %2, %0\n"					\
+	   "	adds	%3, %4, %3\n"					\
+	   "	addcs	%0, %0, #65536\n"				\
+	   "	adds	%1, %1, %3, lsl #16\n"				\
+	   "	adc	%0, %0, %3, lsr #16"				\
+	   : "=&r" ((USItype) (xh)),					\
+	     "=r" ((USItype) (xl)),					\
+	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
+	   : "r" ((USItype) (a)),					\
+	     "r" ((USItype) (b)));}
+#define UMUL_TIME 20
+#define UDIV_TIME 100
+#endif /* __arm__ */
+
+#if defined (__hppa) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "%rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#if defined (_PA_RISC1_1)
+#define umul_ppmm(w1, w0, u, v) \
+  do {									\
+    union								\
+      {									\
+	UDItype __f;							\
+	struct {USItype __w1, __w0;} __w1w0;				\
+      } __t;								\
+    __asm__ ("xmpyu %1,%2,%0"						\
+	     : "=x" (__t.__f)						\
+	     : "x" ((USItype) (u)),					\
+	       "x" ((USItype) (v)));					\
+    (w1) = __t.__w1w0.__w1;						\
+    (w0) = __t.__w1w0.__w0;						\
+     } while (0)
+#define UMUL_TIME 8
+#else
+#define UMUL_TIME 30
+#endif
+#define UDIV_TIME 40
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __tmp;							\
+    __asm__ (								\
+       "ldi		1,%0\n"						\
+"	extru,=		%1,15,16,%%r0		; Bits 31..16 zero?\n"	\
+"	extru,tr	%1,15,16,%1		; No.  Shift down, skip add.\n"\
+"	ldo		16(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,23,8,%%r0		; Bits 15..8 zero?\n"	\
+"	extru,tr	%1,23,8,%1		; No.  Shift down, skip add.\n"\
+"	ldo		8(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,27,4,%%r0		; Bits 7..4 zero?\n"	\
+"	extru,tr	%1,27,4,%1		; No.  Shift down, skip add.\n"\
+"	ldo		4(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,29,2,%%r0		; Bits 3..2 zero?\n"	\
+"	extru,tr	%1,29,2,%1		; No.  Shift down, skip add.\n"\
+"	ldo		2(%0),%0		; Yes.  Perform add.\n"	\
+"	extru		%1,30,1,%1		; Extract bit 1.\n"	\
+"	sub		%0,%1,%0		; Subtract it.\n"	\
+	: "=r" (count), "=r" (__tmp) : "1" (x));			\
+  } while (0)
+#endif
+
+#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
+#define smul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __asm__ ("lr %N0,%1\n\tmr %0,%2"					\
+	     : "=&r" (__x.__ll)						\
+	     : "r" (m0), "r" (m1));					\
+    (xh) = __x.__i.__h; (xl) = __x.__i.__l;				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __x.__i.__h = n1; __x.__i.__l = n0;					\
+    __asm__ ("dr %0,%2"							\
+	     : "=r" (__x.__ll)						\
+	     : "0" (__x.__ll), "r" (d));				\
+    (q) = __x.__i.__l; (r) = __x.__i.__h;				\
+  } while (0)
+#endif
+
+#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl %5,%1\n\tadcl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl %5,%1\n\tsbbl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mull %3"							\
+	   : "=a" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "rm" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, dv) \
+  __asm__ ("divl %4"							\
+	   : "=a" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "rm" ((USItype) (dv)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("bsrl %1,%0"						\
+	     : "=r" (__cbtmp) : "rm" ((USItype) (x)));			\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define count_trailing_zeros(count, x) \
+  __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
+#define UMUL_TIME 40
+#define UDIV_TIME 40
+#endif /* 80x86 */
+
+#if defined (__i960__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("emul	%2,%1,%0"					\
+	   : "=d" (__xx.__ll)						\
+	   : "%dI" ((USItype) (u)),					\
+	     "dI" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("emul	%2,%1,%0"					\
+	     : "=d" (__w)						\
+	     : "%dI" ((USItype) (u)),					\
+	       "dI" ((USItype) (v)));					\
+    __w; })
+#endif /* __i960__ */
+
+#if defined (__M32R__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#endif /* __M32R__ */
+
+#if defined (__mc68000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+
+/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mcpu32__) || defined(mcpu32)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mulu%.l %3,%1:%0"						\
+	   : "=d" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "dmi" ((USItype) (v)))
+#define UMUL_TIME 45
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divu%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+#define UDIV_TIME 90
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divs%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+
+#else /* not mc68020 */
+#if !defined(__mcf5200__)
+/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
+#define umul_ppmm(xh, xl, a, b) \
+  __asm__ ("| Inlined umul_ppmm\n"					\
+	   "	move%.l	%2,%/d0\n"					\
+	   "	move%.l	%3,%/d1\n"					\
+	   "	move%.l	%/d0,%/d2\n"					\
+	   "	swap	%/d0\n"						\
+	   "	move%.l	%/d1,%/d3\n"					\
+	   "	swap	%/d1\n"						\
+	   "	move%.w	%/d2,%/d4\n"					\
+	   "	mulu	%/d3,%/d4\n"					\
+	   "	mulu	%/d1,%/d2\n"					\
+	   "	mulu	%/d0,%/d3\n"					\
+	   "	mulu	%/d0,%/d1\n"					\
+	   "	move%.l	%/d4,%/d0\n"					\
+	   "	eor%.w	%/d0,%/d0\n"					\
+	   "	swap	%/d0\n"						\
+	   "	add%.l	%/d0,%/d2\n"					\
+	   "	add%.l	%/d3,%/d2\n"					\
+	   "	jcc	1f\n"						\
+	   "	add%.l	%#65536,%/d1\n"					\
+	   "1:	swap	%/d2\n"						\
+	   "	moveq	%#0,%/d0\n"					\
+	   "	move%.w	%/d2,%/d0\n"					\
+	   "	move%.w	%/d4,%/d2\n"					\
+	   "	move%.l	%/d2,%1\n"					\
+	   "	add%.l	%/d1,%/d0\n"					\
+	   "	move%.l	%/d0,%0"					\
+	   : "=g" ((USItype) (xh)),					\
+	     "=g" ((USItype) (xl))					\
+	   : "g" ((USItype) (a)),					\
+	     "g" ((USItype) (b))					\
+	   : "d0", "d1", "d2", "d3", "d4")
+#define UMUL_TIME 100
+#define UDIV_TIME 400
+#endif /* not mcf5200 */
+#endif /* not mc68020 */
+
+/* The '020, '030, '040 and '060 have bitfield insns.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mc68060__) || defined(mc68060)
+#define count_leading_zeros(count, x) \
+  __asm__ ("bfffo %1{%b2:%b2},%0"					\
+	   : "=d" ((USItype) (count))					\
+	   : "od" ((USItype) (x)), "n" (0))
+#endif
+#endif /* mc68000 */
+
+#if defined (__m88000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("ff1 %0,%1"						\
+	     : "=r" (__cbtmp)						\
+	     : "r" ((USItype) (x)));					\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 63 /* sic */
+#if defined (__mc88110__)
+#define umul_ppmm(wh, wl, u, v) \
+  do {									\
+    union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+    __asm__ ("mulu.d	%0,%1,%2"					\
+	     : "=r" (__xx.__ll)						\
+	     : "r" ((USItype) (u)),					\
+	       "r" ((USItype) (v)));					\
+    (wh) = __xx.__i.__h;						\
+    (wl) = __xx.__i.__l;						\
+  } while (0)
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+  USItype __q;								\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("divu.d %0,%1,%2"						\
+	   : "=r" (__q)							\
+	   : "r" (__xx.__ll),						\
+	     "r" ((USItype) (d)));					\
+  (r) = (n0) - __q * (d); (q) = __q; })
+#define UMUL_TIME 5
+#define UDIV_TIME 25
+#else
+#define UMUL_TIME 17
+#define UDIV_TIME 150
+#endif /* __mc88110__ */
+#endif /* __m88000__ */
+
+/* Test for gcc >= maj.min, as per __GNUC_PREREQ in glibc */
+#if defined (__GNUC__) && defined (__GNUC_MINOR__)
+#define __GNUC_PREREQ(maj, min) \
+	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
+#else
+#define __GNUC_PREREQ(maj, min)  0
+#endif
+
+/***************************************
+ **************  MIPS  *****************
+ ***************************************/
+#if defined (__mips__) && W_TYPE_SIZE == 32
+#if __GNUC_PREREQ (4,4)
+/* adapted from OpenWRT 001-mips-h-constraint.patch */
+#define umul_ppmm(w1, w0, u, v) \
+  do {                                                                  \
+    UDItype __ll = (UDItype)(u) * (v);                                  \
+    w1 = __ll >> 32;                                                    \
+    w0 = __ll;                                                          \
+  } while (0)
+#else
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("multu %2,%3"                                                \
+	   : "=l" ((USItype)(w0)),                                      \
+	     "=h" ((USItype)(w1))                                       \
+	   : "d" ((USItype)(u)),                                        \
+	     "d" ((USItype)(v)))
+#endif
+
+#define UMUL_TIME 10
+#define UDIV_TIME 100
+#endif /* __mips__ */
+
+#if defined (__ns32000__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("meid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "%0" ((USItype) (u)),					\
+	     "g" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("meid %2,%0"						\
+	     : "=g" (__w)						\
+	     : "%0" ((USItype) (u)),					\
+	       "g" ((USItype) (v)));					\
+    __w; })
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("deid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "0" (__xx.__ll),						\
+	     "g" ((USItype) (d)));					\
+  (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
+#define count_trailing_zeros(count,x) \
+  do {									\
+    __asm__ ("ffsd     %2,%0"						\
+            : "=r" ((USItype) (count))					\
+            : "0" ((USItype) 0),					\
+              "r" ((USItype) (x)));					\
+  } while (0)
+#endif /* __ns32000__ */
+
+/* FIXME: We should test _IBMR2 here when we add assembly support for the
+   system vendor compilers.
+   FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
+   enough, since that hits ARM and m68k too.  */
+#if (defined (_ARCH_PPC)	/* AIX */				\
+     || defined (_ARCH_PWR)	/* AIX */				\
+     || defined (_ARCH_COM)	/* AIX */				\
+     || defined (__powerpc__)	/* gcc */				\
+     || defined (__POWERPC__)	/* BEOS */				\
+     || defined (__ppc__)	/* Darwin */				\
+     || defined (PPC)		/* GNU/Linux, SysV */			\
+     ) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 32
+#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
+  || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    SItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14
+#define UDIV_TIME 120
+#elif defined (_ARCH_PWR)
+#define UMUL_TIME 8
+#define smul_ppmm(xh, xl, m0, m1) \
+  __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
+#define SMUL_TIME 4
+#define sdiv_qrnnd(q, r, nh, nl, d) \
+  __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
+#define UDIV_TIME 100
+#endif
+#endif /* 32-bit POWER architecture variants.  */
+
+/* We should test _IBMR2 here when we add assembly support for the system
+   vendor compilers.  */
+#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    DItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14  /* ??? */
+#define UDIV_TIME 120 /* ??? */
+#endif /* 64-bit PowerPC.  */
+
+#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("a %1,%5\n\tae %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("s %1,%5\n\tse %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ (								\
+       "s	r2,r2\n"						\
+"	mts	r10,%2\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	cas	%0,r2,r0\n"						\
+"	mfs	r10,%1"							\
+	     : "=r" ((USItype) (ph)),					\
+	       "=r" ((USItype) (pl))					\
+	     : "%r" (__m0),						\
+		"r" (__m1)						\
+	     : "r2");							\
+    (ph) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define UMUL_TIME 20
+#define UDIV_TIME 200
+#define count_leading_zeros(count, x) \
+  do {									\
+    if ((x) >= 0x10000)							\
+      __asm__ ("clz	%0,%1"						\
+	       : "=r" ((USItype) (count))				\
+	       : "r" ((USItype) (x) >> 16));				\
+    else								\
+      {									\
+	__asm__ ("clz	%0,%1"						\
+		 : "=r" ((USItype) (count))				\
+		 : "r" ((USItype) (x)));					\
+	(count) += 16;							\
+      }									\
+  } while (0)
+#endif
+
+#if defined (__sh2__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ (								\
+       "dmulu.l	%2,%3\n\tsts	macl,%1\n\tsts	mach,%0"		\
+	   : "=r" ((USItype)(w1)),					\
+	     "=r" ((USItype)(w0))					\
+	   : "r" ((USItype)(u)),					\
+	     "r" ((USItype)(v))						\
+	   : "macl", "mach")
+#define UMUL_TIME 5
+#endif
+
+#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      UDItype x_ = (USItype)(x);					\
+      SItype c_;							\
+									\
+      __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));			\
+      (count) = c_ - 31;						\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
+    && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#if defined (__sparc_v8__)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__n1)),					\
+	     "r" ((USItype) (__n0)),					\
+	     "r" ((USItype) (__d)))
+#else
+#if defined (__sparclite__)
+/* This has hardware multiply but not divide.  It also has two additional
+   instructions scan (ffs from high bit) and divscc.  */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	wr	%%g0,%2,%%y	! Not a delayed write for sparclite\n"	\
+"	tst	%%g0\n"							\
+"	divscc	%3,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%0\n"						\
+"	rd	%%y,%1\n"						\
+"	bl,a 1f\n"							\
+"	add	%1,%4,%1\n"						\
+"1:	! End of inline udiv_qrnnd"					\
+	   : "=r" ((USItype) (q)),					\
+	     "=r" ((USItype) (r))					\
+	   : "r" ((USItype) (n1)),					\
+	     "r" ((USItype) (n0)),					\
+	     "rI" ((USItype) (d))					\
+	   : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME 37
+#define count_leading_zeros(count, x) \
+  do {                                                                  \
+  __asm__ ("scan %1,1,%0"                                               \
+           : "=r" ((USItype) (count))                                   \
+           : "r" ((USItype) (x)));					\
+  } while (0)
+/* Early sparclites return 63 for an argument of 0, but they warn that future
+   implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
+   undefined.  */
+#else
+/* SPARC without integer multiplication and divide instructions.
+   (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("! Inlined umul_ppmm\n"					\
+"	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n"\
+"	sra	%3,31,%%o5	! Don't move this insn\n"		\
+"	and	%2,%%o5,%%o5	! Don't move this insn\n"		\
+"	andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,0,%%g1\n"						\
+"	add	%%g1,%%o5,%0\n"						\
+"	rd	%%y,%1"							\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "%rI" ((USItype) (u)),					\
+	     "r" ((USItype) (v))						\
+	   : "g1", "o5" __AND_CLOBBER_CC)
+#define UMUL_TIME 39		/* 39 instructions */
+/* It's quite necessary to add this much assembler for the sparc.
+   The default udiv_qrnnd (in C) is more than 10 times slower!  */
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	mov	32,%%g1\n"						\
+"	subcc	%1,%2,%%g0\n"						\
+"1:	bcs	5f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	sub	%1,%2,%1	! this kills msb of n\n"		\
+"	addx	%1,%1,%1	! so this can't give carry\n"		\
+"	subcc	%%g1,1,%%g1\n"						\
+"2:	bne	1b\n"							\
+"	 subcc	%1,%2,%%g0\n"						\
+"	bcs	3f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	b	3f\n"							\
+"	 sub	%1,%2,%1	! this kills msb of n\n"		\
+"4:	sub	%1,%2,%1\n"						\
+"5:	addxcc	%1,%1,%1\n"						\
+"	bcc	2b\n"							\
+"	 subcc	%%g1,1,%%g1\n"						\
+"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
+"	bne	4b\n"							\
+"	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
+"	sub	%1,%2,%1\n"						\
+"3:	xnor	%0,0,%0\n"						\
+"	! End of inline udiv_qrnnd"					\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__d)),					\
+	     "1" ((USItype) (__n1)),					\
+	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME (3+7*32)	/* 7 instructions/iteration. 32 iterations.  */
+#endif /* __sparclite__ */
+#endif /* __sparc_v8__ */
+#endif /* sparc32 */
+
+#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
+    && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
+  __asm__ ("addcc %r4,%5,%1\n\t"					\
+   	   "add %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "add %0, 1, %0\n"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "%rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "%rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) 				\
+  __asm__ ("subcc %r4,%5,%1\n\t"					\
+   	   "sub %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "sub %0, 1, %0\n\t"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define umul_ppmm(wh, wl, u, v)						\
+  do {									\
+	  UDItype tmp1, tmp2, tmp3, tmp4;				\
+	  __asm__ __volatile__ (					\
+		   "srl %7,0,%3\n\t"					\
+		   "mulx %3,%6,%1\n\t"					\
+		   "srlx %6,32,%2\n\t"					\
+		   "mulx %2,%3,%4\n\t"					\
+		   "sllx %4,32,%5\n\t"					\
+		   "srl %6,0,%3\n\t"					\
+		   "sub %1,%5,%5\n\t"					\
+		   "srlx %5,32,%5\n\t"					\
+		   "addcc %4,%5,%4\n\t"					\
+		   "srlx %7,32,%5\n\t"					\
+		   "mulx %3,%5,%3\n\t"					\
+		   "mulx %2,%5,%5\n\t"					\
+		   "sethi %%hi(0x80000000),%2\n\t"			\
+		   "addcc %4,%3,%4\n\t"					\
+		   "srlx %4,32,%4\n\t"					\
+		   "add %2,%2,%2\n\t"					\
+		   "movcc %%xcc,%%g0,%2\n\t"				\
+		   "addcc %5,%4,%5\n\t"					\
+		   "sllx %3,32,%3\n\t"					\
+		   "add %1,%3,%1\n\t"					\
+		   "add %5,%2,%0"					\
+	   : "=r" ((UDItype)(wh)),					\
+	     "=&r" ((UDItype)(wl)),					\
+	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
+	   : "r" ((UDItype)(u)),					\
+	     "r" ((UDItype)(v))						\
+	   __CLOBBER_CC);						\
+  } while (0)
+#define UMUL_TIME 96
+#define UDIV_TIME 230
+#endif /* sparc64 */
+
+#if defined (__vax__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {								\
+	UDItype __ll;							\
+	struct {USItype __l, __h;} __i;					\
+      } __xx;								\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("emul %1,%2,$0,%0"						\
+	     : "=r" (__xx.__ll)						\
+	     : "g" (__m0),						\
+	       "g" (__m1));						\
+    (xh) = __xx.__i.__h;						\
+    (xl) = __xx.__i.__l;						\
+    (xh) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {SItype __l, __h;} __i;				\
+	  } __xx;							\
+    __xx.__i.__h = n1; __xx.__i.__l = n0;				\
+    __asm__ ("ediv %3,%2,%0,%1"						\
+	     : "=g" (q), "=g" (r)					\
+	     : "g" (__xx.__ll), "g" (d));				\
+  } while (0)
+#endif /* __vax__ */
+
+#if defined (__z8000__) && W_TYPE_SIZE == 16
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add	%H1,%H5\n\tadc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "%0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "%1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub	%H1,%H5\n\tsbc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {long int __ll;						\
+	   struct {unsigned int __h, __l;} __i;				\
+	  } __xx;							\
+    unsigned int __m0 = (m0), __m1 = (m1);				\
+    __asm__ ("mult	%S0,%H3"					\
+	     : "=r" (__xx.__i.__h),					\
+	       "=r" (__xx.__i.__l)					\
+	     : "%1" (__m0),						\
+	       "rQR" (__m1));						\
+    (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;				\
+    (xh) += ((((signed int) __m0 >> 15) & __m1)				\
+	     + (((signed int) __m1 >> 15) & __m0));			\
+  } while (0)
+#endif /* __z8000__ */
+
+#endif /* __GNUC__ */
+
+/* If this machine has no inline assembler, use C macros.  */
+
+#if !defined (add_ssaaaa)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) + (bl);							\
+    (sh) = (ah) + (bh) + (__x < (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+#if !defined (sub_ddmmss)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) - (bl);							\
+    (sh) = (ah) - (bh) - (__x > (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
+   smul_ppmm.  */
+#if !defined (umul_ppmm) && defined (smul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __w1;							\
+    UWtype __xm0 = (u), __xm1 = (v);					\
+    smul_ppmm (__w1, w0, __xm0, __xm1);					\
+    (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)		\
+		+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);		\
+  } while (0)
+#endif
+
+/* If we still don't have umul_ppmm, define it using plain C.  */
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+    UHWtype __ul, __vl, __uh, __vh;					\
+									\
+    __ul = __ll_lowpart (u);						\
+    __uh = __ll_highpart (u);						\
+    __vl = __ll_lowpart (v);						\
+    __vh = __ll_highpart (v);						\
+									\
+    __x0 = (UWtype) __ul * __vl;					\
+    __x1 = (UWtype) __ul * __vh;					\
+    __x2 = (UWtype) __uh * __vl;					\
+    __x3 = (UWtype) __uh * __vh;					\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    if (__x1 < __x2)		/* did we get it? */			\
+      __x3 += __ll_B;		/* yes, add it in the proper pos.  */	\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v) \
+  ({DWunion __w;							\
+    umul_ppmm (__w.s.high, __w.s.low, u, v);				\
+    __w.ll; })
+#endif
+
+/* Define this unconditionally, so it can be used for debugging.  */
+#define __udiv_qrnnd_c(q, r, n1, n0, d) \
+  do {									\
+    UWtype __d1, __d0, __q1, __q0;					\
+    UWtype __r1, __r0, __m;						\
+    __d1 = __ll_highpart (d);						\
+    __d0 = __ll_lowpart (d);						\
+									\
+    __r1 = (n1) % __d1;							\
+    __q1 = (n1) / __d1;							\
+    __m = (UWtype) __q1 * __d0;						\
+    __r1 = __r1 * __ll_B | __ll_highpart (n0);				\
+    if (__r1 < __m)							\
+      {									\
+	__q1--, __r1 += (d);						\
+	if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
+	  if (__r1 < __m)						\
+	    __q1--, __r1 += (d);					\
+      }									\
+    __r1 -= __m;							\
+									\
+    __r0 = __r1 % __d1;							\
+    __q0 = __r1 / __d1;							\
+    __m = (UWtype) __q0 * __d0;						\
+    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q0--, __r0 += (d);						\
+	if (__r0 >= (d))						\
+	  if (__r0 < __m)						\
+	    __q0--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    (q) = (UWtype) __q1 * __ll_B | __q0;				\
+    (r) = __r0;								\
+  } while (0)
+
+/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
+   __udiv_w_sdiv (defined in libgcc or elsewhere).  */
+#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
+#define udiv_qrnnd(q, r, nh, nl, d) \
+  do {									\
+    USItype __r;							\
+    (q) = __udiv_w_sdiv (&__r, nh, nl, d);				\
+    (r) = __r;								\
+  } while (0)
+#endif
+
+/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
+#if !defined (udiv_qrnnd)
+#define UDIV_NEEDS_NORMALIZATION 1
+#define udiv_qrnnd __udiv_qrnnd_c
+#endif
+
+#if !defined (count_leading_zeros)
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(count, x) \
+  do {									\
+    UWtype __xr = (x);							\
+    UWtype __a;								\
+									\
+    if (W_TYPE_SIZE <= 32)						\
+      {									\
+	__a = __xr < ((UWtype)1<<2*__BITS4)				\
+	  ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)			\
+	  : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);	\
+      }									\
+    else								\
+      {									\
+	for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)			\
+	  if (((__xr >> __a) & 0xff) != 0)				\
+	    break;							\
+      }									\
+									\
+    (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);		\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
+#endif
+
+#if !defined (count_trailing_zeros)
+/* Define count_trailing_zeros using count_leading_zeros.  The latter might be
+   defined in asm, but if it is not, the C version above is good enough.  */
+#define count_trailing_zeros(count, x) \
+  do {									\
+    UWtype __ctz_x = (x);						\
+    UWtype __ctz_c;							\
+    count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);			\
+    (count) = W_TYPE_SIZE - 1 - __ctz_c;				\
+  } while (0)
+#endif
+
+#ifndef UDIV_NEEDS_NORMALIZATION
+#define UDIV_NEEDS_NORMALIZATION 0
+#endif
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index 000000000000..828fc207d316
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,266 @@
+/* More subroutines needed by GCC output code on some machines.  */
+/* Compile this one with gcc.  */
+/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.
+ */
+/* support functions required by the kernel. based on code from gcc-2.95.3 */
+/* I Molton     29/07/01 */
+
+#include <linux/module.h>
+
+#define BITS_PER_UNIT  8
+#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
+
+typedef unsigned int UQItype    __attribute__ ((mode (QI)));
+typedef          int SItype     __attribute__ ((mode (SI)));
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef          int DItype     __attribute__ ((mode (DI)));
+typedef          int word_type 	__attribute__ ((mode (__word__)));
+typedef unsigned int UDItype    __attribute__ ((mode (DI)));
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+  struct DIstruct {USItype low; SItype high;};
+#else
+  struct DIstruct {SItype high; USItype low;};
+#endif
+
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+
+#include "longlong.h"
+
+const UQItype __clz_tab[] =
+{
+  0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+};
+
+UDItype
+__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
+{
+  DIunion ww;
+  DIunion nn, dd;
+  DIunion rr;
+  USItype d0, d1, n0, n1, n2;
+  USItype q0, q1;
+  USItype b, bm;
+
+  nn.ll = n;
+  dd.ll = d;
+
+  d0 = dd.s.low;
+  d1 = dd.s.high;
+  n0 = nn.s.low;
+  n1 = nn.s.high;
+
+  if (d1 == 0)
+    {
+      if (d0 > n1)
+        {
+          /* 0q = nn / 0D */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm != 0)
+            {
+              /* Normalize, i.e. make the most significant bit of the
+                 denominator set.  */
+
+              d0 = d0 << bm;
+              n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
+              n0 = n0 << bm;
+            }
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+          q1 = 0;
+
+          /* Remainder in n0 >> bm.  */
+        }
+      else
+        {
+          /* qq = NN / 0d */
+
+          if (d0 == 0)
+            d0 = 1 / d0;        /* Divide intentionally by zero.  */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm == 0)
+            {
+              /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 leading quotient digit q1 = 1).
+
+                 This special case is necessary, not an optimization.
+                 (Shifts counts of SI_TYPE_SIZE are undefined.)  */
+
+              n1 -= d0;
+              q1 = 1;
+            }
+          else
+            {
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q1, n1, n2, n1, d0);
+            }
+
+          /* n1 != d0...  */
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+
+          /* Remainder in n0 >> bm.  */
+        }
+
+      if (rp != 0)
+        {
+          rr.s.low = n0 >> bm;
+          rr.s.high = 0;
+          *rp = rr.ll;
+        }
+    }
+  else
+    {
+      if (d1 > n1)
+        {
+          /* 00 = nn / DD */
+
+          q0 = 0;
+          q1 = 0;
+
+          /* Remainder in n1n0.  */
+          if (rp != 0)
+            {
+              rr.s.low = n0;
+              rr.s.high = n1;
+              *rp = rr.ll;
+            }
+        }
+      else
+        {
+          /* 0q = NN / dd */
+
+          count_leading_zeros (bm, d1);
+          if (bm == 0)
+            {
+              /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 quotient digit q0 = 0 or 1).
+
+                 This special case is necessary, not an optimization.  */
+
+              /* The condition on the next line takes advantage of that
+                 n1 >= d1 (true due to program flow).  */
+              if (n1 > d1 || n0 >= d0)
+                {
+                  q0 = 1;
+                  sub_ddmmss (n1, n0, n1, n0, d1, d0);
+                }
+              else
+                q0 = 0;
+
+              q1 = 0;
+
+              if (rp != 0)
+                {
+                  rr.s.low = n0;
+                  rr.s.high = n1;
+                  *rp = rr.ll;
+                }
+            }
+          else
+            {
+              USItype m1, m0;
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d1 = (d1 << bm) | (d0 >> b);
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q0, n1, n2, n1, d1);
+              umul_ppmm (m1, m0, q0, d0);
+
+              if (m1 > n1 || (m1 == n1 && m0 > n0))
+                {
+                  q0--;
+                  sub_ddmmss (m1, m0, m1, m0, d1, d0);
+                }
+
+              q1 = 0;
+
+              /* Remainder in (n1n0 - m1m0) >> bm.  */
+              if (rp != 0)
+                {
+                  sub_ddmmss (n1, n0, n1, n0, m1, m0);
+                  rr.s.low = (n1 << b) | (n0 >> bm);
+                  rr.s.high = n1 >> bm;
+                  *rp = rr.ll;
+                }
+            }
+        }
+    }
+
+  ww.s.low = q0;
+  ww.s.high = q1;
+  return ww.ll;
+}
+
+UDItype
+__udivdi3 (UDItype n, UDItype d)
+{
+  return __udivmoddi4 (n, d, (UDItype *) 0);
+}
+EXPORT_SYMBOL(__udivdi3);
+
+UDItype
+__umoddi3 (UDItype u, UDItype v)
+{
+  UDItype w;
+
+  (void) __udivmoddi4 (u ,v, &w);
+
+  return w;
+}
+
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 7f4f93ab22b7..1ee9eb93550c 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -11,7 +11,11 @@ obj-$(CONFIG_64BIT)		+= pgtable-64.o
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 
+ifeq ($(CONFIG_BRCMSTB),y)
+obj-y                           += c-brcmstb.o cex-gen.o tlb-r4k.o
+else
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
+endif
 obj-$(CONFIG_CPU_R3000)		+= c-r3k.o tlb-r3k.o
 obj-$(CONFIG_CPU_R8000)		+= c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_SB1)		+= c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
diff --git a/arch/mips/mm/c-brcmstb.c b/arch/mips/mm/c-brcmstb.c
new file mode 100644
index 000000000000..a5b3b1e7f56b
--- /dev/null
+++ b/arch/mips/mm/c-brcmstb.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/highmem.h>
+
+#include <asm/barrier.h>
+#include <asm/bcache.h>
+#include <asm/bootinfo.h>
+#include <asm/cache.h>
+#include <asm/cacheops.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/r4kcache.h>
+#include <asm/mmu_context.h>
+#include <asm/war.h>
+#include <asm/cacheflush.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/*
+ * R4K-style cache flush functions
+ *
+ * BMIPS5000 uses an optimized implementation from this file
+ * Everything uses uses a mostly-stock c-r4k.c
+ */
+
+#if !defined(CONFIG_CPU_BMIPS5000)
+#include "c-r4k.c"
+#else /* !defined(CONFIG_CPU_BMIPS5000) */
+
+static unsigned long icache_size __read_mostly;
+static unsigned long dcache_size __read_mostly;
+static unsigned long scache_size __read_mostly;
+
+/*
+ * Dummy cache handling routines for machines without boardcaches
+ */
+static void cache_noop(void) {}
+
+static struct bcache_ops no_sc_ops = {
+	.bc_enable = (void *)cache_noop,
+	.bc_disable = (void *)cache_noop,
+	.bc_wback_inv = (void *)cache_noop,
+	.bc_inv = (void *)cache_noop,
+};
+
+struct bcache_ops *bcops = &no_sc_ops;
+
+static void (* r4k_blast_dcache_page)(unsigned long addr);
+static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_dcache)(void);
+static void (* r4k_blast_icache_page)(unsigned long addr);
+static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_icache)(void);
+static void (* r4k_blast_scache_page)(unsigned long addr);
+static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_scache)(void);
+
+static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
+{
+	blast_dcache32_page(addr);
+}
+
+static void r4k___flush_cache_all(void)
+{
+	/* L2 flush implicitly flushes L1 */
+	r4k_blast_scache();
+	__sync();
+}
+
+static void r4k_noop(void)
+{
+}
+
+static void r4k_instruction_hazard(void)
+{
+	__sync();
+	__sync();
+	__asm__ __volatile__(
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	: : : "memory");
+}
+
+static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+{
+	/* Catch bad driver code */
+	BUG_ON(size == 0);
+
+	/* L2 flush implicitly flushes L1 */
+	if (size >= scache_size)
+		r4k_blast_scache();
+	else
+		bc_wback_inv(addr, size);
+
+	__sync();
+}
+
+static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+};
+
+static void __cpuinit probe_pcache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+	unsigned int config = read_c0_config();
+	unsigned long config1;
+	unsigned int lsize;
+
+	switch (c->cputype) {
+	default:
+		if (!(config & MIPS_CONF_M))
+			panic("Don't know how to probe P-caches on this cpu.");
+
+		/*
+		 * So we seem to be a MIPS32 or MIPS64 CPU
+		 * So let's probe the I-cache ...
+		 */
+		config1 = read_c0_config1();
+
+		if ((lsize = ((config1 >> 19) & 7)))
+			c->icache.linesz = 2 << lsize;
+		else
+			c->icache.linesz = lsize;
+		c->icache.sets = 64 << ((config1 >> 22) & 7);
+		c->icache.ways = 1 + ((config1 >> 16) & 7);
+
+		icache_size = c->icache.sets *
+		              c->icache.ways *
+		              c->icache.linesz;
+		c->icache.waybit = __ffs(icache_size/c->icache.ways);
+
+		if (config & 0x8)		/* VI bit */
+			c->icache.flags |= MIPS_CACHE_VTAG;
+
+		/*
+		 * Now probe the MIPS32 / MIPS64 data cache.
+		 */
+		c->dcache.flags = 0;
+
+		if ((lsize = ((config1 >> 10) & 7)))
+			c->dcache.linesz = 2 << lsize;
+		else
+			c->dcache.linesz= lsize;
+		c->dcache.sets = 64 << ((config1 >> 13) & 7);
+		c->dcache.ways = 1 + ((config1 >> 7) & 7);
+
+		dcache_size = c->dcache.sets *
+		              c->dcache.ways *
+		              c->dcache.linesz;
+		c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
+
+		c->options |= MIPS_CPU_PREFETCH;
+		break;
+	}
+
+	/* compute a couple of other cache variables */
+	c->icache.waysize = icache_size / c->icache.ways;
+	c->dcache.waysize = dcache_size / c->dcache.ways;
+
+	c->icache.sets = c->icache.linesz ?
+		icache_size / (c->icache.linesz * c->icache.ways) : 0;
+	c->dcache.sets = c->dcache.linesz ?
+		dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
+
+	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+	       icache_size >> 10,
+	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+	       way_string[c->icache.ways], c->icache.linesz);
+
+	printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
+	       dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+}
+
+extern int mips_sc_init(void);
+
+static void __cpuinit setup_scache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	if (mips_sc_init ()) {
+		scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+		printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+		       scache_size >> 10,
+		       way_string[c->scache.ways], c->scache.linesz);
+	} else {
+		panic("c-r4k cache functions require L2 enabled");
+	}
+	return;
+}
+
+static int __cpuinitdata cca = -1;
+
+static int __init cca_setup(char *str)
+{
+	get_option(&str, &cca);
+
+	return 1;
+}
+
+__setup("cca=", cca_setup);
+
+static void __cpuinit coherency_setup(void)
+{
+	if (cca < 0 || cca > 7)
+		cca = read_c0_config() & CONF_CM_CMASK;
+	_page_cachable_default = cca << _CACHE_SHIFT;
+
+	pr_debug("Using cache attribute %d\n", cca);
+	change_c0_config(CONF_CM_CMASK, cca);
+}
+
+void __cpuinit r4k_cache_init(void)
+{
+	extern void build_clear_page(void);
+	extern void build_copy_page(void);
+	extern char except_vec2_generic;
+
+	/* Default cache error handler for R4000 and R5000 family */
+	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+
+	probe_pcache();
+	setup_scache();
+
+	BUG_ON(cpu_icache_line_size() != 64);
+	BUG_ON(cpu_dcache_line_size() != 32);
+	BUG_ON(cpu_scache_line_size() != 128);
+
+	r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+	r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+	r4k_blast_dcache = blast_dcache32;
+	r4k_blast_icache_page = blast_icache64_page;
+	r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
+	r4k_blast_icache = blast_icache64;
+	r4k_blast_scache_page = blast_scache128_page;
+	r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
+	r4k_blast_scache = blast_scache128;
+
+	/* SWLINUX-2630: align to the way size (8KB) on Zephyr */
+	shm_align_mask = max_t(unsigned long,
+			       current_cpu_data.dcache.waysize, PAGE_SIZE) - 1;
+
+	__flush_cache_vmap	= r4k___flush_cache_all;
+	__flush_cache_vunmap	= r4k___flush_cache_all;
+
+	flush_cache_all		= (void *)r4k_noop;
+	__flush_cache_all	= r4k___flush_cache_all;
+	flush_cache_mm		= (void *)r4k_noop;
+	flush_cache_page	= (void *)r4k_instruction_hazard;
+	flush_cache_range	= (void *)r4k_instruction_hazard;
+
+	flush_cache_sigtramp	= (void *)r4k_noop;
+	flush_icache_all	= (void *)r4k_noop;
+	local_flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_icache_range	= (void *)r4k_instruction_hazard;
+	local_flush_icache_range	= (void *)r4k_instruction_hazard;
+
+	_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;
+	_dma_cache_wback	= r4k_dma_cache_wback_inv;
+	_dma_cache_inv		= r4k_dma_cache_wback_inv;
+
+	build_clear_page();
+	build_copy_page();
+	r4k___flush_cache_all();
+	coherency_setup();
+}
+
+#endif /* !defined(CONFIG_CPU_BMIPS5000) */
+
+/*
+ * Fine-grained cacheflush() syscall for usermode Nexus
+ */
+int brcm_cacheflush(unsigned long addr, unsigned long bytes,
+	unsigned int cache)
+{
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+	/* partial RAC invalidate is not supported */
+	if (cache == RACACHE) {
+		brcm_inv_prefetch(0, 0);
+		return 0;
+	}
+#else
+	/*
+	 * SWLINUX-2607, BMIPS5000_5200-ES100-R: Flush JTB and CRS on
+	 * user-initiated invalidations, in case a JIT buffer with mixed
+	 * code+data is getting rewritten.  This helps prevent a possible
+	 * CPU hang from prefetching invalid instructions.
+	 */
+	write_c0_brcm_action(4 << 16); /* reset JTB this thread */
+	write_c0_brcm_action(5 << 16); /* reset JTB other thread */
+	write_c0_brcm_action(6 << 16); /* reset CRS this thread */
+	write_c0_brcm_action(7 << 16); /* reset CRS other thread */
+#endif
+	/* ICACHE/BCACHE is handled by the standard implementation */
+	if (cache & ICACHE) {
+		flush_icache_range(addr, addr + bytes);
+		return 0;
+	}
+
+	/* New DCACHE implementation flushes D$/L2 out to RAM for DMA */
+	if (cache & DCACHE) {
+		unsigned long pg = addr & PAGE_MASK, end = addr + bytes;
+
+		if (bytes == 0 || (bytes >= dcache_size)) {
+			r4k_blast_dcache();
+			r4k_blast_scache();
+			__sync();
+			return 0;
+		}
+
+		down_read(&current->mm->mmap_sem);
+		while (pg < end) {
+			pgd_t *pgdp = pgd_offset(current->mm, pg);
+			pud_t *pudp = pud_offset(pgdp, pg);
+			pmd_t *pmdp = pmd_offset(pudp, pg);
+			pte_t *ptep = pte_offset(pmdp, pg);
+
+			if (!(pte_val(*ptep) & _PAGE_PRESENT)) {
+				up_read(&current->mm->mmap_sem);
+				return -EFAULT;
+			}
+
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+			r4k_blast_dcache_page(pg);
+#endif
+			r4k_blast_scache_page(pg);
+			pg += PAGE_SIZE;
+		}
+		up_read(&current->mm->mmap_sem);
+	}
+
+	if (cache & RACACHE)
+		brcm_inv_prefetch(addr, bytes);
+
+	__sync();
+	return 0;
+}
+EXPORT_SYMBOL(brcm_cacheflush);
+
+/*
+ * Flush RAC or prefetch lines after DMA from device
+ */
+void brcm_inv_prefetch(unsigned long addr, unsigned long size)
+{
+#if defined(CONFIG_CPU_BMIPS3300)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_CPU_BMIPS4380)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_BRCM_ZSCM_L2)
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+
+	BUG_ON(size == 0);
+
+	addr0 &= ~(linesz - 1);
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+	protected_writeback_scache_line(addr0);
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr1);
+	else
+		return;
+
+	addr0 += linesz;
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr0);
+	else
+		return;
+
+	addr1 -= linesz;
+	if (likely(addr1 > addr0))
+		protected_writeback_scache_line(addr0);
+#endif
+}
+EXPORT_SYMBOL(brcm_inv_prefetch);
+
+/*
+ * Hooks for extra RAC/prefetch flush after DMA
+ */
+static inline void __brcm_sync(struct page *page,
+	unsigned long offset, size_t size, enum dma_data_direction direction)
+{
+	size_t left = size;
+
+	if (direction == DMA_TO_DEVICE)
+		return;
+
+	do {
+		size_t len = left;
+
+		if (PageHighMem(page)) {
+			void *addr;
+
+			if (offset + len > PAGE_SIZE) {
+				if (offset >= PAGE_SIZE) {
+					page += offset >> PAGE_SHIFT;
+					offset &= ~PAGE_MASK;
+				}
+				len = PAGE_SIZE - offset;
+			}
+
+			addr = kmap_atomic(page);
+			brcm_inv_prefetch((unsigned long)addr + offset, len);
+			kunmap_atomic(addr);
+		} else
+			brcm_inv_prefetch((unsigned long)page_address(page) +
+				offset, size);
+		offset = 0;
+		page++;
+		left -= len;
+	} while (left);
+}
+
+void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_addr);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_single_for_cpu(struct device *dev,
+	dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_handle);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_sg_for_cpu(struct device *dev,
+	struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+	int i;
+	for (i = 0; i < nelems; i++, sg++)
+		__brcm_sync(sg_page(sg), sg->offset, sg->length, direction);
+}
+
+static int __init brcm_setup_dma_ops(void)
+{
+	mips_dma_map_ops->sync_single_for_cpu = brcm_dma_sync_single_for_cpu;
+	mips_dma_map_ops->sync_sg_for_cpu = brcm_dma_sync_sg_for_cpu;
+	return 0;
+}
+core_initcall(brcm_setup_dma_ops);
+
+/*
+ * Provide cache details for PI/Nexus
+ */
+void brcm_get_cache_info(struct brcm_cache_info *info)
+{
+	info->max_writeback = cpu_scache_line_size() ? : cpu_dcache_line_size();
+	info->max_writethrough = 0;
+	info->prefetch_enabled = 0;
+
+#if defined(CONFIG_BRCM_ZSCM_L2)
+	/* chips with prefetching L2 */
+	info->prefetch_enabled = 1;
+#elif defined(CONFIG_CPU_BMIPS3300) || defined(CONFIG_CPU_BMIPS4380)
+	/* chips with write-through RAC */
+	info->max_writethrough = info->max_writeback * 4;
+	info->prefetch_enabled = 1;
+#endif
+}
+EXPORT_SYMBOL(brcm_get_cache_info);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c14259edd53f..2b8ac99e2122 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -836,6 +836,18 @@ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 	}
 }
 
+static void b5k_instruction_hazard(void)
+{
+	__sync();
+	__sync();
+	__asm__ __volatile__(
+	"       nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"       nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"       nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"       nop; nop; nop; nop; nop; nop; nop; nop\n"
+	: : : "memory");
+}
+
 static char *way_string[] = { NULL, "direct mapped", "2-way",
 	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 };
@@ -1516,4 +1528,35 @@ void r4k_cache_init(void)
 
 	coherency_setup();
 	board_cache_error_setup = r4k_cache_error_setup;
+
+	/*
+	 * Per-CPU overrides
+	 */
+	switch (current_cpu_type()) {
+	case CPU_BMIPS4350:
+	case CPU_BMIPS4380:
+		/* No IPI is needed because all CPUs share the same D$ */
+		flush_data_cache_page = r4k_blast_dcache_page;
+		break;
+	case CPU_BMIPS5000:
+		/* We lose our superpowers if L2 is disabled */
+		if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
+			break;
+
+		/* I$ fills from D$ just by emptying the write buffers */
+		flush_cache_page = (void *)b5k_instruction_hazard;
+		flush_cache_range = (void *)b5k_instruction_hazard;
+		flush_cache_sigtramp = (void *)b5k_instruction_hazard;
+		local_flush_data_cache_page = (void *)b5k_instruction_hazard;
+		flush_data_cache_page = (void *)b5k_instruction_hazard;
+		flush_icache_range = (void *)b5k_instruction_hazard;
+		local_flush_icache_range = (void *)b5k_instruction_hazard;
+
+		/* Cache aliases are handled in hardware; allow HIGHMEM */
+		current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
+
+		/* Optimization: an L2 flush implicitly flushes the L1 */
+		current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
+		break;
+	}
 }
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index fde7e56d13fe..9fa078a5e584 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -20,6 +20,10 @@
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 /* Cache operations. */
 void (*flush_cache_all)(void);
 void (*__flush_cache_all)(void);
@@ -72,7 +76,11 @@ SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes,
 	if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
 		return -EFAULT;
 
+#ifdef CONFIG_BRCMSTB
+	return brcm_cacheflush(addr, bytes, cache);
+#else
 	flush_icache_range(addr, addr + bytes);
+#endif
 
 	return 0;
 }
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index a1087593b3c2..e38050e6d306 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -23,6 +23,10 @@
 
 #include <dma-coherence.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 #ifdef CONFIG_DMA_MAYBE_COHERENT
 int coherentio = 0;	/* User defined DMA coherency from command line. */
 EXPORT_SYMBOL_GPL(coherentio);
@@ -142,8 +146,16 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
 
 		if (!plat_device_is_coherent(dev)) {
 			dma_cache_wback_inv((unsigned long) ret, size);
+#ifdef CONFIG_BRCM_UPPER_768MB
+			if (brcm_map_coherent(*dma_handle, ret, PFN_ALIGN(size),
+					&ret, gfp)) {
+				free_pages((unsigned long)ret, size);
+				ret = NULL;
+			}
+#else
 			if (!hw_coherentio)
 				ret = UNCAC_ADDR(ret);
+#endif
 		}
 	}
 
@@ -170,8 +182,12 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 
 	plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
+#ifdef CONFIG_BRCM_UPPER_768MB
+	addr = (unsigned long)brcm_unmap_coherent(vaddr);
+#else
 	if (!plat_device_is_coherent(dev) && !hw_coherentio)
 		addr = CAC_ADDR(addr);
+#endif
 
 	free_pages(addr, get_order(size));
 }
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 6b59617760c1..4c17c88aa2c1 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -365,6 +365,9 @@ static inline void mem_init_free_highmem(void)
 	for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
 		struct page *page = pfn_to_page(tmp);
 
+		if (!pfn_valid(tmp))
+			continue;
+
 		if (!page_is_ram(tmp))
 			SetPageReserved(page);
 		else
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 7f840bc08abf..b744052ba5f2 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -127,6 +127,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
 	if (!size || last_addr < phys_addr)
 		return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 	/*
 	 * Map uncached objects in the low 512mb of address space using KSEG1,
 	 * otherwise map using page tables.
@@ -134,6 +135,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
 	if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
 	    flags == _CACHE_UNCACHED)
 		return (void __iomem *) CKSEG1ADDR(phys_addr);
+#endif
 
 	/*
 	 * Don't allow anybody to remap normal RAM that we're using..
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 9c0a6782c091..19da84685feb 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -14,3 +14,5 @@ oprofile-$(CONFIG_CPU_R10000)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_SB1)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_XLR)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_LOONGSON2)	+= op_model_loongson2.o
+oprofile-$(CONFIG_CPU_BMIPS3300)	+= op_model_bmips.o
+oprofile-$(CONFIG_CPU_BMIPS4380)	+= op_model_bmips.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 2a86e38872a7..e71ba038f1a0 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -18,6 +18,9 @@
 
 extern struct op_mips_model op_model_mipsxx_ops __weak;
 extern struct op_mips_model op_model_loongson2_ops __weak;
+#ifdef CONFIG_BRCMSTB
+extern struct op_mips_model op_model_bmips_ops __attribute__((weak));
+#endif
 
 static struct op_mips_model *model;
 
diff --git a/arch/mips/oprofile/op_model_bmips.c b/arch/mips/oprofile/op_model_bmips.c
new file mode 100644
index 000000000000..e82638a7d8df
--- /dev/null
+++ b/arch/mips/oprofile/op_model_bmips.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include "op_impl.h"
+
+/*
+ * Events coming from opcontrol look like: 0xXYZZ
+ *   X = ModuleID
+ *   Y = SetID
+ *   ZZ = EventID
+ *
+ * ModuleID and SetID are set globally so they must match for all events.
+ * Exception: events with ModuleID 0 can be used regardless of the
+ * ModuleID / SetID settings.
+ */
+
+#define BMIPS_MOD_SET(event)		(((event) >> 8) & 0xff)
+#define BMIPS_MOD(event)		(((event) >> 12) & 0x0f)
+#define BMIPS_SET(event)		(((event) >> 8) & 0x03)
+#define BMIPS_EVENT(event)		((event) & 0x7f)
+
+/* Default to using TP0 (HW can only profile one thread at a time) */
+#define PMU_TP				0
+
+#define NUM_COUNTERS			4
+
+#define GLOB_ENABLE			0x80000000
+#define GLOB_SET_SHIFT			0
+#define GLOB_MOD_SHIFT			2
+
+#define CTRL_ENABLE			0x8001
+#define CTRL_EVENT_SHIFT		2
+
+#define CNTR_OVERFLOW			0x80000000
+
+#if defined(CONFIG_CPU_BMIPS3300)
+
+/* These registers do not conform to any known MIPS standard */
+#define r_perfcntr0()			__read_32bit_c0_register($25, 0)
+#define r_perfcntr1()			__read_32bit_c0_register($25, 1)
+#define r_perfcntr2()			__read_32bit_c0_register($25, 2)
+#define r_perfcntr3()			__read_32bit_c0_register($25, 3)
+
+#define w_perfcntr0(x)			__write_32bit_c0_register($25, 0, x)
+#define w_perfcntr1(x)			__write_32bit_c0_register($25, 1, x)
+#define w_perfcntr2(x)			__write_32bit_c0_register($25, 2, x)
+#define w_perfcntr3(x)			__write_32bit_c0_register($25, 3, x)
+
+#define w_perfctrl0(x)			__write_32bit_c0_register($25, 4, x)
+#define w_perfctrl1(x)			__write_32bit_c0_register($25, 5, x)
+
+#define r_glob()			__read_32bit_c0_register($25, 6)
+#define w_glob(x)			__write_32bit_c0_register($25, 6, x)
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+static unsigned long bmips_cbr;
+
+#define PERF_RD(x)			DEV_RD(bmips_cbr + BMIPS_PERF_ ## x)
+#define PERF_WR(x, y)			DEV_WR_RB(bmips_cbr + \
+						BMIPS_PERF_ ## x, (y))
+
+#define r_perfcntr0()			PERF_RD(COUNTER_0)
+#define r_perfcntr1()			PERF_RD(COUNTER_1)
+#define r_perfcntr2()			PERF_RD(COUNTER_2)
+#define r_perfcntr3()			PERF_RD(COUNTER_3)
+
+#define w_perfcntr0(x)			PERF_WR(COUNTER_0, (x))
+#define w_perfcntr1(x)			PERF_WR(COUNTER_1, (x))
+#define w_perfcntr2(x)			PERF_WR(COUNTER_2, (x))
+#define w_perfcntr3(x)			PERF_WR(COUNTER_3, (x))
+
+#define w_perfctrl0(x)			PERF_WR(CONTROL_0, (x))
+#define w_perfctrl1(x)			PERF_WR(CONTROL_1, (x))
+
+#define r_glob()			PERF_RD(GLOBAL_CONTROL)
+#define w_glob(x)			PERF_WR(GLOBAL_CONTROL, (x))
+
+#endif
+
+static int (*save_perf_irq)(void);
+
+struct op_mips_model op_model_bmips_ops;
+
+static struct bmips_register_config {
+	unsigned int globctrl;
+	unsigned int control[4];
+	unsigned int counter[4];
+} reg;
+
+/* Compute all of the registers in preparation for enabling profiling.  */
+
+static void bmips_reg_setup(struct op_counter_config *ctr)
+{
+	int i;
+	unsigned int mod_set = 0;
+	unsigned int ev;
+
+	memset(&reg, 0, sizeof(reg));
+	reg.globctrl = GLOB_ENABLE;
+
+	for (i = 0; i < NUM_COUNTERS; i++) {
+		if (!ctr[i].enabled)
+			continue;
+		ev = ctr[i].event;
+
+		if (mod_set && BMIPS_MOD_SET(ev) &&
+				mod_set != BMIPS_MOD_SET(ev)) {
+			printk(KERN_WARNING "%s: profiling event 0x%x "
+				"conflicts with another event, disabling\n",
+				__FUNCTION__, ev);
+			continue;
+		}
+		reg.counter[i] = ctr[i].count;
+		reg.control[i] = CTRL_ENABLE |
+			(BMIPS_EVENT(ev) << CTRL_EVENT_SHIFT);
+		if (BMIPS_MOD_SET(ev))
+			mod_set = BMIPS_MOD_SET(ev);
+		reg.globctrl |= (BMIPS_MOD(ev) << GLOB_MOD_SHIFT) |
+			(BMIPS_SET(ev) << GLOB_SET_SHIFT);
+	}
+}
+
+/* Program all of the registers in preparation for enabling profiling.  */
+
+static void bmips_cpu_setup(void *args)
+{
+	w_perfcntr0(reg.counter[0]);
+	w_perfcntr1(reg.counter[1]);
+	w_perfcntr2(reg.counter[2]);
+	w_perfcntr3(reg.counter[3]);
+}
+
+static void bmips_cpu_start(void *args)
+{
+	w_perfctrl0(reg.control[0] | (reg.control[1] << 16));
+	w_perfctrl1(reg.control[2] | (reg.control[3] << 16));
+	w_glob(reg.globctrl);
+}
+
+static void bmips_cpu_stop(void *args)
+{
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+}
+
+static int bmips_perfcount_handler(void)
+{
+	int handled = IRQ_NONE;
+
+	if (!(r_glob() & GLOB_ENABLE))
+		return handled;
+
+#define HANDLE_COUNTER(n) \
+	if (r_perfcntr ## n() & CNTR_OVERFLOW) { \
+		oprofile_add_sample(get_irq_regs(), n); \
+		w_perfcntr ## n(reg.counter[n]); \
+		handled = IRQ_HANDLED; \
+	}
+
+	HANDLE_COUNTER(0)
+	HANDLE_COUNTER(1)
+	HANDLE_COUNTER(2)
+	HANDLE_COUNTER(3)
+
+	if (handled == IRQ_HANDLED)
+		bmips_cpu_start(NULL);
+
+	return handled;
+}
+
+static void bmips_perf_reset(void)
+{
+#ifdef CONFIG_CPU_BMIPS4380
+	bmips_cbr = __BMIPS_GET_CBR();
+	change_c0_brcm_cmt_ctrl(0x3 << 30, PMU_TP << 30);
+#endif
+
+	w_glob(GLOB_ENABLE);
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+	w_perfcntr0(0);
+	w_perfcntr1(0);
+	w_perfcntr2(0);
+	w_perfcntr3(0);
+}
+
+static int __init bmips_init(void)
+{
+	bmips_perf_reset();
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS3300:
+		op_model_bmips_ops.cpu_type = "mips/bmips3300";
+		break;
+	case CPU_BMIPS4380:
+		op_model_bmips_ops.cpu_type = "mips/bmips4380";
+		break;
+	default:
+		BUG();
+	}
+	save_perf_irq = perf_irq;
+	perf_irq = bmips_perfcount_handler;
+
+	return 0;
+}
+
+static void bmips_exit(void)
+{
+	bmips_perf_reset();
+	w_glob(0);
+	perf_irq = save_perf_irq;
+}
+
+struct op_mips_model op_model_bmips_ops = {
+	.reg_setup	= bmips_reg_setup,
+	.cpu_setup	= bmips_cpu_setup,
+	.init		= bmips_init,
+	.exit		= bmips_exit,
+	.cpu_start	= bmips_cpu_start,
+	.cpu_stop	= bmips_cpu_stop,
+	.num_counters	= 4
+};
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 1bf60b127377..c7d05aa748c4 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -86,8 +86,13 @@ static void pcibios_scanbus(struct pci_controller *hose)
 	if (!hose->iommu)
 		PCI_DMA_BUS_IS_PHYS = 1;
 
+#ifdef CONFIG_BRCMSTB
+	/* BSP code needs to assign bus numbers */
+	if (hose->get_busno)
+#else
 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
 		next_busno = (*hose->get_busno)();
+#endif
 
 	pci_add_resource_offset(&resources,
 				hose->mem_resource, hose->mem_offset);
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 8cd0daebb82d..7d44fb07336c 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -178,6 +178,7 @@ void __init kvm_cma_reserve(void)
 			align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
 
 		align_size = max(kvm_rma_pages << PAGE_SHIFT, align_size);
-		kvm_cma_declare_contiguous(selected_size, align_size);
+		cma_declare_contiguous(0, selected_size, 0, align_size,
+			KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, &kvm_cma);
 	}
 }
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 2f03ff018d36..ba38ebbaced3 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_X86_BUG_H
 #define _ASM_X86_BUG_H
 
-#ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
 
 #ifdef CONFIG_DEBUG_BUGVERBOSE
@@ -33,8 +32,6 @@ do {								\
 } while (0)
 #endif
 
-#endif /* !CONFIG_BUG */
-
 #include <asm-generic/bug.h>
 
 #endif /* _ASM_X86_BUG_H */
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 040718106629..9c2065e363ec 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1120,7 +1120,7 @@ void __init setup_arch(char **cmdline_p)
 	setup_real_mode();
 
 	memblock_set_current_limit(get_max_mapped());
-	dma_contiguous_reserve(0);
+	dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
 
 	/*
 	 * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3138fbb46a4..37f955fca152 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -130,6 +130,8 @@ source "drivers/staging/Kconfig"
 
 source "drivers/platform/Kconfig"
 
+source "drivers/soc/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/hwspinlock/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e3b8b06c0b2..f028f97c85cc 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,7 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-$(CONFIG_BRCMSTB)		+= brcmstb/
 obj-y				+= irqchip/
 obj-y				+= bus/
 
@@ -33,6 +34,9 @@ obj-y				+= amba/
 # really early.
 obj-$(CONFIG_DMADEVICES)	+= dma/
 
+# SOC specific infrastructure drivers.
+obj-y				+= soc/
+
 obj-$(CONFIG_VIRTIO)		+= virtio/
 obj-$(CONFIG_XEN)		+= xen/
 
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 868429a47be4..ad3e23ae6cff 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -106,6 +106,14 @@ config AHCI_IMX
 
 	  If unsure, say N.
 
+config SATA_BRCMSTB
+	tristate "Broadcom STB AHCI SATA support"
+	depends on SATA_AHCI_PLATFORM && ARCH_BRCMSTB
+	help
+	  This option enables support for STB onchip AHCI SATA cores.
+
+	  If unsure, say N.
+
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
 	depends on FSL_SOC
@@ -330,6 +338,7 @@ config SATA_VITESSE
 
 	  If unsure, say N.
 
+
 comment "PATA SFF controllers with BMDMA"
 
 config PATA_ALI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 46518c622460..b665a7427ca8 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)	+= sata_highbank.o libahci.o
 obj-$(CONFIG_AHCI_IMX)		+= ahci_imx.o
+obj-$(CONFIG_SATA_BRCMSTB)	+= sata_brcmstb.o sata_brcmstb_phy.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index ad36faf31dbd..b4f4770b342d 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -192,6 +192,12 @@ enum {
 	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
 	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
 
+	/* PORT SCR STAT bits */
+	PORT_SCR_STAT_IPM_MASK	  = (0xf << 8), /* i/f IPM state mask */
+	PORT_SCR_STAT_IPM_ACTIVE  = (0x1 << 8), /* i/f in active state */
+	PORT_SCR_STAT_IPM_PARTIAL = (0x2 << 8), /* i/f in partial state */
+	PORT_SCR_STAT_IPM_SLUMBER = (0x6 << 8), /* i/f in slumber state */
+
 	/* PORT_FBS bits */
 	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
 	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 4b231baceb09..ccfae6d61309 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -31,6 +31,7 @@ enum ahci_type {
 	AHCI,		/* standard platform ahci */
 	IMX53_AHCI,	/* ahci on i.mx53 */
 	STRICT_AHCI,	/* delayed DMA engine start */
+	BRCMSTB_AHCI,	/* ahci on BRCM STB */
 };
 
 static struct platform_device_id ahci_devtype[] = {
@@ -44,6 +45,9 @@ static struct platform_device_id ahci_devtype[] = {
 		.name = "strict-ahci",
 		.driver_data = STRICT_AHCI,
 	}, {
+		.name = "brcmstb-ahci",
+		.driver_data = BRCMSTB_AHCI,
+	}, {
 		/* sentinel */
 	}
 };
@@ -81,6 +85,15 @@ static const struct ata_port_info ahci_port_info[] = {
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_platform_ops,
 	},
+	[BRCMSTB_AHCI] = {
+		AHCI_HFLAGS	(AHCI_HFLAG_DELAY_ENGINE),
+		.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
+		.flags2		= ATA_FLAG2_WAKE_BEFORE_STOP,
+		.link_flags	= ATA_LFLAG_NO_DB_DELAY,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_platform_ops,
+	},
 };
 
 static struct scsi_host_template ahci_platform_sht = {
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 8b24a7bb573b..1b4fea35ebee 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -583,6 +583,58 @@ int ahci_stop_engine(struct ata_port *ap)
 	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 tmp;
 
+	/*
+	 * On some controllers, stopping a port's DMA engine
+	 * while the port is in ALPM state (partial or slumber)
+	 * results in failures on subsequent DMA engine starts.
+	 * For those controllers, put the port back in active
+	 * state before stopping it's DMA engine.
+	 */
+	if (ap->flags2 & ATA_FLAG2_WAKE_BEFORE_STOP) {
+		u32 sts, retries = 10;
+		struct ahci_host_priv *hpriv = ap->host->private_data;
+
+		if (!(hpriv->cap & HOST_CAP_ALPM))
+			goto skip_wake_up;
+
+		tmp = readl(port_mmio + PORT_CMD);
+		if (!(tmp & PORT_CMD_ALPE))
+			goto skip_wake_up;
+
+		sts = readl(port_mmio + PORT_SCR_STAT) &
+			PORT_SCR_STAT_IPM_MASK;
+		if ((sts != PORT_SCR_STAT_IPM_PARTIAL) &&
+		    (sts != PORT_SCR_STAT_IPM_SLUMBER))
+			goto skip_wake_up;
+
+		tmp |= PORT_CMD_ICC_ACTIVE;
+		writel(tmp, port_mmio + PORT_CMD);
+
+		do {
+			/*
+			 * The exit latency for partial state is upto 10usec
+			 * whereas it is upto 10msec for slumber state. Use
+			 * this information to choose appropriate waiting
+			 * calls so the time spent in the loop is minimized.
+			 */
+			if (sts == PORT_SCR_STAT_IPM_PARTIAL)
+				udelay(1);
+			else
+				ata_msleep(ap, 1);
+			sts = readl(port_mmio + PORT_SCR_STAT) &
+				PORT_SCR_STAT_IPM_MASK;
+			if (sts == PORT_SCR_STAT_IPM_ACTIVE)
+				break;
+		} while (--retries);
+
+		if (!retries) {
+			dev_err(ap->host->dev,
+				"failed to wake up port\n");
+			return -EIO;
+		}
+	}
+
+skip_wake_up:
 	tmp = readl(port_mmio + PORT_CMD);
 
 	/* check if the HBA is idle */
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index b0e6691faf18..230c5eab85b5 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3611,7 +3611,8 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params,
 		 * immediately after resuming.  Delay 200ms before
 		 * debouncing.
 		 */
-		ata_msleep(link->ap, 200);
+		if (!(link->flags & ATA_LFLAG_NO_DB_DELAY))
+			ata_msleep(link->ap, 200);
 
 		/* is SControl restored correctly? */
 		if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
@@ -5881,6 +5882,7 @@ struct ata_host *ata_host_alloc_pinfo(struct device *dev,
 		ap->mwdma_mask = pi->mwdma_mask;
 		ap->udma_mask = pi->udma_mask;
 		ap->flags |= pi->flags;
+		ap->flags2 |= pi->flags2;
 		ap->link.flags |= pi->link_flags;
 		ap->ops = pi->port_ops;
 
diff --git a/drivers/ata/sata_brcmstb.c b/drivers/ata/sata_brcmstb.c
new file mode 100644
index 000000000000..ccc15b279821
--- /dev/null
+++ b/drivers/ata/sata_brcmstb.c
@@ -0,0 +1,460 @@
+/*
+ *  sata_brcmstb.c - Broadcom SATA3 AHCI Controller Driver
+ *
+ *  Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/libata.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+#include <linux/compiler.h>
+#include <scsi/scsi_host.h>
+#include <linux/string.h>
+
+#include "sata_brcmstb.h"
+#include "ahci.h"
+
+static DEFINE_SPINLOCK(child_pdevs_lock);
+
+static struct pdev_map child_pdevs = {
+	.node = LIST_HEAD_INIT(child_pdevs.node),
+	.key = NULL,
+	.brcm_pdev = NULL,
+	.ahci_pdev = NULL
+};
+
+static int child_pdevs_count;
+
+static int pdev_map(struct device *ahci_dev,
+		    struct platform_device *ahci_pdev,
+		    struct platform_device *brcm_pdev)
+{
+	int status = 0;
+	struct pdev_map *head = &child_pdevs;
+	struct pdev_map *curr = kmalloc(sizeof(struct pdev_map),
+					  GFP_KERNEL);
+
+	if (!curr) {
+		pr_err("Cannot allocate map node!\n");
+		status = -ENOMEM;
+		goto err;
+	}
+
+	curr->key = ahci_dev;
+	curr->brcm_pdev = brcm_pdev;
+	curr->ahci_pdev = ahci_pdev;
+
+	spin_lock(&child_pdevs_lock);
+
+	list_add_tail(&curr->node, &head->node);
+
+	child_pdevs_count++;
+
+	spin_unlock(&child_pdevs_lock);
+
+err:
+	return status;
+}
+
+static struct pdev_map *__pdev_lookup(struct pdev_map *head,
+				       struct device *dev)
+{
+	struct list_head *pos;
+	struct pdev_map *result = NULL;
+
+	list_for_each(pos, &head->node) {
+		struct pdev_map *curr = (struct pdev_map *)pos;
+		if (curr->key == dev) {
+			result = curr;
+			break;
+		}
+	}
+
+	return result;
+}
+
+static int pdev_unmap(struct device *dev)
+{
+	int status = -EFAULT;
+	struct pdev_map *entry;
+
+	spin_lock(&child_pdevs_lock);
+
+	entry = __pdev_lookup(&child_pdevs, dev);
+	if (entry) {
+		list_del(&entry->node);
+		kfree(entry);
+		status = 0;
+		child_pdevs_count--;
+	}
+
+	spin_unlock(&child_pdevs_lock);
+
+	if (status)
+		pr_err("Cannot unmap entry!\n");
+
+	return status;
+}
+
+static int pdev_lookup(struct device *dev,
+		       struct platform_device **ahci_pdev,
+		       struct platform_device **brcm_pdev)
+{
+	int status = -EFAULT;
+	struct pdev_map *entry;
+
+	spin_lock(&child_pdevs_lock);
+
+	entry = __pdev_lookup(&child_pdevs, dev);
+	if (entry) {
+		if (brcm_pdev)
+			*brcm_pdev = entry->brcm_pdev;
+		if (ahci_pdev)
+			*ahci_pdev = entry->ahci_pdev;
+		status = 0;
+	}
+
+	spin_unlock(&child_pdevs_lock);
+
+	if (status)
+		pr_err("Cannot locate map entry!\n");
+
+	return status;
+}
+
+static int brcm_sata3_init_config(void __iomem *ahci_regs,
+				  struct platform_device *ahci_pdev,
+				  struct sata_brcm_pdata *brcm_pdata,
+				  int ports)
+{
+	int i, status = 0;
+	void __iomem *top_regs = NULL;
+	u32 host_caps, port_ctrl;
+
+	top_regs = ioremap(brcm_pdata->top_ctrl_base_addr,
+			   SATA_TOP_CTRL_REG_LENGTH);
+	if (!top_regs) {
+		status = -EFAULT;
+		goto done;
+	}
+
+	/* Enable support for ALPM */
+	writel(SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT,
+		top_regs + SATA_TOP_CTRL_BUS_CTRL);
+	host_caps = readl(ahci_regs + HOST_CAP);
+	writel(host_caps | HOST_CAP_ALPM, ahci_regs + HOST_CAP);
+
+	/* Configure endianness */
+	writel((DATA_ENDIAN << 4) | (DATA_ENDIAN << 2) | (MMIO_ENDIAN << 0),
+		top_regs + SATA_TOP_CTRL_BUS_CTRL);
+
+	/*
+	 * Adjust timeout to allow PLL sufficient time to lock while waking
+	 * up from slumber mode.
+	 */
+	for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL; i < ports;
+	     i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET)
+		writel(0xff1003fc, ahci_regs + SATA_PORT_PCTRL6(port_ctrl));
+done:
+	if (top_regs)
+		iounmap(top_regs);
+
+	return status;
+}
+
+static void clk_cfg(struct platform_device *brcm_pdev, int enable)
+{
+	int status = 0;
+	struct sata_brcm_pdata *brcm_pdata = brcm_pdev->dev.platform_data;
+
+	if (!brcm_pdata->sata_clk) {
+		brcm_pdata->sata_clk = clk_get(&brcm_pdev->dev, "sw_sata3");
+		if (IS_ERR(brcm_pdata->sata_clk)) {
+			brcm_pdata->sata_clk = NULL;
+			pr_debug("failed to get sata clock\n");
+			return;
+		}
+	}
+
+	if (enable) {
+		status = clk_prepare_enable(brcm_pdata->sata_clk);
+		if (status)
+			pr_err("sata clk enable failed\n");
+	} else
+		clk_disable_unprepare(brcm_pdata->sata_clk);
+}
+
+static int brcm_sata3_cfg(struct device *dev, void __iomem *addr, int init)
+{
+	int status = 0;
+	int i;
+	int ports;
+	struct platform_device *brcm_pdev = NULL;
+	struct platform_device *ahci_pdev = NULL;
+	struct sata_brcm_pdata *brcm_pdata = NULL;
+
+	status = pdev_lookup(dev, &ahci_pdev, &brcm_pdev);
+	if (status) {
+		pr_err("Cannot locate matching platform device!\n");
+		goto done;
+	}
+
+	if (init)
+		clk_cfg(brcm_pdev, 1);
+
+	brcm_pdata = brcm_pdev->dev.platform_data;
+	ports = fls(readl(addr + HOST_PORTS_IMPL));
+
+	if (init) {
+		status = brcm_sata3_init_config(addr, ahci_pdev,
+						brcm_pdata, ports);
+		if (status)
+			goto done;
+	}
+
+	for (i = 0; i < ports; i++)
+		brcm_sata3_phy_cfg(brcm_pdata, i, init);
+
+	if (!init)
+		clk_cfg(brcm_pdev, 0);
+
+done:
+	return status;
+}
+
+static int brcm_ahci_init(struct device *dev, void __iomem *addr)
+{
+	return brcm_sata3_cfg(dev, addr, 1);
+}
+
+static void brcm_ahci_exit(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *addr = hpriv->mmio;
+
+	brcm_sata3_cfg(dev, addr, 0);
+}
+
+static int brcm_ahci_suspend(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *addr = hpriv->mmio;
+
+	return brcm_sata3_cfg(dev, addr, 0);
+}
+
+static int brcm_ahci_resume(struct device *dev)
+{
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	void __iomem *addr = hpriv->mmio;
+
+	return brcm_sata3_cfg(dev, addr, 1);
+}
+
+static int brcm_ahci_parse_dt_prop_u32(struct device_node *of_node,
+				       const char *propname, u32 *dst)
+{
+	int status = 0;
+	int tmp;
+
+	if (!of_property_read_u32(of_node, propname, &tmp)) {
+		pr_debug("%s = %xh\n", propname, tmp);
+		*dst = tmp;
+	} else {
+		pr_err("Missing %s property!\n", propname);
+		status = -EFAULT;
+	}
+
+	return status;
+}
+
+static int brcm_ahci_parse_dt_node(struct platform_device *pdev)
+{
+	int status = 0;
+	struct sata_brcm_pdata *brcm_pdata = pdev->dev.platform_data;
+	struct device_node *of_node = pdev->dev.of_node;
+
+	/* MANDATORY */
+	status = brcm_ahci_parse_dt_prop_u32(of_node, "phy-generation",
+					     &brcm_pdata->phy_generation);
+	if (status)
+		goto err;
+
+	/* MANDATORY */
+	status = brcm_ahci_parse_dt_prop_u32(of_node, "phy-base-addr",
+					     &brcm_pdata->phy_base_addr);
+	if (status)
+		goto err;
+
+	/* MANDATORY */
+	status = brcm_ahci_parse_dt_prop_u32(of_node, "top-ctrl-base-addr",
+					     &brcm_pdata->top_ctrl_base_addr);
+	if (status)
+		goto err;
+
+	/* OPTIONAL */
+	status = brcm_ahci_parse_dt_prop_u32(of_node, "phy-enable-ssc-mask",
+					     &brcm_pdata->phy_enable_ssc_mask);
+	if (status)
+		brcm_pdata->phy_enable_ssc_mask = 0;
+
+err:
+	return status;
+}
+
+static int setup_ahci_pdata(struct platform_device *pdev,
+	struct ahci_platform_data *ahci_pd)
+{
+	int status = 0;
+
+	memset(ahci_pd, 0, sizeof(*ahci_pd));
+	ahci_pd->init = &brcm_ahci_init;
+	ahci_pd->exit = &brcm_ahci_exit;
+	ahci_pd->suspend = &brcm_ahci_suspend;
+	ahci_pd->resume = &brcm_ahci_resume;
+
+	return status;
+}
+
+static int brcm_ahci_probe(struct platform_device *pdev)
+{
+	int status;
+	int mapped = 0;
+	struct platform_device *ahci_pdev = NULL;
+	struct sata_brcm_pdata brcm_pdata;
+	struct ahci_platform_data ahci_pdata;
+	static u64 brcm_ahci_dmamask = DMA_BIT_MASK(64);
+
+	ahci_pdev = platform_device_alloc("brcmstb-ahci", child_pdevs_count);
+	if (ahci_pdev == NULL) {
+		pr_err("Cannot allocate AHCI platform device!\n");
+		status = -ENOMEM;
+		goto err_cleanup;
+	}
+
+	memset(&brcm_pdata, 0, sizeof(struct sata_brcm_pdata));
+
+	/*
+	 * Configure the Broadcom AHCI wrapper
+	 */
+
+	/* Keep reference to the "child" platform device */
+	brcm_pdata.ahci_pdev = ahci_pdev;
+
+	status = platform_device_add_data(pdev, &brcm_pdata,
+					  sizeof(struct sata_brcm_pdata));
+	if (status)
+		goto err_cleanup;
+
+	status = brcm_ahci_parse_dt_node(pdev);
+	if (status)
+		goto err_cleanup;
+	/*
+	 * Configure the platform AHCI device
+	 */
+	status = setup_ahci_pdata(pdev, &ahci_pdata);
+	if (status)
+		goto err_cleanup;
+
+	status = platform_device_add_data(ahci_pdev, &ahci_pdata,
+					  sizeof(struct ahci_platform_data));
+	if (status)
+		goto err_cleanup;
+
+	/* Pass the register addresses over to the AHCI platform device */
+	status = platform_device_add_resources(ahci_pdev,
+					       pdev->resource,
+					       pdev->num_resources);
+	if (status)
+		goto err_cleanup;
+
+	ahci_pdev->dev.dma_mask = &brcm_ahci_dmamask;
+	ahci_pdev->dev.coherent_dma_mask = brcm_ahci_dmamask;
+
+	status = pdev_map(&ahci_pdev->dev, ahci_pdev, pdev);
+	if (status)
+		goto err_cleanup;
+	else
+		mapped = 1;
+
+	/* Ready to handoff configuration to platform AHCI driver */
+	status = platform_device_add(ahci_pdev);
+	if (status)
+		goto err_cleanup;
+
+	goto done;
+
+err_cleanup:
+	if (mapped)
+		pdev_unmap(&ahci_pdev->dev);
+
+	if (ahci_pdev != NULL)
+		platform_device_put(ahci_pdev);
+
+done:
+	return status;
+}
+
+static int brcm_ahci_remove(struct platform_device *pdev)
+{
+	struct sata_brcm_pdata *brcm_pdata = pdev->dev.platform_data;
+	struct platform_device *ahci_pdev = brcm_pdata->ahci_pdev;
+
+	if (ahci_pdev) {
+		pdev_unmap(&ahci_pdev->dev);
+		platform_device_unregister(brcm_pdata->ahci_pdev);
+	}
+
+	kfree(brcm_pdata);
+	pdev->dev.platform_data = NULL;
+
+	return 0;
+}
+
+static const struct of_device_id ahci_of_match[] = {
+	{.compatible = "brcm,sata3-ahci"},
+	{},
+};
+
+static struct platform_driver brcm_ahci_driver = {
+	.probe = brcm_ahci_probe,
+	.remove = brcm_ahci_remove,
+	.driver = {
+		.name = "brcm-ahci",
+		.owner = THIS_MODULE,
+		.of_match_table = ahci_of_match,
+	},
+};
+module_platform_driver(brcm_ahci_driver);
+
+MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
+MODULE_AUTHOR("Marc Carino <mcarino@broadcom.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sata-brcmstb");
+MODULE_DEVICE_TABLE(of, ahci_of_match);
diff --git a/drivers/ata/sata_brcmstb.h b/drivers/ata/sata_brcmstb.h
new file mode 100644
index 000000000000..e7a166774772
--- /dev/null
+++ b/drivers/ata/sata_brcmstb.h
@@ -0,0 +1,124 @@
+/*
+ *  sata_brcmstb.h - Broadcom SATA3 AHCI Controller Driver
+ *
+ *  Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __SATA_BRCMSTB_H__
+#define __SATA_BRCMSTB_H__
+
+#ifdef __BIG_ENDIAN
+#define DATA_ENDIAN			 2 /* AHCI->DDR inbound accesses */
+#define MMIO_ENDIAN			 2 /* CPU->AHCI outbound accesses */
+#else
+#define DATA_ENDIAN			 0
+#define MMIO_ENDIAN			 0
+#endif
+
+#define MAX_PORTS			32
+
+#define SATA_MDIO_BANK_OFFSET		0x23c
+#define SATA_MDIO_REG_OFFSET(ofs)	((ofs) * 4)
+#define SATA_MDIO_REG_SPACE_SIZE	0x1000
+#define SATA_MDIO_REG_LENGTH		0x1f00
+
+/* The older SATA PHY registers duplicated per port registers within the map,
+ * rather than having a separate map per port. */
+#define SATA_MDIO_REG_LEGACY_BANK_OFS	0x10
+
+#define MAX_PHY_CTRL_PORTS			2
+#define SATA_TOP_CTRL_REG_LENGTH		0x24
+#define SATA_TOP_CTRL_BUS_CTRL			0x4
+#define SATA_TOP_CTRL_PHY_CTRL_OFS		0xc
+#define SATA_TOP_CTRL_PHY_CTRL_LEN		0x8
+#define SATA_TOP_CTRL_PHY_CTRL_1		0x0
+#define SATA_TOP_CTRL_PHY_CTRL_2		0x4
+#define SATA_TOP_CTRL_REGS_PER_PORT		2
+#define SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT	BIT(16)
+#define SATA_TOP_CTRL_2_SW_RST_MDIOREG		BIT(0)
+#define SATA_TOP_CTRL_2_SW_RST_OOB		BIT(1)
+#define SATA_TOP_CTRL_2_SW_RST_RX		BIT(2)
+#define SATA_TOP_CTRL_2_SW_RST_TX		BIT(3)
+#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET	BIT(14)
+#define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE	BIT(14)
+
+#define SATA_FIRST_PORT_CTRL		0x700
+#define SATA_NEXT_PORT_CTRL_OFFSET	0x80
+#define SATA_PORT_PCTRL6(reg_base)	(reg_base + 0x18)
+
+enum sata_mdio_phy_regs_28nm {
+	PLL_REG_BANK_0 = 0x50,
+	PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
+	TXPMD_REG_BANK = 0x1a0,
+	TXPMD_CONTROL1 = 0x81,
+	TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
+	TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
+	TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
+	TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
+	TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
+	TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
+	TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
+};
+
+enum sata_mdio_phy_regs_legacy {
+	TXPMD_REG_BANK_LEGACY = 0x1a0,
+};
+
+/**
+ * struct pdev_map - Doubly-linked list used to associate a struct device
+ *                     its associated platform devices.
+ * @node: Forward/reverse links
+ * @key: A pointer to a device struct
+ * @brcm_pdev: The Broadcom SATA AHCI platform_device associated with the key
+ * @ahci_pdev: The AHCI platform_device associated with the key
+ */
+struct pdev_map {
+	struct list_head node;
+	struct device *key;
+	struct platform_device *brcm_pdev;
+	struct platform_device *ahci_pdev;
+};
+
+/*
+ * struct sata_brcm_pdata - Platform data for the Broadcom SATA AHCI driver
+ *
+ * These fields are defined in the driver's DT binding documentation.
+ */
+struct sata_brcm_pdata {
+	struct platform_device *ahci_pdev;
+	u32 phy_generation;
+	u32 phy_base_addr;
+	u32 phy_enable_ssc_mask;
+	u32 top_ctrl_base_addr;
+	u32 quirks;
+	struct clk *sata_clk;
+};
+
+struct sata_phy_cfg_ops {
+	void (*cfg_ssc)(void __iomem *base, int port, int ssc_en);
+};
+
+enum sata_phy_mdio_gen {
+	SATA_PHY_MDIO_LEGACY = 0,
+	SATA_PHY_MDIO_28NM,
+	SATA_PHY_MDIO_END,
+};
+
+void brcm_sata3_phy_cfg(const struct sata_brcm_pdata *pdata, int port,
+			int enable);
+
+#endif /* __SATA_BRCMSTB_H__ */
diff --git a/drivers/ata/sata_brcmstb_phy.c b/drivers/ata/sata_brcmstb_phy.c
new file mode 100644
index 000000000000..7171103e717c
--- /dev/null
+++ b/drivers/ata/sata_brcmstb_phy.c
@@ -0,0 +1,240 @@
+/*
+ *  sata_brcmstb_phy.c - Broadcom SATA3 AHCI Controller PHY Driver
+ *
+ *  Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define pr_fmt(fmt) "brcm-sata3-phy: " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/libata.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <scsi/scsi_host.h>
+
+#include "sata_brcmstb.h"
+#include "ahci.h"
+
+static void sata_mdio_wr_28nm(void __iomem *addr, u32 port, u32 bank, u32 ofs,
+			      u32 msk, u32 value)
+{
+	u32 tmp;
+	void __iomem *base = addr + (port * SATA_MDIO_REG_SPACE_SIZE);
+
+	writel(bank, base + SATA_MDIO_BANK_OFFSET);
+	tmp = readl(base + SATA_MDIO_REG_OFFSET(ofs));
+	tmp = (tmp & msk) | value;
+	writel(tmp, base + SATA_MDIO_REG_OFFSET(ofs));
+}
+
+static void sata_mdio_wr_legacy(void __iomem *addr, u32 port, u32 bank, u32 ofs,
+				u32 msk, u32 value)
+{
+	u32 tmp;
+	u32 bank_port = bank + (port * SATA_MDIO_REG_LEGACY_BANK_OFS);
+
+	writel(bank_port, addr + SATA_MDIO_BANK_OFFSET);
+	tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
+	tmp = (tmp & msk) | value;
+	writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
+}
+
+/* These defaults were characterized by H/W group */
+#define FMIN_VAL_DEFAULT 0x3df
+#define FMAX_VAL_DEFAULT 0x3df
+#define FMAX_VAL_SSC 0x83
+
+static void cfg_ssc_28nm(void __iomem *base, int port, int ssc_en)
+{
+	u32 tmp;
+
+	/* override the TX spread spectrum setting */
+	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
+	sata_mdio_wr_28nm(base, port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp,
+		tmp);
+
+	/* set fixed min freq */
+	sata_mdio_wr_28nm(base, port, TXPMD_REG_BANK,
+		TXPMD_TX_FREQ_CTRL_CONTROL2,
+		~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
+		FMIN_VAL_DEFAULT);
+
+	/* set fixed max freq depending on SSC config */
+	if (ssc_en) {
+		pr_info("Enabling SSC on port %d\n", port);
+		tmp = FMAX_VAL_SSC;
+	} else
+		tmp = FMAX_VAL_DEFAULT;
+
+	sata_mdio_wr_28nm(base, port, TXPMD_REG_BANK,
+		TXPMD_TX_FREQ_CTRL_CONTROL3,
+		~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
+}
+
+static void cfg_ssc_legacy(void __iomem *base, int port, int ssc_en)
+{
+	u32 tmp;
+
+	/* override the TX spread spectrum setting */
+	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
+	sata_mdio_wr_legacy(base, port, TXPMD_REG_BANK_LEGACY, TXPMD_CONTROL1,
+		~tmp, tmp);
+
+	/* set fixed min freq */
+	sata_mdio_wr_legacy(base, port, TXPMD_REG_BANK_LEGACY,
+		TXPMD_TX_FREQ_CTRL_CONTROL2,
+		~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
+		FMIN_VAL_DEFAULT);
+
+	/* set fixed max freq depending on SSC config */
+	if (ssc_en) {
+		pr_info("Enabling SSC on port %d\n", port);
+		tmp = FMAX_VAL_SSC;
+	} else
+		tmp = FMAX_VAL_DEFAULT;
+
+	sata_mdio_wr_legacy(base, port, TXPMD_REG_BANK_LEGACY,
+		TXPMD_TX_FREQ_CTRL_CONTROL3,
+		~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
+}
+
+static struct sata_phy_cfg_ops cfg_op_tbl[SATA_PHY_MDIO_END] = {
+	[SATA_PHY_MDIO_LEGACY] = {
+		.cfg_ssc = cfg_ssc_legacy,
+	},
+	[SATA_PHY_MDIO_28NM] = {
+		.cfg_ssc = cfg_ssc_28nm,
+	},
+};
+
+static struct sata_phy_cfg_ops *cfg_op;
+
+static void _brcm_sata3_phy_cfg(const struct sata_brcm_pdata *pdata, int port,
+			       int enable)
+{
+	/* yfzhang@broadcom.com has stated that the core will only have (2)
+	 * ports. Further, the RDB currently lacks documentation for these
+	 * registers. So just keep a map of which port corresponds to these
+	 * magic registers.
+	 */
+	const u32 port_to_phy_ctrl_ofs[MAX_PHY_CTRL_PORTS] = {
+		SATA_TOP_CTRL_PHY_CTRL_OFS + (0 * SATA_TOP_CTRL_PHY_CTRL_LEN),
+		SATA_TOP_CTRL_PHY_CTRL_OFS + (1 * SATA_TOP_CTRL_PHY_CTRL_LEN),
+	};
+	void __iomem *top_ctrl;
+
+	top_ctrl = ioremap(pdata->top_ctrl_base_addr, SATA_TOP_CTRL_REG_LENGTH);
+	if (!top_ctrl) {
+		pr_err("failed to ioremap SATA top ctrl regs\n");
+		return;
+	}
+
+	if (port < MAX_PHY_CTRL_PORTS) {
+		void __iomem *p;
+		u32 reg;
+
+		if (enable) {
+			/* clear PHY_DEFAULT_POWER_STATE */
+			p = top_ctrl + port_to_phy_ctrl_ofs[port] +
+				SATA_TOP_CTRL_PHY_CTRL_1;
+			reg = readl(p);
+			reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
+			writel(reg, p);
+
+			/* reset the PHY digital logic */
+			p = top_ctrl + port_to_phy_ctrl_ofs[port] +
+				SATA_TOP_CTRL_PHY_CTRL_2;
+			reg = readl(p);
+			reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG |
+				 SATA_TOP_CTRL_2_SW_RST_OOB |
+				 SATA_TOP_CTRL_2_SW_RST_RX);
+			reg |= SATA_TOP_CTRL_2_SW_RST_TX;
+			writel(reg, p);
+			reg = readl(p);
+			reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
+			writel(reg, p);
+			reg = readl(p);
+			reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
+			writel(reg, p);
+			reg = readl(p);
+		} else {
+			/* power-off the PHY digital logic */
+			p = top_ctrl + port_to_phy_ctrl_ofs[port] +
+				SATA_TOP_CTRL_PHY_CTRL_2;
+			reg = readl(p);
+			reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG |
+				SATA_TOP_CTRL_2_SW_RST_OOB |
+				SATA_TOP_CTRL_2_SW_RST_RX |
+				SATA_TOP_CTRL_2_SW_RST_TX |
+				SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
+			writel(reg, p);
+
+			/* set PHY_DEFAULT_POWER_STATE */
+			p = top_ctrl + port_to_phy_ctrl_ofs[port] +
+				SATA_TOP_CTRL_PHY_CTRL_1;
+			reg = readl(p);
+			reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
+			writel(reg, p);
+		}
+	}
+
+	iounmap(top_ctrl);
+}
+
+void brcm_sata3_phy_cfg(const struct sata_brcm_pdata *pdata, int port,
+			int enable)
+{
+	const u32 phy_base = pdata->phy_base_addr;
+	const int ssc_enable = pdata->phy_enable_ssc_mask & (1 << port);
+	void __iomem *base;
+
+	base = ioremap(phy_base, SATA_MDIO_REG_LENGTH);
+	if (!base) {
+		pr_err("%s: Failed to ioremap PHY registers!\n", __func__);
+		goto err;
+	}
+
+	if (pdata->phy_generation == 0x2800)
+		cfg_op = &cfg_op_tbl[SATA_PHY_MDIO_28NM];
+	else
+		cfg_op = &cfg_op_tbl[SATA_PHY_MDIO_LEGACY];
+
+	if (enable) {
+		_brcm_sata3_phy_cfg(pdata, port, 1);
+		if (cfg_op->cfg_ssc)
+			cfg_op->cfg_ssc(base, port, ssc_enable);
+	} else
+		_brcm_sata3_phy_cfg(pdata, port, 0);
+
+	iounmap(base);
+
+err:
+	return;
+}
+EXPORT_SYMBOL(brcm_sata3_phy_cfg);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index ec36e7772e57..37cfb331952c 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -208,6 +208,9 @@ config DMA_CMA
 	  to allocate big physically-contiguous blocks of memory for use with
 	  hardware components that do not support I/O map nor scatter-gather.
 
+	  You can disable CMA by specifying "cma=0" on the kernel's command
+	  line.
+
 	  For more information see <include/linux/dma-contiguous.h>.
 	  If unsure, say "n".
 
@@ -250,7 +253,7 @@ endchoice
 
 config CMA_ALIGNMENT
 	int "Maximum PAGE_SIZE order of alignment for contiguous buffers"
-	range 4 9
+	range 4 12
 	default 8
 	help
 	  DMA mapping framework by default aligns all buffers to the smallest
@@ -266,16 +269,6 @@ config CMA_ALIGNMENT
 
 	  If unsure, leave the default value "8".
 
-config CMA_AREAS
-	int "Maximum count of the CMA device-private areas"
-	default 7
-	help
-	  CMA allows to create CMA areas for particular devices. This parameter
-	  sets the maximum number of such device private CMA areas in the
-	  system.
-
-	  If unsure, leave the default value "7".
-
 endif
 
 endmenu
diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
index d3bffa478eca..473ff4892401 100644
--- a/drivers/base/dma-contiguous.c
+++ b/drivers/base/dma-contiguous.c
@@ -24,22 +24,9 @@
 
 #include <linux/memblock.h>
 #include <linux/err.h>
-#include <linux/mm.h>
-#include <linux/mutex.h>
-#include <linux/page-isolation.h>
 #include <linux/sizes.h>
-#include <linux/slab.h>
-#include <linux/swap.h>
-#include <linux/mm_types.h>
 #include <linux/dma-contiguous.h>
-
-struct cma {
-	unsigned long	base_pfn;
-	unsigned long	count;
-	unsigned long	*bitmap;
-};
-
-struct cma *dma_contiguous_default_area;
+#include <linux/cma.h>
 
 #ifdef CONFIG_CMA_SIZE_MBYTES
 #define CMA_SIZE_MBYTES CONFIG_CMA_SIZE_MBYTES
@@ -47,6 +34,8 @@ struct cma *dma_contiguous_default_area;
 #define CMA_SIZE_MBYTES 0
 #endif
 
+struct cma *dma_contiguous_default_area;
+
 /*
  * Default global CMA area size can be defined in kernel's .config.
  * This is useful mainly for distro maintainers to create a kernel
@@ -59,11 +48,22 @@ struct cma *dma_contiguous_default_area;
  */
 static const phys_addr_t size_bytes = CMA_SIZE_MBYTES * SZ_1M;
 static phys_addr_t size_cmdline = -1;
+static phys_addr_t base_cmdline;
+static phys_addr_t limit_cmdline;
 
 static int __init early_cma(char *p)
 {
 	pr_debug("%s(%s)\n", __func__, p);
 	size_cmdline = memparse(p, &p);
+	if (*p != '@')
+		return 0;
+	base_cmdline = memparse(p + 1, &p);
+	if (*p != '-') {
+		limit_cmdline = base_cmdline + size_cmdline;
+		return 0;
+	}
+	limit_cmdline = memparse(p + 1, &p);
+
 	return 0;
 }
 early_param("cma", early_cma);
@@ -107,11 +107,18 @@ static inline __maybe_unused phys_addr_t cma_early_percent_memory(void)
 void __init dma_contiguous_reserve(phys_addr_t limit)
 {
 	phys_addr_t selected_size = 0;
+	phys_addr_t selected_base = 0;
+	phys_addr_t selected_limit = limit;
+	bool fixed = false;
 
 	pr_debug("%s(limit %08lx)\n", __func__, (unsigned long)limit);
 
 	if (size_cmdline != -1) {
 		selected_size = size_cmdline;
+		selected_base = base_cmdline;
+		selected_limit = min_not_zero(limit_cmdline, limit);
+		if (base_cmdline + size_cmdline == limit_cmdline)
+			fixed = true;
 	} else {
 #ifdef CONFIG_CMA_SIZE_SEL_MBYTES
 		selected_size = size_bytes;
@@ -128,147 +135,45 @@ void __init dma_contiguous_reserve(phys_addr_t limit)
 		pr_debug("%s: reserving %ld MiB for global area\n", __func__,
 			 (unsigned long)selected_size / SZ_1M);
 
-		dma_contiguous_reserve_area(selected_size, 0, limit,
-					    &dma_contiguous_default_area);
+		dma_contiguous_reserve_area(selected_size, selected_base,
+					    selected_limit,
+					    &dma_contiguous_default_area,
+					    fixed);
 	}
-};
-
-static DEFINE_MUTEX(cma_mutex);
-
-static int __init cma_activate_area(struct cma *cma)
-{
-	int bitmap_size = BITS_TO_LONGS(cma->count) * sizeof(long);
-	unsigned long base_pfn = cma->base_pfn, pfn = base_pfn;
-	unsigned i = cma->count >> pageblock_order;
-	struct zone *zone;
-
-	cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-
-	if (!cma->bitmap)
-		return -ENOMEM;
-
-	WARN_ON_ONCE(!pfn_valid(pfn));
-	zone = page_zone(pfn_to_page(pfn));
-
-	do {
-		unsigned j;
-		base_pfn = pfn;
-		for (j = pageblock_nr_pages; j; --j, pfn++) {
-			WARN_ON_ONCE(!pfn_valid(pfn));
-			/*
-			 * alloc_contig_range requires the pfn range
-			 * specified to be in the same zone. Make this
-			 * simple by forcing the entire CMA resv range
-			 * to be in the same zone.
-			 */
-			if (page_zone(pfn_to_page(pfn)) != zone)
-				goto err;
-		}
-		init_cma_reserved_pageblock(pfn_to_page(base_pfn));
-	} while (--i);
-
-	return 0;
-
-err:
-	kfree(cma->bitmap);
-	return -EINVAL;
 }
 
-static struct cma cma_areas[MAX_CMA_AREAS];
-static unsigned cma_area_count;
-
-static int __init cma_init_reserved_areas(void)
-{
-	int i;
-
-	for (i = 0; i < cma_area_count; i++) {
-		int ret = cma_activate_area(&cma_areas[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-core_initcall(cma_init_reserved_areas);
-
 /**
  * dma_contiguous_reserve_area() - reserve custom contiguous area
  * @size: Size of the reserved area (in bytes),
  * @base: Base address of the reserved area optional, use 0 for any
  * @limit: End address of the reserved memory (optional, 0 for any).
  * @res_cma: Pointer to store the created cma region.
+ * @fixed: hint about where to place the reserved area
  *
  * This function reserves memory from early allocator. It should be
  * called by arch specific code once the early allocator (memblock or bootmem)
  * has been activated and all other subsystems have already allocated/reserved
  * memory. This function allows to create custom reserved areas for specific
  * devices.
+ *
+ * If @fixed is true, reserve contiguous area at exactly @base.  If false,
+ * reserve in range from @base to @limit.
  */
 int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
-				       phys_addr_t limit, struct cma **res_cma)
+				       phys_addr_t limit, struct cma **res_cma,
+				       bool fixed)
 {
-	struct cma *cma = &cma_areas[cma_area_count];
-	phys_addr_t alignment;
-	int ret = 0;
-
-	pr_debug("%s(size %lx, base %08lx, limit %08lx)\n", __func__,
-		 (unsigned long)size, (unsigned long)base,
-		 (unsigned long)limit);
-
-	/* Sanity checks */
-	if (cma_area_count == ARRAY_SIZE(cma_areas)) {
-		pr_err("Not enough slots for CMA reserved regions!\n");
-		return -ENOSPC;
-	}
-
-	if (!size)
-		return -EINVAL;
-
-	/* Sanitise input arguments */
-	alignment = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
-	base = ALIGN(base, alignment);
-	size = ALIGN(size, alignment);
-	limit &= ~(alignment - 1);
-
-	/* Reserve memory */
-	if (base) {
-		if (memblock_is_region_reserved(base, size) ||
-		    memblock_reserve(base, size) < 0) {
-			ret = -EBUSY;
-			goto err;
-		}
-	} else {
-		/*
-		 * Use __memblock_alloc_base() since
-		 * memblock_alloc_base() panic()s.
-		 */
-		phys_addr_t addr = __memblock_alloc_base(size, alignment, limit);
-		if (!addr) {
-			ret = -ENOMEM;
-			goto err;
-		} else {
-			base = addr;
-		}
-	}
-
-	/*
-	 * Each reserved area must be initialised later, when more kernel
-	 * subsystems (like slab allocator) are available.
-	 */
-	cma->base_pfn = PFN_DOWN(base);
-	cma->count = size >> PAGE_SHIFT;
-	*res_cma = cma;
-	cma_area_count++;
+	int ret;
 
-	pr_info("CMA: reserved %ld MiB at %08lx\n", (unsigned long)size / SZ_1M,
-		(unsigned long)base);
+	ret = cma_declare_contiguous(base, size, limit, 0, 0, fixed, res_cma);
+	if (ret)
+		return ret;
 
 	/* Architecture specific contiguous memory fixup. */
-	dma_contiguous_early_fixup(base, size);
+	dma_contiguous_early_fixup(cma_get_base(*res_cma),
+				cma_get_size(*res_cma));
+
 	return 0;
-err:
-	pr_err("CMA: failed to reserve %ld MiB\n", (unsigned long)size / SZ_1M);
-	return ret;
 }
 
 /**
@@ -279,57 +184,16 @@ err:
  *
  * This function allocates memory buffer for specified device. It uses
  * device specific contiguous memory area if available or the default
- * global one. Requires architecture specific get_dev_cma_area() helper
+ * global one. Requires architecture specific dev_get_cma_area() helper
  * function.
  */
 struct page *dma_alloc_from_contiguous(struct device *dev, int count,
 				       unsigned int align)
 {
-	unsigned long mask, pfn, pageno, start = 0;
-	struct cma *cma = dev_get_cma_area(dev);
-	struct page *page = NULL;
-	int ret;
-
-	if (!cma || !cma->count)
-		return NULL;
-
 	if (align > CONFIG_CMA_ALIGNMENT)
 		align = CONFIG_CMA_ALIGNMENT;
 
-	pr_debug("%s(cma %p, count %d, align %d)\n", __func__, (void *)cma,
-		 count, align);
-
-	if (!count)
-		return NULL;
-
-	mask = (1 << align) - 1;
-
-	mutex_lock(&cma_mutex);
-
-	for (;;) {
-		pageno = bitmap_find_next_zero_area(cma->bitmap, cma->count,
-						    start, count, mask);
-		if (pageno >= cma->count)
-			break;
-
-		pfn = cma->base_pfn + pageno;
-		ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
-		if (ret == 0) {
-			bitmap_set(cma->bitmap, pageno, count);
-			page = pfn_to_page(pfn);
-			break;
-		} else if (ret != -EBUSY) {
-			break;
-		}
-		pr_debug("%s(): memory range at %p is busy, retrying\n",
-			 __func__, pfn_to_page(pfn));
-		/* try again with a bit different memory target */
-		start = pageno + mask + 1;
-	}
-
-	mutex_unlock(&cma_mutex);
-	pr_debug("%s(): returned %p\n", __func__, page);
-	return page;
+	return cma_alloc(dev_get_cma_area(dev), count, align);
 }
 
 /**
@@ -345,25 +209,71 @@ struct page *dma_alloc_from_contiguous(struct device *dev, int count,
 bool dma_release_from_contiguous(struct device *dev, struct page *pages,
 				 int count)
 {
-	struct cma *cma = dev_get_cma_area(dev);
-	unsigned long pfn;
+	return cma_release(dev_get_cma_area(dev), pages, count);
+}
+
+/*
+ * Support for reserved memory regions defined in device tree
+ */
+#ifdef CONFIG_OF_RESERVED_MEM
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_reserved_mem.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) fmt
+
+static void rmem_cma_device_init(struct reserved_mem *rmem, struct device *dev)
+{
+	dev_set_cma_area(dev, rmem->priv);
+}
 
-	if (!cma || !pages)
-		return false;
+static void rmem_cma_device_release(struct reserved_mem *rmem,
+				    struct device *dev)
+{
+	dev_set_cma_area(dev, NULL);
+}
 
-	pr_debug("%s(page %p)\n", __func__, (void *)pages);
+static const struct reserved_mem_ops rmem_cma_ops = {
+	.device_init	= rmem_cma_device_init,
+	.device_release = rmem_cma_device_release,
+};
 
-	pfn = page_to_pfn(pages);
+static int __init rmem_cma_setup(struct reserved_mem *rmem)
+{
+	phys_addr_t align = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+	phys_addr_t mask = align - 1;
+	unsigned long node = rmem->fdt_node;
+	struct cma *cma;
+	int err;
+
+	if (!of_get_flat_dt_prop(node, "reusable", NULL) ||
+	    of_get_flat_dt_prop(node, "no-map", NULL))
+		return -EINVAL;
 
-	if (pfn < cma->base_pfn || pfn >= cma->base_pfn + cma->count)
-		return false;
+	if ((rmem->base & mask) || (rmem->size & mask)) {
+		pr_err("Reserved memory: incorrect alignment of CMA region\n");
+		return -EINVAL;
+	}
+
+	err = cma_init_reserved_mem(rmem->base, rmem->size, 0, &cma);
+	if (err) {
+		pr_err("Reserved memory: unable to setup CMA region\n");
+		return err;
+	}
+	/* Architecture specific contiguous memory fixup. */
+	dma_contiguous_early_fixup(rmem->base, rmem->size);
 
-	VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
+	if (of_get_flat_dt_prop(node, "linux,cma-default", NULL))
+		dma_contiguous_set_default(cma);
 
-	mutex_lock(&cma_mutex);
-	bitmap_clear(cma->bitmap, pfn - cma->base_pfn, count);
-	free_contig_range(pfn, count);
-	mutex_unlock(&cma_mutex);
+	rmem->ops = &rmem_cma_ops;
+	rmem->priv = cma;
 
-	return true;
+	pr_info("Reserved memory: created CMA memory pool at %pa, size %ld MiB\n",
+		&rmem->base, (unsigned long)rmem->size / SZ_1M);
+
+	return 0;
 }
+RESERVEDMEM_OF_DECLARE(cma, "shared-dma-pool", rmem_cma_setup);
+#endif
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index 4251570610c9..d74064af977f 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -23,3 +23,7 @@ config REGMAP_MMIO
 
 config REGMAP_IRQ
 	bool
+
+config REGMAP_DFS
+	bool
+	depends on REGMAP && DEBUG_FS
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index a7c670b4123a..642b9b7f6c1b 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -1,6 +1,6 @@
 obj-$(CONFIG_REGMAP) += regmap.o regcache.o
 obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o regcache-flat.o
-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o
+obj-$(CONFIG_REGMAP_DFS) += regmap-debugfs.o
 obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
 obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
 obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o
diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h
index 33414b1de201..25047e5f9752 100644
--- a/drivers/base/regmap/internal.h
+++ b/drivers/base/regmap/internal.h
@@ -185,7 +185,7 @@ struct regmap_field {
 	unsigned int id_offset;
 };
 
-#ifdef CONFIG_DEBUG_FS
+#ifdef CONFIG_REGMAP_DFS
 extern void regmap_debugfs_initcall(void);
 extern void regmap_debugfs_init(struct regmap *map, const char *name);
 extern void regmap_debugfs_exit(struct regmap *map);
diff --git a/drivers/brcmstb/Kconfig b/drivers/brcmstb/Kconfig
new file mode 100644
index 000000000000..30ac51075223
--- /dev/null
+++ b/drivers/brcmstb/Kconfig
@@ -0,0 +1,1241 @@
+menu "Broadcom STB options"
+	depends on BRCMSTB
+
+
+#####################################################################
+# User options: Chipset selection
+#####################################################################
+
+
+config BRCM_LEGACY
+	bool "Enable legacy platforms"
+	depends on BRCMSTB
+	default n
+	help
+	  Reserved for future use.  Say N.
+
+
+choice
+	prompt "Chipset selection"
+	depends on BRCMSTB
+	help
+	  Select the Broadcom chipset you are building for.
+
+config BCM7228A0
+	bool "7228 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7228
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7231B0
+	bool "7231 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7231
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7344B0
+	bool "7344 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7344
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_11_PLUS
+	select BRCM_HAS_MOCA_MIDRF
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7346B0
+	bool "7346 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7346
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_11_PLUS
+	select BRCM_HAS_MOCA_MIDRF
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7358A0
+	bool "7358 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7358
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V0
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7360A0
+	bool "7360 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7360
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7362A0
+	bool "7362 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7362
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550 if !DREAMBOX
+	select BRCM_UARTC_IS_16550 if !DREAMBOX
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_SATA3 if !DREAMBOX_DM520
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7425B0
+	bool "7425 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7425
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_PCIE
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN21
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_EDU
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_HAS_1GB_MEMC1
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7429B0
+	bool "7429 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7429
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN22
+	select BRCM_MOCA_ON_GENET_1
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_6
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_EDU
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7435B0
+	bool "7435 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7435
+	select BRCM_HAS_BMIPS5000
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_HAS_DUALCORE
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550 if !DREAMBOX
+	select BRCM_UARTC_IS_16550 if !DREAMBOX
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_PCIE
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_MOCA_20_GEN22
+	select BRCM_MOCA_ON_GENET_1 if !DREAMBOX
+	select BRCM_GENET_V3
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_6
+	select BRCM_HAS_NAND_MINOR_2
+	#select BRCM_HAS_EDU
+	select BRCM_HAS_FLASH_DMA
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_2GB_MEMC0
+	select BRCM_HAS_1GB_MEMC1
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7543A0
+	bool "7543 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7543
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7552B0
+	bool "7552 Bx"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7552
+	select BRCM_HAS_BMIPS3300
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+config BCM7563A0
+	bool "7563 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7563
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_GENET_V2
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_WKTMR
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+	select BRCM_HAS_UPPER_MEMORY
+
+config BCM7584A0
+	bool "7584 Ax"
+	depends on MIPS
+	select BRCM_MIPS_DEFAULTS
+	select BCM7584
+	select BRCM_HAS_BMIPS4380
+	select BRCM_HAS_XKS01
+	select BRCM_HAS_XI
+	select BRCM_UARTA_IS_16550
+	select BRCM_UARTB_IS_16550
+	select BRCM_UARTC_IS_16550
+	select BRCM_HAS_USB_CAPS
+	select BRCM_HAS_GENET_0
+	select BRCM_HAS_GENET_1
+	select BRCM_GENET_V2
+	select BRCM_HAS_NOR
+	select BRCM_HAS_NAND_MAJOR_5
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCM_HAS_SATA3
+	select BRCM_HAS_SDIO_V1
+	select BRCM_HAS_EMMC
+	select BRCM_HAS_WKTMR
+	select BRCM_HAS_UPPER_MEMORY
+	select BRCM_HAS_1GB_MEMC0
+	select BRCM_PWR_HANDSHAKE_V1
+	select BRCM_HAS_DIGITAL_DDR_PHY
+
+endchoice
+
+config DREAMBOX
+	bool "Dreambox"
+	select FB_CFB_COPYAREA
+	select FB_CFB_FILLRECT
+	select FB_CFB_IMAGEBLIT
+	select SND_PCM
+
+choice
+	prompt "Dreambox model selection"
+	depends on DREAMBOX
+
+config DREAMBOX_DM520
+	bool "Dreambox DM520"
+	depends on BCM7362A0
+
+config DREAMBOX_DM820
+	bool "Dreambox DM820"
+	depends on BCM7435B0
+
+config DREAMBOX_DM7080
+	bool "Dreambox DM7080"
+	depends on BCM7435B0
+
+endchoice
+
+#####################################################################
+# User options: Memory configuration
+#####################################################################
+
+
+comment "Memory map"
+
+
+config BRCM_UPPER_MEMORY
+	bool "Large (>256MB) memory support"
+	depends on BRCM_HAS_UPPER_MEMORY
+	select ARCH_SPARSEMEM_ENABLE
+	select BRCM_UPPER_768MB if BRCM_HAS_XKS01
+	default y
+	help
+	  Say Y to use a special mapping scheme to access the STB's
+	  upper memory (all RAM above 256MB).  This supports up to 512MB
+	  of ZONE_NORMAL memory on 65nm chips, and 1024MB of ZONE_NORMAL
+	  memory on 40nm chips.
+
+	  On chips where HIGHMEM is available, this option should remain
+	  enabled since it will maximize the amount of memory in ZONE_NORMAL.
+
+	  If this option is disabled, you will only be able to use the
+	  first 256MB of RAM on the system (without HIGHMEM).  HIGHMEM is
+	  not available on most STB chips.
+
+	  It is recommended that this option be used in conjuction with
+	  SPARSEMEM (Kernel type -> Memory model -> Sparse memory).
+	  SPARSEMEM conserves about 2MB by omitting the page tables for the
+	  memory hole.
+
+
+config BRCM_OVERRIDE_RAM_SIZE
+	bool "Override memory size detection"
+	depends on BRCMSTB && MIPS
+	default n
+	help
+	  Say Y to use a compile-time default rather than detecting the
+	  RAM size from strap options or reading it from the bootloader.
+
+	  If unsure, say N.
+
+
+config BRCM_FORCED_DRAM0_SIZE
+	int "RAM on primary DRAM controller (MB)"
+	depends on BRCM_OVERRIDE_RAM_SIZE
+	default 32
+	help
+	  How many megabytes of RAM are on the primary DRAM controller?
+
+config BRCM_FORCED_DRAM1_SIZE
+	int "RAM on secondary DRAM controller (MB)"
+	depends on BRCM_OVERRIDE_RAM_SIZE && BRCM_HAS_1GB_MEMC1
+	default 256
+	help
+	  How many megabytes of RAM are on the secondary DRAM controller?
+
+
+#####################################################################
+# User options: Onchip peripherals
+#####################################################################
+
+
+comment "Onchip peripherals"
+	depends on BRCMSTB
+
+
+config BRCM_CONSOLE_DEVICE
+	int "Default serial console device"
+	depends on BRCMSTB
+	default 0
+	range 0 2
+	help
+	  Default UART to use for console output.  This can be overridden with
+	  "console=" on the kernel command line.
+
+	   0 = /dev/ttyS0 or /dev/ttyBCM0 (UARTA)
+	   1 = /dev/ttyS1 or /dev/ttyBCM1 (UARTB)
+	   2 = /dev/ttyS2 or /dev/ttyBCM2 (UARTC)
+
+	  If unsure, choose 0.
+
+
+config BRCM_FLASH
+	bool "Enable onboard flash devices"
+	depends on (BRCM_HAS_NOR || BRCM_HAS_NAND || BRCM_HAS_SPI) && MTD && \
+		!BRCM_IKOS
+	default y
+	help
+	  Say Y to enable NOR/ROM, NAND, and SPI flash devices.  The EBI
+	  and NAND chip select registers will be scanned at boot time to
+	  determine which devices are configured.
+
+	  NOR/ROM will be handled by the standard physmap driver
+	  (CONFIG_MTD_PHYSMAP) in the MTD menus.  NAND is handled by
+	  CONFIG_MTD_BRCMNAND in this menu.
+
+config BRCM_FIXED_MTD_PARTITIONS
+	bool "Use fixed MTD partition map"
+	depends on BRCM_FLASH
+	default n
+	help
+	  Say Y to use the hard-coded flash partition map from
+	  arch/mips/brcmstb/board.c .
+
+	  The default setting (N) constructs the rootfs/kernel partition
+	  boundaries from CFE environment variables.
+
+	  To use this option, please edit board_get_partition_map() and
+	  review brcmstb_mtd_setup().
+
+	  If unsure, say N.
+
+
+config MTD_NAND_BRCMSTB
+	tristate "Broadcom NAND controller support"
+	depends on BRCM_HAS_NAND && BRCM_FLASH
+	default y
+	help
+	  Say Y to enable the onchip NAND controller.
+
+
+config SPI_BRCMSTB
+	tristate "Broadcom HIF SPI controller support"
+	default y
+	depends on BRCM_HAS_SPI && BRCM_FLASH && SPI_MASTER
+	help
+	  Say Y to enable support for SPI (serial) flash devices.
+
+config BCMGENET
+	tristate "Broadcom STB 10/100/1000 MAC/PHY support"
+	depends on ETHERNET && BRCMSTB
+	default y
+	select CRC32
+	select MII
+	select PHYLIB
+	select FIXED_PHY
+	select BCM7XXX_PHY
+	select BCM531XX_PHY
+	help
+	  Say Y to support the internal 10/100/1000 GENET MAC/PHY on
+	  Broadcom set-top chips.  This driver also supports the datapath
+	  for the onchip MoCA transceiver.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_MOCA
+	tristate "Broadcom MoCA character driver"
+	depends on BRCMSTB && BRCM_HAS_MOCA && !BRCM_IKOS
+	default y
+	help
+	  Say Y to build the MoCA control path driver.  This is a simple
+	  character driver that allows the MoCA daemon (mocad) to
+	  initialize and configure the MoCA interface.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+
+config SATA_BRCMSTB
+	tristate "Broadcom STB SATA support"
+	depends on BRCMSTB && PCI && ATA_SFF && !BRCM_IKOS && \
+		BRCM_HAS_SATA2
+	default y
+	help
+	  This option enables support for STB/DVD onchip SATA cores.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+	  If unsure, say Y.
+
+
+config BRCM_USB
+	tristate "Broadcom STB USB support"
+	depends on BRCMSTB && USB && !BRCM_IKOS
+	default y
+	help
+	  Say Y to enable the drivers for the onchip USB controllers.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_OVERRIDE_USB
+	bool "Override USB defaults"
+	depends on BRCM_USB
+	default n
+	help
+	  Say Y to see advanced USB configuration options.
+
+	  Normally the USB driver in the bootloader will enable the
+	  appropriate settings prior to Linux boot, but this step may be
+	  skipped if a customized bootloader is in use.
+
+	  If unsure, say N.
+
+choice
+	prompt "USB VBUS power enable polarity"
+	depends on BRCM_OVERRIDE_USB
+	default BRCM_FORCE_USB_PWR_LO
+
+config BRCM_FORCE_USB_PWR_LO
+	bool "Active low"
+	help
+	  The board's USB VBUS control IC will have either an active low
+	  or an active high enable.  On most Broadcom reference boards,
+	  active low is used; however, on customer designs this may vary.
+	  The output of the hardware signal USBx_PWRON is affected by
+	  this setting, and it applies to all ports and controllers.
+
+config BRCM_FORCE_USB_PWR_HI
+	bool "Active high"
+
+endchoice
+
+choice
+	prompt "USB overcurrent polarity"
+	depends on BRCM_OVERRIDE_USB
+	default BRCM_FORCE_USB_OC_LO
+
+config BRCM_FORCE_USB_OC_LO
+	bool "Active low"
+	help
+	  Controls the handling of the overcurrent indicator line (input
+	  to BCM7xxx).  Active low is typically used when USBx_PWRFLT is
+	  connected to a power switch chip, as is the case on Broadcom
+	  reference boards.  Active high may be used if USBx_PWRFLT is
+	  connected "downstream" from a fuse.
+
+	  This setting applies to all USB ports and controllers.
+
+config BRCM_FORCE_USB_OC_HI
+	bool "Active high"
+
+endchoice
+
+config BRCM_USB_DISABLE_MASK
+	hex "Bitmask of disabled USB hosts"
+	depends on BRCM_OVERRIDE_USB
+	default 0x00
+	help
+	  This is a bitmask to indicate which controllers should be
+	  disabled.  Disabling unused controllers may reduce boot time
+	  and free up system resources.
+
+	  Setting bit 0 will disable the first USB host.
+	  Setting bit 1 will disable the second USB host.
+	  Setting bit 2 will disable the third USB host.
+	  ...
+
+	  If unsure, say 0x00.
+
+
+# NOTE: SDIO_V1 hardware only (vanilla kernel driver sdhci-pltfm.c)
+config BRCM_SDIO
+	bool "Broadcom SDHCI (SDIO) support"
+	depends on BRCM_HAS_SDIO_V1 && MMC_SDHCI && !BRCM_IKOS
+	default y
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  Say Y to enable the driver for the onchip SDIO controller.
+
+	  If you do not plan on using this device, disabling CONFIG_MMC
+	  will save about 75KB.
+
+	  If unsure, say Y.
+
+
+config BRCM_PM
+	bool "Power management for onchip peripherals"
+	default y
+	help
+	  Say Y to enable power management (clock gating) for onchip
+	  peripherals like USB, ENET/GENET, MoCA, and SATA.
+
+
+choice
+	prompt "System clocksource"
+	depends on BRCMSTB && MIPS
+	default CSRC_R4K_BRCMSTB if !SMP && !BRCM_CPU_DIV
+	default CSRC_WKTMR if BRCM_HAS_WKTMR
+	default CSRC_UPG
+	help
+	  The clocksource is used to maintain the real-time clock and
+	  calculate delays.
+
+config CSRC_WKTMR
+	bool "WKTMR"
+	depends on BRCM_HAS_WKTMR
+	help
+	  Say Y to use the 27Mhz "WKTMR" clocksource.  This is usually
+	  the best choice.
+
+config CSRC_R4K_BRCMSTB
+	bool "CP0 COUNT/COMPARE"
+	depends on !BRCM_CPU_DIV
+	select CSRC_R4K
+	help
+	  Say Y to use the CP0 COUNT/COMPARE timer.  This should not be
+	  used in SMP mode because each CPU (TP) has its own independent
+	  counter which is not coherent with the other TP's counter.
+
+config CSRC_UPG
+	bool "UPG TIMER3"
+	help
+	  Say Y to use the 27Mhz UPG TIMER3 as the system clocksource.
+	  On most older chips with no WKTMR, this is the best
+	  choice.  However, this timer will be owned by the kernel
+	  so applications will not be able to use it.
+
+endchoice
+
+
+#####################################################################
+# User options: Miscellaneous options
+#####################################################################
+
+
+comment "Miscellaneous options"
+	depends on BRCMSTB
+
+# PR10860 - Allow long long types to be used in modules
+config BRCM_LIBGCC
+	bool "Enable libgcc functions"
+	depends on BRCMSTB && MIPS
+	default y
+	help
+	  This will build and export several libgcc functions that are
+	  useful for 64-bit (long long) arithmetic.
+
+	  If unsure, say Y.
+
+
+config BRCM_SCSI_NO_RW10_RETRIES
+	bool "No retries on SCSI READ/WRITE10 command"
+	depends on SCSI
+	default n
+	help
+	  Certain applications prefer minimal retries on reading/writing
+	  bad sectors that will be performed at lower level like libata.
+	  Say Y to abort the transaction early instead of attempting
+	  potentially time-consuming retries.
+
+config BRCM_WLAN_MODULES
+	bool "Enable wireless extensions for external modules"
+	default y
+	select WIRELESS_EXT
+	select WEXT_PRIV
+	help
+	  Say Y to enable support for wireless drivers compiled out of tree.
+
+
+#####################################################################
+# User options: Debugging options
+#####################################################################
+
+
+config BRCM_DEBUG_OPTIONS
+	bool "Debugging options"
+	depends on BRCMSTB
+	default n
+	help
+	  Show extra debugging options.
+
+
+config NO_INLINE
+	bool "Disable inlining"
+	depends on BRCM_DEBUG_OPTIONS
+	default n
+	help
+	  Say Y here if you want to disable inlining.  This can make it easier
+	  to step through disassembled code.
+
+
+config BRCM_IKOS
+	bool "Enable IKOS/Veloce emulation"
+	depends on BRCM_DEBUG_OPTIONS
+	select BRCM_OVERRIDE_RAM_SIZE
+	help
+	  Configure kernel for IKOS/Veloce emulation.  This has the
+	  following effects:
+
+	  Disable any drivers not supported in emulation
+	  Prevent UART drivers from changing the divisor set by the bootloader
+
+config BRCM_IKOS_DEBUG
+	bool "Extra debug output during boot"
+	depends on BRCM_IKOS
+	default y
+	help
+	  Enable additional debugging output on the console by adding
+	  "initcall_debug debug" to the kernel command line.  This will slow
+	  down the emulation but can help troubleshoot boot failures.
+
+
+#####################################################################
+# Hidden options: MIPS
+#####################################################################
+
+
+config BRCM_HAS_BMIPS3300
+	bool
+	select SYS_HAS_CPU_BMIPS32_3300
+	select BRCM_CPU_DIV
+
+config BRCM_HAS_BMIPS4380
+	bool
+	select SYS_HAS_CPU_BMIPS4380
+	select BRCM_CPU_DIV
+
+config BRCM_HAS_BMIPS5000
+	bool
+	select SYS_HAS_CPU_BMIPS5000
+	select BRCM_CPU_DIV
+	select BRCM_ZSCM_L2
+	select SYS_SUPPORTS_HIGHMEM
+
+
+#####################################################################
+# Hidden options: UART
+#####################################################################
+
+
+config BRCM_HAS_16550
+	bool
+	select SERIAL_8250
+	select SERIAL_8250_CONSOLE
+
+config BRCM_HAS_UARTA
+	bool
+
+config BRCM_HAS_UARTB
+	bool
+
+config BRCM_HAS_UARTC
+	bool
+
+config BRCM_UARTA_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTA
+
+config BRCM_UARTB_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTB
+
+config BRCM_UARTC_IS_16550
+	bool
+	select BRCM_HAS_16550
+	select BRCM_HAS_UARTC
+
+
+#####################################################################
+# Hidden options: Onchip peripherals/capabilities
+#####################################################################
+
+
+config BRCM_HAS_PCIE
+	bool
+	select HW_HAS_PCI if !BRCM_IKOS
+
+config BRCM_GENET_V1
+	bool
+
+config BRCM_GENET_V2
+	bool
+
+config BRCM_GENET_V3
+	bool
+
+config BRCM_GENET_V4
+	bool
+
+config BRCM_GENET_VERSION
+	int
+	default 1 if BRCM_GENET_V1
+	default 2 if BRCM_GENET_V2
+	default 3 if BRCM_GENET_V3
+	default 4 if BRCM_GENET_V4
+
+# standalone or MoCA GENET controller
+config BRCM_HAS_GENET
+	bool
+
+# select for standalone GENET_0
+config BRCM_HAS_GENET_0
+	bool
+	select BRCM_HAS_GENET
+
+# select for standalone GENET_1
+config BRCM_HAS_GENET_1
+	bool
+	select BRCM_HAS_GENET
+
+# MoCA controller
+config BRCM_HAS_MOCA
+	bool
+
+# Original MoCA 1.1 (gen1 firmware)
+config BRCM_HAS_MOCA_11
+	bool
+	select BRCM_HAS_MOCA
+
+# Cost-reduced MoCA 1.1 with limited TX RAM (gen1 firmware)
+config BRCM_HAS_MOCA_11_LITE
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 1.1 with selected 2.0 features (gen2 firmware)
+config BRCM_HAS_MOCA_11_PLUS
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 2.0 (gen3 firmware for 1.1, gen2x firmware for 2.0)
+config BRCM_HAS_MOCA_20_GEN21
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN22
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN23
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_MOCA_VERS
+	hex
+	default 0x1100 if BRCM_HAS_MOCA_11
+	default 0x1101 if BRCM_HAS_MOCA_11_LITE
+	default 0x1102 if BRCM_HAS_MOCA_11_PLUS
+	default 0x2001 if BRCM_HAS_MOCA_20_GEN21
+	default 0x2002 if BRCM_HAS_MOCA_20_GEN22
+	default 0x2003 if BRCM_HAS_MOCA_20_GEN23
+
+# select for MoCA on GENET_0
+config BRCM_MOCA_ON_GENET_0
+	bool
+	select BRCM_HAS_GENET_0
+
+# select for MoCA on GENET_1
+config BRCM_MOCA_ON_GENET_1
+	bool
+	select BRCM_HAS_GENET_1
+
+# MoCA is MidRF (default is HighRF)
+config BRCM_HAS_MOCA_MIDRF
+	bool
+
+config BRCM_HAS_DVD
+	bool
+
+config BRCM_HAS_SATA
+	bool
+
+config BRCM_HAS_SATA2
+	bool
+	select BRCM_HAS_SATA
+	select HW_HAS_PCI if !BRCM_IKOS
+
+config BRCM_HAS_SATA3
+	bool
+	select BRCM_HAS_SATA
+	select SATA_AHCI_PLATFORM if ATA
+
+config BRCM_SATA_75MHZ_PLL
+	bool
+	default n
+
+config BRCM_SATA_SINGLE_PORT
+	bool
+	default n
+
+config BRCM_HAS_NOR
+	bool
+
+config BRCM_HAS_NAND_MINOR_0
+	bool
+
+config BRCM_HAS_NAND_MINOR_1
+	bool
+
+config BRCM_HAS_NAND_MINOR_2
+	bool
+
+config BRCM_HAS_NAND_MINOR_3
+	bool
+
+config BRCM_HAS_NAND_MINOR_4
+	bool
+
+# major versions 0, 1, 2 are unsupported.
+config BRCM_HAS_NAND_MAJOR_0
+	bool
+
+config BRCM_HAS_NAND_MAJOR_1
+	bool
+
+config BRCM_HAS_NAND_MAJOR_2
+	bool
+
+config BRCM_HAS_NAND_MAJOR_3
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_4
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_5
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_6
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_7
+	bool
+	select BRCM_HAS_NAND
+
+
+config BRCMNAND_MAJOR_VERS
+	int
+	default "7" if BRCM_HAS_NAND_MAJOR_7
+	default "6" if BRCM_HAS_NAND_MAJOR_6
+	default "5" if BRCM_HAS_NAND_MAJOR_5
+	default "4" if BRCM_HAS_NAND_MAJOR_4
+	default "3" if BRCM_HAS_NAND_MAJOR_3
+	default "2" if BRCM_HAS_NAND_MAJOR_2
+	default "1" if BRCM_HAS_NAND_MAJOR_1
+	default "0" if BRCM_HAS_NAND_MAJOR_0
+
+config BRCMNAND_MINOR_VERS
+	int
+	default "4" if BRCM_HAS_NAND_MINOR_4
+	default "3" if BRCM_HAS_NAND_MINOR_3
+	default "2" if BRCM_HAS_NAND_MINOR_2
+	default "1" if BRCM_HAS_NAND_MINOR_1
+	default "0" if BRCM_HAS_NAND_MINOR_0
+
+config BRCM_HAS_NAND
+	bool
+
+config BRCM_HAS_EDU
+	bool
+	depends on !BRCM_HAS_FLASH_DMA
+
+config BRCM_HAS_FLASH_DMA
+	bool
+
+config BRCM_HAS_SPI
+	bool
+
+# v2 is not supported on 2.6.31
+config BRCM_HAS_BSPI_V2
+	bool
+
+config BRCM_HAS_BSPI_V3
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_HAS_BSPI_V4
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_BSPI_MAJOR_VERS
+	int
+	default "4" if BRCM_HAS_BSPI_V4
+	default "3" if BRCM_HAS_BSPI_V3
+	default "2" if BRCM_HAS_BSPI_V2
+
+# For MSPI prior to v1.5 (first version with a revision register)
+config BRCM_MSPI_LEGACY
+	bool
+
+# MSPI can transfer either 64b or 8b per slot
+config BRCM_MSPI_64B_WORDS
+	bool
+
+config BRCM_HAS_WKTMR
+	bool
+
+config BRCM_HAS_SDIO
+	bool
+
+# V0 hardware is ignored on 2.6.37+
+config BRCM_HAS_SDIO_V0
+	bool
+
+config BRCM_HAS_SDIO_V1
+	bool
+	select BRCM_HAS_SDIO
+
+config BRCM_HAS_EMMC
+	bool
+
+config BRCM_ZSCM_L2
+	bool
+	select MIPS_CPU_SCACHE
+
+# PM: adjustable CPU clock divisor
+config BRCM_CPU_DIV
+	bool
+
+# PM: low power "halt" state with IR wakeup
+config BRCM_IRW_HALT
+	bool
+
+# MIPS: extended kseg0/kseg1 feature
+config BRCM_HAS_XKS01
+	bool
+
+# MIPS: eXecute Inhibit (for no-exec stack)
+config BRCM_HAS_XI
+	bool
+
+# MIPS: 2-core * 2-thread = 4-way SMP (BMIPS5200)
+config BRCM_HAS_DUALCORE
+	bool
+
+config BRCM_HAS_UPPER_MEMORY
+	bool
+
+config BRCM_UPPER_768MB
+	bool
+	select XKS01
+
+# physical address maps supporting 256MB, 512MB, or 1GB on MEMC0
+config BRCM_HAS_1GB_MEMC0
+	bool
+
+# physical address map supporting 2GB on MEMC0
+config BRCM_HAS_2GB_MEMC0
+	bool
+
+# MEMC1 is accessible to the CPU and all Linux peripherals
+config BRCM_HAS_1GB_MEMC1
+	bool
+
+config BRCM_HAS_ANALOG_DDR_PHY
+	bool
+
+config BRCM_HAS_DIGITAL_DDR_PHY
+	bool
+
+
+# no handshake (no bsp_rdy signal) means the SW has to manually set SSPD
+config BRCM_PWR_HANDSHAKE
+	bool
+
+# 40nm A0; 65nm
+config BRCM_PWR_HANDSHAKE_V0
+	bool
+	select BRCM_PWR_HANDSHAKE
+
+# 40nm B0
+config BRCM_PWR_HANDSHAKE_V1
+	bool
+	select BRCM_PWR_HANDSHAKE
+
+# USB_CAPS controller enumeration - 40nm
+config BRCM_HAS_USB_CAPS
+	bool
+
+config BRCM_MIPS_DEFAULTS
+	bool
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_EARLY_PRINTK
+	select BOOT_RAW
+	select SERIAL
+	select SYS_SUPPORTS_KGDB
+	select CEVT_R4K
+	select CSRC_R4K
+	select SWAP_IO_SPACE
+	select DMA_NONCOHERENT
+	select FW_CFE
+	select HAVE_CLK
+	select IRQ_DOMAIN
+	select IRQ_MIPS_CPU
+	# select ARCH_SUSPEND_POSSIBLE
+	select BRCM_MSPI_LEGACY
+
+#####################################################################
+# Hidden options: Chip shortcuts
+#####################################################################
+
+config BCM7228
+	bool
+
+config BCM7231
+	bool
+
+config BCM7344
+	bool
+
+config BCM7346
+	bool
+
+config BCM7358
+	bool
+
+config BCM7360
+	bool
+
+config BCM7362
+	bool
+
+config BCM7425
+	bool
+
+config BCM7429
+	bool
+
+config BCM7435
+	bool
+
+config BCM7543
+	bool
+
+config BCM7552
+	bool
+
+config BCM7563
+	bool
+
+config BCM7584
+	bool
+
+endmenu
diff --git a/drivers/brcmstb/Makefile b/drivers/brcmstb/Makefile
new file mode 100644
index 000000000000..85354906a6f1
--- /dev/null
+++ b/drivers/brcmstb/Makefile
@@ -0,0 +1,5 @@
+obj-$(CONFIG_MIPS)		+= bchip.o bmem.o board.o setup.o \
+				   sysfs.o power.o memc1.o m2m.o s3.o
+ifdef CONFIG_MIPS
+obj-$(CONFIG_PCI)	+= pci.o
+endif
diff --git a/drivers/brcmstb/bchip.c b/drivers/brcmstb/bchip.c
new file mode 100644
index 000000000000..3a1ae1e5de5c
--- /dev/null
+++ b/drivers/brcmstb/bchip.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright (C) 2009 - 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/compiler.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#include <linux/platform_data/bcmgenet.h>
+
+#include "../drivers/mmc/host/sdhci.h"
+#include "../drivers/mmc/host/sdhci-pltfm.h"
+
+/* chip features */
+int brcm_sata_enabled;
+int brcm_pcie_enabled;
+int brcm_moca_enabled;
+int brcm_usb_enabled;
+int brcm_pm_enabled;
+
+/* synchronize writes to shared registers */
+DEFINE_SPINLOCK(brcm_magnum_spinlock);
+EXPORT_SYMBOL(brcm_magnum_spinlock);
+
+/* system / device settings */
+unsigned long brcm_dram0_size_mb;
+unsigned long brcm_dram1_size_mb;
+unsigned long brcm_dram1_linux_mb;
+unsigned long brcm_dram1_start = MEMC1_START;
+unsigned long brcm_min_auth_region_size = 0x1000;
+
+unsigned char brcm_eth0_phy[CFE_STRING_SIZE];
+unsigned long brcm_eth0_speed;
+unsigned long brcm_eth0_no_mdio;
+unsigned char brcm_eth0_phyaddr[CFE_STRING_SIZE];
+
+u8 brcm_primary_macaddr[IFHWADDRLEN] = { 0x00, 0x00, 0xde, 0xad, 0xbe, 0xef };
+
+unsigned long brcm_base_baud0 = BRCM_BASE_BAUD_STB;	/* UPG UARTA */
+unsigned long brcm_base_baud = BRCM_BASE_BAUD_STB;	/* UPG_UART[BC] */
+
+struct bcmgenet_platform_data genet_pdata[BRCM_MAX_GENET];
+
+/***********************************************************************
+ * Per-chip operations
+ ***********************************************************************/
+
+#define ALT_CHIP_ID(chip, rev) do { \
+	u32 arg_id = 0x ## chip; \
+	const u8 rev_name[] = #rev; \
+	u32 arg_rev = ((rev_name[0] - 'a') << 4) | (rev_name[1] - '0'); \
+	if (!kernel_chip_id && arg_id == chip_id) { \
+		kernel_chip_id = arg_id; \
+		kernel_chip_rev = arg_rev; \
+	} \
+	} while (0)
+
+#define MAIN_CHIP_ID(chip, rev) do { \
+	u32 arg_id = 0x ## chip; \
+	const u8 rev_name[] = #rev; \
+	u32 arg_rev = ((rev_name[0] - 'a') << 4) | (rev_name[1] - '0'); \
+	if (!kernel_chip_id) { \
+		kernel_chip_id = arg_id; \
+		kernel_chip_rev = arg_rev; \
+	} \
+	} while (0)
+
+/*
+ * NOTE: This is a quick sanity test to catch known incompatibilities and
+ * obvious chip ID mismatches.  It is not comprehensive.  Higher revs may
+ * or may not maintain software compatibility.
+ *
+ * MAIN_CHIP_ID() must always be the final entry.
+ */
+
+void __init bchip_check_compat(void)
+{
+	u32 chip_id = BRCM_CHIP_ID(), chip_rev = BRCM_CHIP_REV();
+	u32 kernel_chip_id = 0, kernel_chip_rev = 0;
+
+#if defined(CONFIG_BCM7231)
+	MAIN_CHIP_ID(7231, b0);
+#elif defined(CONFIG_BCM7344)
+	MAIN_CHIP_ID(7344, b0);
+#elif defined(CONFIG_BCM7346)
+	ALT_CHIP_ID(73465, a0);
+	MAIN_CHIP_ID(7346, b0);
+#elif defined(CONFIG_BCM7358)
+	/* 7358 kernel can boot on 7552, but not vice-versa */
+	ALT_CHIP_ID(7552, a0);
+	MAIN_CHIP_ID(7358, a0);
+#elif defined(CONFIG_BCM7360)
+	MAIN_CHIP_ID(7360, a0);
+#elif defined(CONFIG_BCM7362)
+	ALT_CHIP_ID(73625, a0);
+	MAIN_CHIP_ID(7362, a0);
+#elif defined(CONFIG_BCM7425)
+	MAIN_CHIP_ID(7425, b0);
+#elif defined(CONFIG_BCM7429)
+	ALT_CHIP_ID(74295, a0);
+	MAIN_CHIP_ID(7429, a0);
+#elif defined(CONFIG_BCM7435)
+	MAIN_CHIP_ID(7435, a0);
+#elif defined(CONFIG_BCM7552)
+	MAIN_CHIP_ID(7552, b0);
+#elif defined(CONFIG_BCM7563)
+	ALT_CHIP_ID(75525, a0);
+	ALT_CHIP_ID(75635, a0);
+	MAIN_CHIP_ID(7563, a0);
+#elif defined(CONFIG_BCM7584)
+	ALT_CHIP_ID(75845, a0);
+	MAIN_CHIP_ID(7584, a0);
+#endif
+	if (!kernel_chip_id)
+		return;
+
+	if (chip_id != kernel_chip_id)
+		cfe_die("PANIC: BCM%04x kernel cannot boot on "
+			"BCM%04x chip.\n", kernel_chip_id, chip_id);
+
+	if (chip_rev < kernel_chip_rev)
+		cfe_die("PANIC: This kernel requires BCM%04x rev >= %02X "
+			"(P%02x)\n", kernel_chip_id,
+			kernel_chip_rev + 0xa0, kernel_chip_rev + 0x10);
+}
+
+/***********************************************************************
+ * Common operations for all chips
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_SATA3
+
+#ifdef __BIG_ENDIAN
+#define DATA_ENDIAN             2       /* AHCI->DDR inbound accesses */
+#define MMIO_ENDIAN             2       /* MIPS->AHCI outbound accesses */
+#else
+#define DATA_ENDIAN             0
+#define MMIO_ENDIAN             0
+#endif /* __BIG_ENDIAN */
+
+/* SATA3 SSC per-port bitfield */
+static u32 sata3_enable_ssc;
+
+#define SATA3_MDIO_TXPMD_0_REG_BANK	0x1A0
+#define SATA3_MDIO_BRIDGE_BASE		(BCHP_SATA_GRB_REG_START + 0x100)
+#define SATA3_MDIO_BASE_REG_ADDR	(SATA3_MDIO_BRIDGE_BASE + 0x8F * 4)
+
+#define SATA_AHCI_GHC_CAP		(BCHP_SATA_AHCI_GHC_REG_START + 0x0)
+#define SATA_AHCI_GHC_PORTS_IMPLEMENTED	(BCHP_SATA_AHCI_GHC_REG_START + 0xC)
+
+#define HOST_CAP_NCQ			(1 << 30)
+
+#define SATA_TOP_CTRL_BUS_CTRL			0x4
+#define SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT	(1 << 16)
+
+#define SATA3_TXPMD_CONTROL1			0x81
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL1	0x82
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL2	0x83
+#define SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3	0x84
+
+static inline void brcm_sata3_mdio_wr_reg(u32 bank, unsigned int ofs, u32 msk,
+		u32 enable)
+{
+	u32 tmp;
+	BDEV_WR(SATA3_MDIO_BASE_REG_ADDR, bank);
+	/* Read, mask, enable */
+	tmp = BDEV_RD(ofs * 4 + SATA3_MDIO_BRIDGE_BASE);
+	tmp = (tmp & msk) | enable;
+	/* Write */
+	BDEV_WR(ofs * 4 + SATA3_MDIO_BRIDGE_BASE, tmp);
+}
+
+static void brcm_sata3_init_freq(int port, int ssc_enable)
+{
+	u32 bank = SATA3_MDIO_TXPMD_0_REG_BANK + port * 0x10;
+
+	if (ssc_enable)
+		pr_info("SATA3: enabling SSC on port %d\n", port);
+
+	/* TXPMD_control1 - enable SSC force */
+	brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_CONTROL1, 0xFFFFFFFC,
+			0x00000003);
+
+	/* TXPMD_tx_freq_ctrl_control2 - set fixed min freq */
+	brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL2,
+			0xFFFFFC00, 0x000003DF);
+
+	/*
+	 * TXPMD_tx_freq_ctrl_control3 - set fixed max freq
+	 *  If ssc_enable == 0, center frequencies
+	 *  Otherwise, spread spectrum frequencies
+	 */
+	if (ssc_enable)
+		brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3,
+				0xFFFFFC00, 0x00000083);
+	else
+		brcm_sata3_mdio_wr_reg(bank, SATA3_TXPMD_TX_FREQ_CTRL_CONTROL3,
+				0xFFFFFC00, 0x000003DF);
+}
+
+/* Check up to 32 ports, although we typically only have 2 */
+#define SATA_MAX_CHECK_PORTS	32
+
+/*
+ * Check commandline for 'sata3_ssc' options. They can be specified in 2 ways:
+ *  (1) 'sata3_ssc'     -> enable SSC on all ports
+ *  (2) 'sata3_ssc=x,y' -> enable SSC on specific port(s), given a comma-
+ *                         separated list of port numbers
+ */
+static int __init sata3_ssc_setup(char *str)
+{
+	int opts[SATA_MAX_CHECK_PORTS + 1], i;
+
+	if (*str == '\0') {
+		/* enable SSC on all ports */
+		sata3_enable_ssc = ~0;
+		return 0;
+	}
+	get_options(str + 1, SATA_MAX_CHECK_PORTS, opts);
+
+	for (i = 0; i < opts[0]; i++) {
+		int port = opts[i + 1];
+		if ((port >= 0) && (port < SATA_MAX_CHECK_PORTS))
+			sata3_enable_ssc |= 1 << port;
+	}
+
+	return 0;
+}
+
+__setup("sata3_ssc", sata3_ssc_setup);
+
+/*
+ * Disables NCQ at the SATA AHCI core level by clearing the bit that indicates
+ * support for it.
+ */
+static void brcm_sata3_disable_ncq(void)
+{
+	u32 top_ctrl = BCHP_SATA_TOP_CTRL_REG_START + SATA_TOP_CTRL_BUS_CTRL;
+
+	BDEV_SET(top_ctrl, SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT);
+
+	/*
+	 * Clear out the NCQ bit so the AHCI driver will not issue FPDMA/NCQ
+	 * commands.
+	 */
+	BDEV_UNSET(SATA_AHCI_GHC_CAP, HOST_CAP_NCQ);
+
+	BDEV_UNSET(top_ctrl, SATA_TOP_CTRL_BUS_CTRL_OVERRIDE_HWINIT);
+}
+#endif /* CONFIG_BRCM_HAS_SATA3 */
+
+void bchip_sata3_init(void)
+{
+#ifdef CONFIG_BRCM_HAS_SATA3
+	int i, ports = fls(BDEV_RD(SATA_AHCI_GHC_PORTS_IMPLEMENTED));
+
+	brcm_sata3_disable_ncq();
+
+	/*
+	 * On BE systems, the AHCI register data is endian-swapped past
+	 * this point.  This affects SATA_AHCI_GHC_* and other ranges,
+	 * but not SATA_TOP_CONTROL or MDIO.
+	 */
+	BDEV_WR(BCHP_SATA_TOP_CTRL_BUS_CTRL, (DATA_ENDIAN << 4) |
+			(DATA_ENDIAN << 2) | (MMIO_ENDIAN << 0));
+
+	for (i = 0; i < ports; i++)
+		brcm_sata3_init_freq(i, sata3_enable_ssc & (1 << i));
+#endif
+}
+
+#ifdef __LITTLE_ENDIAN
+#define USB_ENDIAN		0x03 /* !WABO !FNBO FNHW BABO */
+#else
+#define USB_ENDIAN		0x0e /* WABO FNBO FNHW !BABO */
+#endif
+
+#define USB_ENDIAN_MASK		0x0f
+#define USB_IOC			BCHP_USB_CTRL_SETUP_IOC_MASK
+#define USB_IPP			BCHP_USB_CTRL_SETUP_IPP_MASK
+
+#define USB_REG(x, y)		(x + BCHP_USB_CTRL_##y - \
+				 BCHP_USB_CTRL_REG_START)
+
+static void bchip_usb_init_one(int id, uintptr_t base)
+{
+	/* endianness setup */
+	BDEV_UNSET_RB(USB_REG(base, SETUP), USB_ENDIAN_MASK);
+	BDEV_SET_RB(USB_REG(base, SETUP), USB_ENDIAN);
+
+	/* power control setup */
+#ifdef CONFIG_BRCM_OVERRIDE_USB
+
+#ifdef CONFIG_BRCM_FORCE_USB_OC_LO
+	BDEV_SET(USB_REG(base, SETUP), USB_IOC);
+#else
+	BDEV_UNSET(USB_REG(base, SETUP), USB_IOC);
+#endif
+
+#ifdef CONFIG_BRCM_FORCE_USB_PWR_LO
+	BDEV_SET(USB_REG(base, SETUP), USB_IPP);
+#else
+	BDEV_UNSET(USB_REG(base, SETUP), USB_IPP);
+#endif
+
+#else /* CONFIG_BRCM_OVERRIDE_USB */
+	if ((BDEV_RD(USB_REG(base, SETUP)) & USB_IOC) == 0) {
+		printk(KERN_WARNING "USB%d: IOC was not set by the bootloader;"
+			" forcing default settings\n", id);
+		BDEV_SET(USB_REG(base, SETUP), USB_IOC);
+		BDEV_SET(USB_REG(base, SETUP), USB_IPP);
+	}
+#endif /* CONFIG_BRCM_OVERRIDE_USB */
+
+	printk(KERN_INFO "USB%d: power enable is active %s; overcurrent is "
+		"active %s\n", id,
+		BDEV_RD(USB_REG(base, SETUP)) & USB_IPP ? "low" : "high",
+		BDEV_RD(USB_REG(base, SETUP)) & USB_IOC ? "low" : "high");
+
+	/* PR45703 - for OHCI->SCB bridge lockup */
+	BDEV_UNSET(USB_REG(base, OBRIDGE),
+		BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK);
+
+	/* Disable EHCI transaction combining */
+	BDEV_UNSET(USB_REG(base, EBRIDGE),
+		BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK);
+
+	/* SWLINUX-1705: Avoid OUT packet underflows */
+	BDEV_UNSET(USB_REG(base, EBRIDGE),
+		BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK);
+	BDEV_SET(USB_REG(base, EBRIDGE),
+		0x08 << BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT);
+
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	/* enable access to SCB1 */
+	BDEV_SET(USB_REG(base, SETUP), BIT(14));
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7435B0)
+	/* SWLINUX-2259 - Work around a USB DMA to memc1 arbitration bug */
+	BDEV_SET(USB_REG(base, SETUP), BIT(13));
+#endif
+
+#endif
+
+#if defined(BCHP_USB_CTRL_GENERIC_CTL_1_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, GENERIC_CTL_1),
+		BCHP_USB_CTRL_GENERIC_CTL_1_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_GENERIC_CTL_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, GENERIC_CTL),
+		BCHP_USB_CTRL_GENERIC_CTL_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_PLL_CTL_1_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, PLL_CTL_1),
+		BCHP_USB_CTRL_PLL_CTL_1_PLL_SUSPEND_EN_MASK);
+#elif defined(BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK)
+	BDEV_SET(USB_REG(base, PLL_CTL),
+		BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK);
+#endif
+
+}
+
+void bchip_usb_init(void)
+{
+	bchip_usb_init_one(0, BCHP_USB_CTRL_REG_START);
+#ifdef BCHP_USB1_CTRL_REG_START
+	if (BRCM_PROD_ID() != 0x74285)
+		bchip_usb_init_one(1, BCHP_USB1_CTRL_REG_START);
+#endif
+}
+
+#if defined(CONFIG_BRCM_HAS_MOCA)
+void bchip_moca_init(void)
+{
+#ifdef BCHP_SUN_TOP_CTRL_SW_RESET
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_RESET, moca_sw_reset, 0);
+#else
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_INIT_0_CLEAR, moca_sw_init, 1);
+#endif
+
+#ifdef BCHP_MOCA_HOSTMISC_SW_RESET_moca_enet_reset_MASK
+	BDEV_WR_F_RB(MOCA_HOSTMISC_SW_RESET, moca_enet_reset, 0);
+#endif
+}
+#endif
+
+void __init bchip_set_features(void)
+{
+#if defined(CONFIG_BRCM_HAS_SATA)
+	brcm_sata_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_HAS_PCIE)
+	brcm_pcie_enabled = 1;
+#endif
+#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
+	bmips_smp_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_HAS_MOCA)
+	brcm_moca_enabled = 1;
+#endif
+#if defined(CONFIG_BRCM_PM)
+	brcm_pm_enabled = 1;
+#endif
+	brcm_usb_enabled = 1;
+
+	/* now remove any features disabled in hardware */
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_sata_disable) == 1)
+		brcm_sata_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_usb_disable) == 1)
+		brcm_usb_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_moca_disable) == 1)
+		brcm_moca_enabled = 0;
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_MASK
+	if (BDEV_RD_F(SUN_TOP_CTRL_OTP_OPTION_STATUS_0,
+			otp_option_pcie_disable) == 1)
+		brcm_pcie_enabled = 0;
+#endif
+
+#ifdef CONFIG_BCM7425
+	/* disable PCIe initialization in EP mode */
+	if (BDEV_RD_F(SUN_TOP_CTRL_STRAP_VALUE_0, strap_rc_ep) == 0)
+		brcm_pcie_enabled = 0;
+#endif
+}
+
+void __init bchip_early_setup(void)
+{
+#if defined(CONFIG_BRCM_HAS_WKTMR)
+	struct wktmr_time t;
+
+	if (!(BDEV_RD(AON_RAM(122)) & (3<<30))) {
+		BDEV_WR_F_RB(WKTMR_EVENT, wktmr_alarm_event, 1);
+		BDEV_WR_F_RB(WKTMR_PRESCALER, wktmr_prescaler, WKTMR_FREQ);
+		BDEV_WR_F_RB(WKTMR_COUNTER, wktmr_counter, 0);
+
+		/* wait for first tick so we know the counter is ready to use */
+		wktmr_read(&t);
+		while (wktmr_elapsed(&t) == 0)
+			;
+	}
+#endif
+
+#ifdef CONFIG_PCI
+	if (brcm_pcie_enabled)
+		brcm_early_pcie_setup();
+#endif
+
+	/*
+	 * Initial GENET defaults
+	 * These can be overridden by board_pinmux_setup() or by CFE vars
+	 */
+#if defined(CONFIG_BRCM_HAS_GENET_0)
+
+	genet_pdata[0].base_reg = BCHP_GENET_0_SYS_REG_START;
+	genet_pdata[0].irq0 = BRCM_IRQ_GENET_0_A;
+	genet_pdata[0].irq1 = BRCM_IRQ_GENET_0_B;
+	genet_pdata[0].genet_version = CONFIG_BRCM_GENET_VERSION;
+
+#if defined(CONFIG_BRCM_MOCA_ON_GENET_0)
+	if (brcm_moca_enabled) {
+		genet_pdata[0].phy_interface = PHY_INTERACE_MODE_MOCA;
+		genet_pdata[0].phy_address = 0;
+		genet_pdata[0].phy_duplex = DUPLEX_FULL;
+		genet_pdata[0].phy_speed = SPEED_1000;
+	} else {
+		genet_pdata[0].phy_interface = PHY_INTERFACE_MODE_RGMII_TXID;
+		genet_pdata[0].phy_address = -1;
+		genet_pdata[0].mdio_enabled = true;
+	}
+#else
+	genet_pdata[0].phy_interface = PHY_INTERFACE_MODE_NA;
+	genet_pdata[0].phy_address = 1;
+	genet_pdata[0].mdio_enabled = true;
+#endif
+
+#endif
+
+#if defined(CONFIG_BRCM_HAS_GENET_1)
+
+	genet_pdata[1].base_reg = BCHP_GENET_1_SYS_REG_START;
+	genet_pdata[1].irq0 = BRCM_IRQ_GENET_1_A;
+	genet_pdata[1].irq1 = BRCM_IRQ_GENET_1_B;
+	genet_pdata[1].genet_version = CONFIG_BRCM_GENET_VERSION;
+
+	genet_pdata[1].phy_interface = PHY_INTERFACE_MODE_RGMII_TXID;
+	genet_pdata[1].mdio_enabled = true;
+	genet_pdata[1].phy_address = -1;
+
+#if defined(CONFIG_BRCM_MOCA_ON_GENET_1)
+	if (brcm_moca_enabled) {
+		genet_pdata[1].phy_interface = PHY_INTERFACE_MODE_MOCA;
+		genet_pdata[1].phy_duplex = DUPLEX_FULL;
+		genet_pdata[1].phy_speed = SPEED_1000;
+		genet_pdata[1].phy_address = 0;
+		genet_pdata[1].mdio_enabled = false;
+	}
+#endif
+
+#endif
+}
+
+int brcm_alloc_macaddr(u8 *buf)
+{
+	memcpy(buf, brcm_primary_macaddr, ETH_ALEN);
+	brcm_primary_macaddr[4]++;
+	return 0;
+}
+EXPORT_SYMBOL(brcm_alloc_macaddr);
+
+/***********************************************************************
+ * WKTMR utility functions (boot time only)
+ ***********************************************************************/
+
+void wktmr_read(struct wktmr_time *t)
+{
+	uint32_t tmp;
+
+	do {
+		t->sec = BDEV_RD(BCHP_WKTMR_COUNTER);
+		tmp = BDEV_RD(BCHP_WKTMR_PRESCALER_VAL);
+	} while (tmp >= WKTMR_FREQ);
+
+	t->pre = WKTMR_FREQ - tmp;
+}
+
+unsigned long wktmr_elapsed(struct wktmr_time *t)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+	now.sec -= t->sec;
+	if (now.pre >= t->pre) {
+		now.pre -= t->pre;
+	} else {
+		now.pre = WKTMR_FREQ + now.pre - t->pre;
+		now.sec--;
+	}
+	return (now.sec * WKTMR_FREQ) + now.pre;
+}
+
diff --git a/drivers/brcmstb/bmem.c b/drivers/brcmstb/bmem.c
new file mode 100644
index 000000000000..57f9b7677420
--- /dev/null
+++ b/drivers/brcmstb/bmem.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+#include <linux/compiler.h>
+#include <linux/module.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#if 0
+#define DBG printk
+#else
+#define DBG(...) /* */
+#endif
+
+#define LINUX_MIN_MEM		64
+#define MAX_BMEM_REGIONS	4
+
+struct bmem_region {
+	unsigned long		addr;
+	unsigned long		size;
+	int			valid;
+};
+
+static struct bmem_region bmem_regions[MAX_BMEM_REGIONS];
+static unsigned int n_bmem_regions;
+
+#if defined(CONFIG_BRCM_IKOS)
+static unsigned int bmem_disabled = 1;
+#else
+static unsigned int bmem_disabled;
+#endif
+
+/***********************************************************************
+ * MEMC1 handling
+ ***********************************************************************/
+
+static int __init brcm_memc1_bmem(void)
+{
+	struct bmem_region *r = NULL;
+
+	if (brcm_dram1_size_mb &&
+			brcm_dram1_size_mb > brcm_dram1_linux_mb &&
+			n_bmem_regions < MAX_BMEM_REGIONS) {
+		r = &bmem_regions[n_bmem_regions++];
+		r->addr = brcm_dram1_start + (brcm_dram1_linux_mb << 20);
+		r->size = (brcm_dram1_size_mb - brcm_dram1_linux_mb) << 20;
+		r->valid = 1;
+		printk(KERN_INFO "bmem: adding extra %lu MB RESERVED region at "
+			"%lu MB (0x%08lx@0x%08lx)\n", r->size >> 20,
+			r->addr >> 20, r->size, r->addr);
+	}
+	return 0;
+}
+
+core_initcall(brcm_memc1_bmem);
+
+/***********************************************************************
+ * BMEM (reserved A/V buffer memory) support
+ ***********************************************************************/
+
+/*
+ * Parses command line for bmem= options
+ */
+static int __init bmem_setup(char *str)
+{
+	unsigned long addr = 0, size;
+	unsigned long lower_mem_bytes;
+	char *orig_str = str;
+
+	lower_mem_bytes = (brcm_dram0_size_mb > BRCM_MAX_LOWER_MB) ?
+		(BRCM_MAX_LOWER_MB << 20) : (brcm_dram0_size_mb << 20);
+
+	size = (unsigned long)memparse(str, &str);
+	if (*str == '@')
+		addr = (unsigned long)memparse(str + 1, &str);
+
+	if ((size > 0x40000000) || (addr > 0x80000000)) {
+		printk(KERN_WARNING "bmem: argument '%s' "
+			"is out of range, ignoring\n", orig_str);
+		return 0;
+	}
+
+	if (size == 0) {
+		printk(KERN_INFO "bmem: disabling reserved memory\n");
+		bmem_disabled = 1;
+		return 0;
+	}
+
+	if ((addr & ~PAGE_MASK) || (size & ~PAGE_MASK)) {
+		printk(KERN_WARNING "bmem: ignoring invalid range '%s' "
+			"(is it missing an 'M' suffix?)\n", orig_str);
+		return 0;
+	}
+
+	if (addr == 0) {
+		/*
+		 * default: bmem=xxM allocates xx megabytes at the end of
+		 * lower memory
+		 */
+		if (size >= lower_mem_bytes) {
+			printk(KERN_WARNING "bmem: '%s' is larger than "
+				"lower memory (%lu MB), ignoring\n",
+				orig_str, brcm_dram0_size_mb);
+			return 0;
+		}
+		addr = lower_mem_bytes - size;
+	}
+
+	if (n_bmem_regions == MAX_BMEM_REGIONS) {
+		printk(KERN_WARNING "bmem: too many regions, "
+			"ignoring extras\n");
+		return 0;
+	}
+
+	bmem_regions[n_bmem_regions].addr = addr;
+	bmem_regions[n_bmem_regions].size = size;
+	n_bmem_regions++;
+
+	return 0;
+}
+
+early_param("bmem", bmem_setup);
+
+/*
+ * Returns index if the supplied range falls entirely within a bmem region
+ */
+int bmem_find_region(unsigned long addr, unsigned long size)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if ((addr >= bmem_regions[i].addr) &&
+		    ((addr + size) <=
+			(bmem_regions[i].addr + bmem_regions[i].size))) {
+			return idx;
+		}
+		idx++;
+	}
+	return -ENOENT;
+}
+EXPORT_SYMBOL(bmem_find_region);
+
+/*
+ * Finds the IDX'th valid bmem region, and fills in addr/size if it exists.
+ * Returns 0 on success, <0 on failure.
+ */
+int bmem_region_info(int idx, unsigned long *addr, unsigned long *size)
+{
+	int i;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if (!idx) {
+			*addr = bmem_regions[i].addr;
+			*size = bmem_regions[i].size;
+			return 0;
+		}
+		idx--;
+	}
+	return -ENOENT;
+}
+EXPORT_SYMBOL(bmem_region_info);
+
+/*
+ * Special handling for __get_user_pages() on BMEM reserved memory:
+ *
+ * 1) Override the VM_IO | VM_PFNMAP sanity checks
+ * 2) No cache flushes (this is explicitly under application control)
+ * 3) vm_normal_page() does not work on these regions
+ * 4) Don't need to worry about any kinds of faults; pages are always present
+ *
+ * The vanilla kernel behavior was to prohibit O_DIRECT operations on our
+ * BMEM regions, but direct I/O is absolutely required for PVR and video
+ * playback from SATA/USB.
+ */
+int bmem_get_page(struct mm_struct *mm, struct vm_area_struct *vma,
+	unsigned long start, struct page **page)
+{
+	unsigned long pg = start & PAGE_MASK, pfn;
+	int ret = -EFAULT;
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	pgd = pgd_offset(mm, pg);
+	BUG_ON(pgd_none(*pgd));
+	pud = pud_offset(pgd, pg);
+	BUG_ON(pud_none(*pud));
+	pmd = pmd_offset(pud, pg);
+	if (pmd_none(*pmd))
+		return ret;
+
+	pte = pte_offset_map(pmd, pg);
+	if (pte_none(*pte))
+		goto out;
+
+	pfn = pte_pfn(*pte);
+	if (!pfn_valid(pfn))
+		goto out;
+
+	if (likely(bmem_find_region(pfn << PAGE_SHIFT, PAGE_SIZE) < 0))
+		goto out;
+
+	if (page) {
+		*page = pfn_to_page(pfn);
+		get_page(*page);
+	}
+	ret = 0;
+
+out:
+	pte_unmap(pte);
+	return ret;
+}
+
+static int __initdata bmem_defaults_set;
+
+static void __init brcm_set_default_bmem(void)
+{
+	/*
+	 * Default: (no valid bmem= options specified)
+	 *
+	 * Lower memory is the first 256MB of system RAM.
+	 * bmem gets all but (LINUX_MIN_MEM) megabytes of lower memory.
+	 * Linux gets all upper and high memory (if present).
+	 *
+	 * Options:
+	 *
+	 * Define one or more custom bmem regions, e.g.:
+	 *   bmem=128M (128MB region at the end of lower memory)
+	 *   bmem=128M@64M (128MB hole at 64MB mark)
+	 *   bmem=16M@64M bmem=4M@128M bmem=16M@200M (multiple holes)
+	 *
+	 * Disable bmem; give all system RAM to the Linux VM:
+	 *   bmem=0
+	 *
+	 * Overlapping or invalid regions will usually be silently dropped.
+	 * If you are doing something tricky, watch the boot messages to
+	 * make sure it turns out the way you intended.
+	 */
+	if (bmem_disabled) {
+		n_bmem_regions = 0;
+	} else {
+		if (n_bmem_regions == 0 &&
+		    (brcm_dram0_size_mb > LINUX_MIN_MEM)) {
+			n_bmem_regions = 1;
+			bmem_regions[0].addr = LINUX_MIN_MEM << 20;
+			bmem_regions[0].size =
+				(((brcm_dram0_size_mb <= BRCM_MAX_LOWER_MB) ?
+				  brcm_dram0_size_mb : BRCM_MAX_LOWER_MB) -
+				 LINUX_MIN_MEM) << 20;
+		}
+	}
+}
+
+/*
+ * Invokes free_bootmem(), but truncates ranges where necessary to
+ * avoid releasing the bmem region(s) back to the VM
+ */
+void __init brcm_free_bootmem(unsigned long addr, unsigned long size)
+{
+	if (!bmem_defaults_set) {
+		brcm_set_default_bmem();
+		bmem_defaults_set = 1;
+	}
+
+	while (size) {
+		unsigned long chunksize = size;
+		int i;
+		struct bmem_region *r = NULL;
+
+		/*
+		 * Find the first bmem region (if any) that fits entirely
+		 * within the current bootmem address range.
+		 */
+		for (i = 0; i < n_bmem_regions; i++) {
+			if ((bmem_regions[i].addr >= addr) &&
+			    ((bmem_regions[i].addr + bmem_regions[i].size) <=
+			     (addr + size))) {
+				if (!r || (r->addr > bmem_regions[i].addr))
+					r = &bmem_regions[i];
+			}
+		}
+
+		/*
+		 * Skip over every bmem region; call free_bootmem() for
+		 * every Linux region.  A Linux region is created for
+		 * each chunk of the memory map that is not reserved
+		 * for bmem.
+		 */
+		if (r) {
+			if (addr == r->addr) {
+				printk(KERN_INFO "bmem: adding %lu MB "
+					"RESERVED region at %lu MB "
+					"(0x%08lx@0x%08lx)\n",
+					r->size >> 20, r->addr >> 20,
+					r->size, r->addr);
+				chunksize = r->size;
+				r->valid = 1;
+				goto skip;
+			} else {
+				BUG_ON(addr > r->addr);
+				chunksize = r->addr - addr;
+			}
+		}
+		BUG_ON(chunksize > size);
+
+		printk(KERN_DEBUG "bmem: adding %lu MB LINUX region at %lu MB "
+			"(0x%08lx@0x%08lx)\n", chunksize >> 20, addr >> 20,
+			chunksize, addr);
+		free_bootmem(addr, chunksize);
+
+skip:
+		addr += chunksize;
+		size -= chunksize;
+	}
+}
+
+/*
+ * Create /proc/iomem entries for bmem
+ */
+static int __init bmem_region_setup(void)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		struct resource *r;
+		char *name;
+
+		if (!bmem_regions[i].valid)
+			continue;
+
+		r = kzalloc(sizeof(*r), GFP_KERNEL);
+		name = kzalloc(16, GFP_KERNEL);
+		if (!r || !name)
+			break;
+
+		sprintf(name, "bmem.%d", idx);
+		r->start = bmem_regions[i].addr;
+		r->end = bmem_regions[i].addr + bmem_regions[i].size - 1;
+		r->flags = IORESOURCE_MEM;
+		r->name = name;
+
+		insert_resource(&iomem_resource, r);
+		idx++;
+	}
+	return 0;
+}
+
+arch_initcall(bmem_region_setup);
+
diff --git a/drivers/brcmstb/board.c b/drivers/brcmstb/board.c
new file mode 100644
index 000000000000..1145cdf2da8d
--- /dev/null
+++ b/drivers/brcmstb/board.c
@@ -0,0 +1,839 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/bmoca.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* board features */
+int brcm_docsis_platform;
+char brcm_cfe_boardname[CFE_STRING_SIZE];
+
+/* MTD partition layout */
+unsigned long brcm_mtd_rootfs_start;
+unsigned long brcm_mtd_rootfs_len;
+unsigned long brcm_mtd_kernel_start;
+unsigned long brcm_mtd_kernel_len;
+unsigned long brcm_mtd_ocap_start;
+unsigned long brcm_mtd_ocap_len;
+unsigned long brcm_mtd_flash_size_mb;
+char brcm_mtd_flash_type[CFE_STRING_SIZE];
+
+/* MoCA 3450 I2C port */
+unsigned long brcm_moca_i2c_base;
+
+/* Default MoCA RF band (can be overridden in board_pinmux_setup) */
+#ifdef CONFIG_BRCM_HAS_MOCA_MIDRF
+unsigned long brcm_moca_rf_band = MOCA_BAND_MIDRF;
+#else
+unsigned long brcm_moca_rf_band = MOCA_BAND_HIGHRF;
+#endif
+
+/***********************************************************************
+ * PIN_MUX setup
+ *
+ * NOTE: This code assumes that the bootloader already set up the pinmux
+ * for the primary UART (almost always UARTA) and EBI.
+ *
+ * This code is free to modify genet_pdata[].  For example, to set up an
+ * external RGMII PHY on GENET_0, set up your pinmux / pad voltages /
+ * pulldowns then add:
+ *
+ *   genet_pdata[0].phy_interface = PHY_INTERFACE_MODE_RGMII_TXID;
+ *   genet_pdata[0].phy_address = 0;
+ ***********************************************************************/
+
+#define PINMUX(reg, field, val) do { \
+	BDEV_WR(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg, \
+		(BDEV_RD(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg) & \
+		 ~BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define AON_PINMUX(reg, field, val) do { \
+	BDEV_WR(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg, \
+		(BDEV_RD(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg) & \
+		 ~BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define PADCTRL(reg, field, val) do { \
+	BDEV_WR(BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg, \
+		(BDEV_RD(BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg) & \
+		 ~BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+#define AON_PADCTRL(reg, field, val) do { \
+	BDEV_WR(BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg, \
+		(BDEV_RD(BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg) & \
+		 ~BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_MASK) | \
+		((val) << \
+		 BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_##reg##_##field##_SHIFT)); \
+	} while (0)
+
+
+#define SDIO_CFG_REG(x, y)	(BCHP_SDIO_##x##_CFG_REG_START + \
+				 (BCHP_SDIO_0_CFG_##y - \
+				  BCHP_SDIO_0_CFG_REG_START))
+
+void board_pinmux_setup(void)
+{
+	static int __maybe_unused sdio_0_disabled = -1;
+	static int __maybe_unused sdio_1_disabled = -1;
+
+#if !defined(CONFIG_BRCM_IKOS)
+#if defined(CONFIG_BCM7231)
+
+	PINMUX(11, gpio_94, 1);		/* UARTB TX */
+	PINMUX(11, gpio_95, 1);		/* UARTB RX */
+
+	if (BRCM_PROD_ID() == 0x7230) {
+		/* 7230 is not the same ballout as 7231 */
+		AON_PINMUX(0, aon_gpio_04, 6);	/* SDIO */
+		AON_PINMUX(0, aon_gpio_05, 6);
+		AON_PINMUX(1, aon_gpio_12, 5);
+		AON_PINMUX(1, aon_gpio_13, 5);
+		AON_PINMUX(2, aon_gpio_14, 5);
+		AON_PINMUX(2, aon_gpio_15, 6);
+		AON_PINMUX(2, aon_gpio_16, 6);
+		AON_PINMUX(2, aon_gpio_17, 6);
+		AON_PINMUX(2, aon_gpio_18, 6);
+		AON_PINMUX(2, aon_gpio_19, 6);
+
+		/* disable GPIO pulldowns */
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
+			aon_gpio_04_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
+			aon_gpio_05_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_12_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_13_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_14_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_15_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_16_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_17_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_18_pad_ctrl, 0);
+		BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
+			aon_gpio_19_pad_ctrl, 0);
+	} else {
+		/* set RGMII lines to 2.5V */
+		BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0,
+			rgmii_0_pad_mode, 1);
+
+		PINMUX(15, gpio_132, 1);	/* RGMII RX */
+		PINMUX(15, gpio_133, 1);
+		PINMUX(15, gpio_134, 1);
+		PINMUX(16, gpio_139, 1);
+		PINMUX(16, gpio_140, 1);
+		PINMUX(16, gpio_141, 1);
+		PINMUX(16, gpio_142, 1);
+
+		PINMUX(16, gpio_138, 1);	/* RGMII TX */
+		PINMUX(17, gpio_143, 1);
+		PINMUX(17, gpio_144, 1);
+		PINMUX(17, gpio_145, 1);
+		PINMUX(17, gpio_146, 1);
+		PINMUX(17, gpio_147, 1);
+
+		PINMUX(17, gpio_149, 1);	/* RGMII MDIO */
+		PINMUX(16, gpio_137, 1);
+
+		/* no pulldown on RGMII lines */
+		PADCTRL(8, gpio_132_pad_ctrl, 0);
+		PADCTRL(8, gpio_133_pad_ctrl, 0);
+		PADCTRL(8, gpio_134_pad_ctrl, 0);
+		PADCTRL(8, gpio_137_pad_ctrl, 0);
+		PADCTRL(8, gpio_138_pad_ctrl, 0);
+		PADCTRL(9, gpio_139_pad_ctrl, 0);
+		PADCTRL(9, gpio_140_pad_ctrl, 0);
+		PADCTRL(9, gpio_141_pad_ctrl, 0);
+		PADCTRL(9, gpio_142_pad_ctrl, 0);
+		PADCTRL(9, gpio_143_pad_ctrl, 0);
+		PADCTRL(9, gpio_144_pad_ctrl, 0);
+		PADCTRL(9, gpio_145_pad_ctrl, 0);
+		PADCTRL(9, gpio_146_pad_ctrl, 0);
+		PADCTRL(9, gpio_147_pad_ctrl, 0);
+		PADCTRL(9, gpio_149_pad_ctrl, 0);
+
+		PINMUX(14, gpio_122, 1);	/* SDIO */
+		PINMUX(14, gpio_123, 1);
+		PINMUX(14, gpio_124, 1);
+		PINMUX(14, gpio_125, 1);
+		PINMUX(14, gpio_126, 1);
+		PINMUX(15, gpio_127, 1);
+		PINMUX(15, gpio_128, 1);
+		PINMUX(15, gpio_129, 1);
+		PINMUX(15, gpio_130, 1);
+		PINMUX(15, gpio_131, 1);
+
+		/* no pulldown on SDIO lines */
+		PADCTRL(7, gpio_122_pad_ctrl, 0);
+		PADCTRL(7, gpio_123_pad_ctrl, 0);
+		PADCTRL(8, gpio_124_pad_ctrl, 0);
+		PADCTRL(8, gpio_125_pad_ctrl, 0);
+		PADCTRL(8, gpio_126_pad_ctrl, 0);
+		PADCTRL(8, gpio_127_pad_ctrl, 0);
+		PADCTRL(8, gpio_128_pad_ctrl, 0);
+		PADCTRL(8, gpio_129_pad_ctrl, 0);
+		PADCTRL(8, gpio_130_pad_ctrl, 0);
+		PADCTRL(8, gpio_131_pad_ctrl, 0);
+
+		genet_pdata[1].phy_speed = SPEED_1000;
+		genet_pdata[1].phy_interface = PHY_INTERFACE_MODE_RGMII;
+	}
+
+#elif defined(CONFIG_BCM7344)
+
+	PINMUX(15, gpio_79, 1);		/* MoCA link */
+	PINMUX(15, gpio_80, 1);		/* MoCA activity */
+
+	PINMUX(17, uart_rxdb, 0);	/* UARTB RX */
+	PINMUX(17, uart_txdb, 0);	/* UARTB TX */
+
+	PINMUX(0, gpio_68, 3);		/* SDIO */
+	PINMUX(0, gpio_69, 3);
+	PINMUX(0, gpio_70, 3);
+	PINMUX(0, gpio_71, 2);
+	PINMUX(0, gpio_72, 2);
+	PINMUX(0, gpio_73, 2);
+	PINMUX(0, gpio_74, 2);
+	PINMUX(0, gpio_75, 2);
+	PINMUX(1, gpio_76, 2);
+	PINMUX(1, gpio_77, 2);
+
+	/* enable pullup on SDIO lines */
+	PADCTRL(0, gpio_68_pad_ctrl, 2);
+	PADCTRL(0, gpio_69_pad_ctrl, 2);
+	PADCTRL(0, gpio_70_pad_ctrl, 2);
+	PADCTRL(0, gpio_71_pad_ctrl, 2);
+	PADCTRL(0, gpio_72_pad_ctrl, 2);
+	PADCTRL(0, gpio_73_pad_ctrl, 2);
+	PADCTRL(0, gpio_74_pad_ctrl, 2);
+	PADCTRL(0, gpio_75_pad_ctrl, 2);
+	PADCTRL(0, gpio_76_pad_ctrl, 2);
+	PADCTRL(0, gpio_77_pad_ctrl, 2);
+
+	AON_PINMUX(0, aon_gpio_00, 3);	/* UARTC RX (NC) */
+	AON_PINMUX(0, aon_gpio_01, 3);	/* UARTC TX (NC) */
+
+	PINMUX(16, sgpio_04, 1);	/* MoCA I2C */
+	PINMUX(16, sgpio_05, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCD_REG_START);
+
+	/* 7344 is normally MidRF, but some 7418 boards are HighRF */
+	if (strstarts(brcm_cfe_boardname, "BCM97418SAT") ||
+	    strstarts(brcm_cfe_boardname, "BCM97418SFF_RVU"))
+		brcm_moca_rf_band = MOCA_BAND_MIDRF;
+	else if (strstarts(brcm_cfe_boardname, "BCM97418"))
+		brcm_moca_rf_band = MOCA_BAND_HIGHRF;
+
+#elif defined(CONFIG_BCM7346)
+
+	PINMUX(15, gpio_068, 2);	/* MoCA link */
+	PINMUX(16, gpio_069, 1);	/* MoCA activity */
+
+	PINMUX(9, gpio_017, 1);		/* UARTB TX */
+	PINMUX(9, gpio_018, 1);		/* UARTB RX */
+	PINMUX(10, gpio_021, 1);	/* UARTC TX */
+	PINMUX(10, gpio_022, 1);	/* UARTC RX */
+
+	PINMUX(16, sgpio_02, 1);	/* MoCA I2C on BSCB */
+	PINMUX(16, sgpio_03, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
+
+	/*
+	 * To enable SDIO_LED (activity LED) on the BCM97346 reference boards:
+	 * install R1127, remove R1120, uncomment this line, and don't use MoCA
+	 */
+	/* PINMUX(16, sgpio_02, 3); */
+
+	PINMUX(17, vo_656_5, 2);	/* SDIO_PRES */
+	PINMUX(17, vo_656_4, 1);	/* SDIO_PWR0 */
+	PINMUX(17, vo_656_3, 2);	/* SDIO_DAT3 */
+	PINMUX(17, vo_656_2, 2);	/* SDIO_DAT1 */
+	PINMUX(17, vo_656_1, 2);	/* SDIO_DAT1 */
+	PINMUX(17, vo_656_0, 2);	/* SDIO_DAT0 */
+
+	PINMUX(18, vo_656_clk, 1);	/* SDIO_CLK */
+	PINMUX(18, vo_656_7, 1);	/* SDIO_CMD */
+	PINMUX(18, vo_656_6, 2);	/* SDIO_WPROT */
+
+#elif	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+
+    #if !defined(CONFIG_DREAMBOX_DM520)
+	PINMUX(11, gpio_89, 1);		/* UARTB TX */
+	PINMUX(11, gpio_90, 1);		/* UARTB RX */
+	PINMUX(11, gpio_91, 1);		/* UARTC TX */
+	PINMUX(11, gpio_92, 1);		/* UARTC RX */
+
+	AON_PINMUX(1, aon_gpio_08, 6);	/* SDIO */
+	AON_PINMUX(1, aon_gpio_12, 5);
+	AON_PINMUX(1, aon_gpio_13, 5);
+	AON_PINMUX(2, aon_gpio_14, 4);
+	AON_PINMUX(2, aon_gpio_15, 5);
+	AON_PINMUX(2, aon_gpio_16, 5);
+	AON_PINMUX(2, aon_gpio_17, 5);
+	AON_PINMUX(2, aon_gpio_18, 5);
+	AON_PINMUX(2, aon_gpio_19, 5);
+	AON_PINMUX(2, aon_gpio_20, 5);
+
+	/* enable SDIO pullups */
+	AON_PADCTRL(0, aon_gpio_08_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+    #else
+	/* add dm520 specific pinmux needed for kernel here... */
+    #endif
+
+#elif defined(CONFIG_BCM7425)
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	if (!sdio_0_disabled) {
+		PINMUX(14, gpio_072, 2);
+		PINMUX(14, gpio_073, 2);
+		PINMUX(14, gpio_074, 2);
+		PINMUX(14, gpio_075, 2);
+		PINMUX(15, gpio_076, 2);
+		PINMUX(15, gpio_077, 2);
+		PINMUX(15, gpio_078, 2);
+		PINMUX(15, gpio_079, 2);
+		PINMUX(15, gpio_080, 2);
+		PINMUX(15, gpio_081, 2);
+
+		/* enable internal pullups */
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_072_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_073_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_074_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_075_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_076_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_077_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_078_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_079_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_080_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			gpio_081_pad_ctrl, 2);
+
+		/* always use 3.3V (SDIO0_LOW_V_SEL_N=1) */
+		/* V00 boards or A0 parts */
+		BDEV_UNSET(BCHP_GIO_AON_IODIR_LO, 1 << 4);
+		BDEV_SET(BCHP_GIO_AON_DATA_LO, 1 << 4);
+		/* V10 boards with B parts use SDIO0_VOLT signal */
+		AON_PINMUX(2, gpio_100, 5);
+	}
+
+	PINMUX(18, sgpio_00, 1);	/* MoCA I2C */
+	PINMUX(19, sgpio_01, 1);
+#if defined(CONFIG_BCM7425B0)
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCC_REG_START);
+#else
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCA_REG_START);
+#endif
+
+#elif defined(CONFIG_BCM7435)
+
+#if 0
+	PINMUX(16, gpio_088, 1);        /* MoCA LEDs */
+	PINMUX(16, gpio_087, 1);
+
+	PINMUX(18, sgpio_00, 1);        /* MoCA I2C */
+	PINMUX(19, sgpio_01, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCC_REG_START);
+#endif
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	/* always enabled because of dm820/dm7080 fastboot */
+	if (1 || !sdio_0_disabled) {
+		PINMUX(14, gpio_072, 2);
+		PINMUX(14, gpio_073, 2);
+		PINMUX(14, gpio_074, 2);
+		PINMUX(14, gpio_075, 2);
+		PINMUX(15, gpio_076, 2);
+		PINMUX(15, gpio_077, 2);
+		PINMUX(15, gpio_078, 2);
+		PINMUX(15, gpio_079, 2);
+		PINMUX(15, gpio_080, 2);
+		PINMUX(15, gpio_081, 2);
+
+		/* enable internal pullups */
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_072_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_073_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_074_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_075_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_076_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_077_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_078_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_079_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_080_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
+			     gpio_081_pad_ctrl, 2);
+
+		/* SDIO0_VOLT signal */
+//		AON_PINMUX(2, gpio_100, 5);
+	}
+
+	/* set RGMII lines to 2.5V */
+	BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0, rgmii_0_pad_sel, 1);
+
+	/* If GENET_0 is not configured for internal mode, set
+	 * the pins in EMAC0_ mode
+	 */
+	if (strcmp(brcm_eth0_phy, "INT")) {
+		PINMUX(5, gpio_003, 1);	/* RX_EN_CTL */
+		PINMUX(5, gpio_002, 1); /* RX_CLK */
+		PINMUX(5, gpio_001, 1); /* ENET_LINK */
+		PINMUX(5, gpio_000, 1); /* ENET_ACTIVITY */
+		PINMUX(6, gpio_011, 1); /* TXD_01 */
+		PINMUX(6, gpio_010, 1); /* TXD_00 */
+		PINMUX(6, gpio_009, 1); /* TX_EN_CTL */
+		PINMUX(6, gpio_008, 1); /* TX_CLK */
+		PINMUX(6, gpio_007, 1); /* RXD_03 */
+		PINMUX(6, gpio_006, 1); /* RXD_02 */
+		PINMUX(6, gpio_005, 1); /* RXD_01 */
+		PINMUX(6, gpio_004, 1); /* RXD_00 */
+		PINMUX(7, gpio_015, 2); /* EMAC0_MDC */
+		PINMUX(7, gpio_014, 2); /* EMAC0_MDIO */
+		PINMUX(7, gpio_013, 1); /* TXD_03 */
+		PINMUX(7, gpio_012, 1); /* TXD_02 */
+	}
+
+
+#elif defined(CONFIG_BCM7429)
+
+	PINMUX(11, gpio_094, 1);	/* UARTB TX */
+	PINMUX(11, gpio_095, 1);	/* UARTB RX */
+	PINMUX(12, gpio_096, 1);	/* UARTC TX */
+	PINMUX(12, gpio_097, 1);	/* UARTC RX */
+
+	AON_PINMUX(1, aon_gpio_11, 7);	/* MoCA LEDs */
+	AON_PINMUX(2, aon_gpio_14, 5);
+
+	PINMUX(18, sgpio_00, 1);	/* MoCA I2C */
+	PINMUX(18, sgpio_01, 1);
+	brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCD_REG_START);
+
+	if (sdio_0_disabled < 0)
+		/* Bootloader indicates availability of SDIO_0 in SCRATCH reg */
+		sdio_0_disabled = BDEV_RD(SDIO_CFG_REG(0, SCRATCH)) & 0x01;
+
+	if (!sdio_0_disabled) {
+		/*
+		 * 7241[5] uses GPIO_092 for UART_TX0 instead of SDIO0_VCTL so
+		 * leave it alone. We don't need SDIO0_VCTL because the board
+		 * is 3.3V only and doesn't use it.
+		 */
+		if (!(BRCM_PROD_ID() == 0x7241 ||
+		      BRCM_PROD_ID() == 0x7242 ||
+		      BRCM_PROD_ID() == 0x72415 ||
+		      BRCM_PROD_ID() == 0x72425))
+			PINMUX(11, gpio_092, 5);
+		PINMUX(14, gpio_122, 1);
+		PINMUX(14, gpio_123, 1);
+		PINMUX(14, gpio_124, 1);
+		PINMUX(15, gpio_125, 1);
+		PINMUX(15, gpio_126, 1);
+		PINMUX(15, gpio_127, 1);
+		PINMUX(15, gpio_128, 1);
+		PINMUX(15, gpio_129, 1);
+		PINMUX(15, gpio_131, 1);
+		/*
+		 * 7428[5] pinout uses GPIO_93 for SDIO0_PRES
+		 * 7429[5] pinout uses GPIO_130 for SDIO0_PRES
+		 */
+		if (BRCM_PROD_ID() == 0x7428 || BRCM_PROD_ID() == 0x74285) {
+			PINMUX(11, gpio_093, 5);
+		} else
+			PINMUX(15, gpio_130, 1);
+
+		/* enable internal pullups */
+		if (!(BRCM_PROD_ID() == 0x7241 ||
+		      BRCM_PROD_ID() == 0x7242 ||
+		      BRCM_PROD_ID() == 0x72415 ||
+		      BRCM_PROD_ID() == 0x72425))
+			BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6,
+						 gpio_092_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_122_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_123_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_124_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_125_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_126_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_127_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_128_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8,
+			gpio_129_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_130_pad_ctrl, 2);
+		BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
+			gpio_131_pad_ctrl, 2);
+	}
+
+	if (sdio_1_disabled < 0)
+		/* Bootloader indicates availability of SDIO_1 in SCRATCH reg */
+		sdio_1_disabled = BDEV_RD(SDIO_CFG_REG(1, SCRATCH)) & 0x01;
+
+	if (!sdio_1_disabled)
+		/* default SDIO1 to eMMC */
+		BDEV_SET(BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL, 0x00000001);
+
+	/* GENET_1 is connected to BCM60321 via EXT_MII on BCM97241PLC
+	 * and GENET_1 is connected to a BCM53101 on BCM97241DCSFBTSFF
+	 */
+	if (!strcmp(brcm_cfe_boardname, "BCM97241PLC") ||
+		!strcmp(brcm_cfe_boardname, "BCM97241DCSFBTSFF")) {
+		/* set GENET_1 MII pinmuxing */
+		PINMUX(15, gpio_132, 1);	/* MII_RX_DV */
+		PINMUX(16, gpio_133, 1);	/* MII_RX_ER */
+		PINMUX(16, gpio_134, 1);	/* MII_RX_CLK */
+		PINMUX(16, gpio_135, 1);	/* MII_COL */
+		PINMUX(16, gpio_136, 1);	/* MII_CRS */
+		PINMUX(16, gpio_137, 1);	/* MII_MDIO */
+		PINMUX(16, gpio_138, 1);	/* MII_TX_CLK */
+		PINMUX(16, gpio_139, 1);	/* MII_RXD_03 */
+		PINMUX(16, gpio_140, 1);	/* MII_RXD_02 */
+		PINMUX(17, gpio_141, 1);	/* MII_RXD_01 */
+		PINMUX(17, gpio_142, 1);	/* MII_RXD_00 */
+		PINMUX(17, gpio_143, 1);	/* MII_TXD_03 */
+		PINMUX(17, gpio_144, 1);	/* MII_TXD_02 */
+		PINMUX(17, gpio_145, 1);	/* MII_TXD_01 */
+		PINMUX(17, gpio_146, 1);	/* MII_TXD_00 */
+		PINMUX(17, gpio_147, 1);	/* MII_TX_EN */
+		PINMUX(17, gpio_148, 1);	/* MII_TX_ER */
+		PINMUX(18, gpio_149, 1);	/* MII_MDC */
+
+		/* Switch MII control over GENET_1 */
+		BDEV_WR(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0,
+			(BDEV_RD(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0) |
+			BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK));
+
+		/*
+		 * BCM60321 firmware will snoop MII bus, but avoid any MDIO
+		 * transaction to be safe. The same applies for the BCM53101.
+		 */
+		genet_pdata[1].phy_interface = PHY_INTERFACE_MODE_MII;
+		genet_pdata[1].phy_address = 0;
+		genet_pdata[1].phy_speed = 100;
+
+		if (!strcmp(brcm_cfe_boardname, "BCM97241DCSFBTSFF"))
+			genet_pdata[1].sw_type = 0x53101;
+	}
+
+#elif defined(CONFIG_BCM7563)
+
+	/* NOTE: UARTB and UARTC are disabled by default */
+
+	AON_PINMUX(0, aon_gpio_01, 1);		/* ENET link */
+	PINMUX(4, gpio_105, 1);			/* ENET activity */
+
+	/* SDIO pinmux + pullups */
+	AON_PINMUX(1, aon_gpio_08, 6);
+	AON_PINMUX(1, aon_gpio_12, 5);
+	AON_PINMUX(1, aon_gpio_13, 5);
+	AON_PINMUX(2, aon_gpio_14, 5);
+	AON_PINMUX(2, aon_gpio_15, 5);
+	AON_PINMUX(2, aon_gpio_16, 5);
+	AON_PINMUX(2, aon_gpio_17, 5);
+	AON_PINMUX(2, aon_gpio_18, 5);
+	AON_PINMUX(2, aon_gpio_19, 5);
+	AON_PINMUX(2, aon_gpio_20, 5);
+
+	AON_PADCTRL(0, aon_gpio_08_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+	AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+
+/*
+ * 75525 workarounds are needed because the RDB has changed but
+ * 75525 support is done using ALT_CHIP_ID() for the 7563 which
+ * means we can't included the proper RDB header files.
+ * 1. Locally define the new SD_PIN_SEL register.
+ * 2. The BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 has a new field,
+ *    "sdio1_alt_pin_sel", which needs to be cleared when
+ *    selecting the AON pins via pinmux.
+ */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL 0x00410354
+	if (BRCM_CHIP_ID() == 0x75525) {
+		BDEV_WR(SDIO_CFG_REG(0, SD_PIN_SEL), 0x00000002);
+		BDEV_UNSET(BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0, 0x00000001);
+	}
+#elif defined(CONFIG_BCM7584)
+
+	if (BRCM_PROD_ID() == 0x7583) {
+		/* 7583 ballout - SD card on alt pins, GENET_1 disabled */
+		AON_PINMUX(1, aon_gpio_12, 5);
+		AON_PINMUX(1, aon_gpio_13, 5);
+		AON_PINMUX(2, aon_gpio_14, 4);
+		AON_PINMUX(2, aon_gpio_15, 5);
+		AON_PINMUX(2, aon_gpio_16, 5);
+		AON_PINMUX(2, aon_gpio_17, 5);
+		AON_PINMUX(2, aon_gpio_18, 5);
+		AON_PINMUX(2, aon_gpio_19, 5);
+		AON_PINMUX(2, aon_gpio_20, 5);
+
+		AON_PADCTRL(1, aon_gpio_12_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_13_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_14_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_15_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_16_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_17_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_18_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_19_pad_ctrl, 2);
+		AON_PADCTRL(1, aon_gpio_20_pad_ctrl, 2);
+	} else {
+		/* external BCM3349 on GENET_1 using reverse MII */
+		PINMUX(0, gpio_00, 2);
+		PINMUX(0, gpio_01, 2);
+		PINMUX(0, gpio_02, 2);
+		PINMUX(1, gpio_03, 2);
+		PINMUX(1, gpio_04, 2);
+		PINMUX(1, gpio_05, 2);
+		PINMUX(1, gpio_06, 2);
+		PINMUX(1, gpio_07, 2);
+		PINMUX(1, gpio_08, 2);
+		PINMUX(1, gpio_09, 2);
+		PINMUX(1, gpio_10, 2);
+		PINMUX(2, gpio_11, 2);
+		PINMUX(2, gpio_12, 2);
+		PINMUX(2, gpio_13, 2);
+		PINMUX(2, gpio_14, 2);
+		PINMUX(13, gpio_110, 1);
+
+		/* no MDIO in RvMII mode; avoid driving these pins */
+		PINMUX(15, gpio_123, 0);
+		PINMUX(15, gpio_124, 0);
+
+		/* no pulldowns on MII */
+		PADCTRL(0, gpio_00_pad_ctrl, 0);
+		PADCTRL(0, gpio_01_pad_ctrl, 0);
+		PADCTRL(0, gpio_02_pad_ctrl, 0);
+		PADCTRL(0, gpio_03_pad_ctrl, 0);
+		PADCTRL(0, gpio_04_pad_ctrl, 0);
+		PADCTRL(0, gpio_05_pad_ctrl, 0);
+		PADCTRL(0, gpio_06_pad_ctrl, 0);
+		PADCTRL(0, gpio_07_pad_ctrl, 0);
+		PADCTRL(0, gpio_08_pad_ctrl, 0);
+		PADCTRL(1, gpio_09_pad_ctrl, 0);
+		PADCTRL(1, gpio_10_pad_ctrl, 0);
+		PADCTRL(1, gpio_11_pad_ctrl, 0);
+		PADCTRL(1, gpio_12_pad_ctrl, 0);
+		PADCTRL(1, gpio_13_pad_ctrl, 0);
+		PADCTRL(1, gpio_14_pad_ctrl, 0);
+		PADCTRL(7, gpio_110_pad_ctrl, 0);
+		PADCTRL(8, gpio_123_pad_ctrl, 0);
+		PADCTRL(8, gpio_124_pad_ctrl, 0);
+
+		genet_pdata[1].phy_interface = PHY_INTERFACE_MODE_REVMII;
+		genet_pdata[1].phy_address = 0;
+		genet_pdata[1].phy_speed = 100;
+
+		/* SD card mux + pullups */
+		PINMUX(14, gpio_112, 3);
+		PINMUX(14, gpio_113, 3);
+		PINMUX(14, gpio_114, 3);
+		PINMUX(14, gpio_115, 3);
+		PINMUX(14, gpio_116, 3);
+		PINMUX(14, gpio_117, 3);
+		PINMUX(14, gpio_118, 3);
+		PINMUX(15, gpio_119, 3);
+		PINMUX(15, gpio_120, 3);
+		PINMUX(15, gpio_121, 3);
+		PINMUX(15, gpio_122, 3);
+
+		PADCTRL(7, gpio_112_pad_ctrl, 2);
+		PADCTRL(7, gpio_113_pad_ctrl, 2);
+		PADCTRL(7, gpio_114_pad_ctrl, 2);
+		PADCTRL(7, gpio_115_pad_ctrl, 2);
+		PADCTRL(7, gpio_116_pad_ctrl, 2);
+		PADCTRL(7, gpio_117_pad_ctrl, 2);
+		PADCTRL(8, gpio_118_pad_ctrl, 2);
+		PADCTRL(8, gpio_119_pad_ctrl, 2);
+		PADCTRL(8, gpio_120_pad_ctrl, 2);
+		PADCTRL(8, gpio_121_pad_ctrl, 2);
+		PADCTRL(8, gpio_122_pad_ctrl, 2);
+	}
+
+	PINMUX(11, gpio_89, 1);		/* UARTB TX */
+	PINMUX(11, gpio_90, 1);		/* UARTB RX */
+
+	AON_PINMUX(1, aon_gpio_07, 4);	/* UARTC RX */
+	AON_PINMUX(1, aon_gpio_09, 4);	/* UARTC TX */
+
+	AON_PINMUX(0, aon_gpio_01, 1);	/* ENET link */
+	PINMUX(13, gpio_105, 1);	/* ENET activity */
+
+	/* Bootloader indicates disable of SDIO_1 in SCRATCH reg */
+	if ((BDEV_RD(SDIO_CFG_REG(1, SCRATCH)) & 0x01) == 0)
+		/* Set SDIO1 to eMMC */
+		BDEV_SET(BCHP_HIF_TOP_CTRL_EMMC_PIN_CTRL, 0x00000001);
+
+#endif /* chip type */
+#if defined(BCHP_SDIO_1_BOOT_REG_START)
+	BDEV_UNSET(BCHP_SDIO_1_BOOT_REG_START, 1);
+#endif
+#endif /* !defined(CONFIG_BRCM_IKOS) */
+}
+
+/***********************************************************************
+ * FLASH configuration
+ ***********************************************************************/
+
+#if defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS)
+
+static struct mtd_partition fixed_partition_map[] = {
+	{
+		.name = "entire_device",
+		.size = MTDPART_SIZ_FULL,
+		.offset = 0x00000000,
+    #if defined(CONFIG_DREAMBOX)
+		.mask_flags = MTD_WRITEABLE,
+	}, {
+		.name = "bootloader",
+		.size = 0x00100000,
+		.offset = 0x00000000,
+		.mask_flags = MTD_WRITEABLE,
+	}, {
+		.name = "recovery",
+		.size = MTDPART_SIZ_FULL,
+		.offset = 0x00100000,
+    #endif
+	},
+};
+
+/*
+ * Use the partition map defined at compile time
+ */
+int __init board_get_partition_map(struct mtd_partition **p)
+{
+	*p = fixed_partition_map;
+	return ARRAY_SIZE(fixed_partition_map);
+}
+
+#else /* defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS) */
+
+/*
+ * Construct the partition map for the primary flash device, based on
+ * CFE environment variables that were read from prom.c
+ *
+ * Note that this does NOT have all of the partitions that CFE recognizes
+ * (e.g. macadr, nvram).  It only has the rootfs, entire_device, and
+ * optionally the kernel image partition.
+ */
+int __init board_get_partition_map(struct mtd_partition **p)
+{
+	struct mtd_partition *ret;
+	int nr_parts;
+
+	if (brcm_mtd_rootfs_len == 0)
+		return -ENODEV;
+
+	nr_parts = 2;
+	if (brcm_mtd_kernel_len != 0)
+		nr_parts++;
+
+	ret = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL);
+	if (!ret)
+		return -ENOMEM;
+
+	ret[0].offset = brcm_mtd_rootfs_start;
+	ret[0].size = brcm_mtd_rootfs_len;
+	ret[0].name = "rootfs";
+
+	ret[1].offset = 0;
+	ret[1].size = MTDPART_SIZ_FULL;
+	ret[1].name = "entire_device";
+
+	if (brcm_mtd_kernel_len != 0) {
+		ret[2].offset = brcm_mtd_kernel_start;
+		ret[2].size = brcm_mtd_kernel_len;
+		ret[2].name = "kernel";
+	}
+
+	*p = ret;
+	return nr_parts;
+}
+#endif /* defined(CONFIG_BRCM_FIXED_MTD_PARTITIONS) */
+
+void brcm_get_ocap_info(struct brcm_ocap_info *info)
+{
+	info->ocap_part_start = brcm_mtd_ocap_start;
+	info->ocap_part_len = brcm_mtd_ocap_len;
+	info->docsis_platform = brcm_docsis_platform;
+}
+EXPORT_SYMBOL(brcm_get_ocap_info);
diff --git a/drivers/brcmstb/m2m.c b/drivers/brcmstb/m2m.c
new file mode 100644
index 000000000000..61ce3bbd754b
--- /dev/null
+++ b/drivers/brcmstb/m2m.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#ifdef BCHP_MEM_DMA_0_CTRL
+
+struct brcm_mem_dma_descr {
+	u32     read_addr;
+	u32     write_addr;
+	u32     word[6];
+};
+
+#define DESCR_WORD2     0
+#define DESCR_WORD3     1
+#define DESCR_WORD4     2
+
+#define BRCM_MEM_DMA_TIMEOUT	(0)	/* no timeout */
+
+#define BRCM_MEM_DMA_DEBUG	(0)
+
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer);
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer);
+static void brcm_mem_dma_start_transfer(void);
+
+#if BRCM_MEM_DMA_DEBUG
+#define DBG			printk
+static void brcm_mem_dma_dump_regs(const char *title)
+{
+	printk(KERN_DEBUG "=== MEM DMA registers ===\n");
+	printk(KERN_DEBUG
+	       "FIRST_DESC = 0x%08x CTRL       = 0x%08x WAKE_CTRL  = 0x%08x\n",
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_FIRST_DESC),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CTRL),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_WAKE_CTRL));
+	printk(KERN_DEBUG
+	       "STATUS     = 0x%08x CUR_DESC   = 0x%08x CUR_BYTE   = 0x%08x\n",
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_STATUS),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CUR_DESC),
+	       (unsigned int)BDEV_RD(BCHP_MEM_DMA_0_CUR_BYTE));
+}
+
+static void brcm_mem_dma_dump_descr(struct brcm_mem_dma_descr *d, int num)
+{
+	int index = 0, last = 0;
+	printk(KERN_DEBUG "=== MEM DMA descriptors [%p] ===\n", d);
+	do {
+		last = d->word[DESCR_WORD2] &
+			BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+		printk(KERN_DEBUG "[%02d]: s  = 0x%08x d  = 0x%08x "
+			"w2 = 0x%08x w3 = 0x%08x w4 = 0x%08x\n",
+			index++, d->read_addr, d->write_addr,
+			d->word[0], d->word[1], d->word[2]);
+		d++;
+		if (!--num)
+			break;
+	} while (!last);
+}
+#else
+#define DBG(...)		do { } while (0)
+static inline void brcm_mem_dma_dump_regs(const char *title) {}
+static inline void brcm_mem_dma_dump_descr(struct brcm_mem_dma_descr *d,
+	int num) {}
+#endif
+
+/***********************************************************************
+ * Low-level M2M utilities
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_raddr(struct brcm_mem_dma_descr *descr,
+	u32 addr)
+{
+	descr->read_addr = addr;
+}
+
+static inline void brcm_mem_dma_set_waddr(struct brcm_mem_dma_descr *descr,
+	u32 addr)
+{
+	descr->write_addr = addr;
+}
+
+/***********************************************************************
+ * Enable/disable completion interrupt for descriptor
+ ***********************************************************************/
+static inline void brcm_mem_dma_interrupt_enable(
+	struct brcm_mem_dma_descr *descr, int enable)
+{
+	if (enable)
+		descr->word[DESCR_WORD2] |=
+			BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK;
+	else
+		descr->word[DESCR_WORD2] &=
+			~BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK;
+}
+
+/***********************************************************************
+ * Set transfer size for descriptor
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_xfer_size(struct brcm_mem_dma_descr *descr,
+	u32 len)
+{
+	len &= BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK;
+	descr->word[DESCR_WORD2] &=
+		~BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK;
+	descr->word[DESCR_WORD2] |= len;
+}
+
+/***********************************************************************
+ * Link to the next descriptor
+ * next - virtual address of the descriptor to link with
+ ***********************************************************************/
+static inline void brcm_mem_dma_link_next(struct brcm_mem_dma_descr *descr,
+	struct brcm_mem_dma_descr *next)
+{
+	u32 pa_next = 0;
+
+	if (next) {
+		pa_next = virt_to_phys(next) &
+			BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK;
+		descr->word[DESCR_WORD2] &= ~BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+	} else
+		descr->word[DESCR_WORD2] |= BCHP_MEM_DMA_DESC_WORD2_LAST_MASK;
+
+	descr->word[DESCR_WORD3] &=
+		~BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK;
+	descr->word[DESCR_WORD3] |= pa_next;
+
+}
+
+/***********************************************************************
+ * Configure SCRAM
+ * TODO: encoder/decoder init bit ???
+ ***********************************************************************/
+static inline void brcm_mem_dma_set_scram(struct brcm_mem_dma_descr *descr,
+	int enable, int start, int end, int mode, u8 slot, int init)
+{
+	u32 word4 = 0;
+	word4 |= enable ? BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK : 0;
+	word4 |= start  ? BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK : 0;
+	word4 |= end    ? BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK : 0;
+	word4 |= (mode << BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT) &
+		BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK;
+	word4 |= (slot * 6) & BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK;
+
+	if (mode && init)
+		word4 |= BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK;
+
+	descr->word[DESCR_WORD4] = word4;
+}
+
+/***********************************************************************
+ * Poll for transfer completion
+ ***********************************************************************/
+static int brcm_mem_dma_wait_for_ready(int timeout)
+{
+	while (BDEV_RD_F(MEM_DMA_0_STATUS, DMA_STATUS) == 1) {
+		if (timeout > 0)
+			if (!--timeout)
+				return -1;
+		mdelay(1);
+	}
+	return 0;
+}
+
+static int brcm_mem_dma_num_descriptors(struct brcm_mem_transfer *xfer)
+{
+	int xfer_cnt = 0;
+
+	do {
+		xfer_cnt++;
+	} while ((xfer = xfer->next));
+
+	return xfer_cnt;
+}
+
+/***********************************************************************
+ * Generate descriptor according to transfer request
+ * Returns 0 on success, -1 on incorrect request parameters
+ ***********************************************************************/
+static int brcm_mem_dma_gen_descriptor(struct brcm_mem_transfer *xfer,
+	struct brcm_mem_dma_descr *d, int index, int total)
+{
+	int last = index == total - 1;
+
+	/* sanity checks */
+	if (xfer->len > 0x1000000) {
+		printk(KERN_ERR "MEM DMA "
+			"does not support transfers bigger than 16 MByte\n");
+		return -1;
+	}
+	if ((xfer->pa_dst > xfer->pa_src) &&
+	    (xfer->pa_dst < (xfer->pa_src + xfer->len))) {
+		printk(KERN_ERR "MEM DMA "
+		"does not support overlapping read-write regions\n");
+		return -1;
+	}
+
+	/* set up mem-dma descriptor */
+	brcm_mem_dma_set_raddr(d, xfer->pa_src);
+	brcm_mem_dma_set_waddr(d, xfer->pa_dst);
+	brcm_mem_dma_set_xfer_size(d, xfer->len);
+	brcm_mem_dma_set_scram(d, 1, index == 0, last,
+		xfer->mode, xfer->key, index == 0);
+	brcm_mem_dma_link_next(d, last ? NULL : d + 1);
+
+	return 0;
+}
+
+/***********************************************************************
+ * If caller remapped the buffers, it set pa_src and pa_dst fields
+ * of transfer request. If these fields are not set, we need to remap
+ * them here.
+ * To properly unmap the buffers after the transfer, set bit flags
+ * in the transfer if we are doing remapping. Caller should never touch
+ * these flags.
+ ***********************************************************************/
+static int brcm_mem_dma_map_buffers(struct brcm_mem_transfer *xfer)
+{
+	if (!xfer->len)
+		return -1;
+
+	if (!xfer->pa_src && !xfer->pa_dst && (xfer->src == xfer->dst)) {
+		xfer->pa_dst = xfer->pa_src =
+			dma_map_single(NULL, xfer->src, xfer->len,
+				DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(NULL, xfer->pa_dst))
+			return -1;
+		xfer->src_dst_remapped = 1;
+	}
+
+	if (!xfer->pa_src) {
+		xfer->pa_src = dma_map_single(NULL, xfer->src, xfer->len,
+			DMA_TO_DEVICE);
+		if (dma_mapping_error(NULL, xfer->pa_src))
+			return -1;
+		xfer->src_remapped = 1;
+	}
+
+	if (!xfer->pa_dst) {
+		xfer->pa_dst = dma_map_single(NULL, xfer->dst, xfer->len,
+			DMA_FROM_DEVICE);
+		if (dma_mapping_error(NULL, xfer->pa_dst))
+			return -1;
+		xfer->dst_remapped = 1;
+	}
+
+	return 0;
+}
+
+/***********************************************************************
+ * Unmap the buffers if we mapped them before
+ ***********************************************************************/
+static void brcm_mem_dma_unmap_buffers(struct brcm_mem_transfer *xfer)
+{
+	if (xfer->src_dst_remapped) {
+		dma_unmap_single(NULL, xfer->pa_src, xfer->len,
+				DMA_BIDIRECTIONAL);
+		return;
+	}
+
+	if (xfer->src_remapped) {
+		dma_unmap_single(NULL, xfer->pa_src, xfer->len,
+			DMA_TO_DEVICE);
+	}
+	if (xfer->dst_remapped) {
+		dma_unmap_single(NULL, xfer->pa_dst, xfer->len,
+			DMA_FROM_DEVICE);
+	}
+}
+
+/***********************************************************************
+ * Map the descriptors and write the first descriptor address to the
+ * M2M register. Do not initiate transfer yet.
+ ***********************************************************************/
+static dma_addr_t brcm_mem_dma_prepare_descriptors(
+	struct brcm_mem_dma_descr *d, int size)
+{
+	dma_addr_t pa_d;
+	pa_d = dma_map_single(NULL, d, size, DMA_TO_DEVICE);
+	brcm_mem_dma_wait_for_ready(0);
+	BDEV_WR_RB(BCHP_MEM_DMA_0_FIRST_DESC, pa_d);
+
+	return pa_d;
+}
+
+/***********************************************************************
+ * Unmap the descriptor after completion
+ ***********************************************************************/
+static void brcm_mem_dma_free_descriptors(dma_addr_t pa, int size)
+{
+	brcm_mem_dma_wait_for_ready(0);
+	dma_unmap_single(NULL, pa, size, DMA_TO_DEVICE);
+}
+
+static struct brcm_mem_dma_descr *cur_descr;
+static int cur_total_size;
+static dma_addr_t cur_pa_d;
+
+/***********************************************************************
+ * _brcm_mem_dma_start_transfer
+ * Initiate M2M transfer. If sync is set, wait for completion with timeout.
+ ***********************************************************************/
+static void _brcm_mem_dma_start_transfer(int on, int sync)
+{
+	/* clear RUN bit and wait for IDLE */
+	BDEV_WR_F_RB(MEM_DMA_0_CTRL, RUN, 0);
+	brcm_mem_dma_wait_for_ready(BRCM_MEM_DMA_TIMEOUT);
+
+	if (on) {
+		BDEV_WR_F_RB(MEM_DMA_0_CTRL, RUN, 1);
+		if (sync)
+			brcm_mem_dma_wait_for_ready(BRCM_MEM_DMA_TIMEOUT);
+	}
+}
+
+/***********************************************************************
+ * brcm_mem_dma_start_transfer
+ * Initiate M2M transfer
+ ***********************************************************************/
+static void brcm_mem_dma_start_transfer(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	_brcm_mem_dma_start_transfer(1, 1);
+}
+
+/***********************************************************************
+ * brcm_mem_dma_prepare_transfer
+ * Generates mem dma descriptors, flushes them to memory
+ * and sets up M2M registers, but _DOES NOT_ initiate the transfer.
+ * Use brcm_mem_dma_start_transfer() to start transfer/encoding
+ * This allows S3 standby code to be sure code does not attempt to change
+ * memory content after it has been encoded
+ ***********************************************************************/
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer)
+{
+	int xfer_cnt = brcm_mem_dma_num_descriptors(xfer);
+	int total_size = xfer_cnt * sizeof(struct brcm_mem_dma_descr);
+	int index = 0;
+	struct brcm_mem_transfer *save_xfer = xfer;
+	struct brcm_mem_dma_descr *d =
+		kzalloc(total_size, GFP_ATOMIC), *cur_d;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	WARN_ON(cur_descr);
+
+	if (unlikely(!d))
+		return -1;
+
+	cur_descr = cur_d = d;
+
+	do {
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			printk(KERN_ERR "%s: cannot map buffers", __func__);
+			goto _error;
+		}
+
+		if (brcm_mem_dma_gen_descriptor(xfer, cur_d,
+		    index++, xfer_cnt)) {
+			printk(KERN_ERR "%s: cannot generate descr", __func__);
+			goto _error;
+		}
+
+		xfer = xfer->next;
+		cur_d++;
+	} while (xfer);
+
+	brcm_mem_dma_dump_descr(d, xfer_cnt);
+	/* flush the descriptors */
+	cur_pa_d = brcm_mem_dma_prepare_descriptors(d, total_size);
+	cur_total_size = total_size;
+
+	return 0;
+
+_error:
+	brcm_mem_dma_complete_transfer(save_xfer);
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_complete_transfer
+ * Must be called after M2M transfer was complete
+ * Unmaps everything that was mapped in brcm_mem_dma_prepare_transfer,
+ * frees up all memory
+ ***********************************************************************/
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer)
+{
+	WARN_ON(cur_descr == NULL);
+	WARN_ON(!cur_pa_d);
+	WARN_ON(!cur_total_size);
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	/* clear RUN bit and wait for IDLE */
+	_brcm_mem_dma_start_transfer(0, 1);
+
+	brcm_mem_dma_free_descriptors(cur_pa_d, cur_total_size);
+
+	do {
+		brcm_mem_dma_unmap_buffers(xfer);
+		xfer = xfer->next;
+	} while (xfer);
+
+	kfree(cur_descr);
+
+	cur_descr = NULL;
+	cur_total_size = 0;
+	cur_pa_d = 0;
+
+	return 0;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_simple_transfer
+ * Initiates a single M2M tranfser according to transfer request
+ ***********************************************************************/
+int brcm_mem_dma_simple_transfer(struct brcm_mem_transfer *xfer)
+{
+	int retval = 0;
+	struct brcm_mem_dma_descr *d =
+		kzalloc(sizeof(struct brcm_mem_dma_descr), GFP_ATOMIC);
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	WARN_ON(brcm_mem_dma_num_descriptors(xfer) != 1);
+
+	if (d) {
+		u32 pa_d;
+
+		/* remap the buffers unless the caller has done that */
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			retval = -1;
+			goto _error;
+		}
+		/* set up mem-dma descriptor */
+		if (!brcm_mem_dma_gen_descriptor(xfer, d, 0, 1)) {
+
+			brcm_mem_dma_dump_descr(d, 1);
+			/* flush the descriptor */
+			pa_d = brcm_mem_dma_prepare_descriptors(d,
+				sizeof(struct brcm_mem_dma_descr));
+			_brcm_mem_dma_start_transfer(1, 1);
+			brcm_mem_dma_dump_regs(__func__);
+			_brcm_mem_dma_start_transfer(0, 0);
+			brcm_mem_dma_free_descriptors(pa_d,
+				sizeof(struct brcm_mem_dma_descr));
+		}
+
+		brcm_mem_dma_unmap_buffers(xfer);
+_error:
+		kfree(d);
+		return retval;
+	}
+
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_transfer_sg
+ * Scatter-gather version of M2M tranfser
+ ***********************************************************************/
+int brcm_mem_dma_transfer_sg(struct brcm_mem_transfer *xfer)
+{
+	printk(KERN_WARNING "%s: NOT IMPLEMENTED YET\n", __func__);
+	return -1;
+}
+
+/***********************************************************************
+ * brcm_mem_dma_transfer
+ * Initiates a M2M tranfser according to transfer request. Chained transfer
+ * will generate several descriptors.
+ ***********************************************************************/
+int brcm_mem_dma_transfer(struct brcm_mem_transfer *xfer)
+{
+	struct brcm_mem_dma_descr *d;
+	int index = 0, retval = 0;
+	struct brcm_mem_dma_descr *cur_d;
+	int xfer_cnt = brcm_mem_dma_num_descriptors(xfer), total_size;
+	struct brcm_mem_transfer *xfer_save = xfer;
+	dma_addr_t pa_d;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	total_size = xfer_cnt * sizeof(struct brcm_mem_dma_descr);
+
+	d = kzalloc(total_size, GFP_ATOMIC);
+	if (!d)
+		return -1;
+
+	cur_d = d;
+	do {
+		/* remap the buffers unless the caller has done that */
+		if (brcm_mem_dma_map_buffers(xfer)) {
+			retval = -1;
+			goto _done;
+		}
+
+		if (brcm_mem_dma_gen_descriptor(xfer, cur_d,
+		    index++, xfer_cnt)) {
+			retval = -1;
+			goto _done;
+		}
+
+		xfer = xfer->next;
+		cur_d++;
+	} while (xfer);
+
+	brcm_mem_dma_dump_descr(d, xfer_cnt);
+
+	/* flush the descriptors */
+	pa_d = brcm_mem_dma_prepare_descriptors(d, total_size);
+	brcm_mem_dma_dump_regs(__func__);
+	_brcm_mem_dma_start_transfer(1, 1);
+	_brcm_mem_dma_start_transfer(0, 0);
+
+	brcm_mem_dma_free_descriptors(pa_d, total_size);
+
+_done:
+	xfer = xfer_save;
+	do {
+		brcm_mem_dma_unmap_buffers(xfer);
+		xfer = xfer->next;
+	} while (xfer);
+
+	kfree(d);
+
+	return retval;
+}
+#else
+static int brcm_mem_dma_prepare_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+static int brcm_mem_dma_complete_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+static void brcm_mem_dma_start_transfer(void) {}
+
+int brcm_mem_dma_simple_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+
+int brcm_mem_dma_transfer(struct brcm_mem_transfer *xfer)
+{
+	return -1;
+}
+
+#endif /* BCHP_MEM_DMA_0_CTRL */
+
+static struct brcm_dram_encoder_ops m2m_ops = {
+	.prepare = brcm_mem_dma_prepare_transfer,
+	.start = brcm_mem_dma_start_transfer,
+	.complete = brcm_mem_dma_complete_transfer,
+};
+
+static int brcm_mem_dma_init(void)
+{
+	/* TODO: request interrupt */
+	/* register encoder with power management subsystem */
+	brcm_pm_set_dram_encoder(&m2m_ops);
+	return 0;
+}
+late_initcall(brcm_mem_dma_init);
diff --git a/drivers/brcmstb/memc1.c b/drivers/brcmstb/memc1.c
new file mode 100644
index 000000000000..034b7bf6a325
--- /dev/null
+++ b/drivers/brcmstb/memc1.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <stdarg.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#if 1
+#define DBG	printk
+#else
+#define DBG(...)		do { } while (0)
+#endif
+
+#if defined(BCHP_MEMC_DDR_1_SSPD_CMD)
+
+#define MAX_CLIENT_INFO_NUM		NUM_MEMC_CLIENTS
+#define MAX_DDR_PARAMS_NUM		16
+#define MAX_DDR_APHY_PARAMS_NUM		16
+#define MAX_ARB_PARAMS_NUM		2
+
+#define MEMC_STATE_UNKNOWN		0
+#define MEMC_STATE_ON			1
+#define MEMC_STATE_OFF			2
+
+static int  __brcm_pm_memc1_initialized(void);
+static void __brcm_pm_memc1_clock_start(void);
+static void __brcm_pm_memc1_clock_stop(void);
+static int  __brcm_pm_memc1_clock_running(void);
+static void brcm_pm_memc1_enable_idle_pad(void);
+static void brcm_pm_memc1_disable_idle_pad(void);
+static void brcm_pm_memc1_enable_plls(void);
+static void brcm_pm_memc1_disable_plls(void);
+
+struct memc_config {
+	u32	client_info[MAX_CLIENT_INFO_NUM];
+	u32	ddr23_aphy_params[MAX_DDR_APHY_PARAMS_NUM];
+	u32	ddr_params[MAX_DDR_PARAMS_NUM];
+	u32	arb_params[MAX_ARB_PARAMS_NUM];
+
+	u32	vcdl[4];
+	int	shmoo_value[8];
+
+	int	shmoo_valid;
+	int	valid;
+	/* if CFE did not initialize non-primary MEMC we cannot touch it
+	  because we do not have calibration capabilities.
+	  _initalized_ and _clock_active_ are initially set to
+	  0: unknown
+	  The first time any method is called it will set _initialized_ to
+	  one of the following values:
+	  1: on
+	  2: off - unusable
+	 */
+	int	initialized;
+	int	clock_active;
+};
+
+static struct memc_config __maybe_unused memc1_config;
+
+static void brcm_pm_memc1_sspd_control(int enable)
+{
+	if (enable) {
+		BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 1);
+		while (!BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
+			udelay(1);
+	} else {
+		BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 0);
+		while (BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
+			udelay(1);
+	}
+}
+
+static void brcm_pm_memc1_suspend_s3(void)
+{
+	/* clear standby field */
+	BDEV_UNSET(BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL, 0x0f);
+	/* inhibit DDR_RSTb pulse, Arm for standby */
+	BDEV_SET(BCHP_DDR40_PHY_CONTROL_REGS_1_STANDBY_CONTROL, BIT(5) | 0x05);
+}
+
+static void brcm_pm_memc1_ddr_params(int restore)
+{
+	int ii = 0;
+
+	if (restore) {
+		/* program ddr iobuf registers */
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_2,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_3,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_5,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_0,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_1,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_0,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_1,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_2,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_3,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_4,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_CNTRLR_CONFIG,
+			memc1_config.ddr_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL,
+			memc1_config.ddr_params[ii++]);
+	} else {
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_2);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_3);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_5);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_0);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_1);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_0);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_1);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_2);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_3);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_4);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_CNTRLR_CONFIG);
+		memc1_config.ddr_params[ii++] =
+			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL);
+	}
+	BUG_ON(ii > MAX_DDR_PARAMS_NUM);
+}
+
+static void brcm_pm_memc1_arb_params(int restore)
+{
+	int ii = 0;
+
+	if (restore) {
+		BDEV_WR_RB(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD,
+			memc1_config.arb_params[ii++]);
+		BDEV_WR_RB(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE,
+			memc1_config.arb_params[ii++]);
+	} else {
+		memc1_config.arb_params[ii++] =
+			BDEV_RD(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD);
+		memc1_config.arb_params[ii++] =
+			BDEV_RD(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE);
+	}
+
+	BUG_ON(ii > MAX_ARB_PARAMS_NUM);
+}
+
+static int brcm_pm_memc1_clock_running(void)
+{
+	if (memc1_config.clock_active == MEMC_STATE_UNKNOWN) {
+		/* do this only once */
+		memc1_config.clock_active = __brcm_pm_memc1_clock_running() ?
+			MEMC_STATE_ON : MEMC_STATE_OFF;
+	}
+	return memc1_config.clock_active == MEMC_STATE_ON;
+}
+
+static void brcm_pm_memc1_clock_start(void)
+{
+	if (!brcm_pm_memc1_clock_running())
+		__brcm_pm_memc1_clock_start();
+	memc1_config.clock_active = MEMC_STATE_ON;
+}
+
+static void brcm_pm_memc1_clock_stop(void)
+{
+	if (brcm_pm_memc1_clock_running())
+		__brcm_pm_memc1_clock_stop();
+	memc1_config.clock_active = MEMC_STATE_OFF;
+}
+
+static int brcm_pm_memc1_initialized(void)
+{
+	if (memc1_config.initialized == MEMC_STATE_UNKNOWN) {
+		brcm_pm_memc1_clock_start();
+		/* do this only once */
+		memc1_config.initialized = __brcm_pm_memc1_initialized() ?
+			MEMC_STATE_ON : MEMC_STATE_OFF;
+	}
+	return memc1_config.initialized == MEMC_STATE_ON;
+}
+
+#define CHECK_MEMC1_INIT() \
+	if (!brcm_pm_memc1_initialized()) { \
+		printk(KERN_ERR "%s: not initialized\n", __func__); \
+		return -1; \
+	}
+
+int brcm_pm_memc1_suspend(int is_s3)
+{
+	CHECK_MEMC1_INIT();
+
+	/*
+	 * Force all dirty cache lines to be written
+	 * If a dirty cache line for memc1 were to be written later,
+	 * it might hang the cache unit and/or cpu.
+	 */
+	_dma_cache_wback_inv(0, ~0);
+	if (is_s3)
+		brcm_pm_memc1_suspend_s3();
+	else
+		brcm_pm_memc1_sspd_control(1);
+
+	return 0;
+}
+
+int brcm_pm_memc1_resume(int is_s3)
+{
+	CHECK_MEMC1_INIT();
+
+	if (is_s3 == 0)
+		brcm_pm_memc1_sspd_control(0);
+
+	return 0;
+}
+
+
+int brcm_pm_memc1_powerdown(void)
+{
+	CHECK_MEMC1_INIT();
+
+	DBG(KERN_DEBUG "%s\n", __func__);
+
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_1_REG_START,
+		memc1_config.client_info, 0);
+	brcm_pm_memc1_ddr_params(0);
+	brcm_pm_memc1_arb_params(0);
+	brcm_pm_memc1_enable_idle_pad();
+
+	memc1_config.shmoo_valid = 1;
+	memc1_config.valid = 1;
+
+	/*
+	 * Force all dirty cache lines to be written
+	 * If a dirty cache line for memc1 were to be written later,
+	 * it might hang the cache unit and/or cpu.
+	 */
+	_dma_cache_wback_inv(0, ~0);
+	brcm_pm_memc1_sspd_control(1);
+
+	brcm_pm_memc1_disable_plls();
+
+	DBG(KERN_DEBUG "%s reset\n", __func__);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 1);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 1);
+	BDEV_WR_F_RB(MEMC_DDR_1_DRAM_INIT_CNTRL, DDR3_INIT_MODE, 1);
+	mdelay(1);
+
+	/* Stop the clocks */
+	brcm_pm_memc1_clock_stop();
+	memc1_config.valid = 1;
+
+	return 0;
+}
+
+int brcm_pm_memc1_powerup(void)
+{
+	CHECK_MEMC1_INIT();
+
+	if (!memc1_config.valid || !memc1_config.shmoo_valid) {
+		printk(KERN_ERR "%s: no valid saved configuration %d %d\n",
+		       __func__, memc1_config.valid, memc1_config.shmoo_valid);
+		return -1;
+	}
+
+	DBG(KERN_DEBUG "%s\n", __func__);
+
+	/* Restart the clocks */
+	brcm_pm_memc1_clock_start();
+	brcm_pm_memc1_enable_plls();
+	brcm_pm_memc1_disable_idle_pad();
+
+	brcm_pm_memc1_sspd_control(0);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 0);
+	BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 0);
+	mdelay(1);
+	printk(KERN_DEBUG "memc1: powered up\n");
+
+	brcm_pm_memc1_ddr_params(1);
+	brcm_pm_memc1_arb_params(1);
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_1_REG_START,
+		memc1_config.client_info, 1);
+	brcm_pm_memc1_sspd_control(0);
+
+	return 0;
+}
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7435)
+static int __brcm_pm_memc1_initialized(void)
+{
+	return BDEV_RD_F(MEMC_DDR_1_DRAM_INIT_STATUS, INIT_DONE);
+}
+
+static void __brcm_pm_memc1_clock_start(void)
+{
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_108_CLOCK_ENABLE, 1);
+}
+
+static void __brcm_pm_memc1_clock_stop(void)
+{
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+		DDR1_108_CLOCK_ENABLE, 0);
+}
+
+static int __brcm_pm_memc1_clock_running(void)
+{
+	return BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+			DDR1_SCB_CLOCK_ENABLE) &&
+		BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
+			DDR1_108_CLOCK_ENABLE);
+}
+
+static void brcm_pm_memc1_enable_idle_pad(void)
+{
+	/* enable idle pad powerdown */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		PHY_IDLE_ENABLE, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
+		0x132);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
+			0xFFFFF);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
+			0xFFFFF);
+	DBG(KERN_DEBUG "%s\n", __func__);
+}
+
+static void brcm_pm_memc1_disable_idle_pad(void)
+{
+	/* disable idle pad powerdown */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
+		0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
+			0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
+		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
+			0);
+
+}
+
+static void brcm_pm_memc1_enable_plls(void)
+{
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
+		PWRDN, 0);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 0);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 2);
+	mdelay(1);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 0);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
+		DDR1_MEMORY_STANDBY_ENABLE, 0);
+#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
+		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 0);
+#endif
+
+}
+static void brcm_pm_memc1_disable_plls(void)
+{
+	/* power down the PLLs */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
+		PWRDN, 1);
+	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 3);
+
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
+		DDR1_POWER_SWITCH_MEMORY, 3);
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
+		DDR1_MEMORY_STANDBY_ENABLE, 1);
+
+#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
+	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
+		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 1);
+#endif
+}
+
+
+
+#endif
+
+#endif
diff --git a/drivers/brcmstb/pci.c b/drivers/brcmstb/pci.c
new file mode 100644
index 000000000000..90d5f4fb37a8
--- /dev/null
+++ b/drivers/brcmstb/pci.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright (C) 2009 - 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)		"PCI: " fmt
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/printk.h>
+#include <linux/syscore_ops.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* NOTE: all PHYSICAL addresses */
+
+/* Use assigned bus numbers so "ops" can tell the controllers apart */
+#define BRCM_BUSNO_PCIE		0x00
+
+#define PCIE_OUTBOUND_WIN(win, start, len) do { \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_LO, \
+		(start) + MMIO_ENDIAN); \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_HI, 0); \
+	BDEV_WR(BCHP_PCIE_MISC_CPU_2_PCIE_MEM_WIN##win##_BASE_LIMIT, \
+		(((start) >> 20) << 4) | \
+		 ((((start) + (len) - 1) >> 20) << 20)); \
+	} while (0)
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 *data);
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 data);
+
+static inline int get_busno_pcie(void)  { return BRCM_BUSNO_PCIE;  }
+
+static struct pci_ops brcmstb_pci_ops = {
+	.read = brcm_pci_read_config,
+	.write = brcm_pci_write_config,
+};
+
+/*
+ * Note: our PCIe core does not support IO BARs at all.  MEM only.
+ * The Linux PCI code insists on having IO resources and io_map_base for
+ * all PCI controllers, so those values are totally bogus.
+ */
+#define IO_ADDR_PCIE		0x400
+#define PCIE_IO_SIZE		0x400
+#define BOGUS_IO_MAP_BASE	1
+
+/* pci_controller resources */
+
+static struct resource pcie_mem_resource = {
+	.name			= "External PCIe MEM",
+	.start			= PCIE_MEM_START,
+	.end			= PCIE_MEM_START + PCIE_MEM_SIZE - 1,
+	.flags			= IORESOURCE_MEM,
+};
+
+static struct resource pcie_io_resource = {
+	.name			= "External PCIe IO (unavailable)",
+	.start			= IO_ADDR_PCIE,
+	.end			= IO_ADDR_PCIE + PCIE_IO_SIZE - 1,
+	.flags			= IORESOURCE_MEM,
+};
+
+static struct pci_controller brcmstb_pcie_controller = {
+	.pci_ops		= &brcmstb_pci_ops,
+	.io_resource		= &pcie_io_resource,
+	.mem_resource		= &pcie_mem_resource,
+	.get_busno		= &get_busno_pcie,
+	.io_map_base		= BOGUS_IO_MAP_BASE,
+};
+
+struct brcm_pci_bus {
+	struct pci_controller	*controller;
+	char			*name;
+	unsigned int		hw_busnum;
+	unsigned int		busnum_shift;
+	unsigned int		slot_shift;
+	unsigned int		func_shift;
+	int			memory_hole;
+	unsigned long		idx_reg;
+	unsigned long		data_reg;
+	struct clk		*clk;
+};
+
+static struct brcm_pci_bus brcm_buses[] = {
+	[BRCM_BUSNO_PCIE] = {
+		&brcmstb_pcie_controller, "PCIe",    1, 20, 15, 12, 0 },
+};
+
+
+/***********************************************************************
+ * PCIe Bridge setup
+ ***********************************************************************/
+
+#if defined(__BIG_ENDIAN)
+#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
+#define MMIO_ENDIAN		2	/* MIPS->PCI outbound accesses */
+#else
+#define	DATA_ENDIAN		0
+#define MMIO_ENDIAN		0
+#endif
+
+static struct wktmr_time pcie_reset_started;
+
+#define PCIE_LINK_UP() \
+	(((BDEV_RD(BCHP_PCIE_MISC_PCIE_STATUS) & 0x30) == 0x30) ? 1 : 0)
+
+void brcm_early_pcie_setup(void)
+{
+	/*
+	 * Called from bchip_early_setup() in order to start PCIe link
+	 * negotiation immediately at kernel boot time.  The RC is supposed
+	 * to give the endpoint device 100ms to settle down before
+	 * attempting configuration accesses.  So we let the link negotiation
+	 * happen in the background instead of busy-waiting.
+	 */
+
+	struct wktmr_time tmp;
+
+	/* reset the bridge and the endpoint device */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 1);
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_SW_PERST, 1);
+
+	/* delay 100us */
+	wktmr_read(&tmp);
+	while (wktmr_elapsed(&tmp) < (100 * WKTMR_1US))
+		;
+
+	/* take the bridge out of reset */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 0);
+
+	/* enable SCB_MAX_BURST_SIZE | CSR_READ_UR_MODE | SCB_ACCESS_EN */
+	BDEV_WR(BCHP_PCIE_MISC_MISC_CTRL, 0x00103000);
+
+	/* set up MIPS->PCIE memory windows (4x 128MB) */
+	PCIE_OUTBOUND_WIN(0, PCIE_MEM_START + 0x00000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(1, PCIE_MEM_START + 0x08000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(2, PCIE_MEM_START + 0x10000000, 0x08000000);
+	PCIE_OUTBOUND_WIN(3, PCIE_MEM_START + 0x18000000, 0x08000000);
+
+#if defined(CONFIG_BRCM_HAS_2GB_MEMC0)
+	/* set up 4GB PCIE->SCB memory window on BAR2 */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO, 0x00000011);
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI, 0x00000000);
+	BDEV_WR_F(PCIE_MISC_MISC_CTRL, SCB0_SIZE, 0x10);
+	BDEV_WR_F(PCIE_MISC_MISC_CTRL, SCB1_SIZE, 0x0f);
+#else
+	/* set up 1GB PCIE->SCB memory window on BAR2 */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_LO, 0x0000000f);
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR2_CONFIG_HI, 0x00000000);
+#endif
+
+	/* disable PCIE->GISB window */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR1_CONFIG_LO, 0x00000000);
+	/* disable the other PCIE->SCB memory window */
+	BDEV_WR(BCHP_PCIE_MISC_RC_BAR3_CONFIG_LO, 0x00000000);
+
+	/* disable MSI (for now...) */
+	BDEV_WR(BCHP_PCIE_MISC_MSI_BAR_CONFIG_LO, 0);
+
+	/* set up L2 interrupt masks */
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_CLEAR, 0);
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_MASK_CLEAR, 0);
+	BDEV_WR_RB(BCHP_PCIE_INTR2_CPU_MASK_SET, 0xffffffff);
+
+	/* take the EP device out of reset */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_SW_PERST, 0);
+
+	/* record the current time */
+	wktmr_read(&pcie_reset_started);
+}
+
+void brcm_setup_pcie_bridge(void)
+{
+	/* give the RC/EP time to wake up, before trying to configure RC */
+	while (wktmr_elapsed(&pcie_reset_started) < (100 * WKTMR_1MS))
+		;
+
+	if (!PCIE_LINK_UP()) {
+		struct clk *clk;
+
+		brcm_pcie_enabled = 0;
+		clk = brcm_buses[BRCM_BUSNO_PCIE].clk;
+		if (clk) {
+			clk_disable(clk);
+			clk_put(clk);
+		}
+		pr_info("PCIe link down\n");
+		return;
+	}
+	pr_info("PCIe link up, %sGbps x%lu\n",
+		BDEV_RD_F(PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+			  NEG_LINK_SPEED) == 0x2 ? "5.0" : "2.5",
+		BDEV_RD_F(PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+			  NEG_LINK_WIDTH));
+
+	/* enable MEM_SPACE and BUS_MASTER for RC */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_STATUS_COMMAND, 0x6);
+
+	/* set base/limit for outbound transactions */
+#if defined(CONFIG_BRCM_HAS_2GB_MEMC0)
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT, 0xeff0d000);
+#else
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_MEM_BASE_LIMIT, 0xbff0a000);
+#endif
+
+	/* disable the prefetch range */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_RC_PREF_BASE_LIMIT, 0x0000fff0);
+
+	/* set pri/sec bus numbers */
+	BDEV_WR(BCHP_PCIE_RC_CFG_TYPE1_PRI_SEC_BUS_NO, 0x00010100);
+
+	/* enable configuration request retry (see pci_scan_device()) */
+	BDEV_WR_F(PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, RC_CRS_EN, 1);
+
+	/* PCIE->SCB endian mode for BAR2 */
+	BDEV_WR_F_RB(PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, ENDIAN_MODE_BAR2,
+		DATA_ENDIAN);
+}
+
+#if defined(CONFIG_PM)
+/*
+ * syscore device to handle PCIe bus suspend and resume
+ */
+static inline void pcie_enable(int enable)
+{
+	struct clk *clk;
+
+	if (!brcm_pcie_enabled)
+		return;
+
+	clk = brcm_buses[BRCM_BUSNO_PCIE].clk;
+	if (clk)
+		enable ? clk_enable(clk) : clk_disable(clk);
+}
+
+static int pcie_suspend(void)
+{
+	pcie_enable(0);
+	return 0;
+}
+
+static void pcie_resume(void)
+{
+	pcie_enable(1);
+}
+
+static struct syscore_ops pcie_pm_ops = {
+	.suspend        = pcie_suspend,
+	.resume         = pcie_resume,
+};
+#endif
+
+/***********************************************************************
+ * PCI controller registration
+ ***********************************************************************/
+
+static int __init brcmstb_pci_init(void)
+{
+	if (brcm_pcie_enabled) {
+		brcm_buses[BRCM_BUSNO_PCIE].clk = clk_get(NULL, "pcie");
+		brcm_setup_pcie_bridge();
+		brcm_buses[BRCM_BUSNO_PCIE].idx_reg =
+			BVIRTADDR(BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX);
+		brcm_buses[BRCM_BUSNO_PCIE].data_reg =
+			BVIRTADDR(BCHP_PCIE_EXT_CFG_PCIE_EXT_CFG_DATA);
+
+		register_pci_controller(&brcmstb_pcie_controller);
+#if defined(CONFIG_PM)
+		register_syscore_ops(&pcie_pm_ops);
+#endif
+	}
+	return 0;
+}
+
+arch_initcall(brcmstb_pci_init);
+
+/***********************************************************************
+ * Read/write PCI configuration registers
+ ***********************************************************************/
+
+#define CFG_INDEX(bus, devfn, reg) \
+	(((PCI_SLOT(devfn) & 0x1f) << (brcm_buses[bus->number].slot_shift)) | \
+	 ((PCI_FUNC(devfn) & 0x07) << (brcm_buses[bus->number].func_shift)) | \
+	 (brcm_buses[bus->number].hw_busnum << \
+	  brcm_buses[bus->number].busnum_shift) | \
+	 (reg))
+
+static int devfn_ok(struct pci_bus *bus, unsigned int devfn)
+{
+	/* PCIe: check for link down or invalid slot number */
+	if (bus->number == BRCM_BUSNO_PCIE &&
+	    (!PCIE_LINK_UP() || PCI_SLOT(devfn) != 0))
+		return 0;
+
+	return 1;	/* OK */
+}
+
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 data)
+{
+	u32 val = 0, mask, shift;
+
+	if (!devfn_ok(bus, devfn))
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (size < 4) {
+		/* partial word - read, modify, write */
+		DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+			CFG_INDEX(bus, devfn, where & ~3));
+		val = DEV_RD(brcm_buses[bus->number].data_reg);
+	}
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+
+	DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+		CFG_INDEX(bus, devfn, where & ~3));
+	val = (val & ~mask) | ((data << shift) & mask);
+	DEV_WR_RB(brcm_buses[bus->number].data_reg, val);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+	int where, int size, u32 *data)
+{
+	u32 val, mask, shift;
+
+	if (!devfn_ok(bus, devfn))
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+
+	BUG_ON(((where & 3) + size) > 4);
+
+	DEV_WR_RB(brcm_buses[bus->number].idx_reg,
+		CFG_INDEX(bus, devfn, where & ~3));
+	val = DEV_RD(brcm_buses[bus->number].data_reg);
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+
+	*data = (val & mask) >> shift;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/***********************************************************************
+ * PCI slot to IRQ mappings (aka "fixup")
+ ***********************************************************************/
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	if (dev->bus->number == BRCM_BUSNO_PCIE) {
+		const int pcie_irq[] = {
+			BRCM_IRQ_PCIE_INTA, BRCM_IRQ_PCIE_INTB,
+			BRCM_IRQ_PCIE_INTC, BRCM_IRQ_PCIE_INTD,
+		};
+		if ((pin - 1) > 3)
+			return 0;
+		return pcie_irq[pin - 1];
+	}
+	return 0;
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	return 0;
+}
+
+
+/***********************************************************************
+ * Per-device initialization
+ ***********************************************************************/
+
+static void brcm_pcibios_fixup(struct pci_dev *dev)
+{
+	int slot = PCI_SLOT(dev->devfn);
+
+	pr_info("found device %04x:%04x on %s bus, slot %d (irq %d)\n",
+		dev->vendor, dev->device, brcm_buses[dev->bus->number].name,
+		slot, pcibios_map_irq(dev, slot, 1));
+
+	/* zero out the BARs and let Linux assign an address */
+	pci_write_config_dword(dev, PCI_COMMAND, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0);
+	pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0);
+	pci_write_config_dword(dev, PCI_INTERRUPT_LINE, 0);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
+
+/***********************************************************************
+ * DMA address remapping
+ ***********************************************************************/
+
+/*
+ * PCIe inbound BARs collapse the "holes" in the chip's SCB address space.
+ * Therefore the PCI addresses need to be adjusted as they will not match
+ * the SCB addresses (MIPS physical addresses).
+ *
+ * The address maps can be found in <asm/mach-brcmstb/spaces.h> .
+ */
+
+static int dev_collapses_memory_hole(struct device *dev)
+{
+#if defined(CONFIG_BRCM_UPPER_MEMORY) || defined(CONFIG_HIGHMEM)
+
+	struct pci_dev *pdev;
+
+	if (unlikely(dev == NULL) ||
+	    likely(dev->bus != &pci_bus_type))
+		return 0;
+
+	pdev = to_pci_dev(dev);
+	if (unlikely(pdev == NULL) ||
+	    brcm_buses[pdev->bus->number].memory_hole)
+		return 0;
+
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static dma_addr_t brcm_phys_to_pci(struct device *dev, unsigned long phys)
+{
+	if (!dev_collapses_memory_hole(dev))
+		return phys;
+	if (phys >= MEMC1_START)
+		return phys - MEMC1_PCI_OFFSET;
+	if (phys >= (BRCM_PCI_HOLE_START + BRCM_PCI_HOLE_SIZE))
+		return phys - BRCM_PCI_HOLE_SIZE;
+	return phys;
+}
+
+dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
+	return brcm_phys_to_pci(dev, virt_to_phys(addr));
+}
+
+dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+	return brcm_phys_to_pci(dev, page_to_phys(page));
+}
+
+unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+	if (!dev_collapses_memory_hole(dev))
+		return dma_addr;
+	if (dma_addr >= (MEMC1_START - MEMC1_PCI_OFFSET))
+		return dma_addr + MEMC1_PCI_OFFSET;
+	if (dma_addr >= BRCM_PCI_HOLE_START)
+		return dma_addr + BRCM_PCI_HOLE_SIZE;
+	return dma_addr;
+}
diff --git a/drivers/brcmstb/power.c b/drivers/brcmstb/power.c
new file mode 100644
index 000000000000..fdc0d2985510
--- /dev/null
+++ b/drivers/brcmstb/power.c
@@ -0,0 +1,4541 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <stdarg.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/ctype.h>
+#include <linux/smp.h>
+#include <linux/platform_device.h>
+#include <linux/suspend.h>
+#include <linux/mii.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* Wakeup on timeout (20 sec) even if standby_flags does not request this */
+#define WATCHDOG_TIMER_WAKEUP_ALWAYS		(0)
+
+#define PRINT_PM_CALLBACK		printk(KERN_DEBUG "%s %02x\n", \
+	__func__, (u8)flags)
+#if 0
+#define DBG			printk
+#else
+#define DBG(...)		do { } while (0)
+#endif
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM common internal functions
+ ***********************************************************************/
+struct clk {
+	char		name[16];
+	int             refcnt;
+	struct clk     *parent;
+	int		(*cb)(int, void *);
+	void		*cb_arg;
+	void		(*disable)(u32 flags);
+	void		(*enable)(u32 flags);
+	int		(*set_rate)(unsigned long rate);
+	u32		flags;
+	struct list_head list;
+};
+/*
+ * Flags:
+ * BRCM_PM_FLAG_S3		- S3 standby inititated. Since all blocks lose
+ *	power, there is no need to preserve state.
+ *	On-chip SRAM can be unconditionally powered down.
+ * BRCM_PM_FLAG_ENET_WOL	- Ethernet WOL is a wake-up event
+ * BRCM_PM_FLAG_MOCA_WOL	- MoCA WOL is a wake-up event
+ * BRCM_PM_FLAG_USB_WAKEUP	- USB insertion/removal is a wake-up event
+ */
+#define BRCM_PM_FLAG_S3		0x01 /* set when suspend begins */
+#define BRCM_PM_FLAG_ENET_WOL	0x02 /* ENET WOL is enabled */
+#define BRCM_PM_FLAG_MOCA_WOL	0x04 /* MoCA WOL is enabled */
+#define BRCM_PM_FLAG_USB_WAKEUP	0x08 /* USB insertion/removal wakeup */
+
+#define ANY_WOL(flags) (flags & (BRCM_PM_FLAG_ENET_WOL|BRCM_PM_FLAG_MOCA_WOL))
+#define ENET_WOL(flags) (flags & BRCM_PM_FLAG_ENET_WOL)
+#define MOCA_WOL(flags) (flags & BRCM_PM_FLAG_MOCA_WOL)
+
+static DEFINE_SPINLOCK(brcm_pm_clk_lock);
+
+static void brcm_pm_sata_disable(u32 flags);
+static void brcm_pm_sata_enable(u32 flags);
+static void brcm_pm_genet_disable(u32 flags);
+static void brcm_pm_genet_enable(u32 flags);
+static void brcm_pm_genet_disable_wol(u32 flags);
+static void brcm_pm_genet_enable_wol(u32 flags);
+static void brcm_pm_moca_disable(u32 flags);
+static void brcm_pm_moca_enable(u32 flags);
+static void brcm_pm_moca_disable_wol(u32 flags);
+static void brcm_pm_moca_enable_wol(u32 flags);
+static void brcm_pm_genet1_disable(u32 flags);
+static void brcm_pm_genet1_enable(u32 flags);
+static void brcm_pm_network_disable(u32 flags);
+static void brcm_pm_network_enable(u32 flags);
+static void brcm_pm_usb_disable(u32 flags);
+static void brcm_pm_usb_enable(u32 flags);
+static void brcm_pm_set_ddr_timeout(int);
+static void brcm_pm_initialize(void);
+static int  brcm_pm_moca_cpu_set_rate(unsigned long rate);
+static int  brcm_pm_moca_phy_set_rate(unsigned long rate);
+
+static int brcm_pm_ddr_timeout;
+static unsigned long brcm_pm_standby_flags;
+static unsigned long brcm_pm_standby_timeout;
+
+enum {
+	BRCM_CLK_SATA,
+	BRCM_CLK_GENET,
+	BRCM_CLK_MOCA,
+	BRCM_CLK_USB,
+	BRCM_CLK_GENET1,
+	BRCM_CLK_NETWORK,	/* PLLs/clocks common to all GENETs */
+	BRCM_CLK_GENET_WOL,
+	BRCM_CLK_MOCA_WOL,
+	BRCM_CLK_MOCA_PHY,
+	BRCM_CLK_MOCA_CPU,
+};
+
+static struct clk brcm_clk_table[] = {
+	[BRCM_CLK_SATA] = {
+		.name		= "sata",
+		.disable	= &brcm_pm_sata_disable,
+		.enable		= &brcm_pm_sata_enable,
+	},
+	[BRCM_CLK_GENET] = {
+		.name		= "enet",
+		.disable	= &brcm_pm_genet_disable,
+		.enable		= &brcm_pm_genet_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_NETWORK],
+	},
+	[BRCM_CLK_MOCA] = {
+		.name		= "moca",
+		.disable	= &brcm_pm_moca_disable,
+		.enable		= &brcm_pm_moca_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_GENET1],
+	},
+	[BRCM_CLK_USB] = {
+		.name		= "usb",
+		.disable	= &brcm_pm_usb_disable,
+		.enable		= &brcm_pm_usb_enable,
+	},
+	[BRCM_CLK_GENET1] = {
+		.name		= "moca_genet",
+		.disable	= &brcm_pm_genet1_disable,
+		.enable		= &brcm_pm_genet1_enable,
+		.parent		= &brcm_clk_table[BRCM_CLK_NETWORK],
+	},
+	[BRCM_CLK_NETWORK] = {
+		.name		= "network",
+		.disable	= &brcm_pm_network_disable,
+		.enable		= &brcm_pm_network_enable,
+	},
+	[BRCM_CLK_GENET_WOL] = {
+		.name		= "enet-wol",
+		.disable	= &brcm_pm_genet_disable_wol,
+		.enable		= &brcm_pm_genet_enable_wol,
+	},
+	[BRCM_CLK_MOCA_WOL] = {
+		.name		= "moca-wol",
+		.disable	= &brcm_pm_moca_disable_wol,
+		.enable		= &brcm_pm_moca_enable_wol,
+	},
+	[BRCM_CLK_MOCA_CPU] = {
+		.name		= "moca-cpu",
+		.set_rate	= &brcm_pm_moca_cpu_set_rate,
+	},
+	[BRCM_CLK_MOCA_PHY] = {
+		.name		= "moca-phy",
+		.set_rate	= &brcm_pm_moca_phy_set_rate,
+	},
+};
+
+/* These clocks are chip specific - each .initialize()
+  method will add them if needed */
+static LIST_HEAD(brcm_dyn_clk_list);
+
+static __maybe_unused void __clk_dyn_add(struct clk *clk)
+{
+	struct clk *clk_p;
+	list_for_each_entry(clk_p, &brcm_dyn_clk_list, list) {
+		if (clk_p == clk)
+			return;
+	}
+	list_add(&clk->list, &brcm_dyn_clk_list);
+}
+
+static __maybe_unused void __clk_dyn_del(struct clk *clk)
+{
+	list_del(&clk->list);
+}
+
+static struct clk *brcm_pm_clk_find(const char *name)
+{
+	int i;
+	struct clk *clk = brcm_clk_table;
+
+	if (!name)
+		return ERR_PTR(-ENOENT);
+
+	/* first check static clocks */
+	for (i = 0; i < ARRAY_SIZE(brcm_clk_table); i++, clk++)
+		if (!strncmp(name, clk->name, strlen(name)))
+			return clk;
+
+	/* check dynamic clocks */
+	list_for_each_entry(clk, &brcm_dyn_clk_list, list) {
+		if (!strncmp(name, clk->name, strlen(name)))
+			return clk;
+	}
+	return NULL;
+}
+
+/* sysfs attributes */
+
+ssize_t brcm_pm_show_sata_power(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	return snprintf(buf, PAGE_SIZE, "%d\n", !!clk->refcnt);
+}
+
+ssize_t brcm_pm_store_sata_power(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	int val;
+
+	if (!clk || !clk->cb || sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	return clk->cb(val ? PM_EVENT_RESUME : PM_EVENT_SUSPEND,
+		clk->cb_arg) ? : count;
+}
+
+ssize_t brcm_pm_show_ddr_timeout(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_ddr_timeout);
+}
+
+ssize_t brcm_pm_store_ddr_timeout(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_ddr_timeout = val;
+	if (brcm_pm_enabled)
+		brcm_pm_set_ddr_timeout(val);
+	return count;
+}
+
+ssize_t brcm_pm_show_standby_flags(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%lx\n", brcm_pm_standby_flags);
+}
+
+ssize_t brcm_pm_store_standby_flags(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	unsigned long val;
+	if (sscanf(buf, "%lx", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_standby_flags = val;
+	return count;
+}
+
+ssize_t brcm_pm_show_standby_timeout(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%lu\n", brcm_pm_standby_timeout);
+}
+
+ssize_t brcm_pm_store_standby_timeout(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	unsigned long val;
+	if (sscanf(buf, "%lu", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_standby_timeout = val;
+	return count;
+}
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+/*
+ * brcm_pm_memc1_power
+ * Power state of secondary memory controller
+ * 0 - complete power down (with loss of content)
+ * 1 - full power mode
+ * 2 - SSPD (content preserved)
+ * Direct transition between 0 and 2 is not supported
+ */
+#define BRCM_PM_MEMC1_OFF	0
+#define BRCM_PM_MEMC1_ON	1
+#define BRCM_PM_MEMC1_SSPD	2
+
+static int brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+int __weak brcm_pm_memc1_suspend(int is_s3) { return 0; }
+int __weak brcm_pm_memc1_resume(int is_s3) { return 0; }
+int __weak brcm_pm_memc1_powerdown(void) { return 0; }
+int  __weak brcm_pm_memc1_powerup(void) { return 0; }
+
+ssize_t brcm_pm_show_memc1_power(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_memc1_power);
+}
+
+ssize_t brcm_pm_store_memc1_power(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+
+	/*
+	 * if memc1 memory has been added to system memory pool,
+	 * disable memc1 dynamic PM
+	 */
+	if (brcm_dram1_linux_mb && brcm_dram1_linux_mb <= brcm_dram1_size_mb) {
+		sysfs_chmod_file(&dev->kobj,
+			&attr->attr, attr->attr.mode & ~S_IWUGO);
+		return -EINVAL;
+	}
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	/* check for no change */
+	if (val == brcm_pm_memc1_power)
+		return count;
+
+	switch (val) {
+	case BRCM_PM_MEMC1_OFF:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON)
+			brcm_pm_memc1_powerdown();
+		else
+			return -EINVAL;
+		break;
+	case BRCM_PM_MEMC1_ON:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_OFF) {
+			if (brcm_pm_memc1_powerup())
+				return -EINVAL;
+		} else if (brcm_pm_memc1_power == BRCM_PM_MEMC1_SSPD)
+			brcm_pm_memc1_resume(0);
+		else
+			return -EINVAL;
+		break;
+	case BRCM_PM_MEMC1_SSPD:
+		if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON)
+			brcm_pm_memc1_suspend(0);
+		else
+			return -EINVAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	brcm_pm_memc1_power = val;
+	return count;
+}
+
+#endif
+
+static u32 brcm_pm_time_at_wakeup[2];
+ssize_t brcm_pm_show_time_at_wakeup(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%x 0x%x\n",
+		brcm_pm_time_at_wakeup[0], brcm_pm_time_at_wakeup[1]);
+}
+
+static int brcm_pm_halt_mode=1;
+
+#if 0
+ssize_t brcm_pm_show_halt_mode(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", brcm_pm_halt_mode);
+}
+
+ssize_t brcm_pm_store_halt_mode(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	brcm_pm_halt_mode = !!val;
+	return count;
+}
+#endif
+
+/* Boot time functions */
+
+static int __init brcm_pm_init(void)
+{
+	if (!brcm_pm_enabled)
+		return 0;
+	if (!brcm_moca_enabled)
+		brcm_pm_moca_disable(0);
+	/* chip specific initialization */
+	brcm_pm_initialize();
+	return 0;
+}
+
+early_initcall(brcm_pm_init);
+
+static int nopm_setup(char *str)
+{
+	brcm_pm_enabled = 0;
+	return 0;
+}
+
+__setup("nopm", nopm_setup);
+
+int brcm_pm_hash_enabled = 1;
+
+static int nohash_setup(char *str)
+{
+	brcm_pm_hash_enabled = 0;
+	return 0;
+}
+
+__setup("nohash", nohash_setup);
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM external API
+ ***********************************************************************/
+
+/* internal functions assume the lock is held */
+static int __clk_enable(struct clk *clk, u32 flags)
+{
+	BUG_ON(clk->refcnt < 0);
+	if (++(clk->refcnt) == 1 && brcm_pm_enabled) {
+		if (clk->parent)
+			__clk_enable(clk->parent, clk->flags | flags);
+		printk(KERN_DEBUG "%s: %s [%d]\n",
+			__func__, clk->name, clk->refcnt);
+		if (clk->enable)
+			clk->enable(clk->flags | flags);
+	}
+	return 0;
+}
+
+static void __clk_disable(struct clk *clk, u32 flags)
+{
+	if (--(clk->refcnt) == 0 && brcm_pm_enabled) {
+		printk(KERN_DEBUG "%s: %s [%d]\n",
+			__func__, clk->name, clk->refcnt);
+		if (clk->disable)
+			clk->disable(clk->flags | flags);
+		if (clk->parent)
+			__clk_disable(clk->parent, clk->flags | flags);
+	}
+	BUG_ON(clk->refcnt < 0);
+}
+
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+		__clk_enable(clk, 0);
+		spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+		__clk_disable(clk, 0);
+		spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+	}
+}
+EXPORT_SYMBOL(clk_disable);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned long flags;
+	spinlock_t *lock = &brcm_pm_clk_lock;
+	if (clk && !IS_ERR(clk)) {
+		spin_lock_irqsave(lock, flags);
+		clk->parent = parent;
+		spin_unlock_irqrestore(lock, flags);
+		return 0;
+	}
+	return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (clk && !IS_ERR(clk))
+		return clk->parent;
+
+	return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return -EINVAL;
+}
+
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret;
+	spinlock_t *lock = &brcm_pm_clk_lock;
+
+	if (clk && !IS_ERR(clk) && clk->set_rate) {
+		spin_lock_irqsave(lock, flags);
+		ret = clk->set_rate(rate);
+		spin_unlock_irqrestore(lock, flags);
+		return ret;
+	}
+	return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int brcm_pm_register_cb(char *name, int (*fn)(int, void *), void *arg)
+{
+	struct clk *clk = brcm_pm_clk_find(name);
+	unsigned long flags;
+
+	if (!clk)
+		return -ENOENT;
+
+	spin_lock_irqsave(&brcm_pm_clk_lock, flags);
+	BUG_ON(fn && clk->cb);
+	clk->cb = fn;
+	clk->cb_arg = arg;
+	spin_unlock_irqrestore(&brcm_pm_clk_lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_pm_register_cb);
+
+int brcm_pm_unregister_cb(char *name)
+{
+	return brcm_pm_register_cb(name, NULL, NULL);
+}
+EXPORT_SYMBOL(brcm_pm_unregister_cb);
+
+/***********************************************************************
+ * Wakeup source management
+ *   All kernel drivers can use this api to register their wakeup
+ *   sources. This will enable 'lightweight' resume feature, when
+ *   wakeup event is quickly qualified immediately after resume using
+ *   driver-supplied poll() method. If none of registered poll() method
+ *   recognize the wakeup event, system may be brought back to sleep.
+ *   To allow for other components to use their wakeup capabilities, system
+ *   suspend code will save the pre-suspend PM_L2 mask and, if all poll()
+ *   callbacks deny the wakeup event, check if one of events enabled in the
+ *   saved mask has occurred.
+ ***********************************************************************/
+struct brcm_wakeup_source {
+	struct brcm_wakeup_ops		*ops;
+	void				*ref;
+	struct list_head		list;
+	struct kref			kref;
+	char				name[16];
+};
+
+struct brcm_wakeup_control {
+	spinlock_t			lock;
+	struct list_head		head;
+	int				count;
+};
+
+static struct brcm_wakeup_control bwc;
+
+int brcm_pm_wakeup_register(struct brcm_wakeup_ops *ops, void *ref, char *name)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops == ops && bws->ref == ref) {
+			/* already registered */
+			spin_lock_irqsave(&bwc.lock, flags);
+			kref_get(&bws->kref);
+			spin_unlock_irqrestore(&bwc.lock, flags);
+			return 0;
+		}
+	}
+
+	bws = kmalloc(sizeof(struct brcm_wakeup_source), GFP_ATOMIC);
+	if (!bws)
+		return -1;
+
+	bws->ops = ops;
+	bws->ref = ref;
+	if (name)
+		strncpy(bws->name, name, 16);
+
+	kref_init(&bws->kref);
+	kref_get(&bws->kref);
+
+	spin_lock_irqsave(&bwc.lock, flags);
+	list_add_tail(&bws->list, &bwc.head);
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_register);
+
+/* This function is called with bwc lock held*/
+static void brcm_pm_wakeup_cleanup(struct kref *kref)
+{
+	struct brcm_wakeup_source *bws =
+		container_of(kref, struct brcm_wakeup_source, kref);
+	list_del(&bws->list);
+	kfree(bws);
+}
+
+int brcm_pm_wakeup_unregister(struct brcm_wakeup_ops *ops, void *ref)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list)
+		if (bws->ops == ops && bws->ref == ref)
+			kref_put(&bws->kref, brcm_pm_wakeup_cleanup);
+
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	return 0;
+}
+
+static int brcm_pm_wakeup_enable(void)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->enable)
+			bws->ops->enable(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+	return 0;
+}
+
+static int brcm_pm_wakeup_disable(void)
+{
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->disable)
+			bws->ops->disable(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+	return 0;
+}
+
+/*
+Function asks all registered objects if a wakeup event has happened.
+If no registered object claims the event, it checks for all interrupts
+enabled prior to suspend.
+It returns 0 if no valid wake up event has occurred, 1 otherwise.
+*/
+static int brcm_pm_wakeup_poll(u32 mask)
+{
+	int ev_occurred = 0;
+	struct brcm_wakeup_source *bws;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bwc.lock, flags);
+
+	list_for_each_entry(bws, &bwc.head, list) {
+		if (bws->ops && bws->ops->poll)
+			ev_occurred |= bws->ops->poll(bws->ref);
+	}
+	spin_unlock_irqrestore(&bwc.lock, flags);
+
+	/* Check for events outside of kernel control */
+	if (!ev_occurred)
+		ev_occurred |= brcm_pm_wakeup_get_status(~mask);
+
+	return ev_occurred;
+}
+
+int brcm_pm_wakeup_init(void)
+{
+	spin_lock_init(&bwc.lock);
+	INIT_LIST_HEAD(&bwc.head);
+	return 0;
+}
+early_initcall(brcm_pm_wakeup_init);
+
+/***********************************************************************
+ * USB / ENET / GENET / MoCA / SATA PM implementations (per-chip)
+ ***********************************************************************/
+static __maybe_unused void brcm_ddr_phy_initialize(void);
+
+/*
+ * Per-block power management operations pair.
+ * Parameter flags is used to control wake-up capabilities
+ */
+
+struct brcm_chip_pm_block_ops {
+	void (*enable)(u32 flags);
+	void (*disable)(u32 flags);
+	int (*set_cpu_rate)(unsigned long rate);
+	int (*set_phy_rate)(unsigned long rate);
+};
+
+static u32 brcm_pm_flags;
+
+struct brcm_chip_pm_ops {
+	/* SATA power/clock gating */
+	struct brcm_chip_pm_block_ops sata;
+	/* genet0 power/clock gating */
+	struct brcm_chip_pm_block_ops genet;
+	/* genet1 power/clock gating */
+	struct brcm_chip_pm_block_ops genet1;
+	/* MoCA power/clock gating */
+	struct brcm_chip_pm_block_ops moca;
+	/* USB power/clock gating */
+	struct brcm_chip_pm_block_ops usb;
+	/* genet0/genet1/MoCA common power/clock gating */
+	struct brcm_chip_pm_block_ops network;
+	/* system-wide initialization code */
+	void (*initialize)(void);
+	/* system suspend code */
+	void (*suspend)(u32 flags);
+	/* system resume code */
+	void (*resume)(u32 flags);
+	/*
+	 * System suspend code executed immediately before
+	 * initiating low-level suspend sequence.
+	 * For example, shutting down secondary memory controller
+	 * can be done here when system no longer uses highmem regions
+	 */
+	void (*late_suspend)(int is_s3);
+	void (*early_resume)(int is_s3);
+	/* for chip specific clock mappings ( see #SWLINUX-1764 ) */
+	struct clk* (*clk_get)(struct device *dev, const char *id);
+};
+
+#define DEF_BLOCK_PM_OP(block, chip) \
+	.block.enable	= bcm##chip##_pm_##block##_enable, \
+	.block.disable	= bcm##chip##_pm_##block##_disable
+#define DEF_SYSTEM_PM_OP(chip) \
+	.suspend	= bcm##chip##_pm_suspend, \
+	.resume		= bcm##chip##_pm_resume
+#define DEF_SYSTEM_LATE_PM_OP(chip) \
+	.late_suspend	= bcm##chip##_pm_late_suspend, \
+	.early_resume	= bcm##chip##_pm_early_resume
+
+#define PLL_CH_DIS(x)		BDEV_WR_RB(BCHP_##x, 0x04)
+#define PLL_CH_ENA(x)		do { \
+					BDEV_WR_RB(BCHP_##x, 0x03); \
+					mdelay(1); \
+				} while (0)
+
+#define PLL_DIS(x)		BDEV_WR_RB(BCHP_##x, 0x04)
+#define PLL_ENA(x)		do { \
+					BDEV_WR_RB(BCHP_##x, 0x03); \
+					mdelay(1); \
+				} while (0)
+
+static __maybe_unused struct clk *brcm_pm_clk_get(struct device *dev,
+	const char *id)
+{
+	if (!strncmp(id, "enet", 4) && dev) {
+		struct platform_device *pdev = to_platform_device(dev);
+		if (pdev->id == 0) /* enet */
+			return brcm_pm_clk_find(id);
+		if (pdev->id == 1) /* moca_genet */ {
+			if (strstr(id, "-wol"))
+				return brcm_pm_clk_find("moca-wol");
+			return brcm_pm_clk_find("moca");
+		}
+	}
+
+	return NULL;
+}
+
+/***********************************************************************
+ * Encryption setup for S3 suspend
+ ***********************************************************************/
+static struct brcm_dram_encoder_ops *dram_encoder_ops;
+
+void brcm_pm_set_dram_encoder(struct brcm_dram_encoder_ops *ops)
+{
+	dram_encoder_ops = ops;
+}
+EXPORT_SYMBOL(brcm_pm_set_dram_encoder);
+
+int brcm_pm_dram_encoder_prepare(struct brcm_mem_transfer *param)
+{
+	if (dram_encoder_ops && dram_encoder_ops->prepare)
+		return dram_encoder_ops->prepare(param);
+	return -1;
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_prepare);
+
+int brcm_pm_dram_encoder_complete(struct brcm_mem_transfer *param)
+{
+	if (dram_encoder_ops && dram_encoder_ops->complete)
+		return dram_encoder_ops->complete(param);
+	return -1;
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_complete);
+
+void brcm_pm_dram_encoder_start(void)
+{
+	if (dram_encoder_ops && dram_encoder_ops->start)
+		dram_encoder_ops->start();
+}
+EXPORT_SYMBOL(brcm_pm_dram_encoder_start);
+
+#if defined(CONFIG_BCM7125)
+static void bcm7125_pm_sata_disable(u32 flags)
+{
+	BDEV_WR_F_RB(SUN_TOP_CTRL_GENERAL_CTRL_1, sata_ana_pwrdn, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_99P7, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_108, 1);
+	PLL_CH_DIS(VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4);
+}
+
+static void bcm7125_pm_sata_enable(u32 flags)
+{
+	PLL_CH_ENA(VCXO_CTL_MISC_RAP_AVD_PLL_CHL_4);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA_CLK_PM_CTRL, DIS_CLK_99P7, 0);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_GENERAL_CTRL_1, sata_ana_pwrdn, 0);
+}
+
+static void bcm7125_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_ENET_CG_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_GMII_CG_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_HFB, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_L2_INTR, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_UNIMAC_SYS_TX, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_216, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_250_GENET_MOCA, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_54, 1);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_108, 1);
+		return;
+	}
+	BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL, 0xf77);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL, 0x04);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL, 0x04);
+	BDEV_SET_RB(BCHP_CLKGEN_PLL_MOCA_CTRL, 0x13);
+}
+
+static void bcm7125_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_ENET_CG_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_GMII_CG_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_L2_INTR, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_UNIMAC_SYS_TX, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_216, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL,
+			DIS_CLK_250_GENET_MOCA, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_54, 0);
+		BDEV_WR_F_RB(CLKGEN_MOCA_CLK_PM_CTRL, DIS_CLK_108, 0);
+		return;
+	}
+	BDEV_UNSET_RB(BCHP_CLKGEN_PLL_MOCA_CTRL, 0x13);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH6_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH5_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH4_PM_CTRL, 0x01);
+	BDEV_WR_RB(BCHP_CLKGEN_PLL_MOCA_CH3_PM_CTRL, 0x01);
+	BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL, 0xf77);
+}
+
+static void bcm7125_pm_usb_disable(u32 flags)
+{
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x00);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 1);
+	PLL_CH_DIS(CLKGEN_PLL_MAIN_CH4_PM_CTRL);
+}
+
+static void bcm7125_pm_usb_enable(u32 flags)
+{
+	PLL_CH_ENA(CLKGEN_PLL_MAIN_CH4_PM_CTRL);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0f);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+}
+
+static void bcm7125_pm_suspend(u32 flags)
+{
+	/* PCI/EBI */
+	BDEV_WR_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x3ff8);
+	BDEV_WR_F_RB(CLKGEN_CLK_27_OUT_PM_CTRL, DIS_CLK_27_OUT, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 1);
+	BDEV_SET_RB(BCHP_CLKGEN_HIF_CLK_PM_CTRL, 0x3c);
+
+	/* system PLLs */
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x04);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, 0x07);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 1);
+
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7125_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, 0x07);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x04);
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+
+	/* PCI/EBI */
+	BDEV_UNSET_RB(BCHP_CLKGEN_HIF_CLK_PM_CTRL, 0x3c);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_CLK_27_OUT_PM_CTRL, DIS_CLK_27_OUT, 0);
+	BDEV_WR_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x00);
+
+	brcm_ddr_phy_initialize();
+}
+
+/* There is no non-MoCA GENET on 7125, so any request for 'enet' clock is
+ * redirected to 'moca'
+ */
+static struct clk *bcm7125_pm_clk_get(struct device *dev, const char *id)
+{
+	if (!strncmp(id, "enet", 4)) {
+		if (strstr(id, "-wol"))
+			return brcm_pm_clk_find("moca-wol");
+		else
+			return brcm_pm_clk_find("moca");
+	}
+	return NULL;
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7125),
+	DEF_BLOCK_PM_OP(sata, 7125),
+	DEF_BLOCK_PM_OP(network, 7125),
+	DEF_SYSTEM_PM_OP(7125),
+	.clk_get		= bcm7125_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7340)
+
+static void bcm7340_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/*
+		 * TODO: Stop HFB clock and switch to 27MHz if ACPI
+		 * detector is disabled
+		 */
+#if 0
+		/* TODO: on 1000Mbit link use 54MHz clock and MAIN PLL */
+		BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MAIN_PLL, 1);
+		mdelay(1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_CG_GENET, 1);
+#endif
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,
+			CLOCK_SEL_CG_GENET, 0);
+
+		BDEV_SET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK);
+		return;
+	}
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, EN_CMLBUF_CH4, 0);
+	BDEV_SET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK);
+}
+
+static void bcm7340_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		    BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK);
+		/* switch to faster 54MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS,	CLOCK_SEL_CG_GENET, 1);
+		return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLKGEN_GENET_CLK_PM_CTRL,
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK|
+		BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, EN_CMLBUF_CH4, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH4_PM_CTRL, PWRDN_CH, 0);
+}
+
+static void bcm7340_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+#if 0
+		/* TODO: on 1000Mbit link use 54MHz clock and MAIN PLL */
+		BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MAIN_PLL, 1);
+		mdelay(1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA,
+			1);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA,
+			0);
+#endif
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA,
+			0);
+		BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA,
+			1);
+	    BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+	    return;
+	}
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, EN_CMLBUF_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, PWRDN_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, ENB_CLOCKOUT_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, EN_CMLBUF_CH6, 0);
+	BDEV_SET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+}
+
+static void bcm7340_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+
+	    /* Restore fast clocks */
+	    BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_ENET_CG_MOCA, 1);
+	    BDEV_WR_F_RB(CLKGEN_MISC_CLOCK_SELECTS, CLOCK_SEL_GMII_CG_MOCA, 0);
+
+	    return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLKGEN_MOCA_CLK_PM_CTRL,
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK|
+		BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, EN_CMLBUF_CH6, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH6_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH3_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH2_PM_CTRL, PWRDN_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, EN_CMLBUF_CH, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, ENB_CLOCKOUT_CH, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CH1_PM_CTRL, PWRDN_CH, 0);
+}
+
+static void bcm7340_pm_usb_disable(u32 flags)
+{
+	/* reset and power down all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x0);
+
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 1);
+	/* disable PLL */
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH4_PM_CTRL, PWRDN_CH4_PLLMAIN, 1);
+}
+
+static void bcm7340_pm_usb_enable(u32 flags)
+{
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH4_PM_CTRL, PWRDN_CH4_PLLMAIN, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLK_PM_CTRL, DIS_CLK_216, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xF);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7340_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN_LDO, 1);
+}
+
+static void bcm7340_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN_LDO, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, PWRDN, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMOCA_CTRL, DRESET, 0);
+}
+
+static void bcm7340_pm_suspend(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* PCI/EBI */
+	BDEV_WR_F_RB(CLKGEN_PAD_CLK_PM_CTRL, DIS_CLK_33_27_PCI, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH5_PM_CTRL, PWRDN_CH5_PLLMAIN, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_81, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_27, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_54, 1);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_216_CG, 1);
+	BDEV_WR_F_RB(CLKGEN_HIF_CLK_PM_CTRL, DIS_CLK_SPI, 1);
+
+	/* system PLLs */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, POWERDOWN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, PWRDN, 1);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, RESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, POWERDOWN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ENB_CLOCKOUT, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, PWRDN, 1);
+
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 1);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 1);
+
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7340_pm_resume(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* system PLLs */
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_108, 0);
+	BDEV_WR_F_RB(CLKGEN_VCXO_CLK_PM_CTRL, DIS_CLK_216, 0);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, PWRDN, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_CTRL, ENB_CLOCKOUT, 0);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, RESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, POWERDOWN, 0);
+
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, PWRDN, 1);
+	BDEV_WR_F_RB(CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL, EN_CMLBUF, 0);
+
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, POWERDOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC1_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 0);
+
+	/* PCI/EBI */
+	BDEV_WR_F_RB(CLKGEN_HIF_CLK_PM_CTRL, DIS_CLK_SPI, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_216_CG, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_54, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_27, 0);
+	BDEV_WR_F_RB(CLKGEN_CG_CLK_PM_CTRL, DIS_CLK_81, 0);
+	BDEV_WR_F_RB(CLKGEN_PLLMAIN_CH5_PM_CTRL, PWRDN_CH5_PLLMAIN, 0);
+	BDEV_WR_F_RB(CLKGEN_PAD_CLK_PM_CTRL, DIS_CLK_33_27_PCI, 0);
+
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7340),
+	DEF_BLOCK_PM_OP(moca, 7340),
+	DEF_BLOCK_PM_OP(genet, 7340),
+	DEF_BLOCK_PM_OP(network, 7340),
+	DEF_SYSTEM_PM_OP(7340),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7408)
+static void bcm7408_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/*
+	 * 7408B0 does not support MoCA WOL due to a h/w bug. The
+	 * following code is added in case the bug is fixed in the next
+	 * revision
+	 * http://jira.broadcom.com/browse/HW7408-186
+	 */
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_GMII_TX_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_GENET_RGMII_216M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_L2_INTR_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_GMII_TX_27_108M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_54M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_216M_CLK, 1);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_108M_CLK, 1);
+		return;
+	}
+	BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_ENET_HFB_27_108M_CLK, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, EN_CMLBUF, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_6, DIS_CH, 1);
+	BDEV_SET_RB(BCHP_CLK_MOCA_CLK_PM_CTRL, 0x6ab);
+}
+
+static void bcm7408_pm_network_enable(u32 flags)
+{
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_GENET_RGMII_216M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_L2_INTR_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL,
+			DIS_MOCA_ENET_GMII_TX_27_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_54M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_216M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_CLK_SEL, 0);
+		BDEV_WR_F_RB(CLK_MISC, MOCA_ENET_GMII_TX_CLK_SEL, 0);
+		return;
+	}
+	BDEV_UNSET_RB(BCHP_CLK_MOCA_CLK_PM_CTRL, 0x6ab);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_6, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_5, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_4, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_3, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_MOCA_CLK_PM_CTRL, DIS_MOCA_ENET_HFB_27_108M_CLK, 0);
+}
+
+static void bcm7408_pm_usb_disable(u32 flags)
+{
+	/* reset and power down all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	BDEV_SET_RB(BCHP_CLK_USB_CLK_PM_CTRL,
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_MASK);
+
+	/* disable PLL */
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, DIS_CH, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, EN_CMLBUF, 0);
+}
+
+static void bcm7408_pm_usb_enable(u32 flags)
+{
+	/* enable PLL */
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, EN_CMLBUF, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_0_4, DIS_CH, 0);
+	/* enable the clocks */
+	BDEV_UNSET_RB(BCHP_CLK_USB_CLK_PM_CTRL,
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_54M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_108M_CLK_MASK|
+		BCHP_CLK_USB_CLK_PM_CTRL_DIS_216M_CLK_MASK);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xE);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	/* power up all 4 ports */
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7408_pm_suspend(u32 flags)
+{
+	/* UART */
+	if (!(brcm_pm_standby_flags & BRCM_STANDBY_VERBOSE)) {
+		BDEV_WR_F_RB(CLK_SUN_27M_CLK_PM_CTRL,
+			DIS_SUN_27M_CLK, 1);
+		BDEV_WR_F_RB(CLK_SUN_UART_CLK_PM_CTRL,
+			DIS_SUN_UART_108M_CLK, 1);
+	}
+	/* PAD clocks */
+	BDEV_WR_F_RB(CLK_MISC, VCXOA_OUTCLK_ENABLE, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 1);
+
+	/* system PLLs */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 1);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		CML_2_N_P_EN, 1);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		FREQ_DOUBLER_POWER_DOWN, 1);
+
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, DRESET, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, ARESET, 1);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, POWERDOWN, 1);
+
+	/* MEMC0 */
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 0);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_RB(BCHP_DDR23_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL, 0x132);
+	BDEV_SET_RB(BCHP_DDR23_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL, 0xfffff);
+	BDEV_SET_RB(BCHP_DDR23_PHY_BYTE_LANE_1_0_IDLE_PAD_CONTROL, 0xfffff);
+
+}
+
+static void bcm7408_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(CLK_SYS_PLL_1_CTRL, POWERDOWN, 0);
+
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		CML_2_N_P_EN, 0);
+	BDEV_WR_F_RB(CLK_THIRD_OT_CONTROL_1,
+		FREQ_DOUBLER_POWER_DOWN, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, DRESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, ARESET, 0);
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_CTRL, POWERDOWN, 0);
+
+	/* PAD clocks */
+	BDEV_WR_F_RB(VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, DIS_CH, 0);
+	BDEV_WR_F_RB(CLK_MISC, VCXOA_OUTCLK_ENABLE, 1);
+
+	/* UART */
+	if (!(brcm_pm_standby_flags & BRCM_STANDBY_VERBOSE)) {
+		BDEV_WR_F_RB(CLK_SUN_UART_CLK_PM_CTRL,
+			DIS_SUN_UART_108M_CLK, 0);
+		BDEV_WR_F_RB(CLK_SUN_27M_CLK_PM_CTRL,
+			DIS_SUN_27M_CLK, 0);
+	}
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(network, 7408),
+	DEF_BLOCK_PM_OP(usb, 7408),
+	DEF_SYSTEM_PM_OP(7408),
+};
+#endif
+
+#if defined(CONFIG_BCM7468)
+
+static void bcm7468_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slower 27MHz clocks */
+		BDEV_WR_F_RB(CLK_MISC, GENET_CLK_SEL, 1);
+		BDEV_WR_F_RB(CLK_MISC, GENET_GMII_TX_CLK_SEL, 1);
+		BDEV_SET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x503);
+		return;
+	}
+
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_4, 1);
+	BDEV_SET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x767);
+}
+
+static void bcm7468_pm_genet_enable(u32 flags)
+{
+	if (ENET_WOL(flags)) {
+		BDEV_UNSET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x503);
+		BDEV_WR_F_RB(CLK_MISC, GENET_CLK_SEL, 0);
+		BDEV_WR_F_RB(CLK_MISC, GENET_GMII_TX_CLK_SEL, 0);
+		return;
+	}
+
+	BDEV_UNSET_RB(BCHP_CLK_GENET_CLK_PM_CTRL, 0x767);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_4, 0);
+}
+
+static void bcm7468_pm_usb_disable(u32 flags)
+{
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0x00);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 1);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0x00);
+
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 0);
+	BDEV_SET_RB(BCHP_CLK_USB_CLK_PM_CTRL, 0x07);
+}
+
+static void bcm7468_pm_usb_enable(u32 flags)
+{
+	BDEV_UNSET_RB(BCHP_CLK_USB_CLK_PM_CTRL, 0x07);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, XTAL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL_1, PLL_PWRDWNB, 1);
+
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_SOFT_RESETB, 0xF);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, UTMI_IDDQ, 0);
+	BDEV_WR_F_RB(USB_CTRL_UTMI_CTL_1, PHY_PWDNB, 0xF);
+}
+
+static void bcm7468_pm_suspend(u32 flags)
+{
+	/* SDIO */
+	BDEV_WR_F_RB(CLK_HIF_SDIO_CLK_PM_CTRL, DIS_HIF_SDIO_48M_CLK, 1);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_1, 1);
+
+	/* EBI */
+	BDEV_SET_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x2ff0);
+
+	/* system PLLs */
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_0_3, 0x02);
+
+	if (!ENET_WOL(flags))
+		/* this PLL is needed for EPHY */
+		BDEV_SET_RB(BCHP_CLK_SYS_PLL_1_CTRL, 0x83);
+
+	BDEV_WR_RB(BCHP_VCXO_CTL_MISC_AC1_CTRL, 0x06);
+	BDEV_SET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+}
+
+static void bcm7468_pm_resume(u32 flags)
+{
+	/* system PLLs */
+	BDEV_UNSET_RB(BCHP_VCXO_CTL_MISC_VC0_CTRL, 0x0b);
+	BDEV_WR_RB(BCHP_VCXO_CTL_MISC_AC1_CTRL, 0x00);
+	BDEV_UNSET_RB(BCHP_CLK_SYS_PLL_1_CTRL, 0x83);
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_0_3, 0x01);
+
+	/* EBI */
+	BDEV_UNSET_RB(BCHP_HIF_TOP_CTRL_PM_CTRL, 0x2ff0);
+
+	/* SDIO */
+	BDEV_WR_RB(BCHP_CLK_SYS_PLL_1_1, 0);
+	BDEV_WR_F_RB(CLK_HIF_SDIO_CLK_PM_CTRL, DIS_HIF_SDIO_48M_CLK, 0);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7468),
+	DEF_BLOCK_PM_OP(genet, 7468),
+	DEF_SYSTEM_PM_OP(7468),
+};
+#endif
+
+/* 40nm chips start here */
+
+#if	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7425) || \
+	defined(CONFIG_BCM7429) || \
+	defined(CONFIG_BCM7435) || \
+	defined(CONFIG_BCM7346) || \
+	defined(CONFIG_BCM7231) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7584) || \
+	defined(CONFIG_BCM7563) || \
+	defined(CONFIG_BCM7344) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+static __maybe_unused int mem_power_down = 1;
+
+#undef PLL_CH_ENA
+#undef PLL_CH_DIS
+#undef PLL_ENA
+#undef PLL_DIS
+
+#define PLL_CH_DIS(pll, ch) do { \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, POST_DIVIDER_HOLD_CH ## ch, 1); \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, CLOCK_DIS_CH ## ch, 1); \
+} while (0)
+
+#define PLL_CH_ENA(pll, ch) do { \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, CLOCK_DIS_CH ## ch, 0); \
+	BDEV_WR_F_RB(pll ## _CH_ ## ch, POST_DIVIDER_HOLD_CH ## ch, 0); \
+} while (0)
+
+#define PLL_DIS(pll) do { \
+	BDEV_WR_F_RB(pll ## _RESET, RESETD, 1); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETA, 1); \
+	BDEV_WR_F_RB(pll ## _PWRDN, PWRDN_PLL, 1); \
+} while (0)
+
+#define PLL_ENA(pll) do { \
+	BDEV_WR_F_RB(pll ## _PWRDN, PWRDN_PLL, 0); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETA, 0); \
+	BDEV_WR_F_RB(pll ## _RESET, RESETD, 0); \
+	do { \
+		mdelay(1); \
+	} while (!BDEV_RD_F(pll ## _LOCK_STATUS, LOCK)); \
+} while (0)
+
+
+/* IMPORTANT: must be done in TWO steps per RDB note */
+#define POWER_UP_MEMORY_3(core, mask, inst) \
+do { \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst,\
+		mask ## _POWER_SWITCH_MEMORY ## inst, 2); \
+	udelay(10); \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst,\
+		mask ## _POWER_SWITCH_MEMORY ## inst, 0); \
+} while (0)
+
+#define POWER_UP_MEMORY_1(core) POWER_UP_MEMORY_3(core, core, \
+	)
+#define POWER_UP_MEMORY_1ii(core) \
+	POWER_UP_MEMORY_2(core ## _INST, core ## _INST)
+#define POWER_UP_MEMORY_2(core, mask) POWER_UP_MEMORY_3(core, mask, \
+	)
+#define POWER_UP_MEMORY_2i(core, mask) POWER_UP_MEMORY_3(core ## _INST, mask, \
+	)
+#define POWER_UP_MEMORY_3i(core, mask, inst) \
+	POWER_UP_MEMORY_3(core ## _INST, mask, inst)
+
+#define SRAM_OFF_3(core, mask, inst) \
+do { \
+	if (mem_power_down) \
+		BDEV_WR_F_RB( \
+			CLKGEN_ ## core ## _POWER_SWITCH_MEMORY ## inst, \
+			mask ## _POWER_SWITCH_MEMORY ## inst, 3); \
+	else \
+		BDEV_WR_F_RB( \
+			CLKGEN_ ## core ## _MEMORY_STANDBY_ENABLE ## inst, \
+			mask ## _MEMORY_STANDBY_ENABLE ## inst, 1); \
+} while (0)
+
+#define SRAM_OFF_1i(core) SRAM_OFF_3(core ## _INST, core, \
+	)
+#define SRAM_OFF_1(core) SRAM_OFF_3(core, core, \
+	)
+#define SRAM_OFF_2i(core, mask) SRAM_OFF_3(core ## _INST, mask, \
+	)
+#define SRAM_OFF_3i(core, mask, inst) SRAM_OFF_3(core ## _INST, mask, inst)
+#define SRAM_OFF_2(core, mask) SRAM_OFF_3(core, mask, \
+	)
+
+#define SRAM_ON_3(core, mask, inst) \
+do { \
+	if (mem_power_down) \
+		POWER_UP_MEMORY_3(core, mask, inst); \
+	else \
+	BDEV_WR_F_RB(CLKGEN_ ## core ## _MEMORY_STANDBY_ENABLE ## inst, \
+		mask ## _MEMORY_STANDBY_ENABLE ## inst, 0); \
+} while (0)
+
+#define SRAM_ON_1i(core) SRAM_ON_3(core ## _INST, core, \
+	)
+#define SRAM_ON_1(core) SRAM_ON_3(core, core, \
+	)
+#define SRAM_ON_2i(core, mask) SRAM_ON_3(core ## _INST, mask, \
+	)
+#define SRAM_ON_2(core, mask) SRAM_ON_3(core, mask, \
+	)
+#define SRAM_ON_3i(core, mask, inst) SRAM_ON_3(core ## _INST, mask, inst)
+#endif
+
+/******************************************************************
+ *   USB recovery after S3 warm boot
+ * These parameters are mostly configured by CFE on cold boot, some
+ * of them are set during HC reset code which we do not execute on
+ * warm boot because it re-allocates memory.
+ * The code will probably work on all 40nm chips, but we will see...
+ ******************************************************************/
+static u32 usb_cfg[4];
+
+static __maybe_unused void bcm40nm_pm_usb_disable_s3(void)
+{
+	if (!brcm_pm_deep_sleep())
+		return;
+#ifdef BCHP_USB_CTRL_SETUP
+	usb_cfg[0] = BDEV_RD(BCHP_USB_CTRL_SETUP);
+	usb_cfg[1] = BDEV_RD(BCHP_USB_CTRL_EBRIDGE);
+#endif
+#ifdef BCHP_USB1_CTRL_SETUP
+	if (BRCM_PROD_ID() != 0x74285) {
+		usb_cfg[2] = BDEV_RD(BCHP_USB1_CTRL_SETUP);
+		usb_cfg[3] = BDEV_RD(BCHP_USB1_CTRL_EBRIDGE);
+	}
+#endif
+}
+
+static __maybe_unused void bcm40nm_pm_usb_enable_s3(void)
+{
+	if (!brcm_pm_deep_sleep())
+		return;
+	printk(KERN_DEBUG "Restoring USB HC state from S3 suspend\n");
+#ifdef BCHP_USB_CTRL_SETUP
+	BDEV_WR_RB(BCHP_USB_CTRL_SETUP, usb_cfg[0]);
+	BDEV_WR_RB(BCHP_USB_CTRL_EBRIDGE, usb_cfg[1]);
+#endif
+#ifdef BCHP_USB1_CTRL_SETUP
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_WR_RB(BCHP_USB1_CTRL_SETUP, usb_cfg[2]);
+		BDEV_WR_RB(BCHP_USB1_CTRL_EBRIDGE, usb_cfg[3]);
+	}
+#endif
+	mdelay(500);
+	bchip_usb_init();
+}
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7429) \
+	|| defined(CONFIG_BCM7346) || defined(CONFIG_BCM7435)
+
+#define BRCM_BASE_CLK		3600 /* base clock in MHz */
+
+/*
+ * work around RDB name inconsistencies.
+ */
+#if defined(BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK)
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK)
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK \
+	BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT \
+	BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK)
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_SHIFT
+
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_SHIFT
+#endif
+
+#if defined(BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE)
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT \
+	BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT
+#endif
+
+static void bcm40nm_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* USB0 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1i(USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB0_54_MDIO_CLOCK, 1);
+
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+	/* power down USB PHY */
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+		/* power down USB PLL */
+		BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	}
+
+	SRAM_OFF_1i(USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB1_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+#if defined(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4)
+	/* power down PLL */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+#endif
+}
+
+static void bcm40nm_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* power up PLL */
+#if defined(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4)
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+#endif
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB0_54_MDIO_CLOCK, 0);
+
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1i(USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB1_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1i(USB1);
+
+	/* power up USB PLL */
+	if (BRCM_PROD_ID() != 0x74285) {
+		BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+		/* power up USB PHY */
+		BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+			BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	}
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+/* These are not defined in the RDB headers for any 40nm chips. */
+#define SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK	BIT(8)
+#define SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK	BIT(12)
+#define SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK	BIT(12)
+
+static void bcm40nm_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* put PHY into slumber mode */
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_1,
+		SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK);
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_2,
+		SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK);
+	BDEV_SET(BCHP_SATA_TOP_CTRL_PHY_CTRL_3,
+		SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK);
+
+	SRAM_OFF_2i(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+#if !(defined(CONFIG_BCM7429B0) || defined(CONFIG_BCM7435B0))
+	BDEV_WR_F_RB(CLKGEN_SATA3_INST_CLOCK_DISABLE,
+		DISABLE_27_FUNC_CLK_30, 1);
+#endif
+}
+
+static void bcm40nm_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+#if !(defined(CONFIG_BCM7429B0) || defined(CONFIG_BCM7435B0))
+	BDEV_WR_F_RB(CLKGEN_SATA3_INST_CLOCK_DISABLE,
+		DISABLE_27_FUNC_CLK_30, 0);
+#endif
+
+	SRAM_ON_2i(SATA3_TOP, SATA3);
+
+	/* take PHY out from slumber */
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_3,
+		SATA_TOP_CTRL_PHY_CTRL_3_SW_TX1_SLUMBER_MASK);
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_2,
+		SATA_TOP_CTRL_PHY_CTRL_2_SW_TX0_SLUMBER_MASK);
+	BDEV_UNSET(BCHP_SATA_TOP_CTRL_PHY_CTRL_1,
+		SATA_TOP_CTRL_PHY_CTRL_1_DIS_HW_SLUMBER_MASK);
+}
+
+/* If GENET_1 uses the RGMII_0 pad which is controlled by GENET_0's
+ * clocks, then we need to make sure we do not disable that clock
+ */
+static inline unsigned int genet_needs_clk_250(void)
+{
+	u32 mac_select = 0;
+
+#ifdef BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK
+	mac_select = BDEV_RD_F(SUN_TOP_CTRL_GENERAL_CTRL_0,
+			mii_genet_mac_select);
+#endif
+	/* GENET_1 does not use the RGMII_0 pad */
+	if (mac_select == 0)
+		return 0;
+
+	/* MoCA and internal PHY do not use the RGMII pad */
+	switch (genet_pdata[1].phy_interface) {
+	case PHY_INTERFACE_MODE_NA:
+	case PHY_INTERFACE_MODE_MOCA:
+		return 0;
+	default:
+		return 1;
+	}
+}
+
+static void bcm40nm_pm_genet_disable(u32 flags)
+{
+	unsigned int __maybe_unused needs_clk_250 = genet_needs_clk_250();
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A)
+	SRAM_OFF_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xe);
+
+		/* Every genet0 clock except 108 or 250 for RGMII */
+		if (!needs_clk_250)
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fe);
+		else
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fc);
+	}
+
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0)
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		    0x1e);
+
+		/* Every genet0 clock except 108 or 250 */
+		if (!needs_clk_250)
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fe);
+		else
+			BDEV_UNSET(
+			  BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+			  0x1fc);
+	}
+#else
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x43); /* used to be 0x53 */
+	} else {
+		/* system slow clock, pm clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    3);
+
+		/* Every gnet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x7F);
+	}
+#endif
+}
+
+static void bcm40nm_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A)
+	SRAM_ON_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 0);
+
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xf);
+
+		/* Every genet0 clock */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x1ff);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0)
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_CLOCK_SELECT_GENET0, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0,
+		    GENET0_GMII_CLOCK_SELECT_GENET0, 0);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x106);
+	} else {
+		/* every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		    0x1f);
+
+		/* Every genet0 clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		    0x1ff);
+	}
+#else
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 0);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x43);
+	} else {
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    3);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x7F);
+	}
+#endif
+
+}
+
+static void bcm40nm_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(CONFIG_BCM7425)
+	if (mem_power_down)
+		/* power down memory */
+	    BDEV_WR_F_RB(
+		CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B,
+		GENET1_POWER_SWITCH_MEMORY_B, 3);
+	else
+		/* memory to standby */
+	    BDEV_WR_F_RB(
+		CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A,
+		GENET1_MEMORY_STANDBY_ENABLE_A, 1);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xe0);
+
+		/* Every genet1 clock except 108 */
+		BDEV_UNSET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1fe);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 1);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every clock except AON */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		    0x1e);
+
+		/* Every genet1 clock except 108 */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1fe);
+	}
+#else
+	if (MOCA_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET1_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x2180); /* 0x2980 */
+	} else {
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x3F80);
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xC);
+	}
+#endif
+}
+
+static void bcm40nm_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(CONFIG_BCM7425)
+	if (mem_power_down)
+		/* power up memory */
+		POWER_UP_MEMORY_3i(DUAL_GENET_TOP_DUAL_RGMII, GENET1, _B);
+	else
+		/* memory from standby */
+BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A,
+		GENET1_MEMORY_STANDBY_ENABLE_A, 0);
+#endif
+
+#if defined(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 0);
+
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every genet 1 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		    0xf0);
+
+		/* Every genet 1 clock */
+		BDEV_SET(
+		 BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1ff);
+	}
+#elif defined(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1)
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_CLOCK_SELECT_GENET1, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1,
+		    GENET1_GMII_CLOCK_SELECT_GENET1, 0);
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x106);
+	} else {
+		/* every genet 1 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		    0x1f);
+
+		/* Every genet 1 clock */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		    0x1ff);
+	}
+#else
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		0xC);
+
+	if (MOCA_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 0);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x2180);
+	} else {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		    0x3F80);
+	}
+#endif
+
+}
+
+static void bcm40nm_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+#if defined(BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY)
+	SRAM_OFF_2i(MOCA_TOP, MOCA);
+#endif
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 0);
+
+	if (!MOCA_WOL(flags)) {
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+#if !defined(CONFIG_BCM7435)
+		PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	}
+}
+
+static void bcm40nm_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (!MOCA_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+#if !defined(CONFIG_BCM7435)
+		PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	}
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 1);
+
+#if defined(BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY)
+	SRAM_ON_2i(MOCA_TOP, MOCA);
+#endif
+}
+
+static int bcm40nm_pm_set_moca_cpu_rate(unsigned long rate)
+{
+#ifdef BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0
+	BDEV_WR_F(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0,
+		MDIV_CH0, BRCM_BASE_CLK/(rate/1000000));
+	return 0;
+#else
+	return -EINVAL;
+#endif
+}
+
+static int bcm40nm_pm_set_moca_phy_rate(unsigned long rate)
+{
+#ifdef BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1
+	BDEV_WR_F(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1,
+		MDIV_CH1, BRCM_BASE_CLK/(rate/1000000));
+	return 0;
+#else
+	return -ENOENT;
+#endif
+}
+
+#endif
+
+#if defined(CONFIG_BCM7231)
+
+static void bcm7231_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+	/* USB0 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1(USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	SRAM_OFF_1(USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+	/* power down PLL */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+}
+
+static void bcm7231_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* power up PLL */
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1(USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_1(USB1);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7231_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	SRAM_OFF_2(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7231_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2(SATA3_TOP, SATA3);
+
+}
+
+static void bcm7231_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		/* Disabling L2_INTR clock breaks HFB pattern matching ??? */
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x43); /* used to be 0x53 */
+		return;
+	}
+
+	SRAM_OFF_2(DUAL_GENET_TOP_DUAL_RGMII, GENET0);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 7);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7231_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x43); /* used to be 0x53 */
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	SRAM_ON_2(DUAL_GENET_TOP_DUAL_RGMII, GENET0);
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 7);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7231_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_GMII_CLOCK_SELECT, 1);
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x2980);
+		return;
+	}
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0x38);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x3F80);
+}
+
+static void bcm7231_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+			   0x2980);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+			GENET1_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0x38);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE, 0x3F80);
+}
+
+static void bcm7231_pm_suspend(u32 flags)
+{
+}
+
+static void bcm7231_pm_resume(u32 flags)
+{
+}
+
+static void bcm7231_pm_initialize(void)
+{
+	/* test scan clocks */
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE, 0xC0);
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7231),
+	DEF_BLOCK_PM_OP(sata, 7231),
+	DEF_BLOCK_PM_OP(genet, 7231),
+	DEF_BLOCK_PM_OP(genet1, 7231),
+	DEF_SYSTEM_PM_OP(7231),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7231_pm_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7344)
+static void bcm7344_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xE0);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0xC000);
+}
+
+static void bcm7344_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0xC000);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xE0);
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+}
+
+static void bcm7344_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		/*
+		 * NOTE: disabling L2INTR clock
+		 * breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			   0x43);
+		return;
+	}
+
+	SRAM_OFF_3(DUAL_GENET_TOP_RGMII_INST, GENET0, _A);
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x3);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x7F);
+}
+
+static void bcm7344_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to fast clock */
+		BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			   0x43);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		return;
+	}
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x3);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x7F);
+
+	SRAM_ON_3(DUAL_GENET_TOP_RGMII_INST, GENET0, _A);
+}
+
+static void bcm7344_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+/*	SRAM_OFF_3(DUAL_GENET_TOP_RGMII_INST, GENET1, _B); */
+
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x1C);
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1F80);
+}
+
+static void bcm7344_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+/*	SRAM_ON_3(DUAL_GENET_TOP_RGMII_INST, GENET1, _B); */
+
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0x1C);
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1F80);
+}
+
+static void bcm7344_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* USB0 */
+
+	/* power down PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 1);
+
+	/* power down memory */
+	SRAM_OFF_2i(USB0, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+
+	/* USB1 */
+
+	/* power down PHY and PLL */
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2i(USB1, USB1);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 0);
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7344_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+
+	/* USB0 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB0_INST_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power up memory */
+	SRAM_ON_2i(USB0, USB0);
+
+	/* power up PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 1);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 0);
+
+	/* USB1 */
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_DISABLE,
+		DISABLE_USB_54_MDIO_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB1_INST_CLOCK_ENABLE, USB1_108_CLOCK_ENABLE, 1);
+
+	/* power up memory */
+	SRAM_ON_2i(USB1, USB1);
+
+	/* power up PHY and PLL */
+	BDEV_SET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+	BDEV_UNSET(BCHP_USB1_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7344_pm_moca_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+	SRAM_OFF_2i(MOCA_TOP, MOCA);
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 0);
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+}
+
+static void bcm7344_pm_moca_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (MOCA_WOL(flags)) {
+		/* TODO */
+		return;
+	}
+
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE,
+		MOCA_108_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2i(MOCA_TOP, MOCA);
+}
+
+static void bcm7344_pm_suspend(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_DIS(CLKGEN_PLL_RAAGA_PLL);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_DIS(CLKGEN_PLL_VCXO_PLL);
+
+	if (!ANY_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_SYS1_PLL);
+
+	if (!MOCA_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_MOCA_PLL);
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7344_pm_resume(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+
+	if (!MOCA_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_MOCA_PLL);
+
+	if (!ANY_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_SYS1_PLL);
+
+	PLL_ENA(CLKGEN_PLL_VCXO_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_ENA(CLKGEN_PLL_RAAGA_PLL);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7344),
+	DEF_BLOCK_PM_OP(network, 7344),
+	DEF_BLOCK_PM_OP(genet, 7344),
+	DEF_BLOCK_PM_OP(genet1, 7344),
+	DEF_BLOCK_PM_OP(moca, 7344),
+	DEF_SYSTEM_PM_OP(7344),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7346)
+
+static void bcm7346_pm_network_disable(u32 flags)
+{
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 1);
+}
+
+static void bcm7346_pm_network_enable(u32 flags)
+{
+	if (ANY_WOL(flags))
+		return;
+
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 3);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7346),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+
+#endif
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7435)
+
+static void bcm7425_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+#if defined(CONFIG_BCM7435)
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 1);
+#else
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 1);
+#endif
+}
+
+static void bcm7425_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+#if defined(CONFIG_BCM7435)
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 1);
+#else
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE,
+		DISABLE_GENET_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+#endif
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+}
+
+/*
+ * shared PLL usage.
+ *
+ * PLL  7429    7425    7435
+ * moca
+ *  0   moca    moca    moca
+ *  1   moca    moca    moca
+ *  2   moca    moca    moca
+ *  3   moca    moca    v3d
+ *  4   sdio    sdio    m2mc,sdio
+ *  5   usb0    spi     unused
+ *
+ * net
+ *  0   genet   genet   genet
+ *  1   genet   genet   genet
+ *  2   genet   genet   genet
+ *  3   spi     unused  spi
+ */
+
+static void bcm7425_pm_suspend(u32 flags)
+{
+	/*
+	 * Some PLLs are shared between blocks, so disable them last.
+	 * Do not disable network PLLs if we need WOL.
+	 */
+#if defined(CONFIG_BCM7435)
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 4);
+
+#if defined(BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5)
+	PLL_CH_DIS(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+#endif
+
+#if defined(BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3)
+	PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 3);
+#endif
+
+	if (ANY_WOL(flags) == 0) {
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 0);
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 1);
+		PLL_CH_DIS(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 2);
+		PLL_DIS(CLKGEN_PLL_NETWORK_PLL);
+	}
+}
+
+static void bcm7425_pm_resume(u32 flags)
+{
+	/*
+	 * some PLLs are shared between blocks, so enable them early
+	 */
+	PLL_ENA(CLKGEN_PLL_NETWORK_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 2);
+#if defined(BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_3)
+	PLL_CH_ENA(CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL, 3);
+#endif
+
+#if defined(CONFIG_BCM7435)
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 3);
+#endif
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 4);
+
+#if defined(BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5)
+	PLL_CH_ENA(CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL, 5);
+#endif
+}
+
+static void bcm7425_pm_late_suspend(int is_s3)
+{
+	/*
+	 * 7425 will not go to S2/S3 standby unless both memory controllers
+	 * are in SSPD mode. MEMC0 is handled by AON/BSP, but MEMC1 must
+	 * be put to SSPD by the software.
+	 * So, if MEMC1 was previously powered down, power it up and then
+	 * suspend
+	 */
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_OFF) {
+		brcm_pm_memc1_powerup();
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+	}
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_ON) {
+		brcm_pm_memc1_suspend(is_s3);
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_SSPD;
+	}
+}
+
+static void bcm7425_pm_early_resume(int is_s3)
+{
+	if (brcm_pm_memc1_power == BRCM_PM_MEMC1_SSPD) {
+		brcm_pm_memc1_resume(is_s3);
+		brcm_pm_memc1_power = BRCM_PM_MEMC1_ON;
+	}
+}
+
+static void bcm7425_pm_pcie_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	BDEV_WR_F(PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
+	PLL_CH_DIS(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 0);
+#if defined(BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1)
+	PLL_CH_DIS(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 1);
+#endif
+	PLL_DIS(CLKGEN_PLL_HIF_PLL);
+}
+
+static void bcm7425_pm_pcie_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	PLL_ENA(CLKGEN_PLL_HIF_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 0);
+#if defined(BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1)
+	PLL_CH_ENA(CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL, 1);
+#endif
+	/* take the bridge out of reset to be able to write serdes */
+	BDEV_WR_F_RB(HIF_RGR1_SW_INIT_1, PCIE_BRIDGE_SW_INIT, 0);
+	BDEV_WR_F(PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+	/* delay to allow SERDES to be stable */
+	udelay(100);
+
+#if defined(CONFIG_BRCM_HAS_PCIE) && defined(CONFIG_PCI)
+	BDEV_WR_F_RB(WKTMR_EVENT, wktmr_alarm_event, 1);
+	BDEV_WR_F_RB(WKTMR_PRESCALER, wktmr_prescaler, WKTMR_FREQ);
+
+	if (brcm_pcie_enabled) {
+		brcm_early_pcie_setup();
+		brcm_setup_pcie_bridge();
+	}
+#endif
+}
+
+static struct clk clk_pcie = {
+	.name		= "pcie",
+	.disable	= &bcm7425_pm_pcie_disable,
+	.enable		= &bcm7425_pm_pcie_enable,
+	.refcnt		= 1, /* enabled on boot */
+};
+
+static void bcm7425_initialize(void)
+{
+	brcm_ddr_phy_initialize();
+	__clk_dyn_add(&clk_pcie);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7425),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	DEF_SYSTEM_PM_OP(7425),
+	DEF_SYSTEM_LATE_PM_OP(7425),
+	.moca.set_cpu_rate	= bcm40nm_pm_set_moca_cpu_rate,
+	.moca.set_phy_rate	= bcm40nm_pm_set_moca_phy_rate,
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7425_initialize,
+};
+#endif
+
+#if defined(CONFIG_BCM7429)
+
+static void bcm7429_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	/* need to control network PLLs for 7429 */
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 1);
+}
+
+static void bcm7429_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET0,
+		DISABLE_GENET0_ALWAYSON_CLOCK, 0);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_GENET1,
+		DISABLE_GENET1_ALWAYSON_CLOCK, 0);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0,
+		GENET0_108_CLOCK_ENABLE_GENET0, 1);
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1,
+		GENET1_108_CLOCK_ENABLE_GENET1, 1);
+
+	BDEV_WR_F_RB(CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+
+	/* need to control network PLLs for 7429 */
+}
+static void bcm7429_initialize(void)
+{
+	brcm_ddr_phy_initialize();
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 40nm),
+	DEF_BLOCK_PM_OP(sata, 40nm),
+	DEF_BLOCK_PM_OP(network, 7429),
+	DEF_BLOCK_PM_OP(moca, 40nm),
+	DEF_BLOCK_PM_OP(genet, 40nm),
+	DEF_BLOCK_PM_OP(genet1, 40nm),
+	.moca.set_cpu_rate	= bcm40nm_pm_set_moca_cpu_rate,
+	.moca.set_phy_rate	= bcm40nm_pm_set_moca_phy_rate,
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= bcm7429_initialize,
+};
+#endif
+
+#if	defined(CONFIG_BCM7228) || \
+	defined(CONFIG_BCM7552) || \
+	defined(CONFIG_BCM7358) || \
+	defined(CONFIG_BCM7360) || \
+	defined(CONFIG_BCM7362)
+static void bcm7552_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 1);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_DISABLE, DISABLE_USB_54_MDIO_CLOCK, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7552_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_DISABLE, DISABLE_USB_54_MDIO_CLOCK, 0);
+
+	/* power up memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up PHY and PLL */
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_IDDQ_PWRDN, 0);
+	BDEV_WR_F_RB(USB_CTRL_PLL_CTL, PLL_PWRDWNB, 1);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7552_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		/*
+		 * NOTE: disabling L2INTR clock breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			0x1C7);
+		PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		return;
+	}
+
+	/* Stop GENET clocks */
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+
+	/* Power down PLL channels */
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+}
+
+static void bcm7552_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1C7);
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		return;
+	}
+
+	/* Power up PLL channels */
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+
+	/* Restart GENET clocks */
+	BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+}
+
+static void bcm7552_pm_suspend(u32 flags)
+{
+	/* VCXO channel 0, 1, 2 and PLL 0 */
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+	PLL_DIS(CLKGEN_PLL_VCXO_PLL);
+	/* SYS PLL 1 */
+	if (!ENET_WOL(flags))
+		PLL_DIS(CLKGEN_PLL_SYS1_PLL);
+
+	/* SYS PLL 0 channels 2, 4, 5 */
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_DIS(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+}
+
+static void bcm7552_pm_resume(u32 flags)
+{
+	/* SYS PLL 0 channels 2, 4, 5 */
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 2);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 4);
+	PLL_CH_ENA(CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL, 5);
+	/* SYS PLL 1 */
+	if (!ENET_WOL(flags))
+		PLL_ENA(CLKGEN_PLL_SYS1_PLL);
+
+	/* VCX0 channel 0, 1, 2 and PLL 0 */
+	PLL_ENA(CLKGEN_PLL_VCXO_PLL);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL, 2);
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7552),
+	DEF_BLOCK_PM_OP(genet, 7552),
+	DEF_SYSTEM_PM_OP(7552),
+	.clk_get		= brcm_pm_clk_get,
+	.initialize		= brcm_ddr_phy_initialize,
+};
+#endif
+
+#if	defined(CONFIG_BCM7584)
+
+static void bcm7584_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7584_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power down memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7584_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET0_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x83);
+	} else {
+		/* disable genet0 clocks */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf);
+
+		/* Every genet0 clock */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0xFF);
+	}
+
+}
+static void bcm7584_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x83);
+
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET0_GMII_CLOCK_SELECT, 0);
+
+	} else {
+		/* enable genet0 clocks */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf);
+
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0xFF);
+	}
+
+}
+
+static void bcm7584_pm_genet1_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	if (ENET_WOL(flags)) {
+		/* switch to slow clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 1);
+
+		/*
+		 * Do not clear GENET1_L2INTR_CLOCK_ENABLE - it screws up
+		 * receiver after resume !!!
+		 */
+		/* 250, EEE, UNIMAC-TX */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x4300);
+	} else {
+		/* Disable all genet1 clocks */
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x7F00);
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf0);
+	}
+}
+
+static void bcm7584_pm_genet1_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x4300);
+
+		/* switch to fast clock */
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(
+		    CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT,
+		    GENET1_GMII_CLOCK_SELECT, 0);
+
+	} else {
+		/* enable genet1 clocks */
+		BDEV_SET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		    0x7F00);
+		BDEV_UNSET(
+		    BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE,
+		    0xf0);
+	}
+}
+static void bcm7584_pm_network_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	/* SCB, 108 clocks */
+	BDEV_UNSET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		0x18000);
+
+	SRAM_OFF_3(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+}
+
+static void bcm7584_pm_network_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ANY_WOL(flags))
+		return;
+
+	SRAM_ON_3(DUAL_GENET_TOP_DUAL_RGMII, GENET0, _A);
+
+	/* SCB, 108 clocks */
+	BDEV_SET(BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE,
+		0x18000);
+}
+
+static void bcm7584_pm_sata_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	SRAM_OFF_2(SATA3_TOP, SATA3);
+
+	/* gate the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_DISABLE,
+		DISABLE_SATA_LV_CLK_30, 1);
+}
+
+static void bcm7584_pm_sata_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	/* reenable the clocks */
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_DISABLE,
+		DISABLE_SATA_LV_CLK_30, 0);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_108_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_SATA3_TOP_CLOCK_ENABLE,
+		SATA3_SCB_CLOCK_ENABLE, 1);
+
+	SRAM_ON_2(SATA3_TOP, SATA3);
+
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7584),
+	DEF_BLOCK_PM_OP(genet, 7584),
+	DEF_BLOCK_PM_OP(genet1, 7584),
+	DEF_BLOCK_PM_OP(network, 7584),
+	DEF_BLOCK_PM_OP(sata, 7584),
+	.clk_get		= brcm_pm_clk_get,
+};
+#endif
+
+#if	defined(CONFIG_BCM7563)
+
+static void bcm7563_pm_usb_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+	bcm40nm_pm_usb_disable_s3();
+
+	/* power down USB PHY */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+	/* power down USB PLL */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power down memory */
+	SRAM_OFF_2(USB, USB0);
+
+	/* disable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 0);
+}
+
+static void bcm7563_pm_usb_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	/* enable the clocks */
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_USB_CLOCK_ENABLE, USB0_108_CLOCK_ENABLE, 1);
+
+	/* power down memory */
+	SRAM_ON_2(USB, USB0);
+
+	/* power up USB PLL */
+	BDEV_SET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK);
+
+	/* power up USB PHY */
+	BDEV_UNSET(BCHP_USB_CTRL_PLL_CTL,
+		BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK);
+
+	bcm40nm_pm_usb_enable_s3();
+}
+
+static void bcm7563_pm_genet_disable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 1);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		/*
+		 * NOTE: disabling L2INTR clock breaks ACPI pattern detection
+		 */
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+			0x1C7);
+		PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		return;
+	}
+
+	/* Stop GENET clocks */
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 0);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 0);
+	BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+
+	/* Power down PLL channels */
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_DIS(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+}
+static void bcm7563_pm_genet_enable(u32 flags)
+{
+	PRINT_PM_CALLBACK;
+
+	if (ENET_WOL(flags)) {
+		PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+		BDEV_SET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, 0x1C7);
+		BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xB);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_GMII_CLOCK_SELECT, 0);
+		BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT,
+			GENET0_CLOCK_SELECT, 0);
+		return;
+	}
+
+	/* Power up PLL channels */
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 0);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 1);
+	PLL_CH_ENA(CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL, 2);
+
+	/* Restart GENET clocks */
+	BDEV_UNSET(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, 0xF);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_SCB_CLOCK_ENABLE, 1);
+	BDEV_WR_F_RB(CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE,
+		GENET_108_CLOCK_ENABLE, 1);
+}
+
+static void bcm7563_pm_suspend(u32 flags)
+{
+	/* disable self-refresh since it interferes with suspend */
+	brcm_pm_set_ddr_timeout(0);
+}
+
+static void bcm7563_pm_resume(u32 flags)
+{
+}
+
+#define PM_OPS_DEFINED
+static struct brcm_chip_pm_ops chip_pm_ops = {
+	DEF_BLOCK_PM_OP(usb, 7563),
+	DEF_BLOCK_PM_OP(genet, 7563),
+	DEF_SYSTEM_PM_OP(7563),
+	.clk_get		= brcm_pm_clk_get,
+};
+#endif
+
+#ifndef PM_OPS_DEFINED
+/* default structure - no pm callbacks available */
+static struct brcm_chip_pm_ops chip_pm_ops;
+#endif
+
+static __maybe_unused void brcm_ddr_phy_initialize(void)
+{
+#ifdef BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL
+	/* MEMC0 */
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_0_POWERDOWN,
+		PLLCLKS_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+#endif
+#ifdef BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL
+	/* MEMC1 */
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		DEVCLK_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		HIZ_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
+		PLLCLKS_OFF_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
+		IDDQ_MODE_ON_SELFREF, 1);
+#endif
+	/* restore self-refresh mode */
+	brcm_pm_set_ddr_timeout(brcm_pm_ddr_timeout);
+}
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+	if (chip_pm_ops.clk_get && id) {
+		struct clk *c = chip_pm_ops.clk_get(dev, id);
+		if (c)
+			return c;
+	}
+
+	return brcm_pm_clk_find(id) ? : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+static void brcm_pm_sata_disable(u32 flags)
+{
+	if (chip_pm_ops.sata.disable)
+		chip_pm_ops.sata.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_sata_enable(u32 flags)
+{
+	if (chip_pm_ops.sata.enable)
+		chip_pm_ops.sata.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet1_disable(u32 flags)
+{
+	if (chip_pm_ops.genet1.disable)
+		chip_pm_ops.genet1.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet1_enable(u32 flags)
+{
+	if (chip_pm_ops.genet1.enable)
+		chip_pm_ops.genet1.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_network_disable(u32 flags)
+{
+	if (chip_pm_ops.network.disable)
+		chip_pm_ops.network.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_network_enable(u32 flags)
+{
+	if (chip_pm_ops.network.enable)
+		chip_pm_ops.network.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_disable(u32 flags)
+{
+	if (chip_pm_ops.genet.disable)
+		chip_pm_ops.genet.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_enable(u32 flags)
+{
+	if (chip_pm_ops.genet.enable)
+		chip_pm_ops.genet.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_genet_disable_wol(u32 flags)
+{
+	brcm_pm_flags &= ~BRCM_PM_FLAG_ENET_WOL;
+}
+
+static void brcm_pm_genet_enable_wol(u32 flags)
+{
+	brcm_pm_flags |= BRCM_PM_FLAG_ENET_WOL;
+}
+
+static void brcm_pm_moca_disable(u32 flags)
+{
+	if (chip_pm_ops.moca.disable)
+		chip_pm_ops.moca.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_moca_enable(u32 flags)
+{
+	if (chip_pm_ops.moca.enable)
+		chip_pm_ops.moca.enable(brcm_pm_flags | flags);
+}
+
+static int brcm_pm_moca_cpu_set_rate(unsigned long rate)
+{
+	if (chip_pm_ops.moca.set_cpu_rate)
+		return chip_pm_ops.moca.set_cpu_rate(rate);
+
+	return -ENOENT;
+}
+
+static int brcm_pm_moca_phy_set_rate(unsigned long rate)
+{
+	if (chip_pm_ops.moca.set_phy_rate)
+		return chip_pm_ops.moca.set_phy_rate(rate);
+
+	return -ENOENT;
+}
+
+static void brcm_pm_moca_disable_wol(u32 flags)
+{
+	brcm_pm_flags &= ~BRCM_PM_FLAG_MOCA_WOL;
+}
+
+static void brcm_pm_moca_enable_wol(u32 flags)
+{
+	brcm_pm_flags |= BRCM_PM_FLAG_MOCA_WOL;
+}
+
+static void brcm_pm_usb_disable(u32 flags)
+{
+	if (chip_pm_ops.usb.disable)
+		chip_pm_ops.usb.disable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_usb_enable(u32 flags)
+{
+	if (chip_pm_ops.usb.enable)
+		chip_pm_ops.usb.enable(brcm_pm_flags | flags);
+}
+
+static void brcm_pm_initialize(void)
+{
+	if (chip_pm_ops.initialize)
+		chip_pm_ops.initialize();
+}
+
+static void brcm_pm_set_ddr_timeout(int val)
+{
+#if defined(BCHP_MEMC_DDR_0_SRPD_CONFIG) && defined(CONFIG_MIPS)
+	if (val) {
+#if defined(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL)
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			HIZ_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL,
+			DEVCLK_OFF_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_AC_0_POWERDOWN,
+			PLLCLKS_OFF_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+		BDEV_WR_F(MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL,
+			IDDQ_MODE_ON_SELFREF, 1);
+#endif
+		BDEV_WR_F_RB(MEMC_DDR_0_SRPD_CONFIG, INACT_COUNT, 0xdff);
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, SRPD_EN, 1);
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, INACT_COUNT, 0xffff);
+		do {
+			DEV_RD(KSEG1);
+		} while (BDEV_RD_F(MEMC_DDR_0_POWER_DOWN_STATUS, SRPD));
+		BDEV_WR_F(MEMC_DDR_0_SRPD_CONFIG, SRPD_EN, 0);
+		local_irq_restore(flags);
+	}
+#endif
+}
+
+/***********************************************************************
+ * Passive standby - per-chip
+ ***********************************************************************/
+static void brcm_system_standby(void)
+{
+	if (chip_pm_ops.suspend)
+		chip_pm_ops.suspend(brcm_pm_flags);
+}
+
+static void brcm_system_resume(void)
+{
+	if (chip_pm_ops.resume)
+		chip_pm_ops.resume(brcm_pm_flags);
+}
+
+static void brcm_system_late_standby(int is_s3)
+{
+	if (chip_pm_ops.late_suspend)
+		chip_pm_ops.late_suspend(is_s3);
+}
+
+static void brcm_system_early_resume(int is_s3)
+{
+	if (chip_pm_ops.early_resume)
+		chip_pm_ops.early_resume(is_s3);
+}
+
+/***********************************************************************
+ * Passive standby - common functions
+ ***********************************************************************/
+
+static suspend_state_t suspend_state;
+
+static void brcm_pm_handshake(void)
+{
+#if defined(CONFIG_BRCM_PWR_HANDSHAKE_V0)
+	int i;
+	unsigned long base = BCHP_BSP_CMDBUF_REG_START & ~0xffff;
+	unsigned long cmdbuf = BCHP_BSP_CMDBUF_REG_START;
+	u32 tmp;
+
+	i = 0;
+	while (!(BDEV_RD(base + 0xb008) & 0x02)) {
+		if (i++ == 10) {
+			printk(KERN_WARNING "%s: CMD_IDRY2 timeout\n",
+				__func__);
+			break;
+		}
+		msleep(20);
+	}
+	BDEV_WR_RB(cmdbuf + 0x180, 0x00000010);
+	BDEV_WR_RB(cmdbuf + 0x184, 0x00000098);
+	BDEV_WR_RB(cmdbuf + 0x188, 0xabcdef00);
+	BDEV_WR_RB(cmdbuf + 0x18c, 0xb055aa4f);
+	BDEV_WR_RB(cmdbuf + 0x190, 0x789a0004);
+	BDEV_WR_RB(cmdbuf + 0x194, 0x00000000);
+
+	BDEV_WR_RB(base + 0xb028, 1);
+
+	i = 0;
+	while (!(BDEV_RD(base + 0xb020) & 0x01)) {
+		if (i++ == 10) {
+			printk(KERN_WARNING "%s: CMD_OLOAD2 timeout\n",
+				__func__);
+			break;
+		}
+		mdelay(10);
+	}
+
+	BDEV_WR_RB(base + 0xb010, 0);
+	BDEV_WR_RB(base + 0xb020, 0);
+	tmp = BDEV_RD(cmdbuf + 0x494);
+	if (tmp != 0 && tmp != 1) {
+		printk(KERN_WARNING "%s: command failed: %08lx\n",
+			__func__, (unsigned long)tmp);
+		mdelay(10);
+		return;
+	}
+	BDEV_UNSET_RB(base + 0xb038, 0xff00);
+	printk(KERN_DEBUG "BSP power handshake complete OK: %x\n", tmp);
+#elif defined(CONFIG_BRCM_PWR_HANDSHAKE_V1)
+	BDEV_WR_F_RB(AON_CTRL_HOST_MISC_CMDS, pm_restore, 0);
+	BDEV_WR_F_RB(AON_CTRL_PM_INITIATE, pm_initiate_0, 0);
+	BDEV_WR_F_RB(AON_CTRL_PM_INITIATE, pm_initiate_0, 1);
+	mdelay(10);
+#endif /* CONFIG_BRCM_PWR_HANDSHAKE_V0 */
+}
+
+static int brcm_pm_prepare(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	return 0;
+}
+
+static void brcm_pm_set_pll_on(void)
+{
+	int mips_pll_on = !!(brcm_pm_standby_flags & BRCM_STANDBY_MIPS_PLL_ON);
+	int ddr_pll_on = !!(brcm_pm_standby_flags & BRCM_STANDBY_DDR_PLL_ON);
+
+#if defined(BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK)
+	BDEV_WR_F_RB(CLK_PM_PLL_ALIVE_SEL, MIPS_PLL, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, MIPS_PLL, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_MIPS, mips_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_AVD_MIPS, mips_pll_on);
+#endif
+
+#if defined(BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_MASK)
+	BDEV_WR_F_RB(CLK_PM_PLL_ALIVE_SEL, DDR_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, DDR_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR0, ddr_pll_on);
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR1, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, PLL_DDR, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys_PLL, ddr_pll_on);
+#elif defined(BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK)
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys0_PLL, ddr_pll_on);
+	BDEV_WR_F_RB(CLKGEN_PM_PLL_ALIVE_SEL, memsys1_PLL, ddr_pll_on);
+#endif
+}
+
+void brcm_pm_wakeup_source_enable(u32 mask, int enable)
+{
+#ifdef BCHP_PM_L2_CPU_MASK_SET
+	if (enable) {
+		BDEV_WR_RB(BCHP_PM_L2_CPU_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_CPU_MASK_CLEAR, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_MASK_CLEAR, mask);
+	} else {
+		BDEV_WR_RB(BCHP_PM_L2_CPU_MASK_SET, mask);
+		BDEV_WR_RB(BCHP_PM_L2_PCI_MASK_SET, mask);
+	}
+#else
+	if (enable) {
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_MASK_CLEAR, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_MASK_CLEAR, mask);
+	} else {
+		BDEV_WR_RB(BCHP_AON_PM_L2_CPU_MASK_SET, mask);
+		BDEV_WR_RB(BCHP_AON_PM_L2_PCI_MASK_SET, mask);
+	}
+#endif
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_source_enable);
+
+int brcm_pm_wakeup_get_status(u32 mask)
+{
+#ifdef BCHP_PM_L2_CPU_STATUS
+	return !!(BDEV_RD(BCHP_PM_L2_CPU_STATUS) & mask);
+#else
+	return !!(BDEV_RD(BCHP_AON_PM_L2_CPU_STATUS) &
+		   ~BDEV_RD(BCHP_AON_PM_L2_CPU_MASK_STATUS)
+		   & mask);
+#endif
+}
+EXPORT_SYMBOL(brcm_pm_wakeup_get_status);
+
+static u32 brcm_pm_wakeup_get_mask(void)
+{
+#ifdef BCHP_PM_L2_CPU_STATUS
+	return BDEV_RD(BCHP_PM_L2_CPU_MASK_STATUS);
+#else
+	return BDEV_RD(BCHP_AON_PM_L2_CPU_MASK_STATUS);
+#endif
+}
+
+static int brcm_pm_timer_wakeup_enable(void *ref)
+{
+#if !WATCHDOG_TIMER_WAKEUP_ALWAYS
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+#endif
+		brcm_pm_wakeup_source_enable(TIMER_INTR_MASK, 1);
+	return 0;
+}
+
+static int brcm_pm_timer_wakeup_disable(void *ref)
+{
+	brcm_pm_wakeup_source_enable(TIMER_INTR_MASK, 0);
+	return 0;
+}
+
+static int brcm_pm_timer_wakeup_poll(void *ref)
+{
+	int retval = brcm_pm_wakeup_get_status(TIMER_INTR_MASK);
+	printk(KERN_DEBUG "%s:  %d\n", __func__, retval);
+	return retval;
+}
+
+static struct brcm_wakeup_ops brcm_timer_wakeup_ops = {
+	.enable = brcm_pm_timer_wakeup_enable,
+	.disable = brcm_pm_timer_wakeup_disable,
+	.poll = brcm_pm_timer_wakeup_poll,
+};
+
+static void brcm_pm_set_alarm(int timeout)
+{
+	u32 tmp;
+	BDEV_WR_RB(BCHP_WKTMR_EVENT, 1);
+	if (timeout == 1) {
+		/* Wait for next second to start - if too little time left
+		 * before the counter increment we may receive WKTMR interrupt
+		 * before system is fully suspended.
+		 * One second should be enough to complete suspend
+		 * from this point
+		 */
+		tmp = BDEV_RD(BCHP_WKTMR_COUNTER);
+		while (BDEV_RD(BCHP_WKTMR_COUNTER) == tmp)
+			;
+	}
+	BDEV_WR_RB(BCHP_WKTMR_ALARM, BDEV_RD(BCHP_WKTMR_COUNTER) + timeout);
+}
+
+static void brcm_pm_clear_alarm(void)
+{
+	BDEV_WR_RB(BCHP_WKTMR_EVENT, 1);
+}
+
+#if defined(CONFIG_BCM7468) || defined(CONFIG_BCM7550)
+#define NON_RELOCATABLE_VEC
+#endif
+static int brcm_pm_standby(int is_s3)
+{
+	int ret = 0, valid_event = 1;
+	u32 l2_mask;
+	unsigned long restart_vec = BMIPS_WARM_RESTART_VEC;
+	unsigned long restart_vec_size = bmips_smp_int_vec_end -
+		bmips_smp_int_vec;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+		printk(KERN_INFO "%s: timeout %ld\n",
+			__func__, brcm_pm_standby_timeout);
+
+	do {
+
+		brcm_irq_standby_enter(BRCM_IRQ_STANDBY);
+
+#if defined(NON_RELOCATABLE_VEC)
+	{
+	u32 oldvec[5];
+	const int vecsize = 0x14;
+	void *vec = (void *)ebase + 0x200;
+
+	restart_vec = (unsigned long)vec;
+
+	memcpy(oldvec, vec, vecsize);
+	memcpy(vec, bmips_smp_int_vec, vecsize);
+	flush_icache_range(restart_vec, restart_vec + vecsize);
+#else
+	/* send all IRQs to BMIPS_WARM_RESTART_VEC */
+	clear_c0_cause(CAUSEF_IV);
+	irq_disable_hazard();
+	set_c0_status(ST0_BEV);
+	irq_disable_hazard();
+#endif
+
+	brcm_system_standby();
+	/*
+	 * Save current wakeup mask -
+	 * it may have been changed by usermode or drivers without
+	 * brcm_pm_wakeup API
+	 */
+	l2_mask = brcm_pm_wakeup_get_mask();
+	brcm_pm_wakeup_enable();
+
+#ifdef DEBUG_M2M_DMA
+	if (brcm_pm_standby_flags & 0x40) {
+		unsigned char *tb = kzalloc(PAGE_SIZE*16, GFP_ATOMIC);
+		int result, ii;
+		/* Test 1: simple copy */
+		if (1) {
+			struct brcm_mem_transfer xfer = {
+			.src		= tb,
+			.dst		= tb+PAGE_SIZE,
+			.pa_src		= 0,
+			.pa_dst		= 0,
+			.len		= PAGE_SIZE,
+			.mode		= BRCM_MEM_DMA_SCRAM_NONE,
+			.key		= 0,
+			.next		= NULL
+		};
+		memset(tb, 0xa3, PAGE_SIZE);
+		memset(tb+PAGE_SIZE, 0, PAGE_SIZE);
+
+		brcm_mem_dma_simple_transfer(&xfer);
+		result = memcmp(tb, tb+PAGE_SIZE, PAGE_SIZE);
+		DBG("MEM DMA TEST 1: result %d\n", result);
+		}
+		/* Test 2: encryption/decryption */
+		if (1) {
+			struct brcm_mem_transfer xfer[] = {
+			[0] = {
+				.src		= tb,
+				.dst		= tb+PAGE_SIZE*2,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 5,
+				.next		= &xfer[1],
+			},
+			[1] = {
+				.src		= tb+PAGE_SIZE,
+				.dst		= tb+PAGE_SIZE*3,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 5,
+				.next		= NULL,
+			},
+			[2] = {
+				.src		= tb+PAGE_SIZE*2,
+				.dst		= tb+PAGE_SIZE*4,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 6,
+				.next		= &xfer[3],
+			},
+			[3] = {
+				.src		= tb+PAGE_SIZE*3,
+				.dst		= tb+PAGE_SIZE*5,
+				.pa_src		= 0,
+				.pa_dst		= 0,
+				.len		= PAGE_SIZE,
+				.mode		= BRCM_MEM_DMA_SCRAM_BLOCK,
+				.key		= 6,
+				.next		= NULL,
+			},
+		};
+		memset(tb, 0xa3, PAGE_SIZE*2);
+		memset(tb+PAGE_SIZE*2, 0x45, PAGE_SIZE*4);
+
+		DBG("MEM DMA TEST 2:\ninput\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		brcm_mem_dma_transfer(&xfer[0]);
+		DBG("encrypted\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+PAGE_SIZE*2+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		brcm_mem_dma_transfer(&xfer[2]);
+		DBG("decrypted\n");
+		for (ii = 0; ii < PAGE_SIZE; ii++) {
+			DBG("%02x ", *(tb+PAGE_SIZE*4+ii));
+			if (ii%32 == 31) {
+				DBG("\n"); break;
+			}
+		}
+		result = memcmp(tb, tb+(PAGE_SIZE*4), PAGE_SIZE*2);
+		DBG("result %02x\n", (unsigned char)result);
+		}
+		kfree(tb);
+	} else
+#endif
+	if (brcm_pm_standby_flags & BRCM_STANDBY_NO_SLEEP) {
+		if (brcm_pm_standby_flags & BRCM_STANDBY_DELAY)
+			mdelay(120000);
+		else
+			mdelay(5000);
+	} else {
+		if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+			brcm_pm_set_alarm(brcm_pm_standby_timeout ? : 1);
+#if WATCHDOG_TIMER_WAKEUP_ALWAYS
+		else
+			brcm_pm_set_alarm(20);
+#endif
+		brcm_pm_set_pll_on();
+		brcm_pm_handshake();
+		brcm_system_late_standby(is_s3);
+
+		if (is_s3)
+			ret = brcm_pm_s3_standby(
+				current_cpu_data.dcache.linesz,
+				brcm_pm_standby_flags);
+		else
+			ret = brcm_pm_standby_asm(
+				current_cpu_data.icache.linesz,
+				restart_vec, restart_vec_size,
+				brcm_pm_standby_flags);
+		brcm_system_early_resume(is_s3);
+		brcm_pm_clear_alarm();
+		valid_event = brcm_pm_wakeup_poll(l2_mask);
+	}
+	brcm_pm_wakeup_disable();
+	brcm_system_resume();
+
+#if defined(NON_RELOCATABLE_VEC)
+	memcpy(vec, oldvec, vecsize);
+	flush_icache_range(restart_vec, restart_vec + vecsize);
+	}
+#else
+	/* send IRQs back to the normal runtime vectors */
+	clear_c0_status(ST0_BEV);
+	irq_disable_hazard();
+	set_c0_cause(CAUSEF_IV);
+	irq_disable_hazard();
+#endif
+	brcm_irq_standby_exit();
+	} while (!ret && !valid_event);
+
+	if (ret && !is_s3)
+		printk(KERN_WARNING "%s: standby failed with code %d\n",
+			__func__, ret);
+
+	brcm_pm_time_at_wakeup[0] = BDEV_RD(AON_RAM(0));
+	brcm_pm_time_at_wakeup[1] = BDEV_RD(AON_RAM(1));
+	return 0;
+}
+
+#if defined(BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK) || \
+defined(BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK)
+#define PM_CMD_BASE		0x1A
+#else
+#define PM_CMD_BASE		0x12
+#endif
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define PM_USE_MIPS_READY	0x04
+#else
+#define PM_USE_MIPS_READY	0x00
+#endif
+
+#define PM_STANDBY_CONFIG	(PM_CMD_BASE|PM_USE_MIPS_READY)
+#define PM_STANDBY_COMMAND	(PM_STANDBY_CONFIG|1)
+
+void brcm_pm_s3_cold_boot(void)
+{
+	if (!brcm_pm_halt_mode)
+		/* regular halt, go back */
+		return;
+
+	brcm_irq_standby_enter(BRCM_IRQ_STANDBY);
+	brcm_pm_wakeup_enable();
+	if (brcm_pm_standby_flags & BRCM_STANDBY_TEST)
+		brcm_pm_set_alarm(brcm_pm_standby_timeout ? : 3);
+	brcm_pm_handshake();
+	BDEV_WR_RB(AON_RAM(0), 0);
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT, 0xffff);
+
+	/* PD request is initiated on pm_start_pwrdn transition 0->1 */
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, 0);
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, PM_STANDBY_CONFIG);
+	/* Separate PD request from the rest of PMSM setup */
+	BDEV_WR_RB(BCHP_AON_CTRL_PM_CTRL, PM_STANDBY_COMMAND);
+
+	__asm__ __volatile__(
+	"	wait\n"
+	: : : "memory");
+}
+
+static int brcm_pm_enter(suspend_state_t unused)
+{
+	int ret = 0;
+
+	DBG("%s:%d\n", __func__, __LINE__);
+	switch (suspend_state) {
+	case PM_SUSPEND_STANDBY:
+		ret = brcm_pm_standby(0);
+		break;
+	case PM_SUSPEND_MEM:
+		ret = brcm_pm_standby(1);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void brcm_pm_finish(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	BDEV_WR_RB(AON_RAM(0), 0);
+}
+
+static int brcm_pm_begin(suspend_state_t state)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_state = state;
+	if (state == PM_SUSPEND_MEM)
+		brcm_pm_flags |= BRCM_PM_FLAG_S3;
+	else
+		brcm_pm_flags &= ~BRCM_PM_FLAG_S3;
+	return 0;
+}
+
+static void brcm_pm_end(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_state = PM_SUSPEND_ON;
+	return;
+}
+
+static int brcm_pm_valid(suspend_state_t state)
+{
+	return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
+}
+
+static const struct platform_suspend_ops brcm_pm_ops = {
+	.begin		= brcm_pm_begin,
+	.end		= brcm_pm_end,
+	.prepare	= brcm_pm_prepare,
+	.enter		= brcm_pm_enter,
+	.finish		= brcm_pm_finish,
+	.valid		= brcm_pm_valid,
+};
+
+static int brcm_suspend_init(void)
+{
+	DBG("%s:%d\n", __func__, __LINE__);
+	suspend_set_ops(&brcm_pm_ops);
+	brcm_pm_wakeup_register(&brcm_timer_wakeup_ops, NULL, "WKTMR");
+	return 0;
+}
+late_initcall(brcm_suspend_init);
+
+int brcm_pm_deep_sleep(void)
+{
+	return suspend_state == PM_SUSPEND_MEM;
+}
+EXPORT_SYMBOL(brcm_pm_deep_sleep);
+
+void brcm_pm_sata3(int enable)
+{
+	struct clk *clk = brcm_pm_clk_find("sata");
+	if (clk)
+		enable ? clk_enable(clk) : clk_disable(clk);
+}
+
+void brcm_pm_save_restore_rts(unsigned long reg_addr, u32 *data, int restore)
+{
+	int ii = 0;
+
+	reg_addr += 4;		/* skip debug register */
+	if (restore)
+		for (ii = 0; ii < NUM_MEMC_CLIENTS; ii++) {
+			BDEV_WR_RB(reg_addr, data[ii]);
+			reg_addr += 4;
+		}
+	else
+		/* Save MEMC1 configuration */
+		for (ii = 0; ii < NUM_MEMC_CLIENTS; ii++) {
+			data[ii] = BDEV_RD(reg_addr);
+			reg_addr += 4;
+		}
+}
diff --git a/drivers/brcmstb/s3.c b/drivers/brcmstb/s3.c
new file mode 100644
index 000000000000..2b31422bf86f
--- /dev/null
+++ b/drivers/brcmstb/s3.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#include <asm/mipsregs.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <asm/tlbflush.h>
+#include <asm/sections.h>
+#include <asm/cpu-features.h>
+#include <asm/bmips.h>
+
+#define MAX_GP_REGS	16
+#define MAX_CP0_REGS	32
+#define MAX_IO_REGS	(256 - MAX_GP_REGS - MAX_CP0_REGS)
+
+#if 0
+#define DBG		printk
+#else
+#define DBG(...)	do { } while (0)
+#endif
+
+#define CALCULATE_MEM_HASH		(1)
+#define WARM_BOOT_MAGIC_WORD		(0x5AFEB007)
+#define CFE_PARAMETER_BLOCK		(0)
+#define AUTHENTICATION_REGION_SIZE	(16*1024*1024)
+
+#define AON_CTRL_HASH_START_INDEX	(CFE_PARAMETER_BLOCK+5)
+#define AON_SAVE_CPB(idx, val) \
+	BDEV_WR_RB(AON_RAM_BASE + ((CFE_PARAMETER_BLOCK+idx)<<2), val)
+#define AON_READ_CPB(idx) \
+	BDEV_RD(AON_RAM_BASE + ((CFE_PARAMETER_BLOCK+idx)<<2))
+#define AON_SAVE_HASH(idx, val) \
+	BDEV_WR_RB(AON_RAM_BASE + ((AON_CTRL_HASH_START_INDEX+idx)<<2), val)
+#define AON_READ_HASH(idx) \
+	BDEV_RD(AON_RAM_BASE + ((AON_CTRL_HASH_START_INDEX+idx)<<2))
+
+struct cp0_value {
+	u32	value;
+	u32	index;
+	u32	select;
+};
+
+struct	brcm_pm_s3_context {
+	u32			gp_regs[MAX_GP_REGS];
+	struct cp0_value	cp0_regs[MAX_CP0_REGS];
+	int			cp0_regs_idx;
+	u32			memc0_rts[NUM_MEMC_CLIENTS];
+	u32			relo_vector_control_0;
+	u32			relo_vector_control_1;
+	u32			sc_boot_vec;
+};
+
+struct brcm_pm_s3_context s3_context;
+
+asmlinkage int brcm_pm_s3_standby_asm(unsigned long options,
+	void (*dram_encoder_start)(void), int dcache_linesz);
+extern int s3_reentry;
+
+extern void bmips_enable_xks01(void);
+
+static void __raw_uart_putc(char c);
+
+static void brcm_pm_dump_context(struct brcm_pm_s3_context *cxt);
+
+#define CPO_SAVE_INFO(cxt, ci, idx, _select) \
+do { \
+	cxt->cp0_regs[ci].index = idx; \
+	cxt->cp0_regs[ci].select = _select; \
+	cxt->cp0_regs[ci++].value = read_c0_reg(idx, _select); \
+} while (0);
+#define read_c0_reg(n, s)	__read_32bit_c0_register($##n, s)
+#define write_c0_reg(n, s, v)	__write_32bit_c0_register($##n, s, v)
+
+static __maybe_unused void brcm_pm_init_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	cxt->cp0_regs_idx = 0;
+}
+
+static __maybe_unused void brcm_pm_save_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	int ci = cxt->cp0_regs_idx;
+	void __iomem *cbr;
+
+	/* Generic MIPS */
+
+	CPO_SAVE_INFO(cxt, ci, 4, 0); /* context */
+	CPO_SAVE_INFO(cxt, ci, 4, 2); /* userlocal */
+	CPO_SAVE_INFO(cxt, ci, 5, 0); /* pagemask */
+	CPO_SAVE_INFO(cxt, ci, 7, 0); /* hwrena */
+	CPO_SAVE_INFO(cxt, ci, 11, 0); /* compare */
+	CPO_SAVE_INFO(cxt, ci, 12, 0); /* status */
+
+	/* Broadcom specific */
+
+	CPO_SAVE_INFO(cxt, ci, 22, 0); /* config */
+	CPO_SAVE_INFO(cxt, ci, 22, 1); /* mode */
+	CPO_SAVE_INFO(cxt, ci, 22, 3); /* eDSP */
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS4380:
+		cbr = BMIPS_GET_CBR();
+		cxt->relo_vector_control_1 =
+			__raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		/* falls through */
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4350:
+		cbr = BMIPS_GET_CBR();
+		cxt->relo_vector_control_0 =
+			__raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		break;
+	case CPU_BMIPS5000:
+		CPO_SAVE_INFO(cxt, ci, 22, 4); /* bootvec */
+		CPO_SAVE_INFO(cxt, ci, 15, 1); /* ebase */
+		cxt->sc_boot_vec = bmips_read_zscm_reg(0xa0);
+		break;
+	}
+
+	cxt->cp0_regs_idx = ci;
+}
+
+static __maybe_unused void brcm_pm_restore_cp0_context(
+		struct brcm_pm_s3_context *cxt)
+{
+	int ci = cxt->cp0_regs_idx;
+	void __iomem *cbr;
+
+	/* Broadcom specific */
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS4380:
+		cbr = BMIPS_GET_CBR();
+		__raw_writel(cxt->relo_vector_control_1,
+			cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+		/* falls through */
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4350:
+		cbr = BMIPS_GET_CBR();
+		__raw_writel(cxt->relo_vector_control_0,
+			cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+		break;
+	case CPU_BMIPS5000:
+		bmips_write_zscm_reg(0xa0, cxt->sc_boot_vec);
+		write_c0_reg(15, 1, cxt->cp0_regs[--ci].value); /* ebase */
+		write_c0_reg(22, 4, cxt->cp0_regs[--ci].value); /* bootvec */
+		break;
+	}
+
+	write_c0_reg(22, 3, cxt->cp0_regs[--ci].value); /* eDSP */
+	write_c0_reg(22, 1, cxt->cp0_regs[--ci].value); /* mode */
+	write_c0_reg(22, 0, cxt->cp0_regs[--ci].value); /* config */
+
+	/* Generic MIPS */
+
+	write_c0_reg(12, 0, cxt->cp0_regs[--ci].value); /* status */
+	write_c0_reg(11, 0, cxt->cp0_regs[--ci].value); /* compare */
+	write_c0_reg(7, 0, cxt->cp0_regs[--ci].value); /* hwrena */
+	write_c0_reg(5, 0, cxt->cp0_regs[--ci].value); /* pagemask */
+	write_c0_reg(4, 2, cxt->cp0_regs[--ci].value); /* userlocal */
+	write_c0_reg(4, 0, cxt->cp0_regs[--ci].value); /* context */
+}
+
+static __maybe_unused void brcm_pm_cmp_context(
+		struct brcm_pm_s3_context *cxt,
+		struct brcm_pm_s3_context *cxt2, const char* title)
+{
+	int i;
+	int identical = 1;
+	if (title)
+		DBG("%s\n", title);
+	if (cxt->cp0_regs_idx != cxt2->cp0_regs_idx) {
+		identical = 0;
+		DBG("CP0 reg # is different: %d %d\n",
+			cxt->cp0_regs_idx, cxt2->cp0_regs_idx);
+	} else {
+		for (i = 0; i < cxt->cp0_regs_idx; i++) {
+			if (cxt->cp0_regs[i].value
+					!= cxt2->cp0_regs[i].value) {
+				identical = 0;
+				DBG("\tCP0[%02d.%01d]:  %08x != %08x\n",
+					cxt->cp0_regs[i].index,
+					cxt->cp0_regs[i].select,
+					cxt->cp0_regs[i].value,
+					cxt2->cp0_regs[i].value);
+			}
+		}
+	}
+	if (identical)
+		DBG("Contexts are identical\n");
+	else {
+		brcm_pm_dump_context(cxt);
+		brcm_pm_dump_context(cxt2);
+	}
+}
+
+static void brcm_pm_dump_context(struct brcm_pm_s3_context *cxt)
+{
+	int i;
+	DBG("CPO:\n");
+	for (i = 0; i < cxt->cp0_regs_idx; i++) {
+		DBG("[%02d.%0d]=%08x ",
+			cxt->cp0_regs[i].index,
+			cxt->cp0_regs[i].select,
+			cxt->cp0_regs[i].value);
+		if (i%8 == 7)
+			DBG("\n");
+	}
+	DBG("\n\n");
+}
+
+/***********************************************************************
+ * Encryption setup for S3 suspend
+ ***********************************************************************/
+#if CALCULATE_MEM_HASH
+/*
+ * Default scheme encrypts specified memory region and writes encoded data
+ * to a temporary buffer, overwriting previous data on every block write.
+ * Upon encoding final block, last 16 bytes are stored into AON, then
+ * entire temporary buffer is wiped out
+ * Bootloader will repeat encoding immediately after S3 wakeup to see
+ * if hash value matches.
+ * brcm_pm_s3_tmpbuf - temporary buffer
+ * hash_pointer - pointer to location in memory where hash value is located
+ * after encoding
+ */
+static char __section(.s3_enc_tmpbuf) brcm_pm_s3_tmpbuf[PAGE_SIZE*16];
+static u32 *hash_pointer;
+
+#define MEM_ENCRYPTED_START_ADDR	(0x80000000)
+#define MEM_ENCRYPTED_LEN		(1*1024*1024)
+#define	S3_HASH_LEN			16
+
+#define MAX_TRANSFER_SIZE_MB		(16)
+#define MAX_TRANSFER_SIZE		(MAX_TRANSFER_SIZE_MB*1024*1024)
+
+#define AES_CBC_ENCRYPTION_KEY_SLOT	(5)
+#define AES_CBC_DECRYPTION_KEY_SLOT	(6)
+
+/*
+ * brcm_pm_dram_encoder_set_area
+ * Generates a list of descriptors needed to encrypt area
+ * VA _begin.._begin+len-1 into PA outbuf..outbuf+out_len-1
+ * On return out_len is the length of the last transfer, this
+ * can be used as an offset into the outbuf to extract hash
+ */
+static struct brcm_mem_transfer *brcm_pm_dram_encoder_set_area(void *_begin,
+	u32 len, dma_addr_t outbuf, u32 *out_len,
+	struct brcm_mem_transfer *next)
+{
+	int num_descr = (len + *out_len - 1) / *out_len;
+	struct brcm_mem_transfer *xfer, *x, *last_x;
+	void *_end = _begin + len;
+
+	BUG_ON(*out_len > MAX_TRANSFER_SIZE);
+
+	xfer = kzalloc(num_descr * sizeof(struct brcm_mem_transfer),
+		GFP_ATOMIC);
+
+	if (!xfer) {
+		printk(KERN_ERR "%s: out of memory\n", __func__);
+		return NULL;
+	}
+
+	last_x = x = xfer;
+	while (_begin < _end) {
+		dma_addr_t pa_src = virt_to_phys(_begin);
+		if (_begin + *out_len > _end)
+			*out_len = _end - _begin;
+		/* workaround - M2M DMA does not like 0 address */
+		x->len		= *out_len;
+		if (!pa_src) {
+			pa_src += 0x10;
+			x->len -= 0x10;
+		}
+		x->pa_src	= pa_src;
+		x->pa_dst	= outbuf;
+		x->mode		= BRCM_MEM_DMA_SCRAM_BLOCK;
+		x->key		= AES_CBC_ENCRYPTION_KEY_SLOT;
+		x->next		= x + 1;
+		last_x = x;
+		x++;
+		_begin += *out_len;
+	}
+	last_x->next = next;
+
+	return xfer;
+}
+
+static void brcm_pm_dram_encoder_free_area(struct brcm_mem_transfer *xfer)
+{
+	kfree(xfer);
+}
+
+/* Memory region over which M2M DMA calculates MAC cannot be modified
+   after a call to brcm_pm_dram_encoder_start() */
+void brcm_pm_dram_encode(void)
+{
+	u32 *hp = hash_pointer;
+	u32 outbuflen = sizeof(brcm_pm_s3_tmpbuf);
+	uint32_t tmp0, tmp1;
+	/* clear temporary buffer */
+	memset(brcm_pm_s3_tmpbuf, 0, sizeof(brcm_pm_s3_tmpbuf));
+	_dma_cache_wback_inv(0, ~0);
+	/* start M2M encoder */
+	brcm_pm_dram_encoder_start();
+	/* save hash in AON register */
+	AON_SAVE_HASH(0, *hp++);
+	AON_SAVE_HASH(1, *hp++);
+	AON_SAVE_HASH(2, *hp++);
+	AON_SAVE_HASH(3, *hp++);
+
+	/* clear temporary buffer
+	 * cannot use library function because it will use memory (stack) */
+	__asm__ __volatile__(
+	"	.set	noreorder\n"
+	"	la	%0, brcm_pm_s3_tmpbuf\n"
+	"	move	%1, $0\n"
+	"1:	sw	$0, 0(%0)\n"
+	"	addi	%0, 4\n"
+	"	addi	%1, 4\n"
+	"	bne	%2, %1, 1b\n"
+	"	nop\n"
+	: "=&r" (tmp0), "=&r" (tmp1)
+	: "r" (outbuflen));
+}
+#else
+#define brcm_pm_dram_encode	NULL
+#endif
+
+int brcm_pm_s3_standby(int dcache_linesz, unsigned long options)
+{
+	int retval = 0;
+	unsigned long flags;
+#if CALCULATE_MEM_HASH
+	int r1_len, r2_len, total_len;
+	struct brcm_mem_transfer *xfer[3] = {0};
+	u32 outlen = sizeof(brcm_pm_s3_tmpbuf);
+	u32 outbuflen = outlen, tmp, ii;
+	u32 region_size = AUTHENTICATION_REGION_SIZE;
+	void *src;
+	u32 hash[4];
+
+	/*
+	 * We are using bi-directional mapping to avoid synchronizing cache
+	 * after encoding
+	 */
+	dma_addr_t pa_dst = dma_map_single(NULL, brcm_pm_s3_tmpbuf,
+		outbuflen, DMA_BIDIRECTIONAL);
+
+	if (dma_mapping_error(NULL, pa_dst)) {
+		printk(KERN_ERR "%s: cannot remap temp buffer\n", __func__);
+		return -1;
+	}
+
+	if (region_size < brcm_min_auth_region_size)
+		region_size = brcm_min_auth_region_size;
+
+	printk(KERN_DEBUG "Authentication region size: 0x%08x\n", region_size);
+	printk(KERN_DEBUG "Output buffer  : 0x%08x-0x%08x (0x%08x)\n",
+	       (u32)brcm_pm_s3_tmpbuf,
+	       (u32)brcm_pm_s3_tmpbuf + outlen, outlen);
+
+	/* We add areas to the head of the list - in reverse order
+	 * of M2M DMA execution */
+
+	/* This region starts from _text and bypasses temporary
+	 * output buffer */
+	src = _text;
+	/* check if in/out regions overlap */
+	if (brcm_pm_s3_tmpbuf >= (char *)(src + region_size) ||
+	    brcm_pm_s3_tmpbuf + outlen <= (char *)src) {
+		/* non-overlapping case */
+		r1_len = region_size;
+		r2_len = 0;
+	} else {
+		/* need to cut out the output buffer */
+		r1_len = (int)(brcm_pm_s3_tmpbuf - (char *)src);
+		r2_len = region_size - r1_len;
+	}
+	total_len = r1_len + r2_len;
+
+	xfer[0] = brcm_pm_dram_encoder_set_area((void *)src, r1_len,
+		pa_dst, &outlen, NULL);
+	if (!xfer[0]) {
+		printk(KERN_ERR "%s: cannot setup M2M DMA [0]\n", __func__);
+		goto _failed;
+	}
+
+	printk(KERN_DEBUG "Region 0       : 0x%08x-0x%08x (0x%08x)\n",
+		(u32)src, (u32)src + r1_len, r1_len);
+
+	if (r2_len > 0) {
+		outlen = outbuflen;
+		src = (void *)((u32)(brcm_pm_s3_tmpbuf + outbuflen));
+		xfer[1] = xfer[0];
+		xfer[0] = brcm_pm_dram_encoder_set_area(src, r2_len,
+			pa_dst, &outlen, xfer[1]);
+		if (!xfer[0]) {
+			printk(KERN_ERR "%s: cannot setup M2M DMA [1]\n",
+			       __func__);
+			goto _failed;
+		}
+		printk(KERN_DEBUG "Region 1       : 0x%08x-0x%08x (0x%08x)\n",
+			(u32)src, (u32)(src + r2_len), r2_len);
+	}
+
+	/* First descriptor must include kernel reentry point
+	 * We are processing one output buffer worth of data */
+	src = (void *)((u32)(&s3_reentry) & ~(PAGE_SIZE-1));
+	tmp = outbuflen;
+	xfer[2] = brcm_pm_dram_encoder_set_area((void *)src, outbuflen,
+		pa_dst, &tmp, xfer[0]);
+	if (!xfer[2]) {
+		printk(KERN_ERR "%s: cannot setup M2M DMA [2]\n", __func__);
+		goto _failed;
+	}
+	printk(KERN_DEBUG "Region 2       : 0x%08x-0x%08x (0x%08x)\n",
+		(u32)src, (u32)src + outbuflen, outbuflen);
+	total_len += outbuflen;
+	if (brcm_pm_dram_encoder_prepare(xfer[2])) {
+		printk(KERN_ERR "%s: cannot initialize M2M DMA\n", __func__);
+		goto _failed;
+	}
+
+	hash_pointer = (u32 *)(brcm_pm_s3_tmpbuf +
+		(outlen - S3_HASH_LEN + outbuflen) % outbuflen);
+
+	/* M2M DMA descriptor address */
+	if (brcm_pm_hash_enabled)
+		AON_SAVE_CPB(2, BDEV_RD(BCHP_MEM_DMA_0_FIRST_DESC));
+	else
+		AON_SAVE_CPB(2, 0);
+	/* Encryption key slot */
+	AON_SAVE_CPB(3, AES_CBC_ENCRYPTION_KEY_SLOT);
+	/* Address of hash */
+	AON_SAVE_CPB(4, (u32)hash_pointer);
+	/* Total authentication region size */
+	AON_SAVE_CPB(9, total_len);
+	printk(KERN_DEBUG "Encryption slot: %d\n",
+	       AES_CBC_ENCRYPTION_KEY_SLOT);
+	printk(KERN_DEBUG "Hash pointer   : 0x%p\n", hash_pointer);
+	printk(KERN_DEBUG "Total length   : 0x%08x\n", (u32)total_len);
+	printk(KERN_DEBUG "Reentry point  : 0x%p\n", &s3_reentry);
+#else
+	AON_SAVE_CPB(2, 0);
+#endif
+
+	/* Warm Boot Magic Word */
+	AON_SAVE_CPB(0, WARM_BOOT_MAGIC_WORD);
+	/* Kernel Reentry Address */
+	AON_SAVE_CPB(1, (u32)&s3_reentry);
+
+	/* clear RESET_HISTORY */
+	BDEV_WR_F_RB(AON_CTRL_RESET_CTRL, clear_reset_history, 1);
+
+	local_irq_save(flags);
+	/* save CP0 context */
+	brcm_pm_init_cp0_context(&s3_context);
+	brcm_pm_save_cp0_context(&s3_context);
+
+	/* inhibit DDR_RSTb pulse */
+	BDEV_UNSET(BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL, 0x0f);
+	BDEV_SET(BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL, BIT(5) | 0x05);
+
+	/* save RTS */
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_0_REG_START,
+		s3_context.memc0_rts, 0);
+
+	/* save I/O context */
+
+	local_flush_tlb_all();
+	_dma_cache_wback_inv(0, ~0);
+
+	retval = brcm_pm_s3_standby_asm(options, brcm_pm_dram_encode,
+		dcache_linesz);
+
+	/* CPU reconfiguration */
+	local_flush_tlb_all();
+	brcmstb_cpu_setup();
+	cpumask_clear(&bmips_booted_mask);
+
+	/* restore RTS */
+	brcm_pm_save_restore_rts(BCHP_MEMC_ARB_0_REG_START,
+		s3_context.memc0_rts, 1);
+
+	/* restore I/O context */
+	board_pinmux_setup();
+	ebi_restore_settings();
+
+	/* restore CP0 context */
+	brcm_pm_restore_cp0_context(&s3_context);
+
+#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
+	/* 3548 style - separate register */
+	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
+	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
+#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
+	/* 7405 style - shared with L2 */
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+#endif
+		);
+#endif
+
+	local_irq_restore(flags);
+
+
+#if CALCULATE_MEM_HASH
+	for (ii = 0; ii < 4; ii++)
+		hash[ii] = AON_READ_HASH(ii);
+	printk(KERN_DEBUG "hash: %08x:%08x:%08x:%08x\n",
+	       hash[0], hash[1], hash[2], hash[3]);
+
+	brcm_pm_dram_encoder_complete(xfer[0]);
+_failed:
+	for (ii = 0; ii < 3; ii++)
+		brcm_pm_dram_encoder_free_area(xfer[ii]);
+	dma_unmap_single(NULL, pa_dst, outbuflen, DMA_BIDIRECTIONAL);
+
+#endif
+
+	return retval;
+}
+
+static void __maybe_unused __raw_uart_putc(char c)
+{
+	while (!(BDEV_RD(BCHP_UARTA_LSR) & BCHP_UARTA_LSR_THRE_MASK))
+		;
+	BDEV_WR_RB(BCHP_UARTA_THR, (u32)c);
+}
diff --git a/drivers/brcmstb/setup.c b/drivers/brcmstb/setup.c
new file mode 100644
index 000000000000..7261703de194
--- /dev/null
+++ b/drivers/brcmstb/setup.c
@@ -0,0 +1,1129 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/irqflags.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/bmoca.h>
+#include <linux/io.h>
+#include <linux/i2c/i2c-brcmstb.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <linux/version.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/mmc/host.h>
+#include "../drivers/mmc/host/sdhci-brcmstb.h"
+
+#include <linux/brcmstb/brcmstb.h>
+
+#ifndef CONFIG_MTD
+/* squash MTD warning on IKOS builds */
+#define CONFIG_MTD_MAP_BANK_WIDTH_1 1
+#endif
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/map.h>
+
+/* Default SPI flash chip selects to scan at boot time
+   Can be overriden with spics=N kernel boot argument
+*/
+#define EXTRA_SPI_CS		0x00
+
+/***********************************************************************
+ * Platform device setup
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_SATA3
+
+#define SATA_MEM_START		BPHYSADDR(BCHP_SATA_AHCI_GHC_REG_START)
+#define SATA_MEM_SIZE		0x00010000
+
+static struct resource brcm_ahci_resource[] = {
+	[0] = {
+		.start	= SATA_MEM_START,
+		.end	= SATA_MEM_START + SATA_MEM_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= BRCM_IRQ_SATA,
+		.end	= BRCM_IRQ_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 brcm_ahci_dmamask = DMA_BIT_MASK(32);
+
+static int brcm_ahci_init(struct device *dev, void __iomem *addr)
+{
+	brcm_pm_sata3(1);
+	bchip_sata3_init();
+	return 0;
+}
+
+static void brcm_ahci_exit(struct device *dev)
+{
+	brcm_pm_sata3(0);
+}
+
+static int brcm_ahci_suspend(struct device *dev)
+{
+	brcm_pm_sata3(0);
+	return 0;
+}
+
+static int brcm_ahci_resume(struct device *dev)
+{
+	brcm_pm_sata3(1);
+	bchip_sata3_init();
+	return 0;
+}
+
+static struct ahci_platform_data brcm_ahci_pdata = {
+	.init = &brcm_ahci_init,
+	.exit = &brcm_ahci_exit,
+	.suspend = &brcm_ahci_suspend,
+	.resume = &brcm_ahci_resume,
+};
+
+static struct platform_device brcm_ahci_pdev = {
+	.name		= "strict-ahci",
+	.id		= 0,
+	.resource	= brcm_ahci_resource,
+	.num_resources	= ARRAY_SIZE(brcm_ahci_resource),
+	.dev		= {
+		.dma_mask		= &brcm_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &brcm_ahci_pdata,
+	},
+};
+
+#endif /* CONFIG_BRCM_HAS_SATA3 */
+
+#define BRCM_16550_PLAT_DEVICE(uart_addr, uart_irq) \
+	{ \
+		.mapbase = BPHYSADDR(uart_addr), \
+		.irq = (uart_irq), \
+		.regshift = 2, \
+		.iotype = UPIO_MEM32, \
+		.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE, \
+		.type = PORT_16550A, \
+	},
+
+static struct plat_serial8250_port brcm_16550_ports[] = {
+#ifdef CONFIG_BRCM_UARTA_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTA_REG_START, BRCM_IRQ_UARTA)
+#endif
+#ifdef CONFIG_BRCM_UARTB_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTB_REG_START, BRCM_IRQ_UARTB)
+#endif
+#ifdef CONFIG_BRCM_UARTC_IS_16550
+BRCM_16550_PLAT_DEVICE(BCHP_UARTC_REG_START, BRCM_IRQ_UARTC)
+#endif
+	{
+		.flags = 0,
+	}
+};
+
+static struct platform_device brcm_16550_uarts = {
+	.name = "serial8250",
+	.dev = {
+		.platform_data = &brcm_16550_ports,
+	},
+};
+
+static inline void brcm_bogus_release(struct device *dev)
+{
+}
+
+#if defined(CONFIG_I2C_BRCMSTB)
+
+static const char bsc_pdev_name[] = "brcmstb-i2c";
+
+#define BRCM_PLAT_DEVICE_DATA(_base, _end, _name, _id, _irq)	\
+	{							\
+			.reg_start = (_base),			\
+			.reg_end  = (_end),			\
+			.clk_rate = 375000,			\
+			.bus_name = (_name),			\
+			.flags = BRCMSTB_I2C_BUS_ENABLE,	\
+			.bus_id = (_id),			\
+			.irq = (_irq),				\
+	},
+
+static struct brcmstb_i2c_platform_data bsc_pdata[] = {
+#ifdef BCHP_BSCA_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCA_REG_START, BCHP_BSCA_REG_END, "BSC_A",
+			      0, -1)
+#endif
+
+#ifdef BCHP_BSCB_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCB_REG_START, BCHP_BSCB_REG_END, "BSC_B",
+			      1, -1)
+#endif
+
+#ifdef BCHP_BSCC_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCC_REG_START, BCHP_BSCC_REG_END, "BSC_C",
+			      2, -1)
+#endif
+
+#ifdef BCHP_BSCD_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCD_REG_START, BCHP_BSCD_REG_END, "BSC_D",
+			      3, -1)
+#endif
+
+#ifdef BCHP_BSCE_REG_START
+	BRCM_PLAT_DEVICE_DATA(BCHP_BSCE_REG_START, BCHP_BSCE_REG_END, "BSC_E",
+			      4, -1)
+#endif
+};
+
+static int __init brcm_add_bsc_master(int pdev_id,
+				struct brcmstb_i2c_platform_data *pdata)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(pdata->reg_start);
+	res[0].end = BPHYSADDR(pdata->reg_end);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = res[1].end = pdata->irq;
+	res[1].flags = IORESOURCE_IRQ;
+
+	pdev = platform_device_alloc("brcmstb-i2c", pdev_id);
+	if (!pdev ||
+	    platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
+	    platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
+	    platform_device_add(pdev)) {
+		platform_device_put(pdev);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+/*
+ * This function allow to override the default I2C bus speed for given I2C
+ * bus with a command line option.
+ * Format: i2c_bus=bus_id,clkrate (in hz)
+ */
+static int __init brcm_i2c_bus_cmdline(char *str)
+{
+	int ports;
+	int ints[3];
+	int i;
+
+	ports = ARRAY_SIZE(bsc_pdata);
+	get_options(str, 3, ints);
+	if (ints[0] < 2 || ints[1] < 0 || ints[1] > BRCMSTB_I2C_MAX_BUS_ID)
+		return 0;
+
+	for (i = 0; i < ports; i++) {
+		if (bsc_pdata[i].bus_id == ints[1]) {
+			bsc_pdata[ints[1]].clk_rate = ints[2];
+			bsc_pdata[ints[1]].flags =
+				BRCMSTB_I2C_BUS_ENABLE_CMDLINE;
+		} else {
+			/* disable other channels if we have a cmdline argument
+			   let the user choose the channels */
+			if (bsc_pdata[i].flags & BRCMSTB_I2C_BUS_ENABLE)
+				bsc_pdata[i].flags = BRCMSTB_I2C_BUS_DISABLE;
+		}
+	}
+
+	return 1;
+}
+__setup("i2c_bus=", brcm_i2c_bus_cmdline);
+
+#endif /* CONFIG_I2C_BRCMSTB */
+
+#if defined(CONFIG_BRCM_SDIO)
+
+static int nommc;
+
+static int __init nommc_setup(char *str)
+{
+	nommc = 1;
+	return 0;
+}
+
+__setup("nommc", nommc_setup);
+
+static void __init brcm_add_sdio_host(int id, uintptr_t cfg_base,
+	uintptr_t host_base, int irq)
+{
+	struct resource res[3];
+	struct sdhci_brcmstb_pdata pdata;
+
+	if (nommc) {
+		printk(KERN_INFO "SDIO_%d: disabled via command line\n", id);
+		return;
+	}
+	memset(&res, 0, sizeof(res));
+	memset(&pdata, 0, sizeof(pdata));
+	res[0].start = BPHYSADDR(host_base);
+	res[0].end = BPHYSADDR(host_base + 0xff);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BPHYSADDR(cfg_base);
+	res[1].end = BPHYSADDR(cfg_base + 0xff);
+	res[1].flags = IORESOURCE_MEM;
+
+	res[2].start = res[2].end = irq;
+	res[2].flags = IORESOURCE_IRQ;
+
+	/* second controller is for eMMC */
+	if (id == 1) {
+		pdata.caps |= (MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA);
+		pdata.caps2 |= MMC_CAP2_NO_SLEEP_CMD;
+	}
+	platform_device_register_resndata(NULL, "sdhci-brcmstb", id, res,
+					ARRAY_SIZE(res), &pdata,
+					sizeof(pdata));
+}
+
+#endif /* defined(CONFIG_BRCM_SDIO) */
+
+#define CAP_ACTIVE		0x01
+#define CAP_LAST		0x02
+#define CAP_TYPE		0x0c
+#define CAP_TYPE_SHIFT		0x02
+#define CAP_TYPE_EHCI		0x00
+#define CAP_TYPE_OHCI		0x01
+#define CAP_ADDR		0xffffff00
+
+static void __init brcm_add_usb_host(int type, int id, uintptr_t base)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	static const u64 usb_dmamask = ~(u32)0;
+#ifdef CONFIG_BRCM_USB_DISABLE_MASK
+	const unsigned long usb_disable_mask = CONFIG_BRCM_USB_DISABLE_MASK;
+#else
+	const unsigned long usb_disable_mask = 0x00;
+#endif
+	const int ehci_irqlist[] = BRCM_IRQLIST_EHCI;
+	const int ohci_irqlist[] = BRCM_IRQLIST_OHCI;
+
+	if (usb_disable_mask & (1 << id))
+		return;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = base;
+	res[0].end = base + 0xff;
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].flags = IORESOURCE_IRQ;
+
+	if (type == CAP_TYPE_EHCI) {
+		res[1].start = res[1].end = ehci_irqlist[id];
+		pdev = platform_device_alloc("ehci-brcm", id);
+	} else {
+		res[1].start = res[1].end = ohci_irqlist[id];
+		pdev = platform_device_alloc("ohci-brcm", id);
+	}
+
+	platform_device_add_resources(pdev, res, 2);
+
+	pdev->dev.dma_mask = (u64 *)&usb_dmamask;
+	pdev->dev.coherent_dma_mask = 0xffffffff;
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7435B0)
+	/* SWLINUX-2259: Prevent OHCI from doing DMA to memc1 */
+	if (type == CAP_TYPE_OHCI) {
+		static const u64 lowmem_dma_mask = DMA_BIT_MASK(31);
+		pdev->dev.dma_mask = (u64 *)&lowmem_dma_mask;
+		pdev->dev.coherent_dma_mask = (u32)lowmem_dma_mask;
+	}
+#endif
+
+	platform_device_add(pdev);
+}
+
+static void __init brcm_add_usb_hosts(void)
+{
+#if defined(CONFIG_BRCM_HAS_USB_CAPS)
+	unsigned long caplist[] = { BCHP_USB_CAPS_REG_START,
+#if defined(BCHP_USB1_CAPS_REG_START)
+				    BCHP_USB1_CAPS_REG_START,
+#endif
+				    0 };
+	unsigned long capp, cap;
+	int i, ehci_id = 0, ohci_id = 0;
+
+	/* The second USB is OTP'd out */
+	if (BRCM_PROD_ID() == 0x74285)
+		caplist[1] = 0;
+
+	for (i = 0; caplist[i] != 0; i++) {
+		capp = caplist[i];
+		do {
+			cap = BDEV_RD(capp);
+			capp += 4;
+
+			switch ((cap & CAP_TYPE) >> CAP_TYPE_SHIFT) {
+			case CAP_TYPE_EHCI:
+				if (cap & CAP_ACTIVE)
+					brcm_add_usb_host(CAP_TYPE_EHCI,
+						ehci_id, cap & CAP_ADDR);
+				ehci_id++;
+				break;
+			case CAP_TYPE_OHCI:
+				if (cap & CAP_ACTIVE)
+					brcm_add_usb_host(CAP_TYPE_OHCI,
+						ohci_id, cap & CAP_ADDR);
+				ohci_id++;
+				break;
+			}
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7231B0) || \
+	defined(CONFIG_BCM7344B0) || defined(CONFIG_BCM7346B0) || \
+	defined(CONFIG_BCM7584A0)
+		/* bug: incorrect CAP_LAST bit on some chips */
+		} while (capp != (caplist[i] + 0x20));
+#else
+		} while (!(cap & CAP_LAST));
+#endif
+	}
+
+#else /* CONFIG_BRCM_HAS_USB_CAPS */
+
+#define USB_BASE(shortname)	BCHP_##shortname##_REG_START
+
+#if defined(BCHP_USB_EHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 0, BPHYSADDR(USB_BASE(USB_EHCI)));
+#endif
+#if defined(BCHP_USB_EHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 1, BPHYSADDR(USB_BASE(USB_EHCI1)));
+#endif
+#if defined(BCHP_USB_EHCI2_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 2, BPHYSADDR(USB_BASE(USB_EHCI2)));
+#endif
+#if defined(BCHP_USB_OHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 0, BPHYSADDR(USB_BASE(USB_OHCI)));
+#endif
+#if defined(BCHP_USB_OHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 1, BPHYSADDR(USB_BASE(USB_OHCI1)));
+#endif
+#if defined(BCHP_USB_OHCI2_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 2, BPHYSADDR(USB_BASE(USB_OHCI2)));
+#endif
+#if defined(BCHP_USB1_EHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 2, BPHYSADDR(USB_BASE(USB1_EHCI)));
+#endif
+#if defined(BCHP_USB1_EHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_EHCI, 3, BPHYSADDR(USB_BASE(USB1_EHCI1)));
+#endif
+#if defined(BCHP_USB1_OHCI_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 2, BPHYSADDR(USB_BASE(USB1_OHCI)));
+#endif
+#if defined(BCHP_USB1_OHCI1_REG_START)
+	brcm_add_usb_host(CAP_TYPE_OHCI, 3, BPHYSADDR(USB_BASE(USB1_OHCI1)));
+#endif
+
+#endif /* CONFIG_BRCM_HAS_USB_CAPS */
+}
+
+#if defined(CONFIG_BRCM_HAS_GENET)
+static void __init brcm_override_genet_settings(
+	struct bcmgenet_platform_data *pd)
+{
+	/* update platform_data with any settings from CFE */
+
+	if (strcmp(brcm_eth0_phy, "INT") == 0)
+		pd->phy_interface = PHY_INTERFACE_MODE_NA;
+	else if (strcmp(brcm_eth0_phy, "MII") == 0)
+		pd->phy_interface = PHY_INTERFACE_MODE_MII;
+	else if (strcmp(brcm_eth0_phy, "RVMII") == 0)
+		pd->phy_interface = PHY_INTERFACE_MODE_REVMII;
+	else if (strcmp(brcm_eth0_phy, "RGMII") == 0)
+		pd->phy_interface = PHY_INTERFACE_MODE_RGMII_TXID;
+	else if (strcmp(brcm_eth0_phy, "RGMII_NO_ID") == 0)
+		pd->phy_interface = PHY_INTERFACE_MODE_RGMII;
+
+	if (brcm_eth0_speed)
+		pd->phy_speed = brcm_eth0_speed;
+#if defined(CONFIG_DREAMBOX_DM7080) || defined(CONFIG_DREAMBOX_DM820)
+	BDEV_UNSET(0xb80e18, 0x3f << 4);
+	BDEV_SET(0xb80e18, 0x14 << 4);
+#endif
+	/* note: this completely bypasses probing for a "live" PHY chip */
+	if (brcm_eth0_no_mdio)
+		pd->phy_address = -1;
+	else if (pd->phy_interface != PHY_INTERFACE_MODE_NA) {
+		if (strcmp(brcm_eth0_phyaddr, "probe") == 0)
+			pd->phy_address = -1;
+		else {
+			if (kstrtoint(brcm_eth0_phyaddr, 10, &pd->phy_address) ||
+			    pd->phy_address < 0 || pd->phy_address > 31) {
+				pr_warn("Invalid ETH0_PHYADDR, ignoring\n");
+				pd->phy_address = 1;
+			}
+		}
+	}
+}
+
+static void __init brcm_register_genet(int id, struct bcmgenet_platform_data *pd)
+{
+	struct resource res[3];
+	struct platform_device *pdev;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(pd->base_reg);
+	res[0].end = BPHYSADDR(pd->base_reg + 0x4fff);
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = res[1].end = pd->irq0;
+	res[1].flags = IORESOURCE_IRQ;
+
+	res[2].start = res[2].end = pd->irq1;
+	res[2].flags = IORESOURCE_IRQ;
+
+	brcm_alloc_macaddr(pd->mac_address);
+
+	pdev = platform_device_alloc("bcmgenet", id);
+	platform_device_add_resources(pdev, res, 3);
+	platform_device_add_data(pdev, pd, sizeof(*pd));
+	platform_device_add(pdev);
+}
+#endif /* defined(CONFIG_BRCM_HAS_GENET) */
+
+#if defined(CONFIG_BRCM_HAS_MOCA)
+static void __init brcm_register_moca(int enet_id)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	struct moca_platform_data pdata;
+	u8 macaddr[ETH_ALEN];
+	u32 val;
+
+	bchip_moca_init();
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(BCHP_DATA_MEM_REG_START);
+#ifdef BCHP_MOCA_HOSTMISC_MMP_REG_END
+	res[0].end = BPHYSADDR(BCHP_MOCA_HOSTMISC_MMP_REG_END) + 3;
+#else
+	res[0].end = BPHYSADDR(BCHP_MOCA_HOSTMISC_REG_END) + 3;
+#endif
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BRCM_IRQ_MOCA;
+	res[1].flags = IORESOURCE_IRQ;
+
+	brcm_alloc_macaddr(macaddr);
+	mac_to_u32(&pdata.macaddr_hi, &pdata.macaddr_lo, macaddr);
+
+	strcpy(pdata.enet_name, "bcmgenet");
+	pdata.enet_id = enet_id;
+	pdata.bcm3450_i2c_addr = 0x70;
+	pdata.bcm3450_i2c_base = brcm_moca_i2c_base;
+
+	val = BDEV_RD(BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID);
+	/* Handle 4 vs. 5 digits chip ID */
+	if (val >> 28)
+		pdata.chip_id = (val >> 16) << 16;
+	else
+		pdata.chip_id = (val >> 8) << 8;
+	pdata.chip_id |= (BRCM_CHIP_REV() + 0xa0);
+	pdata.hw_rev = CONFIG_BRCM_MOCA_VERS;
+	pdata.rf_band = brcm_moca_rf_band;
+
+	if (brcm_moca_i2c_base == 0) {
+		printk(KERN_WARNING
+			"error: bmoca I2C base addr is not set\n");
+		return;
+	}
+
+	pdev = platform_device_alloc("bmoca", 0);
+	platform_device_add_resources(pdev, res, 2);
+	platform_device_add_data(pdev, &pdata, sizeof(pdata));
+	platform_device_add(pdev);
+}
+#else /* defined(CONFIG_BRCM_HAS_MOCA) */
+static inline void brcm_register_moca(int enet_id) { }
+#endif /* defined(CONFIG_BRCM_HAS_MOCA) */
+
+static int __init platform_devices_setup(void)
+{
+	int i;
+
+#ifdef CONFIG_I2C_BRCMSTB
+	int j = 0;
+	int ret = 0;
+#endif
+
+#ifdef CONFIG_OF
+	return 0;
+#endif
+
+	/* UARTs */
+
+	brcm_16550_ports[0].uartclk = brcm_base_baud0 * 16;
+	for (i = 1; i < ARRAY_SIZE(brcm_16550_ports) - 1; i++)
+		brcm_16550_ports[i].uartclk = brcm_base_baud * 16;
+	platform_device_register(&brcm_16550_uarts);
+
+#if defined(CONFIG_BRCM_IKOS)
+	/* the remaining devices do not exist in emulation */
+	return 0;
+#endif
+
+	/* USB controllers */
+
+	if (brcm_usb_enabled) {
+		bchip_usb_init();
+		brcm_add_usb_hosts();
+	}
+
+	/* Network interfaces */
+
+#if defined(CONFIG_BRCM_HAS_GENET)
+	brcm_override_genet_settings(&genet_pdata[0]);
+
+	for (i = 0; i < BRCM_MAX_GENET; i++) {
+		struct bcmgenet_platform_data *pd = &genet_pdata[i];
+
+		if (pd->phy_interface == PHY_INTERFACE_MODE_MOCA)
+			brcm_register_moca(i);
+		if (pd->base_reg)
+			brcm_register_genet(i, pd);
+	}
+#endif /* defined(CONFIG_BRCM_HAS_GENET) */
+
+#if defined(CONFIG_BRCM_SDIO)
+	i = 0;
+#if defined(CONFIG_DREAMBOX)
+	/* Need to reverse the probe order */
+	brcm_add_sdio_host(i++, BCHP_SDIO_1_CFG_REG_START,
+		BCHP_SDIO_1_HOST_REG_START, BRCM_IRQ_SDIO1);
+#endif /* defined(CONFIG_DREAMBOX) */
+
+	brcm_add_sdio_host(i++, BCHP_SDIO_0_CFG_REG_START,
+		BCHP_SDIO_0_HOST_REG_START, BRCM_IRQ_SDIO0);
+
+#if !defined(CONFIG_DREAMBOX) && defined(BCHP_SDIO_1_CFG_REG_START)
+	brcm_add_sdio_host(i++, BCHP_SDIO_1_CFG_REG_START,
+		BCHP_SDIO_1_HOST_REG_START, BRCM_IRQ_SDIO1);
+#endif /* defined(BCHP_SDIO_1_CFG_REG_START) */
+
+#endif /* defined(CONFIG_BRCM_SDIO) */
+
+	/* AHCI */
+#if defined(CONFIG_BRCM_HAS_SATA3)
+	if (brcm_sata_enabled)
+		platform_device_register(&brcm_ahci_pdev);
+#endif
+
+#if defined(CONFIG_I2C_BRCMSTB)
+	for (i = 0; i < ARRAY_SIZE(bsc_pdata); i++) {
+		if (bsc_pdata[i].flags & (BRCMSTB_I2C_BUS_ENABLE |
+					 BRCMSTB_I2C_BUS_ENABLE_CMDLINE)) {
+			ret = brcm_add_bsc_master(j++, &bsc_pdata[i]);
+			if (ret < 0) {
+				printk(KERN_WARNING
+					"%s: cannot register bsc master chan %d"
+				       "(error %d)\n", __func__, i, ret);
+				break;
+			}
+
+		}
+	}
+#endif
+
+	return 0;
+}
+
+arch_initcall(platform_devices_setup);
+
+#if defined(CONFIG_BRCM_FLASH)
+
+/***********************************************************************
+ * Flash device setup
+ ***********************************************************************/
+
+#if defined(BCHP_EBI_CS_BASE_5)
+#define NUM_CS			6
+#elif defined(BCHP_EBI_CS_BASE_4)
+#define NUM_CS			5
+#elif defined(BCHP_EBI_CS_BASE_3)
+#define NUM_CS			4
+#elif defined(BCHP_EBI_CS_BASE_2)
+#define NUM_CS			3
+#else
+#define NUM_CS			2
+#endif
+
+#define TYPE_NONE		0
+#define TYPE_NOR		1
+#define TYPE_NAND		2
+#define TYPE_SPI		3
+#define TYPE_MAX		TYPE_SPI
+
+static const char type_names[][8] = { "NONE", "NOR", "NAND", "SPI" };
+
+struct ebi_cs_info {
+	int			type;
+	unsigned long		start;
+	unsigned long		len;
+	int			width;
+	unsigned long		base_reg;
+	unsigned long		config_reg;
+};
+
+static struct ebi_cs_info cs_info[NUM_CS];
+
+#ifdef CONFIG_BRCM_HAS_SPI
+static int __init brcm_setup_spi_flash(int cs, int bus_num, int nr_parts,
+	struct mtd_partition *parts)
+{
+	struct spi_board_info board_info;
+	struct flash_platform_data *pdata;
+	struct spi_master *master;
+
+	master = spi_busnum_to_master(bus_num);
+	if (!master) {
+		printk(KERN_WARNING "%s: can't locate SPI master\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->nr_parts = nr_parts;
+	pdata->parts = parts;
+
+	memset(&board_info, 0, sizeof(board_info));
+
+#if defined(CONFIG_DREAMBOX)
+    #if defined(CONFIG_DREAMBOX_DM520)
+	strcpy(board_info.modalias, "w25q128bv");
+    #else
+	strcpy(board_info.modalias, "mx25l12805d");
+    #endif
+#else
+	strcpy(board_info.modalias, "m25p80");
+#endif
+	board_info.bus_num = bus_num;
+	board_info.chip_select = cs;
+	board_info.mode = SPI_MODE_3;
+	board_info.platform_data = pdata;
+
+	if (spi_new_device(master, &board_info) == NULL) {
+		printk(KERN_WARNING "%s: can't add SPI device\n",
+			__func__);
+		kfree(pdata);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int __init brcm_setup_spi_master(int cs, int bus_id)
+{
+	struct resource res[4];
+	struct brcmspi_platform_data pdata;
+	struct platform_device *pdev;
+	memset(&pdata, 0, sizeof(pdata));
+
+	pdata.flash_cs = cs;
+
+	memset(&res, 0, sizeof(res));
+	res[0].start = BPHYSADDR(BCHP_HIF_MSPI_REG_START);
+	res[0].end = BPHYSADDR(BCHP_HIF_MSPI_REG_END) + 3;
+	res[0].flags = IORESOURCE_MEM;
+
+	res[1].start = BRCM_IRQ_HIF_SPI;
+	res[1].end = BRCM_IRQ_HIF_SPI;
+	res[1].flags = IORESOURCE_IRQ;
+
+	res[2].start = BPHYSADDR(BCHP_BSPI_REG_START);
+	res[2].end = BPHYSADDR(BCHP_BSPI_REG_END) + 3;
+	res[2].flags = IORESOURCE_MEM;
+
+	res[3].start = BPHYSADDR(BCHP_BSPI_RAF_REG_START);
+	res[3].end = BPHYSADDR(BCHP_BSPI_RAF_REG_END) + 3;
+	res[3].flags = IORESOURCE_MEM;
+
+	pdev = platform_device_alloc("spi_brcmstb", bus_id);
+	if (!pdev ||
+	    platform_device_add_resources(pdev, res, 4) ||
+	    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+	    platform_device_add(pdev)) {
+		platform_device_put(pdev);
+		return -ENODEV;
+	}
+	return 0;
+}
+#endif
+
+static int __initdata extra_spi_cs = EXTRA_SPI_CS;
+
+static int __init spics_setup(char *str)
+{
+	if (!*str || !*(str+1))
+		return 0;
+	str++;
+	get_option(&str, &extra_spi_cs);
+	return 0;
+}
+
+__setup("spics", spics_setup);
+
+static void __init brcm_setup_cs(int cs, int nr_parts,
+	struct mtd_partition *parts)
+{
+	struct platform_device *pdev;
+
+	switch (cs_info[cs].type) {
+	case TYPE_NOR: {
+#ifdef CONFIG_BRCM_HAS_NOR
+		struct physmap_flash_data pdata;
+		struct resource res;
+		static int nor_id;
+
+		memset(&res, 0, sizeof(res));
+		memset(&pdata, 0, sizeof(pdata));
+
+		pdata.width = cs_info[cs].width;
+		pdata.nr_parts = nr_parts;
+		pdata.parts = parts;
+
+		res.start = cs_info[cs].start;
+		res.end = cs_info[cs].start + cs_info[cs].len - 1;
+		res.flags = IORESOURCE_MEM;
+
+		pdev = platform_device_alloc("physmap-flash", nor_id++);
+		if (!pdev ||
+		    platform_device_add_resources(pdev, &res, 1) ||
+		    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+		    platform_device_add(pdev))
+			platform_device_put(pdev);
+#endif
+		break;
+	}
+	case TYPE_NAND: {
+		struct brcmnand_platform_data pdata;
+		struct resource r[2];
+		static int nand_id;
+
+		pdata.chip_select = cs;
+		pdata.nr_parts = nr_parts;
+		pdata.parts = parts;
+
+		memset(&r, 0, sizeof(r));
+		r[0].start = BPHYSADDR(BCHP_NAND_REG_START);
+		r[0].end = BPHYSADDR(BCHP_NAND_REG_END);
+		r[0].flags = IORESOURCE_MEM;
+		r[1].start = BRCM_IRQ_HIF;
+		r[1].end = r[1].start;
+		r[1].flags = IORESOURCE_IRQ;
+
+		pdev = platform_device_alloc("brcmnand", nand_id++);
+		if (!pdev ||
+	   	    platform_device_add_resources(pdev, r, ARRAY_SIZE(r)) ||
+		    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
+		    platform_device_add(pdev))
+			platform_device_put(pdev);
+		break;
+	}
+	case TYPE_SPI: {
+#ifdef CONFIG_BRCM_HAS_SPI
+		const int bus_num = 0;
+		static int spi_master_registered;
+		int ret;
+
+		if (!spi_master_registered) {
+			/* spi master must know about all CSs used by
+			   spi interface */
+			int spi_cs = (1 << cs) | extra_spi_cs;
+			ret = brcm_setup_spi_master(spi_cs, bus_num);
+			if (ret) {
+				printk(KERN_WARNING
+					"%s: can't register SPI master "
+					"(error %d)\n", __func__, ret);
+				break;
+			}
+			spi_master_registered = 1;
+		}
+
+		ret = brcm_setup_spi_flash(cs, bus_num, nr_parts, parts);
+		if (ret < 0) {
+			printk(KERN_WARNING
+				"%s: can't register SPI flash (error %d)\n",
+				__func__, ret);
+			break;
+		}
+#endif
+		break;
+	}
+	default:
+		BUG();
+	}
+}
+
+static int __initdata noflash;
+static int __initdata nandcs[NUM_CS];
+
+void ebi_restore_settings(void)
+{
+	int i;
+	for (i = 0; i < NUM_CS; i++) {
+		BDEV_WR(BCHP_EBI_CS_BASE_0 + (i * 8), cs_info[i].base_reg);
+#ifdef BCHP_EBI_CS_CONFIG_0
+		BDEV_WR(BCHP_EBI_CS_CONFIG_0 + (i * 8), cs_info[i].config_reg);
+#endif
+	}
+}
+
+static struct map_info brcm_dummy_map = {
+	.name			= "DUMMY",
+};
+
+static int __init brcmstb_mtd_setup(void)
+{
+	struct mtd_partition *parts;
+	int nr_parts;
+	int i, first = -1, primary = -1, primary_type = TYPE_NAND;
+
+#ifdef CONFIG_OF
+	return 0;
+#endif
+	if (noflash)
+		return 0;
+
+	nr_parts = board_get_partition_map(&parts);
+	if (nr_parts <= 0) {
+		struct mtd_info *mtd;
+
+		/*
+		 * mtd0 is normally the rootfs partition.  If it is missing,
+		 * create a dummy partition so that any person or script
+		 * trying to mount or erase mtd0 does not corrupt the
+		 * whole flash device.
+		 */
+		mtd = do_map_probe("map_absent", &brcm_dummy_map);
+		if (mtd)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
+			mtd_device_register(mtd, NULL, 0);
+#else
+			add_mtd_device(mtd);
+#endif
+
+		printk(KERN_WARNING
+			"warning: unable to build a flash partition map, "
+			"using entire device\n");
+
+		nr_parts = 0;
+		parts = NULL;
+	}
+
+	/* parse CFE FLASH_TYPE variable */
+	for (i = TYPE_NOR; i <= TYPE_MAX; i++)
+		if (strcmp(brcm_mtd_flash_type, type_names[i]) == 0)
+			primary_type = i;
+
+	/* scan each chip select to see what (if anything) lives there */
+	for (i = 0; i < NUM_CS; i++) {
+		u32 base, size, config __maybe_unused;
+
+		cs_info[i].type = TYPE_NONE;
+
+		base = BDEV_RD(BCHP_EBI_CS_BASE_0 + (i * 8));
+		size = base & 0x0f;
+
+		cs_info[i].base_reg = base;
+		cs_info[i].start = (base >> (13 + size)) << (13 + size);
+		cs_info[i].len = 8192UL << (base & 0xf);
+
+#ifdef BCHP_EBI_CS_CONFIG_0
+		config = BDEV_RD(BCHP_EBI_CS_CONFIG_0 + (i * 8));
+		cs_info[i].config_reg = config;
+		if (config & BCHP_EBI_CS_CONFIG_0_enable_MASK)
+			cs_info[i].type = TYPE_NOR;
+
+		if (config & BCHP_EBI_CS_CONFIG_0_dest_size_MASK)
+			cs_info[i].width = 2;
+		else
+			cs_info[i].width = 1;
+#endif
+#ifdef BCHP_EBI_CS_SPI_SELECT
+		/*
+		 * bits 7:0 - owned by HW (at most one bit active)
+		 * bits 23:16 - owned by SW (any number of '1' bits OK)
+		 * A '1' in either position means there is a SPI chip there.
+		 *
+		 * 65nm chips don't have SW bits 15:8 so EXTRA_SPI_CS
+		 * should be set at compile time for multiple SPI flashes.
+		 */
+		if ((BDEV_RD(BCHP_EBI_CS_SPI_SELECT) & (0x101 << i)) ||
+				(extra_spi_cs & (0x01 << i)))
+			cs_info[i].type = TYPE_SPI;
+#endif
+#ifdef BCHP_NAND_CS_NAND_SELECT
+		if (BDEV_RD(BCHP_NAND_CS_NAND_SELECT) & (0x100 << i))
+			cs_info[i].type = TYPE_NAND;
+#endif
+
+		if (cs_info[i].type != TYPE_NAND && nandcs[i] != 0) {
+			cs_info[i].type = TYPE_NAND;
+		} else {
+			/*
+			 * nandcs = ineligible to be primary.  The partition
+			 * information reported by CFE is not for the NAND
+			 * flash if CFE doesn't know the system has a
+			 * NAND flash.
+			 */
+			if (primary == -1 && primary_type == cs_info[i].type)
+				primary = i;
+		}
+		if (first == -1 && cs_info[i].type != TYPE_NONE)
+			first = i;
+	}
+
+	if (primary == -1) {
+		if (first == -1) {
+			printk(KERN_INFO "EBI: No flash devices detected\n");
+			return -ENODEV;
+		}
+		primary = first;
+		primary_type = cs_info[primary].type;
+	}
+
+	/* set up primary first, so that it owns mtd0/mtd1/(mtd2) */
+	printk(KERN_INFO "EBI CS%d: setting up %s flash (primary)\n", primary,
+		type_names[primary_type]);
+	brcm_setup_cs(primary, nr_parts, parts);
+
+	for (i = 0; i < NUM_CS; i++) {
+		if (i != primary && cs_info[i].type != TYPE_NONE) {
+			printk(KERN_INFO "EBI CS%d: setting up %s flash\n", i,
+				type_names[cs_info[i].type]);
+			brcm_setup_cs(i, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * late_initcall means the flash drivers are already loaded, so we control
+ * the order in which the /dev/mtd* devices get created.
+ */
+late_initcall(brcmstb_mtd_setup);
+
+static int __init noflash_setup(char *str)
+{
+	noflash = 1;
+	return 0;
+}
+
+__setup("noflash", noflash_setup);
+
+static int __init nandcs_setup(char *str)
+{
+	int opts[NUM_CS + 1], i;
+
+	if (*str == 0)
+		return 0;
+	get_options(str + 1, NUM_CS, opts);
+
+	for (i = 0; i < opts[0]; i++) {
+		int cs = opts[i + 1];
+		if ((cs >= 0) && (cs < NUM_CS))
+			nandcs[cs] = 1;
+	}
+	return 0;
+}
+
+__setup("nandcs", nandcs_setup);
+
+#else /* defined(CONFIG_BRCM_FLASH) */
+
+void ebi_restore_settings(void)
+{
+}
+
+#endif /* defined(CONFIG_BRCM_FLASH) */
+
+/***********************************************************************
+ * Miscellaneous platform-specific functions
+ ***********************************************************************/
+
+void __init bus_error_init(void)
+{
+}
+
+void brcm_machine_restart(const char *command)
+{
+/* PR21527 - Fix SMP reboot problem */
+#ifdef CONFIG_SMP
+	smp_send_stop();
+	udelay(10);
+#endif
+
+#ifdef BCHP_SUN_TOP_CTRL_SW_RESET
+	BDEV_WR_F_RB(SUN_TOP_CTRL_RESET_CTRL, master_reset_en, 1);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_RESET, chip_master_reset, 1);
+#else
+	BDEV_WR_F_RB(SUN_TOP_CTRL_RESET_SOURCE_ENABLE,
+		sw_master_reset_enable, 1);
+	BDEV_WR_F_RB(SUN_TOP_CTRL_SW_MASTER_RESET, chip_master_reset, 1);
+#endif
+
+	while (1)
+		;
+}
+
+void brcm_machine_halt(void)
+{
+	/* may be S3 cold boot */
+	brcm_pm_s3_cold_boot();
+
+	local_irq_disable();
+	while (1)
+		;
+}
+
+char *brcmstb_pcibios_setup(char *str)
+{
+	/* implement "pci=off" command line option */
+	if (!strcmp(str, "off")) {
+		brcm_sata_enabled = 0;
+		brcm_pcie_enabled = 0;
+		return NULL;
+	}
+	return str;
+}
diff --git a/drivers/brcmstb/sysfs.c b/drivers/brcmstb/sysfs.c
new file mode 100644
index 000000000000..7e65ecf35ad7
--- /dev/null
+++ b/drivers/brcmstb/sysfs.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+
+#ifdef CONFIG_MIPS
+#include <asm/cpu-info.h>
+#include <asm/r4kcache.h>
+#include <asm/mipsregs.h>
+#endif
+
+#include <linux/brcmstb/brcmstb.h>
+
+atomic_t brcm_unaligned_fp_count = ATOMIC_INIT(0);
+atomic_t brcm_rdhwr_count = ATOMIC_INIT(0);
+
+static struct platform_device *brcmstb_pdev;
+
+static ssize_t show_unaligned_fp_count(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+		atomic_read(&brcm_unaligned_fp_count));
+}
+
+static ssize_t show_rdhwr_count(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+		atomic_read(&brcm_rdhwr_count));
+}
+
+static ssize_t show_chip_id(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%04x\n", BRCM_CHIP_ID());
+}
+
+static ssize_t show_chip_rev(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%02X\n", BRCM_CHIP_REV() + 0xa0);
+}
+
+static ssize_t show_bmem(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int idx = 0;
+	unsigned long addr = 0, size = 0;
+	const char *name = attr->attr.name;
+
+	while (*name != 0) {
+		if (isdigit(*name)) {
+			idx = simple_strtoul(name, NULL, 10);
+			break;
+		}
+		name++;
+	}
+	bmem_region_info(idx, &addr, &size);
+
+	return snprintf(buf, PAGE_SIZE, "0x%08lx 0x%08lx\n", addr, size);
+}
+
+static ssize_t show_ocap_partition(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%08lx 0x%08lx\n",
+		brcm_mtd_ocap_start, brcm_mtd_ocap_len);
+}
+
+static ssize_t show_cfe_boardname(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%s\n", brcm_cfe_boardname);
+}
+
+#ifdef CONFIG_MIPS
+static ssize_t show_cache_max_writeback(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.max_writeback);
+}
+
+static ssize_t show_cache_max_writethrough(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.max_writethrough);
+}
+
+static ssize_t show_cache_prefetch_enabled(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct brcm_cache_info info;
+	brcm_get_cache_info(&info);
+	return snprintf(buf, PAGE_SIZE, "%d\n", info.prefetch_enabled);
+}
+
+static ssize_t show_cpu_name(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%s\n", __cpu_name[0]);
+}
+
+static ssize_t show_cp0_config_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "0x%08x 0x%08x 0x%08x\n",
+		__read_32bit_c0_register($16, 0),
+		__read_32bit_c0_register($16, 1),
+		__read_32bit_c0_register($16, 7));
+}
+
+static inline ssize_t show_cp0_brcm_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE,
+		"0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+		__read_32bit_c0_register($22, 0),
+		__read_32bit_c0_register($22, 1),
+		__read_32bit_c0_register($22, 2),
+		__read_32bit_c0_register($22, 3),
+		__read_32bit_c0_register($22, 4),
+		__read_32bit_c0_register($22, 5),
+		__read_32bit_c0_register($22, 6),
+		__read_32bit_c0_register($22, 7));
+}
+
+static ssize_t show_cpu_khz(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%ld\n", brcm_adj_cpu_khz);
+}
+#endif
+
+static inline ssize_t dump_core_regs(unsigned long cbr,
+	const int *regs, int n_regs, char *buf)
+{
+	int i, bytes = 0;
+
+	for (i = 0; i < n_regs; i++)
+		bytes += snprintf(&buf[bytes], PAGE_SIZE - bytes, "0x%08lx ",
+			DEV_RD(cbr + regs[i]));
+	buf[bytes - 1] = '\n';
+	return bytes;
+}
+
+#ifdef CONFIG_CPU_BMIPS3300
+static ssize_t show_bmips3300_core_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const int regs[] = { BMIPS_RAC_CONFIG, BMIPS_RAC_ADDRESS_RANGE };
+
+	return dump_core_regs(__BMIPS_GET_CBR(), regs, ARRAY_SIZE(regs), buf);
+}
+#endif
+
+#ifdef CONFIG_CPU_BMIPS4380
+static ssize_t show_bmips4380_core_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	const int regs[] = {
+		BMIPS_RAC_CONFIG, BMIPS_RAC_ADDRESS_RANGE, BMIPS_RAC_CONFIG_1,
+		BMIPS_L2_CONFIG, BMIPS_LMB_CONTROL, BMIPS_SYSTEM_BASE,
+		BMIPS_PERF_GLOBAL_CONTROL, BMIPS_PERF_CONTROL_0,
+		BMIPS_PERF_CONTROL_1, BMIPS_PERF_COUNTER_0,
+		BMIPS_PERF_COUNTER_1, BMIPS_PERF_COUNTER_2,
+		BMIPS_PERF_COUNTER_3, BMIPS_RELO_VECTOR_CONTROL_0,
+		BMIPS_RELO_VECTOR_CONTROL_1 };
+
+	return dump_core_regs(__BMIPS_GET_CBR(), regs, ARRAY_SIZE(regs), buf);
+}
+#endif
+
+/* Display secondary cache module settings */
+
+#if defined(CONFIG_BRCM_ZSCM_L2)
+
+static ssize_t show_zscm_regs(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE,
+		"0x%08lx 0x%08lx 0x%08lx 0x%08lx 0x%08lx "
+		"0x%08lx 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
+		bmips_read_zscm_reg(0x00), bmips_read_zscm_reg(0x10),
+		bmips_read_zscm_reg(0x20), bmips_read_zscm_reg(0x30),
+		bmips_read_zscm_reg(0x40), bmips_read_zscm_reg(0x50),
+		bmips_read_zscm_reg(0x60), bmips_read_zscm_reg(0x70),
+		bmips_read_zscm_reg(0x80), bmips_read_zscm_reg(0x90));
+}
+#endif
+
+static struct device_attribute brcmstb_attr_list[] = {
+	__ATTR(unaligned_fp_count, 0444, show_unaligned_fp_count, NULL),
+	__ATTR(rdhwr_count, 0444, show_rdhwr_count, NULL),
+	__ATTR(chip_id, 0444, show_chip_id, NULL),
+	__ATTR(chip_rev, 0444, show_chip_rev, NULL),
+	__ATTR(ocap_partition, 0444, show_ocap_partition, NULL),
+	__ATTR(cfe_boardname, 0444, show_cfe_boardname, NULL),
+#if defined(CONFIG_MIPS)
+	__ATTR(cache_max_writeback, 0444, show_cache_max_writeback, NULL),
+	__ATTR(cache_max_writethrough, 0444, show_cache_max_writethrough, NULL),
+	__ATTR(cache_prefetch_enabled, 0444, show_cache_prefetch_enabled, NULL),
+	__ATTR(cpu_name, 0444, show_cpu_name, NULL),
+	__ATTR(cp0_config_regs, 0444, show_cp0_config_regs, NULL),
+	__ATTR(cpu_khz, 0444, show_cpu_khz, NULL),
+#endif
+#if   defined(CONFIG_CPU_BMIPS3300)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+	__ATTR(bmips3300_core_regs, 0444, show_bmips3300_core_regs, NULL),
+#elif defined(CONFIG_CPU_BMIPS4380)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+	__ATTR(bmips4380_core_regs, 0444, show_bmips4380_core_regs, NULL),
+#elif defined(CONFIG_CPU_BMIPS5000)
+	__ATTR(cp0_brcm_regs, 0444, show_cp0_brcm_regs, NULL),
+#endif
+#if defined(CONFIG_BRCM_ZSCM_L2)
+	__ATTR(zscm_regs, 0444, show_zscm_regs, NULL),
+#endif
+#if defined(CONFIG_BRCM_CPU_DIV)
+	__ATTR(cpu_div, 0644, brcm_pm_show_cpu_div, brcm_pm_store_cpu_div),
+#endif
+#if defined(CONFIG_BRCM_CPU_PLL)
+	__ATTR(cpu_pll, 0644, brcm_pm_show_cpu_pll, brcm_pm_store_cpu_pll),
+#endif
+	__ATTR(sata_power, 0644, brcm_pm_show_sata_power,
+		brcm_pm_store_sata_power),
+	__ATTR(ddr_timeout, 0644, brcm_pm_show_ddr_timeout,
+		brcm_pm_store_ddr_timeout),
+	__ATTR(standby_flags, 0644, brcm_pm_show_standby_flags,
+		brcm_pm_store_standby_flags),
+	__ATTR(standby_timeout, 0644, brcm_pm_show_standby_timeout,
+		brcm_pm_store_standby_timeout),
+	__ATTR(time_at_wakeup, 0444, brcm_pm_show_time_at_wakeup, NULL),
+#if defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	__ATTR(memc1_power, 0644, brcm_pm_show_memc1_power,
+		brcm_pm_store_memc1_power),
+#endif
+//	__ATTR(halt_mode, 0644, brcm_pm_show_halt_mode,
+//		brcm_pm_store_halt_mode),
+	__ATTR_NULL,
+};
+
+static int __init brcm_pdev_init(void)
+{
+	struct device *dev;
+	int i;
+	struct device_attribute *attr;
+
+	brcmstb_pdev = platform_device_alloc("brcmstb", -1);
+	if (brcmstb_pdev == NULL) {
+		printk(KERN_WARNING "%s: can't allocate device\n",
+			__func__);
+		return -ENODEV;
+	}
+	platform_device_add(brcmstb_pdev);
+	dev = &brcmstb_pdev->dev;
+
+	for (attr = brcmstb_attr_list; attr->attr.name != NULL; attr++)
+		if (device_create_file(dev, attr) != 0)
+			WARN(1, "Can't create sysfs file\n");
+
+	/* create an attribute for each bmem region */
+	for (i = 0; ; i++) {
+		unsigned long addr, size;
+		struct device_attribute *attr;
+		char *name;
+
+		if (bmem_region_info(i, &addr, &size) < 0)
+			break;
+		attr = kzalloc(sizeof(*attr), GFP_KERNEL);
+		if (attr == NULL)
+			break;
+
+		name = kzalloc(16, GFP_KERNEL);
+		if (name == NULL)
+			break;
+		snprintf(name, 16, "bmem.%d", i);
+
+		sysfs_attr_init(&attr->attr);
+		attr->attr.name = name;
+		attr->attr.mode = 0444;
+		attr->show = show_bmem;
+
+		if (device_create_file(dev, attr) != 0)
+			WARN(1, "Can't create sysfs file\n");
+	}
+
+	return 0;
+}
+
+arch_initcall(brcm_pdev_init);
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 552373c4e362..c3e3d3730be1 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,14 @@
 
 menu "Bus devices"
 
+config BRCMSTB_GISB_ARB
+	bool "Broadcom STB GISB bus arbiter"
+	depends on ARM || MIPS
+	help
+	  Driver for the Broadcom Set Top Box System-on-a-chip internal bus
+	  arbiter. This driver provides timeout and target abort error handling
+	  and internal bus master decoding.
+
 config IMX_WEIM
 	bool "Freescale EIM DRIVER"
 	depends on ARCH_MXC
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 8947bdd0de8b..04dee2062c63 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
 obj-$(CONFIG_IMX_WEIM)	+= imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
new file mode 100644
index 000000000000..d27fe4182064
--- /dev/null
+++ b/drivers/bus/brcmstb_gisb.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/of.h>
+#include <linux/bitops.h>
+#include <linux/pm.h>
+
+#include <asm/bug.h>
+#include <asm/signal.h>
+
+#define ARB_TIMER			0x008
+#define ARB_ERR_CAP_CLR			0x7e4
+#define  ARB_ERR_CAP_CLEAR		(1 << 0)
+#define ARB_ERR_CAP_HI_ADDR		0x7e8
+#define ARB_ERR_CAP_ADDR		0x7ec
+#define ARB_ERR_CAP_DATA		0x7f0
+#define ARB_ERR_CAP_STATUS		0x7f4
+#define  ARB_ERR_CAP_STATUS_TIMEOUT	(1 << 12)
+#define  ARB_ERR_CAP_STATUS_TEA		(1 << 11)
+#define  ARB_ERR_CAP_STATUS_BS_SHIFT	(1 << 2)
+#define  ARB_ERR_CAP_STATUS_BS_MASK	0x3c
+#define  ARB_ERR_CAP_STATUS_WRITE	(1 << 1)
+#define  ARB_ERR_CAP_STATUS_VALID	(1 << 0)
+#define ARB_ERR_CAP_MASTER		0x7f8
+
+struct brcmstb_gisb_arb_device {
+	void __iomem	*base;
+	struct mutex	lock;
+	struct list_head next;
+	u32 valid_mask;
+	const char *master_names[sizeof(u32) * BITS_PER_BYTE];
+	u32 saved_timeout;
+};
+
+static LIST_HEAD(brcmstb_gisb_arb_device_list);
+
+static ssize_t gisb_arb_get_timeout(struct device *dev,
+				    struct device_attribute *attr,
+				    char *buf)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+	u32 timeout;
+
+	mutex_lock(&gdev->lock);
+	timeout = ioread32(gdev->base + ARB_TIMER);
+	mutex_unlock(&gdev->lock);
+
+	return sprintf(buf, "%d", timeout);
+}
+
+static ssize_t gisb_arb_set_timeout(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+	int val, ret;
+
+	ret = kstrtoint(buf, 10, &val);
+	if (ret < 0)
+		return ret;
+
+	if (val == 0 || val >= 0xffffffff)
+		return -EINVAL;
+
+	mutex_lock(&gdev->lock);
+	iowrite32(val, gdev->base + ARB_TIMER);
+	mutex_unlock(&gdev->lock);
+
+	return count;
+}
+
+static const char *
+brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
+						u32 masters)
+{
+	u32 mask = gdev->valid_mask & masters;
+
+	if (hweight_long(mask) != 1)
+		return NULL;
+
+	return gdev->master_names[ffs(mask) - 1];
+}
+
+static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
+					const char *reason)
+{
+	u32 cap_status;
+	unsigned long arb_addr;
+	u32 master;
+	const char *m_name;
+	char m_fmt[11];
+
+	cap_status = ioread32(gdev->base + ARB_ERR_CAP_STATUS);
+
+	/* Invalid captured address, bail out */
+	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
+		return 1;
+
+	/* Read the address and master */
+	arb_addr = ioread32(gdev->base + ARB_ERR_CAP_ADDR) & 0xffffffff;
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	arb_addr |= (u64)ioread32(gdev->base + ARB_ERR_CAP_HI_ADDR) << 32;
+#endif
+	master = ioread32(gdev->base + ARB_ERR_CAP_MASTER);
+
+	m_name = brcmstb_gisb_master_to_str(gdev, master);
+	if (!m_name) {
+		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
+		m_name = m_fmt;
+	}
+
+	pr_crit("%s: %s at 0x%lx [%c %s], core: %s\n",
+		__func__, reason, arb_addr,
+		cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
+		cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
+		m_name);
+
+	/* clear the GISB error */
+	iowrite32(ARB_ERR_CAP_CLEAR, gdev->base + ARB_ERR_CAP_CLR);
+
+	return 0;
+}
+
+static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr,
+				     struct pt_regs *regs)
+{
+	int ret = 0;
+	struct brcmstb_gisb_arb_device *gdev;
+
+	/* iterate over each GISB arb registered handlers */
+	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
+		ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
+	/*
+	 * If it was an imprecise abort, then we need to correct the
+	 * return address to be _after_ the instruction.
+	*/
+	if (fsr & (1 << 10))
+		regs->ARM_pc += 4;
+
+	return ret;
+}
+
+static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
+{
+	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
+{
+	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
+
+	return IRQ_HANDLED;
+}
+
+static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
+		gisb_arb_get_timeout, gisb_arb_set_timeout);
+
+static struct attribute *gisb_arb_sysfs_attrs[] = {
+	&dev_attr_gisb_arb_timeout.attr,
+	NULL,
+};
+
+static struct attribute_group gisb_arb_sysfs_attr_group = {
+	.attrs = gisb_arb_sysfs_attrs,
+};
+
+static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct brcmstb_gisb_arb_device *gdev;
+	struct resource *r;
+	int err, timeout_irq, tea_irq;
+	unsigned int num_masters, j = 0;
+	int i, first, last;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	timeout_irq = platform_get_irq(pdev, 0);
+	tea_irq = platform_get_irq(pdev, 1);
+
+	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
+	if (!gdev)
+		return -ENOMEM;
+
+	mutex_init(&gdev->lock);
+	INIT_LIST_HEAD(&gdev->next);
+
+	gdev->base = devm_request_and_ioremap(&pdev->dev, r);
+	if (!gdev->base)
+		return -ENOMEM;
+
+	err = devm_request_irq(&pdev->dev, timeout_irq,
+				brcmstb_gisb_timeout_handler, 0, pdev->name,
+				gdev);
+	if (err < 0)
+		return err;
+
+	err = devm_request_irq(&pdev->dev, tea_irq,
+				brcmstb_gisb_tea_handler, 0, pdev->name,
+				gdev);
+	if (err < 0)
+		return err;
+
+	/* If we do not have a valid mask, assume all masters are enabled */
+	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
+				&gdev->valid_mask))
+		gdev->valid_mask = 0xffffffff;
+
+	/* Proceed with reading the litteral names if we agree on the
+	 * number of masters
+	 */
+	num_masters = of_property_count_strings(dn,
+			"brcm,gisb-arb-master-names");
+	if (hweight_long(gdev->valid_mask) == num_masters) {
+		first = ffs(gdev->valid_mask) - 1;
+		last = fls(gdev->valid_mask) - 1;
+
+		for (i = first; i < last; i++) {
+			if (!(gdev->valid_mask & BIT(i)))
+				continue;
+
+			of_property_read_string_index(dn,
+					"brcm,gisb-arb-master-names", j,
+					&gdev->master_names[i]);
+			j++;
+		}
+	}
+
+	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
+	if (err)
+		return err;
+
+	platform_set_drvdata(pdev, gdev);
+
+	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
+
+	hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0,
+			"imprecise external abort");
+
+	dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
+			gdev->base, timeout_irq, tea_irq);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_gisb_arb_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+
+	gdev->saved_timeout = ioread32(gdev->base + ARB_TIMER);
+
+	return 0;
+}
+
+/* Make sure we provide the same timeout value that was configured before, and
+ * do this before the GISB timeout interrupt handler has any chance to run
+ */
+static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct brcmstb_gisb_arb_device *gdev = platform_get_drvdata(pdev);
+
+	iowrite32(gdev->saved_timeout, gdev->base + ARB_TIMER);
+
+	return 0;
+}
+#else
+#define brcmstb_gisb_arb_suspend	NULL
+#define brcmstb_gisb_arb_resume_noirq	NULL
+#endif
+
+static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
+	.suspend	= brcmstb_gisb_arb_suspend,
+	.resume_noirq	= brcmstb_gisb_arb_resume_noirq,
+};
+
+static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
+	{ .compatible = "brcm,gisb-arb" },
+	{ },
+};
+
+static struct platform_driver brcmstb_gisb_arb_driver = {
+	.driver = {
+		.name	= "brcm-gisb-arb",
+		.owner	= THIS_MODULE,
+		.of_match_table = brcmstb_gisb_arb_of_match,
+		.pm	= &brcmstb_gisb_arb_pm_ops,
+	},
+};
+
+static int __init brcm_gisb_driver_init(void)
+{
+	return platform_driver_probe(&brcmstb_gisb_arb_driver,
+				     brcmstb_gisb_arb_probe);
+}
+
+module_init(brcm_gisb_driver_init);
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index a324f9303e36..6b2e404d3760 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -61,3 +61,5 @@ obj-$(CONFIG_JS_RTC)		+= js-rtc.o
 js-rtc-y = rtc.o
 
 obj-$(CONFIG_TILE_SROM)		+= tile-srom.o
+
+obj-$(CONFIG_BRCM_MOCA)		+= bmoca.o
diff --git a/drivers/char/bmoca.c b/drivers/char/bmoca.c
new file mode 100644
index 000000000000..7fd2eafa38b5
--- /dev/null
+++ b/drivers/char/bmoca.c
@@ -0,0 +1,2957 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)            KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/version.h>
+#include <linux/scatterlist.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_net.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/clk-brcmstb.h>
+#include <linux/netdevice.h>
+#include <linux/suspend.h>
+
+#define DRV_VERSION		0x00040000
+#define DRV_BUILD_NUMBER	0x20110831
+
+#if defined(CONFIG_BRCMSTB)
+#define MOCA6816		0
+#include <linux/bmoca.h>
+#elif defined(DSL_MOCA)
+#define MOCA6816		1
+#include "bmoca.h"
+#include <boardparms.h>
+#include <bcm3450.h>
+#include <linux/netdevice.h>
+#else
+#define MOCA6816		1
+#include <linux/bmoca.h>
+#endif
+
+#if defined(CONFIG_BRCMSTB)
+#include <linux/brcmstb/brcmstb.h>
+#endif
+
+#define MOCA_ENABLE		1
+#define MOCA_DISABLE		0
+
+#define OFF_PKT_REINIT_MEM	0x00a08000
+#define PKT_REINIT_MEM_SIZE	(32 * 1024)
+#define PKT_REINIT_MEM_END	(OFF_PKT_REINIT_MEM  + PKT_REINIT_MEM_SIZE)
+
+/* The mailbox layout is different for MoCA 2.0 compared to
+   MoCA 1.1 */
+
+/* MoCA 1.1 mailbox layout */
+#define HOST_REQ_SIZE_11        304
+#define HOST_RESP_SIZE_11       256
+#define CORE_REQ_SIZE_11        400
+#define CORE_RESP_SIZE_11       64
+
+/* MoCA 1.1 offsets from the mailbox pointer */
+#define HOST_REQ_OFFSET_11      0
+#define HOST_RESP_OFFSET_11     (HOST_REQ_OFFSET_11 + HOST_REQ_SIZE_11)
+#define CORE_REQ_OFFSET_11      (HOST_RESP_OFFSET_11 + HOST_RESP_SIZE_11)
+#define CORE_RESP_OFFSET_11     (CORE_REQ_OFFSET_11 + CORE_REQ_SIZE_11)
+
+/* MoCA 2.0 mailbox layout */
+#define HOST_REQ_SIZE_20        512
+#define HOST_RESP_SIZE_20       512
+#define CORE_REQ_SIZE_20        512
+#define CORE_RESP_SIZE_20       512
+
+/* MoCA 2.0 offsets from the mailbox pointer */
+#define HOST_REQ_OFFSET_20      0
+#define HOST_RESP_OFFSET_20     (HOST_REQ_OFFSET_20 + 0)
+#define CORE_REQ_OFFSET_20      (HOST_RESP_OFFSET_20 + HOST_RESP_SIZE_20)
+#define CORE_RESP_OFFSET_20     (CORE_REQ_OFFSET_20 + 0)
+
+#define HOST_REQ_SIZE_MAX       HOST_REQ_SIZE_20
+#define CORE_REQ_SIZE_MAX       CORE_REQ_SIZE_20
+#define CORE_RESP_SIZE_MAX      CORE_RESP_SIZE_20
+
+/* local H2M, M2H buffers */
+#define NUM_CORE_MSG		32
+#define NUM_HOST_MSG		8
+
+#define FW_CHUNK_SIZE		4096
+#define MAX_BL_CHUNKS		8
+#define MAX_FW_SIZE		(1024 * 1024)
+#define MAX_FW_PAGES		((MAX_FW_SIZE >> PAGE_SHIFT) + 1)
+#define MAX_LAB_PRINTF		104
+
+#ifdef __LITTLE_ENDIAN
+#define M2M_WRITE		(BIT(31) | BIT(27) | BIT(28))
+#define M2M_READ		(BIT(30) | BIT(27) | BIT(28))
+#else
+#define M2M_WRITE		(BIT(31) | BIT(27))
+#define M2M_READ		(BIT(30) | BIT(27))
+#endif
+
+#define RESET_HIGH_CPU		BIT(0)
+#define RESET_MOCA_SYS		BIT(1)
+#define RESET_LOW_CPU		BIT(2)
+
+#define RESET_GMII		BIT(3)
+#define RESET_PHY_0		BIT(4)
+#define RESET_PHY_1		BIT(5)
+#define DISABLE_CLOCKS		BIT(7)
+#define DISABLE_PHY_0_CLOCK	BIT(8)
+#define DISABLE_PHY_1_CLOCK	BIT(9)
+
+#define M2M_TIMEOUT_MS		100
+
+#define NO_FLUSH_IRQ		0
+#define FLUSH_IRQ		1
+#define FLUSH_DMA_ONLY		2
+#define FLUSH_REQRESP_ONLY	3
+#define FLUSH_WOL_ONLY		4
+
+#define DEFAULT_PHY_CLOCK	(300 * 1000000)
+#define MOCA_SUSPEND_TIMEOUT_MS 300
+
+/* DMA buffers may not share a cache line with anything else */
+#define __DMA_ALIGN__		__aligned(L1_CACHE_BYTES)
+
+struct moca_host_msg {
+	u32			data[HOST_REQ_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct list_head	chain __DMA_ALIGN__;
+	u32			len;
+};
+
+struct moca_core_msg {
+	u32			data[CORE_REQ_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct list_head	chain __DMA_ALIGN__;
+	u32			len;
+};
+
+struct moca_regs {
+	unsigned int		data_mem_offset;
+	unsigned int		data_mem_size;
+	unsigned int		cntl_mem_size;
+	unsigned int		cntl_mem_offset;
+	unsigned int		gp0_offset;
+	unsigned int		gp1_offset;
+	unsigned int		ringbell_offset;
+	unsigned int		l2_status_offset;
+	unsigned int		l2_clear_offset;
+	unsigned int		l2_mask_set_offset;
+	unsigned int		l2_mask_clear_offset;
+	unsigned int		sw_reset_offset;
+	unsigned int		led_ctrl_offset;
+	unsigned int		m2m_src_offset;
+	unsigned int		m2m_dst_offset;
+	unsigned int		m2m_cmd_offset;
+	unsigned int		m2m_status_offset;
+	unsigned int		m2m_src_high_offset;
+	unsigned int		m2m_dst_high_offset;
+	unsigned int		moca2host_mmp_inbox_0_offset;
+	unsigned int		moca2host_mmp_inbox_1_offset;
+	unsigned int		moca2host_mmp_inbox_2_offset;
+	unsigned int		extras_mmp_outbox_3_offset;
+	unsigned int		h2m_resp_bit[2]; /* indexed by cpu */
+	unsigned int		h2m_req_bit[2]; /* indexed by cpu */
+	unsigned int		sideband_gmii_fc_offset;
+};
+
+struct moca_priv_data {
+	struct platform_device	*pdev;
+	struct device		*dev;
+
+	unsigned int		minor;
+	int			irq;
+	struct work_struct	work;
+	void __iomem		*base;
+	void __iomem		*i2c_base;
+	struct device_node	*enet_node;
+
+	unsigned int		mbx_offset[2]; /* indexed by MoCA cpu */
+	struct page		*fw_pages[MAX_FW_PAGES];
+	struct scatterlist	fw_sg[MAX_FW_PAGES];
+	struct completion	copy_complete;
+	struct completion	chunk_complete;
+
+	struct list_head	host_msg_free_list;
+	struct list_head	host_msg_pend_list;
+	struct moca_host_msg	host_msg_queue[NUM_HOST_MSG] __DMA_ALIGN__;
+	wait_queue_head_t	host_msg_wq;
+
+	struct list_head	core_msg_free_list;
+	struct list_head	core_msg_pend_list;
+	u32		core_resp_buf[CORE_RESP_SIZE_MAX / 4] __DMA_ALIGN__;
+	struct moca_core_msg	core_msg_queue[NUM_CORE_MSG] __DMA_ALIGN__;
+	struct moca_core_msg	core_msg_temp __DMA_ALIGN__;
+	wait_queue_head_t	core_msg_wq;
+
+	spinlock_t		list_lock;
+	spinlock_t		clock_lock;
+	spinlock_t		irq_status_lock;
+	struct mutex		dev_mutex;
+	struct mutex		copy_mutex;
+	struct mutex		moca_i2c_mutex;
+	int			host_mbx_busy;
+	int			host_resp_pending;
+	int			core_req_pending;
+	int			assert_pending;
+	int			wdt_pending;
+
+	int			enabled;
+	int			running;
+	struct clk		*clk;
+	struct clk		*phy_clk;
+	struct clk		*cpu_clk;
+	struct clk		*wol_clk;
+
+
+	int			refcount;
+	unsigned long		start_time;
+	dma_addr_t		tpcap_buf_phys;
+
+	unsigned int		bonded_mode;
+	unsigned int		phy_freq;
+
+	unsigned int		hw_rev;
+
+	const struct moca_regs	*regs;
+
+	/* MMP Parameters */
+	unsigned int		mmp_20;
+	unsigned int		host_req_size;
+	unsigned int		host_resp_size;
+	unsigned int		core_req_size;
+	unsigned int		core_resp_size;
+	unsigned int		host_req_offset;
+	unsigned int		host_resp_offset;
+	unsigned int		core_req_offset;
+	unsigned int		core_resp_offset;
+
+	/* for user space suspend/resume notifications */
+	struct notifier_block	pm_notifier;
+	enum moca_pm_states	state;
+	struct completion	suspend_complete;
+
+	/* wol */
+	int     wol_irq;
+};
+
+static const struct moca_regs regs_11_plus = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (256 * 1024),
+	.cntl_mem_offset		= 0x00040000,
+	.cntl_mem_size			= (128 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_11_lite = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (96 * 1024),
+	.cntl_mem_offset		= 0x0004c000,
+	.cntl_mem_size			= (80 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_11 = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (256 * 1024),
+	.cntl_mem_offset		= 0x0004c000,
+	.cntl_mem_size			= (80 * 1024),
+	.gp0_offset			= 0x000a2050,
+	.gp1_offset			= 0x000a2054,
+	.ringbell_offset		= 0x000a2060,
+	.l2_status_offset		= 0x000a2080,
+	.l2_clear_offset		= 0x000a2088,
+	.l2_mask_set_offset		= 0x000a2090,
+	.l2_mask_clear_offset		= 0x000a2094,
+	.sw_reset_offset		= 0x000a2040,
+	.led_ctrl_offset		= 0x000a204c,
+	.m2m_src_offset			= 0x000a2000,
+	.m2m_dst_offset			= 0x000a2004,
+	.m2m_cmd_offset			= 0x000a2008,
+	.m2m_status_offset		= 0x000a200c,
+	.h2m_resp_bit[1]		= 0x1,
+	.h2m_req_bit[1]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x000a1420
+};
+
+static const struct moca_regs regs_20 = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (288 * 1024),
+	.cntl_mem_offset		= 0x00120000,
+	.cntl_mem_size			= (384 * 1024),
+	.gp0_offset			= 0,
+	.gp1_offset			= 0,
+	.ringbell_offset		= 0x001ffd0c,
+	.l2_status_offset		= 0x001ffc40,
+	.l2_clear_offset		= 0x001ffc48,
+	.l2_mask_set_offset		= 0x001ffc50,
+	.l2_mask_clear_offset		= 0x001ffc54,
+	.sw_reset_offset		= 0x001ffd00,
+	.led_ctrl_offset		= 0,
+	.m2m_src_offset			= 0x001ffc00,
+	.m2m_dst_offset			= 0x001ffc04,
+	.m2m_cmd_offset			= 0x001ffc08,
+	.m2m_status_offset		= 0x001ffc0c,
+	.m2m_src_high_offset		= 0x001ffc10,
+	.m2m_dst_high_offset		= 0x001ffc14,
+	.moca2host_mmp_inbox_0_offset	= 0x001ffd58,
+	.moca2host_mmp_inbox_1_offset	= 0x001ffd5c,
+	.moca2host_mmp_inbox_2_offset	= 0x001ffd60,
+	.extras_mmp_outbox_3_offset	= 0x001fec3c,
+	.h2m_resp_bit[1]		= 0x10,
+	.h2m_req_bit[1]			= 0x20,
+	.h2m_resp_bit[0]		= 0x1,
+	.h2m_req_bit[0]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x001fec18
+};
+
+static const struct moca_regs regs_20_gen4 = {
+	.data_mem_offset		= 0,
+	.data_mem_size			= (768 * 1024),
+	.cntl_mem_offset		= 0x00100000,
+	.cntl_mem_size			= (416 * 1024),
+	.gp0_offset			= 0,
+	.gp1_offset			= 0,
+	.ringbell_offset		= 0x001ffd0c,
+	.l2_status_offset		= 0x001ffc40,
+	.l2_clear_offset		= 0x001ffc48,
+	.l2_mask_set_offset		= 0x001ffc50,
+	.l2_mask_clear_offset		= 0x001ffc54,
+	.sw_reset_offset		= 0x001ffd00,
+	.led_ctrl_offset		= 0,
+	.m2m_src_offset			= 0x001ffc00,
+	.m2m_dst_offset			= 0x001ffc04,
+	.m2m_cmd_offset			= 0x001ffc08,
+	.m2m_status_offset		= 0x001ffc0c,
+	.m2m_src_high_offset		= 0x001ffc10,
+	.m2m_dst_high_offset		= 0x001ffc14,
+	.moca2host_mmp_inbox_0_offset	= 0x001ffd58,
+	.moca2host_mmp_inbox_1_offset	= 0x001ffd5c,
+	.moca2host_mmp_inbox_2_offset	= 0x001ffd60,
+	.h2m_resp_bit[1]		= 0x10,
+	.h2m_req_bit[1]			= 0x20,
+	.h2m_resp_bit[0]		= 0x1,
+	.h2m_req_bit[0]			= 0x2,
+	.sideband_gmii_fc_offset	= 0x001fec18
+};
+
+#define MOCA_FW_MAGIC		0x4d6f4341
+
+struct moca_fw_hdr {
+	uint32_t		jump[2];
+	uint32_t		length;
+	uint32_t		cpuid;
+	uint32_t		magic;
+	uint32_t		hw_rev;
+	uint32_t		bl_chunks;
+	uint32_t		res1;
+};
+
+struct bsc_regs {
+	u32			chip_address;
+	u32			data_in[8];
+	u32			cnt_reg;
+	u32			ctl_reg;
+	u32			iic_enable;
+	u32			data_out[8];
+	u32			ctlhi_reg;
+	u32			scl_param;
+};
+
+static const char * const __maybe_unused moca_state_string[] = {
+	[MOCA_ACTIVE] = "active",
+	[MOCA_SUSPENDING] = "suspending",
+	[MOCA_SUSPENDING_WAITING_ACK] = "suspending waiting for ACK",
+	[MOCA_SUSPENDING_GOT_ACK] = "suspending got ACK",
+	[MOCA_SUSPENDED] = "suspended",
+	[MOCA_RESUMING] = "resuming",
+	[MOCA_RESUMING_ASSERT] = "resuming ASSERT",
+	[MOCA_RESUMING_WDOG] = "resuming WDOG"
+};
+
+/* support for multiple MoCA devices */
+#define NUM_MINORS		8
+static struct moca_priv_data *minor_tbl[NUM_MINORS];
+static struct class *moca_class;
+
+/* character major device number */
+#define MOCA_MAJOR		234
+#define MOCA_CLASS		"bmoca"
+
+#define M2H_RESP		BIT(0)
+#define M2H_REQ			BIT(1)
+#define M2H_ASSERT		BIT(2)
+#define M2H_NEXTCHUNK		BIT(3)
+#define M2H_NEXTCHUNK_CPU0	BIT(4)
+#define M2H_WDT_CPU0		BIT(6)
+#define M2H_WOL			BIT(7)
+#define M2H_WDT_CPU1		BIT(10)
+#define M2H_DMA			BIT(11)
+
+#define M2H_RESP_CPU0		BIT(13)
+#define M2H_REQ_CPU0		BIT(14)
+#define M2H_ASSERT_CPU0		BIT(15)
+
+#define ASSERT_PENDING_CPU0	BIT(0)
+#define ASSERT_PENDING_CPU1	BIT(1)
+
+/* does this word contain a NIL byte (i.e. end of string)? */
+#define HAS0(x)			((((x) & 0xff) == 0) || \
+				 (((x) & 0xff00) == 0) || \
+				 (((x) & 0xff0000) == 0) || \
+				 (((x) & 0xff000000) == 0))
+
+#define MOCA_SET(x, y)	 MOCA_WR(x, MOCA_RD(x) | (y))
+#define MOCA_UNSET(x, y) MOCA_WR(x, MOCA_RD(x) & ~(y))
+
+static void moca_3450_write_i2c(struct moca_priv_data *priv, u8 addr,
+				u32 data);
+static u32 moca_3450_read_i2c(struct moca_priv_data *priv, u8 addr);
+static int moca_get_mbx_offset(struct moca_priv_data *priv);
+
+#define INRANGE(x, a, b)	(((x) >= (a)) && ((x) < (b)))
+
+static inline int moca_range_ok(struct moca_priv_data *priv,
+	unsigned long offset, unsigned long len)
+{
+	const struct moca_regs *r = priv->regs;
+	unsigned long lastad = offset + len - 1;
+
+	if (lastad < offset)
+		return -EINVAL;
+
+	if (INRANGE(offset, r->cntl_mem_offset,
+		    r->cntl_mem_offset + r->cntl_mem_size) &&
+	    INRANGE(lastad, r->cntl_mem_offset,
+		    r->cntl_mem_offset + r->cntl_mem_size))
+		return 0;
+
+	if (INRANGE(offset, r->data_mem_offset,
+		    r->data_mem_offset + r->data_mem_size) &&
+	    INRANGE(lastad, r->data_mem_offset,
+		    r->data_mem_offset + r->data_mem_size))
+		return 0;
+
+	if (INRANGE(offset, OFF_PKT_REINIT_MEM, PKT_REINIT_MEM_END) &&
+	    INRANGE(lastad, OFF_PKT_REINIT_MEM, PKT_REINIT_MEM_END))
+		return 0;
+
+	return -EINVAL;
+}
+
+static void moca_mmp_init(struct moca_priv_data *priv, int is20)
+{
+	if (is20) {
+		priv->host_req_size    = HOST_REQ_SIZE_20;
+		priv->host_resp_size   = HOST_RESP_SIZE_20;
+		priv->core_req_size    = CORE_REQ_SIZE_20;
+		priv->core_resp_size   = CORE_RESP_SIZE_20;
+		priv->host_req_offset  = HOST_REQ_OFFSET_20;
+		priv->host_resp_offset = HOST_RESP_OFFSET_20;
+		priv->core_req_offset  = CORE_REQ_OFFSET_20;
+		priv->core_resp_offset = CORE_RESP_OFFSET_20;
+		priv->mmp_20 = 1;
+	} else {
+		priv->host_req_size    = HOST_REQ_SIZE_11;
+		priv->host_resp_size   = HOST_RESP_SIZE_11;
+		priv->core_req_size    = CORE_REQ_SIZE_11;
+		priv->core_resp_size   = CORE_RESP_SIZE_11;
+		priv->host_req_offset  = HOST_REQ_OFFSET_11;
+		priv->host_resp_offset = HOST_RESP_OFFSET_11;
+		priv->core_req_offset  = CORE_REQ_OFFSET_11;
+		priv->core_resp_offset = CORE_RESP_OFFSET_11;
+		priv->mmp_20 = 0;
+	}
+}
+
+static bool moca_is_20(struct moca_priv_data *priv)
+{
+	return (priv->hw_rev & MOCA_PROTVER_MASK) == MOCA_PROTVER_20;
+}
+
+static bool moca_has_m2m_high(struct moca_priv_data *priv)
+{
+	return priv->hw_rev >= HWREV_MOCA_20_GEN23;
+}
+
+#ifdef CONFIG_BRCM_MOCA_BUILTIN_FW
+#error Not supported in this version
+#else
+static const char *bmoca_fw_image;
+#endif
+
+/*
+ * LOW-LEVEL DEVICE OPERATIONS
+ */
+
+#define MOCA_RD(x)		__raw_readl((void __iomem *)(x))
+#define MOCA_WR(x, y)		__raw_writel((y), (void __iomem *)(x))
+
+#define I2C_RD(x)		MOCA_RD(x)
+#define I2C_WR(x, y)		MOCA_WR(x, y)
+
+static void moca_hw_reset(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* disable and clear all interrupts */
+	MOCA_WR(priv->base + r->l2_mask_set_offset, 0xffffffff);
+	MOCA_RD(priv->base + r->l2_mask_set_offset);
+
+	/* assert resets */
+
+	/* reset CPU first, both CPUs for MoCA 20 HW */
+	MOCA_SET(priv->base + r->sw_reset_offset, RESET_HIGH_CPU |
+		 (moca_is_20(priv) ? RESET_LOW_CPU : 0));
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	udelay(20);
+
+	/* reset everything else except clocks */
+	MOCA_SET(priv->base + r->sw_reset_offset,
+		 ~(RESET_GMII | DISABLE_CLOCKS));
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	/* disable clocks */
+	MOCA_SET(priv->base + r->sw_reset_offset, ~RESET_GMII);
+	MOCA_RD(priv->base + r->sw_reset_offset);
+
+	MOCA_WR(priv->base + r->l2_clear_offset, 0xffffffff);
+	MOCA_RD(priv->base + r->l2_clear_offset);
+}
+
+/* called any time we start/restart/stop MoCA */
+static void moca_hw_init(struct moca_priv_data *priv, int action)
+{
+	const struct moca_regs *r = priv->regs;
+	int clk_status = 0;
+
+	if (action == MOCA_ENABLE && !priv->enabled) {
+		clk_status = clk_prepare_enable(priv->clk);
+		if (clk_status != 0) {
+			dev_err(priv->dev, "moca clk enable failed\n");
+			goto clk_err_chk;
+		}
+
+		clk_status = clk_prepare_enable(priv->phy_clk);
+		if (clk_status != 0) {
+			dev_err(priv->dev, "moca phy clk enable failed\n");
+			goto clk_err_chk;
+		}
+		clk_status = clk_prepare_enable(priv->cpu_clk);
+		if (clk_status != 0) {
+			dev_err(priv->dev, "moca cpu clk enable failed\n");
+			goto clk_err_chk;
+		}
+
+		clk_status = clk_prepare_enable(priv->wol_clk);
+		if (clk_status != 0)
+			dev_err(priv->dev, "moca cpu clk enable failed\n");
+clk_err_chk:
+		priv->enabled = clk_status ? 0 : 1;
+	}
+
+	/* clock not enabled, register accesses will fail with bus error */
+	if (!priv->enabled)
+		return;
+
+	moca_hw_reset(priv);
+	udelay(1);
+
+	if (action == MOCA_ENABLE) {
+		/* deassert moca_sys_reset and clock */
+		MOCA_UNSET(priv->base + r->sw_reset_offset,
+			   RESET_MOCA_SYS | DISABLE_CLOCKS);
+
+		if (priv->hw_rev >= HWREV_MOCA_20_GEN22) {
+			/* Take PHY0 out of reset and enable clock */
+			MOCA_UNSET(priv->base + r->sw_reset_offset,
+				   RESET_PHY_0 | DISABLE_PHY_0_CLOCK);
+
+			if (priv->bonded_mode) {
+				/* Take PHY1 out of reset and enable clock */
+				MOCA_UNSET(priv->base + r->sw_reset_offset,
+					   RESET_PHY_1 | DISABLE_PHY_1_CLOCK);
+			}
+		}
+		MOCA_RD(priv->base + r->sw_reset_offset);
+	}
+
+	if (!moca_is_20(priv)) {
+		/* clear junk out of GP0/GP1 */
+		MOCA_WR(priv->base + r->gp0_offset, 0xffffffff);
+		MOCA_WR(priv->base + r->gp1_offset, 0x0);
+		/* set up activity LED for 50% duty cycle */
+		MOCA_WR(priv->base + r->led_ctrl_offset, 0x40004000);
+	}
+
+	/* enable DMA completion interrupts */
+	MOCA_WR(priv->base + r->ringbell_offset, 0);
+	MOCA_WR(priv->base + r->l2_mask_clear_offset, M2H_DMA);
+	MOCA_RD(priv->base + r->l2_mask_clear_offset);
+
+	if (action == MOCA_DISABLE && priv->enabled) {
+		priv->enabled = 0;
+		clk_disable_unprepare(priv->cpu_clk);
+		clk_disable_unprepare(priv->phy_clk);
+		clk_disable_unprepare(priv->clk);
+		clk_disable_unprepare(priv->wol_clk);
+	}
+}
+
+static void moca_ringbell(struct moca_priv_data *priv, u32 mask)
+{
+	const struct moca_regs *r = priv->regs;
+
+	MOCA_WR(priv->base + r->ringbell_offset, mask);
+	MOCA_RD(priv->base + r->ringbell_offset);
+}
+
+static u32 moca_irq_status(struct moca_priv_data *priv, int flush)
+{
+	const struct moca_regs *r = priv->regs;
+	u32 stat, dma_mask = M2H_DMA | M2H_NEXTCHUNK;
+	unsigned long flags;
+
+	if (moca_is_20(priv))
+		dma_mask |= M2H_NEXTCHUNK_CPU0;
+
+	spin_lock_irqsave(&priv->irq_status_lock, flags);
+
+	stat = MOCA_RD(priv->base + priv->regs->l2_status_offset);
+
+	if (flush == FLUSH_IRQ) {
+		MOCA_WR(priv->base + r->l2_clear_offset, stat);
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+	if (flush == FLUSH_DMA_ONLY) {
+		MOCA_WR(priv->base + r->l2_clear_offset,
+			stat & dma_mask);
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+	if (flush == FLUSH_REQRESP_ONLY) {
+		MOCA_WR(priv->base + r->l2_clear_offset,
+			stat & (M2H_RESP | M2H_REQ |
+			M2H_RESP_CPU0 | M2H_REQ_CPU0));
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+	if (flush == FLUSH_WOL_ONLY) {
+		MOCA_WR(priv->base + r->l2_clear_offset,
+			stat & M2H_WOL);
+		MOCA_RD(priv->base + r->l2_clear_offset);
+	}
+
+	spin_unlock_irqrestore(&priv->irq_status_lock, flags);
+
+	return stat;
+}
+
+static void moca_enable_irq(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* unmask everything */
+	u32 mask = M2H_REQ | M2H_RESP | M2H_ASSERT | M2H_WDT_CPU1 |
+		M2H_NEXTCHUNK | M2H_DMA;
+
+	if (moca_is_20(priv))
+		mask |= M2H_WDT_CPU0 | M2H_NEXTCHUNK_CPU0 |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0 | M2H_ASSERT_CPU0;
+
+	MOCA_WR(priv->base + r->l2_mask_clear_offset, mask);
+	MOCA_RD(priv->base + r->l2_mask_clear_offset);
+}
+
+static void moca_disable_irq(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+
+	/* mask everything except DMA completions */
+	u32 mask = M2H_REQ | M2H_RESP | M2H_ASSERT | M2H_WDT_CPU1 |
+		M2H_NEXTCHUNK;
+
+	if (moca_is_20(priv))
+		mask |= M2H_WDT_CPU0 | M2H_NEXTCHUNK_CPU0 |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0 | M2H_ASSERT_CPU0;
+
+	MOCA_WR(priv->base + r->l2_mask_set_offset, mask);
+	MOCA_RD(priv->base + r->l2_mask_set_offset);
+}
+
+static u32 moca_start_mips(struct moca_priv_data *priv, u32 cpu)
+{
+	const struct moca_regs *r = priv->regs;
+
+	if (moca_is_20(priv)) {
+		if (cpu == 1)
+			MOCA_UNSET(priv->base + r->sw_reset_offset,
+				   RESET_HIGH_CPU);
+		else {
+			moca_mmp_init(priv, 1);
+			MOCA_UNSET(priv->base + r->sw_reset_offset,
+				   RESET_LOW_CPU);
+		}
+	} else
+		MOCA_UNSET(priv->base + r->sw_reset_offset, RESET_HIGH_CPU);
+	MOCA_RD(priv->base + r->sw_reset_offset);
+	return 0;
+}
+
+static void moca_m2m_xfer(struct moca_priv_data *priv,
+	dma_addr_t dst, dma_addr_t src, u32 ctl)
+{
+	const struct moca_regs *r = priv->regs;
+	u32 status;
+	long timeout = msecs_to_jiffies(M2M_TIMEOUT_MS);
+	u32 dst_low = lower_32_bits(dst);
+	u32 src_low = lower_32_bits(src);
+	u32 dst_high = upper_32_bits(dst);
+	u32 src_high = upper_32_bits(src);
+
+	MOCA_WR(priv->base + r->m2m_src_offset, src_low);
+	MOCA_WR(priv->base + r->m2m_dst_offset, dst_low);
+	if (moca_has_m2m_high(priv)) {
+		MOCA_WR(priv->base + r->m2m_src_high_offset, src_high);
+		MOCA_WR(priv->base + r->m2m_dst_high_offset, dst_high);
+	}
+	MOCA_WR(priv->base + r->m2m_status_offset, 0);
+	MOCA_RD(priv->base + r->m2m_status_offset);
+	MOCA_WR(priv->base + r->m2m_cmd_offset, ctl);
+
+	if (wait_for_completion_timeout(&priv->copy_complete, timeout) == 0) {
+		dev_warn(priv->dev, "DMA interrupt timed out, status %x\n",
+			 moca_irq_status(priv, NO_FLUSH_IRQ));
+	}
+
+	status = MOCA_RD(priv->base + r->m2m_status_offset);
+
+	if (status & (3 << 29))
+		dev_warn(priv->dev, "bad status %08x (s/d/c %pad %pad %08x)\n",
+			 status, &src, &dst, ctl);
+}
+
+static void moca_write_mem(struct moca_priv_data *priv,
+	dma_addr_t dst_offset, void *src, unsigned int len)
+{
+	dma_addr_t pa;
+
+	if (moca_range_ok(priv, dst_offset, len) < 0) {
+		dev_warn(priv->dev, "copy past end of cntl memory: %pad\n",
+			 &dst_offset);
+		return;
+	}
+
+	pa = dma_map_single(&priv->pdev->dev, src, len, DMA_TO_DEVICE);
+	moca_m2m_xfer(priv, dst_offset + priv->regs->data_mem_offset, pa,
+		len | M2M_WRITE);
+	dma_unmap_single(&priv->pdev->dev, pa, len, DMA_TO_DEVICE);
+}
+
+static void moca_read_mem(struct moca_priv_data *priv,
+	void *dst, dma_addr_t src_offset, unsigned int len)
+{
+	int i;
+
+	if (moca_range_ok(priv, src_offset, len) < 0) {
+		dev_warn(priv->dev, "copy past end of cntl memory: %pad\n",
+			 &src_offset);
+		return;
+	}
+
+	for (i = 0; i < len; i += 4)
+		DEV_WR(dst + i, cpu_to_be32(
+			MOCA_RD(priv->base + src_offset +
+				priv->regs->data_mem_offset + i)));
+}
+
+static void moca_write_sg(struct moca_priv_data *priv,
+	dma_addr_t dst_offset, struct scatterlist *sg, int nents)
+{
+	int j;
+	uintptr_t addr = priv->regs->data_mem_offset + dst_offset;
+
+	dma_map_sg(&priv->pdev->dev, sg, nents, DMA_TO_DEVICE);
+
+	for (j = 0; j < nents; j++) {
+		moca_m2m_xfer(priv, addr, sg[j].dma_address,
+			sg[j].length | M2M_WRITE);
+
+		addr += sg[j].length;
+	}
+
+	dma_unmap_sg(&priv->pdev->dev, sg, nents, DMA_TO_DEVICE);
+}
+
+static inline void moca_read_sg(struct moca_priv_data *priv,
+	dma_addr_t src_offset, struct scatterlist *sg, int nents)
+{
+	int j;
+	uintptr_t addr = priv->regs->data_mem_offset + src_offset;
+
+	dma_map_sg(&priv->pdev->dev, sg, nents, DMA_FROM_DEVICE);
+
+	for (j = 0; j < nents; j++) {
+		moca_m2m_xfer(priv, sg[j].dma_address, addr,
+			sg[j].length | M2M_READ);
+
+		addr += sg[j].length;
+		SetPageDirty(sg_page(&sg[j]));
+	}
+
+	dma_unmap_sg(&priv->pdev->dev, sg, nents, DMA_FROM_DEVICE);
+}
+
+#define moca_3450_write moca_3450_write_i2c
+#define moca_3450_read moca_3450_read_i2c
+
+static void moca_put_pages(struct moca_priv_data *priv, int pages)
+{
+	int i;
+
+	for (i = 0; i < pages; i++)
+		page_cache_release(priv->fw_pages[i]);
+}
+
+static int moca_get_pages(struct moca_priv_data *priv, unsigned long addr,
+	int size, unsigned int moca_addr, int write)
+{
+	unsigned int pages, chunk_size;
+	int ret, i;
+
+	if (addr & 3)
+		return -EINVAL;
+	if ((size <= 0) || (size > MAX_FW_SIZE))
+		return -EINVAL;
+
+	pages = ((addr & ~PAGE_MASK) + size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+
+	down_read(&current->mm->mmap_sem);
+	ret = get_user_pages(current, current->mm, addr & PAGE_MASK, pages,
+		write, 0, priv->fw_pages, NULL);
+	up_read(&current->mm->mmap_sem);
+
+	if (ret < 0)
+		return ret;
+	BUG_ON((ret > MAX_FW_PAGES) || (pages == 0));
+
+	if (ret < pages) {
+		dev_warn(priv->dev,
+			 "get_user_pages returned %d expecting %d\n",
+			 ret, pages);
+		moca_put_pages(priv, ret);
+		return -EFAULT;
+	}
+
+	chunk_size = PAGE_SIZE - (addr & ~PAGE_MASK);
+	if (size < chunk_size)
+		chunk_size = size;
+
+	sg_set_page(&priv->fw_sg[0], priv->fw_pages[0], chunk_size,
+		addr & ~PAGE_MASK);
+	size -= chunk_size;
+
+	for (i = 1; i < pages; i++) {
+		sg_set_page(&priv->fw_sg[i], priv->fw_pages[i],
+			size > PAGE_SIZE ? PAGE_SIZE : size, 0);
+		size -= PAGE_SIZE;
+	}
+	return ret;
+}
+
+static int moca_write_img(struct moca_priv_data *priv, struct moca_xfer *x)
+{
+	int pages, i, ret = -EINVAL;
+	struct moca_fw_hdr hdr;
+	u32 bl_chunks;
+	long timeout = msecs_to_jiffies(M2M_TIMEOUT_MS);
+
+	if (copy_from_user(&hdr, (void __user *)(unsigned long)x->buf,
+			sizeof(hdr)))
+		return -EFAULT;
+
+	bl_chunks = be32_to_cpu(hdr.bl_chunks);
+	if (!bl_chunks || (bl_chunks > MAX_BL_CHUNKS))
+		bl_chunks = 1;
+
+	pages = moca_get_pages(priv, (unsigned long)x->buf, x->len, 0, 0);
+	if (pages < 0)
+		return pages;
+	if (pages < (bl_chunks + 2))
+		goto out;
+
+	/* host must use FW_CHUNK_SIZE MMU pages (for now) */
+	BUG_ON(FW_CHUNK_SIZE != PAGE_SIZE);
+
+	/* write the first two chunks, then start the MIPS */
+	moca_write_sg(priv, 0, &priv->fw_sg[0], bl_chunks + 1);
+	moca_enable_irq(priv);
+	moca_start_mips(priv, be32_to_cpu(hdr.cpuid));
+	ret = 0;
+
+	/* wait for an ACK, then write each successive chunk */
+	for (i = bl_chunks + 1; i < pages; i++) {
+		if (wait_for_completion_timeout(&priv->chunk_complete, timeout)
+		    == 0) {
+			moca_disable_irq(priv);
+			dev_warn(priv->dev, "chunk ack timed out\n");
+			ret = -EIO;
+			goto out;
+		}
+		moca_write_sg(priv, priv->regs->data_mem_offset +
+			      FW_CHUNK_SIZE * bl_chunks,
+			      &priv->fw_sg[i], 1);
+	}
+
+	/* wait for ACK of last block.  Older firmware images didn't
+	   ACK the last block, so don't return an error */
+	wait_for_completion_timeout(&priv->chunk_complete, timeout);
+
+out:
+	moca_put_pages(priv, pages);
+	return ret;
+}
+
+/*
+ * MESSAGE AND LIST HANDLING
+ */
+
+static void moca_handle_lab_printf(struct moca_priv_data *priv,
+	struct moca_core_msg *m)
+{
+	u32 str_len;
+	u32 str_addr;
+
+	if (priv->mmp_20) {
+		str_len = (be32_to_cpu(m->data[4]) + 3) & ~3;
+		str_addr = be32_to_cpu(m->data[3]) & 0x1fffffff;
+
+		if ((be32_to_cpu(m->data[0]) == 0x3) &&
+		    (be32_to_cpu(m->data[1]) == 12) &&
+		    ((be32_to_cpu(m->data[2]) & 0xffffff) == 0x090801) &&
+		    (be32_to_cpu(m->data[4]) <= MAX_LAB_PRINTF)) {
+			m->len = 3 + str_len;
+			moca_read_mem(priv, &m->data[3], str_addr, str_len);
+
+			m->data[1] = cpu_to_be32(m->len - 8);
+		}
+	} else {
+		str_len = (be32_to_cpu(m->data[3]) + 3) & ~3;
+		str_addr = be32_to_cpu(m->data[2]) & 0x1fffffff;
+
+		if ((be32_to_cpu(m->data[0]) & 0xff0000ff) == 0x09000001 &&
+			be32_to_cpu(m->data[1]) == 0x600b0008 &&
+			(be32_to_cpu(m->data[3]) <= MAX_LAB_PRINTF)) {
+
+			m->len = 8 + str_len;
+			moca_read_mem(priv, &m->data[2], str_addr, str_len);
+
+			m->data[1] = cpu_to_be32((MOCA_IE_DRV_PRINTF << 16) +
+				m->len - 8);
+		}
+	}
+}
+static void moca_msg_reset(struct moca_priv_data *priv)
+{
+	int i;
+
+	if (priv->running)
+		moca_disable_irq(priv);
+	priv->running = 0;
+	priv->host_mbx_busy = 0;
+	priv->host_resp_pending = 0;
+	priv->core_req_pending = 0;
+	priv->assert_pending = 0;
+	priv->mbx_offset[0] = -1;
+	priv->mbx_offset[1] = -1;
+
+	spin_lock_bh(&priv->list_lock);
+	INIT_LIST_HEAD(&priv->core_msg_free_list);
+	INIT_LIST_HEAD(&priv->core_msg_pend_list);
+
+	for (i = 0; i < NUM_CORE_MSG; i++)
+		list_add_tail(&priv->core_msg_queue[i].chain,
+			&priv->core_msg_free_list);
+
+	INIT_LIST_HEAD(&priv->host_msg_free_list);
+	INIT_LIST_HEAD(&priv->host_msg_pend_list);
+
+	for (i = 0; i < NUM_HOST_MSG; i++)
+		list_add_tail(&priv->host_msg_queue[i].chain,
+			&priv->host_msg_free_list);
+	spin_unlock_bh(&priv->list_lock);
+}
+
+static struct list_head *moca_detach_head(struct moca_priv_data *priv,
+	struct list_head *h)
+{
+	struct list_head *r = NULL;
+
+	spin_lock_bh(&priv->list_lock);
+	if (!list_empty(h)) {
+		r = h->next;
+		list_del(r);
+	}
+	spin_unlock_bh(&priv->list_lock);
+
+	return r;
+}
+
+static void moca_attach_tail(struct moca_priv_data *priv,
+	struct list_head *elem, struct list_head *list)
+{
+	spin_lock_bh(&priv->list_lock);
+	list_add_tail(elem, list);
+	spin_unlock_bh(&priv->list_lock);
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_recvmsg(struct moca_priv_data *priv, uintptr_t offset,
+	u32 max_size, uintptr_t reply_offset, u32 cpuid)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+	unsigned int w, rw, num_ies;
+	u32 data, size;
+	char *msg;
+	int err = -ENOMEM;
+	u32 *reply = priv->core_resp_buf;
+	int attach = 1;
+
+	m = &priv->core_msg_temp;
+
+	/* make sure we have the mailbox offset before using it */
+	moca_get_mbx_offset(priv);
+
+	/* read only as much as is necessary.
+	   The second word is the length for mmp_20 */
+	if (priv->mmp_20) {
+		moca_read_mem(priv, m->data,
+			offset + priv->mbx_offset[cpuid], 8);
+
+		size = (be32_to_cpu(m->data[1])+3) & 0xFFFFFFFC;
+		/* if size is too large, this is a protocol error.
+		   mocad will output the error message */
+		if (size > max_size - 8)
+			size = max_size - 8;
+
+		moca_read_mem(priv, &m->data[2],
+			offset + priv->mbx_offset[cpuid] + 8, size);
+	} else
+		moca_read_mem(priv, m->data,
+			offset + priv->mbx_offset[cpuid], max_size);
+
+	data = be32_to_cpu(m->data[0]);
+
+	if (priv->mmp_20) {
+		/* In MoCA 2.0, there is only 1 IE per message */
+		num_ies = 1;
+	} else {
+		num_ies = data & 0xffff;
+	}
+
+	if (reply_offset) {
+		if (priv->mmp_20) {
+			/* In MoCA 2.0, the ACK is to simply set the
+			   MSB in the incoming message and send it
+			   back */
+			reply[0] = cpu_to_be32(data | 0x80000000);
+			rw = 1;
+		} else {
+			/* ACK + seq number + number of IEs */
+			reply[0] = cpu_to_be32((data & 0x00ff0000) |
+				0x04000000 | num_ies);
+			rw = 1;
+		}
+	}
+
+	err = -EINVAL;
+	w = 1;
+	max_size >>= 2;
+	while (num_ies) {
+		if (w >= max_size) {
+			msg = "dropping long message";
+			goto bad;
+		}
+
+		data = be32_to_cpu(m->data[w++]);
+
+		if (reply_offset && !priv->mmp_20) {
+			/*
+			 * ACK each IE in the original message;
+			 * return code is always 0
+			 */
+			if ((rw << 2) >= priv->core_resp_size)
+				dev_warn(priv->dev,
+					 "Core ack buffer overflowed\n");
+			else {
+				reply[rw] = cpu_to_be32((data & ~0xffff) | 4);
+				rw++;
+				reply[rw] = cpu_to_be32(0);
+				rw++;
+			}
+		}
+		if (data & 3) {
+			msg = "IE is not a multiple of 4 bytes";
+			goto bad;
+		}
+
+		w += ((data & 0xffff) >> 2);
+
+		if (w > max_size) {
+			msg = "dropping long message";
+			goto bad;
+		}
+		num_ies--;
+	}
+	m->len = w << 2;
+
+	/* special case for lab_printf traps */
+	moca_handle_lab_printf(priv, m);
+
+	/*
+	 * Check to see if we can add this new message to the current queue.
+	 * The result will be a single message with multiple IEs.
+	 */
+	if (!priv->mmp_20) {
+		spin_lock_bh(&priv->list_lock);
+		if (!list_empty(&priv->core_msg_pend_list)) {
+			ml = priv->core_msg_pend_list.prev;
+			m = list_entry(ml, struct moca_core_msg, chain);
+
+			if (m->len + priv->core_msg_temp.len > max_size)
+				ml = NULL;
+			else {
+				u32 d0 = be32_to_cpu(
+						priv->core_msg_temp.data[0]);
+
+				/* Only concatenate traps from the core */
+				if (((be32_to_cpu(m->data[0]) & 0xff000000) !=
+					0x09000000) ||
+					((d0 & 0xff000000) != 0x09000000))
+					ml = NULL;
+				else {
+					/*
+					 * We can add the message to the
+					 * previous one. Update the num of IEs,
+					 * update the length and copy the data.
+					 */
+					data = be32_to_cpu(m->data[0]);
+					num_ies = data & 0xffff;
+					num_ies += d0 & 0xffff;
+					data &= 0xffff0000;
+					data |= num_ies;
+					m->data[0] = cpu_to_be32(data);
+
+					/*
+					 * Subtract 4 bytes from length for
+					   message header
+					 */
+					memcpy(&m->data[m->len >> 2],
+						&priv->core_msg_temp.data[1],
+						priv->core_msg_temp.len - 4);
+					m->len += priv->core_msg_temp.len - 4;
+					attach = 0;
+				}
+			}
+		}
+		spin_unlock_bh(&priv->list_lock);
+	}
+
+	if (ml == NULL) {
+		ml = moca_detach_head(priv, &priv->core_msg_free_list);
+		if (ml == NULL) {
+			msg = "no entries left on core_msg_free_list";
+			err = -ENOMEM;
+			goto bad;
+		}
+		m = list_entry(ml, struct moca_core_msg, chain);
+
+		memcpy(m->data, priv->core_msg_temp.data,
+			priv->core_msg_temp.len);
+		m->len = priv->core_msg_temp.len;
+	}
+
+	if (reply_offset) {
+		if ((cpuid == 1) &&
+			(moca_irq_status(priv, NO_FLUSH_IRQ) & M2H_ASSERT)) {
+			/* do not retry - message is gone forever */
+			err = 0;
+			msg = "core_req overwritten by assertion";
+			goto bad;
+		}
+		if ((cpuid == 0) &&
+			(moca_irq_status(priv, NO_FLUSH_IRQ)
+			& M2H_ASSERT_CPU0)) {
+			/* do not retry - message is gone forever */
+			err = 0;
+			msg = "core_req overwritten by assertion";
+			goto bad;
+		}
+		moca_write_mem(priv, reply_offset + priv->mbx_offset[cpuid],
+			reply, rw << 2);
+		moca_ringbell(priv, priv->regs->h2m_resp_bit[cpuid]);
+	}
+
+	if (attach) {
+		moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+		wake_up(&priv->core_msg_wq);
+	}
+
+	return 0;
+
+bad:
+	dev_warn(priv->dev, "%s\n", msg);
+
+	if (ml)
+		moca_attach_tail(priv, ml, &priv->core_msg_free_list);
+
+	return err;
+}
+
+static int moca_h2m_sanity_check(struct moca_priv_data *priv,
+	struct moca_host_msg *m)
+{
+	unsigned int w, num_ies;
+	u32 data;
+
+	if (priv->mmp_20) {
+		/* The length is stored in data[1]
+		   plus 8 extra header bytes */
+		data = be32_to_cpu(m->data[1]) + 8;
+		if (data > priv->host_req_size)
+			return -1;
+		else
+			return (int) data;
+	} else {
+		data = be32_to_cpu(m->data[0]);
+		num_ies = data & 0xffff;
+
+		w = 1;
+		while (num_ies) {
+			if (w >= (m->len << 2))
+				return -1;
+
+			data = be32_to_cpu(m->data[w++]);
+
+			if (data & 3)
+				return -1;
+			w += (data & 0xffff) >> 2;
+			num_ies--;
+		}
+		return w << 2;
+	}
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_sendmsg(struct moca_priv_data *priv, u32 cpuid)
+{
+	struct list_head *ml = NULL;
+	struct moca_host_msg *m;
+
+	if (priv->host_mbx_busy == 1)
+		return -1;
+
+	ml = moca_detach_head(priv, &priv->host_msg_pend_list);
+	if (ml == NULL)
+		return -EAGAIN;
+	m = list_entry(ml, struct moca_host_msg, chain);
+
+	moca_write_mem(priv, priv->mbx_offset[cpuid] + priv->host_req_offset,
+		m->data, m->len);
+
+	moca_ringbell(priv, priv->regs->h2m_req_bit[cpuid]);
+	moca_attach_tail(priv, ml, &priv->host_msg_free_list);
+	wake_up(&priv->host_msg_wq);
+
+	return 0;
+}
+
+/* Must have dev_mutex when calling this function */
+static int moca_wdt(struct moca_priv_data *priv, u32 cpu)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+
+	ml = moca_detach_head(priv, &priv->core_msg_free_list);
+	if (ml == NULL) {
+		dev_warn(priv->dev, "no entries left on core_msg_free_list\n");
+		return -ENOMEM;
+	}
+
+	if (priv->mmp_20) {
+		/*
+		 * generate phony wdt message to pass to the user
+		 * type = 0x03 (trap)
+		 * IE type = 0x11003 (wdt), 4 bytes length
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		m->data[0] = cpu_to_be32(0x3);
+		m->data[1] = cpu_to_be32(4);
+		m->data[2] = cpu_to_be32(0x11003);
+		m->len = 12;
+	} else {
+		/*
+		 * generate phony wdt message to pass to the user
+		 * type = 0x09 (trap)
+		 * IE type = 0xff01 (wdt), 4 bytes length
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		m->data[0] = cpu_to_be32(0x09000001);
+		m->data[1] = cpu_to_be32((MOCA_IE_WDT << 16) | 4);
+		m->data[2] = cpu_to_be32(cpu);
+		m->len = 12;
+	}
+
+	moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+	wake_up(&priv->core_msg_wq);
+
+	return 0;
+}
+
+static int moca_get_mbx_offset(struct moca_priv_data *priv)
+{
+	const struct moca_regs *r = priv->regs;
+	uintptr_t base;
+
+	if (priv->mbx_offset[1] == -1) {
+		if (moca_is_20(priv))
+			base = MOCA_RD(priv->base +
+				r->moca2host_mmp_inbox_0_offset) &
+				0x1fffffff;
+		else
+			base = MOCA_RD(priv->base + r->gp0_offset) &
+				0x1fffffff;
+
+		if ((base == 0) ||
+			(base >= r->cntl_mem_size + r->cntl_mem_offset) ||
+			(base & 0x07)) {
+			dev_warn(priv->dev,
+				 "can't get mailbox base CPU 1 (%X)\n",
+				 (int)base);
+			return -1;
+		}
+		priv->mbx_offset[1] = base;
+	}
+
+	if ((priv->mbx_offset[0] == -1) && moca_is_20(priv) && priv->mmp_20) {
+		base = MOCA_RD(priv->base +
+			r->moca2host_mmp_inbox_2_offset) &
+			0x1fffffff;
+		if ((base == 0) ||
+			(base >= r->cntl_mem_size + r->cntl_mem_offset) ||
+			(base & 0x07)) {
+			dev_warn(priv->dev,
+				 "can't get mailbox base CPU 0 (%X)\n",
+				 (int)base);
+			return -1;
+		}
+
+		priv->mbx_offset[0] = base;
+	}
+
+	return 0;
+}
+
+/*
+ * INTERRUPT / WORKQUEUE BH
+ */
+
+static void moca_work_handler(struct work_struct *work)
+{
+	struct moca_priv_data *priv =
+		container_of(work, struct moca_priv_data, work);
+	u32 mask = 0;
+	int ret, stopped = 0;
+
+	mutex_lock(&priv->dev_mutex);
+
+
+	if (priv->enabled) {
+		mask = moca_irq_status(priv, FLUSH_IRQ);
+
+		if (mask & M2H_DMA) {
+			mask &= ~M2H_DMA;
+			complete(&priv->copy_complete);
+		}
+
+		if (mask & M2H_NEXTCHUNK) {
+			mask &= ~M2H_NEXTCHUNK;
+			complete(&priv->chunk_complete);
+		}
+
+		if (moca_is_20(priv) && mask & M2H_NEXTCHUNK_CPU0) {
+			mask &= ~M2H_NEXTCHUNK_CPU0;
+			complete(&priv->chunk_complete);
+		}
+
+		if (mask == 0) {
+			mutex_unlock(&priv->dev_mutex);
+			moca_enable_irq(priv);
+			return;
+		}
+
+		if (mask & (M2H_REQ | M2H_RESP |
+			M2H_REQ_CPU0 | M2H_RESP_CPU0)) {
+			if (moca_get_mbx_offset(priv)) {
+				/* mbx interrupt but mbx_offset is bogus?? */
+				mutex_unlock(&priv->dev_mutex);
+				moca_enable_irq(priv);
+				return;
+			}
+		}
+	}
+
+	if (!priv->running) {
+		stopped = 1;
+	} else {
+		/* fatal events */
+		if (mask & M2H_ASSERT) {
+			ret = moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 1);
+			if (ret == -ENOMEM)
+				priv->assert_pending = ASSERT_PENDING_CPU1;
+		}
+		if (mask & M2H_ASSERT_CPU0) {
+			ret = moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 0);
+			if (ret == -ENOMEM)
+				priv->assert_pending = ASSERT_PENDING_CPU0;
+		}
+		/* M2H_WDT_CPU1 is mapped to the only CPU for MoCA11 HW */
+		if (mask & M2H_WDT_CPU1) {
+			ret = moca_wdt(priv, 2);
+			if (ret == -ENOMEM)
+				priv->wdt_pending |= BIT(1);
+			stopped = 1;
+		}
+		if (moca_is_20(priv) && mask & M2H_WDT_CPU0) {
+			ret = moca_wdt(priv, 1);
+			if (ret == -ENOMEM)
+				priv->wdt_pending |= BIT(0);
+			stopped = 1;
+		}
+	}
+	if (stopped) {
+		priv->running = 0;
+		priv->core_req_pending = 0;
+		priv->host_resp_pending = 0;
+		priv->host_mbx_busy = 1;
+		mutex_unlock(&priv->dev_mutex);
+		wake_up(&priv->core_msg_wq);
+		return;
+	}
+
+	/* normal events */
+	if (mask & M2H_REQ) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 1);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 2;
+	}
+	if (mask & M2H_RESP) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 1);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 2;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 1);
+		}
+	}
+
+	if (mask & M2H_REQ_CPU0) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 0);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 1;
+	}
+	if (mask & M2H_RESP_CPU0) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 0);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 1;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 0);
+		}
+	}
+	mutex_unlock(&priv->dev_mutex);
+
+	moca_enable_irq(priv);
+}
+
+static irqreturn_t moca_interrupt(int irq, void *arg)
+{
+	struct moca_priv_data *priv = arg;
+
+	if (1) {
+		u32 mask = moca_irq_status(priv, FLUSH_DMA_ONLY);
+
+		/* need to handle DMA completions ASAP */
+		if (mask & M2H_DMA) {
+			complete(&priv->copy_complete);
+			mask &= ~M2H_DMA;
+		}
+		if (mask & M2H_NEXTCHUNK) {
+			complete(&priv->chunk_complete);
+			mask &= ~M2H_NEXTCHUNK;
+		}
+
+		if (!mask)
+			return IRQ_HANDLED;
+	}
+	moca_disable_irq(priv);
+	schedule_work(&priv->work);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * BCM3450 ACCESS VIA I2C
+ */
+static int moca_3450_wait(struct moca_priv_data *priv)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	unsigned long time_left = jiffies + msecs_to_jiffies(50);
+
+	do {
+		if (I2C_RD(&bsc->iic_enable) & 2) {
+			I2C_WR(&bsc->iic_enable, 0);
+			return 0;
+		}
+
+		if (time_after(jiffies, time_left)) {
+			I2C_WR(&bsc->iic_enable, 0);
+			dev_warn(priv->dev, "3450 I2C timed out\n");
+			return -ETIMEDOUT;
+		}
+	} while (1);
+}
+
+static void moca_3450_write_i2c(struct moca_priv_data *priv, u8 addr, u32 data)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	I2C_WR(&bsc->iic_enable, 0);
+	I2C_WR(&bsc->chip_address, pd->bcm3450_i2c_addr << 1);
+	I2C_WR(&bsc->data_in[0], (addr >> 2) | (data << 8));
+	I2C_WR(&bsc->data_in[1], data >> 24);
+	I2C_WR(&bsc->cnt_reg, (5 << 0) | (0 << 6)); /* 5B out, 0B in */
+	I2C_WR(&bsc->ctl_reg, (1 << 4) | (0 << 0)); /* write only, 390kHz */
+	I2C_WR(&bsc->ctlhi_reg, (1 << 6));          /* 32-bit words */
+	I2C_WR(&bsc->iic_enable, 1);
+
+	moca_3450_wait(priv);
+}
+
+static u32 moca_3450_read_i2c(struct moca_priv_data *priv, u8 addr)
+{
+	struct bsc_regs *bsc = priv->i2c_base;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	I2C_WR(&bsc->iic_enable, 0);
+	I2C_WR(&bsc->chip_address, pd->bcm3450_i2c_addr << 1);
+	I2C_WR(&bsc->data_in[0], (addr >> 2));
+	I2C_WR(&bsc->cnt_reg, (1 << 0) | (4 << 6));   /* 1B out then 4B in */
+	I2C_WR(&bsc->ctl_reg, (1 << 4) | (3 << 0));   /* write/read, 390kHz */
+	I2C_WR(&bsc->ctlhi_reg, (1 << 6));	      /* 32-bit words */
+	I2C_WR(&bsc->iic_enable, 1);
+
+	if (moca_3450_wait(priv) == 0)
+		return I2C_RD(&bsc->data_out[0]);
+	else
+		return 0xffffffff;
+}
+
+#define BCM3450_CHIP_ID		0x00
+#define BCM3450_CHIP_REV	0x04
+#define BCM3450_LNACNTL		0x14
+#define BCM3450_PACNTL		0x18
+#define BCM3450_MISC		0x1c
+
+static void moca_3450_init(struct moca_priv_data *priv, int action)
+{
+	u32 data;
+
+	/* some platforms connect the i2c directly to the MoCA core */
+	if (!priv->i2c_base)
+		return;
+
+	mutex_lock(&priv->moca_i2c_mutex);
+
+	if (action == MOCA_ENABLE) {
+		/* reset the 3450's I2C block */
+		moca_3450_write(priv, BCM3450_MISC,
+			moca_3450_read(priv, BCM3450_MISC) | 1);
+
+		/* verify chip ID */
+		data = moca_3450_read(priv, BCM3450_CHIP_ID);
+		if (data != 0x3450)
+			dev_warn(priv->dev, "invalid 3450 chip ID 0x%08x\n",
+				 data);
+
+		/* reset the 3450's deserializer */
+		data = moca_3450_read(priv, BCM3450_MISC);
+		data &= ~0x8000; /* power on PA/LNA */
+		moca_3450_write(priv, BCM3450_MISC, data | 2);
+		moca_3450_write(priv, BCM3450_MISC, data & ~2);
+
+		/* set new PA gain */
+		data = moca_3450_read(priv, BCM3450_PACNTL);
+
+		moca_3450_write(priv, BCM3450_PACNTL, (data & ~0x02007ffd) |
+			(0x09 << 11) |		/* RDEG */
+			(0x38 << 5) |		/* CURR_CONT */
+			(0x05 << 2));		/* CURR_FOLLOWER */
+
+		/* Set LNACNTRL to default value */
+		moca_3450_write(priv, BCM3450_LNACNTL, 0x4924);
+
+	} else {
+		/* power down the PA/LNA */
+		data = moca_3450_read(priv, BCM3450_MISC);
+		moca_3450_write(priv, BCM3450_MISC, data | 0x8000);
+
+		data = moca_3450_read(priv, BCM3450_PACNTL);
+		moca_3450_write(priv, BCM3450_PACNTL, data |
+			BIT(0) |	/* PA_PWRDWN */
+			BIT(25));	/* PA_SELECT_PWRUP_BSC */
+
+		data = moca_3450_read(priv, BCM3450_LNACNTL);
+		/* LNA_INBIAS=0, LNA_PWRUP_IIC=0: */
+		data &= ~((7<<12) | (1<<28));
+		/* LNA_SELECT_PWRUP_IIC=1: */
+		moca_3450_write(priv, BCM3450_LNACNTL, data | (1<<29));
+
+	}
+	mutex_unlock(&priv->moca_i2c_mutex);
+}
+
+/*
+ * FILE OPERATIONS
+ */
+
+static int moca_file_open(struct inode *inode, struct file *file)
+{
+	unsigned int minor = iminor(inode);
+	struct moca_priv_data *priv;
+
+	if ((minor > NUM_MINORS) || minor_tbl[minor] == NULL)
+		return -ENODEV;
+
+	file->private_data = priv = minor_tbl[minor];
+
+	mutex_lock(&priv->dev_mutex);
+	priv->refcount++;
+	mutex_unlock(&priv->dev_mutex);
+	return 0;
+}
+
+static int moca_file_release(struct inode *inode, struct file *file)
+{
+	struct moca_priv_data *priv = file->private_data;
+
+	mutex_lock(&priv->dev_mutex);
+	priv->refcount--;
+	if (priv->refcount == 0 && priv->running == 1) {
+		/* last user closed the device */
+		moca_msg_reset(priv);
+		moca_hw_init(priv, MOCA_DISABLE);
+	}
+	mutex_unlock(&priv->dev_mutex);
+	return 0;
+}
+
+static int moca_ioctl_readmem(struct moca_priv_data *priv,
+	unsigned long xfer_uaddr)
+{
+	struct moca_xfer x;
+	uintptr_t i, src;
+	u32 *dst;
+
+	if (copy_from_user(&x, (void __user *)xfer_uaddr, sizeof(x)))
+		return -EFAULT;
+
+	if (moca_range_ok(priv, x.moca_addr, x.len) < 0)
+		return -EINVAL;
+
+	src = (uintptr_t)priv->base + x.moca_addr;
+	dst = (void *)(unsigned long)x.buf;
+
+	for (i = 0; i < x.len; i += 4, src += 4, dst++)
+		if (put_user(cpu_to_be32(MOCA_RD(src)), dst))
+			return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_writemem(struct moca_priv_data *priv,
+	unsigned long xfer_uaddr)
+{
+	struct moca_xfer x;
+	uintptr_t i, dst;
+	u32 *src;
+
+	if (copy_from_user(&x, (void __user *)xfer_uaddr, sizeof(x)))
+		return -EFAULT;
+
+	if (moca_range_ok(priv, x.moca_addr, x.len) < 0)
+		return -EINVAL;
+
+	dst = (uintptr_t)priv->base + x.moca_addr;
+	src = (void *)(unsigned long)x.buf;
+
+	for (i = 0; i < x.len; i += 4, src++, dst += 4) {
+		unsigned int x;
+		if (get_user(x, src))
+			return -EFAULT;
+
+		MOCA_WR(dst, cpu_to_be32(x));
+	}
+
+	return 0;
+}
+
+/* legacy ioctl - DEPRECATED */
+static int moca_ioctl_get_drv_info_v2(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	struct moca_kdrv_info_v2 info;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	memset(&info, 0, sizeof(info));
+	info.version = DRV_VERSION;
+	info.build_number = DRV_BUILD_NUMBER;
+	info.builtin_fw = !!bmoca_fw_image;
+
+	info.uptime = (jiffies - priv->start_time) / HZ;
+	info.refcount = priv->refcount;
+	if (moca_is_20(priv))
+		info.gp1 = priv->running ? MOCA_RD(priv->base +
+			priv->regs->moca2host_mmp_inbox_1_offset) : 0;
+	else
+		info.gp1 = priv->running ?
+			MOCA_RD(priv->base + priv->regs->gp1_offset) : 0;
+
+	memcpy(info.enet_name, pd->enet_name, MOCA_IFNAMSIZ);
+
+	info.enet_id = -1;
+	info.macaddr_hi = pd->macaddr_hi;
+	info.macaddr_lo = pd->macaddr_lo;
+	info.hw_rev = pd->chip_id;
+	info.rf_band = pd->rf_band;
+
+
+	if (copy_to_user((void *)arg, &info, sizeof(info)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_get_drv_info(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	struct moca_kdrv_info info;
+	struct moca_platform_data *pd = priv->pdev->dev.platform_data;
+
+	memset(&info, 0, sizeof(info));
+	info.version = DRV_VERSION;
+	info.build_number = DRV_BUILD_NUMBER;
+	info.builtin_fw = !!bmoca_fw_image;
+
+	info.uptime = (jiffies - priv->start_time) / HZ;
+	info.refcount = priv->refcount;
+	if (moca_is_20(priv))
+		info.gp1 = priv->running ? MOCA_RD(priv->base +
+			priv->regs->moca2host_mmp_inbox_1_offset) : 0;
+	else
+		info.gp1 = priv->running ?
+			MOCA_RD(priv->base + priv->regs->gp1_offset) : 0;
+
+	info.macaddr_hi = pd->macaddr_hi;
+	info.macaddr_lo = pd->macaddr_lo;
+	info.chip_id = pd->chip_id;
+	info.hw_rev = pd->hw_rev;
+	info.rf_band = pd->rf_band;
+	info.phy_freq = priv->phy_freq;
+
+	if (priv->enet_node) {
+		struct net_device *enet_dev;
+
+		rcu_read_lock();
+		enet_dev = of_find_net_device_by_node(priv->enet_node);
+		if (enet_dev) {
+			dev_hold(enet_dev);
+			strlcpy(info.enet_name, enet_dev->name, IFNAMSIZ);
+			dev_put(enet_dev);
+		}
+		rcu_read_unlock();
+		info.enet_id = MOCA_IFNAME_USE_ID;
+	} else {
+		strlcpy(info.enet_name, pd->enet_name, IFNAMSIZ);
+		info.enet_id = pd->enet_id;
+	}
+
+	if (copy_to_user((void *)arg, &info, sizeof(info)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int moca_ioctl_check_for_data(struct moca_priv_data *priv,
+	unsigned long arg)
+{
+	int data_avail = 0;
+	int ret;
+	u32 mask;
+
+	moca_disable_irq(priv);
+
+	moca_get_mbx_offset(priv);
+
+	/* If an IRQ is pending, process it here rather than waiting for it to
+	   ensure the results are ready. Clear the ones we are currently
+	   processing */
+	mask = moca_irq_status(priv, FLUSH_REQRESP_ONLY);
+
+	if (mask & M2H_REQ) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 1);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 2;
+	}
+	if (mask & M2H_RESP) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 1);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 2;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 1);
+		}
+	}
+
+	if (mask & M2H_REQ_CPU0) {
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+			priv->core_req_size, priv->core_resp_offset, 0);
+		if (ret == -ENOMEM)
+			priv->core_req_pending = 1;
+	}
+	if (mask & M2H_RESP_CPU0) {
+		ret = moca_recvmsg(priv, priv->host_resp_offset,
+			priv->host_resp_size, 0, 0);
+		if (ret == -ENOMEM)
+			priv->host_resp_pending = 1;
+		if (ret == 0) {
+			priv->host_mbx_busy = 0;
+			moca_sendmsg(priv, 0);
+		}
+	}
+
+	moca_enable_irq(priv);
+
+	spin_lock_bh(&priv->list_lock);
+	data_avail = !list_empty(&priv->core_msg_pend_list);
+	spin_unlock_bh(&priv->list_lock);
+
+	if (copy_to_user((void *)arg, &data_avail, sizeof(data_avail)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static long moca_file_ioctl(struct file *file, unsigned int cmd,
+	unsigned long arg)
+{
+	struct moca_priv_data *priv = file->private_data;
+	struct moca_start start;
+	long ret = -ENOTTY;
+
+	mutex_lock(&priv->dev_mutex);
+
+	switch (cmd) {
+	case MOCA_IOCTL_START:
+		ret = clk_set_rate(priv->phy_clk, DEFAULT_PHY_CLOCK);
+		/* FIXME: this fails on some platforms, so ignore the value */
+		ret = 0;
+		if (ret < 0)
+			break;
+
+		if (copy_from_user(&start, (void __user *)arg, sizeof(start)))
+			ret = -EFAULT;
+
+		if (ret >= 0) {
+			priv->bonded_mode =
+				(start.boot_flags & MOCA_BOOT_FLAGS_BONDED);
+			if (!priv->enabled) {
+				moca_msg_reset(priv);
+				moca_hw_init(priv, MOCA_ENABLE);
+				moca_3450_init(priv, MOCA_ENABLE);
+				moca_irq_status(priv, FLUSH_IRQ);
+				moca_mmp_init(priv, 0);
+			}
+
+			ret = moca_write_img(priv, &start.x);
+			if (ret >= 0)
+				priv->running = 1;
+		}
+		break;
+
+#ifdef CONFIG_PM
+	case MOCA_IOCTL_PM_SUSPEND:
+		if (priv->state == MOCA_SUSPENDING_WAITING_ACK)
+			complete(&priv->suspend_complete);
+		ret = 0;
+		break;
+#endif
+	case MOCA_IOCTL_STOP:
+		moca_msg_reset(priv);
+		moca_3450_init(priv, MOCA_DISABLE);
+		moca_hw_init(priv, MOCA_DISABLE);
+		ret = 0;
+		break;
+	case MOCA_IOCTL_READMEM:
+		if (priv->running)
+			ret = moca_ioctl_readmem(priv, arg);
+		break;
+	case MOCA_IOCTL_WRITEMEM:
+		if (priv->running)
+			ret = moca_ioctl_writemem(priv, arg);
+		break;
+	case MOCA_IOCTL_GET_DRV_INFO_V2:
+		ret = moca_ioctl_get_drv_info_v2(priv, arg);
+		break;
+	case MOCA_IOCTL_GET_DRV_INFO:
+		ret = moca_ioctl_get_drv_info(priv, arg);
+		break;
+	case MOCA_IOCTL_CHECK_FOR_DATA:
+		if (priv->running)
+			ret = moca_ioctl_check_for_data(priv, arg);
+		else
+			ret = -EIO;
+		break;
+	case MOCA_IOCTL_WOL:
+		ret = 0;
+		break;
+	case MOCA_IOCTL_SET_CPU_RATE:
+		if (!priv->cpu_clk)
+			ret = -EIO;
+		else
+			ret = clk_set_rate(priv->cpu_clk,
+						     (unsigned int)arg);
+		break;
+	case MOCA_IOCTL_SET_PHY_RATE:
+		if (!priv->phy_clk)
+			ret = -EIO;
+		else
+			ret = clk_set_rate(priv->phy_clk,
+						     (unsigned int)arg);
+		break;
+	}
+	mutex_unlock(&priv->dev_mutex);
+
+	return ret;
+}
+
+static ssize_t moca_file_read(struct file *file, char __user *buf,
+	size_t count, loff_t *ppos)
+{
+	struct moca_priv_data *priv = file->private_data;
+	DECLARE_WAITQUEUE(wait, current);
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m = NULL;
+	ssize_t ret;
+	int empty_free_list = 0;
+
+	if (count < priv->core_req_size)
+		return -EINVAL;
+
+	add_wait_queue(&priv->core_msg_wq, &wait);
+	do {
+		__set_current_state(TASK_INTERRUPTIBLE);
+
+		ml = moca_detach_head(priv, &priv->core_msg_pend_list);
+		if (ml != NULL) {
+			m = list_entry(ml, struct moca_core_msg, chain);
+			ret = 0;
+			break;
+		}
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			break;
+		}
+		if (signal_pending(current)) {
+			ret = -ERESTARTSYS;
+			break;
+		}
+		schedule();
+	} while (1);
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&priv->core_msg_wq, &wait);
+
+	if (ret < 0)
+		return ret;
+
+	if (copy_to_user(buf, m->data, m->len))
+		ret = -EFAULT;	/* beware: message will be dropped */
+	else
+		ret = m->len;
+
+	spin_lock_bh(&priv->list_lock);
+	if (list_empty(&priv->core_msg_free_list))
+		empty_free_list = 1;
+	list_add_tail(ml, &priv->core_msg_free_list);
+	spin_unlock_bh(&priv->list_lock);
+
+	if (empty_free_list) {
+		/*
+		 * we just freed up space for another message, so if there was
+		 * a backlog, clear it out
+		 */
+		mutex_lock(&priv->dev_mutex);
+
+		if (moca_get_mbx_offset(priv)) {
+			mutex_unlock(&priv->dev_mutex);
+			return -EIO;
+		}
+
+		if (priv->assert_pending & ASSERT_PENDING_CPU1) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 1) != -ENOMEM)
+				priv->assert_pending &= ~ASSERT_PENDING_CPU1;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg assert failed\n");
+		}
+		if (priv->assert_pending & 1) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, 0, 0) != -ENOMEM)
+				priv->assert_pending &= ~ASSERT_PENDING_CPU0;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg assert failed\n");
+		}
+		if (priv->wdt_pending)
+			if (moca_wdt(priv, priv->wdt_pending) != -ENOMEM)
+				priv->wdt_pending = 0;
+
+		if (priv->core_req_pending & 1) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, priv->core_resp_offset, 0)
+				!= -ENOMEM)
+				priv->core_req_pending &= ~1;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg core_req failed\n");
+		}
+		if (priv->core_req_pending & 2) {
+			if (moca_recvmsg(priv, priv->core_req_offset,
+				priv->core_req_size, priv->core_resp_offset, 1)
+				!= -ENOMEM)
+				priv->core_req_pending &= ~2;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg core_req failed\n");
+		}
+		if (priv->host_resp_pending & 1) {
+			if (moca_recvmsg(priv, priv->host_resp_offset,
+				priv->host_resp_size, 0, 0) != -ENOMEM)
+				priv->host_resp_pending &= ~1;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg host_resp failed\n");
+		}
+		if (priv->host_resp_pending & 2) {
+			if (moca_recvmsg(priv, priv->host_resp_offset,
+				priv->host_resp_size, 0, 1) != -ENOMEM)
+				priv->host_resp_pending &= ~2;
+			else
+				dev_warn(priv->dev,
+					 "moca_recvmsg host_resp failed\n");
+		}
+		mutex_unlock(&priv->dev_mutex);
+	}
+
+	return ret;
+}
+
+static ssize_t moca_file_write(struct file *file, const char __user *buf,
+	size_t count, loff_t *ppos)
+{
+	struct moca_priv_data *priv = file->private_data;
+	DECLARE_WAITQUEUE(wait, current);
+	struct list_head *ml = NULL;
+	struct moca_host_msg *m = NULL;
+	ssize_t ret;
+	u32 cpuid;
+
+	if (count > priv->host_req_size)
+		return -EINVAL;
+
+	add_wait_queue(&priv->host_msg_wq, &wait);
+	do {
+		__set_current_state(TASK_INTERRUPTIBLE);
+
+		ml = moca_detach_head(priv, &priv->host_msg_free_list);
+		if (ml != NULL) {
+			m = list_entry(ml, struct moca_host_msg, chain);
+			ret = 0;
+			break;
+		}
+		if (file->f_flags & O_NONBLOCK) {
+			ret = -EAGAIN;
+			break;
+		}
+		if (signal_pending(current)) {
+			ret = -ERESTARTSYS;
+			break;
+		}
+		schedule();
+	} while (1);
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&priv->host_msg_wq, &wait);
+
+	if (ret < 0)
+		return ret;
+
+	m->len = count;
+
+	if (copy_from_user(m->data, buf, m->len)) {
+		ret = -EFAULT;
+		goto bad;
+	}
+
+	ret = moca_h2m_sanity_check(priv, m);
+	if (ret < 0) {
+		ret = -EINVAL;
+		goto bad;
+	}
+
+	moca_attach_tail(priv, ml, &priv->host_msg_pend_list);
+
+	if (!priv->mmp_20)
+		cpuid = 1;
+	else {
+		if (cpu_to_be32(m->data[0]) & 0x10)
+			cpuid = 0;
+		else
+			cpuid = 1;
+	}
+	mutex_lock(&priv->dev_mutex);
+	if (priv->running) {
+		if (moca_get_mbx_offset(priv))
+			ret = -EIO;
+		else
+			moca_sendmsg(priv, cpuid);
+	} else
+		ret = -EIO;
+	mutex_unlock(&priv->dev_mutex);
+
+	return ret;
+
+bad:
+	moca_attach_tail(priv, ml, &priv->host_msg_free_list);
+
+	return ret;
+}
+
+static unsigned int moca_file_poll(struct file *file, poll_table *wait)
+{
+	struct moca_priv_data *priv = file->private_data;
+	unsigned int ret = 0;
+
+	poll_wait(file, &priv->core_msg_wq, wait);
+	poll_wait(file, &priv->host_msg_wq, wait);
+
+	spin_lock_bh(&priv->list_lock);
+	if (!list_empty(&priv->core_msg_pend_list))
+		ret |= POLLIN | POLLRDNORM;
+	if (!list_empty(&priv->host_msg_free_list))
+		ret |= POLLOUT | POLLWRNORM;
+	spin_unlock_bh(&priv->list_lock);
+
+	return ret;
+}
+
+static const struct file_operations moca_fops = {
+	.owner =		THIS_MODULE,
+	.open =			moca_file_open,
+	.release =		moca_file_release,
+	.unlocked_ioctl =	moca_file_ioctl,
+	.read =			moca_file_read,
+	.write =		moca_file_write,
+	.poll =			moca_file_poll,
+};
+
+/*
+ * PLATFORM DRIVER
+ */
+#ifdef CONFIG_OF
+static int moca_parse_dt_node(struct moca_priv_data *priv)
+{
+	struct platform_device *pdev = priv->pdev;
+	struct moca_platform_data pd;
+	struct device_node *of_node = pdev->dev.of_node;
+	phandle enet_ph;
+	int status = 0, i = 0;
+	const u8 *macaddr;
+	const char *rfb;
+	const char *const of_rfb[MOCA_BAND_MAX + 1] = MOCA_BAND_NAMES;
+	u32 val;
+
+	memset(&pd, 0, sizeof(pd));
+
+	/* mandatory entries */
+
+	/* get the common clocks from bmoca node */
+	priv->clk = devm_clk_get(&pdev->dev, "sw_moca");
+	if (IS_ERR(priv->clk)) {
+		dev_err(&pdev->dev,
+			"can't find sw_moca clk\n");
+		priv->clk = NULL;
+	}
+
+	priv->cpu_clk = devm_clk_get(&pdev->dev, "sw_moca_cpu");
+	if (IS_ERR(priv->cpu_clk)) {
+		dev_err(&pdev->dev,
+			"can't find moca_cpu clk\n");
+		priv->cpu_clk = NULL;
+	}
+
+	priv->phy_clk = devm_clk_get(&pdev->dev, "sw_moca_phy");
+	if (IS_ERR(priv->phy_clk)) {
+		dev_err(&pdev->dev,
+			"can't find moca_phy clk\n");
+		priv->phy_clk = NULL;
+	}
+
+	priv->wol_clk = of_clk_get_by_name(of_node, "sw_mocawol");
+	if (IS_ERR(priv->wol_clk)) {
+		dev_err(&pdev->dev,
+			"can't find mocawol clk\n");
+		priv->wol_clk = NULL;
+	}
+
+	status = of_property_read_u32(of_node, "hw-rev", &pd.hw_rev);
+	if (status)
+		goto err;
+
+	status = of_property_read_u32(of_node, "enet-id", &enet_ph);
+	if (status)
+		goto err;
+	priv->enet_node = of_find_node_by_phandle(enet_ph);
+	if (!priv->enet_node) {
+		dev_err(&pdev->dev,
+			"can't find associated network interface\n");
+		return -EINVAL;
+	}
+
+	macaddr = of_get_mac_address(of_node);
+	if (!macaddr) {
+		dev_err(&pdev->dev, "can't find MAC address\n");
+		return -EINVAL;
+	}
+
+	mac_to_u32(&pd.macaddr_hi, &pd.macaddr_lo, macaddr);
+
+	/* defaults for optional entries.  All other defaults are 0 */
+	pd.use_dma = 1;
+
+	status = of_property_read_string(of_node, "rf-band", &rfb);
+	if (!status) {
+		for (i = 0; i < MOCA_BAND_MAX; i++) {
+			if (strcmp(rfb, of_rfb[i]) == 0) {
+				pd.rf_band = i;
+				dev_info(&pdev->dev, "using %s(%d) band\n",
+					 of_rfb[i], i);
+				break;
+			}
+		}
+	}
+
+	if (status || i == MOCA_BAND_MAX) {
+		dev_warn(&pdev->dev, "Defaulting to rf-band %s\n", of_rfb[0]);
+		pd.rf_band = 0;
+	}
+
+	/* optional entries */
+	if (!of_property_read_u32(of_node, "i2c-base", &val))
+		pd.bcm3450_i2c_base = val;
+	of_property_read_u32(of_node, "i2c-addr", &pd.bcm3450_i2c_addr);
+	of_property_read_u32(of_node, "use-dma", &pd.use_dma);
+	of_property_read_u32(of_node, "use-spi", &pd.use_spi);
+
+	/* Try to read the chip-id property.  If not present, fall back to
+	 * reading it from the chip family ID register.
+	 */
+	if (of_property_read_u32(of_node, "chip-id", &pd.chip_id)) {
+		val = BDEV_RD(BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID);
+		if (val >> 28)
+			/* 4-digit chip ID */
+			pd.chip_id = (val >> 16) << 16;
+		else
+			/* 5-digit chip ID */
+			pd.chip_id = (val >> 8) << 8;
+		pd.chip_id |= (BRCM_CHIP_REV() + 0xa0);
+	}
+
+	status = platform_device_add_data(pdev, &pd, sizeof(pd));
+
+err:
+	return status;
+
+}
+
+static const struct of_device_id bmoca_instance_match[] = {
+	{ .compatible = "brcm,bmoca-instance" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(bmoca, bmoca_instance_match);
+#else
+static int moca_parse_pdata(struct moca_priv_data *priv)
+{
+
+	struct platform_device *pdev = priv->pdev;
+
+	priv->clk = clk_get(&pdev->dev, "moca");
+	priv->cpu_clk = clk_get(&pdev->dev, "moca-cpu");
+	priv->phy_clk = clk_get(&pdev->dev, "moca-phy");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PM
+
+static int moca_in_reset(struct moca_priv_data *priv)
+{
+	/*
+	 * Make sure the mocad is not stopped
+	 */
+	if (!priv || !priv->running)
+		return 1;
+
+	if (MOCA_RD(priv->base + priv->regs->sw_reset_offset)
+	    & RESET_MOCA_SYS) {
+		/*
+		 * If we lost power to the block
+		 * (e.g. unclean S3 transition)
+		 */
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Caller is assumed hold the mutex lock before changing the PM
+ * state
+ */
+static void moca_set_pm_state(struct moca_priv_data *priv,
+			      enum moca_pm_states state)
+{
+	dev_info(priv->dev, "state %s -> %s\n", moca_state_string[priv->state],
+		 moca_state_string[state]);
+	priv->state = state;
+}
+
+static int moca_send_reset_trap(struct moca_priv_data *priv)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+
+	ml = moca_detach_head(priv, &priv->core_msg_free_list);
+	if (ml == NULL) {
+		dev_warn(priv->dev, "no entries left on core_msg_free_list\n");
+		return -ENOMEM;
+	}
+
+	if (priv->mmp_20) {
+		/*
+		 * generate an IE_MOCA_RESET_REQUEST trap to the user space
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		/* trap */
+		m->data[0] = cpu_to_be32(0x3);
+		/* length 12 bytes following this word */
+		m->data[1] = cpu_to_be32(12);
+		/* group 5, IE 0x805 = IE_MOCA_RESET_REQUEST */
+		m->data[3] = cpu_to_be32(0x111); /*cause */
+
+		m->data[2] = cpu_to_be32(0x50805);
+		m->data[4] = cpu_to_be32(0); /* mr_seq_num */
+		m->len = 20;
+		moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+		wake_up(&priv->core_msg_wq);
+	}
+
+	return 0;
+}
+
+static int moca_send_pm_trap(struct moca_priv_data *priv,
+					     enum moca_pm_states state)
+{
+	struct list_head *ml = NULL;
+	struct moca_core_msg *m;
+
+	ml = moca_detach_head(priv, &priv->core_msg_free_list);
+	if (ml == NULL) {
+		dev_warn(priv->dev, "no entries left on core_msg_free_list\n");
+		return -ENOMEM;
+	}
+
+	if (priv->mmp_20) {
+		/*
+		 * generate an IE_PM_NOTIFICATION trap to the user space
+		 */
+		m = list_entry(ml, struct moca_core_msg, chain);
+		m->data[0] = cpu_to_be32(0x3);
+		m->data[1] = cpu_to_be32(8);
+		m->data[2] = cpu_to_be32(0x11014);
+		m->data[3] = cpu_to_be32(state);
+		m->len = 16;
+		moca_attach_tail(priv, ml, &priv->core_msg_pend_list);
+		wake_up(&priv->core_msg_wq);
+	}
+
+	return 0;
+}
+
+static void moca_prepare_suspend(struct moca_priv_data *priv)
+{
+	int rc;
+	long timeout = msecs_to_jiffies(MOCA_SUSPEND_TIMEOUT_MS);
+
+	mutex_lock(&priv->dev_mutex);
+	if (moca_in_reset(priv)) {
+		dev_warn(priv->dev, "MoCA core powered off\n");
+		goto out;
+	}
+
+	switch (priv->state) {
+	case MOCA_ACTIVE:
+		/*
+		 * MOCA is active is online. Set state to MOCA_SUSPENDING and
+		 * notify user space daemon to go into hostless mode
+		 */
+		rc = moca_send_pm_trap(priv, MOCA_SUSPENDING);
+		if (rc != 0)
+			goto out;
+
+		moca_set_pm_state(priv, MOCA_SUSPENDING_WAITING_ACK);
+		mutex_unlock(&priv->dev_mutex);
+		/* wait for the ACK from mocad */
+		rc = wait_for_completion_timeout(&priv->suspend_complete,
+						 timeout);
+		if (!rc)
+			dev_err(priv->dev, "suspend timeout\n");
+
+		mutex_lock(&priv->dev_mutex);
+		break;
+	default:
+		dev_warn(priv->dev, "device not in MOCA_ACTIVE state\n");
+		break;
+	}
+
+out:
+	moca_set_pm_state(priv, MOCA_SUSPENDING_GOT_ACK);
+	mutex_unlock(&priv->dev_mutex);
+}
+
+static void moca_complete_resume(struct moca_priv_data *priv)
+{
+	int rc;
+
+	mutex_lock(&priv->dev_mutex);
+
+	if (moca_in_reset(priv)) {
+		dev_warn(priv->dev, "MoCA core in reset\n");
+		goto out;
+	}
+
+	if (priv->state == MOCA_RESUMING_ASSERT) {
+		/*
+		 * There should be an assert message queued.
+		 * It doesn't matter what CPU, mocad will figure it out.
+		 */
+		int ret = moca_recvmsg(priv, priv->core_req_offset,
+				       priv->core_req_size, 0, 1);
+		if (ret == -ENOMEM)
+			priv->assert_pending = ASSERT_PENDING_CPU1;
+		ret = moca_recvmsg(priv, priv->core_req_offset,
+				   priv->core_req_size, 0, 0);
+		if (ret == -ENOMEM)
+			priv->assert_pending |= ASSERT_PENDING_CPU0;
+	}
+
+	if (priv->state != MOCA_RESUMING) {
+		dev_warn(priv->dev, "state %s should be %s\n",
+			 moca_state_string[priv->state],
+			 moca_state_string[MOCA_RESUMING]);
+		goto out;
+	}
+
+	/* Send a trap to moca firmware so that mocad resumes in host mode */
+	rc = moca_send_pm_trap(priv, MOCA_ACTIVE);
+	if (rc != 0)
+		dev_warn(priv->dev, "could not send MOCA_ACTIVE trap\n");
+
+out:
+	moca_set_pm_state(priv, MOCA_ACTIVE);
+	mutex_unlock(&priv->dev_mutex);
+}
+
+static int moca_pm_notifier(struct notifier_block *notifier,
+			     unsigned long pm_event,
+			     void *unused)
+{
+	struct moca_priv_data *priv = container_of(notifier,
+						   struct moca_priv_data,
+						   pm_notifier);
+	if (!priv->running) {
+		dev_warn(priv->dev, "%s: mocad not running\n",
+			 __func__);
+	}
+
+	switch (pm_event) {
+		dev_info(priv->dev, "%s for state %lu", __func__, pm_event);
+	case PM_HIBERNATION_PREPARE:
+	case PM_SUSPEND_PREPARE:
+		moca_prepare_suspend(priv);
+		break;
+	case PM_POST_HIBERNATION:
+	case PM_POST_SUSPEND:
+	case PM_POST_RESTORE:
+		moca_complete_resume(priv);
+		break;
+	case PM_RESTORE_PREPARE:
+		break;
+	default:
+		break;
+	}
+	return NOTIFY_DONE;
+}
+
+static int moca_register_pm_notifier(struct moca_priv_data *priv)
+{
+	priv->pm_notifier.notifier_call = moca_pm_notifier;
+	return register_pm_notifier(&priv->pm_notifier);
+}
+
+static int moca_unregister_pm_notifier(struct moca_priv_data *priv)
+{
+	return unregister_pm_notifier(&priv->pm_notifier);
+}
+#else
+
+static inline void moca_set_pm_state(struct moca_priv_data *priv,
+				     enum moca_pm_states state)
+{
+}
+
+#endif /* CONFIG_PM */
+
+static irqreturn_t moca_wol_isr(int irq, void *dev_id)
+{
+	struct moca_priv_data *priv = dev_id;
+
+	/* get status reg and log */
+	u32 stat = moca_irq_status(priv, FLUSH_WOL_ONLY);
+	u32 assert_code_in = 0;
+	if (moca_is_20(priv))
+		assert_code_in = MOCA_RD(priv->base +
+				    priv->regs->extras_mmp_outbox_3_offset);
+
+	/* Assert takes precedence over Watchdog, takes precedence over WoL */
+	if (((stat & M2H_WOL) && assert_code_in != 0)
+	    || (stat & (M2H_ASSERT | M2H_ASSERT_CPU0))) {
+		dev_dbg(priv->dev, "ASSERT %x!\n", assert_code_in);
+		moca_set_pm_state(priv, MOCA_RESUMING_ASSERT);
+	} else if (stat & M2H_WOL) {
+		dev_dbg(priv->dev, "WOL!\n");
+	}
+
+	if (stat & (M2H_WDT_CPU1 | M2H_WDT_CPU0)) {
+		dev_dbg(priv->dev, "WATCHDOG!\n");
+		moca_set_pm_state(priv, MOCA_RESUMING_WDOG);
+	}
+
+	pm_wakeup_event(&priv->pdev->dev, 0);
+
+	return IRQ_HANDLED;
+}
+
+static int moca_probe(struct platform_device *pdev)
+{
+	struct moca_priv_data *priv;
+	struct resource *mres;
+	int minor, err;
+	struct moca_platform_data *pd;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(&pdev->dev, "out of memory\n");
+		return -ENOMEM;
+	}
+	dev_set_drvdata(&pdev->dev, priv);
+	priv->pdev = pdev;
+	priv->start_time = jiffies;
+
+#if defined(CONFIG_OF)
+	err = moca_parse_dt_node(priv);
+#else
+	err = moca_parse_pdata(priv);
+	if (err)
+		return err;
+#endif
+	pd = pdev->dev.platform_data;
+	priv->hw_rev = pd->hw_rev;
+
+	if (pd->hw_rev == HWREV_MOCA_11_PLUS)
+		priv->regs = &regs_11_plus;
+	else if (pd->hw_rev == HWREV_MOCA_11_LITE)
+		priv->regs = &regs_11_lite;
+	else if (pd->hw_rev == HWREV_MOCA_11)
+		priv->regs = &regs_11;
+	else if ((pd->hw_rev == HWREV_MOCA_20_ALT) ||
+		(pd->hw_rev == HWREV_MOCA_20_GEN21) ||
+		(pd->hw_rev == HWREV_MOCA_20_GEN22) ||
+		(pd->hw_rev == HWREV_MOCA_20_GEN23))
+		priv->regs = &regs_20;
+	else if (pd->hw_rev == HWREV_MOCA_20_GEN24)
+		priv->regs = &regs_20_gen4;
+	else {
+		dev_err(&pdev->dev, "unsupported MoCA HWREV: %x\n",
+			pd->hw_rev);
+		return -EINVAL;
+	}
+
+	init_waitqueue_head(&priv->host_msg_wq);
+	init_waitqueue_head(&priv->core_msg_wq);
+	init_completion(&priv->copy_complete);
+	init_completion(&priv->chunk_complete);
+	init_completion(&priv->suspend_complete);
+
+	spin_lock_init(&priv->list_lock);
+	spin_lock_init(&priv->clock_lock);
+	spin_lock_init(&priv->irq_status_lock);
+
+	mutex_init(&priv->dev_mutex);
+	mutex_init(&priv->copy_mutex);
+	mutex_init(&priv->moca_i2c_mutex);
+
+	sg_init_table(priv->fw_sg, MAX_FW_PAGES);
+
+	INIT_WORK(&priv->work, moca_work_handler);
+
+	priv->minor = -1;
+	for (minor = 0; minor < NUM_MINORS; minor++) {
+		if (minor_tbl[minor] == NULL) {
+			priv->minor = minor;
+			break;
+		}
+	}
+
+	if (priv->minor == -1) {
+		dev_err(&pdev->dev, "can't allocate minor device\n");
+		return -EIO;
+	}
+
+	mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, mres);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "can't get IRQ\n");
+		return -EIO;
+	}
+
+	priv->wol_irq = platform_get_irq(pdev, 1);
+	if (priv->wol_irq < 0)
+		dev_err(&pdev->dev, "can't find IRQs\n");
+
+	if (pd->bcm3450_i2c_base)
+		priv->i2c_base = devm_ioremap(&pdev->dev, pd->bcm3450_i2c_base,
+					      sizeof(struct bsc_regs));
+
+	/* leave core in reset until we get an ioctl */
+	moca_hw_reset(priv);
+
+	if (request_irq(priv->irq, moca_interrupt, 0, "moca",
+			priv) < 0) {
+		dev_err(&pdev->dev, "can't request interrupt\n");
+		return -EIO;
+	}
+
+	/* Request the WOL interrupt line and advertise suspend if available */
+	err = devm_request_irq(&pdev->dev, priv->wol_irq, moca_wol_isr, 0,
+			       "mocawol", priv);
+	if (!err && !(priv->wol_irq < 0)) {
+		device_set_wakeup_capable(&pdev->dev, 1);
+		device_set_wakeup_enable(&priv->pdev->dev, 1);
+		enable_irq_wake(priv->wol_irq);
+	}
+
+	moca_hw_init(priv, MOCA_ENABLE);
+	moca_disable_irq(priv);
+	moca_msg_reset(priv);
+	moca_hw_init(priv, MOCA_DISABLE);
+
+	dev_info(&pdev->dev, "minor #%d %pR irq %d\n",
+		 priv->minor, mres, priv->irq);
+	if (pd->bcm3450_i2c_base) {
+		dev_info(&pdev->dev, "I2C %pa/0x%02x\n",
+			 &pd->bcm3450_i2c_base, pd->bcm3450_i2c_addr);
+	}
+
+	minor_tbl[priv->minor] = priv;
+	priv->dev = device_create(moca_class, NULL,
+		MKDEV(MOCA_MAJOR, priv->minor), NULL, "bmoca%d", priv->minor);
+	if (IS_ERR(priv->dev)) {
+		dev_warn(&pdev->dev, "can't register class device\n");
+		priv->dev = NULL;
+	}
+
+#ifdef CONFIG_PM
+	err = moca_register_pm_notifier(priv);
+	if (err) {
+		dev_err(&pdev->dev, "register_pm_notifier failed err %d\n",
+			err);
+		return err;
+	}
+#endif
+
+	return 0;
+}
+
+static int moca_remove(struct platform_device *pdev)
+{
+	struct moca_priv_data *priv = dev_get_drvdata(&pdev->dev);
+	int err = 0;
+
+	if (priv->dev)
+		device_destroy(moca_class, MKDEV(MOCA_MAJOR, priv->minor));
+	minor_tbl[priv->minor] = NULL;
+
+#ifdef CONFIG_PM
+	err = moca_unregister_pm_notifier(priv);
+	if (err) {
+		dev_err(&pdev->dev, "unregister_pm_notifier failed err %d\n",
+			err);
+	}
+#endif
+
+	return err;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int moca_suspend(struct device *dev)
+{
+	int minor;
+	for (minor = 0; minor < NUM_MINORS; minor++) {
+		struct moca_priv_data *priv = minor_tbl[minor];
+		if (priv && priv->enabled) {
+			mutex_lock(&priv->dev_mutex);
+
+			/* check if either moca core in reset or
+			 * mocad has been killed
+			 */
+			if (moca_in_reset(priv)) {
+				moca_set_pm_state(priv, MOCA_SUSPENDED);
+				mutex_unlock(&priv->dev_mutex);
+				return 0;
+			}
+
+			switch (priv->state) {
+			case MOCA_SUSPENDING_GOT_ACK:
+				moca_set_pm_state(priv, MOCA_SUSPENDED);
+				break;
+
+			case MOCA_SUSPENDING:
+			case MOCA_SUSPENDING_WAITING_ACK:
+			default:
+				dev_warn(priv->dev, "state %s should be %s\n",
+				 moca_state_string[priv->state],
+				 moca_state_string[MOCA_SUSPENDING_GOT_ACK]);
+			}
+			mutex_unlock(&priv->dev_mutex);
+		}
+	}
+	return 0;
+}
+
+static int moca_resume(struct device *dev)
+{
+	int minor;
+	int rc;
+
+	for (minor = 0; minor < NUM_MINORS; minor++) {
+		struct moca_priv_data *priv = minor_tbl[minor];
+
+		if (priv && priv->enabled) {
+			if (priv->state != MOCA_RESUMING_WDOG
+			    && moca_in_reset(priv)) {
+				/*
+				 * If we lost power to the block
+				 * (e.g. unclean S3 transition), but
+				 * the driver still thinks the core is
+				 * enabled, try to get things back in
+				 * sync.
+				 */
+				priv->enabled = 0;
+				dev_warn(priv->dev, "S3 : sending moca reset\n");
+				moca_msg_reset(priv);
+				rc = moca_send_reset_trap(priv);
+				if (rc)
+					dev_dbg(priv->dev,
+						"S3 : moca reset failed\n");
+			}
+
+			mutex_lock(&priv->dev_mutex);
+			if (priv->state != MOCA_SUSPENDED)
+				dev_warn(priv->dev, "state %s should be %s\n",
+					 moca_state_string[priv->state],
+					 moca_state_string[MOCA_SUSPENDED]);
+
+			if (priv->state != MOCA_RESUMING_ASSERT
+			    && priv->state != MOCA_RESUMING_WDOG)
+				moca_set_pm_state(priv, MOCA_RESUMING);
+			mutex_unlock(&priv->dev_mutex);
+		}
+	}
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(moca_pm_ops, moca_suspend, moca_resume);
+
+static struct platform_driver moca_plat_drv = {
+	.probe =		moca_probe,
+	.remove =		moca_remove,
+	.driver = {
+		.name =		"bmoca",
+		.owner =	THIS_MODULE,
+		.pm =		&moca_pm_ops,
+		.of_match_table = of_match_ptr(bmoca_instance_match),
+	},
+};
+
+static int moca_init(void)
+{
+	int ret;
+	memset(minor_tbl, 0, sizeof(minor_tbl));
+	ret = register_chrdev(MOCA_MAJOR, MOCA_CLASS, &moca_fops);
+	if (ret < 0) {
+		pr_err("can't register major %d\n", MOCA_MAJOR);
+		goto bad;
+	}
+
+	moca_class = class_create(THIS_MODULE, MOCA_CLASS);
+	if (IS_ERR(moca_class)) {
+		pr_err("can't create device class\n");
+		ret = PTR_ERR(moca_class);
+		goto bad2;
+	}
+
+	ret = platform_driver_register(&moca_plat_drv);
+	if (ret < 0) {
+		pr_err("can't register platform_driver\n");
+		goto bad3;
+	}
+
+
+
+	return 0;
+
+bad3:
+	class_destroy(moca_class);
+bad2:
+	unregister_chrdev(MOCA_MAJOR, MOCA_CLASS);
+bad:
+	return ret;
+}
+
+static void moca_exit(void)
+{
+	platform_driver_unregister(&moca_plat_drv);
+	class_destroy(moca_class);
+	unregister_chrdev(MOCA_MAJOR, MOCA_CLASS);
+}
+
+module_init(moca_init);
+module_exit(moca_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("MoCA messaging driver");
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a367a9831717..9f9e1d8ad646 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-divider.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-gate.o
+obj-$(CONFIG_COMMON_CLK)	+= clk-multiplier.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-mux.o
 obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 
@@ -13,6 +14,7 @@ obj-$(CONFIG_COMMON_CLK)	+= clk-composite.o
 # please keep this section sorted lexicographically by file/directory path name
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
 obj-$(CONFIG_ARCH_BCM2835)		+= clk-bcm2835.o
+obj-$(CONFIG_ARCH_BRCMSTB)		+= clk-brcmstb.o
 obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
 obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
 obj-$(CONFIG_MACH_LOONGSON1)		+= clk-ls1x.o
diff --git a/drivers/clk/clk-brcmstb.c b/drivers/clk/clk-brcmstb.c
new file mode 100644
index 000000000000..eede1f5a3005
--- /dev/null
+++ b/drivers/clk/clk-brcmstb.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt) "clk-brcmstb: " fmt
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/syscore_ops.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/clk/clk-brcmstb.h>
+
+static bool shut_off_unused_clks = true;
+static int bcm_full_clk = 2;
+static void __iomem *cpu_clk_div_reg;
+
+struct bcm_clk_gate {
+	struct clk_hw hw;
+	void __iomem *reg;
+	u8 bit_idx;
+	u8 flags;
+	u32 delay[2];
+	spinlock_t *lock;
+	struct clk_ops ops;
+};
+
+struct bcm_clk_sw {
+	struct clk_hw hw;
+	struct clk_ops ops;
+};
+
+#define to_brcmstb_clk_gate(p) container_of(p, struct bcm_clk_gate, hw)
+#define to_brcmstb_clk_sw(p) container_of(p, struct bcm_clk_sw, hw)
+
+static DEFINE_SPINLOCK(lock);
+
+static int cpu_clk_div_pos __initdata;
+static int cpu_clk_div_width __initdata;
+
+static int __init parse_cpu_clk_div_dimensions(struct device_node *np)
+{
+	struct property *prop;
+	const __be32 *p = NULL;
+	int len;
+	int elem_cnt;
+	const char *propname = "div-shift-width";
+
+	prop = of_find_property(np, propname, &len);
+	if (!prop) {
+		pr_err("%s property undefined\n", propname);
+		return -EINVAL;
+	}
+
+	elem_cnt = len / sizeof(u32);
+
+	if (elem_cnt != 2) {
+		pr_err("%s should have only 2 elements\n", propname);
+		return -EINVAL;
+	}
+
+	p = of_prop_next_u32(prop, p, &cpu_clk_div_pos);
+	of_prop_next_u32(prop, p, &cpu_clk_div_width);
+
+	return 0;
+}
+
+static struct clk_div_table *cpu_clk_div_table;
+
+static int __init parse_cpu_clk_div_table(struct device_node *np)
+{
+	struct property *prop;
+	const __be32 *p = NULL;
+	struct clk_div_table *cur_tbl_ptr;
+	int len;
+	int elem_cnt;
+	int i;
+	const char *propname = "div-table";
+
+	prop = of_find_property(np, propname, &len);
+	if (!prop) {
+		pr_err("%s property undefined\n", propname);
+		return -EINVAL;
+	}
+
+	elem_cnt = len / sizeof(u32);
+
+	if (elem_cnt < 2) {
+		pr_err("%s should have at least 2 elements\n", propname);
+		return -EINVAL;
+	}
+
+	if ((elem_cnt % 2) != 0) {
+		pr_err("%s should have even number of elements\n", propname);
+		return -EINVAL;
+	}
+
+	/* need room for last sentinel entry */
+	len += 2 * sizeof(u32);
+
+	cpu_clk_div_table = kmalloc(len, GFP_KERNEL);
+	if (!cpu_clk_div_table)
+		return -ENOMEM;
+
+	cur_tbl_ptr = cpu_clk_div_table;
+
+	for (i = 0; i < elem_cnt; i += 2) {
+		p = of_prop_next_u32(prop, p, &cur_tbl_ptr->val);
+		p = of_prop_next_u32(prop, p, &cur_tbl_ptr->div);
+
+		cur_tbl_ptr++;
+	}
+
+	/* last entry should be zeroed out */
+	cur_tbl_ptr->val = 0;
+	cur_tbl_ptr->div = 0;
+
+	return 0;
+}
+
+static void __init cpu_clk_div_setup(struct device_node *np)
+{
+	struct clk *clk;
+	int rc;
+
+	cpu_clk_div_reg = of_iomap(np, 0);
+	if (!cpu_clk_div_reg) {
+		pr_err("unable to iomap cpu clk divider register!\n");
+		return;
+	}
+
+	rc = parse_cpu_clk_div_dimensions(np);
+	if (rc)
+		goto err;
+
+	rc = parse_cpu_clk_div_table(np);
+	if (rc)
+		goto err;
+
+	clk = clk_register_divider_table(NULL, "cpu-clk-div",
+					 of_clk_get_parent_name(np, 0), 0,
+					 cpu_clk_div_reg,
+					 cpu_clk_div_pos, cpu_clk_div_width,
+					 0, cpu_clk_div_table, &lock);
+	if (IS_ERR(clk))
+		goto err;
+
+	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
+	if (rc) {
+		pr_err("error adding clock provider (%d)\n", rc);
+		goto err;
+	}
+
+	return;
+
+err:
+	kfree(cpu_clk_div_table);
+	cpu_clk_div_table = NULL;
+
+	if (cpu_clk_div_reg)
+		iounmap(cpu_clk_div_reg);
+}
+
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ *	set2dis = 1	-> clear bit	-> set = 0
+ *	set2dis = 0	-> set bit	-> set = 1
+ *
+ * For disabling clock, enable = 0
+ *	set2dis = 1	-> set bit	-> set = 1
+ *	set2dis = 0	-> clear bit	-> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void brcmstb_clk_gate_endisable(struct clk_hw *hw, int enable)
+{
+	struct bcm_clk_gate *gate = to_brcmstb_clk_gate(hw);
+	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+	unsigned long flags = 0;
+	u32 reg;
+
+	set ^= enable;
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+
+	if (set)
+		reg |= BIT(gate->bit_idx);
+	else
+		reg &= ~BIT(gate->bit_idx);
+
+	writel(reg, gate->reg);
+
+	if (set == 0 && gate->delay[0])
+		udelay(gate->delay[0]);
+	else if (set == 1 && gate->delay[1])
+		udelay(gate->delay[1]);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int brcmstb_clk_gate_enable(struct clk_hw *hw)
+{
+	brcmstb_clk_gate_endisable(hw, 1);
+	return 0;
+}
+
+static void brcmstb_clk_gate_disable(struct clk_hw *hw)
+{
+	brcmstb_clk_gate_endisable(hw, 0);
+}
+
+static int brcmstb_clk_gate_is_enabled(struct clk_hw *hw)
+{
+	u32 reg;
+	struct bcm_clk_gate *gate = to_brcmstb_clk_gate(hw);
+
+	reg = readl(gate->reg);
+
+	/* if a set bit disables this clk, flip it before masking */
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		reg ^= BIT(gate->bit_idx);
+
+	reg &= BIT(gate->bit_idx);
+	return reg ? 1 : 0;
+}
+
+static const struct clk_ops brcmstb_clk_gate_ops = {
+	.enable = brcmstb_clk_gate_enable,
+	.disable = brcmstb_clk_gate_disable,
+	.is_enabled = brcmstb_clk_gate_is_enabled,
+};
+
+static const struct clk_ops brcmstb_clk_gate_inhib_dis_ops = {
+	.enable = brcmstb_clk_gate_enable,
+	.is_enabled = brcmstb_clk_gate_is_enabled,
+};
+
+static const struct clk_ops brcmstb_clk_gate_ro_ops = {
+	.is_enabled = brcmstb_clk_gate_is_enabled,
+};
+
+/**
+ * brcm_clk_gate_register - register a bcm gate clock with the clock framework.
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of this clock's parent
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @delay: usec delay in turning on, off.
+ * @lock: shared register lock for this clock
+ */
+static struct clk __init *brcm_clk_gate_register(
+	struct device *dev, const char *name, const char *parent_name,
+	unsigned long flags, void __iomem *reg, u8 bit_idx,
+	u8 clk_gate_flags, u32 delay[2], spinlock_t *lock,
+	bool read_only, bool inhibit_disable)
+{
+	struct bcm_clk_gate *gate;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the gate */
+	gate = kzalloc(sizeof(struct bcm_clk_gate), GFP_KERNEL);
+	if (!gate) {
+		pr_err("%s: could not allocate bcm gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = inhibit_disable ? &brcmstb_clk_gate_inhib_dis_ops
+		: read_only ? &brcmstb_clk_gate_ro_ops : &brcmstb_clk_gate_ops;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+	init.flags = flags | (parent_name ? 0 : CLK_IS_ROOT);
+	if (!shut_off_unused_clks)
+		init.flags |= CLK_IGNORE_UNUSED; /* FIXME */
+
+	/* struct bcm_gate assignments */
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+	gate->delay[0] = delay[0];
+	gate->delay[1] = delay[1];
+	gate->hw.init = &init;
+
+	clk = clk_register(dev, &gate->hw);
+
+	if (IS_ERR(clk))
+		kfree(gate);
+
+	return clk;
+}
+
+static const struct clk_ops brcmstb_clk_sw_ops = {};
+
+/**
+ * brcmstb_clk_sw_register - register a bcm gate clock with the clock framework.
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parents: name of this clock's parents; not known by clock framework
+ * @num_parents: number of parents
+ * @flags: framework-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+static struct clk __init *brcmstb_clk_sw_register(
+	struct device *dev, const char *name, const char **parent_names,
+	int num_parents, unsigned long flags, spinlock_t *lock)
+{
+	struct bcm_clk_sw *sw_clk;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the gate */
+	sw_clk = kzalloc(sizeof(struct bcm_clk_sw), GFP_KERNEL);
+	if (!sw_clk) {
+		pr_err("%s: could not allocate bcm sw clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &brcmstb_clk_sw_ops;
+	init.parent_names = parent_names;
+	init.num_parents = num_parents;
+	init.flags = flags | CLK_IS_BASIC | CLK_IS_SW;
+	if (!shut_off_unused_clks)
+		init.flags |= CLK_IGNORE_UNUSED; /* FIXME */
+
+	sw_clk->hw.init = &init;
+	clk = clk_register(dev, &sw_clk->hw);
+	if (IS_ERR(clk))
+		kfree(sw_clk);
+	return clk;
+}
+
+/**
+ * of_brcmstb_gate_clk_setup() - Setup function for brcmstb gate clock
+ */
+static void __init of_brcmstb_clk_gate_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+	u8 clk_gate_flags = 0;
+	u32 bit_idx = 0;
+	u32 delay[2] = {0, 0};
+	int ret;
+	bool read_only = false;
+	bool inhibit_disable = false;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent_name = of_clk_get_parent_name(node, 0);
+	if (of_property_read_u32(node, "bit-shift", &bit_idx)) {
+		pr_err("%s: missing bit-shift property for %s\n",
+				__func__, node->name);
+		return;
+	}
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("unable to iomap cpu clk divider register!\n");
+		return;
+	}
+
+	of_property_read_u32_array(node, "brcm,delay", delay, 2);
+
+	if (of_property_read_bool(node, "set-bit-to-disable"))
+		clk_gate_flags |= CLK_GATE_SET_TO_DISABLE;
+
+	if (of_property_read_bool(node, "brcm,read-only"))
+		read_only = true;
+
+	if (of_property_read_bool(node, "brcm,inhibit-disable"))
+		inhibit_disable = true;
+
+	clk = brcm_clk_gate_register(NULL, clk_name, parent_name, 0, reg,
+				     (u8) bit_idx, clk_gate_flags, delay,
+				     &lock, read_only, inhibit_disable);
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		ret = clk_register_clkdev(clk, clk_name, NULL);
+		if (ret)
+			pr_err("%s: clk device registration failed for '%s'\n",
+			       __func__, clk_name);
+	}
+}
+
+static void __init of_brcmstb_clk_sw_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	int num_parents;
+	const char **parent_names;
+	int ret, i;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	num_parents = of_property_count_strings(node, "clock-names");
+	if (num_parents < 1) {
+		pr_err("%s: brcm-sw-clock %s must have parent(s)\n",
+				__func__, node->name);
+		return;
+	}
+	parent_names = kzalloc((sizeof(char *) * num_parents),
+			GFP_KERNEL);
+	if (!parent_names) {
+		pr_err("%s: failed to alloc parent_names\n", __func__);
+		return;
+	}
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	clk = brcmstb_clk_sw_register(NULL, clk_name, parent_names, num_parents,
+				   0, NULL);
+	kfree(parent_names);
+
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+		ret = clk_register_clkdev(clk, clk_name, NULL);
+		if (ret)
+			pr_err("%s: clk device registration failed for '%s'\n",
+			       __func__, clk_name);
+	}
+}
+
+
+static int __init _bcm_full_clk(char *str)
+{
+	get_option(&str, &bcm_full_clk);
+	shut_off_unused_clks = bcm_full_clk > 1;
+	return 0;
+}
+
+early_param("bcm_full_clk", _bcm_full_clk);
+
+static const struct of_device_id brcmstb_clk_match[] __initconst = {
+	{ .compatible = "fixed-clock",
+	  .data = of_fixed_clk_setup, },
+	{ .compatible = "brcm,brcmstb-cpu-clk-div",
+	  .data = cpu_clk_div_setup, },
+	{}
+};
+
+static const struct of_device_id brcmstb_clk_match_full[] __initconst = {
+	{ .compatible = "brcm,brcmstb-gate-clk",
+	  .data = of_brcmstb_clk_gate_setup, },
+	{ .compatible = "brcm,brcmstb-sw-clk",
+	  .data = of_brcmstb_clk_sw_setup, },
+	{ .compatible = "brcm,brcmstb-cpu-clk-div",
+	  .data = cpu_clk_div_setup, },
+	{ .compatible = "fixed-clock",
+	  .data = of_fixed_clk_setup, },
+	{ .compatible = "fixed-factor-clock",
+	  .data = of_fixed_factor_clk_setup, },
+	{ .compatible = "divider-clock",
+	  .data = of_divider_clk_setup, },
+	{ .compatible = "multiplier-clock",
+	  .data = of_multiplier_clk_setup, },
+	{}
+};
+
+#ifdef CONFIG_PM_SLEEP
+static u32 cpu_clk_div_reg_dump;
+
+static int brcmstb_clk_suspend(void)
+{
+	if (cpu_clk_div_reg)
+		cpu_clk_div_reg_dump = __raw_readl(cpu_clk_div_reg);
+	return 0;
+}
+
+static void brcmstb_clk_resume(void)
+{
+	if (cpu_clk_div_reg)
+		__raw_writel(cpu_clk_div_reg_dump, cpu_clk_div_reg);
+}
+
+static struct syscore_ops brcmstb_clk_syscore_ops = {
+	.suspend = brcmstb_clk_suspend,
+	.resume = brcmstb_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+void __init brcmstb_clocks_init(void)
+{
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&brcmstb_clk_syscore_ops);
+#endif
+	/* DT-based clock config */
+	of_clk_init(bcm_full_clk ? brcmstb_clk_match_full : brcmstb_clk_match);
+}
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 5543b7df8e16..8297a5b80354 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -17,6 +17,8 @@
 #include <linux/err.h>
 #include <linux/string.h>
 #include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 /*
  * DOC: basic adjustable divider clock that cannot gate
@@ -71,6 +73,8 @@ static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
 		return val;
 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 		return 1 << val;
+	if (divider->flags & CLK_DIVIDER_MAX_AT_ZERO)
+		return val ? val : div_mask(divider) + 1;
 	if (divider->table)
 		return _get_table_div(divider->table, val);
 	return val + 1;
@@ -93,6 +97,9 @@ static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
 		return div;
 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
 		return __ffs(div);
+	if (divider->flags & CLK_DIVIDER_MAX_AT_ZERO)
+		return (div == div_mask(divider) + 1)
+			? 0 : div;
 	if (divider->table)
 		return  _get_table_val(divider->table, div);
 	return div - 1;
@@ -159,7 +166,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 
 	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
 		parent_rate = *best_parent_rate;
-		bestdiv = DIV_ROUND_UP(parent_rate, rate);
+		bestdiv = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 		bestdiv = bestdiv == 0 ? 1 : bestdiv;
 		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
 		return bestdiv;
@@ -343,3 +350,107 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
 			width, clk_divider_flags, table, lock);
 }
 EXPORT_SYMBOL_GPL(clk_register_divider_table);
+
+#ifdef CONFIG_OF
+static struct clk_div_table *of_clk_get_div_table(struct device_node *node)
+{
+	int i;
+	unsigned int table_size;
+	struct clk_div_table *table;
+	const __be32 *tablespec;
+	u32 val;
+
+	tablespec = of_get_property(node, "table", (int *) &table_size);
+
+	if (!tablespec)
+		return NULL;
+
+	table_size /= sizeof(struct clk_div_table);
+
+	table = kzalloc(sizeof(struct clk_div_table) * table_size, GFP_KERNEL);
+	if (!table) {
+		pr_err("%s: unable to allocate memory for %s table\n", __func__,
+		       node->name);
+		return NULL;
+	}
+
+	for (i = 0; i < table_size; i++) {
+		of_property_read_u32_index(node, "table", i * 2, &val);
+		table[i].div = val;
+		of_property_read_u32_index(node, "table", i * 2 + 1, &val);
+		table[i].val = val;
+	}
+
+	return table;
+}
+
+/**
+ * of_divider_clk_setup() - Setup function for simple div rate clock
+ */
+void of_divider_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+	u8 clk_divider_flags = 0;
+	u32 mask = 0;
+	u32 shift = 0;
+	u32 width;
+	struct clk_div_table *table;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s: no memory mapped for property reg\n", __func__);
+		return;
+	}
+
+	if (of_property_read_u32(node, "bit-mask", &mask)) {
+		pr_err("%s: missing bit-mask property for %s\n", __func__,
+		       node->name);
+		return;
+	}
+	width = fls(mask);
+	if ((1 << width) - 1 != mask) {
+		pr_err("%s: bad bit-mask for %s\n", __func__, node->name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "bit-shift", &shift)) {
+		shift = __ffs(mask);
+		pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+				__func__, shift, node->name);
+	}
+
+	if (of_property_read_bool(node, "index-starts-at-one"))
+		clk_divider_flags |= CLK_DIVIDER_ONE_BASED;
+
+	if (of_property_read_bool(node, "index-power-of-two"))
+		clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+	if (of_property_read_bool(node, "index-allow-zero"))
+		clk_divider_flags |= CLK_DIVIDER_ALLOW_ZERO;
+
+	if (of_property_read_bool(node, "index-max-at-zero"))
+		clk_divider_flags |= CLK_DIVIDER_MAX_AT_ZERO;
+
+	if (of_property_read_bool(node, "hiword-mask"))
+		clk_divider_flags |= CLK_DIVIDER_HIWORD_MASK;
+
+	table = of_clk_get_div_table(node);
+	if (IS_ERR(table))
+		return;
+
+	clk = _register_divider(NULL, clk_name, parent_name, 0, reg, shift,
+			width, clk_divider_flags, table, NULL);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+EXPORT_SYMBOL_GPL(of_divider_clk_setup);
+CLK_OF_DECLARE(divider_clk, "divider-clock", of_divider_clk_setup);
+#endif
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
new file mode 100644
index 000000000000..e7b452d430fc
--- /dev/null
+++ b/drivers/clk/clk-multiplier.c
@@ -0,0 +1,550 @@
+/*
+ * Copyright (C) 2015 Jim Quinlan, Broadcom <jim2101024@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable multiplier clock implementation.  This is essentially
+ * the mirror of clk-divider.c.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/log2.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+/*
+ * DOC: basic adjustable multiplier clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = (parent->rate * multiplier)
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
+
+#define mult_mask(width)	((1 << (width)) - 1)
+
+static unsigned int _get_table_minmult(const struct clk_mult_table *table)
+{
+	unsigned int minmult = UINT_MAX;
+	const struct clk_mult_table *clkt;
+
+	for (clkt = table; clkt->mult; clkt++)
+		if (clkt->mult < minmult)
+			minmult = clkt->mult;
+	return minmult;
+}
+
+static unsigned int _get_table_maxmult(const struct clk_mult_table *table)
+{
+	unsigned int maxmult = 0;
+	const struct clk_mult_table *clkt;
+
+	for (clkt = table; clkt->mult; clkt++)
+		if (clkt->mult > maxmult)
+			maxmult = clkt->mult;
+	return maxmult;
+}
+
+static unsigned int _get_minmult(const struct clk_mult_table *table)
+{
+	if (table)
+		return _get_table_minmult(table);
+	return 1;
+}
+
+static unsigned int _get_maxmult(const struct clk_mult_table *table, u8 width,
+				unsigned long flags)
+{
+	if (flags & CLK_MULTIPLIER_ONE_BASED)
+		return mult_mask(width);
+	if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+		return 1 << mult_mask(width);
+	if (table)
+		return _get_table_maxmult(table);
+	return mult_mask(width) + 1;
+}
+
+static unsigned int _get_table_mult(const struct clk_mult_table *table,
+							unsigned int val)
+{
+	const struct clk_mult_table *clkt;
+
+	for (clkt = table; clkt->mult; clkt++)
+		if (clkt->val == val)
+			return clkt->mult;
+	return 0;
+}
+
+static unsigned int _get_mult(const struct clk_mult_table *table,
+			      u8 width, unsigned int val, unsigned long flags)
+{
+	if (flags & CLK_MULTIPLIER_ONE_BASED)
+		return val;
+	if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+		return 1 << val;
+	if (flags & CLK_MULTIPLIER_MAX_MULT_AT_ZERO)
+		return val ? val : mult_mask(width) + 1;
+	if (table)
+		return _get_table_mult(table, val);
+	return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_mult_table *table,
+				   unsigned int mult)
+{
+	const struct clk_mult_table *clkt;
+
+	for (clkt = table; clkt->mult; clkt++)
+		if (clkt->mult == mult)
+			return clkt->val;
+	return 0;
+}
+
+static unsigned int _get_val(const struct clk_mult_table *table,
+			     u8 width, unsigned int mult, unsigned long flags)
+{
+	if (flags & CLK_MULTIPLIER_ONE_BASED)
+		return mult;
+	if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+		return __ffs(mult);
+	if (flags & CLK_MULTIPLIER_MAX_MULT_AT_ZERO)
+		return (mult == mult_mask(width) + 1)
+			? 0 : mult;
+	if (table)
+		return  _get_table_val(table, mult);
+	return mult - 1;
+}
+
+unsigned long multiplier_recalc_rate(struct clk_hw *hw,
+				     unsigned long parent_rate,
+				     unsigned int val,
+				     const struct clk_mult_table *table,
+				     unsigned long flags)
+{
+	struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+	unsigned int mult;
+
+	mult = _get_mult(table, multiplier->width, val, flags);
+	if (!mult) {
+		WARN(!(flags & CLK_MULTIPLIER_ALLOW_ZERO),
+			"%s: Zero multiplier and CLK_MULTIPLIER_ALLOW_ZERO not set\n",
+			__clk_get_name(hw->clk));
+		return parent_rate;
+	}
+
+	return parent_rate * mult;
+}
+EXPORT_SYMBOL_GPL(multiplier_recalc_rate);
+
+static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+	unsigned int val;
+
+	val = clk_readl(multiplier->reg) >> multiplier->shift;
+	val &= mult_mask(multiplier->width);
+
+	return multiplier_recalc_rate(hw, parent_rate, val, multiplier->table,
+				   multiplier->flags);
+}
+
+static bool _is_valid_table_mult(const struct clk_mult_table *table,
+							 unsigned int mult)
+{
+	const struct clk_mult_table *clkt;
+
+	for (clkt = table; clkt->mult; clkt++)
+		if (clkt->mult == mult)
+			return true;
+	return false;
+}
+
+static bool _is_valid_mult(const struct clk_mult_table *table,
+			   unsigned int mult, unsigned long flags)
+{
+	if (flags & CLK_MULTIPLIER_POWER_OF_TWO)
+		return is_power_of_2(mult);
+	if (table)
+		return _is_valid_table_mult(table, mult);
+	return true;
+}
+
+static int clk_multiplier_bestmult(struct clk_hw *hw, unsigned long rate,
+			       unsigned long *best_parent_rate,
+			       const struct clk_mult_table *table, u8 width,
+			       unsigned long flags)
+{
+	int i, bestmult = 0;
+	unsigned long parent_rate, best = 0, now, maxmult, minmult;
+	unsigned long parent_rate_saved = *best_parent_rate;
+
+	if (!rate)
+		rate = 1;
+
+	minmult = _get_minmult(table);
+	maxmult = _get_maxmult(table, width, flags);
+
+	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+		parent_rate = *best_parent_rate;
+		bestmult = rate / parent_rate;
+		bestmult = bestmult == 0 ? minmult : bestmult;
+		bestmult = bestmult > maxmult ? maxmult : bestmult;
+		return bestmult;
+	}
+
+	/*
+	 * The maximum multiplier we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxmult = min(ULONG_MAX / parent_rate_saved, maxmult);
+
+	for (i = 1; i <= maxmult; i++) {
+		if (!_is_valid_mult(table, i, flags))
+			continue;
+		if (rate == parent_rate_saved * i) {
+			/*
+			 * It's the most ideal case if the requested rate can be
+			 * multiplied from parent clock without needing to
+			 * change the parent rate, so return the multiplier
+			 * immediately.
+			 */
+			*best_parent_rate = parent_rate_saved;
+			return i;
+		}
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+					       rate / i);
+		now = parent_rate * i;
+		if (now <= rate && now > best) {
+			bestmult = i;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
+
+	if (!bestmult) {
+		bestmult = _get_minmult(table);
+		*best_parent_rate
+			= __clk_round_rate(__clk_get_parent(hw->clk), 1);
+	}
+
+	return bestmult;
+}
+
+long multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
+			   unsigned long *prate,
+			   const struct clk_mult_table *table,
+			   u8 width, unsigned long flags)
+{
+	int mult;
+
+	mult = clk_multiplier_bestmult(hw, rate, prate, table, width, flags);
+
+	return *prate * mult;
+}
+EXPORT_SYMBOL_GPL(multiplier_round_rate);
+
+static long clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+	int bestmult;
+
+	/* if read only, just return current value */
+	if (multiplier->flags & CLK_MULTIPLIER_READ_ONLY) {
+		bestmult = readl(multiplier->reg) >> multiplier->shift;
+		bestmult &= mult_mask(multiplier->width);
+		bestmult = _get_mult(multiplier->table, multiplier->width,
+				     bestmult, multiplier->flags);
+		if ((__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT))
+			*prate = __clk_round_rate(__clk_get_parent(hw->clk),
+						  rate);
+		return *prate * bestmult;
+	}
+
+	return multiplier_round_rate(hw, rate, prate, multiplier->table,
+				  multiplier->width, multiplier->flags);
+}
+
+int multiplier_get_val(unsigned long rate, unsigned long parent_rate,
+		    const struct clk_mult_table *table, u8 width,
+		    unsigned long flags)
+{
+	unsigned int mult, value;
+
+	mult = rate / parent_rate;
+	value = _get_val(table, width, mult, flags);
+	return min_t(unsigned int, value, mult_mask(width));
+}
+EXPORT_SYMBOL_GPL(multiplier_get_val);
+
+static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_multiplier *multiplier = to_clk_multiplier(hw);
+	unsigned int value;
+	unsigned long flags = 0;
+	u32 val;
+
+	value = multiplier_get_val(rate, parent_rate, multiplier->table,
+				multiplier->width, multiplier->flags);
+
+	if (multiplier->lock)
+		spin_lock_irqsave(multiplier->lock, flags);
+
+	if (multiplier->flags & CLK_MULTIPLIER_HIWORD_MASK) {
+		val = mult_mask(multiplier->width) << (multiplier->shift + 16);
+	} else {
+		val = clk_readl(multiplier->reg);
+		val &= ~(mult_mask(multiplier->width) << multiplier->shift);
+	}
+	val |= value << multiplier->shift;
+	clk_writel(val, multiplier->reg);
+
+	if (multiplier->lock)
+		spin_unlock_irqrestore(multiplier->lock, flags);
+
+	return 0;
+}
+
+const struct clk_ops clk_multiplier_ops = {
+	.recalc_rate = clk_multiplier_recalc_rate,
+	.round_rate = clk_multiplier_round_rate,
+	.set_rate = clk_multiplier_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_multiplier_ops);
+
+const struct clk_ops clk_multiplier_ro_ops = {
+	.recalc_rate = clk_multiplier_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_multiplier_ro_ops);
+
+static struct clk *_register_multiplier(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_multiplier_flags, const struct clk_mult_table *table,
+		spinlock_t *lock)
+{
+	struct clk_multiplier *mult;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	if (clk_multiplier_flags & CLK_MULTIPLIER_HIWORD_MASK) {
+		if (width + shift > 16) {
+			pr_warn("multiplier value exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
+
+	/* allocate the multiplier */
+	mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
+	if (!mult)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	if (clk_multiplier_flags & CLK_MULTIPLIER_READ_ONLY)
+		init.ops = &clk_multiplier_ro_ops;
+	else
+		init.ops = &clk_multiplier_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	/* struct clk_multiplier assignments */
+	mult->reg = reg;
+	mult->shift = shift;
+	mult->width = width;
+	mult->flags = clk_multiplier_flags;
+	mult->lock = lock;
+	mult->hw.init = &init;
+	mult->table = table;
+
+	/* register the clock */
+	clk = clk_register(dev, &mult->hw);
+
+	if (IS_ERR(clk))
+		kfree(mult);
+
+	return clk;
+}
+
+/**
+ * clk_register_multiplier - register a multiplier clock with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust multiplier
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_multiplier_flags: multiplier-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_multiplier(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_multiplier_flags, spinlock_t *lock)
+{
+	return _register_multiplier(dev, name, parent_name, flags, reg, shift,
+			width, clk_multiplier_flags, NULL, lock);
+}
+EXPORT_SYMBOL_GPL(clk_register_multiplier);
+
+/**
+ * clk_register_multiplier_table - register a table based multiplier clock with
+ * the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust multiplier
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_multiplier_flags: multiplier-specific flags for this clock
+ * @table: array of multiplier/value pairs ending with a mult set to 0
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_multiplier_table(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_multiplier_flags, const struct clk_mult_table *table,
+		spinlock_t *lock)
+{
+	return _register_multiplier(dev, name, parent_name, flags, reg, shift,
+			width, clk_multiplier_flags, table, lock);
+}
+EXPORT_SYMBOL_GPL(clk_register_multiplier_table);
+
+void clk_unregister_multiplier(struct clk *clk)
+{
+	struct clk_multiplier *mult;
+	struct clk_hw *hw;
+
+	hw = __clk_get_hw(clk);
+	if (!hw)
+		return;
+
+	mult = to_clk_multiplier(hw);
+
+	clk_unregister(clk);
+	kfree(mult);
+}
+EXPORT_SYMBOL_GPL(clk_unregister_multiplier);
+
+#ifdef CONFIG_OF
+static struct clk_mult_table *of_clk_get_mult_table(struct device_node *node)
+{
+	int i;
+	unsigned int table_size;
+	struct clk_mult_table *table;
+	const __be32 *tablespec;
+	u32 val;
+
+	tablespec = of_get_property(node, "table", (int *) &table_size);
+
+	if (!tablespec)
+		return NULL;
+
+	table_size /= sizeof(struct clk_mult_table);
+
+	if (!table_size) {
+		pr_err("%s: %s table has zero length\n", __func__,
+		       node->name);
+		return ERR_PTR(-EINVAL);
+	}
+
+	table = kzalloc(sizeof(struct clk_mult_table) * (table_size + 1),
+			GFP_KERNEL);
+	if (!table) {
+		pr_err("%s: unable to allocate memory for %s table\n", __func__,
+		       node->name);
+		return NULL;
+	}
+
+	for (i = 0; i < table_size; i++) {
+		of_property_read_u32_index(node, "table", i * 2, &val);
+		table[i].mult = val;
+		of_property_read_u32_index(node, "table", i * 2 + 1, &val);
+		table[i].val = val;
+	}
+
+	return table;
+}
+
+/**
+ * of_multiplier_clk_setup() - Setup function for simple mult rate clock
+ */
+void of_multiplier_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	const char *parent_name;
+	u8 clk_multiplier_flags = 0;
+	u32 mask = 0;
+	u32 shift = 0;
+	u32 width;
+	struct clk_mult_table *table;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s: no memory mapped for property reg\n", __func__);
+		return;
+	}
+
+	if (of_property_read_u32(node, "bit-mask", &mask)) {
+		pr_err("%s: missing bit-mask property for %s\n", __func__,
+		       node->name);
+		return;
+	}
+	width = fls(mask);
+	if ((1 << width) - 1 != mask) {
+		pr_err("%s: bad bit-mask for %s\n", __func__, node->name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "bit-shift", &shift)) {
+		shift = __ffs(mask);
+		pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+				__func__, shift, node->name);
+	}
+
+	if (of_property_read_bool(node, "index-starts-at-one"))
+		clk_multiplier_flags |= CLK_MULTIPLIER_ONE_BASED;
+
+	if (of_property_read_bool(node, "index-power-of-two"))
+		clk_multiplier_flags |= CLK_MULTIPLIER_POWER_OF_TWO;
+
+	if (of_property_read_bool(node, "index-allow-zero"))
+		clk_multiplier_flags |= CLK_MULTIPLIER_ALLOW_ZERO;
+
+	if (of_property_read_bool(node, "index-max-mult-at-zero"))
+		clk_multiplier_flags |= CLK_MULTIPLIER_MAX_MULT_AT_ZERO;
+
+	table = of_clk_get_mult_table(node);
+	if (IS_ERR(table))
+		return;
+
+	clk = _register_multiplier(NULL, clk_name, parent_name, 0, reg, shift,
+			width, clk_multiplier_flags, table, NULL);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+EXPORT_SYMBOL_GPL(of_multiplier_clk_setup);
+CLK_OF_DECLARE(multiplier_clk, "multiplier-clock", of_multiplier_clk_setup);
+#endif
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 4f96ff3ba728..2e8836176eed 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -2,6 +2,7 @@
  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ * Copyright (C) 2011-2013 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,6 +17,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 /*
  * DOC: basic adjustable multiplexer clock that cannot gate
@@ -177,3 +180,76 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 				      NULL, lock);
 }
 EXPORT_SYMBOL_GPL(clk_register_mux);
+
+#ifdef CONFIG_OF
+/**
+ * of_mux_clk_setup() - Setup function for simple mux rate clock
+ */
+void of_mux_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	void __iomem *reg;
+	int num_parents;
+	const char **parent_names;
+	int i;
+	u8 clk_mux_flags = 0;
+	u32 mask = 0;
+	u32 shift = 0;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	num_parents = of_clk_get_parent_count(node);
+	if (num_parents < 1) {
+		pr_err("%s: mux-clock %s must have parent(s)\n",
+				__func__, node->name);
+		return;
+	}
+
+	parent_names = kzalloc((sizeof(char*) * num_parents),
+			GFP_KERNEL);
+
+	if (!parent_names) {
+		pr_err("%s: could not allocate parent names\n", __func__);
+		return;
+	}
+
+	for (i = 0; i < num_parents; i++)
+		parent_names[i] = of_clk_get_parent_name(node, i);
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("%s: no memory mapped for property reg\n", __func__);
+		goto fail;
+	}
+
+	if (of_property_read_u32(node, "bit-mask", &mask)) {
+		pr_err("%s: missing bit-mask property for %s\n", __func__, node->name);
+		goto fail;
+	}
+
+	if (of_property_read_u32(node, "bit-shift", &shift)) {
+		shift = __ffs(mask);
+		pr_debug("%s: bit-shift property defaults to 0x%x for %s\n",
+				__func__, shift, node->name);
+	}
+
+	if (of_property_read_bool(node, "index-starts-at-one"))
+		clk_mux_flags |= CLK_MUX_INDEX_ONE;
+
+	if (of_property_read_bool(node, "hiword-mask"))
+		clk_mux_flags |= CLK_MUX_HIWORD_MASK;
+
+	clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
+			0, reg, shift, mask, clk_mux_flags, NULL, NULL);
+
+	if (!IS_ERR(clk))
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+	return;
+fail:
+	kfree(parent_names);
+}
+EXPORT_SYMBOL_GPL(of_mux_clk_setup);
+CLK_OF_DECLARE(mux_clk, "mux-clock", of_mux_clk_setup);
+#endif
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7145f6d93567..ec3db8a8e66c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/syscore_ops.h>
 
 #include "clk.h"
 
@@ -35,6 +36,7 @@ static int enable_refcnt;
 static HLIST_HEAD(clk_root_list);
 static HLIST_HEAD(clk_orphan_list);
 static LIST_HEAD(clk_notifier_list);
+static HLIST_HEAD(clk_sw_list);
 
 /***           locking             ***/
 static void clk_prepare_lock(void)
@@ -99,8 +101,35 @@ static void clk_enable_unlock(unsigned long flags)
 
 static struct dentry *rootdir;
 static struct dentry *orphandir;
+static struct dentry *swdir;
 static int inited = 0;
 
+/* Only used when (flags & CLK_IS_SW) */
+static int sw_clk_show(struct seq_file *s, void *what)
+{
+	struct clk *clk = s->private;
+	int i;
+
+	seq_printf(s, "Parents of %s:\n", clk->name);
+	for (i = 0; i < clk->num_parents; i++)
+		seq_printf(s, "\t%s\n", clk->parents[i]
+			   ? clk->parents[i]->name : "null");
+	return 0;
+}
+
+/* Only used when (flags & CLK_IS_SW) */
+static int sw_clk_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, sw_clk_show, inode->i_private);
+}
+
+static const struct file_operations sw_clk_ops = {
+	.open		= sw_clk_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
 static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
 {
 	if (!c)
@@ -277,6 +306,13 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
 	if (!d)
 		goto err_out;
 
+	if (clk->flags & CLK_IS_SW) {
+		d = debugfs_create_file("parents", S_IFREG | S_IRUGO,
+					clk->dentry, clk, &sw_clk_ops);
+		if (!d)
+			goto err_out;
+	}
+
 	ret = 0;
 	goto out;
 
@@ -287,6 +323,31 @@ out:
 	return ret;
 }
 
+/* For sw clks which have multiple parents, create a symlink from
+ * the clock's directory to the sw_clock */
+static int clk_debug_create_symlink(struct clk *clk, struct clk *sw_clk)
+{
+	int i, n;
+	struct clk *tmp;
+	char *target;
+
+	for (n = 0, tmp = clk; tmp; n++)
+		tmp = __clk_get_parent(tmp);
+
+	target = kzalloc(strlen(clk->name) + sizeof("sw-clks/")
+			       + 3*n + 1, GFP_KERNEL);
+	if (!target)
+		return -ENOMEM;
+
+	for (i = 0; i < n; i++)
+		strcat(target, "../");
+	strcat(target, "sw-clks/");
+	strcat(target, sw_clk->name);
+	debugfs_create_symlink(sw_clk->name, clk->dentry, target);
+	kfree(target);
+	return 0;
+}
+
 /* caller must hold prepare_lock */
 static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
 {
@@ -301,6 +362,15 @@ static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
 	if (ret)
 		goto out;
 
+	if (clk->flags & CLK_IS_SW) {
+		int i;
+
+		for (i = 0, ret = 0; i < clk->num_parents && ret == 0; i++)
+			if (clk->parents[i])
+				ret = clk_debug_create_symlink(
+					clk->parents[i], clk);
+	}
+
 	hlist_for_each_entry(child, &clk->children, child_node)
 		clk_debug_create_subtree(child, clk->dentry);
 
@@ -338,6 +408,8 @@ static int clk_debug_register(struct clk *clk)
 	if (!parent)
 		if (clk->flags & CLK_IS_ROOT)
 			pdentry = rootdir;
+		else if (clk->flags & CLK_IS_SW)
+			pdentry = swdir;
 		else
 			pdentry = orphandir;
 	else
@@ -437,6 +509,11 @@ static int __init clk_debug_init(void)
 	if (!orphandir)
 		return -ENOMEM;
 
+	swdir = debugfs_create_dir("sw-clks", rootdir);
+
+	if (!swdir)
+		return -ENOMEM;
+
 	clk_prepare_lock();
 
 	hlist_for_each_entry(clk, &clk_root_list, child_node)
@@ -445,6 +522,9 @@ static int __init clk_debug_init(void)
 	hlist_for_each_entry(clk, &clk_orphan_list, child_node)
 		clk_debug_create_subtree(clk, orphandir);
 
+	hlist_for_each_entry(clk, &clk_sw_list, child_node)
+		clk_debug_create_subtree(clk, swdir);
+
 	inited = 1;
 
 	clk_prepare_unlock();
@@ -534,13 +614,13 @@ static int __init clk_ignore_unused_setup(char *__unused)
 }
 __setup("clk_ignore_unused", clk_ignore_unused_setup);
 
-static int clk_disable_unused(void)
+static void clk_disable_unused(void)
 {
 	struct clk *clk;
 
 	if (clk_ignore_unused) {
 		pr_warn("clk: Not disabling unused clocks\n");
-		return 0;
+		return;
 	}
 
 	clk_prepare_lock();
@@ -558,10 +638,19 @@ static int clk_disable_unused(void)
 		clk_unprepare_unused_subtree(clk);
 
 	clk_prepare_unlock();
+}
+
+static struct syscore_ops disable_unused_ops = {
+	.resume	= clk_disable_unused,
+};
 
+static int clk_init_disable_unused(void)
+{
+	clk_disable_unused();
+	register_syscore_ops(&disable_unused_ops);
 	return 0;
 }
-late_initcall_sync(clk_disable_unused);
+late_initcall_sync(clk_init_disable_unused);
 
 /***    helper functions   ***/
 
@@ -788,6 +877,8 @@ EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
 
 void __clk_unprepare(struct clk *clk)
 {
+	int i;
+
 	if (!clk)
 		return;
 
@@ -802,7 +893,11 @@ void __clk_unprepare(struct clk *clk)
 	if (clk->ops->unprepare)
 		clk->ops->unprepare(clk->hw);
 
-	__clk_unprepare(clk->parent);
+	if (clk->flags & CLK_IS_SW)
+		for (i = 0; i < clk->num_parents; i++)
+			__clk_unprepare(clk->parents[i]);
+	else
+		__clk_unprepare(clk->parent);
 }
 
 /**
@@ -826,13 +921,28 @@ EXPORT_SYMBOL_GPL(clk_unprepare);
 
 int __clk_prepare(struct clk *clk)
 {
-	int ret = 0;
+	int i, j, ret = 0;
 
 	if (!clk)
 		return 0;
 
 	if (clk->prepare_count == 0) {
-		ret = __clk_prepare(clk->parent);
+		if (clk->flags & CLK_IS_SW)
+			for (i = 0; i < clk->num_parents; i++) {
+				if (!clk->parents[i])
+					clk->parents[i] =
+						__clk_lookup(clk->parent_names[i]);
+				ret = __clk_prepare(clk->parents[i]);
+				if (ret) {
+					for (j = i - 1; j >= 0; j--)
+						__clk_unprepare(
+							clk->parents[j]);
+					break;
+				}
+			}
+		else
+			ret = __clk_prepare(clk->parent);
+
 		if (ret)
 			return ret;
 
@@ -876,6 +986,8 @@ EXPORT_SYMBOL_GPL(clk_prepare);
 
 static void __clk_disable(struct clk *clk)
 {
+	int i;
+
 	if (!clk)
 		return;
 
@@ -891,7 +1003,11 @@ static void __clk_disable(struct clk *clk)
 	if (clk->ops->disable)
 		clk->ops->disable(clk->hw);
 
-	__clk_disable(clk->parent);
+	if (clk->flags & CLK_IS_SW)
+		for (i = 0; i < clk->num_parents; i++)
+			__clk_disable(clk->parents[i]);
+	else
+		__clk_disable(clk->parent);
 }
 
 /**
@@ -918,7 +1034,7 @@ EXPORT_SYMBOL_GPL(clk_disable);
 
 static int __clk_enable(struct clk *clk)
 {
-	int ret = 0;
+	int i, j, ret = 0;
 
 	if (!clk)
 		return 0;
@@ -927,7 +1043,20 @@ static int __clk_enable(struct clk *clk)
 		return -ESHUTDOWN;
 
 	if (clk->enable_count == 0) {
-		ret = __clk_enable(clk->parent);
+		if (clk->flags & CLK_IS_SW)
+			for (i = 0; i < clk->num_parents && !ret; i++) {
+				if (!clk->parents[i])
+					clk->parents[i] =
+						__clk_lookup(clk->parent_names[i]);
+				ret = __clk_enable(clk->parents[i]);
+				if (ret) {
+					for (j = i - 1; j >= 0; j--)
+						__clk_disable(clk->parents[j]);
+					break;
+				}
+			}
+		else
+			ret = __clk_enable(clk->parent);
 
 		if (ret)
 			return ret;
@@ -1838,7 +1967,8 @@ int __clk_init(struct device *dev, struct clk *clk)
 	 * If clk->parents is not NULL we skip this entire block.  This allows
 	 * for clock drivers to statically initialize clk->parents.
 	 */
-	if (clk->num_parents > 1 && !clk->parents) {
+	if ((clk->num_parents > 1 || (clk->flags & CLK_IS_SW))
+	    && !clk->parents) {
 		clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *),
 					GFP_KERNEL);
 		/*
@@ -1853,7 +1983,7 @@ int __clk_init(struct device *dev, struct clk *clk)
 					__clk_lookup(clk->parent_names[i]);
 	}
 
-	clk->parent = __clk_init_parent(clk);
+	clk->parent = (clk->flags & CLK_IS_SW) ? NULL : __clk_init_parent(clk);
 
 	/*
 	 * Populate clk->parent if parent has already been __clk_init'd.  If
@@ -1870,6 +2000,8 @@ int __clk_init(struct device *dev, struct clk *clk)
 				&clk->parent->children);
 	else if (clk->flags & CLK_IS_ROOT)
 		hlist_add_head(&clk->child_node, &clk_root_list);
+	else if (clk->flags & CLK_IS_SW)
+		hlist_add_head(&clk->child_node, &clk_sw_list);
 	else
 		hlist_add_head(&clk->child_node, &clk_orphan_list);
 
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 95fb944e15ee..5ea6a1f6a399 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -263,7 +263,13 @@ static void __arch_timer_setup(unsigned type,
 	clk->features = CLOCK_EVT_FEAT_ONESHOT;
 
 	if (type == ARCH_CP15_TIMER) {
+#ifndef CONFIG_BRCMSTB
+		/* Our Brahma B15 local timer is kept running during WFI, and
+		 * we rely on this "Cortex A15 oddity" for high-resolution
+		 * timers to be available.
+		 */
 		clk->features |= CLOCK_EVT_FEAT_C3STOP;
+#endif
 		clk->name = "arch_sys_timer";
 		clk->rating = 450;
 		clk->cpumask = cpumask_of(smp_processor_id());
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 31297499a60a..f07813f585d6 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -9,6 +9,15 @@ config ARM_BIG_LITTLE_CPUFREQ
 	help
 	  This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.
 
+config ARM_BRCMSTB_CPUFREQ
+	tristate "Broadcom STB CPUfreq driver"
+	depends on ARCH_BRCMSTB || COMPILE_TEST
+	help
+	  Some Broadcom SoCs offer multiple operating frequencies that CPUfreq
+	  can take advantage of to improve energy efficiency.
+
+	  Say Y, if you have a supported Broadcom SoC.
+
 config ARM_DT_BL_CPUFREQ
 	tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
 	depends on ARM_BIG_LITTLE_CPUFREQ && OF
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index dac58f67307a..5f8b7063586d 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ)	+= arm_big_little.o
 # LITTLE drivers, so that it is probed last.
 obj-$(CONFIG_ARM_DT_BL_CPUFREQ)		+= arm_big_little_dt.o
 
+obj-$(CONFIG_ARM_BRCMSTB_CPUFREQ)	+= brcmstb-cpufreq.o
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o
 obj-$(CONFIG_UX500_SOC_DB8500)		+= dbx500-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
diff --git a/drivers/cpufreq/brcmstb-cpufreq.c b/drivers/cpufreq/brcmstb-cpufreq.c
new file mode 100644
index 000000000000..8e136e289449
--- /dev/null
+++ b/drivers/cpufreq/brcmstb-cpufreq.c
@@ -0,0 +1,386 @@
+/*
+ * CPU frequency scaling for Broadcom set top box SoCs
+ *
+ * Copyright (c) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/cpufreq.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#define BRCMSTB_CPUFREQ_PREFIX	"brcmstb"
+#define BRCMSTB_CPUFREQ_NAME	BRCMSTB_CPUFREQ_PREFIX "-cpufreq"
+
+/* We search for these compatible strings. */
+#define BRCMSTB_DT_CPU_CLK_CTRL	"brcm,brcmstb-cpu-clk-div"
+#define BRCMSTB_DT_MEMC_DDR	"brcm,brcmstb-memc-ddr"
+#define BRCM_AVS_CPU_DATA	"brcm,avs-cpu-data-mem"
+
+/* We also need a few clocks in device tree. These are node names. */
+#define BRCMSTB_CLK_MDIV_CH0	"cpu_mdiv_ch0"
+#define BRCMSTB_CLK_NDIV_INT	"cpu_ndiv_int"
+#define BRCMSTB_CLK_SW_SCB	"sw_scb"
+
+#define BRCMSTB_TBL_SAFE_MODE	BIT(0)
+#define BRCMSTB_REG_SAFE_MODE	BIT(4)
+
+#define TRANSITION_LATENCY	(25 * 1000)	/* 25 us */
+
+/* This is as low as we'll go in the frequency table. */
+#define MIN_CPU_FREQ		(100 * 1000)	/* in kHz */
+
+struct private_data {
+	void __iomem *cpu_clk_ctrl_reg;
+	struct device *dev;
+};
+
+static struct private_data *driver_data;
+static struct cpufreq_frequency_table *global_freq_table;
+static struct platform_device *global_pdev;
+
+/* Count the active memory controllers in the system. */
+static int count_memory_controllers(void)
+{
+	struct device_node *np = NULL;
+	int i = 0;
+
+	do {
+		np = of_find_compatible_node(np, NULL, BRCMSTB_DT_MEMC_DDR);
+		if (of_device_is_available(np))
+			i++;
+		of_node_put(np);
+	} while (np);
+
+	return i;
+}
+
+static int get_frequencies(const struct cpufreq_policy *policy,
+			   unsigned int *vco_freq, unsigned int *cpu_freq,
+			   unsigned int *scb_freq)
+{
+	struct clk *cpu_ndiv_int, *sw_scb;
+
+	cpu_ndiv_int = __clk_lookup(BRCMSTB_CLK_NDIV_INT);
+	if (!cpu_ndiv_int)
+		return -ENODEV;
+
+	sw_scb = __clk_lookup(BRCMSTB_CLK_SW_SCB);
+	if (!sw_scb)
+		return -ENODEV;
+
+	/* return frequencies in kHz */
+	*vco_freq = clk_get_rate(cpu_ndiv_int) / 1000;
+	*cpu_freq = clk_get_rate(policy->clk) / 1000;
+	*scb_freq = clk_get_rate(sw_scb) / 1000;
+
+	return 0;
+}
+
+/*
+ * Safe mode: When set, the CPU's bus unit is being throttled. This is done to
+ * avoid buffer overflows when the CPU-to-bus-clock ratio is low.
+ *
+ * The formula as to what constitutes a low CPU-to-bus-clock ratio takes into
+ * account the number of memory controllers active in the system and the SCB
+ * frequency. More memory controllers means safe mode is required starting at
+ * higher frequencies.
+ *
+ * For 1 memory controller, cpu_freq/scb_freq must be greater than or equal to
+ * 2 to not require safe mode.
+ *
+ * For 2 or 3 memory controllers, cpu_freq/scb_freq must be greater than or
+ * equal 3 to not require safe mode.
+ */
+
+static int freq_requires_safe_mode(unsigned int cpu_freq, unsigned int scb_freq,
+				   int num_memc)
+{
+	unsigned int safe_ratio;
+
+	switch (num_memc) {
+	case 1:
+		safe_ratio = 2;
+		break;
+	case 2:
+	case 3:
+		safe_ratio = 3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return ((cpu_freq / scb_freq) < safe_ratio);
+}
+
+static struct cpufreq_frequency_table *
+brcmstb_get_freq_table(const struct cpufreq_policy *policy)
+{
+	unsigned int cpu_freq, vco_freq, scb_freq, mdiv, init_mdiv, f;
+	struct cpufreq_frequency_table *table;
+	struct private_data *priv;
+	int num_memc, ret;
+	unsigned int i = 0;
+
+	ret = get_frequencies(policy, &vco_freq, &cpu_freq, &scb_freq);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = driver_data;
+	num_memc = count_memory_controllers();
+
+	/* Calculate the initial mdiv value. We'll increment mdiv from here. */
+	init_mdiv = vco_freq / cpu_freq;
+
+	/* Count how many frequencies we'll offer. */
+	f = cpu_freq;
+	for (mdiv = init_mdiv; f >= MIN_CPU_FREQ; mdiv++, f = vco_freq / mdiv) {
+		/* We only want to use "whole" MHz. */
+		if ((f % 1000) == 0)
+			i++;
+	}
+
+	table = devm_kzalloc(priv->dev, (i + 1) * sizeof(*table), GFP_KERNEL);
+	if (!table)
+		return ERR_PTR(-ENOMEM);
+
+	/* Now, fill the table. */
+	f = cpu_freq;
+	i = 0;
+	for (mdiv = init_mdiv; f >= MIN_CPU_FREQ; mdiv++, f = vco_freq / mdiv) {
+		if ((f % 1000) == 0) {
+			table[i].frequency = f;
+			ret = freq_requires_safe_mode(f, scb_freq, num_memc);
+			if (ret < 0)
+				return ERR_PTR(ret);
+			if (ret > 0)
+				table[i].driver_data |= BRCMSTB_TBL_SAFE_MODE;
+			i++;
+		}
+	}
+	table[i].frequency = CPUFREQ_TABLE_END;
+
+	return table;
+}
+
+static int brcmstb_target_index(struct cpufreq_policy *policy,
+				unsigned int index)
+{
+	struct cpufreq_frequency_table *entry;
+	struct private_data *priv;
+	int ret, safe_mode_needed;
+	u32 reg;
+
+	priv = driver_data;
+	entry = &global_freq_table[index];
+	safe_mode_needed = entry->driver_data & BRCMSTB_TBL_SAFE_MODE;
+
+	reg = readl(priv->cpu_clk_ctrl_reg);
+	if (safe_mode_needed && !(reg & BRCMSTB_REG_SAFE_MODE)) {
+		reg |= BRCMSTB_REG_SAFE_MODE;
+		writel(reg, priv->cpu_clk_ctrl_reg);
+	}
+	ret = clk_set_rate(policy->clk, entry->frequency * 1000);
+	if (!ret && !safe_mode_needed && (reg & BRCMSTB_REG_SAFE_MODE)) {
+		reg &= ~BRCMSTB_REG_SAFE_MODE;
+		writel(reg, priv->cpu_clk_ctrl_reg);
+	}
+
+	return ret;
+}
+
+/*
+ * All initialization code that we only want to execute once goes here. Setup
+ * code that can be re-tried on every core (if it failed before) can go into
+ * brcmstb_cpufreq_init().
+ */
+static int brcmstb_prepare_init(struct platform_device *pdev)
+{
+	struct private_data *priv;
+	struct resource *res;
+	struct device *dev;
+
+	/*
+	 * If the BRCM STB AVS CPUfreq driver is supported, we bail, so that
+	 * the more modern approach implementing DVFS in firmware can be used.
+	 */
+	if (IS_ENABLED(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ)) {
+		struct device_node *np;
+
+		np = of_find_compatible_node(NULL, NULL, BRCM_AVS_CPU_DATA);
+		if (np) {
+			of_node_put(np);
+			return -ENXIO;
+		}
+	}
+
+	dev = &pdev->dev;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->cpu_clk_ctrl_reg = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->cpu_clk_ctrl_reg)) {
+		dev_err(dev, "couldn't map DT entry %s\n",
+			BRCMSTB_DT_CPU_CLK_CTRL);
+		return -ENODEV;
+	}
+
+	priv->dev = dev;
+	platform_set_drvdata(pdev, priv);
+
+	return 0;
+}
+
+static int brcmstb_cpufreq_init(struct cpufreq_policy *policy)
+{
+	struct cpufreq_frequency_table *freq_table;
+	struct platform_device *pdev;
+	struct private_data *priv;
+	struct clk *cpu_mdiv_ch0;
+	struct device *dev;
+	int ret;
+
+	cpu_mdiv_ch0 = __clk_lookup(BRCMSTB_CLK_MDIV_CH0);
+	if (!cpu_mdiv_ch0)
+		return -ENODEV;
+
+	pdev = global_pdev;
+	priv = platform_get_drvdata(pdev);
+	dev = &pdev->dev;
+
+	policy->clk = cpu_mdiv_ch0;
+	driver_data = priv;
+
+	freq_table = brcmstb_get_freq_table(policy);
+	global_freq_table = freq_table;
+	if (IS_ERR(freq_table)) {
+		ret = PTR_ERR(freq_table);
+		dev_err(dev, "Couldn't determine frequency table (%d).\n", ret);
+		if (ret == -EINVAL)
+			dev_emerg(dev,
+				"Invalid number of memory controllers -- %d!\n",
+				count_memory_controllers());
+		return ret;
+	}
+
+	ret = cpufreq_generic_init(policy, freq_table, TRANSITION_LATENCY);
+	if (!ret)
+		dev_info(dev, "registered\n");
+
+	return ret;
+}
+
+/* Shows the number of memory controllers. */
+static ssize_t show_brcmstb_num_memc(struct cpufreq_policy *policy, char *buf)
+{
+	return sprintf(buf, "%u\n", count_memory_controllers());
+}
+
+/* Shows vco_freq, cpu_freq, and scb_freq in kHz. */
+static ssize_t show_brcmstb_freqs(struct cpufreq_policy *policy, char *buf)
+{
+	unsigned int vco_freq, cpu_freq, scb_freq;
+	int ret;
+
+	ret = get_frequencies(policy, &vco_freq, &cpu_freq, &scb_freq);
+	if (ret)
+		return sprintf(buf, "<unknown>\n");
+
+	return sprintf(buf, "%u %u %u\n", vco_freq, cpu_freq, scb_freq);
+}
+
+/* Shows the lowest frequency (in kHz) that can be used without "safe mode". */
+static ssize_t show_brcmstb_safe_freq(struct cpufreq_policy *policy, char *buf)
+{
+	int i;
+	unsigned int safe_freq = 0;
+
+	for (i = 0; global_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+		if (!(global_freq_table[i].driver_data & BRCMSTB_TBL_SAFE_MODE))
+			safe_freq = global_freq_table[i].frequency;
+	}
+
+	return sprintf(buf, "%u\n", safe_freq);
+}
+
+cpufreq_freq_attr_ro(brcmstb_num_memc);
+cpufreq_freq_attr_ro(brcmstb_freqs);
+cpufreq_freq_attr_ro(brcmstb_safe_freq);
+
+static struct freq_attr *brcmstb_cpufreq_attr[] = {
+	&cpufreq_freq_attr_scaling_available_freqs,
+	&brcmstb_num_memc,
+	&brcmstb_freqs,
+	&brcmstb_safe_freq,
+	NULL
+};
+
+static struct cpufreq_driver brcmstb_driver = {
+	.flags		= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
+	.verify		= cpufreq_generic_frequency_table_verify,
+	.target_index	= brcmstb_target_index,
+	.get		= cpufreq_generic_get,
+	.init		= brcmstb_cpufreq_init,
+	.attr		= brcmstb_cpufreq_attr,
+	.name		= BRCMSTB_CPUFREQ_PREFIX,
+};
+
+static int brcmstb_cpufreq_probe(struct platform_device *pdev)
+{
+	int ret;
+
+	ret = brcmstb_prepare_init(pdev);
+	if (ret)
+		return ret;
+
+	global_pdev = pdev;
+
+	return cpufreq_register_driver(&brcmstb_driver);
+}
+
+static int brcmstb_cpufreq_remove(struct platform_device *pdev)
+{
+	int ret;
+
+	ret = cpufreq_unregister_driver(&brcmstb_driver);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id brcmstb_cpufreq_match[] = {
+	{ .compatible = BRCMSTB_DT_CPU_CLK_CTRL },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, brcmstb_cpufreq_match);
+
+static struct platform_driver brcmstb_cpufreq_platdrv = {
+	.driver = {
+		.name	= BRCMSTB_CPUFREQ_NAME,
+		.of_match_table = brcmstb_cpufreq_match,
+	},
+	.probe		= brcmstb_cpufreq_probe,
+	.remove		= brcmstb_cpufreq_remove,
+};
+module_platform_driver(brcmstb_cpufreq_platdrv);
+
+MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
+MODULE_DESCRIPTION("CPUfreq driver for Broadcom STB SoCs");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7025562ede12..4bdf470b9d89 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -56,6 +56,9 @@ config GPIO_ACPI
 	def_bool y
 	depends on ACPI
 
+config GPIOLIB_IRQCHIP
+	bool
+
 config DEBUG_GPIO
 	bool "Debug GPIO calls"
 	depends on DEBUG_KERNEL
@@ -109,6 +112,15 @@ config GPIO_MAX730X
 
 comment "Memory mapped GPIO drivers:"
 
+config GPIO_BRCMSTB
+	tristate "BRCMSTB GPIO support"
+	default y if ARCH_BRCMSTB
+	depends on OF_GPIO && (ARCH_BRCMSTB || COMPILE_TEST)
+	select GPIO_GENERIC
+	select IRQ_DOMAIN
+	help
+	  Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
+
 config GPIO_CLPS711X
 	tristate "CLPS711X GPIO support"
 	depends on ARCH_CLPS711X || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5d50179ece16..b487bbde23f5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
 obj-$(CONFIG_GPIO_BCM_KONA)	+= gpio-bcm-kona.o
+obj-$(CONFIG_GPIO_BRCMSTB)	+= gpio-brcmstb.o
 obj-$(CONFIG_GPIO_BT8XX)	+= gpio-bt8xx.o
 obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
 obj-$(CONFIG_GPIO_CS5535)	+= gpio-cs5535.o
diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
new file mode 100644
index 000000000000..20146f19d049
--- /dev/null
+++ b/drivers/gpio/gpio-brcmstb.c
@@ -0,0 +1,792 @@
+/*
+ * Copyright (C) 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/gpio/driver.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/module.h>
+#include <linux/basic_mmio_gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+
+#define GIO_BANK_SIZE           0x20
+#define GIO_ODEN(bank)          (((bank) * GIO_BANK_SIZE) + 0x00)
+#define GIO_DATA(bank)          (((bank) * GIO_BANK_SIZE) + 0x04)
+#define GIO_IODIR(bank)         (((bank) * GIO_BANK_SIZE) + 0x08)
+#define GIO_EC(bank)            (((bank) * GIO_BANK_SIZE) + 0x0c)
+#define GIO_EI(bank)            (((bank) * GIO_BANK_SIZE) + 0x10)
+#define GIO_MASK(bank)          (((bank) * GIO_BANK_SIZE) + 0x14)
+#define GIO_LEVEL(bank)         (((bank) * GIO_BANK_SIZE) + 0x18)
+#define GIO_STAT(bank)          (((bank) * GIO_BANK_SIZE) + 0x1c)
+#define GIO_BANK_OFF(bank, off)	(((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
+
+struct brcmstb_gpio_bank {
+	struct list_head node;
+	int id;
+	struct bgpio_chip bgc;
+	struct brcmstb_gpio_priv *parent_priv;
+	u32 width;
+	u32 wake_active;
+	u32 regs[GIO_BANK_SIZE / sizeof(u32)];
+};
+
+struct brcmstb_gpio_priv {
+	struct list_head bank_list;
+	void __iomem *reg_base;
+	int num_gpios;
+	struct platform_device *pdev;
+	struct irq_chip irq_chip;
+	struct irq_domain *irq_domain;
+	int parent_irq;
+	int gpio_base;
+	bool can_wake;
+	int parent_wake_irq;
+	struct notifier_block reboot_notifier;
+};
+
+#define MAX_GPIO_PER_BANK       32
+#define GPIO_BANK(gpio)         ((gpio) >> 5)
+/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
+#define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
+
+static inline struct brcmstb_gpio_bank *
+brcmstb_gpio_gc_to_bank(struct gpio_chip *gc)
+{
+	struct bgpio_chip *bgc = to_bgpio_chip(gc);
+	return container_of(bgc, struct brcmstb_gpio_bank, bgc);
+}
+
+static inline struct brcmstb_gpio_priv *
+brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
+{
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	return bank->parent_priv;
+}
+
+static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
+		unsigned int offset, bool enable)
+{
+	struct bgpio_chip *bgc = &bank->bgc;
+	struct brcmstb_gpio_priv *priv = bank->parent_priv;
+	u32 mask = bgc->pin2mask(bgc, offset);
+	u32 imask;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bgc->lock, flags);
+	imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id));
+	if (enable)
+		imask |= mask;
+	else
+		imask &= ~mask;
+	bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
+	spin_unlock_irqrestore(&bgc->lock, flags);
+}
+
+static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned gc_offset)
+{
+	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+	/* gc_offset is relative to this gpio_chip; want real offset */
+	int offset = gc_offset + (gc->base - priv->gpio_base);
+
+	if (offset >= priv->num_gpios)
+		return -ENXIO;
+	return irq_create_mapping(priv->irq_domain, offset);
+}
+
+/* -------------------- IRQ chip functions -------------------- */
+
+static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
+		struct brcmstb_gpio_bank *bank)
+{
+	return hwirq - (bank->bgc.gc.base - bank->parent_priv->gpio_base);
+}
+
+static void brcmstb_gpio_irq_mask(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	int offset = brcmstb_gpio_hwirq_to_offset(d->hwirq, bank);
+
+	brcmstb_gpio_set_imask(bank, offset, false);
+}
+
+static void brcmstb_gpio_irq_unmask(struct irq_data *d)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	int offset = brcmstb_gpio_hwirq_to_offset(d->hwirq, bank);
+
+	brcmstb_gpio_set_imask(bank, offset, true);
+}
+
+static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	struct brcmstb_gpio_priv *priv = bank->parent_priv;
+	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
+	u32 edge_insensitive, iedge_insensitive;
+	u32 edge_config, iedge_config;
+	u32 level, ilevel;
+	unsigned long flags;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_LOW:
+		level = mask;
+		edge_config = 0;
+		edge_insensitive = 0;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		level = mask;
+		edge_config = mask;
+		edge_insensitive = 0;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		level = 0;
+		edge_config = 0;
+		edge_insensitive = 0;
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		level = 0;
+		edge_config = mask;
+		edge_insensitive = 0;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		level = 0;
+		edge_config = 0;  /* don't care, but want known value */
+		edge_insensitive = mask;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&bank->bgc.lock, flags);
+
+	iedge_config = bank->bgc.read_reg(priv->reg_base +
+			GIO_EC(bank->id)) & ~mask;
+	iedge_insensitive = bank->bgc.read_reg(priv->reg_base +
+			GIO_EI(bank->id)) & ~mask;
+	ilevel = bank->bgc.read_reg(priv->reg_base +
+			GIO_LEVEL(bank->id)) & ~mask;
+
+	bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id),
+			iedge_config | edge_config);
+	bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id),
+			iedge_insensitive | edge_insensitive);
+	bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
+			ilevel | level);
+
+	spin_unlock_irqrestore(&bank->bgc.lock, flags);
+	return 0;
+}
+
+static int __brcmstb_gpio_irq_set_wake(struct brcmstb_gpio_priv *priv,
+		unsigned int enable)
+{
+	int ret = 0;
+
+	/*
+	 * Only enable wake IRQ once for however many hwirqs can wake
+	 * since they all use the same wake IRQ.  Mask will be set
+	 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
+	 */
+	if (enable)
+		ret = enable_irq_wake(priv->parent_wake_irq);
+	else
+		ret = disable_irq_wake(priv->parent_wake_irq);
+	if (ret)
+		dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
+				enable ? "enable" : "disable");
+	return ret;
+}
+
+static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
+
+	/* Do not do anything specific for now, suspend/resume callbacks will
+	 * configure the interrupt mask appropriately
+	 */
+	if (enable)
+		bank->wake_active |= mask;
+	else
+		bank->wake_active &= ~mask;
+
+	return __brcmstb_gpio_irq_set_wake(priv, enable);
+}
+
+static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
+{
+	struct brcmstb_gpio_priv *priv = data;
+
+	if (!priv || irq != priv->parent_wake_irq)
+		return IRQ_NONE;
+	pm_wakeup_event(&priv->pdev->dev, 0);
+	return IRQ_HANDLED;
+}
+
+static void brcmstb_gpio_irq_bank_handler(int irq,
+		struct brcmstb_gpio_bank *bank)
+{
+	struct brcmstb_gpio_priv *priv = bank->parent_priv;
+	struct irq_domain *domain = priv->irq_domain;
+	int hwbase = bank->bgc.gc.base - priv->gpio_base;
+	void __iomem *reg_base = priv->reg_base;
+	unsigned long status;
+	unsigned long flags;
+
+	spin_lock_irqsave(&bank->bgc.lock, flags);
+	while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) &
+			 bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) {
+		int bit;
+
+		/* Ack the status bits we are about to service */
+		bank->bgc.write_reg(reg_base + GIO_STAT(bank->id),
+				    status);
+		spin_unlock_irqrestore(&bank->bgc.lock, flags);
+
+		for_each_set_bit(bit, &status, 32) {
+			int hwirq = hwbase + bit;
+			if (bit >= bank->width)
+				dev_warn(&priv->pdev->dev,
+					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
+					 bank->id, bit);
+			generic_handle_irq(irq_find_mapping(domain, hwirq));
+		}
+
+		spin_lock_irqsave(&bank->bgc.lock, flags);
+	}
+	spin_unlock_irqrestore(&bank->bgc.lock, flags);
+}
+
+/* Each UPG GIO block has one IRQ for all banks */
+static void brcmstb_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct list_head *pos;
+
+	/* Interrupts weren't properly cleared during probe */
+	BUG_ON(!priv || !chip);
+
+	chained_irq_enter(chip, desc);
+	list_for_each(pos, &priv->bank_list) {
+		struct brcmstb_gpio_bank *bank =
+			list_entry(pos, struct brcmstb_gpio_bank, node);
+		brcmstb_gpio_irq_bank_handler(irq, bank);
+	}
+	chained_irq_exit(chip, desc);
+}
+
+static int brcmstb_gpio_reboot(struct notifier_block *nb,
+		unsigned long action, void *data)
+{
+	struct brcmstb_gpio_priv *priv =
+		container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
+
+	/* Enable GPIO for S5 cold boot */
+	if (action == SYS_POWER_OFF)
+		__brcmstb_gpio_irq_set_wake(priv, 1);
+
+	return NOTIFY_DONE;
+}
+
+static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
+		struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
+{
+	struct list_head *pos;
+	int i = 0;
+
+	/* banks are in descending order */
+	list_for_each_prev(pos, &priv->bank_list) {
+		struct brcmstb_gpio_bank *bank =
+			list_entry(pos, struct brcmstb_gpio_bank, node);
+		i += bank->bgc.gc.ngpio;
+		if (hwirq < i)
+			return bank;
+	}
+	return NULL;
+}
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key brcmstb_gpio_irq_lock_class;
+
+
+static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
+		irq_hw_number_t hwirq)
+{
+	struct brcmstb_gpio_priv *priv = d->host_data;
+	struct brcmstb_gpio_bank *bank =
+		brcmstb_gpio_hwirq_to_bank(priv, hwirq);
+	struct platform_device *pdev = priv->pdev;
+	int ret;
+
+	if (!bank)
+		return -EINVAL;
+
+	dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
+		irq, (int)hwirq, bank->id);
+	ret = irq_set_chip_data(irq, &bank->bgc.gc);
+	if (ret < 0)
+		return ret;
+	irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class);
+	irq_set_chip_and_handler(irq, &priv->irq_chip, handle_simple_irq);
+#ifdef CONFIG_ARM
+	set_irq_flags(irq, IRQF_VALID);
+#else
+	irq_set_noprobe(irq);
+#endif
+	return 0;
+}
+
+static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
+{
+	irq_set_chip_and_handler(irq, NULL, NULL);
+	irq_set_chip_data(irq, NULL);
+}
+
+static struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
+	.map = brcmstb_gpio_irq_map,
+	.unmap = brcmstb_gpio_irq_unmap,
+	.xlate = irq_domain_xlate_twocell,
+};
+
+/* Make sure that the number of banks matches up between properties */
+static int brcmstb_gpio_sanity_check_banks(struct device *dev,
+		struct device_node *np, struct resource *res)
+{
+	int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
+	int num_banks = of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
+
+	if (res_num_banks != num_banks) {
+		dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
+				res_num_banks, num_banks);
+		return -EINVAL;
+	} else {
+		return 0;
+	}
+}
+
+static int brcmstb_gpio_remove(struct platform_device *pdev)
+{
+	struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
+	struct list_head *pos;
+	struct brcmstb_gpio_bank *bank;
+	int ret = 0;
+
+	if (!priv) {
+		dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
+		return -EFAULT;
+	}
+
+	/*
+	 * You can lose return values below, but we report all errors, and it's
+	 * more important to actually perform all of the steps.
+	 */
+	list_for_each(pos, &priv->bank_list) {
+		bank = list_entry(pos, struct brcmstb_gpio_bank, node);
+		ret = bgpio_remove(&bank->bgc);
+		if (ret)
+			dev_err(&pdev->dev, "bgpio_remove fail in cleanup\n");
+	}
+	if (priv->reboot_notifier.notifier_call) {
+		ret = unregister_reboot_notifier(&priv->reboot_notifier);
+		if (ret)
+			dev_err(&pdev->dev,
+				"failed to unregister reboot notifier\n");
+	}
+	return ret;
+}
+
+static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
+		const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
+	struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
+	int offset;
+
+	if (gc->of_gpio_n_cells != 2) {
+		WARN_ON(1);
+		return -EINVAL;
+	}
+
+	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+		return -EINVAL;
+
+	offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
+	if (offset >= gc->ngpio || offset < 0)
+		return -EINVAL;
+
+	if (unlikely(offset >= bank->width)) {
+		dev_warn_ratelimited(&priv->pdev->dev,
+			"Received request for invalid GPIO offset %d\n",
+			gpiospec->args[0]);
+	}
+
+	if (flags)
+		*flags = gpiospec->args[1];
+
+	return offset;
+}
+
+/* priv->parent_irq and priv->num_gpios must be set before calling */
+static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
+		struct brcmstb_gpio_priv *priv)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = NULL;
+
+	priv->irq_chip.name = dev_name(dev);
+	priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
+	priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
+	priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
+	priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
+
+	/* Ensures that interrupts are masked when changing their type  */
+	priv->irq_chip.flags = IRQCHIP_SET_TYPE_MASKED;
+
+	if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake
+		&& !priv->parent_wake_irq) {
+		priv->parent_wake_irq = platform_get_irq(pdev, 1);
+		while (priv->parent_wake_irq < 0) {
+			np = of_find_compatible_node(np, NULL,
+							"brcm,brcmstb-gpio");
+			if (!np)
+				break;
+			pdev = of_find_device_by_node(np);
+			of_node_put(np);
+			if (!pdev)
+				continue;
+			priv->parent_wake_irq = platform_get_irq(pdev, 1);
+		}
+		if (priv->parent_wake_irq < 0) {
+			dev_warn(dev,
+				"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
+		} else {
+			int err;
+
+			/*
+			 * Set wakeup capability before requesting wakeup
+			 * interrupt, so we can process boot-time "wakeups"
+			 * (e.g., from S5 cold boot)
+			 */
+			device_set_wakeup_capable(dev, true);
+			device_wakeup_enable(dev);
+			err = devm_request_irq(dev, priv->parent_wake_irq,
+					brcmstb_gpio_wake_irq_handler, IRQF_SHARED,
+					"brcmstb-gpio-wake", priv);
+
+			if (err < 0) {
+				dev_err(dev, "Couldn't request wake IRQ");
+				return err;
+			}
+
+			priv->reboot_notifier.notifier_call =
+				brcmstb_gpio_reboot;
+			register_reboot_notifier(&priv->reboot_notifier);
+			priv->can_wake = true;
+		}
+	}
+
+	if (priv->can_wake)
+		priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
+	else
+		/* Ensures that all non-wakeup IRQs are disabled at suspend */
+		priv->irq_chip.flags |= IRQCHIP_MASK_ON_SUSPEND;
+
+	/* Restore the intended value of np */
+	np = dev->of_node;
+
+	priv->irq_domain =
+		irq_domain_add_linear(np, priv->num_gpios,
+				      &brcmstb_gpio_irq_domain_ops,
+				      priv);
+	if (!priv->irq_domain) {
+		dev_err(dev, "Couldn't allocate IRQ domain\n");
+		return -ENXIO;
+	}
+	irq_set_chained_handler(priv->parent_irq,
+				brcmstb_gpio_irq_handler);
+	irq_set_handler_data(priv->parent_irq, priv);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
+				   struct brcmstb_gpio_bank *bank)
+{
+	struct bgpio_chip *bgc = &bank->bgc;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(bank->regs); i++)
+		bank->regs[i] = bgc->read_reg(priv->reg_base +
+					      GIO_BANK_OFF(bank->id, i));
+}
+
+static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
+				      struct brcmstb_gpio_bank *bank)
+{
+	struct bgpio_chip *bgc = &bank->bgc;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(bank->regs); i++)
+		bgc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
+				bank->regs[i]);
+}
+
+static int brcmstb_gpio_suspend(struct device *dev)
+{
+	struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
+	struct brcmstb_gpio_bank *bank;
+	struct bgpio_chip *bgc;
+	struct list_head *pos;
+	u32 imask;
+
+	list_for_each(pos, &priv->bank_list) {
+		bank = list_entry(pos, struct brcmstb_gpio_bank, node);
+		bgc = &bank->bgc;
+
+		brcmstb_gpio_bank_save(priv, bank);
+
+		/* Unmask GPIOs which have been flagged as wake-up sources */
+		if (priv->can_wake) {
+			imask = bgc->read_reg(priv->reg_base +
+					      GIO_MASK(bank->id));
+			imask |= bank->wake_active;
+			bgc->write_reg(priv->reg_base + GIO_MASK(bank->id),
+				       imask);
+		}
+	}
+
+	return 0;
+}
+
+static int brcmstb_gpio_resume(struct device *dev)
+{
+	struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
+	struct brcmstb_gpio_bank *bank;
+	struct list_head *pos;
+	struct bgpio_chip *bgc;
+	u32 imask;
+
+	list_for_each(pos, &priv->bank_list) {
+		bank = list_entry(pos, struct brcmstb_gpio_bank, node);
+		bgc = &bank->bgc;
+
+		brcmstb_gpio_bank_restore(priv, bank);
+
+		/* Mask GPIOs which have been flagged as wake-up sources */
+		if (priv->can_wake) {
+			imask = bgc->read_reg(priv->reg_base +
+					      GIO_MASK(bank->id));
+			imask &= ~bank->wake_active;
+			bgc->write_reg(priv->reg_base + GIO_MASK(bank->id),
+				       imask);
+		}
+	}
+
+	return 0;
+}
+
+#else
+#define brcmstb_gpio_suspend	NULL
+#define brcmstb_gpio_resume	NULL
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
+	.suspend_noirq	= brcmstb_gpio_suspend,
+	.resume_noirq = brcmstb_gpio_resume,
+};
+
+static int brcmstb_gpio_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void __iomem *reg_base;
+	struct brcmstb_gpio_priv *priv;
+	struct resource *res;
+	struct property *prop;
+	const __be32 *p;
+	u32 bank_width;
+	int num_banks = 0;
+	int err;
+	static int gpio_base;
+	struct bgpio_chip *bgc;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, priv);
+	INIT_LIST_HEAD(&priv->bank_list);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	reg_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(reg_base))
+		return PTR_ERR(reg_base);
+
+	priv->gpio_base = gpio_base;
+	priv->reg_base = reg_base;
+	priv->pdev = pdev;
+
+	if (of_property_read_bool(np, "interrupt-controller")) {
+		priv->parent_irq = platform_get_irq(pdev, 0);
+		if (priv->parent_irq < 0) {
+#ifdef CONFIG_BCM7120_L2_IRQ
+			dev_err(dev, "Couldn't get IRQ");
+			return -ENOENT;
+#else
+			/* TODO: change back when BCM7120_L2_IRQ is default */
+			dev_warn(dev, "Couldn't get IRQ. Enable CONFIG_BCM7120_L2_IRQ if you want GPIO interrupt support\n");
+#endif
+		}
+	} else {
+		priv->parent_irq = -ENOENT;
+	}
+
+	if (brcmstb_gpio_sanity_check_banks(dev, np, res))
+		return -EINVAL;
+
+	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
+			bank_width) {
+		struct brcmstb_gpio_bank *bank;
+		struct gpio_chip *gc;
+
+		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
+		if (!bank) {
+			err = -ENOMEM;
+			goto fail;
+		}
+
+		bank->parent_priv = priv;
+		bank->id = num_banks;
+		if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
+			dev_err(dev, "Invalid bank width %d\n", bank_width);
+			err = -EINVAL;
+			goto fail;
+		} else {
+			bank->width = bank_width;
+		}
+
+		/*
+		 * Regs are 4 bytes wide, have data reg, no set/clear regs,
+		 * and direction bits have 0 = output and 1 = input
+		 */
+		bgc = &bank->bgc;
+		err = bgpio_init(bgc, dev, 4,
+				reg_base + GIO_DATA(bank->id),
+				NULL, NULL, NULL,
+				reg_base + GIO_IODIR(bank->id), 0);
+		if (err) {
+			dev_err(dev, "bgpio_init() failed\n");
+			goto fail;
+		}
+
+		gc = &bgc->gc;
+		gc->of_node = np;
+		gc->owner = THIS_MODULE;
+		gc->label = np->full_name;
+		gc->base = gpio_base;
+		gc->of_gpio_n_cells = 2;
+		gc->of_xlate = brcmstb_gpio_of_xlate;
+		/* not all ngpio lines are valid, will use bank width later */
+		gc->ngpio = MAX_GPIO_PER_BANK;
+		if (priv->parent_irq >= 0)
+			gc->to_irq = brcmstb_gpio_to_irq;
+
+		/*
+		 * Mask all interrupts by default, since wakeup interrupts may
+		 * be retained from S5 cold boot
+		 */
+		bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0);
+
+		err = gpiochip_add(gc);
+		if (err) {
+			dev_err(dev, "Could not add gpiochip for bank %d\n",
+					bank->id);
+			/*
+			 * In premise, should go to post_gpio_init_fail but
+			 * since that calls bgpio_remove() which just calls
+			 * gpiochip_remove() it would crash.
+			 */
+			goto fail;
+		}
+		gpio_base += gc->ngpio;
+
+		dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
+			gc->base, gc->ngpio, bank->width);
+
+		/* Everything looks good, so add bank to list */
+		list_add(&bank->node, &priv->bank_list);
+
+		num_banks++;
+	}
+
+	priv->num_gpios = gpio_base - priv->gpio_base;
+	if (priv->parent_irq >= 0) {
+		err = brcmstb_gpio_irq_setup(pdev, priv);
+		if (err)
+			goto fail;
+	}
+
+	dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
+			num_banks, priv->gpio_base, gpio_base - 1);
+
+	return 0;
+
+fail:
+	(void) brcmstb_gpio_remove(pdev);
+	return err;
+}
+
+static struct of_device_id brcmstb_gpio_of_match[] = {
+	{ .compatible = "brcm,brcmstb-gpio" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
+
+static struct platform_driver brcmstb_gpio_driver = {
+	.driver = {
+		.name = "brcmstb-gpio",
+		.of_match_table = brcmstb_gpio_of_match,
+		.pm = &brcmstb_gpio_pm_ops,
+	},
+	.probe = brcmstb_gpio_probe,
+	.remove = brcmstb_gpio_remove,
+};
+
+static int __init brcmstb_gpio_init(void)
+{
+	return platform_driver_register(&brcmstb_gpio_driver);
+}
+subsys_initcall(brcmstb_gpio_init);
+
+static void __exit brcmstb_gpio_exit(void)
+{
+	platform_driver_unregister(&brcmstb_gpio_driver);
+}
+module_exit(brcmstb_gpio_exit);
+
+MODULE_AUTHOR("Gregory Fong");
+MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c
index d2196bf73847..788391658273 100644
--- a/drivers/gpio/gpio-generic.c
+++ b/drivers/gpio/gpio-generic.c
@@ -218,6 +218,14 @@ static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 	return 0;
 }
 
+static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct bgpio_chip *bgc = to_bgpio_chip(gc);
+
+	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
+	       GPIOF_DIR_OUT : GPIOF_DIR_IN;
+}
+
 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 {
 	struct bgpio_chip *bgc = to_bgpio_chip(gc);
@@ -267,6 +275,14 @@ static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
 	return 0;
 }
 
+static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct bgpio_chip *bgc = to_bgpio_chip(gc);
+
+	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
+	       GPIOF_DIR_IN : GPIOF_DIR_OUT;
+}
+
 static int bgpio_setup_accessors(struct device *dev,
 				 struct bgpio_chip *bgc,
 				 bool bit_be,
@@ -376,10 +392,12 @@ static int bgpio_setup_direction(struct bgpio_chip *bgc,
 		bgc->reg_dir = dirout;
 		bgc->gc.direction_output = bgpio_dir_out;
 		bgc->gc.direction_input = bgpio_dir_in;
+		bgc->gc.get_direction = bgpio_get_dir;
 	} else if (dirin) {
 		bgc->reg_dir = dirin;
 		bgc->gc.direction_output = bgpio_dir_out_inv;
 		bgc->gc.direction_input = bgpio_dir_in_inv;
+		bgc->gc.get_direction = bgpio_get_dir_inv;
 	} else {
 		bgc->gc.direction_output = bgpio_simple_dir_out;
 		bgc->gc.direction_input = bgpio_simple_dir_in;
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index a03e18f5e562..3b9f10e29d59 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -66,9 +66,7 @@ struct gpio_desc {
 #define GPIO_FLAGS_MASK		((1 << ID_SHIFT) - 1)
 #define GPIO_TRIGGER_MASK	(BIT(FLAG_TRIG_FALL) | BIT(FLAG_TRIG_RISE))
 
-#ifdef CONFIG_DEBUG_FS
 	const char		*label;
-#endif
 };
 static struct gpio_desc gpio_desc[ARCH_NR_GPIOS];
 
@@ -87,7 +85,6 @@ static void gpiod_free(struct gpio_desc *desc);
 
 /* With descriptor prefix */
 
-#ifdef CONFIG_DEBUG_FS
 #define gpiod_emerg(desc, fmt, ...)					       \
 	pr_emerg("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label ? : "?",\
                  ##__VA_ARGS__)
@@ -106,20 +103,6 @@ static void gpiod_free(struct gpio_desc *desc);
 #define gpiod_dbg(desc, fmt, ...)					       \
 	pr_debug("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label ? : "?",\
                  ##__VA_ARGS__)
-#else
-#define gpiod_emerg(desc, fmt, ...)					\
-	pr_emerg("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_crit(desc, fmt, ...)					\
-	pr_crit("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_err(desc, fmt, ...)					\
-	pr_err("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_warn(desc, fmt, ...)					\
-	pr_warn("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_info(desc, fmt, ...)					\
-	pr_info("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#define gpiod_dbg(desc, fmt, ...)					\
-	pr_debug("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
-#endif
 
 /* With chip prefix */
 
@@ -138,9 +121,7 @@ static void gpiod_free(struct gpio_desc *desc);
 
 static inline void desc_set_label(struct gpio_desc *d, const char *label)
 {
-#ifdef CONFIG_DEBUG_FS
 	d->label = label;
-#endif
 }
 
 /*
@@ -164,16 +145,17 @@ struct gpio_desc *gpio_to_desc(unsigned gpio)
 EXPORT_SYMBOL_GPL(gpio_to_desc);
 
 /**
- * Convert an offset on a certain chip to a corresponding descriptor
+ * Get the GPIO descriptor corresponding to the given hw number for this chip.
  */
-static struct gpio_desc *gpiochip_offset_to_desc(struct gpio_chip *chip,
-						 unsigned int offset)
+struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
+				    u16 hwnum)
 {
-	if (offset >= chip->ngpio)
+	if (hwnum >= chip->ngpio)
 		return ERR_PTR(-EINVAL);
 
-	return &chip->desc[offset];
+	return &chip->desc[hwnum];
 }
+EXPORT_SYMBOL_GPL(gpiochip_get_desc);
 
 /**
  * Convert a GPIO descriptor to the integer namespace.
@@ -350,9 +332,9 @@ static ssize_t gpio_direction_store(struct device *dev,
 	if (!test_bit(FLAG_EXPORT, &desc->flags))
 		status = -EIO;
 	else if (sysfs_streq(buf, "high"))
-		status = gpiod_direction_output(desc, 1);
+		status = gpiod_direction_output_raw(desc, 1);
 	else if (sysfs_streq(buf, "out") || sysfs_streq(buf, "low"))
-		status = gpiod_direction_output(desc, 0);
+		status = gpiod_direction_output_raw(desc, 0);
 	else if (sysfs_streq(buf, "in"))
 		status = gpiod_direction_input(desc);
 	else
@@ -1272,6 +1254,9 @@ fail:
 }
 EXPORT_SYMBOL_GPL(gpiochip_add);
 
+/* Forward-declaration */
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip);
+
 /**
  * gpiochip_remove() - unregister a gpio_chip
  * @chip: the chip to unregister
@@ -1288,6 +1273,7 @@ int gpiochip_remove(struct gpio_chip *chip)
 
 	spin_lock_irqsave(&gpio_lock, flags);
 
+	gpiochip_irqchip_remove(chip);
 	gpiochip_remove_pin_ranges(chip);
 	of_gpiochip_remove(chip);
 	acpi_gpiochip_remove(chip);
@@ -1355,6 +1341,240 @@ static struct gpio_chip *find_chip_by_name(const char *name)
 	return gpiochip_find((void *)name, gpiochip_match_name);
 }
 
+#ifdef CONFIG_GPIOLIB_IRQCHIP
+
+/*
+ * The following is irqchip helper code for gpiochips.
+ */
+
+/**
+ * gpiochip_add_chained_irqchip() - adds a chained irqchip to a gpiochip
+ * @gpiochip: the gpiochip to add the irqchip to
+ * @irqchip: the irqchip to add to the gpiochip
+ * @parent_irq: the irq number corresponding to the parent IRQ for this
+ * chained irqchip
+ * @parent_handler: the parent interrupt handler for the accumulated IRQ
+ * coming out of the gpiochip
+ */
+void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
+				  struct irq_chip *irqchip,
+				  int parent_irq,
+				  irq_flow_handler_t parent_handler)
+{
+	if (gpiochip->can_sleep) {
+		chip_err(gpiochip, "you cannot have chained interrupts on a chip that may sleep\n");
+		return;
+	}
+
+	/*
+	 * The parent irqchip is already using the chip_data for this
+	 * irqchip, so our callbacks simply use the handler_data.
+	 */
+	irq_set_handler_data(parent_irq, gpiochip);
+	irq_set_chained_handler(parent_irq, parent_handler);
+}
+EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpiochip_irq_lock_class;
+
+/**
+ * gpiochip_irq_map() - maps an IRQ into a GPIO irqchip
+ * @d: the irqdomain used by this irqchip
+ * @irq: the global irq number used by this GPIO irqchip irq
+ * @hwirq: the local IRQ/GPIO line offset on this gpiochip
+ *
+ * This function will set up the mapping for a certain IRQ line on a
+ * gpiochip by assigning the gpiochip as chip data, and using the irqchip
+ * stored inside the gpiochip.
+ */
+static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
+			    irq_hw_number_t hwirq)
+{
+	struct gpio_chip *chip = d->host_data;
+
+	irq_set_chip_data(irq, chip);
+	irq_set_lockdep_class(irq, &gpiochip_irq_lock_class);
+	irq_set_chip_and_handler(irq, chip->irqchip, chip->irq_handler);
+	/* Chips that can sleep need nested thread handlers */
+	if (chip->can_sleep)
+		irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+	set_irq_flags(irq, IRQF_VALID);
+#else
+	irq_set_noprobe(irq);
+#endif
+	/*
+	 * No set-up of the hardware will happen if IRQ_TYPE_NONE
+	 * is passed as default type.
+	 */
+	if (chip->irq_default_type != IRQ_TYPE_NONE)
+		irq_set_irq_type(irq, chip->irq_default_type);
+
+	return 0;
+}
+
+static void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)
+{
+	struct gpio_chip *chip = d->host_data;
+
+#ifdef CONFIG_ARM
+	set_irq_flags(irq, 0);
+#endif
+	if (chip->can_sleep)
+		irq_set_nested_thread(irq, 0);
+	irq_set_chip_and_handler(irq, NULL, NULL);
+	irq_set_chip_data(irq, NULL);
+}
+
+static const struct irq_domain_ops gpiochip_domain_ops = {
+	.map	= gpiochip_irq_map,
+	.unmap	= gpiochip_irq_unmap,
+	/* Virtually all GPIO irqchips are twocell:ed */
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static int gpiochip_irq_reqres(struct irq_data *d)
+{
+	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+
+	if (gpio_lock_as_irq(chip, d->hwirq)) {
+		chip_err(chip,
+			"unable to lock HW IRQ %lu for IRQ\n",
+			d->hwirq);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void gpiochip_irq_relres(struct irq_data *d)
+{
+	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+
+	gpio_unlock_as_irq(chip, d->hwirq);
+}
+
+static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	return irq_find_mapping(chip->irqdomain, offset);
+}
+
+/**
+ * gpiochip_irqchip_remove() - removes an irqchip added to a gpiochip
+ * @gpiochip: the gpiochip to remove the irqchip from
+ *
+ * This is called only from gpiochip_remove()
+ */
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip)
+{
+	unsigned int offset;
+
+	/* Remove all IRQ mappings and delete the domain */
+	if (gpiochip->irqdomain) {
+		for (offset = 0; offset < gpiochip->ngpio; offset++)
+			irq_dispose_mapping(gpiochip->irq_base + offset);
+		irq_domain_remove(gpiochip->irqdomain);
+	}
+
+	if (gpiochip->irqchip) {
+		gpiochip->irqchip->irq_request_resources = NULL;
+		gpiochip->irqchip->irq_release_resources = NULL;
+		gpiochip->irqchip = NULL;
+	}
+}
+
+/**
+ * gpiochip_irqchip_add() - adds an irqchip to a gpiochip
+ * @gpiochip: the gpiochip to add the irqchip to
+ * @irqchip: the irqchip to add to the gpiochip
+ * @first_irq: if not dynamically assigned, the base (first) IRQ to
+ * allocate gpiochip irqs from
+ * @handler: the irq handler to use (often a predefined irq core function)
+ * @type: the default type for IRQs on this irqchip, pass IRQ_TYPE_NONE
+ * to have the core avoid setting up any default type in the hardware.
+ *
+ * This function closely associates a certain irqchip with a certain
+ * gpiochip, providing an irq domain to translate the local IRQs to
+ * global irqs in the gpiolib core, and making sure that the gpiochip
+ * is passed as chip data to all related functions. Driver callbacks
+ * need to use container_of() to get their local state containers back
+ * from the gpiochip passed as chip data. An irqdomain will be stored
+ * in the gpiochip that shall be used by the driver to handle IRQ number
+ * translation. The gpiochip will need to be initialized and registered
+ * before calling this function.
+ *
+ * This function will handle two cell:ed simple IRQs and assumes all
+ * the pins on the gpiochip can generate a unique IRQ. Everything else
+ * need to be open coded.
+ */
+int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
+			 struct irq_chip *irqchip,
+			 unsigned int first_irq,
+			 irq_flow_handler_t handler,
+			 unsigned int type)
+{
+	struct device_node *of_node;
+	unsigned int offset;
+	unsigned irq_base = 0;
+
+	if (!gpiochip || !irqchip)
+		return -EINVAL;
+
+	if (!gpiochip->dev) {
+		pr_err("missing gpiochip .dev parent pointer\n");
+		return -EINVAL;
+	}
+	of_node = gpiochip->dev->of_node;
+#ifdef CONFIG_OF_GPIO
+	/*
+	 * If the gpiochip has an assigned OF node this takes precendence
+	 * FIXME: get rid of this and use gpiochip->dev->of_node everywhere
+	 */
+	if (gpiochip->of_node)
+		of_node = gpiochip->of_node;
+#endif
+	gpiochip->irqchip = irqchip;
+	gpiochip->irq_handler = handler;
+	gpiochip->irq_default_type = type;
+	gpiochip->to_irq = gpiochip_to_irq;
+	gpiochip->irqdomain = irq_domain_add_simple(of_node,
+					gpiochip->ngpio, first_irq,
+					&gpiochip_domain_ops, gpiochip);
+	if (!gpiochip->irqdomain) {
+		gpiochip->irqchip = NULL;
+		return -EINVAL;
+	}
+	irqchip->irq_request_resources = gpiochip_irq_reqres;
+	irqchip->irq_release_resources = gpiochip_irq_relres;
+
+	/*
+	 * Prepare the mapping since the irqchip shall be orthogonal to
+	 * any gpiochip calls. If the first_irq was zero, this is
+	 * necessary to allocate descriptors for all IRQs.
+	 */
+	for (offset = 0; offset < gpiochip->ngpio; offset++) {
+		irq_base = irq_create_mapping(gpiochip->irqdomain, offset);
+		if (offset == 0)
+			/*
+			 * Store the base into the gpiochip to be used when
+			 * unmapping the irqs.
+			 */
+			gpiochip->irq_base = irq_base;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(gpiochip_irqchip_add);
+
+#else /* CONFIG_GPIOLIB_IRQCHIP */
+
+static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip) {}
+
+#endif /* CONFIG_GPIOLIB_IRQCHIP */
+
 #ifdef CONFIG_PINCTRL
 
 /**
@@ -1475,26 +1695,14 @@ EXPORT_SYMBOL_GPL(gpiochip_remove_pin_ranges);
  * on each other, and help provide better diagnostics in debugfs.
  * They're called even less than the "set direction" calls.
  */
-static int gpiod_request(struct gpio_desc *desc, const char *label)
+static int __gpiod_request(struct gpio_desc *desc, const char *label)
 {
-	struct gpio_chip	*chip;
-	int			status = -EPROBE_DEFER;
+	struct gpio_chip	*chip = desc->chip;
+	int			status;
 	unsigned long		flags;
 
-	if (!desc) {
-		pr_warn("%s: invalid GPIO\n", __func__);
-		return -EINVAL;
-	}
-
 	spin_lock_irqsave(&gpio_lock, flags);
 
-	chip = desc->chip;
-	if (chip == NULL)
-		goto done;
-
-	if (!try_module_get(chip->owner))
-		goto done;
-
 	/* NOTE:  gpio_request() can be called in early boot,
 	 * before IRQs are enabled, for non-sleeping (SOC) GPIOs.
 	 */
@@ -1504,7 +1712,6 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
 		status = 0;
 	} else {
 		status = -EBUSY;
-		module_put(chip->owner);
 		goto done;
 	}
 
@@ -1516,7 +1723,6 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
 
 		if (status < 0) {
 			desc_set_label(desc, NULL);
-			module_put(chip->owner);
 			clear_bit(FLAG_REQUESTED, &desc->flags);
 			goto done;
 		}
@@ -1528,9 +1734,34 @@ static int gpiod_request(struct gpio_desc *desc, const char *label)
 		spin_lock_irqsave(&gpio_lock, flags);
 	}
 done:
+	spin_unlock_irqrestore(&gpio_lock, flags);
+	return status;
+}
+
+static int gpiod_request(struct gpio_desc *desc, const char *label)
+{
+	int status = -EPROBE_DEFER;
+	struct gpio_chip *chip;
+
+	if (!desc) {
+		pr_warn("%s: invalid GPIO\n", __func__);
+		return -EINVAL;
+	}
+
+	chip = desc->chip;
+	if (!chip)
+		goto done;
+
+	if (try_module_get(chip->owner)) {
+		status = __gpiod_request(desc, label);
+		if (status < 0)
+			module_put(chip->owner);
+	}
+
+done:
 	if (status)
 		gpiod_dbg(desc, "%s: status %d\n", __func__, status);
-	spin_unlock_irqrestore(&gpio_lock, flags);
+
 	return status;
 }
 
@@ -1540,18 +1771,14 @@ int gpio_request(unsigned gpio, const char *label)
 }
 EXPORT_SYMBOL_GPL(gpio_request);
 
-static void gpiod_free(struct gpio_desc *desc)
+static bool __gpiod_free(struct gpio_desc *desc)
 {
+	bool			ret = false;
 	unsigned long		flags;
 	struct gpio_chip	*chip;
 
 	might_sleep();
 
-	if (!desc) {
-		WARN_ON(extra_checks);
-		return;
-	}
-
 	gpiod_unexport(desc);
 
 	spin_lock_irqsave(&gpio_lock, flags);
@@ -1565,15 +1792,23 @@ static void gpiod_free(struct gpio_desc *desc)
 			spin_lock_irqsave(&gpio_lock, flags);
 		}
 		desc_set_label(desc, NULL);
-		module_put(desc->chip->owner);
 		clear_bit(FLAG_ACTIVE_LOW, &desc->flags);
 		clear_bit(FLAG_REQUESTED, &desc->flags);
 		clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
 		clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
-	} else
-		WARN_ON(extra_checks);
+		ret = true;
+	}
 
 	spin_unlock_irqrestore(&gpio_lock, flags);
+	return ret;
+}
+
+static void gpiod_free(struct gpio_desc *desc)
+{
+	if (desc && __gpiod_free(desc))
+		module_put(desc->chip->owner);
+	else
+		WARN_ON(extra_checks);
 }
 
 void gpio_free(unsigned gpio)
@@ -1608,7 +1843,7 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
 	if (flags & GPIOF_DIR_IN)
 		err = gpiod_direction_input(desc);
 	else
-		err = gpiod_direction_output(desc,
+		err = gpiod_direction_output_raw(desc,
 				(flags & GPIOF_INIT_HIGH) ? 1 : 0);
 
 	if (err)
@@ -1669,8 +1904,8 @@ EXPORT_SYMBOL_GPL(gpio_free_array);
  * @offset: of signal within controller's 0..(ngpio - 1) range
  *
  * Returns NULL if the GPIO is not currently requested, else a string.
- * If debugfs support is enabled, the string returned is the label passed
- * to gpio_request(); otherwise it is a meaningless constant.
+ * The string returned is the label passed to gpio_request(); if none has been
+ * passed it is a meaningless, non-NULL constant.
  *
  * This function is for use by GPIO controller drivers.  The label can
  * help with diagnostics, and knowing that the signal is used as a GPIO
@@ -1687,14 +1922,41 @@ const char *gpiochip_is_requested(struct gpio_chip *chip, unsigned offset)
 
 	if (test_bit(FLAG_REQUESTED, &desc->flags) == 0)
 		return NULL;
-#ifdef CONFIG_DEBUG_FS
 	return desc->label;
-#else
-	return "?";
-#endif
 }
 EXPORT_SYMBOL_GPL(gpiochip_is_requested);
 
+/**
+ * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor
+ * @desc: GPIO descriptor to request
+ * @label: label for the GPIO
+ *
+ * Function allows GPIO chip drivers to request and use their own GPIO
+ * descriptors via gpiolib API. Difference to gpiod_request() is that this
+ * function will not increase reference count of the GPIO chip module. This
+ * allows the GPIO chip module to be unloaded as needed (we assume that the
+ * GPIO chip driver handles freeing the GPIOs it has requested).
+ */
+int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label)
+{
+	if (!desc || !desc->chip)
+		return -EINVAL;
+
+	return __gpiod_request(desc, label);
+}
+
+/**
+ * gpiochip_free_own_desc - Free GPIO requested by the chip driver
+ * @desc: GPIO descriptor to free
+ *
+ * Function frees the given GPIO requested previously with
+ * gpiochip_request_own_desc().
+ */
+void gpiochip_free_own_desc(struct gpio_desc *desc)
+{
+	if (desc)
+		__gpiod_free(desc);
+}
 
 /* Drivers MUST set GPIO direction before making get/set calls.  In
  * some cases this is done in early boot, before IRQs are enabled.
@@ -1774,28 +2036,13 @@ fail:
 }
 EXPORT_SYMBOL_GPL(gpiod_direction_input);
 
-/**
- * gpiod_direction_output - set the GPIO direction to input
- * @desc:	GPIO to set to output
- * @value:	initial output value of the GPIO
- *
- * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
- * be called safely on it. The initial value of the output must be specified.
- *
- * Return 0 in case of success, else an error code.
- */
-int gpiod_direction_output(struct gpio_desc *desc, int value)
+static int _gpiod_direction_output_raw(struct gpio_desc *desc, int value)
 {
 	unsigned long		flags;
 	struct gpio_chip	*chip;
 	int			status = -EINVAL;
 	int offset;
 
-	if (!desc || !desc->chip) {
-		pr_warn("%s: invalid GPIO\n", __func__);
-		return -EINVAL;
-	}
-
 	/* GPIOs used for IRQs shall not be set as output */
 	if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
 		gpiod_err(desc,
@@ -1858,6 +2105,50 @@ fail:
 		gpiod_dbg(desc, "%s: gpio status %d\n", __func__, status);
 	return status;
 }
+
+/**
+ * gpiod_direction_output_raw - set the GPIO direction to output
+ * @desc:	GPIO to set to output
+ * @value:	initial output value of the GPIO
+ *
+ * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
+ * be called safely on it. The initial value of the output must be specified
+ * as raw value on the physical line without regard for the ACTIVE_LOW status.
+ *
+ * Return 0 in case of success, else an error code.
+ */
+int gpiod_direction_output_raw(struct gpio_desc *desc, int value)
+{
+	if (!desc || !desc->chip) {
+		pr_warn("%s: invalid GPIO\n", __func__);
+		return -EINVAL;
+	}
+	return _gpiod_direction_output_raw(desc, value);
+}
+EXPORT_SYMBOL_GPL(gpiod_direction_output_raw);
+
+/**
+ * gpiod_direction_output - set the GPIO direction to output
+ * @desc:	GPIO to set to output
+ * @value:	initial output value of the GPIO
+ *
+ * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
+ * be called safely on it. The initial value of the output must be specified
+ * as the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
+ * account.
+ *
+ * Return 0 in case of success, else an error code.
+ */
+int gpiod_direction_output(struct gpio_desc *desc, int value)
+{
+	if (!desc || !desc->chip) {
+		pr_warn("%s: invalid GPIO\n", __func__);
+		return -EINVAL;
+	}
+	if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
+		value = !value;
+	return _gpiod_direction_output_raw(desc, value);
+}
 EXPORT_SYMBOL_GPL(gpiod_direction_output);
 
 /**
@@ -2155,10 +2446,7 @@ EXPORT_SYMBOL_GPL(gpiod_to_irq);
  * @gpio: the GPIO line to lock as used for IRQ
  *
  * This is used directly by GPIO drivers that want to lock down
- * a certain GPIO line to be used as IRQs, for example in the
- * .to_irq() callback of their gpio_chip, or in the .irq_enable()
- * of its irq_chip implementation if the GPIO is known from that
- * code.
+ * a certain GPIO line to be used for IRQs.
  */
 int gpiod_lock_as_irq(struct gpio_desc *desc)
 {
@@ -2179,7 +2467,7 @@ EXPORT_SYMBOL_GPL(gpiod_lock_as_irq);
 
 int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
 {
-	return gpiod_lock_as_irq(gpiochip_offset_to_desc(chip, offset));
+	return gpiod_lock_as_irq(gpiochip_get_desc(chip, offset));
 }
 EXPORT_SYMBOL_GPL(gpio_lock_as_irq);
 
@@ -2201,7 +2489,7 @@ EXPORT_SYMBOL_GPL(gpiod_unlock_as_irq);
 
 void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
 {
-	return gpiod_unlock_as_irq(gpiochip_offset_to_desc(chip, offset));
+	return gpiod_unlock_as_irq(gpiochip_get_desc(chip, offset));
 }
 EXPORT_SYMBOL_GPL(gpio_unlock_as_irq);
 
@@ -2302,22 +2590,27 @@ void gpiod_add_lookup_table(struct gpiod_lookup_table *table)
 	mutex_unlock(&gpio_lookup_lock);
 }
 
-#ifdef CONFIG_OF
 static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
 				      unsigned int idx,
 				      enum gpio_lookup_flags *flags)
 {
+	static const char *suffixes[] = { "gpios", "gpio" };
 	char prop_name[32]; /* 32 is max size of property name */
 	enum of_gpio_flags of_flags;
 	struct gpio_desc *desc;
+	unsigned int i;
 
-	if (con_id)
-		snprintf(prop_name, 32, "%s-gpios", con_id);
-	else
-		snprintf(prop_name, 32, "gpios");
+	for (i = 0; i < ARRAY_SIZE(suffixes); i++) {
+		if (con_id)
+			snprintf(prop_name, 32, "%s-%s", con_id, suffixes[i]);
+		else
+			snprintf(prop_name, 32, "%s", suffixes[i]);
 
-	desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
-					&of_flags);
+		desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
+						&of_flags);
+		if (!IS_ERR(desc) || (PTR_ERR(desc) == -EPROBE_DEFER))
+			break;
+	}
 
 	if (IS_ERR(desc))
 		return desc;
@@ -2327,14 +2620,6 @@ static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
 
 	return desc;
 }
-#else
-static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
-				      unsigned int idx,
-				      enum gpio_lookup_flags *flags)
-{
-	return ERR_PTR(-ENODEV);
-}
-#endif
 
 static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
 					unsigned int idx,
@@ -2422,7 +2707,7 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
 			return ERR_PTR(-EINVAL);
 		}
 
-		desc = gpiochip_offset_to_desc(chip, p->chip_hwnum);
+		desc = gpiochip_get_desc(chip, p->chip_hwnum);
 		*flags = p->flags;
 
 		return desc;
@@ -2432,7 +2717,7 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
 }
 
 /**
- * gpio_get - obtain a GPIO for a given GPIO function
+ * gpiod_get - obtain a GPIO for a given GPIO function
  * @dev:	GPIO consumer, can be NULL for system-global GPIOs
  * @con_id:	function within the GPIO consumer
  *
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index 82be586c1f90..cf092941a9fd 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -43,4 +43,7 @@ acpi_get_gpiod_by_index(struct device *dev, int index,
 }
 #endif
 
+int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label);
+void gpiochip_free_own_desc(struct gpio_desc *desc);
+
 #endif /* GPIOLIB_H */
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 7703e3bc604b..f0f93a20d890 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1210,6 +1210,16 @@ config SENSORS_SCH5636
 	  This driver can also be built as a module.  If so, the module
 	  will be called sch5636.
 
+config SENSORS_ADC128D818
+	tristate "Texas Instruments ADC128D818"
+	depends on I2C
+	help
+	  If you say yes here you get support for the Texas Instruments
+	  ADC128D818 System Monitor with Temperature Sensor chip.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called adc128d818.
+
 config SENSORS_ADS1015
 	tristate "Texas Instruments ADS1015"
 	depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index ec7cde06eb52..0831dbcd3ef2 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SENSORS_ABITUGURU3)+= abituguru3.o
 obj-$(CONFIG_SENSORS_AD7314)	+= ad7314.o
 obj-$(CONFIG_SENSORS_AD7414)	+= ad7414.o
 obj-$(CONFIG_SENSORS_AD7418)	+= ad7418.o
+obj-$(CONFIG_SENSORS_ADC128D818) += adc128d818.o
 obj-$(CONFIG_SENSORS_ADCXX)	+= adcxx.o
 obj-$(CONFIG_SENSORS_ADM1021)	+= adm1021.o
 obj-$(CONFIG_SENSORS_ADM1025)	+= adm1025.o
diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c
new file mode 100644
index 000000000000..1c23cb7a23a9
--- /dev/null
+++ b/drivers/hwmon/adc128d818.c
@@ -0,0 +1,577 @@
+/*
+ * Driver for TI ADC128D818 System Monitor with Temperature Sensor
+ *
+ * Copyright (c) 2014 Guenter Roeck
+ * Copyright (c) 2014 Andreas Oberritter
+ *
+ * Derived from lm80.c
+ * Copyright (C) 1998, 1999  Frodo Looijaard <frodol@dds.nl>
+ *			     and Philip Edelbrock <phil@netroedge.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mutex.h>
+#include <linux/platform_data/adc128d818.h>
+
+/* Addresses to scan
+ * The chip also supports addresses 0x35..0x37. Don't scan those addresses
+ * since they are also used by some EEPROMs, which may result in false
+ * positives.
+ */
+static const unsigned short normal_i2c[] = {
+	0x1d, 0x1e, 0x1f, 0x2d, 0x2e, 0x2f, I2C_CLIENT_END };
+
+/* registers */
+#define ADC128_REG_IN_MAX(nr)		(0x2a + (nr) * 2)
+#define ADC128_REG_IN_MIN(nr)		(0x2b + (nr) * 2)
+#define ADC128_REG_IN(nr)		(0x20 + (nr))
+
+#define ADC128_REG_TEMP			0x27
+#define ADC128_REG_TEMP_MAX		0x38
+#define ADC128_REG_TEMP_HYST		0x39
+
+#define ADC128_REG_CONFIG		0x00
+#define ADC128_REG_ALARM		0x01
+#define ADC128_REG_MASK			0x03
+#define ADC128_REG_CONV_RATE		0x07
+#define ADC128_REG_ONESHOT		0x09
+#define ADC128_REG_SHUTDOWN		0x0a
+#define ADC128_REG_CONFIG_ADV		0x0b
+#define ADC128_REG_BUSY_STATUS		0x0c
+
+#define ADC128_REG_MAN_ID		0x3e
+#define ADC128_REG_DEV_ID		0x3f
+
+struct adc128_data {
+	struct i2c_client *client;
+	struct regulator *regulator;
+	int vref;		/* Reference voltage in mV */
+	struct mutex update_lock;
+	bool valid;		/* true if following fields are valid */
+	unsigned long last_updated;	/* In jiffies */
+	unsigned int mode;	/* Mode of operation */
+	unsigned int vlt_channels;	/* Number of voltage channels */
+
+	u16 in[3][8];		/* Register value, normalized to 12 bit
+				 * 0: input voltage
+				 * 1: min limit
+				 * 2: max limit
+				 */
+	s16 temp[3];		/* Register value, normalized to 9 bit
+				 * 0: sensor 1: limit 2: hyst
+				 */
+	u8 alarms;		/* alarm register value */
+};
+
+static struct adc128_data *adc128_update_device(struct device *dev)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	struct i2c_client *client = data->client;
+	struct adc128_data *ret = data;
+	int i, rv;
+
+	mutex_lock(&data->update_lock);
+
+	if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
+		for (i = 0; i < data->vlt_channels; i++) {
+			rv = i2c_smbus_read_word_swapped(client,
+							 ADC128_REG_IN(i));
+			if (rv < 0)
+				goto abort;
+			data->in[0][i] = rv >> 4;
+
+			rv = i2c_smbus_read_byte_data(client,
+						      ADC128_REG_IN_MIN(i));
+			if (rv < 0)
+				goto abort;
+			data->in[1][i] = rv << 4;
+
+			rv = i2c_smbus_read_byte_data(client,
+						      ADC128_REG_IN_MAX(i));
+			if (rv < 0)
+				goto abort;
+			data->in[2][i] = rv << 4;
+		}
+
+		if (data->vlt_channels < 8) {
+			rv = i2c_smbus_read_word_swapped(client, ADC128_REG_TEMP);
+			if (rv < 0)
+				goto abort;
+			data->temp[0] = rv >> 7;
+
+			rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_MAX);
+			if (rv < 0)
+				goto abort;
+			data->temp[1] = rv << 1;
+
+			rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_HYST);
+			if (rv < 0)
+				goto abort;
+			data->temp[2] = rv << 1;
+		}
+
+		rv = i2c_smbus_read_byte_data(client, ADC128_REG_ALARM);
+		if (rv < 0)
+			goto abort;
+		data->alarms |= rv;
+
+		data->last_updated = jiffies;
+		data->valid = true;
+	}
+	goto done;
+
+abort:
+	ret = ERR_PTR(rv);
+	data->valid = false;
+done:
+	mutex_unlock(&data->update_lock);
+	return ret;
+}
+
+static ssize_t adc128_show_in(struct device *dev, struct device_attribute *attr,
+			      char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int index = to_sensor_dev_attr_2(attr)->index;
+	int nr = to_sensor_dev_attr_2(attr)->nr;
+	int val;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	val = DIV_ROUND_CLOSEST(data->in[index][nr] * data->vref, 4095);
+	return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t adc128_set_in(struct device *dev, struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	int index = to_sensor_dev_attr_2(attr)->index;
+	int nr = to_sensor_dev_attr_2(attr)->nr;
+	u8 reg, regval;
+	long val;
+	int err;
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	mutex_lock(&data->update_lock);
+	/* 10 mV LSB on limit registers */
+	regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255);
+	data->in[index][nr] = regval << 4;
+	reg = index == 1 ? ADC128_REG_IN_MIN(nr) : ADC128_REG_IN_MAX(nr);
+	i2c_smbus_write_byte_data(data->client, reg, regval);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+static ssize_t adc128_show_temp(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int index = to_sensor_dev_attr(attr)->index;
+	int temp;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	temp = (data->temp[index] << 7) >> 7;	/* sign extend */
+	return sprintf(buf, "%d\n", temp * 500);/* 0.5 degrees C resolution */
+}
+
+static ssize_t adc128_set_temp(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	int index = to_sensor_dev_attr(attr)->index;
+	long val;
+	int err;
+	s8 regval;
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	mutex_lock(&data->update_lock);
+	regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
+	data->temp[index] = regval << 1;
+	i2c_smbus_write_byte_data(data->client,
+				  index == 1 ? ADC128_REG_TEMP_MAX
+					     : ADC128_REG_TEMP_HYST,
+				  regval);
+	mutex_unlock(&data->update_lock);
+
+	return count;
+}
+
+static ssize_t adc128_show_alarm(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+	int mask = 1 << to_sensor_dev_attr(attr)->index;
+	u8 alarms;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	/*
+	 * Clear an alarm after reporting it to user space. If it is still
+	 * active, the next update sequence will set the alarm bit again.
+	 */
+	alarms = data->alarms;
+	data->alarms &= ~mask;
+
+	return sprintf(buf, "%u\n", !!(alarms & mask));
+}
+
+static int adc128_set_config_adv(struct adc128_data *data)
+{
+	unsigned int nchannels_lut[] = { 7, 8, 4, 6 };
+	u8 regval;
+	int err;
+
+	BUG_ON(data->mode > 3);
+
+	mutex_lock(&data->update_lock);
+	regval = (data->mode << 1);
+	/* If external vref is selected, configure the chip to use it */
+	if (data->regulator)
+		regval |= 0x01;
+	err = i2c_smbus_write_byte_data(data->client, ADC128_REG_CONFIG_ADV, regval);
+	data->vlt_channels = nchannels_lut[data->mode];
+	memset(data->in, 0, sizeof(data->in));
+	memset(data->temp, 0, sizeof(data->temp));
+	mutex_unlock(&data->update_lock);
+
+	return err;
+}
+
+static ssize_t adc128_show_mode(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct adc128_data *data = adc128_update_device(dev);
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	return sprintf(buf, "%u\n", data->mode);
+}
+
+static ssize_t adc128_set_mode(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct adc128_data *data = dev_get_drvdata(dev);
+	long val;
+	int err;
+
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	err = kstrtol(buf, 10, &val);
+	if (err < 0)
+		return err;
+
+	if (val < 0 || val > 3)
+		return -EINVAL;
+
+	data->mode = val;
+	err = adc128_set_config_adv(data);
+	if (err < 0)
+		return err;
+
+	return count;
+}
+
+static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO,
+			    adc128_show_in, NULL, 0, 0);
+static SENSOR_DEVICE_ATTR_2(in0_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 0, 1);
+static SENSOR_DEVICE_ATTR_2(in0_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 0, 2);
+
+static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO,
+			    adc128_show_in, NULL, 1, 0);
+static SENSOR_DEVICE_ATTR_2(in1_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 1, 1);
+static SENSOR_DEVICE_ATTR_2(in1_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 1, 2);
+
+static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO,
+			    adc128_show_in, NULL, 2, 0);
+static SENSOR_DEVICE_ATTR_2(in2_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 2, 1);
+static SENSOR_DEVICE_ATTR_2(in2_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 2, 2);
+
+static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO,
+			    adc128_show_in, NULL, 3, 0);
+static SENSOR_DEVICE_ATTR_2(in3_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 3, 1);
+static SENSOR_DEVICE_ATTR_2(in3_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 3, 2);
+
+static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO,
+			    adc128_show_in, NULL, 4, 0);
+static SENSOR_DEVICE_ATTR_2(in4_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 4, 1);
+static SENSOR_DEVICE_ATTR_2(in4_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 4, 2);
+
+static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO,
+			    adc128_show_in, NULL, 5, 0);
+static SENSOR_DEVICE_ATTR_2(in5_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 5, 1);
+static SENSOR_DEVICE_ATTR_2(in5_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 5, 2);
+
+static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO,
+			    adc128_show_in, NULL, 6, 0);
+static SENSOR_DEVICE_ATTR_2(in6_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 6, 1);
+static SENSOR_DEVICE_ATTR_2(in6_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 6, 2);
+
+static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO,
+			    adc128_show_in, NULL, 7, 0);
+static SENSOR_DEVICE_ATTR_2(in7_min, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 7, 1);
+static SENSOR_DEVICE_ATTR_2(in7_max, S_IWUSR | S_IRUGO,
+			    adc128_show_in, adc128_set_in, 7, 2);
+
+static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, adc128_show_temp, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
+			  adc128_show_temp, adc128_set_temp, 1);
+static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IWUSR | S_IRUGO,
+			  adc128_show_temp, adc128_set_temp, 2);
+
+static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, adc128_show_alarm, NULL, 0);
+static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, adc128_show_alarm, NULL, 1);
+static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, adc128_show_alarm, NULL, 2);
+static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, adc128_show_alarm, NULL, 3);
+static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, adc128_show_alarm, NULL, 4);
+static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, adc128_show_alarm, NULL, 5);
+static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, adc128_show_alarm, NULL, 6);
+static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, adc128_show_alarm, NULL, 7);
+static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, adc128_show_alarm, NULL, 7);
+
+static SENSOR_DEVICE_ATTR(mode, S_IWUSR | S_IRUGO, adc128_show_mode, adc128_set_mode, 0);
+
+static struct attribute *adc128_attrs[] = {
+	&sensor_dev_attr_in0_min.dev_attr.attr,
+	&sensor_dev_attr_in1_min.dev_attr.attr,
+	&sensor_dev_attr_in2_min.dev_attr.attr,
+	&sensor_dev_attr_in3_min.dev_attr.attr,
+	&sensor_dev_attr_in4_min.dev_attr.attr,
+	&sensor_dev_attr_in5_min.dev_attr.attr,
+	&sensor_dev_attr_in6_min.dev_attr.attr,
+	&sensor_dev_attr_in7_min.dev_attr.attr,
+	&sensor_dev_attr_in0_max.dev_attr.attr,
+	&sensor_dev_attr_in1_max.dev_attr.attr,
+	&sensor_dev_attr_in2_max.dev_attr.attr,
+	&sensor_dev_attr_in3_max.dev_attr.attr,
+	&sensor_dev_attr_in4_max.dev_attr.attr,
+	&sensor_dev_attr_in5_max.dev_attr.attr,
+	&sensor_dev_attr_in6_max.dev_attr.attr,
+	&sensor_dev_attr_in7_max.dev_attr.attr,
+	&sensor_dev_attr_in0_input.dev_attr.attr,
+	&sensor_dev_attr_in1_input.dev_attr.attr,
+	&sensor_dev_attr_in2_input.dev_attr.attr,
+	&sensor_dev_attr_in3_input.dev_attr.attr,
+	&sensor_dev_attr_in4_input.dev_attr.attr,
+	&sensor_dev_attr_in5_input.dev_attr.attr,
+	&sensor_dev_attr_in6_input.dev_attr.attr,
+	&sensor_dev_attr_in7_input.dev_attr.attr,
+	&sensor_dev_attr_temp1_input.dev_attr.attr,
+	&sensor_dev_attr_temp1_max.dev_attr.attr,
+	&sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
+	&sensor_dev_attr_in0_alarm.dev_attr.attr,
+	&sensor_dev_attr_in1_alarm.dev_attr.attr,
+	&sensor_dev_attr_in2_alarm.dev_attr.attr,
+	&sensor_dev_attr_in3_alarm.dev_attr.attr,
+	&sensor_dev_attr_in4_alarm.dev_attr.attr,
+	&sensor_dev_attr_in5_alarm.dev_attr.attr,
+	&sensor_dev_attr_in6_alarm.dev_attr.attr,
+	&sensor_dev_attr_in7_alarm.dev_attr.attr,
+	&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
+	&sensor_dev_attr_mode.dev_attr.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(adc128);
+
+static int adc128_detect(struct i2c_client *client, struct i2c_board_info *info)
+{
+	int man_id, dev_id;
+
+	if (!i2c_check_functionality(client->adapter,
+				     I2C_FUNC_SMBUS_BYTE_DATA |
+				     I2C_FUNC_SMBUS_WORD_DATA))
+		return -ENODEV;
+
+	man_id = i2c_smbus_read_byte_data(client, ADC128_REG_MAN_ID);
+	dev_id = i2c_smbus_read_byte_data(client, ADC128_REG_DEV_ID);
+	if (man_id != 0x01 || dev_id != 0x09)
+		return -ENODEV;
+
+	/* Check unused bits for confirmation */
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG) & 0xf4)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONV_RATE) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_ONESHOT) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_SHUTDOWN) & 0xfe)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_CONFIG_ADV) & 0xf8)
+		return -ENODEV;
+	if (i2c_smbus_read_byte_data(client, ADC128_REG_BUSY_STATUS) & 0xfc)
+		return -ENODEV;
+
+	strlcpy(info->type, "adc128d818", I2C_NAME_SIZE);
+
+	return 0;
+}
+
+static int adc128_init_client(struct adc128_data *data)
+{
+	struct i2c_client *client = data->client;
+	int err;
+
+	/*
+	 * Reset chip to defaults.
+	 * This makes most other initializations unnecessary.
+	 */
+	err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x80);
+	if (err)
+		return err;
+
+	/* Start monitoring */
+	err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x01);
+	if (err)
+		return err;
+
+	err = adc128_set_config_adv(data);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int adc128_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct adc128_platform_data *pdata;
+	struct device *dev = &client->dev;
+	struct regulator *regulator;
+	struct device *hwmon_dev;
+	struct adc128_data *data;
+	int err, vref;
+
+	data = devm_kzalloc(dev, sizeof(struct adc128_data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	/* vref is optional. If specified, is used as chip reference voltage */
+	regulator = devm_regulator_get_optional(dev, "vref");
+	if (!IS_ERR(regulator)) {
+		data->regulator = regulator;
+		err = regulator_enable(regulator);
+		if (err < 0)
+			return err;
+		vref = regulator_get_voltage(regulator);
+		if (vref < 0) {
+			err = vref;
+			goto error;
+		}
+		data->vref = DIV_ROUND_CLOSEST(vref, 1000);
+	} else {
+		data->vref = 2560;	/* 2.56V, in mV */
+	}
+
+	pdata = dev_get_platdata(dev);
+	if (pdata) {
+		if (pdata->mode > 3) {
+			err = -EINVAL;
+			goto error;
+		}
+		data->mode = pdata->mode;
+	}
+
+	data->client = client;
+	i2c_set_clientdata(client, data);
+	mutex_init(&data->update_lock);
+
+	/* Initialize the chip */
+	err = adc128_init_client(data);
+	if (err < 0)
+		goto error;
+
+	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
+							   data, adc128_groups);
+	if (IS_ERR(hwmon_dev)) {
+		err = PTR_ERR(hwmon_dev);
+		goto error;
+	}
+
+	return 0;
+
+error:
+	if (data->regulator)
+		regulator_disable(data->regulator);
+	return err;
+}
+
+static int adc128_remove(struct i2c_client *client)
+{
+	struct adc128_data *data = i2c_get_clientdata(client);
+
+	if (data->regulator)
+		regulator_disable(data->regulator);
+
+	return 0;
+}
+
+static const struct i2c_device_id adc128_id[] = {
+	{ "adc128d818", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, adc128_id);
+
+static struct i2c_driver adc128_driver = {
+	.class		= I2C_CLASS_HWMON,
+	.driver = {
+		.name	= "adc128d818",
+	},
+	.probe		= adc128_probe,
+	.remove		= adc128_remove,
+	.id_table	= adc128_id,
+	.detect		= adc128_detect,
+	.address_list	= normal_i2c,
+};
+
+module_i2c_driver(adc128_driver);
+
+MODULE_AUTHOR("Guenter Roeck");
+MODULE_DESCRIPTION("Driver for ADC128D818");
+MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
index 84a55eacd903..7b06712b6582 100644
--- a/drivers/hwmon/lm75.c
+++ b/drivers/hwmon/lm75.c
@@ -177,6 +177,10 @@ static const struct attribute_group lm75_group = {
 	.attrs = lm75_attributes,
 };
 
+static const struct thermal_zone_of_device_ops lm75_of_thermal_ops = {
+	.get_temp = lm75_read_temp,
+};
+
 /*-----------------------------------------------------------------------*/
 
 /* device probe and removal */
@@ -290,10 +294,9 @@ lm75_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		goto exit_remove;
 	}
 
-	data->tz = thermal_zone_of_sensor_register(&client->dev,
-						   0,
+	data->tz = thermal_zone_of_sensor_register(&client->dev, 0,
 						   &client->dev,
-						   lm75_read_temp, NULL);
+						   &lm75_of_thermal_ops);
 	if (IS_ERR(data->tz))
 		data->tz = NULL;
 
diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c
index 6748b4583e7b..0f0927199dfc 100644
--- a/drivers/hwmon/tmp102.c
+++ b/drivers/hwmon/tmp102.c
@@ -159,6 +159,10 @@ static const struct attribute_group tmp102_attr_group = {
 #define TMP102_CONFIG  (TMP102_CONF_TM | TMP102_CONF_EM | TMP102_CONF_CR1)
 #define TMP102_CONFIG_RD_ONLY (TMP102_CONF_R0 | TMP102_CONF_R1 | TMP102_CONF_AL)
 
+static const struct thermal_zone_of_device_ops tmp102_of_thermal_ops = {
+	.get_temp = tmp102_read_temp,
+};
+
 static int tmp102_probe(struct i2c_client *client,
 				  const struct i2c_device_id *id)
 {
@@ -218,7 +222,7 @@ static int tmp102_probe(struct i2c_client *client,
 
 	tmp102->tz = thermal_zone_of_sensor_register(&client->dev, 0,
 						     &client->dev,
-						     tmp102_read_temp, NULL);
+						     &tmp102_of_thermal_ops);
 	if (IS_ERR(tmp102->tz))
 		tmp102->tz = NULL;
 
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index c5eec0290b37..e1a9d71cfc45 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1012,4 +1012,14 @@ config SCx200_ACB
 	  This support is also available as a module.  If so, the module
 	  will be called scx200_acb.
 
+config I2C_BRCMSTB
+	tristate "BRCM Settop I2C adapter"
+	depends on BRCMSTB
+	default m
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C interface on the Broadcom Settop SoCs.
+
+	  If you do not need BRCMSTB I2C inteface, say N.
+
 endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index a08931fe73e1..fa1ef380e57a 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -97,5 +97,6 @@ obj-$(CONFIG_I2C_PCA_ISA)	+= i2c-pca-isa.o
 obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_BRCMSTB)	+= i2c-brcmstb.o
 
 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c
new file mode 100644
index 000000000000..45af282c39a2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-brcmstb.c
@@ -0,0 +1,726 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+
+#define N_DATA_REGS					8
+
+/*
+ * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
+ * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
+ * data register whereas STB SoCs use 4 byte per data register transfer,
+ * account for this difference in total count per transaction and mask to
+ * use.
+ */
+#define BSC_CNT_REG1_MASK(nb)	(nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
+#define BSC_CNT_REG1_SHIFT	0
+
+/* BSC CTL register field definitions */
+#define BSC_CTL_REG_DTF_MASK				0x00000003
+#define BSC_CTL_REG_SCL_SEL_MASK			0x00000030
+#define BSC_CTL_REG_SCL_SEL_SHIFT			4
+#define BSC_CTL_REG_INT_EN_MASK				0x00000040
+#define BSC_CTL_REG_INT_EN_SHIFT			6
+#define BSC_CTL_REG_DIV_CLK_MASK			0x00000080
+
+/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
+#define BSC_IIC_EN_RESTART_MASK				0x00000040
+#define BSC_IIC_EN_NOSTART_MASK				0x00000020
+#define BSC_IIC_EN_NOSTOP_MASK				0x00000010
+#define BSC_IIC_EN_NOACK_MASK				0x00000004
+#define BSC_IIC_EN_INTRP_MASK				0x00000002
+#define BSC_IIC_EN_ENABLE_MASK				0x00000001
+
+/* BSC_CTLHI control register field definitions */
+#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK	0x00000080
+#define BSC_CTLHI_REG_DATAREG_SIZE_MASK			0x00000040
+#define BSC_CTLHI_REG_IGNORE_ACK_MASK			0x00000002
+#define BSC_CTLHI_REG_WAIT_DIS_MASK			0x00000001
+
+#define I2C_TIMEOUT					100 /* msecs */
+
+/* Condition mask used for non combined transfer */
+#define COND_RESTART		BSC_IIC_EN_RESTART_MASK
+#define COND_NOSTART		BSC_IIC_EN_NOSTART_MASK
+#define COND_NOSTOP		BSC_IIC_EN_NOSTOP_MASK
+#define COND_START_STOP		(COND_RESTART | COND_NOSTART | COND_NOSTOP)
+
+/* BSC data transfer direction */
+#define DTF_WR_MASK		0x00000000
+#define DTF_RD_MASK		0x00000001
+/* BSC data transfer direction combined format */
+#define DTF_RD_WR_MASK		0x00000002
+#define DTF_WR_RD_MASK		0x00000003
+
+#define INT_ENABLE		true
+#define INT_DISABLE		false
+
+/* BSC block register map structure to cache fields to be written */
+struct bsc_regs {
+	u32	chip_address;           /* slave address */
+	u32	data_in[N_DATA_REGS];   /* tx data buffer*/
+	u32	cnt_reg;		/* rx/tx data length */
+	u32	ctl_reg;		/* control register */
+	u32	iic_enable;		/* xfer enable and status */
+	u32	data_out[N_DATA_REGS];  /* rx data buffer */
+	u32	ctlhi_reg;		/* more control fields */
+	u32	scl_param;		/* reserved */
+};
+
+struct bsc_clk_param {
+	u32 hz;
+	u32 scl_mask;
+	u32 div_mask;
+};
+
+enum bsc_xfer_cmd {
+	CMD_WR,
+	CMD_RD,
+	CMD_WR_NOACK,
+	CMD_RD_NOACK,
+};
+
+static char const *cmd_string[] = {
+	[CMD_WR] = "WR",
+	[CMD_RD] = "RD",
+	[CMD_WR_NOACK] = "WR NOACK",
+	[CMD_RD_NOACK] = "RD NOACK",
+};
+
+enum bus_speeds {
+	SPD_375K,
+	SPD_390K,
+	SPD_187K,
+	SPD_200K,
+	SPD_93K,
+	SPD_97K,
+	SPD_46K,
+	SPD_50K
+};
+
+static const struct bsc_clk_param bsc_clk[] = {
+	[SPD_375K] = {
+		.hz = 375000,
+		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_390K] = {
+		.hz = 390000,
+		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_187K] = {
+		.hz = 187500,
+		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_200K] = {
+		.hz = 200000,
+		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = 0
+	},
+	[SPD_93K]  = {
+		.hz = 93750,
+		.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_97K]  = {
+		.hz = 97500,
+		.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_46K]  = {
+		.hz = 46875,
+		.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	},
+	[SPD_50K]  = {
+		.hz = 50000,
+		.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
+		.div_mask = BSC_CTL_REG_DIV_CLK_MASK
+	}
+};
+
+struct brcmstb_i2c_dev {
+	struct device *device;
+	void __iomem *base;
+	void __iomem *irq_base;
+	int irq;
+	struct bsc_regs *bsc_regmap;
+	struct i2c_adapter adapter;
+	struct completion done;
+	bool is_suspended;
+	u32 clk_freq_hz;
+	int data_regsz;
+};
+
+/* register accessors for both be and le cpu arch */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __bsc_readl(_reg) ioread32be(_reg)
+#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
+#else
+#define __bsc_readl(_reg) ioread32(_reg)
+#define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
+#endif
+
+#define bsc_readl(_dev, _reg)						\
+	__bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
+
+#define bsc_writel(_dev, _val, _reg)					\
+	__bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
+
+static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
+{
+	return (N_DATA_REGS * dev->data_regsz);
+}
+
+static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
+{
+	return dev->data_regsz;
+}
+
+static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
+					   bool int_en)
+{
+
+	if (int_en)
+		/* Enable BSC  CTL interrupt line */
+		dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
+	else
+		/* Disable BSC CTL interrupt line */
+		dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
+
+	barrier();
+	bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
+}
+
+static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
+{
+	struct brcmstb_i2c_dev *dev = devid;
+	u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
+	u32 status_iic_intrp = bsc_readl(dev, iic_enable);
+
+	dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
+		status_bsc_ctl, status_iic_intrp);
+
+	if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
+		return IRQ_NONE;
+
+	brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
+	complete_all(&dev->done);
+
+	dev_dbg(dev->device, "isr handled");
+	return IRQ_HANDLED;
+}
+
+/* Wait for device to be ready */
+static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
+
+	while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
+		if (time_after(jiffies, timeout))
+			return -ETIMEDOUT;
+		cpu_relax();
+	}
+	return 0;
+}
+
+/* i2c xfer completion function, handles both irq and polling mode */
+static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
+{
+	int ret = 0;
+	unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
+
+	if (dev->irq >= 0) {
+		if (!wait_for_completion_timeout(&dev->done, timeout))
+			ret = -ETIMEDOUT;
+	} else {
+		/* we are in polling mode */
+		u32 bsc_intrp;
+		unsigned long time_left = jiffies + timeout;
+
+		do {
+			bsc_intrp = bsc_readl(dev, iic_enable) &
+				BSC_IIC_EN_INTRP_MASK;
+			if (time_after(jiffies, time_left)) {
+				ret = -ETIMEDOUT;
+				break;
+			}
+			cpu_relax();
+		} while (!bsc_intrp);
+	}
+
+	if (dev->irq < 0 || ret == -ETIMEDOUT)
+		brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
+
+	return ret;
+}
+
+/* Set xfer START/STOP conditions for subsequent transfer */
+static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
+				       u32 cond_flag)
+{
+	u32 regval = dev->bsc_regmap->iic_enable;
+
+	dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
+}
+
+/* Send I2C request check completion */
+static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
+				enum bsc_xfer_cmd cmd)
+{
+	int rc = 0;
+	struct bsc_regs *pi2creg = dev->bsc_regmap;
+
+	/* Make sure the hardware is ready */
+	rc = brcmstb_i2c_wait_if_busy(dev);
+	if (rc < 0)
+		return rc;
+
+	/* only if we are in interrupt mode */
+	if (dev->irq >= 0)
+		reinit_completion(&dev->done);
+
+	/* enable BSC CTL interrupt line */
+	brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
+
+	/* initiate transfer by setting iic_enable */
+	pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
+	bsc_writel(dev, pi2creg->iic_enable, iic_enable);
+
+	/* Wait for transaction to finish or timeout */
+	rc = brcmstb_i2c_wait_for_completion(dev);
+	if (rc) {
+		dev_dbg(dev->device, "intr timeout for cmd %s\n",
+			cmd_string[cmd]);
+		goto cmd_out;
+	}
+
+	if ((CMD_RD || CMD_WR) &&
+	    bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
+		rc = -EREMOTEIO;
+		dev_dbg(dev->device, "controller received NOACK intr for %s\n",
+			cmd_string[cmd]);
+	}
+
+cmd_out:
+	bsc_writel(dev, 0, cnt_reg);
+	bsc_writel(dev, 0, iic_enable);
+
+	return rc;
+}
+
+/* Actual data transfer through the BSC master */
+static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
+				     u8 *buf, unsigned int len,
+				     struct i2c_msg *pmsg)
+{
+	int cnt, byte, i, rc;
+	enum bsc_xfer_cmd cmd;
+	u32 ctl_reg;
+	struct bsc_regs *pi2creg = dev->bsc_regmap;
+	int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
+	int data_regsz = brcmstb_i2c_get_data_regsz(dev);
+	int xfersz = brcmstb_i2c_get_xfersz(dev);
+
+	/* see if the transaction needs to check NACK conditions */
+	if (no_ack || len <= xfersz) {
+		cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
+			: CMD_WR_NOACK;
+		pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
+	} else {
+		cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
+		pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
+	}
+	bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
+
+	/* set data transfer direction */
+	ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
+	if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
+		pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
+	else
+		pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
+
+	/* set the read/write length */
+	bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
+		   (len << BSC_CNT_REG1_SHIFT), cnt_reg);
+
+	/* Write data into data_in register */
+
+	if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
+		for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
+			u32 word = 0;
+
+			for (byte = 0; byte < data_regsz; byte++) {
+				word >>= BITS_PER_BYTE;
+				if ((cnt + byte) < len)
+					word |= buf[cnt + byte] <<
+					(BITS_PER_BYTE * (data_regsz - 1));
+			}
+			bsc_writel(dev, word, data_in[i]);
+		}
+	}
+
+	/* Initiate xfer, the function will return on completion */
+	rc = brcmstb_send_i2c_cmd(dev, cmd);
+
+	if (rc != 0) {
+		dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
+		return rc;
+	}
+
+	/* Read data from data_out register */
+	if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
+		for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
+			u32 data = bsc_readl(dev, data_out[i]);
+
+			for (byte = 0; byte < data_regsz &&
+				     (byte + cnt) < len; byte++) {
+				buf[cnt + byte] = data & 0xff;
+				data >>= BITS_PER_BYTE;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/* Write a single byte of data to the i2c bus */
+static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
+				       u8 *buf, unsigned int nak_expected)
+{
+	enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
+
+	bsc_writel(dev, 1, cnt_reg);
+	bsc_writel(dev, *buf, data_in);
+
+	return brcmstb_send_i2c_cmd(dev, cmd);
+}
+
+/* Send i2c address */
+static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
+			       struct i2c_msg *msg)
+{
+	unsigned char addr;
+
+	if (msg->flags & I2C_M_TEN) {
+		/* First byte is 11110XX0 where XX is upper 2 bits */
+		addr = 0xF0 | ((msg->addr & 0x300) >> 7);
+		bsc_writel(dev, addr, chip_address);
+
+		/* Second byte is the remaining 8 bits */
+		addr = msg->addr & 0xFF;
+		if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
+			return -EREMOTEIO;
+
+		if (msg->flags & I2C_M_RD) {
+			/* For read, send restart without stop condition */
+			brcmstb_set_i2c_start_stop(dev, COND_RESTART
+						   | COND_NOSTOP);
+			/* Then re-send the first byte with the read bit set */
+			addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
+			if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
+				return -EREMOTEIO;
+
+		}
+	} else {
+		addr = msg->addr << 1;
+		if (msg->flags & I2C_M_RD)
+			addr |= 1;
+
+		bsc_writel(dev, addr, chip_address);
+	}
+
+	return 0;
+}
+
+/* Master transfer function */
+static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
+			    struct i2c_msg msgs[], int num)
+{
+	struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
+	struct i2c_msg *pmsg;
+	int rc = 0;
+	int i;
+	int bytes_to_xfer;
+	u8 *tmp_buf;
+	int len = 0;
+	int xfersz = brcmstb_i2c_get_xfersz(dev);
+
+	if (dev->is_suspended)
+		return -EBUSY;
+
+	/* Loop through all messages */
+	for (i = 0; i < num; i++) {
+		pmsg = &msgs[i];
+		len = pmsg->len;
+		tmp_buf = pmsg->buf;
+
+		dev_dbg(dev->device,
+			"msg# %d/%d flg %x buf %x len %d\n", i,
+			num - 1, pmsg->flags,
+			pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
+
+		if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
+			brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP));
+		else
+			brcmstb_set_i2c_start_stop(dev,
+						   COND_RESTART | COND_NOSTOP);
+
+		/* Send slave address */
+		if (!(pmsg->flags & I2C_M_NOSTART)) {
+			rc = brcmstb_i2c_do_addr(dev, pmsg);
+			if (rc < 0) {
+				dev_dbg(dev->device,
+					"NACK for addr %2.2x msg#%d rc = %d\n",
+					pmsg->addr, i, rc);
+				goto out;
+			}
+		}
+
+		/* Perform data transfer */
+		while (len) {
+			bytes_to_xfer = min(len, xfersz);
+
+			if (len <= xfersz && i == (num - 1))
+				brcmstb_set_i2c_start_stop(dev,
+							   ~(COND_START_STOP));
+
+			rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
+						       bytes_to_xfer, pmsg);
+			if (rc < 0)
+				goto out;
+
+			len -=  bytes_to_xfer;
+			tmp_buf += bytes_to_xfer;
+		}
+	}
+
+	rc = num;
+out:
+	return rc;
+
+}
+
+static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
+		| I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+static const struct i2c_algorithm brcmstb_i2c_algo = {
+	.master_xfer = brcmstb_i2c_xfer,
+	.functionality = brcmstb_i2c_functionality,
+};
+
+static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
+{
+	int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
+	u32 clk_freq_hz = dev->clk_freq_hz;
+
+	for (i = 0; i < num_speeds; i++) {
+		if (bsc_clk[i].hz == clk_freq_hz) {
+			dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
+						| BSC_CTL_REG_DIV_CLK_MASK);
+			dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
+						     bsc_clk[i].div_mask);
+			bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
+			break;
+		}
+	}
+
+	/* in case we did not get find a valid speed */
+	if (i == num_speeds) {
+		i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
+			BSC_CTL_REG_SCL_SEL_SHIFT;
+		dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
+			bsc_clk[i].hz);
+	}
+}
+
+static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
+{
+	if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
+		/* set 4 byte data in/out xfers  */
+		dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
+	else
+		dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
+
+	bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
+	/* set bus speed */
+	brcmstb_i2c_set_bus_speed(dev);
+}
+
+static int brcmstb_i2c_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct brcmstb_i2c_dev *dev;
+	struct i2c_adapter *adap;
+	struct resource *iomem;
+	const char *int_name;
+
+	/* Allocate memory for private data structure */
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap),
+				       GFP_KERNEL);
+	if (!dev->bsc_regmap)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, dev);
+	dev->device = &pdev->dev;
+	init_completion(&dev->done);
+
+	/* Map hardware registers */
+	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->base = devm_ioremap_resource(dev->device, iomem);
+	if (IS_ERR(dev->base)) {
+		rc = -ENOMEM;
+		goto probe_errorout;
+	}
+
+	rc = of_property_read_string(dev->device->of_node, "interrupt-names",
+				     &int_name);
+	if (rc < 0)
+		int_name = NULL;
+
+	/* Get the interrupt number */
+	dev->irq = platform_get_irq(pdev, 0);
+
+	/* disable the bsc interrupt line */
+	brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
+
+	/* register the ISR handler */
+	rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
+			      IRQF_SHARED,
+			      int_name ? int_name : pdev->name,
+			      dev);
+
+	if (rc) {
+		dev_dbg(dev->device, "falling back to polling mode");
+		dev->irq = -1;
+	}
+
+	if (of_property_read_u32(dev->device->of_node,
+				 "clock-frequency", &dev->clk_freq_hz)) {
+		dev_warn(dev->device, "setting clock-frequency@%dHz\n",
+			 bsc_clk[0].hz);
+		dev->clk_freq_hz = bsc_clk[0].hz;
+	}
+
+	/* set the data in/out register size for compatible SoCs */
+	if (of_device_is_compatible(dev->device->of_node,
+				    "brcmstb,brcmper-i2c"))
+		dev->data_regsz = sizeof(u8);
+	else
+		dev->data_regsz = sizeof(u32);
+
+	brcmstb_i2c_set_bsc_reg_defaults(dev);
+
+	/* Add the i2c adapter */
+	adap = &dev->adapter;
+	i2c_set_adapdata(adap, dev);
+	adap->owner = THIS_MODULE;
+	strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
+	if (int_name)
+		strlcat(adap->name, int_name, sizeof(adap->name));
+	adap->algo = &brcmstb_i2c_algo;
+	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
+	rc = i2c_add_adapter(adap);
+	if (rc) {
+		dev_err(dev->device, "failed to add adapter\n");
+		goto probe_errorout;
+	}
+
+	dev_info(dev->device, "%s@%dhz registered in %s mode\n",
+		 int_name ? int_name : " ", dev->clk_freq_hz,
+		 (dev->irq >= 0) ? "interrupt" : "polling");
+
+	return 0;
+
+probe_errorout:
+	return rc;
+}
+
+static int brcmstb_i2c_remove(struct platform_device *pdev)
+{
+	struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&dev->adapter);
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_i2c_suspend(struct device *dev)
+{
+	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
+
+	i2c_lock_adapter(&i2c_dev->adapter);
+	i2c_dev->is_suspended = true;
+	i2c_unlock_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+
+static int brcmstb_i2c_resume(struct device *dev)
+{
+	struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
+
+	i2c_lock_adapter(&i2c_dev->adapter);
+	brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
+	i2c_dev->is_suspended = false;
+	i2c_unlock_adapter(&i2c_dev->adapter);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
+			 brcmstb_i2c_resume);
+
+static const struct of_device_id brcmstb_i2c_of_match[] = {
+	{.compatible = "brcm,brcmstb-i2c"},
+	{.compatible = "brcm,brcmper-i2c"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
+
+static struct platform_driver brcmstb_i2c_driver = {
+	.driver = {
+		   .name = "brcmstb-i2c",
+		   .of_match_table = brcmstb_i2c_of_match,
+		   .pm = &brcmstb_i2c_pm,
+		   },
+	.probe = brcmstb_i2c_probe,
+	.remove = brcmstb_i2c_remove,
+};
+module_platform_driver(brcmstb_i2c_driver);
+
+MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
+MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 29ca0bb4f561..9994a9408456 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -667,6 +667,7 @@ EXPORT_SYMBOL(input_close_device);
  */
 static void input_dev_release_keys(struct input_dev *dev)
 {
+	bool need_sync = false;
 	int code;
 
 	if (is_event_supported(EV_KEY, dev->evbit, EV_MAX)) {
@@ -674,9 +675,12 @@ static void input_dev_release_keys(struct input_dev *dev)
 			if (is_event_supported(code, dev->keybit, KEY_MAX) &&
 			    __test_and_clear_bit(code, dev->key)) {
 				input_pass_event(dev, EV_KEY, code, 0);
+				need_sync = true;
 			}
 		}
-		input_pass_event(dev, EV_SYN, SYN_REPORT, 1);
+
+		if (need_sync)
+			input_pass_event(dev, EV_SYN, SYN_REPORT, 1);
 	}
 }
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 61ffdca96e25..e8e33b7179ce 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,9 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config BCM7120_L2_IRQ
+	bool
+
 config DW_APB_ICTL
 	bool
 	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5194afb39e78..7313fa9a7471 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,6 +1,8 @@
 obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
+obj-$(CONFIG_BRCMSTB)			+= irq-brcmstb-l2.o
+obj-$(CONFIG_BCM7120_L2_IRQ)		+= irq-bcm7120-l2.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)		+= irq-armada-370-xp.o
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
new file mode 100644
index 000000000000..435006db9329
--- /dev/null
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -0,0 +1,237 @@
+/*
+ * Broadcom BCM7120 style Level 2 interrupt controller driver
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/reboot.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include "irqchip.h"
+
+/* Register offset in the L2 interrupt controller */
+#define IRQEN		0x00
+#define IRQSTAT		0x04
+
+struct bcm7120_l2_intc_data {
+	void __iomem *base;
+	struct irq_domain *domain;
+	bool can_wake;
+	unsigned int num_parents;
+	struct bcm7120_l1_intc_data *l1_data;
+	u32 irq_fwd_mask;
+	u32 saved_mask;
+};
+
+struct bcm7120_l1_intc_data {
+	struct bcm7120_l2_intc_data *b;
+	u32 irq_map_mask;
+};
+
+static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
+{
+	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
+	struct bcm7120_l2_intc_data *b = data->b;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	u32 status;
+
+	chained_irq_enter(chip, desc);
+
+	/* Mask status with only the per-L1 interrupt map_mask */
+	status = __raw_readl(b->base + IRQSTAT) & data->irq_map_mask;
+	while (status) {
+		irq = ffs(status) - 1;
+		status &= ~(1 << irq);
+		generic_handle_irq(irq_find_mapping(b->domain, irq));
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static void bcm7120_l2_intc_suspend(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct bcm7120_l2_intc_data *b = gc->private;
+	u32 reg;
+
+	irq_gc_lock(gc);
+	/* Save the current mask and the interrupt forward mask */
+	b->saved_mask = __raw_readl(b->base) | b->irq_fwd_mask;
+	if (b->can_wake) {
+		reg = b->saved_mask | gc->wake_active;
+		__raw_writel(reg, b->base);
+	}
+	irq_gc_unlock(gc);
+}
+
+static void bcm7120_l2_intc_resume(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct bcm7120_l2_intc_data *b = gc->private;
+
+	/* Restore the saved mask */
+	irq_gc_lock(gc);
+	__raw_writel(b->saved_mask, b->base);
+	irq_gc_unlock(gc);
+}
+
+static int bcm7120_l2_intc_init_one(struct device_node *dn,
+					struct bcm7120_l2_intc_data *data,
+					int irq, const __be32 *map_mask,
+					u32 *valid_mask)
+{
+	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
+	int parent_irq;
+
+	parent_irq = irq_of_parse_and_map(dn, irq);
+	if (parent_irq < 0) {
+		pr_err("failed to map interrupt %d\n", irq);
+		return parent_irq;
+	}
+
+	/* We need to bind a given L1 interrupt with its map_mask to
+	 * properly mask the status register since we utilize the same
+	 * handler function with different parent interrupts
+	 */
+	l1_data->irq_map_mask = be32_to_cpup(map_mask + irq);
+	l1_data->b = data;
+	*valid_mask |= l1_data->irq_map_mask;
+
+	irq_set_handler_data(parent_irq, l1_data);
+	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
+
+	return 0;
+}
+
+int __init bcm7120_l2_intc_of_init(struct device_node *dn,
+					struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct bcm7120_l2_intc_data *data;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	const __be32 *map_mask;
+	int num_parent_irqs;
+	int ret = 0, len, irq;
+	u32 valid_mask = 0;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->base = of_iomap(dn, 0);
+	if (!data->base) {
+		pr_err("failed to remap intc L2 registers\n");
+		ret = -ENOMEM;
+		goto out_free;
+	}
+
+	if (of_property_read_u32(dn, "brcm,int-fwd-mask", &data->irq_fwd_mask))
+		data->irq_fwd_mask = 0;
+
+	/* Enable all interrupt specified in the interrupt forward mask and have
+	 * the other disabled
+	 */
+	__raw_writel(data->irq_fwd_mask, data->base + IRQEN);
+
+	num_parent_irqs = of_irq_count(dn);
+	if (num_parent_irqs <= 0) {
+		pr_err("invalid number of parent interrupts\n");
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	data->l1_data = kcalloc(num_parent_irqs, sizeof(*data->l1_data),
+				  GFP_KERNEL);
+	if (!data->l1_data) {
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
+	if (!map_mask || (len != (sizeof(*map_mask) * num_parent_irqs))) {
+		pr_err("invalid brcm,int-map-mask property\n");
+		ret = -EINVAL;
+		goto out_free_l1_data;
+	}
+
+	for (irq = 0; irq < num_parent_irqs; irq++) {
+		ret = bcm7120_l2_intc_init_one(dn, data, irq, map_mask,
+					       &valid_mask);
+		if (ret)
+			goto out_free_l1_data;
+	}
+
+	data->domain = irq_domain_add_linear(dn, 32,
+					&irq_generic_chip_ops, NULL);
+	if (!data->domain) {
+		ret = -ENOMEM;
+		goto out_free_l1_data;
+	}
+
+	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
+				dn->full_name, handle_level_irq, clr, 0,
+				IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		pr_err("failed to allocate generic irq chip\n");
+		goto out_free_domain;
+	}
+
+	gc = irq_get_domain_generic_chip(data->domain, 0);
+	gc->unused = 0xffffffff & ~valid_mask;
+	gc->reg_base = data->base;
+	gc->private = data;
+	ct = gc->chip_types;
+
+	ct->regs.mask = IRQEN;
+	ct->chip.irq_mask = irq_gc_mask_clr_bit;
+	ct->chip.irq_unmask = irq_gc_mask_set_bit;
+	ct->chip.irq_ack = irq_gc_noop;
+	ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
+	ct->chip.irq_resume = bcm7120_l2_intc_resume;
+
+	if (of_property_read_bool(dn, "brcm,irq-can-wake")) {
+		data->can_wake = true;
+		/* This IRQ chip can wake the system, set all relevant child
+		 * interupts in wake_enabled mask
+		 */
+		gc->wake_enabled = 0xffffffff;
+		gc->wake_enabled &= ~gc->unused;
+		ct->chip.irq_set_wake = irq_gc_set_wake;
+	}
+
+	pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
+			data->base, num_parent_irqs);
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(data->domain);
+out_free_l1_data:
+	kfree(data->l1_data);
+out_unmap:
+	iounmap(data->base);
+out_free:
+	kfree(data);
+	return ret;
+}
+IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc",
+		bcm7120_l2_intc_of_init);
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
new file mode 100644
index 000000000000..63bf8fc98c5c
--- /dev/null
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -0,0 +1,241 @@
+/*
+ * Generic Broadcom STB Level 2 Interrupt controller driver
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/reboot.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+
+#include "irqchip.h"
+
+/* Register offsets in the L2 interrupt controller */
+#define CPU_STATUS	0x00
+#define CPU_SET		0x04
+#define CPU_CLEAR	0x08
+#define CPU_MASK_STATUS	0x0c
+#define CPU_MASK_SET	0x10
+#define CPU_MASK_CLEAR	0x14
+
+/* L2 intc private data structure */
+struct brcmstb_l2_intc_data {
+	int parent_irq;
+	void __iomem *base;
+	struct irq_domain *domain;
+	bool can_wake;
+	u32 saved_mask; /* for suspend/resume */
+	struct notifier_block reboot_notifier;
+};
+
+static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
+{
+	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_get_chip(irq);
+	u32 status;
+
+	chained_irq_enter(chip, desc);
+
+	status = __raw_readl(b->base + CPU_STATUS) &
+		~(__raw_readl(b->base + CPU_MASK_STATUS));
+
+	if (status == 0) {
+		raw_spin_lock(&desc->lock);
+		handle_bad_irq(irq, desc);
+		raw_spin_unlock(&desc->lock);
+		goto out;
+	}
+
+	do {
+		irq = ffs(status) - 1;
+		/* ack at our level */
+		__raw_writel(1 << irq, b->base + CPU_CLEAR);
+		status &= ~(1 << irq);
+		generic_handle_irq(irq_find_mapping(b->domain, irq));
+	} while (status);
+out:
+	chained_irq_exit(chip, desc);
+}
+
+static void brcmstb_l2_intc_suspend(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_l2_intc_data *b = gc->private;
+
+	irq_gc_lock(gc);
+	/* Save the current mask */
+	b->saved_mask = __raw_readl(b->base + CPU_MASK_STATUS);
+
+	if (b->can_wake) {
+		/* Program the wakeup mask */
+		__raw_writel(~gc->wake_active, b->base + CPU_MASK_SET);
+		__raw_writel(gc->wake_active, b->base + CPU_MASK_CLEAR);
+	}
+	irq_gc_unlock(gc);
+}
+
+static void brcmstb_l2_intc_resume(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct brcmstb_l2_intc_data *b = gc->private;
+
+	irq_gc_lock(gc);
+	/* Clear unmasked non-wakeup interrupts */
+	__raw_writel(~b->saved_mask & ~gc->wake_active, b->base + CPU_CLEAR);
+
+	/* Restore the saved mask */
+	__raw_writel(b->saved_mask, b->base + CPU_MASK_SET);
+	__raw_writel(~b->saved_mask, b->base + CPU_MASK_CLEAR);
+	irq_gc_unlock(gc);
+}
+
+static int brcmstb_l2_intc_reboot(struct notifier_block *nb,
+		unsigned long action, void *data)
+{
+	struct brcmstb_l2_intc_data *b;
+	struct irq_chip_generic *gc;
+
+	b = container_of(nb, struct brcmstb_l2_intc_data, reboot_notifier);
+	gc = irq_get_domain_generic_chip(b->domain, 0);
+
+	irq_gc_lock(gc);
+
+	if (action == SYS_POWER_OFF) {
+		if (!gc->wake_active)
+			pr_err("WARNING: NO WAKEUP SOURCE CONFIGURED\n");
+		/* Program the wakeup mask */
+		__raw_writel(~gc->wake_active, b->base + CPU_MASK_SET);
+		__raw_writel(gc->wake_active, b->base + CPU_MASK_CLEAR);
+	}
+
+	irq_gc_unlock(gc);
+
+	return NOTIFY_DONE;
+}
+
+int __init brcmstb_l2_intc_of_init(struct device_node *np,
+					struct device_node *parent)
+{
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	struct brcmstb_l2_intc_data *data;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	int ret;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->base = of_iomap(np, 0);
+	if (!data->base) {
+		pr_err("failed to remap intc L2 registers\n");
+		return -ENOMEM;
+	}
+
+	if (of_property_read_bool(np, "brcm,irq-can-wake"))
+		data->can_wake = true;
+
+	/* Disable all interrupts by default */
+	__raw_writel(0xffffffff, data->base + CPU_MASK_SET);
+
+	/* Wakeup interrupts may be retained from S5 (cold boot) */
+	if (!data->can_wake)
+		__raw_writel(0xffffffff, data->base + CPU_CLEAR);
+
+	data->parent_irq = irq_of_parse_and_map(np, 0);
+	if (data->parent_irq < 0) {
+		pr_err("failed to find parent interrupt\n");
+		ret = data->parent_irq;
+		goto out_unmap;
+	}
+
+	data->domain = irq_domain_add_linear(np, 32,
+				&irq_generic_chip_ops, NULL);
+	if (!data->domain) {
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	/* Allocate a single Generic IRQ chip for this node */
+	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
+				np->full_name, handle_edge_irq, clr, 0, 0);
+	if (ret) {
+		pr_err("failed to allocate generic irq chip\n");
+		goto out_free_domain;
+	}
+
+	/* Set the IRQ chaining logic */
+	irq_set_handler_data(data->parent_irq, data);
+	irq_set_chained_handler(data->parent_irq, brcmstb_l2_intc_irq_handle);
+
+	gc = irq_get_domain_generic_chip(data->domain, 0);
+	gc->reg_base = data->base;
+	gc->private = data;
+	ct = gc->chip_types;
+
+	ct->chip.irq_ack = irq_gc_ack_set_bit;
+	ct->regs.ack = CPU_CLEAR;
+
+	ct->chip.irq_mask = irq_gc_mask_disable_reg;
+	ct->regs.disable = CPU_MASK_SET;
+
+	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+	ct->regs.enable = CPU_MASK_CLEAR;
+
+	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
+	ct->chip.irq_resume = brcmstb_l2_intc_resume;
+
+	if (data->can_wake) {
+		/* This IRQ chip can wake the system, set all child interrupts
+		 * in wake_enabled mask
+		 */
+		gc->wake_enabled = 0xffffffff;
+		ct->chip.irq_set_wake = irq_gc_set_wake;
+
+		/* Run reboot notifier last */
+		data->reboot_notifier.priority = -1;
+		data->reboot_notifier.notifier_call = brcmstb_l2_intc_reboot;
+		register_reboot_notifier(&data->reboot_notifier);
+	}
+
+	pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n",
+			data->base, data->parent_irq);
+
+	return 0;
+
+out_free_domain:
+	irq_domain_remove(data->domain);
+out_unmap:
+	iounmap(data->base);
+	kfree(data);
+	return ret;
+}
+IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init);
diff --git a/drivers/media/dvb-core/dmxdev.c b/drivers/media/dvb-core/dmxdev.c
index c0363f1b6c90..289a14aa7465 100644
--- a/drivers/media/dvb-core/dmxdev.c
+++ b/drivers/media/dvb-core/dmxdev.c
@@ -82,7 +82,11 @@ static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src,
 
 		ret = wait_event_interruptible(src->queue,
 					       !dvb_ringbuffer_empty(src) ||
-					       (src->error != 0));
+					       (src->error != 0) ||
+					       (src->do_wait != 1));
+		if (src->do_wait != 1)
+			ret = -EINTR;
+
 		if (ret < 0)
 			break;
 
@@ -103,6 +107,7 @@ static ssize_t dvb_dmxdev_buffer_read(struct dvb_ringbuffer *src,
 		buf += ret;
 	}
 
+
 	return (count - todo) ? (count - todo) : ret;
 }
 
@@ -955,6 +960,22 @@ dvb_demux_read(struct file *file, char __user *buf, size_t count,
 	return ret;
 }
 
+static int dvb_demux_lock_filter(struct dmxdev_filter *dmxdevfilter)
+{
+	int ret;
+
+	dmxdevfilter->buffer.do_wait = 0;
+
+	if (waitqueue_active(&dmxdevfilter->buffer.queue))
+		wake_up(&dmxdevfilter->buffer.queue);
+
+	ret = mutex_lock_interruptible(&dmxdevfilter->mutex);
+
+	dmxdevfilter->buffer.do_wait = 1;
+
+	return ret;
+}
+
 static int dvb_demux_do_ioctl(struct file *file,
 			      unsigned int cmd, void *parg)
 {
@@ -968,7 +989,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 
 	switch (cmd) {
 	case DMX_START:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -980,7 +1001,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_STOP:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -989,7 +1010,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_FILTER:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -998,7 +1019,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_PES_FILTER:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -1007,7 +1028,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_SET_BUFFER_SIZE:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			mutex_unlock(&dmxdev->mutex);
 			return -ERESTARTSYS;
 		}
@@ -1051,7 +1072,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_ADD_PID:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			ret = -ERESTARTSYS;
 			break;
 		}
@@ -1060,7 +1081,7 @@ static int dvb_demux_do_ioctl(struct file *file,
 		break;
 
 	case DMX_REMOVE_PID:
-		if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
+		if (dvb_demux_lock_filter(dmxdevfilter)) {
 			ret = -ERESTARTSYS;
 			break;
 		}
diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c
index 46a984291b7d..3eff67e52c6f 100644
--- a/drivers/media/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb-core/dvb_frontend.c
@@ -34,7 +34,6 @@
 #include <linux/wait.h>
 #include <linux/slab.h>
 #include <linux/poll.h>
-#include <linux/semaphore.h>
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/freezer.h>
@@ -108,7 +107,7 @@ struct dvb_frontend_private {
 	struct dvb_device *dvbdev;
 	struct dvb_frontend_parameters parameters_out;
 	struct dvb_fe_events events;
-	struct semaphore sem;
+	struct mutex lock;
 	struct list_head list_head;
 	wait_queue_head_t wait_queue;
 	struct task_struct *thread;
@@ -248,12 +247,12 @@ static int dvb_frontend_get_event(struct dvb_frontend *fe,
 		if (flags & O_NONBLOCK)
 			return -EWOULDBLOCK;
 
-		up(&fepriv->sem);
+		mutex_unlock(&fepriv->lock);
 
 		ret = wait_event_interruptible (events->wait_queue,
 						events->eventw != events->eventr);
 
-		if (down_interruptible (&fepriv->sem))
+		if (mutex_lock_interruptible(&fepriv->lock))
 			return -ERESTARTSYS;
 
 		if (ret < 0)
@@ -603,23 +602,12 @@ static int dvb_frontend_thread(void *data)
 	enum dvbfe_algo algo;
 
 	bool re_tune = false;
-	bool semheld = false;
+	bool lockheld = false;
 
 	dev_dbg(fe->dvb->device, "%s:\n", __func__);
 
-	fepriv->check_wrapped = 0;
-	fepriv->quality = 0;
-	fepriv->delay = 3*HZ;
-	fepriv->status = 0;
-	fepriv->wakeup = 0;
-	fepriv->reinitialise = 0;
-
-	dvb_frontend_init(fe);
-
 	set_freezable();
 	while (1) {
-		up(&fepriv->sem);	    /* is locked when we enter the thread... */
-restart:
 		wait_event_interruptible_timeout(fepriv->wait_queue,
 			dvb_frontend_should_wakeup(fe) || kthread_should_stop()
 				|| freezing(current),
@@ -627,16 +615,16 @@ restart:
 
 		if (kthread_should_stop() || dvb_frontend_is_exiting(fe)) {
 			/* got signal or quitting */
-			if (!down_interruptible(&fepriv->sem))
-				semheld = true;
+			if (!mutex_lock_interruptible(&fepriv->lock))
+				lockheld = true;
 			fepriv->exit = DVB_FE_NORMAL_EXIT;
 			break;
 		}
 
 		if (try_to_freeze())
-			goto restart;
+			continue;
 
-		if (down_interruptible(&fepriv->sem))
+		if (mutex_lock_interruptible(&fepriv->lock))
 			break;
 
 		if (fepriv->reinitialise) {
@@ -721,6 +709,8 @@ restart:
 		} else {
 			dvb_frontend_swzigzag(fe);
 		}
+
+		mutex_unlock(&fepriv->lock);
 	}
 
 	if (dvb_powerdown_on_sleep) {
@@ -744,8 +734,8 @@ restart:
 		fepriv->exit = DVB_FE_NO_EXIT;
 	mb();
 
-	if (semheld)
-		up(&fepriv->sem);
+	if (lockheld)
+		mutex_unlock(&fepriv->lock);
 	dvb_frontend_wakeup(fe);
 	return 0;
 }
@@ -764,7 +754,7 @@ static void dvb_frontend_stop(struct dvb_frontend *fe)
 
 	kthread_stop(fepriv->thread);
 
-	sema_init(&fepriv->sem, 1);
+	mutex_init(&fepriv->lock);
 	fepriv->state = FESTATE_IDLE;
 
 	/* paranoia check in case a signal arrived */
@@ -834,12 +824,22 @@ static int dvb_frontend_start(struct dvb_frontend *fe)
 
 	if (signal_pending(current))
 		return -EINTR;
-	if (down_interruptible (&fepriv->sem))
+	if (mutex_lock_interruptible(&fepriv->lock))
 		return -EINTR;
 
 	fepriv->state = FESTATE_IDLE;
 	fepriv->exit = DVB_FE_NO_EXIT;
 	fepriv->thread = NULL;
+
+	fepriv->check_wrapped = 0;
+	fepriv->quality = 0;
+	fepriv->delay = 3*HZ;
+	fepriv->status = 0;
+	fepriv->wakeup = 0;
+	fepriv->reinitialise = 0;
+
+	dvb_frontend_init(fe);
+
 	mb();
 
 	fe_thread = kthread_run(dvb_frontend_thread, fe,
@@ -849,11 +849,13 @@ static int dvb_frontend_start(struct dvb_frontend *fe)
 		dev_warn(fe->dvb->device,
 				"dvb_frontend_start: failed to start kthread (%d)\n",
 				ret);
-		up(&fepriv->sem);
-		return ret;
+	} else {
+		fepriv->thread = fe_thread;
+		ret = 0;
 	}
-	fepriv->thread = fe_thread;
-	return 0;
+
+	mutex_unlock(&fepriv->lock);
+	return ret;
 }
 
 static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe,
@@ -1239,11 +1241,9 @@ static int dtv_property_legacy_params_sync(struct dvb_frontend *fe,
 /**
  * dtv_get_frontend - calls a callback for retrieving DTV parameters
  * @fe:		struct dvb_frontend pointer
- * @c:		struct dtv_frontend_properties pointer (DVBv5 cache)
  * @p_out	struct dvb_frontend_parameters pointer (DVBv3 FE struct)
  *
  * This routine calls either the DVBv3 or DVBv5 get_frontend call.
- * If c is not null, it will update the DVBv5 cache struct pointed by it.
  * If p_out is not null, it will update the DVBv3 params pointed by it.
  */
 static int dtv_get_frontend(struct dvb_frontend *fe,
@@ -1255,11 +1255,11 @@ static int dtv_get_frontend(struct dvb_frontend *fe,
 		r = fe->ops.get_frontend(fe);
 		if (unlikely(r < 0))
 			return r;
-		if (p_out)
-			dtv_property_legacy_params_sync(fe, p_out);
-		return 0;
 	}
 
+	if (p_out)
+		dtv_property_legacy_params_sync(fe, p_out);
+
 	/* As everything is in cache, get_frontend fops are always supported */
 	return 0;
 }
@@ -1901,18 +1901,18 @@ static int dvb_frontend_ioctl(struct file *file,
 	int err = -EOPNOTSUPP;
 
 	dev_dbg(fe->dvb->device, "%s: (%d)\n", __func__, _IOC_NR(cmd));
-	if (down_interruptible(&fepriv->sem))
+	if (mutex_lock_interruptible(&fepriv->lock))
 		return -ERESTARTSYS;
 
 	if (fepriv->exit != DVB_FE_NO_EXIT) {
-		up(&fepriv->sem);
+		mutex_unlock(&fepriv->lock);
 		return -ENODEV;
 	}
 
 	if ((file->f_flags & O_ACCMODE) == O_RDONLY &&
 	    (_IOC_DIR(cmd) != _IOC_READ || cmd == FE_GET_EVENT ||
 	     cmd == FE_DISEQC_RECV_SLAVE_REPLY)) {
-		up(&fepriv->sem);
+		mutex_unlock(&fepriv->lock);
 		return -EPERM;
 	}
 
@@ -1923,7 +1923,7 @@ static int dvb_frontend_ioctl(struct file *file,
 		err = dvb_frontend_ioctl_legacy(file, cmd, parg);
 	}
 
-	up(&fepriv->sem);
+	mutex_unlock(&fepriv->lock);
 	return err;
 }
 
@@ -2607,7 +2607,7 @@ int dvb_register_frontend(struct dvb_adapter* dvb,
 	}
 	fepriv = fe->frontend_priv;
 
-	sema_init(&fepriv->sem, 1);
+	mutex_init(&fepriv->lock);
 	init_waitqueue_head (&fepriv->wait_queue);
 	init_waitqueue_head (&fepriv->events.wait_queue);
 	mutex_init(&fepriv->events.mtx);
diff --git a/drivers/media/dvb-core/dvb_ringbuffer.c b/drivers/media/dvb-core/dvb_ringbuffer.c
index a5712cd7c65f..6b96c836551b 100644
--- a/drivers/media/dvb-core/dvb_ringbuffer.c
+++ b/drivers/media/dvb-core/dvb_ringbuffer.c
@@ -45,6 +45,7 @@ void dvb_ringbuffer_init(struct dvb_ringbuffer *rbuf, void *data, size_t len)
 	rbuf->data=data;
 	rbuf->size=len;
 	rbuf->error=0;
+	rbuf->do_wait=1;
 
 	init_waitqueue_head(&rbuf->queue);
 
@@ -149,19 +150,23 @@ void dvb_ringbuffer_read(struct dvb_ringbuffer *rbuf, u8 *buf, size_t len)
 
 ssize_t dvb_ringbuffer_write(struct dvb_ringbuffer *rbuf, const u8 *buf, size_t len)
 {
+	ssize_t pwrite = rbuf->pwrite;
 	size_t todo = len;
 	size_t split;
 
-	split = (rbuf->pwrite + len > rbuf->size) ? rbuf->size - rbuf->pwrite : 0;
+	split = (pwrite + len > rbuf->size) ? rbuf->size - pwrite : 0;
 
 	if (split > 0) {
-		memcpy(rbuf->data+rbuf->pwrite, buf, split);
+		memcpy(rbuf->data+pwrite, buf, split);
 		buf += split;
 		todo -= split;
-		rbuf->pwrite = 0;
+		pwrite = 0;
 	}
-	memcpy(rbuf->data+rbuf->pwrite, buf, todo);
-	rbuf->pwrite = (rbuf->pwrite + todo) % rbuf->size;
+	memcpy(rbuf->data+pwrite, buf, todo);
+
+	smp_wmb();
+
+	rbuf->pwrite = (pwrite + todo) % rbuf->size;
 
 	return len;
 }
diff --git a/drivers/media/dvb-core/dvb_ringbuffer.h b/drivers/media/dvb-core/dvb_ringbuffer.h
index 41f04dae69b6..25a853b51b94 100644
--- a/drivers/media/dvb-core/dvb_ringbuffer.h
+++ b/drivers/media/dvb-core/dvb_ringbuffer.h
@@ -38,6 +38,7 @@ struct dvb_ringbuffer {
 	int               error;
 
 	wait_queue_head_t queue;
+	int               do_wait;
 	spinlock_t        lock;
 };
 
diff --git a/drivers/media/dvb-core/dvbdev.c b/drivers/media/dvb-core/dvbdev.c
index 983db75de350..a1fe736bddf6 100644
--- a/drivers/media/dvb-core/dvbdev.c
+++ b/drivers/media/dvb-core/dvbdev.c
@@ -298,7 +298,7 @@ static int dvbdev_check_free_adapter_num(int num)
 
 static int dvbdev_get_free_adapter_num (void)
 {
-	int num = 0;
+	int num = 1;
 
 	while (num < DVB_MAX_ADAPTERS) {
 		if (dvbdev_check_free_adapter_num(num))
diff --git a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c
index 8a054d66e708..7f7eacee84fd 100644
--- a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c
+++ b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c
@@ -21,10 +21,10 @@
 
 #include "dvb_usb_common.h"
 
-int dvb_usbv2_disable_rc_polling;
+int dvb_usbv2_disable_rc_polling=1;
 module_param_named(disable_rc_polling, dvb_usbv2_disable_rc_polling, int, 0644);
 MODULE_PARM_DESC(disable_rc_polling,
-		"disable remote control polling (default: 0)");
+		"disable remote control polling (default: 1)");
 static int dvb_usb_force_pid_filter_usage;
 module_param_named(force_pid_filter_usage, dvb_usb_force_pid_filter_usage,
 		int, 0444);
diff --git a/drivers/media/usb/dvb-usb/dvb-usb-init.c b/drivers/media/usb/dvb-usb/dvb-usb-init.c
index 1adf325012f7..6283131ba78d 100644
--- a/drivers/media/usb/dvb-usb/dvb-usb-init.c
+++ b/drivers/media/usb/dvb-usb/dvb-usb-init.c
@@ -18,9 +18,9 @@ int dvb_usb_debug;
 module_param_named(debug, dvb_usb_debug, int, 0644);
 MODULE_PARM_DESC(debug, "set debugging level (1=info,xfer=2,pll=4,ts=8,err=16,rc=32,fw=64,mem=128,uxfer=256  (or-able))." DVB_USB_DEBUG_STATUS);
 
-int dvb_usb_disable_rc_polling;
+int dvb_usb_disable_rc_polling=1;
 module_param_named(disable_rc_polling, dvb_usb_disable_rc_polling, int, 0644);
-MODULE_PARM_DESC(disable_rc_polling, "disable remote control polling (default: 0).");
+MODULE_PARM_DESC(disable_rc_polling, "disable remote control polling (default: 1).");
 
 static int dvb_usb_force_pid_filter_usage;
 module_param_named(force_pid_filter_usage, dvb_usb_force_pid_filter_usage, int, 0444);
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 2cc6082d0060..dc5dd2126660 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -2056,7 +2056,11 @@ static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card,
 	 * index anymore so we keep track of a name index.
 	 */
 	if (!subname) {
-		md->name_idx = find_first_zero_bit(name_use, max_devices);
+		md->name_idx = card->host->index;
+#if defined(CONFIG_ARCH_BRCMSTB)
+		if (md->name_idx < 2)
+			md->name_idx ^= 1;
+#endif
 		__set_bit(md->name_idx, name_use);
 	} else
 		md->name_idx = ((struct mmc_blk_data *)
@@ -2381,6 +2385,13 @@ static const struct mmc_fixup blk_fixups[] =
 	MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
 		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
 
+	/*
+	 * Some Micron eMMC devices will not go into boot mode on
+	 * CMD0 arg: 0XF0F0F0F0 after going into SLEEP state.
+	 * This will hang a reboot.
+	 */
+	MMC_FIXUP(CID_NAME_ANY, 0xfe, 0x014e, add_quirk_mmc,
+		  MMC_QUIRK_BROKEN_SLEEP),
 	END_FIXUP
 };
 
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 1bbe372a9e04..54b6ae126d0c 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2584,12 +2584,8 @@ EXPORT_SYMBOL(mmc_power_restore_host);
  */
 int mmc_flush_cache(struct mmc_card *card)
 {
-	struct mmc_host *host = card->host;
 	int err = 0;
 
-	if (!(host->caps2 & MMC_CAP2_CACHE_CTRL))
-		return err;
-
 	if (mmc_card_mmc(card) &&
 			(card->ext_csd.cache_size > 0) &&
 			(card->ext_csd.cache_ctrl & 1)) {
@@ -2616,8 +2612,7 @@ int mmc_cache_ctrl(struct mmc_host *host, u8 enable)
 	unsigned int timeout;
 	int err = 0;
 
-	if (!(host->caps2 & MMC_CAP2_CACHE_CTRL) ||
-			mmc_card_is_removable(host))
+	if (mmc_card_is_removable(host))
 		return err;
 
 	if (card && mmc_card_mmc(card) &&
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 49bc403e31f0..81e59fd386b7 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -429,6 +429,8 @@ int mmc_of_parse(struct mmc_host *host)
 		host->pm_caps |= MMC_PM_KEEP_POWER;
 	if (of_find_property(np, "enable-sdio-wakeup", &len))
 		host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
+	if (of_find_property(np, "mmc-hs200-1_8v", &len))
+		host->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
 
 	return 0;
 
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 229407229ecd..0844b6bb5968 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -296,13 +296,12 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd)
 		}
 	}
 
+	/*
+	 * The EXT_CSD format is meant to be forward compatible. As long
+	 * as CSD_STRUCTURE does not change, all values for EXT_CSD_REV
+	 * are authorized, see JEDEC JESD84-B50 section B.8.
+	 */
 	card->ext_csd.rev = ext_csd[EXT_CSD_REV];
-	if (card->ext_csd.rev > 7) {
-		pr_err("%s: unrecognised EXT_CSD revision %d\n",
-			mmc_hostname(card->host), card->ext_csd.rev);
-		err = -EINVAL;
-		goto out;
-	}
 
 	card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0];
 	card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1];
@@ -1294,8 +1293,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	 * If cache size is higher than 0, this indicates
 	 * the existence of cache and it can be turned on.
 	 */
-	if ((host->caps2 & MMC_CAP2_CACHE_CTRL) &&
-			card->ext_csd.cache_size > 0) {
+	if (card->ext_csd.cache_size > 0) {
 		err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 				EXT_CSD_CACHE_CTRL, 1,
 				card->ext_csd.generic_cmd6_time);
@@ -1356,7 +1354,8 @@ err:
 
 static int mmc_can_sleep(struct mmc_card *card)
 {
-	return (card && card->ext_csd.rev >= 3);
+	return card && card->ext_csd.rev >= 3 &&
+		((card->quirks & MMC_QUIRK_BROKEN_SLEEP) == 0);
 }
 
 static int mmc_sleep(struct mmc_host *host)
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 692fdb177294..4a410a1bfaa2 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -389,18 +389,9 @@ static int sd_select_driver_type(struct mmc_card *card, u8 *status)
 {
 	int host_drv_type = SD_DRIVER_TYPE_B;
 	int card_drv_type = SD_DRIVER_TYPE_B;
-	int drive_strength;
+	int drive_strength, drv_type;
 	int err;
 
-	/*
-	 * If the host doesn't support any of the Driver Types A,C or D,
-	 * or there is no board specific handler then default Driver
-	 * Type B is used.
-	 */
-	if (!(card->host->caps & (MMC_CAP_DRIVER_TYPE_A | MMC_CAP_DRIVER_TYPE_C
-	    | MMC_CAP_DRIVER_TYPE_D)))
-		return 0;
-
 	if (!card->host->ops->select_drive_strength)
 		return 0;
 
@@ -429,22 +420,24 @@ static int sd_select_driver_type(struct mmc_card *card, u8 *status)
 	 * return what is possible given the options
 	 */
 	mmc_host_clk_hold(card->host);
-	drive_strength = card->host->ops->select_drive_strength(
+	drive_strength = card->host->ops->select_drive_strength(card,
 		card->sw_caps.uhs_max_dtr,
-		host_drv_type, card_drv_type);
+		host_drv_type, card_drv_type, &drv_type);
 	mmc_host_clk_release(card->host);
 
-	err = mmc_sd_switch(card, 1, 2, drive_strength, status);
-	if (err)
-		return err;
-
-	if ((status[15] & 0xF) != drive_strength) {
-		pr_warning("%s: Problem setting drive strength!\n",
-			mmc_hostname(card->host));
-		return 0;
+	if (drive_strength) {
+		err = mmc_sd_switch(card, 1, 2, drive_strength, status);
+		if (err)
+			return err;
+		if ((status[15] & 0xF) != drive_strength) {
+			pr_warn("%s: Problem setting drive strength!\n",
+				mmc_hostname(card->host));
+			return 0;
+		}
 	}
 
-	mmc_set_driver_type(card->host, drive_strength);
+	if (drv_type)
+		mmc_set_driver_type(card->host, drv_type);
 
 	return 0;
 }
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index ae360b3b4fda..b6bd83943456 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -401,21 +401,10 @@ static void sdio_select_driver_type(struct mmc_card *card)
 {
 	int host_drv_type = SD_DRIVER_TYPE_B;
 	int card_drv_type = SD_DRIVER_TYPE_B;
-	int drive_strength;
+	int drive_strength, drv_type;
 	unsigned char card_strength;
 	int err;
 
-	/*
-	 * If the host doesn't support any of the Driver Types A,C or D,
-	 * or there is no board specific handler then default Driver
-	 * Type B is used.
-	 */
-	if (!(card->host->caps &
-		(MMC_CAP_DRIVER_TYPE_A |
-		 MMC_CAP_DRIVER_TYPE_C |
-		 MMC_CAP_DRIVER_TYPE_D)))
-		return;
-
 	if (!card->host->ops->select_drive_strength)
 		return;
 
@@ -443,25 +432,29 @@ static void sdio_select_driver_type(struct mmc_card *card)
 	 * information and let the hardware specific code
 	 * return what is possible given the options
 	 */
-	drive_strength = card->host->ops->select_drive_strength(
+	drive_strength = card->host->ops->select_drive_strength(card,
 		card->sw_caps.uhs_max_dtr,
-		host_drv_type, card_drv_type);
+		host_drv_type, card_drv_type, &drv_type);
 
-	/* if error just use default for drive strength B */
-	err = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_DRIVE_STRENGTH, 0,
-		&card_strength);
-	if (err)
-		return;
+	if (drive_strength) {
+		/* if error just use default for drive strength B */
+		err = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_DRIVE_STRENGTH, 0,
+				       &card_strength);
+		if (err)
+			return;
 
-	card_strength &= ~(SDIO_DRIVE_DTSx_MASK<<SDIO_DRIVE_DTSx_SHIFT);
-	card_strength |= host_drive_to_sdio_drive(drive_strength);
+		card_strength &= ~(SDIO_DRIVE_DTSx_MASK<<SDIO_DRIVE_DTSx_SHIFT);
+		card_strength |= host_drive_to_sdio_drive(drive_strength);
 
-	err = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_DRIVE_STRENGTH,
-		card_strength, NULL);
+		/* if error default to drive strength B */
+		err = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_DRIVE_STRENGTH,
+				       card_strength, NULL);
+		if (err)
+			return;
+	}
 
-	/* if error default to drive strength B */
-	if (!err)
-		mmc_set_driver_type(card->host, drive_strength);
+	if (drv_type)
+		mmc_set_driver_type(card->host, drv_type);
 }
 
 
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3483b6b6b880..acdee2827cd4 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
 obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
+obj-$(CONFIG_BRCM_SDIO)			+= sdhci-brcmstb.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
new file mode 100644
index 000000000000..a4ae21bd1adf
--- /dev/null
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -0,0 +1,605 @@
+/*
+ * sdhci-brcmstb.c Support for SDHCI on Broadcom SoC's
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * Author: Al Cooper <acooper@broadcom.com>
+ * Based on sdhci-dove.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/brcmstb/brcmstb.h>
+#include "sdhci-brcmstb.h"
+
+#include "sdhci-pltfm.h"
+
+#define SDIO_CFG_REG(x, y)	(x + BCHP_SDIO_0_CFG_##y -	\
+				BCHP_SDIO_0_CFG_REG_START)
+
+struct sdhci_brcmstb_priv {
+	void __iomem *cfg_regs;
+	int host_driver_type;
+	int host_hs_driver_type;
+	int card_driver_type;
+};
+
+#define MASK_OFF_DRV (SDHCI_PRESET_SDCLK_FREQ_MASK |	\
+			SDHCI_PRESET_CLKGEN_SEL_MASK)
+
+static char *strength_type_to_string[] = {"B", "A", "C", "D"};
+
+#if defined(CONFIG_BCM74371A0)
+/*
+ * HW7445-1183
+ * Setting the RESET_ALL or RESET_DATA bits will hang the SDIO
+ * core so don't allow these bits to be set. This workaround
+ * allows the driver to be used for development and testing
+ * but will prevent recovery from normally recoverable errors
+ * and should NOT be used in production systems.
+ */
+static void sdhci_brcmstb_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	if (reg == SDHCI_SOFTWARE_RESET)
+		val &= ~(SDHCI_RESET_ALL | SDHCI_RESET_DATA);
+	writeb(val, host->ioaddr + reg);
+}
+
+/* We don't support drive strength override on chips that use the
+ * old version of the SDIO core.
+ */
+static void set_host_driver_strength_overrides(
+	struct sdhci_host *host,
+	struct sdhci_brcmstb_priv *priv)
+{
+}
+
+#else /* CONFIG_BCM74371A0 */
+
+#ifndef CONFIG_MIPS
+static void set_host_driver_strength_overrides(
+	struct sdhci_host *host,
+	struct sdhci_brcmstb_priv *priv)
+{
+	u16 strength;
+	u16 sdr25;
+	u16 sdr50;
+	u16 ddr50;
+	u16 sdr104;
+	u32 val;
+	u32 cfg_base = (u32)priv->cfg_regs;
+
+	if (priv->host_driver_type) {
+		dev_info(mmc_dev(host->mmc),
+			"Changing UHS Host Driver TYPE Presets to TYPE %s\n",
+			strength_type_to_string[priv->host_driver_type]);
+		strength = (u16)priv->host_driver_type << 11;
+		sdr25 = sdhci_readw(host,
+				SDHCI_PRESET_FOR_SDR25) & MASK_OFF_DRV;
+		sdr50 = sdhci_readw(host,
+				SDHCI_PRESET_FOR_SDR50) & MASK_OFF_DRV;
+		ddr50 = sdhci_readw(host,
+				SDHCI_PRESET_FOR_DDR50) & MASK_OFF_DRV;
+		sdr104 = sdhci_readw(host,
+				SDHCI_PRESET_FOR_SDR104) & MASK_OFF_DRV;
+		val = (sdr25 | strength);
+		val |= ((u32)(sdr50 | strength)) << 16;
+		val |= 0x80000000;
+		DEV_WR(SDIO_CFG_REG(cfg_base, PRESET3), val);
+		val = (sdr104 | strength);
+		val |= ((u32)(ddr50 | strength)) << 16;
+		val |= 0x80000000;
+		DEV_WR(SDIO_CFG_REG(cfg_base, PRESET4), val);
+	}
+
+	/*
+	 * The Host Controller Specification states that the driver
+	 * strength setting is only valid for UHS modes, but our
+	 * host controller allows this setting to be used for HS modes
+	 * as well.
+	 */
+	if (priv->host_hs_driver_type) {
+		u16 sdr12;
+		u16 hs;
+
+		dev_info(mmc_dev(host->mmc),
+			"Changing HS Host Driver TYPE Presets to TYPE %s\n",
+			strength_type_to_string[priv->host_hs_driver_type]);
+		strength = (u16)priv->host_hs_driver_type << 11;
+		sdr12 = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12) &
+			MASK_OFF_DRV;
+		hs = sdhci_readw(host, SDHCI_PRESET_FOR_HS) & MASK_OFF_DRV;
+		val = (hs | strength);
+		val |= ((u32)(sdr12 | strength)) << 16;
+		val |= 0x80000000;
+		DEV_WR(SDIO_CFG_REG(cfg_base, PRESET2), val);
+	}
+}
+#else
+static void set_host_driver_strength_overrides(
+		struct sdhci_host *host,
+		struct sdhci_brcmstb_priv *priv)
+{
+}
+#endif /* CONFIG_MIPS */
+
+#endif /* CONFIG_BCM74371A0 */
+
+static int select_one_drive_strength(struct sdhci_host *host, int supported,
+				int requested, char *type)
+{
+	char strength_ok_msg[] = "Changing %s Driver to TYPE %s\n";
+	char strength_err_msg[] =
+		"Request to change %s Driver to TYPE %s not supported by %s\n";
+	if (supported & (1 << requested)) {
+		if (requested)
+			dev_info(mmc_dev(host->mmc), strength_ok_msg, type,
+				strength_type_to_string[requested], type);
+		return requested;
+	} else {
+		dev_warn(mmc_dev(host->mmc), strength_err_msg, type,
+			strength_type_to_string[requested], type);
+		return 0;
+	}
+}
+
+static int sdhci_brcmstb_select_drive_strength(struct sdhci_host *host,
+					struct mmc_card *card,
+					unsigned int max_dtr, int host_drv,
+					int card_drv, int *drv_type)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+	*drv_type = select_one_drive_strength(host, host_drv,
+					priv->host_driver_type,	"Host");
+	return select_one_drive_strength(host, card_drv,
+					priv->card_driver_type,	"Card");
+}
+
+#ifdef CONFIG_MIPS
+static int sdhci_brcmstb_supported(void)
+{
+	/* Chips with broken SDIO - 7429A0, 7435A0, 7425B0 and 7425B1 */
+	if ((BRCM_CHIP_ID() == 0x7425) &&
+	    ((BRCM_CHIP_REV() == 0x10) || (BRCM_CHIP_REV() == 0x11)))
+		return 0;
+	if ((BRCM_CHIP_ID() == 0x7429) && (BRCM_CHIP_REV() == 0x00))
+		return 0;
+	if ((BRCM_CHIP_ID() == 0x7435) && (BRCM_CHIP_REV() == 0x00))
+		return 0;
+	return 1;
+}
+
+
+static u32 sdhci_brcmstb_readl(struct sdhci_host *host, int reg)
+{
+	return __raw_readl(host->ioaddr + reg);
+}
+
+static void sdhci_brcmstb_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	__raw_writel(val, host->ioaddr + reg);
+}
+
+static u16 sdhci_brcmstb_readw(struct sdhci_host *host, int reg)
+{
+	return __raw_readw(host->ioaddr + reg);
+}
+
+static void sdhci_brcmstb_writew(struct sdhci_host *host, u16 val, int reg)
+{
+#if defined(CONFIG_BCM7425B0)
+	if (reg == SDHCI_HOST_CONTROL2 && BRCM_CHIP_REV() == 0x12) {
+		/* HW7425-1414: I/O voltage uses Power Control Register (29h) */
+		int pow_reg = __raw_readb(host->ioaddr + SDHCI_POWER_CONTROL);
+
+		pow_reg &= ~SDHCI_POWER_330;
+		if (val & SDHCI_CTRL_VDD_180)
+			pow_reg |= SDHCI_POWER_180;
+		else
+			pow_reg |= SDHCI_POWER_330;
+		__raw_writeb(pow_reg, host->ioaddr + SDHCI_POWER_CONTROL);
+	}
+#endif
+	__raw_writew(val, host->ioaddr + reg);
+}
+#endif
+
+static struct sdhci_ops sdhci_brcmstb_ops = {
+	.select_drive_strength	= sdhci_brcmstb_select_drive_strength,
+#ifdef CONFIG_MIPS
+	.read_w		= sdhci_brcmstb_readw,
+	.write_w	= sdhci_brcmstb_writew,
+	.read_l		= sdhci_brcmstb_readl,
+	.write_l	= sdhci_brcmstb_writel,
+#endif
+};
+
+static struct sdhci_pltfm_data sdhci_brcmstb_pdata = {
+#ifdef CONFIG_MIPS
+	.quirks2 = SDHCI_QUIRK2_NO_1_8_V
+#endif
+};
+
+#if defined(CONFIG_BCM3390A0) || defined(CONFIG_BCM7250B0) ||	\
+	defined(CONFIG_BCM7364A0) || defined(CONFIG_BCM7445D0)
+static void sdhci_override_caps(struct sdhci_host *host,
+				struct sdhci_brcmstb_priv *priv,
+				uint32_t cap0_setbits,
+				uint32_t cap0_clearbits,
+				uint32_t cap1_setbits,
+				uint32_t cap1_clearbits)
+{
+	uint32_t val;
+	void *cfg_base = priv->cfg_regs;
+
+	/*
+	 * The CAP's override bits in the CFG registers default to all
+	 * zeros so start by getting the correct settings from the HOST
+	 * CAPS registers and then modify the requested bits and write
+	 * them to the override CFG registers.
+	 */
+	val = sdhci_readl(host, SDHCI_CAPABILITIES);
+	val &= ~cap0_clearbits;
+	val |= cap0_setbits;
+	DEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG0), val);
+	val = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+	val &= ~cap1_clearbits;
+	val |= cap1_setbits;
+	DEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG1), val);
+	DEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG_OVERRIDE),
+		BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK);
+}
+#elif !defined(CONFIG_MIPS)
+static inline void sdhci_override_caps(struct sdhci_host *host,
+				       struct sdhci_brcmstb_priv *priv,
+				       uint32_t cap0_setbits,
+				       uint32_t cap0_clearbits,
+				       uint32_t cap1_setbits,
+				       uint32_t cap1_clearbits)
+{
+}
+#endif
+
+#if !defined(CONFIG_MIPS)
+static void sdhci_fix_caps(struct sdhci_host *host,
+			struct sdhci_brcmstb_priv *priv)
+{
+#if defined(CONFIG_BCM7445D0)
+	/* Fixed for E0 and above */
+	if (BRCM_CHIP_REV() >= 0x40)
+		return;
+#endif
+	/* Disable SDR50 support because tuning is broken. */
+	sdhci_override_caps(host, priv, 0, 0, 0, SDHCI_SUPPORT_SDR50);
+}
+
+#else
+
+#define SDIO_CFG_SET(base, reg, mask) do {				\
+		DEV_SET(SDIO_CFG_REG(base, reg),			\
+			 BCHP_SDIO_0_CFG_##reg##_##mask##_MASK);	\
+	} while (0)
+#define SDIO_CFG_UNSET(base, reg, mask) do {				\
+		DEV_UNSET(SDIO_CFG_REG(base, reg),			\
+			   BCHP_SDIO_0_CFG_##reg##_##mask##_MASK);	\
+	} while (0)
+#define SDIO_CFG_FIELD(base, reg, field, val) do {			\
+		DEV_UNSET(SDIO_CFG_REG(base, reg),			\
+			   BCHP_SDIO_0_CFG_##reg##_##field##_MASK);	\
+		DEV_SET(SDIO_CFG_REG(base, reg),			\
+		 val << BCHP_SDIO_0_CFG_##reg##_##field##_SHIFT);	\
+	} while (0)
+
+#define SDHCI_OVERRIDE_OPTIONS_NONE		0x00000000
+#define SDHCI_OVERRIDE_OPTIONS_UHS_SDR50	0x00000001
+#define SDHCI_OVERRIDE_OPTIONS_TUNING		0x00000002
+
+#define CAP0_SHIFT(field) BCHP_SDIO_0_CFG_CAP_REG0_##field##_SHIFT
+#define CAP1_SHIFT(field) BCHP_SDIO_0_CFG_CAP_REG1_##field##_SHIFT
+
+static inline void sdhci_override_caps(void __iomem *cfg_base, int base_clock,
+				       int timeout_clock, int options)
+{
+	uint32_t val;
+
+	/* Set default for every field with all options off */
+	val = (0 << CAP0_SHIFT(DDR50_SUPPORT) |			\
+	       0 << CAP0_SHIFT(SD104_SUPPORT) |			\
+	       0 << CAP0_SHIFT(SDR50) |				\
+	       0 << CAP0_SHIFT(SLOT_TYPE) |			\
+	       0 << CAP0_SHIFT(ASYNCH_INT_SUPPORT) |		\
+	       0 << CAP0_SHIFT(64B_SYS_BUS_SUPPORT) |		\
+	       0 << CAP0_SHIFT(1_8V_SUPPORT) |			\
+	       0 << CAP0_SHIFT(3_0V_SUPPORT) |			\
+	       1 << CAP0_SHIFT(3_3V_SUPPORT) |			\
+	       1 << CAP0_SHIFT(SUSP_RES_SUPPORT) |		\
+	       1 << CAP0_SHIFT(SDMA_SUPPORT) |			\
+	       1 << CAP0_SHIFT(HIGH_SPEED_SUPPORT) |		\
+	       1 << CAP0_SHIFT(ADMA2_SUPPORT) |			\
+	       1 << CAP0_SHIFT(EXTENDED_MEDIA_SUPPORT) |	\
+	       1 << CAP0_SHIFT(MAX_BL) |			\
+	       0 << CAP0_SHIFT(BASE_FREQ) |			\
+	       1 << CAP0_SHIFT(TIMEOUT_CLK_UNIT) |		\
+	       0 << CAP0_SHIFT(TIMEOUT_FREQ));
+
+	val |= (base_clock << CAP0_SHIFT(BASE_FREQ));
+	val |= (timeout_clock << CAP0_SHIFT(TIMEOUT_FREQ));
+	if (options & SDHCI_OVERRIDE_OPTIONS_UHS_SDR50)
+		val |= (1 << CAP0_SHIFT(SDR50)) |
+			(1 << CAP0_SHIFT(1_8V_SUPPORT));
+	DEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG0), val);
+
+	val = (1 << CAP1_SHIFT(CAP_REG_OVERRIDE) |	\
+	       0 << CAP1_SHIFT(SPI_BLK_MODE) |		\
+	       0 << CAP1_SHIFT(SPI_MODE) |		\
+	       0 << CAP1_SHIFT(CLK_MULT) |		\
+	       0 << CAP1_SHIFT(RETUNING_MODES) |	\
+	       0 << CAP1_SHIFT(USE_TUNING) |		\
+	       0 << CAP1_SHIFT(RETUNING_TIMER) |	\
+	       0 << CAP1_SHIFT(Driver_D_SUPPORT) |	\
+	       0 << CAP1_SHIFT(Driver_C_SUPPORT) |	\
+	       0 << CAP1_SHIFT(Driver_A_SUPPORT));
+	DEV_WR(SDIO_CFG_REG(cfg_base, CAP_REG1), val);
+}
+static void sdhci_fix_caps(struct sdhci_host *host,
+			struct sdhci_brcmstb_priv *priv)
+{
+	void __iomem *cfg_base = priv->cfg_regs;
+
+	if (DEV_RD(SDIO_CFG_REG(cfg_base, SCRATCH)) & 0x01) {
+		dev_info(mmc_dev(host->mmc), "Disabled by bootloader\n");
+		return;
+	}
+	dev_info(mmc_dev(host->mmc), "Enabling controller\n");
+	DEV_UNSET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0xf000);
+	DEV_UNSET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL2), 0x00ff);
+
+	/*
+	 * This is broken on all chips and defaults to enabled on
+	 * some chips so disable it.
+	 */
+	SDIO_CFG_UNSET(cfg_base, SDIO_EMMC_CTRL1, SCB_SEQ_EN);
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+	/* FRAME_NHW | BUFFER_ABO */
+	DEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0x3000);
+#else
+	/* WORD_ABO | FRAME_NBO | FRAME_NHW */
+	DEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL1), 0xe000);
+	/* address swap only */
+	DEV_SET(SDIO_CFG_REG(cfg_base, SDIO_EMMC_CTRL2), 0x0050);
+#endif
+
+#if defined(CONFIG_BCM7231B0) || defined(CONFIG_BCM7346B0)
+	SDIO_CFG_SET(cfg_base, CAP_REG1, CAP_REG_OVERRIDE);
+#elif defined(CONFIG_BCM7344B0)
+	SDIO_CFG_SET(cfg_base, CAP_REG0, HIGH_SPEED_SUPPORT);
+	SDIO_CFG_SET(cfg_base, CAP_REG1, CAP_REG_OVERRIDE);
+#elif defined(CONFIG_BCM7425)
+	/*
+	 * HW7425-1352: Disable TUNING because it's broken.
+	 * Use manual input and output clock delays to work around
+	 * 7425B2 timing issues.
+	 */
+	if (BRCM_CHIP_REV() == 0x12) {
+		/* disable tuning */
+		sdhci_override_caps(cfg_base, 100, 50,
+				    SDHCI_OVERRIDE_OPTIONS_UHS_SDR50);
+
+		/* enable input delay, resolution = 1, value = 8 */
+		SDIO_CFG_FIELD(cfg_base, IP_DLY, IP_TAP_DELAY, 8);
+		SDIO_CFG_FIELD(cfg_base, IP_DLY, IP_DELAY_CTRL, 1);
+		SDIO_CFG_SET(cfg_base, IP_DLY, IP_TAP_EN);
+
+		/* enable output delay */
+		SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_TAP_DELAY, 4);
+		SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_DELAY_CTRL, 3);
+		SDIO_CFG_SET(cfg_base, OP_DLY, OP_TAP_EN);
+
+		/* Use the manual clock delay */
+		SDIO_CFG_FIELD(cfg_base, SD_CLOCK_DELAY, INPUT_CLOCK_DELAY, 8);
+	}
+#elif defined(CONFIG_BCM7563A0)
+	sdhci_override_caps(cfg_base, 50, 50, SDHCI_OVERRIDE_OPTIONS_NONE);
+#elif defined(CONFIG_BCM7584A0)
+	/* enable output delay */
+	SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_TAP_DELAY, 4);
+	SDIO_CFG_FIELD(cfg_base, OP_DLY, OP_DELAY_CTRL, 3);
+	SDIO_CFG_SET(cfg_base, OP_DLY, OP_TAP_EN);
+#endif
+}
+#endif /* CONFIG_MIPS */
+
+#ifdef CONFIG_PM_SLEEP
+
+static int sdhci_brcmstb_suspend(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	int res;
+
+	res = sdhci_suspend_host(host);
+	if (res)
+		return res;
+	clk_disable(pltfm_host->clk);
+	return res;
+}
+
+static int sdhci_brcmstb_resume(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+	int err;
+
+	err = clk_enable(pltfm_host->clk);
+	if (err)
+		return err;
+	sdhci_fix_caps(host, priv);
+	set_host_driver_strength_overrides(host, priv);
+	return sdhci_resume_host(host);
+}
+
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(sdhci_brcmstb_pmops, sdhci_brcmstb_suspend,
+			sdhci_brcmstb_resume);
+
+static void sdhci_brcmstb_of_get_driver_type(struct device_node *dn,
+					char *name, int *dtype)
+{
+	const char *driver_type;
+	int res;
+
+	res = of_property_read_string(dn, name, &driver_type);
+	if (res == 0) {
+		if (strcmp(driver_type, "A") == 0)
+			*dtype = MMC_SET_DRIVER_TYPE_A;
+		else if (strcmp(driver_type, "B") == 0)
+			*dtype = MMC_SET_DRIVER_TYPE_B;
+		else if (strcmp(driver_type, "C") == 0)
+			*dtype = MMC_SET_DRIVER_TYPE_C;
+		else if (strcmp(driver_type, "D") == 0)
+			*dtype = MMC_SET_DRIVER_TYPE_D;
+	}
+}
+
+
+static int sdhci_brcmstb_probe(struct platform_device *pdev)
+{
+	struct sdhci_brcmstb_pdata *pdata = pdev->dev.platform_data;
+	struct device_node *dn = pdev->dev.of_node;
+	struct sdhci_host *host;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct sdhci_brcmstb_priv *priv;
+	struct clk *clk;
+	struct resource *resource;
+	int res;
+
+#ifdef CONFIG_MIPS
+	if (!sdhci_brcmstb_supported()) {
+		dev_info(&pdev->dev, "Disabled, unsupported chip revision\n");
+		return -ENODEV;
+	}
+#endif
+
+	clk = of_clk_get_by_name(dn, "sw_sdio");
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "Clock not found in Device Tree\n");
+		clk = NULL;
+	}
+	res = clk_prepare_enable(clk);
+	if (res)
+		goto undo_clk_get;
+
+#if defined(CONFIG_BCM74371A0)
+	/* Only enable reset workaround for 74371a0 senior */
+	if (BRCM_CHIP_ID() == 0x7439)
+		sdhci_brcmstb_ops.write_b = sdhci_brcmstb_writeb;
+#endif /* CONFIG_BCM74371A0 */
+	sdhci_brcmstb_pdata.ops = &sdhci_brcmstb_ops;
+	host = sdhci_pltfm_init(pdev, &sdhci_brcmstb_pdata,
+				sizeof(struct sdhci_brcmstb_priv));
+	if (IS_ERR(host)) {
+		res = PTR_ERR(host);
+		goto undo_clk_prep;
+	}
+
+
+	/* Enable MMC_CAP2_HC_ERASE_SZ for better max discard calculations */
+	host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
+	if (pdata) {
+		host->mmc->caps |= pdata->caps;
+		host->mmc->caps2 |= pdata->caps2;
+	}
+
+	sdhci_get_of_property(pdev);
+	mmc_of_parse(host->mmc);
+	pltfm_host = sdhci_priv(host);
+	priv = sdhci_pltfm_priv(pltfm_host);
+	resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (resource == NULL) {
+		dev_err(&pdev->dev, "can't get SDHCI CFG base address\n");
+		return -EINVAL;
+	}
+	priv->cfg_regs = devm_request_and_ioremap(&pdev->dev, resource);
+	if (!priv->cfg_regs) {
+		dev_err(&pdev->dev, "can't map register space\n");
+		return -EINVAL;
+	}
+	sdhci_fix_caps(host, priv);
+
+	sdhci_brcmstb_of_get_driver_type(dn, "host-driver-strength",
+					&priv->host_driver_type);
+	sdhci_brcmstb_of_get_driver_type(dn, "host-hs-driver-strength",
+					&priv->host_hs_driver_type);
+	sdhci_brcmstb_of_get_driver_type(dn, "card-driver-strength",
+					&priv->card_driver_type);
+	set_host_driver_strength_overrides(host, priv);
+
+	res = sdhci_add_host(host);
+	if (res)
+		goto undo_pltfm_init;
+
+	pltfm_host->clk = clk;
+	return res;
+
+undo_pltfm_init:
+	sdhci_pltfm_free(pdev);
+undo_clk_prep:
+	clk_disable_unprepare(clk);
+undo_clk_get:
+	clk_put(clk);
+	return res;
+}
+
+static int sdhci_brcmstb_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	int res;
+	res = sdhci_pltfm_unregister(pdev);
+	clk_disable_unprepare(pltfm_host->clk);
+	clk_put(pltfm_host->clk);
+	return res;
+}
+
+
+static const struct of_device_id sdhci_brcm_of_match[] = {
+	{ .compatible = "brcm,sdhci-brcmstb" },
+	{},
+};
+
+static struct platform_driver sdhci_brcmstb_driver = {
+	.driver		= {
+		.name	= "sdhci-brcmstb",
+		.owner	= THIS_MODULE,
+		.pm	= &sdhci_brcmstb_pmops,
+		.of_match_table = of_match_ptr(sdhci_brcm_of_match),
+	},
+	.probe		= sdhci_brcmstb_probe,
+	.remove		= sdhci_brcmstb_remove,
+};
+
+module_platform_driver(sdhci_brcmstb_driver);
+
+MODULE_DESCRIPTION("SDHCI driver for Broadcom");
+MODULE_AUTHOR("Al Cooper <acooper@broadcom.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-brcmstb.h b/drivers/mmc/host/sdhci-brcmstb.h
new file mode 100644
index 000000000000..7867e735778d
--- /dev/null
+++ b/drivers/mmc/host/sdhci-brcmstb.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+struct sdhci_brcmstb_pdata {
+	unsigned long caps;
+	unsigned long caps2;
+};
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 75d3c28940f1..74b5a948d6fc 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1026,6 +1026,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 	mod_timer(&host->timer, timeout);
 
 	host->cmd = cmd;
+	host->busy_handle = 0;
 
 	sdhci_prepare_data(host, cmd);
 
@@ -1527,8 +1528,18 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
 			ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
 			if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
 				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
+			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
+				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
 			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
 				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
+			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
+				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
+			else {
+				pr_warn("%s: invalid driver type, default to "
+					"driver type B\n",
+					mmc_hostname(host->mmc));
+				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
+			}
 
 			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 		} else {
@@ -1860,7 +1871,6 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	u16 ctrl;
 	u32 ier;
 	int tuning_loop_counter = MAX_TUNING_LOOP;
-	unsigned long timeout;
 	int err = 0;
 	bool requires_tuning_nonuhs = false;
 	unsigned long flags;
@@ -1919,14 +1929,10 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
 	 * of loops reaches 40 times or a timeout of 150ms occurs.
 	 */
-	timeout = 150;
 	do {
 		struct mmc_command cmd = {0};
 		struct mmc_request mrq = {NULL};
 
-		if (!tuning_loop_counter && !timeout)
-			break;
-
 		cmd.opcode = opcode;
 		cmd.arg = 0;
 		cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
@@ -1934,6 +1940,9 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 		cmd.data = NULL;
 		cmd.error = 0;
 
+		if (tuning_loop_counter-- == 0)
+			break;
+
 		mrq.cmd = &cmd;
 		host->mrq = &mrq;
 
@@ -1991,8 +2000,6 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 		host->tuning_done = 0;
 
 		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-		tuning_loop_counter--;
-		timeout--;
 		mdelay(1);
 	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 
@@ -2000,17 +2007,15 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	 * The Host Driver has exhausted the maximum number of loops allowed,
 	 * so use fixed sampling frequency.
 	 */
-	if (!tuning_loop_counter || !timeout) {
+	if (tuning_loop_counter < 0) {
 		ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+	}
+	if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+		pr_info(DRIVER_NAME ": Tuning procedure"
+			" failed, falling back to fixed sampling"
+			" clock\n");
 		err = -EIO;
-	} else {
-		if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
-			pr_info(DRIVER_NAME ": Tuning procedure"
-				" failed, falling back to fixed sampling"
-				" clock\n");
-			err = -EIO;
-		}
 	}
 
 out:
@@ -2053,6 +2058,18 @@ out:
 	return err;
 }
 
+static int sdhci_select_drive_strength(struct mmc_card *card,
+				       unsigned int max_dtr, int host_drv,
+				       int card_drv, int *drv_type)
+{
+	struct sdhci_host *host = mmc_priv(card->host);
+
+	if (!host->ops->select_drive_strength)
+		return 0;
+
+	return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
+						card_drv, drv_type);
+}
 
 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
 {
@@ -2119,6 +2136,7 @@ static const struct mmc_host_ops sdhci_ops = {
 	.enable_sdio_irq = sdhci_enable_sdio_irq,
 	.start_signal_voltage_switch	= sdhci_start_signal_voltage_switch,
 	.execute_tuning			= sdhci_execute_tuning,
+	.select_drive_strength		= sdhci_select_drive_strength,
 	.card_event			= sdhci_card_event,
 	.card_busy	= sdhci_card_busy,
 };
@@ -2286,8 +2304,12 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 		if (host->cmd->data)
 			DBG("Cannot wait for busy signal when also "
 				"doing a data transfer");
-		else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
+		else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
+				&& !host->busy_handle) {
+			/* Mark that command complete before busy is ended */
+			host->busy_handle = 1;
 			return;
+		}
 
 		/* The controller does not support the end-of-busy IRQ,
 		 * fall through and take the SDHCI_INT_RESPONSE */
@@ -2350,7 +2372,15 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 		 */
 		if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
 			if (intmask & SDHCI_INT_DATA_END) {
-				sdhci_finish_command(host);
+				/*
+				 * Some cards handle busy-end interrupt
+				 * before the command completed, so make
+				 * sure we do things in the proper order.
+				 */
+				if (host->busy_handle)
+					sdhci_finish_command(host);
+				else
+					host->busy_handle = 1;
 				return;
 			}
 		}
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0a3ed01887db..d9c082539942 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -229,6 +229,7 @@
 
 /* 60-FB reserved */
 
+#define SDHCI_PRESET_FOR_HS 0x64
 #define SDHCI_PRESET_FOR_SDR12 0x66
 #define SDHCI_PRESET_FOR_SDR25 0x68
 #define SDHCI_PRESET_FOR_SDR50 0x6A
@@ -296,6 +297,10 @@ struct sdhci_ops {
 	void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 	void	(*platform_init)(struct sdhci_host *host);
 	void    (*card_event)(struct sdhci_host *host);
+	int	(*select_drive_strength)(struct sdhci_host *host,
+					 struct mmc_card *card,
+					 unsigned int max_dtr, int host_drv,
+					 int card_drv, int *drv_type);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/drivers/mtd/devices/block2mtd.c b/drivers/mtd/devices/block2mtd.c
index d9fd87a4c8dc..b69bbeb24599 100644
--- a/drivers/mtd/devices/block2mtd.c
+++ b/drivers/mtd/devices/block2mtd.c
@@ -22,6 +22,8 @@
 #include <linux/slab.h>
 #include <linux/major.h>
 
+extern int del_mtd_device(struct mtd_info *mtd);
+
 /* Info for the block device */
 struct block2mtd_dev {
 	struct list_head list;
@@ -210,7 +212,7 @@ static void block2mtd_free_device(struct block2mtd_dev *dev)
 
 
 /* FIXME: ensure that mtd->size % erase_size == 0 */
-static struct block2mtd_dev *add_device(char *devname, int erase_size)
+static struct block2mtd_dev *add_device(char *devname, int erase_size, int write_size)
 {
 	const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL;
 	struct block_device *bdev;
@@ -261,7 +263,7 @@ static struct block2mtd_dev *add_device(char *devname, int erase_size)
 
 	dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
 	dev->mtd.erasesize = erase_size;
-	dev->mtd.writesize = 1;
+	dev->mtd.writesize = write_size;
 	dev->mtd.writebufsize = PAGE_SIZE;
 	dev->mtd.type = MTD_RAM;
 	dev->mtd.flags = MTD_CAP_RAM;
@@ -277,10 +279,11 @@ static struct block2mtd_dev *add_device(char *devname, int erase_size)
 		goto devinit_err;
 	}
 	list_add(&dev->list, &blkmtd_device_list);
-	pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n",
+	pr_info("mtd%d: [%s] erase_size = %dKiB [%d] write_size = %dKiB [%d]\n",
 		dev->mtd.index,
 		dev->mtd.name + strlen("block2mtd: "),
-		dev->mtd.erasesize >> 10, dev->mtd.erasesize);
+		dev->mtd.erasesize >> 10, dev->mtd.erasesize,
+		dev->mtd.writesize >> 10, dev->mtd.writesize);
 	return dev;
 
 devinit_err:
@@ -342,16 +345,43 @@ static inline void kill_final_newline(char *str)
 
 #ifndef MODULE
 static int block2mtd_init_called = 0;
-static char block2mtd_paramline[80 + 12]; /* 80 for device, 12 for erase size */
+static char block2mtd_paramline[80 + 12 + 12]; /* 80 for device, 12 for erase size, 12 for writesize */
 #endif
 
+static void remove_device_by_name(const char *name)
+{
+	struct list_head *pos, *next;
+	int name_offset = strlen("block2mtd: ");
+
+	list_for_each_safe(pos, next, &blkmtd_device_list) {
+		struct block2mtd_dev *dev = list_entry(pos, typeof(*dev), list);
+		if (!strcmp(name, dev->mtd.name + name_offset)) {
+			int err;
+			block2mtd_sync(&dev->mtd);
+			err = del_mtd_device(&dev->mtd);
+			if (err == 0) {
+				pr_info("mtd%d: [%s] removed\n",
+						dev->mtd.index, name);
+				list_del(&dev->list);
+				block2mtd_free_device(dev);
+			} else
+				pr_err("mtd%d: [%s] cannot remove: %d\n",
+						dev->mtd.index, name, err);
+
+			return;
+		}
+	}
+	pr_err("no such device: %s\n", name);
+}
+
 static int block2mtd_setup2(const char *val)
 {
-	char buf[80 + 12]; /* 80 for device, 12 for erase size */
+	char buf[80 + 12 + 12]; /* 80 for device, 12 for erase size, 12 for writesize */
 	char *str = buf;
-	char *token[2];
+	char *token[3];
 	char *name;
 	size_t erase_size = PAGE_SIZE;
+	size_t write_size = 1;
 	int i, ret;
 
 	if (strnlen(val, sizeof(buf)) >= sizeof(buf)) {
@@ -362,7 +392,7 @@ static int block2mtd_setup2(const char *val)
 	strcpy(str, val);
 	kill_final_newline(str);
 
-	for (i = 0; i < 2; i++)
+	for (i = 0; i < 3; i++)
 		token[i] = strsep(&str, ",");
 
 	if (str) {
@@ -382,14 +412,24 @@ static int block2mtd_setup2(const char *val)
 	}
 
 	if (token[1]) {
+		if (!strcmp("remove", token[1])) {
+			remove_device_by_name(name);
+			return 0;
+		}
 		ret = parse_num(&erase_size, token[1]);
 		if (ret) {
 			pr_err("illegal erase size\n");
 			return 0;
 		}
 	}
+	if (token[2]) {
+		ret = parse_num(&write_size, token[2]);
+		if (ret) {
+			parse_err("illegal write size");
+		}
+	}
 
-	add_device(name, erase_size);
+	add_device(name, erase_size, write_size);
 
 	return 0;
 }
@@ -423,7 +463,7 @@ static int block2mtd_setup(const char *val, struct kernel_param *kp)
 
 
 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
+MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>,<writesize>]\"");
 
 static int __init block2mtd_init(void)
 {
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index ad1913909702..a68e79db01a8 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -50,6 +50,7 @@
 #define	OPCODE_SE		0xd8	/* Sector erase (usually 64KiB) */
 #define	OPCODE_RDID		0x9f	/* Read JEDEC ID */
 #define	OPCODE_RDCR             0x35    /* Read configuration register */
+#define OPCODE_RDFSR		0x70	/* Read flag status register */
 
 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
 #define	OPCODE_NORM_READ_4B	0x13	/* Read data bytes (low frequency) */
@@ -81,6 +82,9 @@
 
 #define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
 
+/* Flag Status Register bits */
+#define FSR_READY		0x80
+
 /* Configuration Register bits. */
 #define CR_QUAD_EN_SPAN		0x2     /* Spansion Quad I/O */
 
@@ -98,6 +102,10 @@ enum read_type {
 	M25P80_QUAD,
 };
 
+enum m25p_option_flags {
+	M25P_F_USE_FSR		= BIT(0),
+};
+
 struct m25p {
 	struct spi_device	*spi;
 	struct mutex		lock;
@@ -109,6 +117,8 @@ struct m25p {
 	u8			program_opcode;
 	u8			*command;
 	enum read_type		flash_read;
+
+	u32			flags;
 };
 
 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -145,6 +155,26 @@ static int read_sr(struct m25p *flash)
 }
 
 /*
+ * Read the flag status register, returning its value in the location
+ * Return the status register value.
+ * Returns negative if error occurred.
+ */
+static int read_fsr(struct m25p *flash)
+{
+	ssize_t ret;
+	u8 code = OPCODE_RDFSR;
+	u8 val;
+
+	ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
+	if (ret < 0) {
+		dev_err(&flash->spi->dev, "error %d reading FSR\n", (int)ret);
+		return ret;
+	}
+
+	return val;
+}
+
+/*
  * Read configuration register, returning its value in the
  * location. Return the configuration register value.
  * Returns negative if error occured.
@@ -233,7 +263,7 @@ static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
  * Service routine to read status register until ready, or timeout occurs.
  * Returns non-zero if error.
  */
-static int wait_till_ready(struct m25p *flash)
+static int wait_till_sr_ready(struct m25p *flash)
 {
 	unsigned long deadline;
 	int sr;
@@ -253,6 +283,40 @@ static int wait_till_ready(struct m25p *flash)
 	return 1;
 }
 
+static int wait_till_fsr_ready(struct m25p *flash)
+{
+	unsigned long deadline;
+	int sr;
+	int fsr;
+
+	deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+
+	do {
+		cond_resched();
+
+		sr = read_sr(flash);
+		if (sr < 0) {
+			break;
+		} else if (!(sr & SR_WIP)) {
+			fsr = read_fsr(flash);
+			if (fsr < 0)
+				break;
+			if (fsr & FSR_READY)
+				return 0;
+		}
+	} while (!time_after_eq(jiffies, deadline));
+
+	return -ETIMEDOUT;
+}
+
+static int wait_till_ready(struct m25p *flash)
+{
+	if (flash->flags & M25P_F_USE_FSR)
+		return wait_till_fsr_ready(flash);
+	else
+		return wait_till_sr_ready(flash);
+}
+
 /*
  * Write status Register and configuration register with 2 bytes
  * The first byte will be written to the status register, while the
@@ -856,6 +920,7 @@ struct flash_info {
 #define	M25P_NO_FR	0x08		/* Can't do fastread */
 #define	SECT_4K_PMC	0x10		/* OPCODE_BE_4K_PMC works uniformly */
 #define	M25P80_QUAD_READ	0x20    /* Flash supports Quad Read */
+#define USE_FSR		0x80		/* use flag status register */
 };
 
 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)	\
@@ -903,6 +968,7 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "en25q32b",   INFO(0x1c3016, 0, 64 * 1024,   64, 0) },
 	{ "en25p64",    INFO(0x1c2017, 0, 64 * 1024,  128, 0) },
 	{ "en25q64",    INFO(0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
+	{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, SECT_4K) },
 	{ "en25qh256",  INFO(0x1c7019, 0, 64 * 1024,  512, 0) },
 
 	/* ESMT */
@@ -941,6 +1007,8 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, 0) },
 	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K) },
 	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
+	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
+	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
 
 	/* PMC */
 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
@@ -1191,6 +1259,9 @@ static int m25p_probe(struct spi_device *spi)
 	else
 		flash->mtd._write = m25p80_write;
 
+	if ((info->flags & USE_FSR))
+		flash->flags |= M25P_F_USE_FSR;
+
 	/* prefer "small sector" erase if possible */
 	if (info->flags & SECT_4K) {
 		flash->erase_opcode = OPCODE_BE_4K;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 542b5689eb63..c11bc5c3f5b8 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_BCH)		+= nand_bch.o
 obj-$(CONFIG_MTD_NAND_IDS)		+= nand_ids.o
 obj-$(CONFIG_MTD_SM_COMMON) 		+= sm_common.o
 
+obj-$(CONFIG_MTD_NAND_BRCMSTB)		+= brcmstb_nand.o
 obj-$(CONFIG_MTD_NAND_CAFE)		+= cafe_nand.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-delta.o
 obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
diff --git a/drivers/mtd/nand/brcmstb_nand.c b/drivers/mtd/nand/brcmstb_nand.c
new file mode 100644
index 000000000000..c2512e3d32c0
--- /dev/null
+++ b/drivers/mtd/nand/brcmstb_nand.c
@@ -0,0 +1,2087 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/bug.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/mm.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of.h>
+#include <linux/of_mtd.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+/*
+ * SWLINUX-1818: this flag controls if WP stays on between erase/write
+ * commands to mitigate flash corruption due to power glitches. Values:
+ * 0: NAND_WP is not used or not available
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
+static int wp_on = 1;
+module_param(wp_on, int, 0444);
+
+/***********************************************************************
+ * Definitions
+ ***********************************************************************/
+
+#define DBG(args...)		pr_debug(args)
+
+#define DRV_NAME		"brcmstb_nand"
+#define CONTROLLER_VER		(10 * CONFIG_BRCMNAND_MAJOR_VERS + \
+		CONFIG_BRCMNAND_MINOR_VERS)
+
+#define CMD_NULL		0x00
+#define CMD_PAGE_READ		0x01
+#define CMD_SPARE_AREA_READ	0x02
+#define CMD_STATUS_READ		0x03
+#define CMD_PROGRAM_PAGE	0x04
+#define CMD_PROGRAM_SPARE_AREA	0x05
+#define CMD_COPY_BACK		0x06
+#define CMD_DEVICE_ID_READ	0x07
+#define CMD_BLOCK_ERASE		0x08
+#define CMD_FLASH_RESET		0x09
+#define CMD_BLOCKS_LOCK		0x0a
+#define CMD_BLOCKS_LOCK_DOWN	0x0b
+#define CMD_BLOCKS_UNLOCK	0x0c
+#define CMD_READ_BLOCKS_LOCK_STATUS	0x0d
+
+#if CONTROLLER_VER >= 40
+#define CMD_PARAMETER_READ	0x0e
+#define CMD_PARAMETER_CHANGE_COL	0x0f
+#define CMD_LOW_LEVEL_OP	0x10
+#endif
+
+struct brcm_nand_dma_desc {
+	u32 next_desc;
+	u32 next_desc_ext;
+	u32 cmd_irq;
+	u32 dram_addr;
+	u32 dram_addr_ext;
+	u32 tfr_len;
+	u32 total_len;
+	u32 flash_addr;
+	u32 flash_addr_ext;
+	u32 cs;
+	u32 pad2[5];
+	u32 status_valid;
+} __packed;
+
+/* Bitfields for brcm_nand_dma_desc::status_valid */
+#define FLASH_DMA_ECC_ERROR	(1 << 8)
+#define FLASH_DMA_CORR_ERROR	(1 << 9)
+
+/* 512B flash cache in the NAND controller HW */
+#define FC_SHIFT		9U
+#define FC_BYTES		512U
+#define FC_WORDS		(FC_BYTES >> 2)
+#define FC(x)			(BCHP_NAND_FLASH_CACHEi_ARRAY_BASE + ((x) << 2))
+
+#if CONTROLLER_VER >= 60
+#define MAX_CONTROLLER_OOB	64
+#define OFS_10_RD		BCHP_NAND_SPARE_AREA_READ_OFS_10
+#define OFS_10_WR		BCHP_NAND_SPARE_AREA_WRITE_OFS_10
+#elif CONTROLLER_VER >= 50
+#define MAX_CONTROLLER_OOB	32
+#define OFS_10_RD		BCHP_NAND_SPARE_AREA_READ_OFS_10
+#define OFS_10_WR		BCHP_NAND_SPARE_AREA_WRITE_OFS_10
+#else
+#define MAX_CONTROLLER_OOB	16
+#define OFS_10_RD		-1
+#define OFS_10_WR		-1
+#endif
+
+#if CONTROLLER_VER >= 71
+#define REG_SPACING		0x14UL
+#else
+#define REG_SPACING		0x10UL
+#endif
+
+#if CONTROLLER_VER >= 60
+
+#define REG_ACC_CONTROL(cs) (BCHP_NAND_ACC_CONTROL_CS0 + ((cs) * REG_SPACING))
+
+#define REG_CONFIG(cs) (BCHP_NAND_CONFIG_CS0 + ((cs) * REG_SPACING))
+#define REG_CONFIG_EXT(cs) (BCHP_NAND_CONFIG_EXT_CS0 + ((cs) * REG_SPACING))
+
+#define REG_TIMING_1(cs) (BCHP_NAND_TIMING_1_CS0 + ((cs) * REG_SPACING))
+#define REG_TIMING_2(cs) (BCHP_NAND_TIMING_2_CS0 + ((cs) * REG_SPACING))
+
+#define CORR_ERROR_COUNT (BDEV_RD(BCHP_NAND_CORR_ERROR_COUNT))
+
+#define WR_CORR_THRESH(cs, val) do { \
+	u32 contents = BDEV_RD(BCHP_NAND_CORR_STAT_THRESHOLD); \
+	u32 shift = BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT * (cs); \
+	contents &= ~(BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK \
+			<< shift); \
+	contents |= ((val) & BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK) \
+			<< shift; \
+	BDEV_WR(BCHP_NAND_CORR_STAT_THRESHOLD, contents); \
+	} while (0);
+
+#else /* CONTROLLER_VER < 60 */
+
+#define REG_ACC_CONTROL(cs) \
+	((cs) == 0 ? BCHP_NAND_ACC_CONTROL : \
+	 (BCHP_NAND_ACC_CONTROL_CS1 + (((cs) - 1) << 4)))
+
+#define REG_CONFIG(cs) \
+	((cs) == 0 ? BCHP_NAND_CONFIG : \
+	 (BCHP_NAND_CONFIG_CS1 + (((cs) - 1) << 4)))
+
+#define REG_TIMING_1(cs) \
+	((cs) == 0 ? BCHP_NAND_TIMING_1 : \
+	 (BCHP_NAND_TIMING_1_CS1 + (((cs) - 1) << 4)))
+#define REG_TIMING_2(cs) \
+	((cs) == 0 ? BCHP_NAND_TIMING_2 : \
+	 (BCHP_NAND_TIMING_2_CS1 + (((cs) - 1) << 4)))
+
+#define CORR_ERROR_COUNT (1)
+
+#define WR_CORR_THRESH(cs, val) do { \
+	BDEV_WR(BCHP_NAND_CORR_STAT_THRESHOLD, \
+		((val) & BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK) \
+		    << BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT); \
+	} while (0);
+
+#endif /* CONTROLLER_VER < 60 */
+
+#define WR_CONFIG(cs, field, val) do { \
+	u32 reg = REG_CONFIG(cs), contents = BDEV_RD(reg); \
+	contents &= ~(BCHP_NAND_CONFIG_CS1_##field##_MASK); \
+	contents |= (val) << BCHP_NAND_CONFIG_CS1_##field##_SHIFT; \
+	BDEV_WR(reg, contents); \
+	} while (0)
+
+#define WR_CONFIG_EXT(cs, field, val) do { \
+	u32 reg = REG_CONFIG_EXT(cs), contents = BDEV_RD(reg); \
+	contents &= ~(BCHP_NAND_CONFIG_EXT_CS1_##field##_MASK); \
+	contents |= (val) << BCHP_NAND_CONFIG_EXT_CS1_##field##_SHIFT; \
+	BDEV_WR(reg, contents); \
+	} while (0)
+
+#define RD_CONFIG(cs, field) \
+	((BDEV_RD(REG_CONFIG(cs)) & BCHP_NAND_CONFIG_CS1_##field##_MASK) \
+	 >> BCHP_NAND_CONFIG_CS1_##field##_SHIFT)
+
+#define RD_CONFIG_EXT(cs, field) \
+	((BDEV_RD(REG_CONFIG_EXT(cs)) & \
+	  BCHP_NAND_CONFIG_EXT_CS1_##field##_MASK) \
+	 >> BCHP_NAND_CONFIG_EXT_CS1_##field##_SHIFT)
+
+#define WR_ACC_CONTROL(cs, field, val) do { \
+	u32 reg = REG_ACC_CONTROL(cs), contents = BDEV_RD(reg); \
+	contents &= ~(BCHP_NAND_ACC_CONTROL_CS1_##field##_MASK); \
+	contents |= (val) << BCHP_NAND_ACC_CONTROL_CS1_##field##_SHIFT; \
+	BDEV_WR(reg, contents); \
+	} while (0)
+
+#define RD_ACC_CONTROL(cs, field) \
+	((BDEV_RD(REG_ACC_CONTROL(cs)) & \
+	BCHP_NAND_ACC_CONTROL_CS1_##field##_MASK) \
+		>> BCHP_NAND_ACC_CONTROL_CS1_##field##_SHIFT)
+
+#define HIF_ENABLED_IRQ(bit) \
+	(!BDEV_RD_F(HIF_INTR2_CPU_MASK_STATUS, bit##_INTR))
+
+#define FLASH_RDY	(NAND_STATUS_READY)
+#define NAND_CTRL_RDY	(BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK \
+			 | BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK)
+
+struct brcmstb_nand_controller {
+	struct nand_hw_control	controller;
+	volatile void __iomem	*flash_dma_base;
+	unsigned int		irq;
+	unsigned int		dma_irq;
+	bool			irq_cascaded;
+	int			cmd_pending;
+	bool			dma_pending;
+	struct completion	done;
+	struct completion	dma_done;
+
+	/* List of NAND hosts (one for each chip-select) */
+	struct list_head host_list;
+
+	struct brcm_nand_dma_desc *dma_desc;
+	dma_addr_t		dma_pa;
+
+	/* in-memory cache of the FLASH_CACHE, used only for some commands */
+	u32			flash_cache[FC_WORDS];
+
+	u32			nand_cs_nand_select;
+	u32			nand_cs_nand_xor;
+	u32			corr_stat_threshold;
+	u32			flash_dma_mode;
+};
+
+struct brcmstb_nand_cfg {
+	u64			device_size;
+	unsigned int		block_size;
+	unsigned int		page_size;
+	unsigned int		spare_area_size;
+	unsigned int		device_width;
+	unsigned int		col_adr_bytes;
+	unsigned int		blk_adr_bytes;
+	unsigned int		ful_adr_bytes;
+	unsigned int		sector_size_1k;
+	unsigned int		ecc_level;
+	/* use for low-power standby/resume only */
+	u32			acc_control;
+	u32			config;
+	u32			config_ext;
+	u32			timing_1;
+	u32			timing_2;
+};
+
+struct brcmstb_nand_host {
+	struct list_head	node;
+	struct device_node	*of_node;
+
+	struct nand_chip	chip;
+	struct mtd_info		mtd;
+	struct platform_device	*pdev;
+	int			cs;
+
+	unsigned int		last_cmd;
+	unsigned int		last_byte;
+	u64			last_addr;
+	struct brcmstb_nand_cfg	hwcfg;
+	struct brcmstb_nand_controller *ctrl;
+};
+
+static struct nand_ecclayout brcmstb_nand_dummy_layout = {
+	.eccbytes		= 16,
+	.eccpos			= { 0, 1, 2, 3, 4, 5, 6, 7,
+				    8, 9, 10, 11, 12, 13, 14, 15 },
+};
+
+/***********************************************************************
+ * Flash DMA
+ ***********************************************************************/
+
+enum flash_dma_reg {
+	FLASH_DMA_REVISION		= 0x00,
+	FLASH_DMA_FIRST_DESC		= 0x04,
+	FLASH_DMA_FIRST_DESC_EXT	= 0x08,
+	FLASH_DMA_CTRL			= 0x0c,
+	FLASH_DMA_MODE			= 0x10,
+	FLASH_DMA_STATUS		= 0x14,
+	FLASH_DMA_INTERRUPT_DESC	= 0x18,
+	FLASH_DMA_INTERRUPT_DESC_EXT	= 0x1c,
+	FLASH_DMA_ERROR_STATUS		= 0x20,
+	FLASH_DMA_CURRENT_DESC		= 0x24,
+	FLASH_DMA_CURRENT_DESC_EXT	= 0x28,
+};
+
+static inline bool has_flash_dma(struct brcmstb_nand_controller *ctrl)
+{
+	return ctrl->flash_dma_base;
+}
+
+static inline bool flash_dma_buf_ok(const void *buf)
+{
+	return buf && !is_vmalloc_addr(buf) &&
+		likely(IS_ALIGNED((uintptr_t)buf, 4));
+}
+
+static inline void flash_dma_writel(struct brcmstb_nand_controller *ctrl, u8 offs,
+		u32 val)
+{
+	__raw_writel(val, ctrl->flash_dma_base + offs);
+}
+
+static inline u32 flash_dma_readl(struct brcmstb_nand_controller *ctrl, u8 offs)
+{
+	return __raw_readl(ctrl->flash_dma_base + offs);
+}
+
+static inline bool flash_dma_irq_done(struct brcmstb_nand_controller *ctrl)
+{
+#ifdef BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK
+	if (HIF_TEST_IRQ(FLASH_DMA_DONE)) {
+		HIF_ACK_IRQ(FLASH_DMA_DONE);
+		return true;
+	}
+#endif
+	return false;
+}
+
+static inline void flash_dma_irq_enable(struct brcmstb_nand_controller *ctrl)
+{
+#ifdef BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK
+	HIF_ACK_IRQ(FLASH_DMA_DONE);
+	HIF_ENABLE_IRQ(FLASH_DMA_DONE);
+#endif
+}
+
+static inline void flash_dma_irq_disable(struct brcmstb_nand_controller *ctrl)
+{
+#ifdef BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK
+	HIF_DISABLE_IRQ(FLASH_DMA_DONE);
+#endif
+}
+
+static inline bool flash_dma_irq_enabled(struct brcmstb_nand_controller *ctrl)
+{
+#ifdef BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK
+	return HIF_ENABLED_IRQ(FLASH_DMA_DONE);
+#else
+	return false;
+#endif
+}
+
+/*
+ * Get the DMA physical address for the n'th DMA descriptor
+ */
+static inline dma_addr_t flash_dma_get_desc_pa(
+		struct brcmstb_nand_controller *ctrl, int idx)
+{
+	return ctrl->dma_pa + (idx * sizeof(struct brcm_nand_dma_desc));
+}
+
+/* Low-level operation types: command, address, write, or read */
+enum brcmstb_nand_llop_type {
+	LL_OP_CMD,
+	LL_OP_ADDR,
+	LL_OP_WR,
+	LL_OP_RD,
+};
+
+/***********************************************************************
+ * Internal support functions
+ ***********************************************************************/
+
+static inline bool is_hamming_ecc(struct brcmstb_nand_cfg *cfg)
+{
+	return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
+		cfg->ecc_level == 15;
+}
+
+/*
+ * Returns a nand_ecclayout strucutre for the given layout/configuration.
+ * Returns NULL on failure.
+ */
+static struct nand_ecclayout *brcmstb_nand_create_layout(int ecc_level,
+		struct brcmstb_nand_host *host)
+{
+	struct brcmstb_nand_cfg *cfg = &host->hwcfg;
+	int i, j;
+	struct nand_ecclayout *layout;
+	int req;
+	int sectors;
+	int sas;
+	int idx1, idx2;
+
+	layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
+	if (!layout)
+		return NULL;
+
+	sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+	sas = cfg->spare_area_size << cfg->sector_size_1k;
+
+	/* Hamming */
+	if (is_hamming_ecc(cfg)) {
+		for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+			/* First sector of each page may have BBI */
+			if (i == 0) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				/* Small-page NAND use byte 6 for BBI */
+				if (cfg->page_size == 512)
+					layout->oobfree[idx2].offset--;
+				layout->oobfree[idx2].length = 5;
+			} else {
+				layout->oobfree[idx2].offset = i * sas;
+				layout->oobfree[idx2].length = 6;
+			}
+			idx2++;
+			layout->eccpos[idx1++] = i * sas + 6;
+			layout->eccpos[idx1++] = i * sas + 7;
+			layout->eccpos[idx1++] = i * sas + 8;
+			layout->oobfree[idx2].offset = i * sas + 9;
+			layout->oobfree[idx2].length = 7;
+			idx2++;
+			/* Leave zero-terminated entry for OOBFREE */
+			if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				    idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+				break;
+		}
+		goto out;
+	}
+
+	/*
+	 * CONTROLLER_VERSION:
+	 *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
+	 *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)  [see SWLINUX-2038]
+	 * But we will just be conservative.
+	 */
+	req = (ecc_level * 14 + 7) / 8;
+	if (req >= sas) {
+		pr_info("%s: ECC too large for OOB, using dummy layout\n",
+			__func__);
+		memcpy(layout, &brcmstb_nand_dummy_layout, sizeof(*layout));
+		return layout;
+	}
+
+	DBG("OOBLAYOUT: sas=%d  req=%d  sectors=%d\n", sas, req, sectors);
+
+	layout->eccbytes = req * sectors;
+	for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+		for (j = sas - req; j < sas && idx1 <
+				MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
+			layout->eccpos[idx1] = i * sas + j;
+
+		/* First sector of each page may have BBI */
+		if (i == 0) {
+			if (cfg->page_size == 512 && (sas - req >= 6)) {
+				/* Small-page NAND use byte 6 for BBI */
+				layout->oobfree[idx2].offset = 0;
+				layout->oobfree[idx2].length = 5;
+				idx2++;
+				if (sas - req > 6) {
+					layout->oobfree[idx2].offset = 6;
+					layout->oobfree[idx2].length =
+						sas - req - 6;
+					idx2++;
+				}
+			} else if (sas > req + 1) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				layout->oobfree[idx2].length = sas - req - 1;
+				idx2++;
+			}
+		} else if (sas > req) {
+			layout->oobfree[idx2].offset = i * sas;
+			layout->oobfree[idx2].length = sas - req;
+			idx2++;
+		}
+		/* Leave zero-terminated entry for OOBFREE */
+		if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+			break;
+	}
+out:
+	/* Sum available OOB */
+	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
+		layout->oobavail += layout->oobfree[i].length;
+	return layout;
+}
+
+static struct nand_ecclayout *brcmstb_choose_ecc_layout(
+		struct brcmstb_nand_host *host)
+{
+	struct nand_ecclayout *layout;
+	struct brcmstb_nand_cfg *p = &host->hwcfg;
+	unsigned int ecc_level = p->ecc_level;
+
+	if (p->sector_size_1k)
+		ecc_level <<= 1;
+
+	layout = brcmstb_nand_create_layout(ecc_level, host);
+	if (!layout) {
+		dev_err(&host->pdev->dev,
+				"no proper ecc_layout for this NAND cfg\n");
+		return NULL;
+	}
+
+	return layout;
+}
+
+static void brcmstb_nand_wp_set(struct mtd_info *mtd, int wp)
+{
+#ifdef BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK
+	if (wp_on == 1) {
+		static int old_wp = -1;
+		if (old_wp != wp) {
+			DBG("%s: WP %s\n", __func__, wp ? "on" : "off");
+			old_wp = wp;
+		}
+		BDEV_WR_F_RB(NAND_CS_NAND_SELECT, NAND_WP, wp);
+	}
+#endif
+
+}
+
+static int brcmstb_nand_ctrl_busy_poll(struct mtd_info *mtd, u32 mask)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+	if (!mask)
+		mask = BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK;
+
+	while ((BDEV_RD(BCHP_NAND_INTFC_STATUS) & mask) != mask) {
+		if (time_after(jiffies, timeout)) {
+			dev_warn(&host->pdev->dev, "timeout on ctrl_ready\n");
+			return -ETIMEDOUT;
+		}
+		cpu_relax();
+	}
+	return 0;
+}
+
+static void brcmstb_nand_wp(struct mtd_info *mtd, int wp_en)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	uint8_t is_wp, sts_reg;
+
+	brcmstb_nand_ctrl_busy_poll(mtd, NAND_CTRL_RDY | FLASH_RDY);
+	if (wp_on == 1)
+		brcmstb_nand_wp_set(mtd, wp_en);
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+	/* again make sure the flash is also ready */
+	brcmstb_nand_ctrl_busy_poll(mtd, NAND_CTRL_RDY | FLASH_RDY);
+
+	/*
+	 * we always return "not write protected" status due
+	 * to SWLINUX-1818 lets read the true status before
+	 * proceeding
+	 */
+	sts_reg =  BDEV_RD(BCHP_NAND_INTFC_STATUS) & 0xff;
+	/* NAND_STATUS_WP 0x80 = not protected, 0x00 = protected*/
+	is_wp = (sts_reg & NAND_STATUS_WP) ? 0 : 1;
+
+	if ((wp_on == 1) && (is_wp != wp_en)) {
+		dev_err_ratelimited(&host->pdev->dev,
+				    "#WP %s sts:0x%x expected %s\n",
+				    is_wp ? "On" : "Off", sts_reg & 0xff,
+				    wp_en ? "On" : "Off");
+	}
+}
+
+/* Helper functions for reading and writing OOB registers */
+static inline unsigned char oob_reg_read(int offs)
+{
+	if (offs >= MAX_CONTROLLER_OOB)
+		return 0x77;
+
+	if (offs < 16)
+		return BDEV_RD(BCHP_NAND_SPARE_AREA_READ_OFS_0 + (offs & ~0x03))
+			>> (24 - ((offs & 0x03) << 3));
+
+	offs -= 16;
+
+	return BDEV_RD(OFS_10_RD + (offs & ~0x03))
+		>> (24 - ((offs & 0x03) << 3));
+}
+
+static inline void oob_reg_write(int offs, unsigned long data)
+{
+	if (offs >= MAX_CONTROLLER_OOB)
+		return;
+
+	if (offs < 16) {
+		BDEV_WR(BCHP_NAND_SPARE_AREA_WRITE_OFS_0 + (offs & ~0x03),
+				data);
+		return;
+	}
+
+	offs -= 16;
+
+	BDEV_WR(OFS_10_WR + (offs & ~0x03), data);
+}
+
+/*
+ * read_oob_from_regs - read data from OOB registers
+ * @i: sub-page sector index
+ * @oob: buffer to read to
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int read_oob_from_regs(int i, u8 *oob, int sas, int sector_1k)
+{
+	int tbytes = sas << sector_1k;
+	int j;
+
+	/* Adjust OOB values for 1K sector size */
+	if (sector_1k && (i & 0x01))
+		tbytes = max(0, tbytes - MAX_CONTROLLER_OOB);
+	tbytes = min(tbytes, MAX_CONTROLLER_OOB);
+
+	for (j = 0; j < tbytes; j++)
+		oob[j] = oob_reg_read(j);
+	return tbytes;
+}
+
+/*
+ * write_oob_to_regs - write data to OOB registers
+ * @i: sub-page sector index
+ * @oob: buffer to write from
+ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
+ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
+ */
+static int write_oob_to_regs(int i, const u8 *oob, int sas, int sector_1k)
+{
+	int tbytes = sas << sector_1k;
+	int j;
+
+	/* Adjust OOB values for 1K sector size */
+	if (sector_1k && (i & 0x01))
+		tbytes = max(0, tbytes - MAX_CONTROLLER_OOB);
+	tbytes = min(tbytes, MAX_CONTROLLER_OOB);
+
+	for (j = 0; j < tbytes; j += 4)
+		oob_reg_write(j,
+				(oob[j + 0] << 24) |
+				(oob[j + 1] << 16) |
+				(oob[j + 2] <<  8) |
+				(oob[j + 3] <<  0));
+	return tbytes;
+}
+
+static irqreturn_t brcmstb_nand_ctlrdy_irq(int irq, void *data)
+{
+	struct brcmstb_nand_controller *ctrl = data;
+
+	/* Discard all NAND_CTLRDY interrupts during DMA */
+	if (ctrl->dma_pending)
+		return IRQ_HANDLED;
+
+	complete(&ctrl->done);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t brcmstb_nand_dma_irq(int irq, void *data)
+{
+	struct brcmstb_nand_controller *ctrl = data;
+
+	complete(&ctrl->dma_done);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * High-level HIF interrupt handler; used only if we aren't using a
+ * properly-cascaded L2 interrupt controller driver
+ */
+static irqreturn_t brcmstb_nand_irq(int irq, void *data)
+{
+	struct brcmstb_nand_controller *ctrl = data;
+
+	if (has_flash_dma(ctrl) && flash_dma_irq_done(ctrl))
+		return brcmstb_nand_dma_irq(irq, data);
+
+	if (HIF_TEST_IRQ(NAND_CTLRDY)) {
+		HIF_ACK_IRQ(NAND_CTLRDY);
+		return brcmstb_nand_ctlrdy_irq(irq, data);
+	}
+	return IRQ_NONE;
+}
+
+static void brcmstb_nand_send_cmd(struct brcmstb_nand_host *host, int cmd)
+{
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+
+	DBG("%s: native cmd %d addr_lo 0x%lx\n", __func__, cmd,
+		BDEV_RD(BCHP_NAND_CMD_ADDRESS));
+	BUG_ON(ctrl->cmd_pending != 0);
+	ctrl->cmd_pending = cmd;
+	mb();
+	BDEV_WR(BCHP_NAND_CMD_START, cmd << BCHP_NAND_CMD_START_OPCODE_SHIFT);
+}
+
+/***********************************************************************
+ * NAND MTD API: read/program/erase
+ ***********************************************************************/
+
+static void brcmstb_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
+	unsigned int ctrl)
+{
+	/* intentionally left blank */
+}
+
+static int brcmstb_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	unsigned long timeo = msecs_to_jiffies(100);
+
+	DBG("%s: native cmd %d\n", __func__, ctrl->cmd_pending);
+	if (ctrl->cmd_pending &&
+			wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
+		dev_err_ratelimited(&host->pdev->dev,
+			"timeout waiting for command %u (%ld)\n",
+			host->last_cmd, BDEV_RD(BCHP_NAND_CMD_START) >>
+			BCHP_NAND_CMD_START_OPCODE_SHIFT);
+		dev_err_ratelimited(&host->pdev->dev,
+			"irq status %08lx, intfc status %08lx\n",
+			BDEV_RD(BCHP_HIF_INTR2_CPU_STATUS),
+			BDEV_RD(BCHP_NAND_INTFC_STATUS));
+	}
+	ctrl->cmd_pending = 0;
+	return BDEV_RD_F(NAND_INTFC_STATUS, FLASH_STATUS);
+}
+
+static int brcmstb_nand_low_level_op(struct brcmstb_nand_host *host,
+		enum brcmstb_nand_llop_type type, u32 data, bool last_op)
+{
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = &host->chip;
+	u32 tmp;
+
+	tmp = data & BCHP_NAND_LL_OP_DATA_MASK;
+	switch (type) {
+	case LL_OP_CMD:
+		tmp |= BCHP_NAND_LL_OP_CLE_MASK;
+		tmp |= BCHP_NAND_LL_OP_WE_MASK;
+		break;
+	case LL_OP_ADDR:
+		tmp |= BCHP_NAND_LL_OP_ALE_MASK;
+		tmp |= BCHP_NAND_LL_OP_WE_MASK;
+		break;
+	case LL_OP_WR:
+		tmp |= BCHP_NAND_LL_OP_WE_MASK;
+		break;
+	case LL_OP_RD:
+		tmp |= BCHP_NAND_LL_OP_RE_MASK;
+		break;
+	}
+	if (last_op)
+		tmp |= BCHP_NAND_LL_OP_RETURN_IDLE_MASK;
+
+	DBG("%s: cmd 0x%lx\n", __func__, (unsigned long)tmp);
+
+	BDEV_WR_RB(BCHP_NAND_LL_OP, tmp);
+
+	brcmstb_nand_send_cmd(host, CMD_LOW_LEVEL_OP);
+	return brcmstb_nand_waitfunc(mtd, chip);
+}
+
+static void brcmstb_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
+	int column, int page_addr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	u64 addr = (u64)page_addr << chip->page_shift;
+	int native_cmd = 0;
+
+	if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
+			command == NAND_CMD_RNDOUT)
+		addr = (u64)column;
+	/* Avoid propagating a negative, don't-care address */
+	else if (page_addr < 0)
+		addr = 0;
+
+	DBG("%s: cmd 0x%x addr 0x%llx\n", __func__, command,
+		(unsigned long long)addr);
+	host->last_cmd = command;
+	host->last_byte = 0;
+	host->last_addr = addr;
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		native_cmd = CMD_FLASH_RESET;
+		break;
+	case NAND_CMD_STATUS:
+		native_cmd = CMD_STATUS_READ;
+		break;
+	case NAND_CMD_READID:
+		native_cmd = CMD_DEVICE_ID_READ;
+		break;
+	case NAND_CMD_READOOB:
+		native_cmd = CMD_SPARE_AREA_READ;
+		break;
+	case NAND_CMD_ERASE1:
+		native_cmd = CMD_BLOCK_ERASE;
+		brcmstb_nand_wp(mtd, 0);
+		break;
+#if CONTROLLER_VER >= 40
+	case NAND_CMD_PARAM:
+		native_cmd = CMD_PARAMETER_READ;
+		break;
+	case NAND_CMD_SET_FEATURES:
+	case NAND_CMD_GET_FEATURES:
+		brcmstb_nand_low_level_op(host, LL_OP_CMD, command, false);
+		brcmstb_nand_low_level_op(host, LL_OP_ADDR, column, false);
+		break;
+	case NAND_CMD_RNDOUT:
+		native_cmd = CMD_PARAMETER_CHANGE_COL;
+		addr &= ~((u64)(FC_BYTES - 1));
+		/*
+		 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
+		 * NB: hwcfg.sector_size_1k may not be initialized yet
+		 */
+		if (RD_ACC_CONTROL(host->cs, SECTOR_SIZE_1K)) {
+			host->hwcfg.sector_size_1k =
+				RD_ACC_CONTROL(host->cs, SECTOR_SIZE_1K);
+			WR_ACC_CONTROL(host->cs, SECTOR_SIZE_1K, 0);
+		}
+		break;
+#endif
+	}
+
+	if (!native_cmd)
+		return;
+
+	BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+		(host->cs << 16) | ((addr >> 32) & 0xffff));
+	BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+
+	brcmstb_nand_send_cmd(host, native_cmd);
+	brcmstb_nand_waitfunc(mtd, chip);
+
+#if CONTROLLER_VER >= 40
+	if (native_cmd == CMD_PARAMETER_READ ||
+			native_cmd == CMD_PARAMETER_CHANGE_COL) {
+		int i;
+		/*
+		 * Must cache the FLASH_CACHE now, since changes in
+		 * SECTOR_SIZE_1K may invalidate it
+		 */
+		for (i = 0; i < FC_WORDS; i++)
+			ctrl->flash_cache[i] = le32_to_cpu(BDEV_RD(FC(i)));
+		/* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
+		if (host->hwcfg.sector_size_1k)
+			WR_ACC_CONTROL(host->cs, SECTOR_SIZE_1K,
+					host->hwcfg.sector_size_1k);
+	}
+#endif
+
+	/* Re-enable protection is necessary only after erase */
+	if (command == NAND_CMD_ERASE1)
+		brcmstb_nand_wp(mtd, 1);
+}
+
+static uint8_t brcmstb_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	uint8_t ret = 0;
+	int addr, offs;
+
+	switch (host->last_cmd) {
+	case NAND_CMD_READID:
+		if (host->last_byte < 4)
+			ret = BDEV_RD(BCHP_NAND_FLASH_DEVICE_ID) >>
+				(24 - (host->last_byte << 3));
+		else if (host->last_byte < 8)
+			ret = BDEV_RD(BCHP_NAND_FLASH_DEVICE_ID_EXT) >>
+				(56 - (host->last_byte << 3));
+		break;
+
+	case NAND_CMD_READOOB:
+		ret = oob_reg_read(host->last_byte);
+		break;
+
+	case NAND_CMD_STATUS:
+		ret = BDEV_RD(BCHP_NAND_INTFC_STATUS) & 0xff;
+		if (wp_on) /* SWLINUX-1818: hide WP status from MTD */
+			ret |= NAND_STATUS_WP;
+		break;
+
+#if CONTROLLER_VER >= 40
+	case NAND_CMD_PARAM:
+	case NAND_CMD_RNDOUT:
+		addr = host->last_addr + host->last_byte;
+		offs = addr & (FC_BYTES - 1);
+
+		/* At FC_BYTES boundary, switch to next column */
+		if (host->last_byte > 0 && offs == 0)
+			chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
+
+		ret = ctrl->flash_cache[offs >> 2] >>
+					(24 - ((offs & 0x03) << 3));
+		break;
+	case NAND_CMD_GET_FEATURES:
+		if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
+			ret = 0;
+		} else {
+			bool last = host->last_byte ==
+				ONFI_SUBFEATURE_PARAM_LEN - 1;
+			brcmstb_nand_low_level_op(host, LL_OP_RD, 0, last);
+			ret = BDEV_RD(BCHP_NAND_LL_RDDATA) & 0xff;
+		}
+#endif
+	}
+
+	DBG("%s: byte = 0x%02x\n", __func__, ret);
+	host->last_byte++;
+
+	return ret;
+}
+
+static void brcmstb_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++, buf++)
+		*buf = brcmstb_nand_read_byte(mtd);
+}
+
+static void brcmstb_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	struct brcmstb_nand_host *host = chip->priv;
+
+	switch (host->last_cmd) {
+	case NAND_CMD_SET_FEATURES:
+		for (i = 0; i < len; i++)
+			brcmstb_nand_low_level_op(host, LL_OP_WR, buf[i], (i + 1) == len);
+		break;
+	default:
+		BUG();
+		break;
+	}
+}
+
+/**
+ * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
+ * following ahead of time:
+ *  - Is this descriptor the beginning or end of a linked list?
+ *  - What is the (DMA) address of the next descriptor in the linked list?
+ */
+static int brcmstb_nand_fill_dma_desc(struct brcmstb_nand_host *host,
+		struct brcm_nand_dma_desc *desc, u64 addr, dma_addr_t buf,
+		u32 len, u8 dma_cmd, bool begin, bool end, dma_addr_t next_desc)
+{
+	memset(desc, 0, sizeof(*desc));
+	/* Descriptors are written in native byte order (wordwise) */
+	desc->next_desc = next_desc & 0xffffffff;
+	desc->next_desc_ext = ((u64)next_desc) >> 32;
+	desc->cmd_irq = (dma_cmd << 24) |
+		(end ? (0x03 << 8) : 0) | /* IRQ | STOP */
+		(!!begin) | ((!!end) << 1); /* head, tail */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	desc->cmd_irq |= 0x01 << 12;
+#endif
+	desc->dram_addr = buf & 0xffffffff;
+	desc->dram_addr_ext = (u64)buf >> 32;
+	desc->tfr_len = len;
+	desc->total_len = len;
+	desc->flash_addr = addr & 0xffffffff;
+	desc->flash_addr_ext = addr >> 32;
+	desc->cs = host->cs;
+	desc->status_valid = 0x01;
+	return 0;
+}
+
+/**
+ * Kick the FLASH_DMA engine, with a given DMA descriptor
+ */
+static void brcmstb_nand_dma_run(struct brcmstb_nand_host *host, dma_addr_t desc)
+{
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	unsigned long timeo = msecs_to_jiffies(100);
+
+	flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, desc & 0xffffffff);
+	(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
+	flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, (u64)desc >> 32);
+	(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
+
+	/* Start FLASH_DMA engine */
+	ctrl->dma_pending = true;
+	mb();
+	flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
+
+	if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
+		dev_err(&host->pdev->dev,
+				"timeout waiting for DMA; status %#x, error status %#x\n",
+				flash_dma_readl(ctrl, FLASH_DMA_STATUS),
+				flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
+	}
+	ctrl->dma_pending = false;
+	flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
+}
+
+static int brcmstb_nand_dma_trans(struct brcmstb_nand_host *host, u64 addr,
+	u32 *buf, u32 len, u8 dma_cmd)
+{
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	dma_addr_t buf_pa;
+	int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	buf_pa = dma_map_single(&host->pdev->dev, buf, len, dir);
+
+	brcmstb_nand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
+				   dma_cmd, true, true, 0);
+
+	brcmstb_nand_dma_run(host, ctrl->dma_pa);
+
+	dma_unmap_single(&host->pdev->dev, buf_pa, len, dir);
+
+	if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
+		return -EBADMSG;
+	else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
+		return -EUCLEAN;
+
+	return 0;
+}
+
+/*
+ * Assumes proper CS is already set
+ */
+static int brcmstb_nand_read_by_pio(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, unsigned int trans,
+	u32 *buf, u8 *oob, u64 *err_addr)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	int i, j, ret = 0;
+
+	/* Clear error addresses */
+	BDEV_WR_RB(BCHP_NAND_ECC_UNC_ADDR, 0);
+	BDEV_WR_RB(BCHP_NAND_ECC_CORR_ADDR, 0);
+
+	BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+			(host->cs << 16) | ((addr >> 32) & 0xffff));
+
+	for (i = 0; i < trans; i++, addr += FC_BYTES) {
+		BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+		/* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
+		brcmstb_nand_send_cmd(host, CMD_PAGE_READ);
+		brcmstb_nand_waitfunc(mtd, chip);
+
+		if (likely(buf))
+			for (j = 0; j < FC_WORDS; j++, buf++)
+				*buf = le32_to_cpu(BDEV_RD(FC(j)));
+
+		if (oob)
+			oob += read_oob_from_regs(i, oob, mtd->oobsize / trans, host->hwcfg.sector_size_1k);
+
+		if (!ret) {
+			*err_addr = BDEV_RD(BCHP_NAND_ECC_UNC_ADDR) |
+				((u64)(BDEV_RD(BCHP_NAND_ECC_UNC_EXT_ADDR) &
+					0xffff) << 32);
+			if (*err_addr)
+				ret = -EBADMSG;
+		}
+
+		if (!ret) {
+			*err_addr = BDEV_RD(BCHP_NAND_ECC_CORR_ADDR) |
+				((u64)(BDEV_RD(BCHP_NAND_ECC_CORR_EXT_ADDR) &
+					0xffff) << 32);
+			if (*err_addr)
+				ret = -EUCLEAN;
+		}
+	}
+
+	return ret;
+}
+
+/*
+ * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
+ * error
+ *
+ * Because the HW ECC signals an ECC error if an erase paged has even a single
+ * bitflip, we must check each ECC error to see if it is actually an erased
+ * page with bitflips, not a truly corrupted page.
+ *
+ * On a real error, return a negative error code (-EBADMSG for ECC error), and
+ * buf will contain raw data.
+ * Otherwise, fill buf with 0xff and return the maximum number of
+ * bitflips-per-ECC-sector to the caller.
+ *
+ */
+static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
+		  struct nand_chip *chip, void *buf, u64 addr)
+{
+	int i, sas, oob_nbits, data_nbits;
+	void *oob = chip->oob_poi;
+	unsigned int max_bitflips = 0;
+	int page = addr >> chip->page_shift;
+	int ret;
+
+	if (!buf) {
+		buf = chip->buffers->databuf;
+		/* Invalidate page cache */
+		chip->pagebuf = -1;
+	}
+
+	sas = mtd->oobsize / chip->ecc.steps;
+	oob_nbits = sas << 3;
+	data_nbits = chip->ecc.size << 3;
+
+	/* read without ecc for verification */
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+	ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
+		unsigned int bitflips = 0;
+
+		bitflips += oob_nbits - bitmap_weight(oob, oob_nbits);
+		bitflips += data_nbits - bitmap_weight(buf, data_nbits);
+
+		buf += chip->ecc.size;
+		addr += chip->ecc.size;
+
+		/* Too many bitflips */
+		if (bitflips > chip->ecc.strength)
+			return -EBADMSG;
+
+		max_bitflips = max(max_bitflips, bitflips);
+	}
+
+	return max_bitflips;
+}
+
+static int brcmstb_nand_read(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, unsigned int trans,
+	u32 *buf, u8 *oob)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	u64 err_addr = 0;
+	int err;
+	bool retry = true;
+
+	DBG("%s %llx -> %p\n", __func__, (unsigned long long)addr, buf);
+
+try_dmaread:
+#if CONTROLLER_VER >= 60
+	BDEV_WR_RB(BCHP_NAND_UNCORR_ERROR_COUNT, 0);
+#endif
+	if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
+		err = brcmstb_nand_dma_trans(host, addr, buf, trans * FC_BYTES,
+					     CMD_PAGE_READ);
+		if (err) {
+			if (mtd_is_bitflip_or_eccerr(err))
+				err_addr = addr;
+			else
+				return -EIO;
+		}
+	} else {
+		if (oob)
+			memset(oob, 0x99, mtd->oobsize);
+
+		err = brcmstb_nand_read_by_pio(mtd, chip, addr, trans, buf,
+					       oob, &err_addr);
+	}
+
+	if (mtd_is_eccerr(err)) {
+		int ret = 0;
+		/*
+		 * CRNAND-32 : if we are doing a DMA read after a prior
+		 * PIO read that reported uncorrectable error, the DMA
+		 * engine captures this error in the first DMA read
+		 * after this PIO read, cleared only on subsequent DMA
+		 * read, so just retry once to clear a possible false
+		 * error reported for current DMA read
+		 */
+		if (retry) {
+			retry = false;
+			goto try_dmaread;
+		}
+		ret = brcmstb_nand_verify_erased_page(mtd, chip, buf, addr);
+		if (ret < 0) {
+			dev_dbg(&host->pdev->dev,
+					"uncorrectable error at 0x%llx\n",
+					(unsigned long long)err_addr);
+			mtd->ecc_stats.failed++;
+			/* NAND layer expects zero on ECC errors */
+			return 0;
+		} else {
+			if (buf)
+				memset(buf, 0xff, FC_BYTES * trans);
+			if (oob)
+				memset(oob, 0xff, mtd->oobsize);
+
+			dev_info(&host->pdev->dev,
+					"corrected %d bitflips in blank page at 0x%llx\n",
+					ret, (unsigned long long)addr);
+			return ret;
+		}
+	}
+
+	if (mtd_is_bitflip(err)) {
+		unsigned int corrected = CORR_ERROR_COUNT;
+		dev_dbg(&host->pdev->dev, "corrected error at 0x%llx\n",
+			(unsigned long long)err_addr);
+		mtd->ecc_stats.corrected += corrected;
+		/* Always exceed the software-imposed threshold */
+		return max(mtd->bitflip_threshold, corrected);
+	}
+
+	return 0;
+}
+
+static int brcmstb_nand_read_page(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	return brcmstb_nand_read(mtd, chip, host->last_addr,
+			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+}
+
+static int brcmstb_nand_read_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+	int ret;
+
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, 0);
+	ret = brcmstb_nand_read(mtd, chip, host->last_addr,
+			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, host->hwcfg.ecc_level);
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+	return ret;
+}
+
+static int brcmstb_nand_read_oob(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	return brcmstb_nand_read(mtd, chip, (u64)page << chip->page_shift,
+			mtd->writesize >> FC_SHIFT,
+			NULL, (u8 *)chip->oob_poi);
+}
+
+static int brcmstb_nand_read_oob_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, 0);
+	brcmstb_nand_read(mtd, chip, (u64)page << chip->page_shift,
+		mtd->writesize >> FC_SHIFT,
+		NULL, (u8 *)chip->oob_poi);
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, host->hwcfg.ecc_level);
+	WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+	return 0;
+}
+
+static int brcmstb_nand_read_subpage(struct mtd_info *mtd,
+	struct nand_chip *chip, uint32_t data_offs, uint32_t readlen,
+	uint8_t *bufpoi)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+
+	return brcmstb_nand_read(mtd, chip, host->last_addr + data_offs,
+			readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
+}
+
+static int brcmstb_nand_write(struct mtd_info *mtd,
+	struct nand_chip *chip, u64 addr, const u32 *buf, u8 *oob)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
+	int status, ret = 0;
+
+	DBG("%s %llx <- %p\n", __func__, (unsigned long long)addr, buf);
+
+	if (unlikely((u32)buf & 0x03)) {
+		dev_warn(&host->pdev->dev, "unaligned buffer: %p\n", buf);
+		buf = (u32 *)((u32)buf & ~0x03);
+	}
+
+	brcmstb_nand_wp(mtd, 0);
+
+	for (i = 0; i < MAX_CONTROLLER_OOB; i += 4)
+		oob_reg_write(i, 0xffffffff);
+
+	if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
+		if (brcmstb_nand_dma_trans(host, addr, (u32 *)buf,
+					mtd->writesize, CMD_PROGRAM_PAGE))
+			ret = -EIO;
+		goto out;
+	}
+
+	BDEV_WR_RB(BCHP_NAND_CMD_EXT_ADDRESS,
+		(host->cs << 16) | ((addr >> 32) & 0xffff));
+
+	for (i = 0; i < trans; i++, addr += FC_BYTES) {
+		/* full address MUST be set before populating FC */
+		BDEV_WR_RB(BCHP_NAND_CMD_ADDRESS, addr & 0xffffffff);
+
+		if (buf)
+			for (j = 0; j < FC_WORDS; j++, buf++)
+				BDEV_WR(FC(j), cpu_to_le32(*buf));
+		else if (oob)
+			for (j = 0; j < FC_WORDS; j++)
+				BDEV_WR(FC(j), 0xffffffff);
+
+		if (oob) {
+			oob += write_oob_to_regs(i, oob, mtd->oobsize / trans,
+					host->hwcfg.sector_size_1k);
+		}
+
+		/* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
+		brcmstb_nand_send_cmd(host, CMD_PROGRAM_PAGE);
+		status = brcmstb_nand_waitfunc(mtd, chip);
+
+		if (status & NAND_STATUS_FAIL) {
+			dev_info(&host->pdev->dev, "program failed at %llx\n",
+				(unsigned long long)addr);
+			ret = -EIO;
+			goto out;
+		}
+	}
+out:
+	brcmstb_nand_wp(mtd, 1);
+	return ret;
+}
+
+static int brcmstb_nand_write_page(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	brcmstb_nand_write(mtd, chip, host->last_addr, (u32 *)buf, oob);
+	return 0;
+}
+
+static int brcmstb_nand_write_page_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 0);
+	brcmstb_nand_write(mtd, chip, host->last_addr, (u32 *)buf, oob);
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+	return 0;
+}
+
+static int brcmstb_nand_write_oob(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	return brcmstb_nand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+		(u8 *)chip->oob_poi);
+}
+
+static int brcmstb_nand_write_oob_raw(struct mtd_info *mtd,
+	struct nand_chip *chip, int page)
+{
+	struct brcmstb_nand_host *host = chip->priv;
+	int ret;
+
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 0);
+	ret = brcmstb_nand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+		(u8 *)chip->oob_poi);
+	WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+
+	return ret;
+}
+
+/***********************************************************************
+ * Per-CS setup (1 NAND device)
+ ***********************************************************************/
+
+#if CONTROLLER_VER >= 71
+/* use powers of two */
+#elif CONTROLLER_VER >= 60
+static const unsigned int block_sizes[] = { 8, 16, 128, 256, 512, 1024, 2048 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192 };
+#elif CONTROLLER_VER >= 40
+static const unsigned int block_sizes[] = { 16, 128, 8, 512, 256, 1024, 2048 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192 };
+#else
+static const unsigned int block_sizes[] = { 16, 128, 8, 512, 256 };
+static const unsigned int page_sizes[] = { 512, 2048, 4096 };
+#endif
+
+static void brcmstb_nand_set_cfg(struct brcmstb_nand_host *host,
+	struct brcmstb_nand_cfg *cfg)
+{
+#if CONTROLLER_VER >= 71
+	if (cfg->block_size < 8192 || cfg->block_size > 8192*1024)
+		dev_warn(&host->pdev->dev, "invalid block size %u\n",
+			cfg->block_size);
+	else
+		WR_CONFIG_EXT(host->cs, BLOCK_SIZE,
+			      ffs(cfg->block_size) - ffs(8192));
+
+	if (cfg->page_size < 512 || cfg->page_size > 16384)
+		dev_warn(&host->pdev->dev, "invalid page size %u\n",
+			cfg->page_size);
+	else
+		WR_CONFIG_EXT(host->cs, PAGE_SIZE,
+			      ffs(cfg->page_size) - ffs(512));
+#else
+	int i, found;
+
+	for (i = 0, found = 0; i < ARRAY_SIZE(block_sizes); i++)
+		if ((block_sizes[i] << 10) == cfg->block_size) {
+			WR_CONFIG(host->cs, BLOCK_SIZE, i);
+			found = 1;
+		}
+	if (!found)
+		dev_warn(&host->pdev->dev, "invalid block size %u\n",
+			cfg->block_size);
+
+	for (i = 0, found = 0; i < ARRAY_SIZE(page_sizes); i++)
+		if (page_sizes[i] == cfg->page_size) {
+			WR_CONFIG(host->cs, PAGE_SIZE, i);
+			found = 1;
+		}
+	if (!found)
+		dev_warn(&host->pdev->dev, "invalid page size %u\n",
+			cfg->page_size);
+#endif
+
+	if (fls64(cfg->device_size) < 23)
+		dev_warn(&host->pdev->dev, "invalid device size 0x%llx\n",
+			(unsigned long long)cfg->device_size);
+
+	WR_CONFIG(host->cs, DEVICE_SIZE, fls64(cfg->device_size) - 23);
+	WR_CONFIG(host->cs, DEVICE_WIDTH, cfg->device_width == 16 ? 1 : 0);
+	WR_CONFIG(host->cs, COL_ADR_BYTES, cfg->col_adr_bytes);
+	WR_CONFIG(host->cs, BLK_ADR_BYTES, cfg->blk_adr_bytes);
+	WR_CONFIG(host->cs, FUL_ADR_BYTES, cfg->ful_adr_bytes);
+
+	WR_ACC_CONTROL(host->cs, SPARE_AREA_SIZE, cfg->spare_area_size);
+#if CONTROLLER_VER >= 50
+	WR_ACC_CONTROL(host->cs, SECTOR_SIZE_1K, cfg->sector_size_1k);
+#endif
+
+	WR_ACC_CONTROL(host->cs, ECC_LEVEL, cfg->ecc_level);
+	/* threshold = ceil(BCH-level * 0.75) */
+	WR_CORR_THRESH(host->cs, ((cfg->ecc_level << cfg->sector_size_1k)
+				* 3 + 2) / 4);
+}
+
+static void brcmstb_nand_get_cfg(struct brcmstb_nand_host *host,
+	struct brcmstb_nand_cfg *cfg)
+{
+#if CONTROLLER_VER >= 71
+	cfg->block_size = 8192 << RD_CONFIG_EXT(host->cs, BLOCK_SIZE);
+	cfg->page_size = 512 << RD_CONFIG_EXT(host->cs, PAGE_SIZE);
+#else
+	cfg->block_size = RD_CONFIG(host->cs, BLOCK_SIZE);
+	if (cfg->block_size < ARRAY_SIZE(block_sizes))
+		cfg->block_size = block_sizes[cfg->block_size] << 10;
+	else
+		cfg->block_size = 128 << 10;
+
+	cfg->page_size = RD_CONFIG(host->cs, PAGE_SIZE);
+	if (cfg->page_size < ARRAY_SIZE(page_sizes))
+		cfg->page_size = page_sizes[cfg->page_size];
+	else
+		cfg->page_size = 2048;
+#endif
+	cfg->device_size = (4ULL << 20) << RD_CONFIG(host->cs, DEVICE_SIZE);
+	cfg->device_width = RD_CONFIG(host->cs, DEVICE_WIDTH) ? 16 : 8;
+	cfg->col_adr_bytes = RD_CONFIG(host->cs, COL_ADR_BYTES);
+	cfg->blk_adr_bytes = RD_CONFIG(host->cs, BLK_ADR_BYTES);
+	cfg->ful_adr_bytes = RD_CONFIG(host->cs, FUL_ADR_BYTES);
+	cfg->spare_area_size = RD_ACC_CONTROL(host->cs, SPARE_AREA_SIZE);
+#if CONTROLLER_VER >= 50
+	cfg->sector_size_1k = RD_ACC_CONTROL(host->cs, SECTOR_SIZE_1K);
+#else
+	cfg->sector_size_1k = 0;
+#endif
+	cfg->ecc_level = RD_ACC_CONTROL(host->cs, ECC_LEVEL);
+}
+
+static void brcmstb_nand_print_cfg(char *buf, struct brcmstb_nand_cfg *cfg)
+{
+	buf += sprintf(buf,
+		"%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
+		(unsigned long long)cfg->device_size >> 20,
+		cfg->block_size >> 10,
+		cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
+		cfg->page_size >= 1024 ? "KiB" : "B",
+		cfg->spare_area_size, cfg->device_width);
+
+	/* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
+	if (is_hamming_ecc(cfg))
+		sprintf(buf, ", Hamming ECC");
+	else if (cfg->sector_size_1k)
+		sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
+	else
+		sprintf(buf, ", BCH-%u\n", cfg->ecc_level);
+}
+
+/*
+ * Return true if the two configurations are basically identical. Note that we
+ * allow certain variations in spare area size.
+ */
+static bool brcmstb_nand_config_match(struct brcmstb_nand_cfg *orig,
+		struct brcmstb_nand_cfg *new)
+{
+	/* Negative matches */
+	if (orig->device_size != new->device_size)
+		return false;
+	if (orig->block_size != new->block_size)
+		return false;
+	if (orig->page_size != new->page_size)
+		return false;
+	if (orig->device_width != new->device_width)
+		return false;
+	if (orig->col_adr_bytes != new->col_adr_bytes)
+		return false;
+	/* blk_adr_bytes can be larger than expected, but not smaller */
+	if (orig->blk_adr_bytes < new->blk_adr_bytes)
+		return false;
+	if (orig->ful_adr_bytes < new->ful_adr_bytes)
+		return false;
+
+	/* Positive matches */
+	if (orig->spare_area_size == new->spare_area_size)
+		return true;
+	return orig->spare_area_size >= 27 &&
+	       orig->spare_area_size <= new->spare_area_size;
+}
+
+/*
+ * Minimum number of bytes to address a page. Calculated as:
+ *     roundup(log2(size / page-size) / 8)
+ *
+ * NB: the following does not "round up" for non-power-of-2 'size'; but this is
+ *     OK because many other things will break if 'size' is irregular...
+ */
+static inline int get_blk_adr_bytes(u64 size, u32 writesize)
+{
+	return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
+}
+
+static int brcmstb_nand_setup_dev(struct brcmstb_nand_host *host)
+{
+	struct mtd_info *mtd = &host->mtd;
+	struct nand_chip *chip = &host->chip;
+	struct brcmstb_nand_cfg orig_cfg, new_cfg;
+	char msg[128];
+
+	brcmstb_nand_get_cfg(host, &orig_cfg);
+	host->hwcfg = orig_cfg;
+
+	memset(&new_cfg, 0, sizeof(new_cfg));
+	new_cfg.device_size = mtd->size;
+	new_cfg.block_size = mtd->erasesize;
+	new_cfg.page_size = mtd->writesize;
+	new_cfg.spare_area_size = mtd->oobsize / (mtd->writesize >> FC_SHIFT);
+	new_cfg.device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
+	new_cfg.col_adr_bytes = 2;
+	new_cfg.blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
+
+	new_cfg.ful_adr_bytes = new_cfg.blk_adr_bytes;
+	if (mtd->writesize > 512)
+		new_cfg.ful_adr_bytes += new_cfg.col_adr_bytes;
+	else
+		new_cfg.ful_adr_bytes += 1;
+
+	if (new_cfg.spare_area_size > MAX_CONTROLLER_OOB)
+		new_cfg.spare_area_size = MAX_CONTROLLER_OOB;
+
+	if (!brcmstb_nand_config_match(&orig_cfg, &new_cfg)) {
+#if CONTROLLER_VER >= 50
+		/* default to 1K sector size (if page is large enough) */
+		new_cfg.sector_size_1k = (new_cfg.page_size >= 1024) ? 1 : 0;
+#endif
+
+		WR_ACC_CONTROL(host->cs, RD_ECC_EN, 1);
+		WR_ACC_CONTROL(host->cs, WR_ECC_EN, 1);
+
+		if (new_cfg.spare_area_size >= 36 && new_cfg.sector_size_1k)
+			new_cfg.ecc_level = 20;
+		else if (new_cfg.spare_area_size >= 22)
+			new_cfg.ecc_level = 12;
+		else if (chip->badblockpos == NAND_SMALL_BADBLOCK_POS)
+			new_cfg.ecc_level = 5;
+		else
+			new_cfg.ecc_level = 8;
+
+		brcmstb_nand_set_cfg(host, &new_cfg);
+		host->hwcfg = new_cfg;
+
+		if (BDEV_RD(BCHP_NAND_CS_NAND_SELECT) & (0x100 << host->cs)) {
+			/* bootloader activated this CS */
+			dev_warn(&host->pdev->dev, "overriding bootloader "
+				"settings on CS%d\n", host->cs);
+			brcmstb_nand_print_cfg(msg, &orig_cfg);
+			dev_warn(&host->pdev->dev, "was: %s\n", msg);
+			brcmstb_nand_print_cfg(msg, &new_cfg);
+			dev_warn(&host->pdev->dev, "now: %s\n", msg);
+		} else {
+			/*
+			 * nandcs= argument activated this CS; assume that
+			 * nobody even tried to set the device configuration
+			 */
+			brcmstb_nand_print_cfg(msg, &new_cfg);
+			dev_info(&host->pdev->dev, "detected %s\n", msg);
+		}
+	} else {
+		/*
+		 * Set oobsize to be consistent with controller's
+		 * spare_area_size. This helps nandwrite testing.
+		 */
+		mtd->oobsize = orig_cfg.spare_area_size *
+			       (mtd->writesize >> FC_SHIFT);
+
+		brcmstb_nand_print_cfg(msg, &orig_cfg);
+		dev_info(&host->pdev->dev, "%s\n", msg);
+	}
+
+#if CONTROLLER_VER < 70
+	WR_ACC_CONTROL(host->cs, FAST_PGM_RDIN, 0);
+#endif
+	WR_ACC_CONTROL(host->cs, RD_ERASED_ECC_EN, 0);
+	WR_ACC_CONTROL(host->cs, PARTIAL_PAGE_EN, 0);
+	WR_ACC_CONTROL(host->cs, PAGE_HIT_EN, 1);
+#if CONTROLLER_VER >= 60
+	WR_ACC_CONTROL(host->cs, PREFETCH_EN, 0);
+#endif
+	mb();
+
+	return 0;
+}
+
+static int brcmstb_nand_init_cs(struct brcmstb_nand_host *host)
+{
+	struct brcmstb_nand_controller *ctrl = host->ctrl;
+	struct brcmnand_platform_data *pd = host->pdev->dev.platform_data;
+	struct device_node *dn = host->of_node;
+	struct platform_device *pdev = host->pdev;
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	int ret = 0;
+
+	const char *part_probe_types[] = { "cmdlinepart", "ofpart", "RedBoot",
+		NULL };
+#ifdef CONFIG_OF
+	struct mtd_part_parser_data ppdata = { .of_node = dn };
+#endif
+
+	if (dn) {
+		ret = of_property_read_u32(dn, "reg", &host->cs);
+		if (ret) {
+			dev_err(&pdev->dev, "can't get chip-select\n");
+			return -ENXIO;
+		}
+	} else {
+		host->cs = pd->chip_select;
+	}
+
+	DBG("%s: cs %d\n", __func__, host->cs);
+
+	mtd = &host->mtd;
+	chip = &host->chip;
+
+	chip->priv = host;
+	mtd->priv = chip;
+	mtd->name = dev_name(&pdev->dev);
+	mtd->owner = THIS_MODULE;
+	mtd->dev.parent = &pdev->dev;
+
+	chip->IO_ADDR_R = (void *)0xdeadbeef;
+	chip->IO_ADDR_W = (void *)0xdeadbeef;
+
+	chip->cmd_ctrl = brcmstb_nand_cmd_ctrl;
+	chip->cmdfunc = brcmstb_nand_cmdfunc;
+	chip->waitfunc = brcmstb_nand_waitfunc;
+	chip->read_byte = brcmstb_nand_read_byte;
+	chip->read_buf = brcmstb_nand_read_buf;
+	chip->write_buf = brcmstb_nand_write_buf;
+
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.read_page = brcmstb_nand_read_page;
+	chip->ecc.read_subpage = brcmstb_nand_read_subpage;
+	chip->ecc.write_page = brcmstb_nand_write_page;
+	chip->ecc.read_page_raw = brcmstb_nand_read_page_raw;
+	chip->ecc.write_page_raw = brcmstb_nand_write_page_raw;
+	chip->ecc.write_oob_raw = brcmstb_nand_write_oob_raw;
+	chip->ecc.read_oob_raw = brcmstb_nand_read_oob_raw;
+	chip->ecc.read_oob = brcmstb_nand_read_oob;
+	chip->ecc.write_oob = brcmstb_nand_write_oob;
+
+	chip->controller = &ctrl->controller;
+
+	if (nand_scan_ident(mtd, 1, NULL))
+		return -ENXIO;
+
+	chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;
+	/*
+	 * NAND_USE_BOUNCE_BUFFER option prevents us from getting
+	 * passed kmapped buffer that we cannot DMA.
+	 * When option is set nand_base passes preallocated poi
+	 * buffer that is used as bounce buffer for DMA
+	 */
+	chip->options |= NAND_USE_BOUNCE_BUFFER;
+
+	if (of_get_nand_on_flash_bbt(dn))
+		chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+
+	if (brcmstb_nand_setup_dev(host))
+		return -ENXIO;
+
+	/* nand_scan_tail() needs this to be set up */
+	if (is_hamming_ecc(&host->hwcfg))
+		chip->ecc.strength = 1;
+	else
+		chip->ecc.strength = host->hwcfg.ecc_level
+				<< host->hwcfg.sector_size_1k;
+	chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
+	/* only use our internal HW threshold */
+	mtd->bitflip_threshold = 1;
+
+	chip->ecc.layout = brcmstb_choose_ecc_layout(host);
+	if (!chip->ecc.layout)
+		return -ENXIO;
+
+	if (nand_scan_tail(mtd) || chip->scan_bbt(mtd))
+		return -ENXIO;
+
+	/* Update ecclayout info after nand_scan_tail() */
+	mtd->oobavail = chip->ecc.layout->oobavail;
+	mtd->ecclayout = chip->ecc.layout;
+
+#ifdef CONFIG_OF
+	return mtd_device_parse_register(mtd, part_probe_types, &ppdata, NULL, 0);
+#else
+	return mtd_device_parse_register(mtd, part_probe_types, NULL, pd->parts,
+					 pd->nr_parts);
+#endif
+}
+
+static int brcmstb_nand_suspend(struct device *dev)
+{
+	struct brcmstb_nand_controller *ctrl = dev_get_drvdata(dev);
+	struct brcmstb_nand_host *host;
+
+	dev_dbg(dev, "Save state for S3 suspend\n");
+
+	list_for_each_entry(host, &ctrl->host_list, node) {
+		host->hwcfg.acc_control = BDEV_RD(REG_ACC_CONTROL(host->cs));
+		host->hwcfg.config = BDEV_RD(REG_CONFIG(host->cs));
+#if CONTROLLER_VER >= 71
+		host->hwcfg.config_ext = BDEV_RD(REG_CONFIG_EXT(host->cs));
+#endif
+		host->hwcfg.timing_1 = BDEV_RD(REG_TIMING_1(host->cs));
+		host->hwcfg.timing_2 = BDEV_RD(REG_TIMING_2(host->cs));
+	}
+
+	ctrl->nand_cs_nand_select = BDEV_RD(BCHP_NAND_CS_NAND_SELECT);
+	ctrl->nand_cs_nand_xor = BDEV_RD(BCHP_NAND_CS_NAND_XOR);
+	ctrl->corr_stat_threshold = BDEV_RD(BCHP_NAND_CORR_STAT_THRESHOLD);
+
+	if (!ctrl->irq_cascaded) {
+		HIF_DISABLE_IRQ(NAND_CTLRDY);
+		if (has_flash_dma(ctrl))
+			flash_dma_irq_disable(ctrl);
+	}
+
+	if (has_flash_dma(ctrl))
+		ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
+
+	return 0;
+}
+
+static int brcmstb_nand_resume(struct device *dev)
+{
+	struct brcmstb_nand_controller *ctrl = dev_get_drvdata(dev);
+	struct brcmstb_nand_host *host;
+
+	dev_dbg(dev, "Restore state after S3 suspend\n");
+
+	if (has_flash_dma(ctrl)) {
+		flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
+		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
+	}
+
+	BDEV_WR_RB(BCHP_NAND_CS_NAND_SELECT, ctrl->nand_cs_nand_select);
+	BDEV_WR_RB(BCHP_NAND_CS_NAND_XOR, ctrl->nand_cs_nand_xor);
+	BDEV_WR_RB(BCHP_NAND_CORR_STAT_THRESHOLD,
+			ctrl->corr_stat_threshold);
+
+	if (!ctrl->irq_cascaded) {
+		HIF_ACK_IRQ(NAND_CTLRDY);
+		HIF_ENABLE_IRQ(NAND_CTLRDY);
+		if (has_flash_dma(ctrl))
+			flash_dma_irq_enable(ctrl);
+	}
+
+	list_for_each_entry(host, &ctrl->host_list, node) {
+		struct mtd_info *mtd = &host->mtd;
+		struct nand_chip *chip = mtd->priv;
+
+		BDEV_WR_RB(REG_ACC_CONTROL(host->cs), host->hwcfg.acc_control);
+		BDEV_WR_RB(REG_CONFIG(host->cs), host->hwcfg.config);
+#if CONTROLLER_VER >= 71
+		BDEV_WR_RB(REG_CONFIG_EXT(host->cs), host->hwcfg.config_ext);
+#endif
+		BDEV_WR_RB(REG_TIMING_1(host->cs), host->hwcfg.timing_1);
+		BDEV_WR_RB(REG_TIMING_2(host->cs), host->hwcfg.timing_2);
+
+		/* Reset the chip, required by some chips after power-up */
+		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops brcmstb_nand_pm_ops = {
+	.suspend		= brcmstb_nand_suspend,
+	.resume			= brcmstb_nand_resume,
+};
+
+/***********************************************************************
+ * Platform driver setup (per controller)
+ ***********************************************************************/
+
+static int brcmstb_nand_check_irq_cascade(struct device *dev,
+		struct brcmstb_nand_controller *ctrl)
+{
+	struct device_node *dn = dev->of_node, *int_parent;
+	int ret, intlen;
+
+	int_parent = of_parse_phandle(dn, "interrupt-parent", 0);
+	if (!int_parent) {
+		ctrl->irq_cascaded = false;
+		return 0;
+	}
+
+	ret = of_property_read_u32(int_parent, "#interrupt-cells", &intlen);
+	if (ret)
+		return -EINVAL;
+	if (intlen == 1) {
+		dev_info(dev, "using HIF_INTR2 cascaded IRQ\n");
+		ctrl->irq_cascaded = true;
+	}
+
+	return 0;
+}
+
+static int brcmstb_nand_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *dn = dev->of_node, *child;
+	static struct brcmstb_nand_controller *ctrl;
+	struct resource *res;
+	int ret;
+
+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, ctrl);
+
+	init_completion(&ctrl->done);
+	init_completion(&ctrl->dma_done);
+	spin_lock_init(&ctrl->controller.lock);
+	init_waitqueue_head(&ctrl->controller.wq);
+	INIT_LIST_HEAD(&ctrl->host_list);
+
+	ret = brcmstb_nand_check_irq_cascade(dev, ctrl);
+	if (ret)
+		return ret;
+
+	/*
+	 * NAND
+	 * FIXME: eventually, should get resource by name ("nand"), but the DT
+	 * binding may be in flux for a while (8/16/13)
+	 */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "can't get NAND register range\n");
+		return -ENODEV;
+	}
+
+	if (!devm_request_mem_region(dev, res->start, resource_size(res),
+				DRV_NAME)) {
+		dev_err(dev, "can't request NAND memory region\n");
+		return -ENODEV;
+	}
+
+	/* FLASH_DMA */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
+	if (res) {
+		ctrl->flash_dma_base = devm_request_and_ioremap(dev, res);
+		if (!ctrl->flash_dma_base)
+			return -ENODEV;
+
+		flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
+		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
+
+		/* Allocate descriptor(s) */
+		ctrl->dma_desc = dmam_alloc_coherent(dev,
+						     sizeof(*ctrl->dma_desc),
+						     &ctrl->dma_pa, GFP_KERNEL);
+		if (!ctrl->dma_desc)
+			return -ENOMEM;
+
+		if (ctrl->irq_cascaded) {
+			ctrl->dma_irq = platform_get_irq(pdev, 1);
+			if ((int)ctrl->dma_irq < 0) {
+				dev_err(dev, "missing FLASH_DMA IRQ\n");
+				return -ENODEV;
+			}
+
+			ret = devm_request_irq(dev, ctrl->dma_irq,
+					brcmstb_nand_dma_irq, 0, DRV_NAME,
+					ctrl);
+			if (ret < 0) {
+				dev_err(dev, "can't allocate IRQ %d: error %d\n",
+						ctrl->dma_irq, ret);
+				return ret;
+			}
+		}
+
+		dev_info(dev, "enabling FLASH_DMA\n");
+	}
+
+	BDEV_WR_F(NAND_CS_NAND_SELECT, AUTO_DEVICE_ID_CONFIG, 0);
+
+	/* disable direct addressing + XOR for all NAND devices */
+	BDEV_UNSET(BCHP_NAND_CS_NAND_SELECT, 0xff);
+	BDEV_UNSET(BCHP_NAND_CS_NAND_XOR, 0xff);
+
+#ifdef BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK
+	if (wp_on == 2) /* SWLINUX-1818: Permanently remove write-protection */
+		BDEV_WR_F_RB(NAND_CS_NAND_SELECT, NAND_WP, 0);
+#else
+	wp_on = 0;
+#endif
+
+	/* IRQ */
+	ctrl->irq = platform_get_irq(pdev, 0);
+	if ((int)ctrl->irq < 0) {
+		dev_err(dev, "no IRQ defined\n");
+		return -ENODEV;
+	}
+
+	if (!ctrl->irq_cascaded) {
+		HIF_ACK_IRQ(NAND_CTLRDY);
+		HIF_ENABLE_IRQ(NAND_CTLRDY);
+		if (has_flash_dma(ctrl))
+			flash_dma_irq_enable(ctrl);
+	}
+
+	if (ctrl->irq_cascaded) {
+		ret = devm_request_irq(dev, ctrl->irq, brcmstb_nand_ctlrdy_irq,
+				0, DRV_NAME, ctrl);
+	} else {
+		ret = devm_request_irq(dev, ctrl->irq, brcmstb_nand_irq,
+				IRQF_SHARED, DRV_NAME, ctrl);
+	}
+	if (ret < 0) {
+		dev_err(dev, "can't allocate IRQ %d: error %d\n",
+			ctrl->irq, ret);
+		goto out;
+	}
+	for_each_available_child_of_node(dn, child) {
+		if (of_device_is_compatible(child, "brcm,nandcs")) {
+			struct brcmstb_nand_host *host;
+
+			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+			if (!host) {
+				ret = -ENOMEM;
+				goto out;
+			}
+			host->pdev = pdev;
+			host->ctrl = ctrl;
+			host->of_node = child;
+
+			ret = brcmstb_nand_init_cs(host);
+			if (ret)
+				continue; /* Try all chip-selects */
+
+			list_add_tail(&host->node, &ctrl->host_list);
+		}
+	}
+
+	if (!dn) {
+		struct brcmstb_nand_host *host;
+
+		host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+		if (!host) {
+			ret = -ENOMEM;
+			goto out;
+		}
+		host->pdev = pdev;
+		host->ctrl = ctrl;
+
+		ret = brcmstb_nand_init_cs(host);
+		if (ret)
+			return ret;
+
+		list_add_tail(&host->node, &ctrl->host_list);
+	}
+
+	/* No chip-selects could initialize properly */
+	if (list_empty(&ctrl->host_list)) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	return 0;
+
+out:
+	if (!ctrl->irq_cascaded) {
+		HIF_DISABLE_IRQ(NAND_CTLRDY);
+		if (has_flash_dma(ctrl))
+			flash_dma_irq_disable(ctrl);
+	}
+	return ret;
+}
+
+static int brcmstb_nand_remove(struct platform_device *pdev)
+{
+	struct brcmstb_nand_controller *ctrl = dev_get_drvdata(&pdev->dev);
+	struct brcmstb_nand_host *host;
+
+	list_for_each_entry(host, &ctrl->host_list, node)
+		nand_release(&host->mtd);
+
+	if (!ctrl->irq_cascaded) {
+		HIF_DISABLE_IRQ(NAND_CTLRDY);
+		if (has_flash_dma(ctrl))
+			flash_dma_irq_disable(ctrl);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id brcmstb_nand_of_match[] = {
+	{ .compatible = "brcm,brcmnand" },
+	{},
+};
+
+static struct platform_driver brcmstb_nand_driver = {
+	.probe			= brcmstb_nand_probe,
+	.remove			= brcmstb_nand_remove,
+	.driver = {
+		.name		= "brcmnand",
+		.owner		= THIS_MODULE,
+		.pm		= &brcmstb_nand_pm_ops,
+		.of_match_table = of_match_ptr(brcmstb_nand_of_match),
+	}
+};
+module_platform_driver(brcmstb_nand_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("NAND driver for STB chips");
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index efc542d00c84..5ff009b589ea 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -37,6 +37,7 @@
 #include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
+#include <linux/mm.h>
 #include <linux/types.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -1498,6 +1499,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 		mtd->oobavail : mtd->oobsize;
 
 	uint8_t *bufpoi, *oob, *buf;
+	int use_bufpoi;
 	unsigned int max_bitflips = 0;
 	int retry_mode = 0;
 	bool ecc_fail = false;
@@ -1520,9 +1522,20 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 		bytes = min(mtd->writesize - col, readlen);
 		aligned = (bytes == mtd->writesize);
 
+		if (!aligned)
+			use_bufpoi = 1;
+		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+			use_bufpoi = !virt_addr_valid(buf);
+		else
+			use_bufpoi = 0;
+
 		/* Is the current page in the buffer? */
 		if (realpage != chip->pagebuf || oob) {
-			bufpoi = aligned ? buf : chip->buffers->databuf;
+			bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
+
+			if (use_bufpoi && aligned)
+				pr_debug("%s: using read bounce buffer for buf@%p\n",
+						 __func__, buf);
 
 read_retry:
 			chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
@@ -1543,7 +1556,7 @@ read_retry:
 				ret = chip->ecc.read_page(mtd, chip, bufpoi,
 							  oob_required, page);
 			if (ret < 0) {
-				if (!aligned)
+				if (use_bufpoi)
 					/* Invalidate page cache */
 					chip->pagebuf = -1;
 				break;
@@ -1552,7 +1565,7 @@ read_retry:
 			max_bitflips = max_t(unsigned int, max_bitflips, ret);
 
 			/* Transfer not aligned data */
-			if (!aligned) {
+			if (use_bufpoi) {
 				if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
 				    !(mtd->ecc_stats.failed - ecc_failures) &&
 				    (ops->mode != MTD_OPS_RAW)) {
@@ -2372,11 +2385,23 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 		int bytes = mtd->writesize;
 		int cached = writelen > bytes && page != blockmask;
 		uint8_t *wbuf = buf;
+		int use_bufpoi;
+		int part_pagewr = (column || writelen < (mtd->writesize - 1));
+
+		if (part_pagewr)
+			use_bufpoi = 1;
+		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+			use_bufpoi = !virt_addr_valid(buf);
+		else
+			use_bufpoi = 0;
 
-		/* Partial page write? */
-		if (unlikely(column || writelen < (mtd->writesize - 1))) {
+		/* Partial page write?, or need to use bounce buffer */
+		if (use_bufpoi) {
+			pr_debug("%s: using write bounce buffer for buf@%p\n",
+					 __func__, buf);
 			cached = 0;
-			bytes = min_t(int, bytes - column, (int) writelen);
+			if (part_pagewr)
+				bytes = min_t(int, bytes - column, writelen);
 			chip->pagebuf = -1;
 			memset(chip->buffers->databuf, 0xff, mtd->writesize);
 			memcpy(&chip->buffers->databuf[column], buf, bytes);
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index b8fe808b7957..dcc839102032 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -36,4 +36,16 @@ config NET_DSA_MV88E6123_61_65
 	  This enables support for the Marvell 88E6123/6161/6165
 	  ethernet switch chips.
 
+config NET_DSA_BCM_SF2
+	tristate "Broadcom Starfighter 2 Ethernet switch support"
+	select NET_DSA
+	select NET_DSA_TAG_BRCM
+	select BCM7XXX_PHY
+	select BCM531XX_PHY
+	select MDIO_UNIMAC
+	default y if BRCMSTB
+	---help---
+	  This enables support for the Broadcom Starfighter 2 ethernet
+	  switch chips.
+
 endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index f3bda05536cc..dd3cd3b8157f 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -7,3 +7,4 @@ endif
 ifdef CONFIG_NET_DSA_MV88E6131
 mv88e6xxx_drv-y += mv88e6131.o
 endif
+obj-$(CONFIG_NET_DSA_BCM_SF2)	+= bcm_sf2.o
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
new file mode 100644
index 000000000000..b79a688ea776
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -0,0 +1,1207 @@
+/*
+ * Broadcom Starfighter 2 DSA switch driver
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/mii.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <net/dsa.h>
+#include <linux/ethtool.h>
+#include <linux/if_bridge.h>
+#include <linux/brcmphy.h>
+#include <linux/kexec.h>
+
+#include "bcm_sf2.h"
+#include "bcm_sf2_regs.h"
+
+/* String, offset, and register size in bytes if different from 4 bytes */
+static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
+	{ "TxOctets",		0x000, 8	},
+	{ "TxDropPkts",		0x020		},
+	{ "TxQPKTQ0",		0x030		},
+	{ "TxBroadcastPkts",	0x040		},
+	{ "TxMulticastPkts",	0x050		},
+	{ "TxUnicastPKts",	0x060		},
+	{ "TxCollisions",	0x070		},
+	{ "TxSingleCollision",	0x080		},
+	{ "TxMultipleCollision", 0x090		},
+	{ "TxDeferredCollision", 0x0a0		},
+	{ "TxLateCollision",	0x0b0		},
+	{ "TxExcessiveCollision", 0x0c0		},
+	{ "TxFrameInDisc",	0x0d0		},
+	{ "TxPausePkts",	0x0e0		},
+	{ "TxQPKTQ1",		0x0f0		},
+	{ "TxQPKTQ2",		0x100		},
+	{ "TxQPKTQ3",		0x110		},
+	{ "TxQPKTQ4",		0x120		},
+	{ "TxQPKTQ5",		0x130		},
+	{ "RxOctets",		0x140, 8	},
+	{ "RxUndersizePkts",	0x160		},
+	{ "RxPausePkts",	0x170		},
+	{ "RxPkts64Octets",	0x180		},
+	{ "RxPkts65to127Octets", 0x190		},
+	{ "RxPkts128to255Octets", 0x1a0		},
+	{ "RxPkts256to511Octets", 0x1b0		},
+	{ "RxPkts512to1023Octets", 0x1c0	},
+	{ "RxPkts1024toMaxPktsOctets", 0x1d0	},
+	{ "RxOversizePkts",	0x1e0		},
+	{ "RxJabbers",		0x1f0		},
+	{ "RxAlignmentErrors",	0x200		},
+	{ "RxFCSErrors",	0x210		},
+	{ "RxGoodOctets",	0x220, 8	},
+	{ "RxDropPkts",		0x240		},
+	{ "RxUnicastPkts",	0x250		},
+	{ "RxMulticastPkts",	0x260		},
+	{ "RxBroadcastPkts",	0x270		},
+	{ "RxSAChanges",	0x280		},
+	{ "RxFragments",	0x290		},
+	{ "RxJumboPkt",		0x2a0		},
+	{ "RxSymblErr",		0x2b0		},
+	{ "InRangeErrCount",	0x2c0		},
+	{ "OutRangeErrCount",	0x2d0		},
+	{ "EEELpiEvent",	0x2e0		},
+	{ "EEELpiDuration",	0x2f0		},
+	{ "RxDiscard",		0x300, 8	},
+	{ "TxQPKTQ6",		0x320		},
+	{ "TxQPKTQ7",		0x330		},
+	{ "TxPkts64Octets",	0x340		},
+	{ "TxPkts65to127Octets", 0x350		},
+	{ "TxPkts128to255Octets", 0x360		},
+	{ "TxPkts256to511Ocets", 0x370		},
+	{ "TxPkts512to1023Ocets", 0x380		},
+	{ "TxPkts1024toMaxPktOcets", 0x390	},
+};
+
+#define BCM_SF2_STATS_SIZE	ARRAY_SIZE(bcm_sf2_mib)
+
+static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
+					int port, uint8_t *data)
+{
+	unsigned int i;
+
+	for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
+		memcpy(data + i * ETH_GSTRING_LEN,
+			bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
+}
+
+static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
+					int port, uint64_t *data)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	const struct bcm_sf2_hw_stats *s;
+	unsigned int i;
+	u64 val = 0;
+	u32 offset;
+
+	mutex_lock(&priv->stats_mutex);
+
+	/* Now fetch the per-port counters */
+	for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
+		s = &bcm_sf2_mib[i];
+
+		/* Do a latched 64-bit read if needed */
+		offset = s->reg + CORE_P_MIB_OFFSET(port);
+		if (s->sizeof_stat == 8)
+			val = core_readq(priv, offset);
+		else
+			val = core_readl(priv, offset);
+
+		data[i] = (u64)val;
+	}
+
+	mutex_unlock(&priv->stats_mutex);
+}
+
+static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
+{
+	return BCM_SF2_STATS_SIZE;
+}
+
+static char *bcm_sf2_sw_probe(struct mii_bus *bus, int sw_addr)
+{
+	return "Broadcom Starfighter 2";
+}
+
+/* Return the number of active ports, not counting the IMP (CPU) port */
+static unsigned bcm_sf2_num_active_ports(struct dsa_switch *ds)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int port, count = 0;
+
+	for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
+		if (dsa_is_cpu_port(ds, port))
+			continue;
+		if (priv->port_sts[port].enabled)
+			count++;
+	}
+
+	return count;
+}
+
+static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned long new_rate;
+	unsigned int ports_active;
+	/* Frequenty in Mhz */
+	const unsigned long rate_table[] = {
+		59220000,
+		60820000,
+		62500000,
+		62500000,
+	};
+
+	ports_active = bcm_sf2_num_active_ports(ds);
+	if (ports_active == 0 || !priv->clk_mdiv)
+		return;
+
+	/* If we overflow our table, just use the recommended operational
+	 * frequency
+	 */
+	if (ports_active > ARRAY_SIZE(rate_table))
+		new_rate = 90000000;
+	else
+		new_rate = rate_table[ports_active - 1];
+	clk_set_rate(priv->clk_mdiv, new_rate);
+}
+
+static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int i;
+	u32 reg;
+
+	/* Enable the IMP Port to be in the same VLAN as the other ports
+	 * on a per-port basis such that we only have Port i and IMP in
+	 * the same VLAN.
+	 */
+	for (i = 0; i < priv->hw_params.num_ports; i++) {
+		if (!((1 << i) & ds->phys_port_mask))
+			continue;
+
+		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+		reg |= (1 << cpu_port);
+		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+	}
+}
+
+static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 reg, val;
+
+	/* Enable the port memories */
+	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+	reg &= ~P_TXQ_PSM_VDD(port);
+	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+	/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
+	reg = core_readl(priv, CORE_IMP_CTL);
+	reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
+	reg &= ~(RX_DIS | TX_DIS);
+	core_writel(priv, reg, CORE_IMP_CTL);
+
+	/* Enable forwarding */
+	core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
+
+	/* Enable IMP port in dumb mode */
+	reg = core_readl(priv, CORE_SWITCH_CTRL);
+	reg |= MII_DUMB_FWDG_EN;
+	core_writel(priv, reg, CORE_SWITCH_CTRL);
+
+	/* Resolve which bit controls the Broadcom tag */
+	switch (port) {
+	case 8:
+		val = BRCM_HDR_EN_P8;
+		break;
+	case 7:
+		val = BRCM_HDR_EN_P7;
+		break;
+	case 5:
+		val = BRCM_HDR_EN_P5;
+		break;
+	default:
+		val = 0;
+		break;
+	}
+
+	/* Enable Broadcom tags for IMP port */
+	reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
+	reg |= val;
+	core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
+
+	/* Enable reception Broadcom tag for CPU TX (switch RX) to
+	 * allow us to tag outgoing frames
+	 */
+	reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
+	reg &= ~(1 << port);
+	core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
+
+	/* Enable transmission of Broadcom tags from the switch (CPU RX) to
+	 * allow delivering frames to the per-port net_devices
+	 */
+	reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
+	reg &= ~(1 << port);
+	core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
+
+	/* Force link status for IMP port */
+	reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
+	reg |= (MII_SW_OR | LINK_STS);
+	core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
+
+	priv->port_sts[port].enabled = true;
+}
+
+static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 reg;
+
+	reg = core_readl(priv, CORE_EEE_EN_CTRL);
+	if (enable)
+		reg |= 1 << port;
+	else
+		reg &= ~(1 << port);
+	core_writel(priv, reg, CORE_EEE_EN_CTRL);
+}
+
+static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 reg;
+
+	reg = reg_readl(priv, REG_SPHY_CNTRL);
+	if (enable) {
+		reg |= PHY_RESET;
+		reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
+		reg_writel(priv, reg, REG_SPHY_CNTRL);
+		udelay(21);
+		reg = reg_readl(priv, REG_SPHY_CNTRL);
+		reg &= ~PHY_RESET;
+	} else {
+		reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
+		reg_writel(priv, reg, REG_SPHY_CNTRL);
+		mdelay(1);
+		reg |= CK25_DIS;
+	}
+	reg_writel(priv, reg, REG_SPHY_CNTRL);
+
+	/* Use PHY-driven LED signaling */
+	if (!enable) {
+		reg = reg_readl(priv, REG_LED_CNTRL(0));
+		reg |= SPDLNK_SRC_SEL;
+		reg_writel(priv, reg, REG_LED_CNTRL(0));
+	}
+}
+
+static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
+			      struct phy_device *phy)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	s8 cpu_port = ds->dst[ds->index].cpu_port;
+	u32 reg;
+
+	priv->port_sts[port].enabled = true;
+
+	bcm_sf2_recalc_clock(ds);
+
+	/* Clear the memory power down */
+	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+	reg &= ~P_TXQ_PSM_VDD(port);
+	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+	/* Clear the Rx and Tx disable bits and set to no spanning tree */
+	core_writel(priv, 0, CORE_G_PCTL_PORT(port));
+
+	/* Re-enable the GPHY and re-apply workarounds */
+	if (port == 0 && priv->hw_params.num_gphy == 1) {
+		bcm_sf2_gphy_enable_set(ds, true);
+		if (phy) {
+			/* if phy_stop() has been called before, phy
+			 * will be in halted state, and phy_start()
+			 * will call resume.
+			 *
+			 * the resume path does not configure back
+			 * autoneg settings, and since we hard reset
+			 * the phy manually here, we need to reset the
+			 * state machine also.
+			 */
+			phy->state = PHY_READY;
+			phy_init_hw(phy);
+		}
+	}
+
+	/* Enable port 7 interrupts to get notified */
+	if (port == 7)
+		intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
+
+	/* Set this port, and only this one to be in the default VLAN,
+	 * if member of a bridge, restore its membership prior to
+	 * bringing down this port.
+	 */
+	reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+	reg &= ~PORT_VLAN_CTRL_MASK;
+	reg |= (1 << port);
+	reg |= priv->port_sts[port].vlan_ctl_mask;
+	core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
+
+	bcm_sf2_imp_vlan_setup(ds, cpu_port);
+
+	/* If EEE was enabled, restore it */
+	if (priv->port_sts[port].eee.eee_enabled)
+		bcm_sf2_eee_enable_set(ds, port, true);
+
+	/* Set per-queue pause threshold to 32 */
+	core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
+
+	/* Set ACB threshold to 24 */
+	reg = acb_readl(priv, ACB_QUEUE_CFG(port * 8));
+	reg &= ~XOFF_THRESHOLD_MASK;
+	reg |= 24;
+	acb_writel(priv, reg, ACB_QUEUE_CFG(port * 8));
+
+	return 0;
+}
+
+static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 off, reg;
+
+	if (priv->wol_ports_mask & (1 << port)) {
+		pr_info("%s: port %d used for WoL\n", __func__, port);
+		return;
+	}
+
+	if (port == 7) {
+		intrl2_1_mask_set(priv, P_IRQ_MASK(P7_IRQ_OFF));
+		intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
+	}
+
+	if (port == 0 && priv->hw_params.num_gphy == 1)
+		bcm_sf2_gphy_enable_set(ds, false);
+
+	if (dsa_is_cpu_port(ds, port))
+		off = CORE_IMP_CTL;
+	else
+		off = CORE_G_PCTL_PORT(port);
+
+	reg = core_readl(priv, off);
+	reg |= RX_DIS | TX_DIS;
+	core_writel(priv, reg, off);
+
+	/* Power down the port memory */
+	reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+	reg |= P_TXQ_PSM_VDD(port);
+	core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+	priv->port_sts[port].enabled = false;
+
+	bcm_sf2_recalc_clock(ds);
+}
+
+/* Returns 0 if EEE was not enabled, or 1 otherwise
+ */
+static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
+			    struct phy_device *phy)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	struct ethtool_eee *p = &priv->port_sts[port].eee;
+	int ret;
+
+	p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
+
+	ret = phy_init_eee(phy, 0);
+	if (ret)
+		return 0;
+
+	bcm_sf2_eee_enable_set(ds, port, true);
+
+	return 1;
+}
+
+static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
+			      struct ethtool_eee *e)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	struct ethtool_eee *p = &priv->port_sts[port].eee;
+	u32 reg;
+
+	reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
+	e->eee_enabled = p->eee_enabled;
+	e->eee_active = !!(reg & (1 << port));
+
+	return 0;
+}
+
+static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
+			      struct phy_device *phydev,
+			      struct ethtool_eee *e)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	struct ethtool_eee *p = &priv->port_sts[port].eee;
+
+	p->eee_enabled = e->eee_enabled;
+
+	if (!p->eee_enabled)
+		bcm_sf2_eee_enable_set(ds, port, false);
+	else {
+		p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
+		if (!p->eee_enabled)
+			return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
+/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
+ * flush for that port.
+ */
+static int bcm_sf2_sw_fast_age_port(struct dsa_switch  *ds, int port)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int timeout = 1000;
+	u32 reg;
+
+	core_writel(priv, port, CORE_FAST_AGE_PORT);
+
+	reg = core_readl(priv, CORE_FAST_AGE_CTRL);
+	reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
+	core_writel(priv, reg, CORE_FAST_AGE_CTRL);
+
+	do {
+		reg = core_readl(priv, CORE_FAST_AGE_CTRL);
+		if (!(reg & FAST_AGE_STR_DONE))
+			break;
+
+		cpu_relax();
+	} while (timeout--);
+
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	core_writel(priv, 0, CORE_FAST_AGE_CTRL);
+
+	return 0;
+}
+
+static void bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
+			       u32 br_port_mask)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int i;
+	u32 reg, p_ctl;
+
+	p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+
+	for (i = 0; i < priv->hw_params.num_ports; i++) {
+		if (!((1 << i) & br_port_mask))
+			continue;
+
+		/* Add this local port to the remote port VLAN control
+		 * membership and update the remote port bitmask
+		 */
+		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+		reg |= 1 << port;
+		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+		priv->port_sts[i].vlan_ctl_mask = reg;
+
+		p_ctl |= 1 << i;
+	}
+
+	/* Configure the local port VLAN control membership to include
+	 * remote ports and update the local port bitmask
+	 */
+	core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
+	priv->port_sts[port].vlan_ctl_mask = p_ctl;
+}
+
+static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
+				u32 br_port_mask)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int i;
+	u32 reg, p_ctl;
+
+	p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+
+	for (i = 0; i < priv->hw_params.num_ports; i++) {
+		/* Don't touch the remaining ports */
+		if (!((1 << i) & br_port_mask))
+			continue;
+
+		reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+		reg &= ~(1 << port);
+		core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+		priv->port_sts[port].vlan_ctl_mask = reg;
+
+		/* Prevent self removal to preserve isolation */
+		if (port != i)
+			p_ctl &= ~(1 << i);
+	}
+
+	core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
+	priv->port_sts[port].vlan_ctl_mask = p_ctl;
+}
+
+static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
+					unsigned int state)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u8 hw_state, cur_hw_state;
+	int ret = 0;
+	u32 reg;
+
+	reg = core_readl(priv, CORE_G_PCTL_PORT(port));
+	cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
+
+	switch (state) {
+	case BR_STATE_DISABLED:
+		hw_state = G_MISTP_DIS_STATE;
+		break;
+	case BR_STATE_LISTENING:
+		hw_state = G_MISTP_LISTEN_STATE;
+		break;
+	case BR_STATE_LEARNING:
+		hw_state = G_MISTP_LEARN_STATE;
+		break;
+	case BR_STATE_FORWARDING:
+		hw_state = G_MISTP_FWD_STATE;
+		break;
+	case BR_STATE_BLOCKING:
+		hw_state = G_MISTP_BLOCK_STATE;
+		break;
+	default:
+		pr_err("%s: invalid STP state: %d\n", __func__, state);
+		return;
+	}
+
+	/* Fast-age ARL entries if we are moving a port from Learning or
+	 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
+	 * state (hw_state)
+	 */
+	if (cur_hw_state != hw_state) {
+		if (cur_hw_state >= G_MISTP_LEARN_STATE &&
+		    hw_state <= G_MISTP_LISTEN_STATE) {
+			ret = bcm_sf2_sw_fast_age_port(ds, port);
+			if (ret) {
+				pr_err("%s: fast-ageing failed\n", __func__);
+				return;
+			}
+		}
+	}
+
+	reg = core_readl(priv, CORE_G_PCTL_PORT(port));
+	reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
+	reg |= hw_state;
+	core_writel(priv, reg, CORE_G_PCTL_PORT(port));
+}
+
+static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
+{
+	struct bcm_sf2_priv *priv = dev_id;
+
+	priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
+				~priv->irq0_mask;
+	intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
+{
+	struct bcm_sf2_priv *priv = dev_id;
+
+	priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
+				~priv->irq1_mask;
+	intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
+
+	if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
+		priv->port_sts[7].link = 1;
+	if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
+		priv->port_sts[7].link = 0;
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
+{
+	unsigned int timeout = 1000;
+	u32 reg;
+
+	reg = core_readl(priv, CORE_WATCHDOG_CTRL);
+	reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
+	core_writel(priv, reg, CORE_WATCHDOG_CTRL);
+
+	do {
+		reg = core_readl(priv, CORE_WATCHDOG_CTRL);
+		if (!(reg & SOFTWARE_RESET))
+			break;
+
+		usleep_range(1000, 2000);
+	} while (timeout-- > 0);
+
+	if (timeout == 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
+{
+	intrl2_0_mask_set(priv, 0xffffffff);
+	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+	intrl2_1_mask_set(priv, 0xffffffff);
+	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+}
+
+static int bcm_sf2_sw_setup(struct dsa_switch *ds)
+{
+	const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	struct device_node *dn;
+	void __iomem **base;
+	unsigned int port;
+	unsigned int i;
+	u32 reg, rev;
+	int ret;
+
+	spin_lock_init(&priv->indir_lock);
+	mutex_init(&priv->stats_mutex);
+
+	/* All the interesting properties are at the parent device_node
+	 * level
+	 */
+	dn = ds->pd->of_node->parent;
+
+	priv->irq0 = irq_of_parse_and_map(dn, 0);
+	priv->irq1 = irq_of_parse_and_map(dn, 1);
+
+	base = &priv->core;
+	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
+		*base = of_iomap(dn, i);
+		if (*base == NULL) {
+			pr_err("unable to find register: %s\n", reg_names[i]);
+			ret = -ENODEV;
+			goto out_unmap;
+		}
+		base++;
+	}
+
+	priv->clk = of_clk_get_by_name(dn, "sw_switch");
+	if (IS_ERR(priv->clk)) {
+		pr_warn("%s: failed to request clock\n", __func__);
+		priv->clk = NULL;
+	}
+	clk_prepare_enable(priv->clk);
+
+	priv->clk_mdiv = of_clk_get_by_name(dn, "sw_switch_mdiv");
+	if (IS_ERR(priv->clk_mdiv)) {
+		pr_warn("%s: failed to request divider clock\n", __func__);
+		priv->clk_mdiv = NULL;
+	}
+	clk_prepare_enable(priv->clk_mdiv);
+
+	ret = bcm_sf2_sw_rst(priv);
+	if (ret) {
+		pr_err("%s: failed to reset switch\n", __func__);
+		goto out_clk;
+	}
+
+	/* Disable all interrupts and request them */
+	bcm_sf2_intr_disable(priv);
+
+	ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
+				"switch_0", priv);
+	if (ret < 0) {
+		pr_err("failed to request switch_0 IRQ\n");
+		goto out_clk;
+	}
+
+	ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
+				"switch_1", priv);
+	if (ret < 0) {
+		pr_err("failed to request switch_1 IRQ\n");
+		goto out_irq0;
+	}
+
+	/* Reset the MIB counters */
+	reg = core_readl(priv, CORE_GMNCFGCFG);
+	reg |= RST_MIB_CNT;
+	core_writel(priv, reg, CORE_GMNCFGCFG);
+	reg &= ~RST_MIB_CNT;
+	core_writel(priv, reg, CORE_GMNCFGCFG);
+
+	/* Get the maximum number of ports for this switch */
+	priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
+	if (priv->hw_params.num_ports > DSA_MAX_PORTS)
+		priv->hw_params.num_ports = DSA_MAX_PORTS;
+
+	/* Assume a single GPHY setup if we can't read that property */
+	if (of_property_read_u32(dn, "brcm,num-gphy",
+				&priv->hw_params.num_gphy))
+		priv->hw_params.num_gphy = 1;
+
+	/* Enable all valid ports and disable those unused */
+	for (port = 0; port < priv->hw_params.num_ports; port++) {
+		/* IMP port receives special treatment */
+		if ((1 << port) & ds->phys_port_mask)
+			bcm_sf2_port_setup(ds, port, NULL);
+		else if (dsa_is_cpu_port(ds, port))
+			bcm_sf2_imp_setup(ds, port);
+		else
+			bcm_sf2_port_disable(ds, port);
+	}
+
+	/* Enable ACB globally */
+	reg = acb_readl(priv, ACB_CONTROL);
+	reg |= ACB_EN | ACB_ALGORITHM;
+	acb_writel(priv, reg, ACB_CONTROL);
+
+	/* Include the pseudo-PHY address and the broadcast PHY address to
+	 * divert reads towards our workaround. This is only required for
+	 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
+	 * that we can use the regular SWITCH_MDIO master controller instead.
+	 *
+	 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
+	 * to have a 1:1 mapping between Port address and PHY address in order
+	 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
+	 * not what we want here, so we initialize phys_mii_mask 0 to always
+	 * utilize the "master" MDIO bus backed by "mdio-unimac".
+	 */
+	if (of_machine_is_compatible("brcm,bcm7445d0"))
+		ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
+	else
+		ds->phys_mii_mask = 0;
+
+	rev = reg_readl(priv, REG_SWITCH_REVISION);
+	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
+					SWITCH_TOP_REV_MASK;
+	priv->hw_params.core_rev = (rev & SF2_REV_MASK);
+
+	rev = reg_readl(priv, REG_PHY_REVISION);
+	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
+
+	pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
+		priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
+		priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
+		priv->core, priv->irq0, priv->irq1);
+
+	return 0;
+
+out_irq0:
+	free_irq(priv->irq0, priv);
+out_clk:
+	clk_disable_unprepare(priv->clk_mdiv);
+	clk_disable_unprepare(priv->clk);
+out_unmap:
+	base = &priv->core;
+	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
+		if (*base)
+			iounmap(*base);
+		base++;
+	}
+	return ret;
+}
+
+static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
+{
+	return 0;
+}
+
+static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+
+	/* The BCM7xxx PHY driver expects to find the integrated PHY revision
+	 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
+	 * the REG_PHY_REVISION register layout is.
+	 */
+
+	return priv->hw_params.gphy_rev;
+}
+
+static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
+					int regnum, u16 val)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	int ret = 0;
+	u32 reg;
+
+	reg = reg_readl(priv, REG_SWITCH_CNTRL);
+	reg |= MDIO_MASTER_SEL;
+	reg_writel(priv, reg, REG_SWITCH_CNTRL);
+
+	/* Page << 8 | offset */
+	reg = 0x70;
+	reg <<= 2;
+	core_writel(priv, addr, reg);
+
+	/* Page << 8 | offset */
+	reg = 0x80 << 8 | regnum << 1;
+	reg <<= 2;
+
+	if (op)
+		ret = core_readl(priv, reg);
+	else
+		core_writel(priv, val, reg);
+
+	reg = reg_readl(priv, REG_SWITCH_CNTRL);
+	reg &= ~MDIO_MASTER_SEL;
+	reg_writel(priv, reg, REG_SWITCH_CNTRL);
+
+	return ret & 0xffff;
+}
+
+static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
+{
+	/* Intercept reads from the MDIO broadcast address or Broadcom
+	 * pseudo-PHY address
+	 */
+	switch (addr) {
+	case 0:
+	case BRCM_PSEUDO_PHY_ADDR:
+		return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
+	default:
+		return 0xffff;
+	}
+}
+
+static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
+				u16 val)
+{
+	/* Intercept writes to the MDIO broadcast address or Broadcom
+	 * pseudo-PHY address
+	 */
+	switch (addr) {
+	case 0:
+	case BRCM_PSEUDO_PHY_ADDR:
+		bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
+		break;
+	}
+
+	return 0;
+}
+
+static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
+					struct phy_device *phydev)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 id_mode_dis = 0, port_mode;
+	const char *str = NULL;
+	u32 reg;
+
+	switch (phydev->interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+		str = "RGMII (no delay)";
+		id_mode_dis = 1;
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		if (!str)
+			str = "RGMII (TX delay)";
+		port_mode = EXT_GPHY;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+		str = "MII";
+		port_mode = EXT_EPHY;
+		break;
+	case PHY_INTERFACE_MODE_REVMII:
+		str = "Reverse MII";
+		port_mode = EXT_REVMII;
+		break;
+	default:
+		/* All other PHYs: internal and MoCA */
+		goto force_link;
+	}
+
+	/* If the link is down, just disable the interface to conserve power */
+	if (!phydev->link) {
+		reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
+		reg &= ~RGMII_MODE_EN;
+		reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
+		goto force_link;
+	}
+
+	/* Clear id_mode_dis bit, and the existing port mode, but
+	 * make sure we enable the RGMII block for data to pass
+	 */
+	reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
+	reg &= ~ID_MODE_DIS;
+	reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
+	reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
+
+	reg |= port_mode | RGMII_MODE_EN;
+	if (id_mode_dis)
+		reg |= ID_MODE_DIS;
+
+	if (phydev->pause) {
+		if (phydev->asym_pause)
+			reg |= TX_PAUSE_EN;
+		reg |= RX_PAUSE_EN;
+	}
+
+	reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
+
+	pr_info("Port %d configured for %s\n", port, str);
+
+force_link:
+	/* Force link settings detected from the PHY */
+	reg = SW_OVERRIDE;
+	switch (phydev->speed) {
+	case SPEED_1000:
+		reg |= SPDSTS_1000 << SPEED_SHIFT;
+		break;
+	case SPEED_100:
+		reg |= SPDSTS_100 << SPEED_SHIFT;
+		break;
+	}
+
+	if (phydev->link)
+		reg |= LINK_STS;
+	if (phydev->duplex == DUPLEX_FULL)
+		reg |= DUPLX_MODE;
+
+	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
+}
+
+static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
+					struct fixed_phy_status *status)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	u32 duplex, pause, speed;
+	u32 reg;
+
+	duplex = core_readl(priv, CORE_DUPSTS);
+	pause = core_readl(priv, CORE_PAUSESTS);
+	speed = core_readl(priv, CORE_SPDSTS);
+
+	speed >>= (port * SPDSTS_SHIFT);
+	speed &= SPDSTS_MASK;
+
+	status->link = 0;
+
+	/* Port 7 is special as we do not get link status from CORE_LNKSTS,
+	 * which means that we need to force the link at the port override
+	 * level to get the data to flow. We do use what the interrupt handler
+	 * did determine before.
+	 *
+	 * For the other ports, we just force the link status, since this is
+	 * a fixed PHY device.
+	 */
+	if (port == 7) {
+		status->link = priv->port_sts[port].link;
+		if (!status->link)
+			netif_carrier_off(ds->ports[port]);
+		status->duplex = 1;
+	} else {
+		status->link = 1;
+		status->duplex = !!(duplex & (1 << port));
+	}
+
+	reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
+	reg |= SW_OVERRIDE;
+	if (status->link)
+		reg |= LINK_STS;
+	else
+		reg &= ~LINK_STS;
+	core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
+
+	switch (speed) {
+	case SPDSTS_10:
+		status->speed = SPEED_10;
+		break;
+	case SPDSTS_100:
+		status->speed = SPEED_100;
+		break;
+	case SPDSTS_1000:
+		status->speed = SPEED_1000;
+		break;
+	}
+
+	if ((pause & (1 << port)) &&
+		(pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
+		status->asym_pause = 1;
+		status->pause = 1;
+	}
+
+	if (pause & (1 << port))
+		status->pause = 1;
+}
+
+static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int port;
+
+	bcm_sf2_intr_disable(priv);
+
+	/* Disable all ports physically present including the IMP
+	 * port, the other ones have already been disabled during
+	 * bcm_sf2_sw_setup
+	 */
+	for (port = 0; port < DSA_MAX_PORTS; port++) {
+		if ((1 << port) & ds->phys_port_mask ||
+			dsa_is_cpu_port(ds, port))
+			bcm_sf2_port_disable(ds, port);
+	}
+
+	if (!priv->wol_ports_mask)
+		clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static int bcm_sf2_sw_resume(struct dsa_switch *ds)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	unsigned int port;
+	int ret;
+
+	if (!priv->wol_ports_mask)
+		clk_prepare_enable(priv->clk);
+
+	ret = bcm_sf2_sw_rst(priv);
+	if (ret) {
+		pr_err("%s: failed to software reset switch\n", __func__);
+		return ret;
+	}
+
+	if (priv->hw_params.num_gphy == 1)
+		bcm_sf2_gphy_enable_set(ds, true);
+
+	for (port = 0; port < DSA_MAX_PORTS; port++) {
+		if ((1 << port) & ds->phys_port_mask)
+			bcm_sf2_port_setup(ds, port, NULL);
+		else if (dsa_is_cpu_port(ds, port))
+			bcm_sf2_imp_setup(ds, port);
+	}
+
+	return 0;
+}
+
+static void bcm_sf2_sw_shutdown(struct dsa_switch *ds)
+{
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+
+	/* For a kernel about to be kexec'd we want to keep the GPHY on
+	 * for a successful MDIO bus scan to occur. If we did turn off
+	 * the GPHY before, this will also power it back on.
+	 */
+	if (priv->hw_params.num_gphy == 1)
+		bcm_sf2_gphy_enable_set(ds, kexec_in_progress);
+}
+
+static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
+				struct ethtool_wolinfo *wol)
+{
+	struct net_device *p = ds->dst[ds->index].master_netdev;
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	struct ethtool_wolinfo pwol;
+
+	/* Get the parent device WoL settings */
+	p->ethtool_ops->get_wol(p, &pwol);
+
+	/* Advertise the parent device supported settings */
+	wol->supported = pwol.supported;
+	memset(&wol->sopass, 0, sizeof(wol->sopass));
+
+	if (pwol.wolopts & WAKE_MAGICSECURE)
+		memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
+
+	if (priv->wol_ports_mask & (1 << port))
+		wol->wolopts = pwol.wolopts;
+	else
+		wol->wolopts = 0;
+}
+
+static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
+				struct ethtool_wolinfo *wol)
+{
+	struct net_device *p = ds->dst[ds->index].master_netdev;
+	struct bcm_sf2_priv *priv = ds_to_priv(ds);
+	s8 cpu_port = ds->dst[ds->index].cpu_port;
+	struct ethtool_wolinfo pwol;
+
+	p->ethtool_ops->get_wol(p, &pwol);
+	if (wol->wolopts & ~pwol.supported)
+		return -EINVAL;
+
+	if (wol->wolopts)
+		priv->wol_ports_mask |= (1 << port);
+	else
+		priv->wol_ports_mask &= ~(1 << port);
+
+	/* If we have at least one port enabled, make sure the CPU port
+	 * is also enabled. If the CPU port is the last one enabled, we disable
+	 * it since this configuration does not make sense.
+	 */
+	if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
+		priv->wol_ports_mask |= (1 << cpu_port);
+	else
+		priv->wol_ports_mask &= ~(1 << cpu_port);
+
+	return p->ethtool_ops->set_wol(p, wol);
+}
+
+static struct dsa_switch_driver bcm_sf2_switch_driver = {
+	.tag_protocol		= htons(ETH_P_BRCMTAG),
+	.priv_size		= sizeof(struct bcm_sf2_priv),
+	.probe			= bcm_sf2_sw_probe,
+	.setup			= bcm_sf2_sw_setup,
+	.set_addr		= bcm_sf2_sw_set_addr,
+	.get_phy_flags		= bcm_sf2_sw_get_phy_flags,
+	.phy_read		= bcm_sf2_sw_phy_read,
+	.phy_write		= bcm_sf2_sw_phy_write,
+	.get_strings		= bcm_sf2_sw_get_strings,
+	.get_ethtool_stats	= bcm_sf2_sw_get_ethtool_stats,
+	.get_sset_count		= bcm_sf2_sw_get_sset_count,
+	.adjust_link		= bcm_sf2_sw_adjust_link,
+	.fixed_link_update	= bcm_sf2_sw_fixed_link_update,
+	.suspend		= bcm_sf2_sw_suspend,
+	.resume			= bcm_sf2_sw_resume,
+	.shutdown		= bcm_sf2_sw_shutdown,
+	.get_wol		= bcm_sf2_sw_get_wol,
+	.set_wol		= bcm_sf2_sw_set_wol,
+	.port_enable		= bcm_sf2_port_setup,
+	.port_disable		= bcm_sf2_port_disable,
+	.get_eee		= bcm_sf2_sw_get_eee,
+	.set_eee		= bcm_sf2_sw_set_eee,
+	.br_join		= bcm_sf2_sw_br_join,
+	.br_leave		= bcm_sf2_sw_br_leave,
+	.br_set_stp_state	= bcm_sf2_sw_br_set_stp_state,
+};
+
+static int __init bcm_sf2_init(void)
+{
+	register_switch_driver(&bcm_sf2_switch_driver);
+
+	return 0;
+}
+module_init(bcm_sf2_init);
+
+static void __exit bcm_sf2_exit(void)
+{
+	unregister_switch_driver(&bcm_sf2_switch_driver);
+}
+module_exit(bcm_sf2_exit);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:brcm-sf2");
diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h
new file mode 100644
index 000000000000..eb7c71b73478
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2.h
@@ -0,0 +1,161 @@
+/*
+ * Broadcom Starfighter2 private context
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __BCM_SF2_H
+#define __BCM_SF2_H
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+
+#include <net/dsa.h>
+
+#include "bcm_sf2_regs.h"
+
+struct bcm_sf2_hw_params {
+	u16	top_rev;
+	u16	core_rev;
+	u16	gphy_rev;
+	u32	num_gphy;
+	u8	num_acb_queue;
+	u8	num_rgmii;
+	u8	num_ports;
+	u8	fcb_pause_override:1;
+	u8	acb_packets_inflight:1;
+};
+
+#define BCM_SF2_REGS_NAME {\
+	"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
+}
+#define BCM_SF2_REGS_NUM	6
+
+struct bcm_sf2_port_status {
+	unsigned int link;
+
+	bool enabled;
+
+	struct ethtool_eee eee;
+
+	u32 vlan_ctl_mask;
+};
+
+struct bcm_sf2_priv {
+	/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
+	void __iomem			*core;
+	void __iomem			*reg;
+	void __iomem			*intrl2_0;
+	void __iomem			*intrl2_1;
+	void __iomem			*fcb;
+	void __iomem			*acb;
+	spinlock_t			indir_lock;
+
+	int				irq0;
+	int				irq1;
+	u32				irq0_stat;
+	u32				irq0_mask;
+	u32				irq1_stat;
+	u32				irq1_mask;
+
+	struct mutex			stats_mutex;
+
+	struct bcm_sf2_hw_params	hw_params;
+
+	struct bcm_sf2_port_status	port_sts[DSA_MAX_PORTS];
+
+	/* Mask of ports enabled for Wake-on-LAN */
+	u32				wol_ports_mask;
+	struct clk			*clk;
+	struct clk			*clk_mdiv;
+};
+
+static inline struct bcm_sf2_priv *ds_to_priv(struct dsa_switch *ds)
+{
+	return (void *)(ds + 1);
+}
+
+struct bcm_sf2_hw_stats {
+	const char	*string;
+	u16		reg;
+	u8		sizeof_stat;
+};
+
+#define SF2_IO_MACRO(name) \
+static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)	\
+{									\
+	return __raw_readl(priv->name + off);				\
+}									\
+static inline void name##_writel(struct bcm_sf2_priv *priv,		\
+				  u32 val, u32 off)			\
+{									\
+	__raw_writel(val, priv->name + off);				\
+}									\
+
+/* Accesses to 64-bits register requires us to latch the hi/lo pairs
+ * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
+ * spinlock is automatically grabbed and released to provide relative
+ * atomiticy with latched reads/writes.
+ *
+ * For reads, we first need to read the regular 32-bits register, and then
+ * issue a read to the REG_DIR_DATA_READ register and assemble the 64-bits
+ * quantity.
+ *
+ * For writes, it is the opposite, we need to write to REG_DIR_DATA_WRITE and
+ * then to the regular 32-bits register.
+ */
+#define SF2_IO64_MACRO(name) \
+static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off)	\
+{									\
+	u32 indir, dir;							\
+	spin_lock(&priv->indir_lock);					\
+	dir = __raw_readl(priv->name + off);				\
+	indir = reg_readl(priv, REG_DIR_DATA_READ);			\
+	spin_unlock(&priv->indir_lock);					\
+	return (u64)indir << 32 | dir;					\
+}									\
+static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off,	\
+							u64 val)	\
+{									\
+	spin_lock(&priv->indir_lock);					\
+	reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);	\
+	__raw_writel(lower_32_bits(val), priv->name + off);		\
+	spin_unlock(&priv->indir_lock);					\
+}
+
+#define SWITCH_INTR_L2(which)						\
+static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
+						u32 mask)		\
+{									\
+	priv->irq##which##_mask &= ~(mask);				\
+	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);	\
+}									\
+static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
+						u32 mask)		\
+{									\
+	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);	\
+	priv->irq##which##_mask |= (mask);				\
+}									\
+
+SF2_IO_MACRO(core);
+SF2_IO_MACRO(reg);
+SF2_IO64_MACRO(core);
+SF2_IO_MACRO(intrl2_0);
+SF2_IO_MACRO(intrl2_1);
+SF2_IO_MACRO(fcb);
+SF2_IO_MACRO(acb);
+
+SWITCH_INTR_L2(0);
+SWITCH_INTR_L2(1);
+
+#endif /* __BCM_SF2_H */
diff --git a/drivers/net/dsa/bcm_sf2_regs.h b/drivers/net/dsa/bcm_sf2_regs.h
new file mode 100644
index 000000000000..8bff2549ddaf
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2_regs.h
@@ -0,0 +1,272 @@
+/*
+ * Broadcom Starfighter 2 switch register defines
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __BCM_SF2_REGS_H
+#define __BCM_SF2_REGS_H
+
+
+/* Register set relative to 'REG' */
+#define REG_SWITCH_CNTRL		0x00
+#define  MDIO_MASTER_SEL		(1 << 0)
+
+#define REG_SWITCH_STATUS		0x04
+#define REG_DIR_DATA_WRITE		0x08
+#define REG_DIR_DATA_READ		0x0C
+
+#define REG_SWITCH_REVISION		0x18
+#define  SF2_REV_MASK			0xffff
+#define  SWITCH_TOP_REV_SHIFT		16
+#define  SWITCH_TOP_REV_MASK		0xffff
+
+#define REG_PHY_REVISION		0x1C
+#define  PHY_REVISION_MASK		0xffff
+
+#define REG_SPHY_CNTRL			0x2C
+#define  IDDQ_BIAS			(1 << 0)
+#define  EXT_PWR_DOWN			(1 << 1)
+#define  FORCE_DLL_EN			(1 << 2)
+#define  IDDQ_GLOBAL_PWR		(1 << 3)
+#define  CK25_DIS			(1 << 4)
+#define  PHY_RESET			(1 << 5)
+#define  PHY_PHYAD_SHIFT		8
+#define  PHY_PHYAD_MASK			0x1F
+
+#define REG_RGMII_0_BASE		0x34
+#define REG_RGMII_CNTRL			0x00
+#define REG_RGMII_IB_STATUS		0x04
+#define REG_RGMII_RX_CLOCK_DELAY_CNTRL	0x08
+#define REG_RGMII_CNTRL_SIZE		0x0C
+#define REG_RGMII_CNTRL_P(x)		(REG_RGMII_0_BASE + \
+					((x) * REG_RGMII_CNTRL_SIZE))
+/* Relative to REG_RGMII_CNTRL */
+#define  RGMII_MODE_EN			(1 << 0)
+#define  ID_MODE_DIS			(1 << 1)
+#define  PORT_MODE_SHIFT		2
+#define  INT_EPHY			(0 << PORT_MODE_SHIFT)
+#define  INT_GPHY			(1 << PORT_MODE_SHIFT)
+#define  EXT_EPHY			(2 << PORT_MODE_SHIFT)
+#define  EXT_GPHY			(3 << PORT_MODE_SHIFT)
+#define  EXT_REVMII			(4 << PORT_MODE_SHIFT)
+#define  PORT_MODE_MASK			0x7
+#define  RVMII_REF_SEL			(1 << 5)
+#define  RX_PAUSE_EN			(1 << 6)
+#define  TX_PAUSE_EN			(1 << 7)
+#define  TX_CLK_STOP_EN			(1 << 8)
+#define  LPI_COUNT_SHIFT		9
+#define  LPI_COUNT_MASK			0x3F
+
+#define REG_LED_CNTRL_BASE		0x90
+#define REG_LED_CNTRL(x)		(REG_LED_CNTRL_BASE + (x) * 4)
+#define  SPDLNK_SRC_SEL			(1 << 24)
+
+/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
+#define INTRL2_CPU_STATUS		0x00
+#define INTRL2_CPU_SET			0x04
+#define INTRL2_CPU_CLEAR		0x08
+#define INTRL2_CPU_MASK_STATUS		0x0c
+#define INTRL2_CPU_MASK_SET		0x10
+#define INTRL2_CPU_MASK_CLEAR		0x14
+
+/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
+#define P_LINK_UP_IRQ(x)		(1 << (0 + (x)))
+#define P_LINK_DOWN_IRQ(x)		(1 << (1 + (x)))
+#define P_ENERGY_ON_IRQ(x)		(1 << (2 + (x)))
+#define P_ENERGY_OFF_IRQ(x)		(1 << (3 + (x)))
+#define P_GPHY_IRQ(x)			(1 << (4 + (x)))
+#define P_NUM_IRQ			5
+#define P_IRQ_MASK(x)			(P_LINK_UP_IRQ((x)) | \
+					 P_LINK_DOWN_IRQ((x)) | \
+					 P_ENERGY_ON_IRQ((x)) | \
+					 P_ENERGY_OFF_IRQ((x)) | \
+					 P_GPHY_IRQ((x)))
+
+/* INTRL2_0 interrupt sources */
+#define P0_IRQ_OFF			0
+#define MEM_DOUBLE_IRQ			(1 << 5)
+#define EEE_LPI_IRQ			(1 << 6)
+#define P5_CPU_WAKE_IRQ			(1 << 7)
+#define P8_CPU_WAKE_IRQ			(1 << 8)
+#define P7_CPU_WAKE_IRQ			(1 << 9)
+#define IEEE1588_IRQ			(1 << 10)
+#define MDIO_ERR_IRQ			(1 << 11)
+#define MDIO_DONE_IRQ			(1 << 12)
+#define GISB_ERR_IRQ			(1 << 13)
+#define UBUS_ERR_IRQ			(1 << 14)
+#define FAILOVER_ON_IRQ			(1 << 15)
+#define FAILOVER_OFF_IRQ		(1 << 16)
+#define TCAM_SOFT_ERR_IRQ		(1 << 17)
+
+/* INTRL2_1 interrupt sources */
+#define P7_IRQ_OFF			0
+#define P_IRQ_OFF(x)			((6 - (x)) * P_NUM_IRQ)
+
+/* Register set relative to 'ACB' */
+#define ACB_CONTROL			0x00
+#define  ACB_EN				(1 << 0)
+#define  ACB_ALGORITHM			(1 << 1)
+
+#define ACB_QUEUE_0_CFG			0x08
+#define  XOFF_THRESHOLD_MASK		0x7ff
+#define  XON_EN				(1 << 11)
+#define  TOTAL_XOFF_THRESHOLD_SHIFT	12
+#define  TOTAL_XOFF_THRESHOLD_MASK	0x7ff
+#define  TOTAL_XOFF_EN			(1 << 23)
+#define  TOTAL_XON_EN			(1 << 24)
+#define  PKTLEN_SHIFT			25
+#define  PKTLEN_MASK			0x3f
+#define ACB_QUEUE_CFG(x)		(ACB_QUEUE_0_CFG + (x * 0x4))
+
+/* Register set relative to 'CORE' */
+#define CORE_G_PCTL_PORT0		0x00000
+#define CORE_G_PCTL_PORT(x)		(CORE_G_PCTL_PORT0 + (x * 0x4))
+#define CORE_IMP_CTL			0x00020
+#define  RX_DIS				(1 << 0)
+#define  TX_DIS				(1 << 1)
+#define  RX_BCST_EN			(1 << 2)
+#define  RX_MCST_EN			(1 << 3)
+#define  RX_UCST_EN			(1 << 4)
+#define  G_MISTP_STATE_SHIFT		5
+#define  G_MISTP_NO_STP			(0 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_DIS_STATE		(1 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_BLOCK_STATE		(2 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_LISTEN_STATE		(3 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_LEARN_STATE		(4 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_FWD_STATE		(5 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_STATE_MASK		0x7
+
+#define CORE_SWMODE			0x0002c
+#define  SW_FWDG_MODE			(1 << 0)
+#define  SW_FWDG_EN			(1 << 1)
+#define  RTRY_LMT_DIS			(1 << 2)
+
+#define CORE_STS_OVERRIDE_IMP		0x00038
+#define  GMII_SPEED_UP_2G		(1 << 6)
+#define  MII_SW_OR			(1 << 7)
+
+#define CORE_NEW_CTRL			0x00084
+#define  IP_MC				(1 << 0)
+#define  OUTRANGEERR_DISCARD		(1 << 1)
+#define  INRANGEERR_DISCARD		(1 << 2)
+#define  CABLE_DIAG_LEN			(1 << 3)
+#define  OVERRIDE_AUTO_PD_WAR		(1 << 4)
+#define  EN_AUTO_PD_WAR			(1 << 5)
+#define  UC_FWD_EN			(1 << 6)
+#define  MC_FWD_EN			(1 << 7)
+
+#define CORE_SWITCH_CTRL		0x00088
+#define  MII_DUMB_FWDG_EN		(1 << 6)
+
+#define CORE_SFT_LRN_CTRL		0x000f8
+#define  SW_LEARN_CNTL(x)		(1 << (x))
+
+#define CORE_STS_OVERRIDE_GMIIP_PORT(x)	(0x160 + (x) * 4)
+#define  LINK_STS			(1 << 0)
+#define  DUPLX_MODE			(1 << 1)
+#define  SPEED_SHIFT			2
+#define  SPEED_MASK			0x3
+#define  RXFLOW_CNTL			(1 << 4)
+#define  TXFLOW_CNTL			(1 << 5)
+#define  SW_OVERRIDE			(1 << 6)
+
+#define CORE_WATCHDOG_CTRL		0x001e4
+#define  SOFTWARE_RESET			(1 << 7)
+#define  EN_CHIP_RST			(1 << 6)
+#define  EN_SW_RESET			(1 << 4)
+
+#define CORE_FAST_AGE_CTRL		0x00220
+#define  EN_FAST_AGE_STATIC		(1 << 0)
+#define  EN_AGE_DYNAMIC			(1 << 1)
+#define  EN_AGE_PORT			(1 << 2)
+#define  EN_AGE_VLAN			(1 << 3)
+#define  EN_AGE_SPT			(1 << 4)
+#define  EN_AGE_MCAST			(1 << 5)
+#define  FAST_AGE_STR_DONE		(1 << 7)
+
+#define CORE_FAST_AGE_PORT		0x00224
+#define  AGE_PORT_MASK			0xf
+
+#define CORE_FAST_AGE_VID		0x00228
+#define  AGE_VID_MASK			0x3fff
+
+#define CORE_LNKSTS			0x00400
+#define  LNK_STS_MASK			0x1ff
+
+#define CORE_SPDSTS			0x00410
+#define  SPDSTS_10			0
+#define  SPDSTS_100			1
+#define  SPDSTS_1000			2
+#define  SPDSTS_SHIFT			2
+#define  SPDSTS_MASK			0x3
+
+#define CORE_DUPSTS			0x00420
+#define  CORE_DUPSTS_MASK		0x1ff
+
+#define CORE_PAUSESTS			0x00428
+#define  PAUSESTS_TX_PAUSE_SHIFT	9
+
+#define CORE_GMNCFGCFG			0x0800
+#define  RST_MIB_CNT			(1 << 0)
+#define  RXBPDU_EN			(1 << 1)
+
+#define CORE_IMP0_PRT_ID		0x0804
+
+#define CORE_BRCM_HDR_CTRL		0x0080c
+#define  BRCM_HDR_EN_P8			(1 << 0)
+#define  BRCM_HDR_EN_P5			(1 << 1)
+#define  BRCM_HDR_EN_P7			(1 << 2)
+
+#define CORE_BRCM_HDR_CTRL2		0x0828
+
+#define CORE_HL_PRTC_CTRL		0x0940
+#define  ARP_EN				(1 << 0)
+#define  RARP_EN			(1 << 1)
+#define  DHCP_EN			(1 << 2)
+#define  ICMPV4_EN			(1 << 3)
+#define  ICMPV6_EN			(1 << 4)
+#define  ICMPV6_FWD_MODE		(1 << 5)
+#define  IGMP_DIP_EN			(1 << 8)
+#define  IGMP_RPTLVE_EN			(1 << 9)
+#define  IGMP_RTPLVE_FWD_MODE		(1 << 10)
+#define  IGMP_QRY_EN			(1 << 11)
+#define  IGMP_QRY_FWD_MODE		(1 << 12)
+#define  IGMP_UKN_EN			(1 << 13)
+#define  IGMP_UKN_FWD_MODE		(1 << 14)
+#define  MLD_RPTDONE_EN			(1 << 15)
+#define  MLD_RPTDONE_FWD_MODE		(1 << 16)
+#define  MLD_QRY_EN			(1 << 17)
+#define  MLD_QRY_FWD_MODE		(1 << 18)
+
+#define CORE_RST_MIB_CNT_EN		0x0950
+
+#define CORE_BRCM_HDR_RX_DIS		0x0980
+#define CORE_BRCM_HDR_TX_DIS		0x0988
+
+#define CORE_MEM_PSM_VDD_CTRL		0x2380
+#define  P_TXQ_PSM_VDD_SHIFT		2
+#define  P_TXQ_PSM_VDD_MASK		0x3
+#define  P_TXQ_PSM_VDD(x)		(P_TXQ_PSM_VDD_MASK << \
+					((x) * P_TXQ_PSM_VDD_SHIFT))
+
+#define	CORE_P0_MIB_OFFSET		0x8000
+#define P_MIB_SIZE			0x400
+#define CORE_P_MIB_OFFSET(x)		(CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
+
+#define CORE_PORT_VLAN_CTL_PORT(x)	(0xc400 + ((x) * 0x8))
+#define  PORT_VLAN_CTRL_MASK		0x1ff
+
+#define CORE_TXQ_THD_PAUSE_QN_PORT_0	0x2c80
+#define  TXQ_PAUSE_THD_MASK		0x7ff
+#define CORE_TXQ_THD_PAUSE_QN_PORT(x)	(CORE_TXQ_THD_PAUSE_QN_PORT_0 + \
+					(x) * 0x8)
+
+#define CORE_EEE_EN_CTRL		0x24800
+#define CORE_EEE_LPI_INDICATE		0x24810
+
+#endif /* __BCM_SF2_REGS_H */
diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig
index 3f97d9fd0a71..154a6ace7107 100644
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig
@@ -139,4 +139,16 @@ config BGMAC
 	  In case of using this driver on BCM4706 it's also requires to enable
 	  BCMA_DRIVER_GMAC_CMN to make it work.
 
+config SYSTEM_PORT
+	tristate "Broadcom System Port Ethernet support"
+	depends on BRCMSTB
+	default y
+	select PHYLIB
+	select FIXED_PHY
+	---help---
+	  This driver supports the Broadcom System Port Ethernet controller
+	  found in Broadcom BCM7xxx ARM-based Set Top Box platforms. To
+	  compile this driver as a module, choose M here: the module
+	  will be called bcmsysport. This is recommended.
+
 endif # NET_VENDOR_BROADCOM
diff --git a/drivers/net/ethernet/broadcom/Makefile b/drivers/net/ethernet/broadcom/Makefile
index 68efa1a3fb88..c7eaa3153d09 100644
--- a/drivers/net/ethernet/broadcom/Makefile
+++ b/drivers/net/ethernet/broadcom/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_BNX2X) += bnx2x/
 obj-$(CONFIG_SB1250_MAC) += sb1250-mac.o
 obj-$(CONFIG_TIGON3) += tg3.o
 obj-$(CONFIG_BGMAC) += bgmac.o
+obj-$(CONFIG_BCMGENET) += genet/
+obj-$(CONFIG_SYSTEM_PORT) += bcmsysport.o
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c
new file mode 100644
index 000000000000..a459c25b8ce5
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -0,0 +1,2106 @@
+/*
+ * Broadcom BCM7xxx System Port Ethernet MAC driver
+ *
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/clk.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+
+#include "bcmsysport.h"
+
+/* I/O accessors register helpers */
+#define BCM_SYSPORT_IO_MACRO(name, offset) \
+static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off)	\
+{									\
+	u32 reg = __raw_readl(priv->base + offset + off);		\
+	return reg;							\
+}									\
+static inline void name##_writel(struct bcm_sysport_priv *priv,		\
+				  u32 val, u32 off)			\
+{									\
+	__raw_writel(val, priv->base + offset + off);			\
+}									\
+
+BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
+BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
+BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
+BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
+BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET);
+BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
+BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
+BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
+BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
+BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
+
+/* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
+ * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
+  */
+#define BCM_SYSPORT_INTR_L2(which)	\
+static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
+						u32 mask)		\
+{									\
+	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);	\
+	priv->irq##which##_mask &= ~(mask);				\
+}									\
+static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
+						u32 mask)		\
+{									\
+	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);	\
+	priv->irq##which##_mask |= (mask);				\
+}									\
+
+BCM_SYSPORT_INTR_L2(0)
+BCM_SYSPORT_INTR_L2(1)
+
+/* Register accesses to GISB/RBUS registers are expensive (few hundred
+ * nanoseconds), so keep the check for 64-bits explicit here to save
+ * one register write per-packet on 32-bits platforms.
+ */
+static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
+				     void __iomem *d,
+				     dma_addr_t addr)
+{
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
+				d + DESC_ADDR_HI_STATUS_LEN);
+#endif
+	writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
+}
+
+static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
+						struct dma_desc *desc,
+						unsigned int port)
+{
+	/* Ports are latched, so write upper address first */
+	tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
+	tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
+}
+
+/* Ethtool operations */
+static int bcm_sysport_set_settings(struct net_device *dev,
+				    struct ethtool_cmd *cmd)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	return phy_ethtool_sset(priv->phydev, cmd);
+}
+
+static int bcm_sysport_get_settings(struct net_device *dev,
+				    struct ethtool_cmd *cmd)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	return phy_ethtool_gset(priv->phydev, cmd);
+}
+
+static int bcm_sysport_set_rx_csum(struct net_device *dev,
+				   netdev_features_t wanted)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
+	reg = rxchk_readl(priv, RXCHK_CONTROL);
+	if (priv->rx_chk_en)
+		reg |= RXCHK_EN;
+	else
+		reg &= ~RXCHK_EN;
+
+	/* If UniMAC forwards CRC, we need to skip over it to get
+	 * a valid CHK bit to be set in the per-packet status word
+	 */
+	if (priv->rx_chk_en && priv->crc_fwd)
+		reg |= RXCHK_SKIP_FCS;
+	else
+		reg &= ~RXCHK_SKIP_FCS;
+
+	/* If Broadcom tags are enabled (e.g: using a switch), make
+	 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
+	 * tag after the Ethernet MAC Source Addresss.
+	 */
+	if (netdev_uses_brcm_tags(dev))
+		reg |= RXCHK_BRCM_TAG_EN;
+	else
+		reg &= ~RXCHK_BRCM_TAG_EN;
+
+	rxchk_writel(priv, reg, RXCHK_CONTROL);
+
+	return 0;
+}
+
+static int bcm_sysport_set_tx_csum(struct net_device *dev,
+					netdev_features_t wanted)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	/* Hardware transmit checksum requires us to enable the Transmit status
+	 * block prepended to the packet contents
+	 */
+	priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
+	reg = tdma_readl(priv, TDMA_CONTROL);
+	if (priv->tsb_en)
+		reg |= TSB_EN;
+	else
+		reg &= ~TSB_EN;
+	tdma_writel(priv, reg, TDMA_CONTROL);
+
+	return 0;
+}
+
+static int bcm_sysport_set_features(struct net_device *dev,
+				    netdev_features_t features)
+{
+	netdev_features_t changed = features ^ dev->features;
+	netdev_features_t wanted = dev->wanted_features;
+	int ret = 0;
+
+	if (changed & NETIF_F_RXCSUM)
+		ret = bcm_sysport_set_rx_csum(dev, wanted);
+	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
+		ret = bcm_sysport_set_tx_csum(dev, wanted);
+
+	return ret;
+}
+
+/* Hardware counters must be kept in sync because the order/offset
+ * is important here (order in structure declaration = order in hardware)
+ */
+static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
+	/* general stats */
+	STAT_NETDEV(rx_packets),
+	STAT_NETDEV(tx_packets),
+	STAT_NETDEV(rx_bytes),
+	STAT_NETDEV(tx_bytes),
+	STAT_NETDEV(rx_errors),
+	STAT_NETDEV(tx_errors),
+	STAT_NETDEV(rx_dropped),
+	STAT_NETDEV(tx_dropped),
+	STAT_NETDEV(multicast),
+	/* UniMAC RSV counters */
+	STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
+	STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
+	STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
+	STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
+	STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
+	STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
+	STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
+	STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
+	STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
+	STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
+	STAT_MIB_RX("rx_pkts", mib.rx.pkt),
+	STAT_MIB_RX("rx_bytes", mib.rx.bytes),
+	STAT_MIB_RX("rx_multicast", mib.rx.mca),
+	STAT_MIB_RX("rx_broadcast", mib.rx.bca),
+	STAT_MIB_RX("rx_fcs", mib.rx.fcs),
+	STAT_MIB_RX("rx_control", mib.rx.cf),
+	STAT_MIB_RX("rx_pause", mib.rx.pf),
+	STAT_MIB_RX("rx_unknown", mib.rx.uo),
+	STAT_MIB_RX("rx_align", mib.rx.aln),
+	STAT_MIB_RX("rx_outrange", mib.rx.flr),
+	STAT_MIB_RX("rx_code", mib.rx.cde),
+	STAT_MIB_RX("rx_carrier", mib.rx.fcr),
+	STAT_MIB_RX("rx_oversize", mib.rx.ovr),
+	STAT_MIB_RX("rx_jabber", mib.rx.jbr),
+	STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
+	STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
+	STAT_MIB_RX("rx_unicast", mib.rx.uc),
+	STAT_MIB_RX("rx_ppp", mib.rx.ppp),
+	STAT_MIB_RX("rx_crc", mib.rx.rcrc),
+	/* UniMAC TSV counters */
+	STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
+	STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
+	STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
+	STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
+	STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
+	STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
+	STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
+	STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
+	STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
+	STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
+	STAT_MIB_TX("tx_pkts", mib.tx.pkts),
+	STAT_MIB_TX("tx_multicast", mib.tx.mca),
+	STAT_MIB_TX("tx_broadcast", mib.tx.bca),
+	STAT_MIB_TX("tx_pause", mib.tx.pf),
+	STAT_MIB_TX("tx_control", mib.tx.cf),
+	STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
+	STAT_MIB_TX("tx_oversize", mib.tx.ovr),
+	STAT_MIB_TX("tx_defer", mib.tx.drf),
+	STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
+	STAT_MIB_TX("tx_single_col", mib.tx.scl),
+	STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
+	STAT_MIB_TX("tx_late_col", mib.tx.lcl),
+	STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
+	STAT_MIB_TX("tx_frags", mib.tx.frg),
+	STAT_MIB_TX("tx_total_col", mib.tx.ncl),
+	STAT_MIB_TX("tx_jabber", mib.tx.jbr),
+	STAT_MIB_TX("tx_bytes", mib.tx.bytes),
+	STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
+	STAT_MIB_TX("tx_unicast", mib.tx.uc),
+	/* UniMAC RUNT counters */
+	STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
+	STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
+	STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
+	STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
+	/* RXCHK misc statistics */
+	STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
+	STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
+			RXCHK_OTHER_DISC_CNTR),
+	/* RBUF misc statistics */
+	STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
+	STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
+	STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
+	STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
+	STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
+};
+
+#define BCM_SYSPORT_STATS_LEN	ARRAY_SIZE(bcm_sysport_gstrings_stats)
+
+static void bcm_sysport_get_drvinfo(struct net_device *dev,
+				    struct ethtool_drvinfo *info)
+{
+	strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
+	strlcpy(info->version, "0.1", sizeof(info->version));
+	strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
+	info->n_stats = BCM_SYSPORT_STATS_LEN;
+}
+
+static u32 bcm_sysport_get_msglvl(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	return priv->msg_enable;
+}
+
+static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	priv->msg_enable = enable;
+}
+
+static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
+{
+	switch (string_set) {
+	case ETH_SS_STATS:
+		return BCM_SYSPORT_STATS_LEN;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static void bcm_sysport_get_strings(struct net_device *dev,
+					u32 stringset, u8 *data)
+{
+	int i;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
+			memcpy(data + i * ETH_GSTRING_LEN,
+				bcm_sysport_gstrings_stats[i].stat_string,
+				ETH_GSTRING_LEN);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
+{
+	int i, j = 0;
+
+	for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
+		const struct bcm_sysport_stats *s;
+		u8 offset = 0;
+		u32 val = 0;
+		char *p;
+
+		s = &bcm_sysport_gstrings_stats[i];
+		switch (s->type) {
+		case BCM_SYSPORT_STAT_NETDEV:
+		case BCM_SYSPORT_STAT_SOFT:
+			continue;
+		case BCM_SYSPORT_STAT_MIB_RX:
+		case BCM_SYSPORT_STAT_MIB_TX:
+		case BCM_SYSPORT_STAT_RUNT:
+			if (s->type != BCM_SYSPORT_STAT_MIB_RX)
+				offset = UMAC_MIB_STAT_OFFSET;
+			val = umac_readl(priv, UMAC_MIB_START + j + offset);
+			break;
+		case BCM_SYSPORT_STAT_RXCHK:
+			val = rxchk_readl(priv, s->reg_offset);
+			if (val == ~0)
+				rxchk_writel(priv, 0, s->reg_offset);
+			break;
+		case BCM_SYSPORT_STAT_RBUF:
+			val = rbuf_readl(priv, s->reg_offset);
+			if (val == ~0)
+				rbuf_writel(priv, 0, s->reg_offset);
+			break;
+		}
+
+		j += s->stat_sizeof;
+		p = (char *)priv + s->stat_offset;
+		*(u32 *)p = val;
+	}
+
+	netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
+}
+
+static void bcm_sysport_get_stats(struct net_device *dev,
+				  struct ethtool_stats *stats,
+				  u64 *data)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	int i;
+
+	if (netif_running(dev))
+		bcm_sysport_update_mib_counters(priv);
+
+	for (i =  0; i < BCM_SYSPORT_STATS_LEN; i++) {
+		const struct bcm_sysport_stats *s;
+		char *p;
+
+		s = &bcm_sysport_gstrings_stats[i];
+		if (s->type == BCM_SYSPORT_STAT_NETDEV)
+			p = (char *)&dev->stats;
+		else
+			p = (char *)priv;
+		p += s->stat_offset;
+		data[i] = *(u32 *)p;
+	}
+}
+
+static void bcm_sysport_get_wol(struct net_device *dev,
+				struct ethtool_wolinfo *wol)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
+	wol->wolopts = priv->wolopts;
+
+	if (!(priv->wolopts & WAKE_MAGICSECURE))
+		return;
+
+	/* Return the programmed SecureOn password */
+	reg = umac_readl(priv, UMAC_PSW_MS);
+	put_unaligned_be16(reg, &wol->sopass[0]);
+	reg = umac_readl(priv, UMAC_PSW_LS);
+	put_unaligned_be32(reg, &wol->sopass[2]);
+}
+
+static int bcm_sysport_set_wol(struct net_device *dev,
+				struct ethtool_wolinfo *wol)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
+
+	if (!device_can_wakeup(kdev))
+		return -ENOTSUPP;
+
+	if (wol->wolopts & ~supported)
+		return -EINVAL;
+
+	/* Program the SecureOn password */
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
+				UMAC_PSW_MS);
+		umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
+				UMAC_PSW_LS);
+	}
+
+	/* Flag the device and relevant IRQ as wakeup capable */
+	if (wol->wolopts) {
+		device_set_wakeup_enable(kdev, 1);
+		if (priv->wol_irq_disabled)
+			enable_irq_wake(priv->wol_irq);
+		priv->wol_irq_disabled = 0;
+	} else {
+		device_set_wakeup_enable(kdev, 0);
+		/* Avoid unbalanced disable_irq_wake calls */
+		if (!priv->wol_irq_disabled)
+			disable_irq_wake(priv->wol_irq);
+		priv->wol_irq_disabled = 1;
+	}
+
+	priv->wolopts = wol->wolopts;
+
+	return 0;
+}
+
+static int bcm_sysport_get_coalesce(struct net_device *dev,
+				    struct ethtool_coalesce *ec)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
+
+	ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
+	ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
+
+	reg = rdma_readl(priv, RDMA_MBDONE_INTR);
+
+	ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
+	ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
+
+	return 0;
+}
+
+static int bcm_sysport_set_coalesce(struct net_device *dev,
+				    struct ethtool_coalesce *ec)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	u32 reg;
+
+	/* Base system clock is 125Mhz, DMA timeout is this reference clock
+	 * divided by 1024, which yield roughly 8.192 us, our maximum value has
+	 * to fit in the RING_TIMEOUT_MASK (16 bits).
+	 */
+	if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
+	    ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
+	    ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
+	    ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
+		return -EINVAL;
+
+	if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
+	    (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
+		return -EINVAL;
+
+	for (i = 0; i < dev->num_tx_queues; i++) {
+		reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
+		reg &= ~(RING_INTR_THRESH_MASK |
+			 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
+		reg |= ec->tx_max_coalesced_frames;
+		reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
+			 RING_TIMEOUT_SHIFT;
+		tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
+	}
+
+	reg = rdma_readl(priv, RDMA_MBDONE_INTR);
+	reg &= ~(RDMA_INTR_THRESH_MASK |
+		 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
+	reg |= ec->rx_max_coalesced_frames;
+	reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) <<
+			    RDMA_TIMEOUT_SHIFT;
+	rdma_writel(priv, reg, RDMA_MBDONE_INTR);
+
+	return 0;
+}
+
+static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
+{
+	dev_kfree_skb_any(cb->skb);
+	cb->skb = NULL;
+	dma_unmap_addr_set(cb, dma_addr, 0);
+}
+
+static int bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
+				 struct bcm_sysport_cb *cb)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct net_device *ndev = priv->netdev;
+	dma_addr_t mapping;
+	int ret;
+
+	cb->skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
+	if (!cb->skb) {
+		netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
+		return -ENOMEM;
+	}
+
+	mapping = dma_map_single(kdev, cb->skb->data,
+				RX_BUF_LENGTH, DMA_FROM_DEVICE);
+	ret = dma_mapping_error(kdev, mapping);
+	if (ret) {
+		priv->mib.rx_dma_failed++;
+		bcm_sysport_free_cb(cb);
+		netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
+		return ret;
+	}
+
+	dma_unmap_addr_set(cb, dma_addr, mapping);
+	dma_desc_set_addr(priv, cb->bd_addr, mapping);
+
+	netif_dbg(priv, rx_status, ndev, "RX refill\n");
+
+	return 0;
+}
+
+static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
+{
+	struct bcm_sysport_cb *cb;
+	int ret = 0;
+	unsigned int i;
+
+	for (i = 0; i < priv->num_rx_bds; i++) {
+		cb = &priv->rx_cbs[i];
+		if (cb->skb)
+			continue;
+
+		ret = bcm_sysport_rx_refill(priv, cb);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+/* Poll the hardware for up to budget packets to process */
+static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
+					unsigned int budget)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct net_device *ndev = priv->netdev;
+	unsigned int processed = 0, to_process;
+	struct bcm_sysport_cb *cb;
+	struct sk_buff *skb;
+	unsigned int p_index;
+	u16 len, status;
+	struct rsb *rsb;
+	int ret;
+
+	/* Determine how much we should process since last call */
+	p_index = rdma_readl(priv, RDMA_PROD_INDEX);
+	p_index &= RDMA_PROD_INDEX_MASK;
+
+	if (p_index < priv->rx_c_index)
+		to_process = (RDMA_CONS_INDEX_MASK + 1) -
+				priv->rx_c_index + p_index;
+	else
+		to_process = p_index - priv->rx_c_index;
+
+	netif_dbg(priv, rx_status, ndev,
+		"p_index=%d rx_c_index=%d to_process=%d\n",
+		p_index, priv->rx_c_index, to_process);
+
+	while ((processed < to_process) &&
+		(processed < budget)) {
+
+		cb = &priv->rx_cbs[priv->rx_read_ptr];
+		skb = cb->skb;
+
+		processed++;
+		priv->rx_read_ptr++;
+		if (priv->rx_read_ptr == priv->num_rx_bds)
+			priv->rx_read_ptr = 0;
+
+		/* We do not have a backing SKB, so we do not a corresponding
+		 * DMA mapping for this incoming packet since
+		 * bcm_sysport_rx_refill always either has both skb and mapping
+		 * or none.
+		 */
+		if (unlikely(!skb)) {
+			netif_err(priv, rx_err, ndev, "out of memory!\n");
+			ndev->stats.rx_dropped++;
+			ndev->stats.rx_errors++;
+			goto refill;
+		}
+
+		dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
+				RX_BUF_LENGTH, DMA_FROM_DEVICE);
+
+		/* Extract the Receive Status Block prepended */
+		rsb = (struct rsb *)skb->data;
+		len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
+		status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
+			DESC_STATUS_MASK;
+
+		netif_dbg(priv, rx_status, ndev,
+			"p_ind=%d, c_ind=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
+			p_index, priv->rx_c_index, priv->rx_read_ptr,
+			len, status);
+
+		if (unlikely(len > RX_BUF_LENGTH)) {
+			netif_err(priv, rx_status, ndev, "oversized packet\n");
+			ndev->stats.rx_over_errors++;
+			ndev->stats.rx_errors++;
+			dev_kfree_skb_any(skb);
+			goto refill;
+		}
+
+		if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
+			netif_err(priv, rx_status, ndev, "fragmented packet!\n");
+			ndev->stats.rx_dropped++;
+			ndev->stats.rx_errors++;
+			bcm_sysport_free_cb(cb);
+			goto refill;
+		}
+
+		if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
+			netif_err(priv, rx_err, ndev, "error packet\n");
+			if (status & RX_STATUS_OVFLOW)
+				ndev->stats.rx_over_errors++;
+			ndev->stats.rx_dropped++;
+			ndev->stats.rx_errors++;
+			bcm_sysport_free_cb(cb);
+			goto refill;
+		}
+
+		skb_put(skb, len);
+
+		/* Hardware validated our checksum */
+		if (likely(status & DESC_L4_CSUM))
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+		/* Hardware pre-pends packets with 2bytes between Ethernet
+		 * and IP header plus we have the Receive Status Block, strip
+		 * off all of this from the SKB.
+		 */
+		skb_pull(skb, sizeof(*rsb) + 2);
+		len -= (sizeof(*rsb) + 2);
+
+		/* UniMAC may forward CRC */
+		if (priv->crc_fwd) {
+			skb_trim(skb, len - ETH_FCS_LEN);
+			len -= ETH_FCS_LEN;
+		}
+
+		skb->protocol = eth_type_trans(skb, ndev);
+		ndev->stats.rx_packets++;
+		ndev->stats.rx_bytes += len;
+
+		napi_gro_receive(&priv->napi, skb);
+refill:
+		ret = bcm_sysport_rx_refill(priv, cb);
+		if (ret)
+			priv->mib.alloc_rx_buff_failed++;
+	}
+
+	return processed;
+}
+
+static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv,
+					struct bcm_sysport_cb *cb,
+					unsigned int *bytes_compl,
+					unsigned int *pkts_compl)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct net_device *ndev = priv->netdev;
+
+	if (cb->skb) {
+		ndev->stats.tx_bytes += cb->skb->len;
+		*bytes_compl += cb->skb->len;
+		dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
+				dma_unmap_len(cb, dma_len),
+				DMA_TO_DEVICE);
+		ndev->stats.tx_packets++;
+		(*pkts_compl)++;
+		bcm_sysport_free_cb(cb);
+	/* SKB fragment */
+	} else if (dma_unmap_addr(cb, dma_addr)) {
+		ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len);
+		dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
+				dma_unmap_len(cb, dma_len),
+				DMA_TO_DEVICE);
+		dma_unmap_addr_set(cb, dma_addr, 0);
+	}
+}
+
+/* Reclaim queued SKBs for transmission completion, lockless version */
+static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
+					     struct bcm_sysport_tx_ring *ring)
+{
+	struct net_device *ndev = priv->netdev;
+	unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
+	unsigned int pkts_compl = 0, bytes_compl = 0;
+	struct bcm_sysport_cb *cb;
+	struct netdev_queue *txq;
+	u32 hw_ind;
+
+	txq = netdev_get_tx_queue(ndev, ring->index);
+
+	/* Compute how many descriptors have been processed since last call */
+	hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
+	c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
+	ring->p_index = (hw_ind & RING_PROD_INDEX_MASK);
+
+	last_c_index = ring->c_index;
+	num_tx_cbs = ring->size;
+
+	c_index &= (num_tx_cbs - 1);
+
+	if (c_index >= last_c_index)
+		last_tx_cn = c_index - last_c_index;
+	else
+		last_tx_cn = num_tx_cbs - last_c_index + c_index;
+
+	netif_dbg(priv, tx_done, ndev,
+		"ring=%d p_index=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
+		ring->index, ring->p_index, c_index, last_tx_cn, last_c_index);
+
+	while (last_tx_cn-- > 0) {
+		cb = ring->cbs + last_c_index;
+		bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl);
+
+		ring->desc_count++;
+		last_c_index++;
+		last_c_index &= (num_tx_cbs - 1);
+	}
+
+	ring->c_index = c_index;
+
+	if (netif_tx_queue_stopped(txq) && pkts_compl)
+		netif_tx_wake_queue(txq);
+
+	netif_dbg(priv, tx_done, ndev,
+		"ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
+		ring->index, ring->c_index, pkts_compl, bytes_compl);
+
+	return pkts_compl;
+}
+
+/* Locked version of the per-ring TX reclaim routine */
+static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
+					   struct bcm_sysport_tx_ring *ring)
+{
+	unsigned long flags;
+	unsigned int released;
+
+	spin_lock_irqsave(&ring->lock, flags);
+	released = __bcm_sysport_tx_reclaim(priv, ring);
+	spin_unlock_irqrestore(&ring->lock, flags);
+
+	return released;
+}
+
+static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
+{
+	unsigned int q;
+
+	for (q = 0; q < priv->netdev->num_tx_queues; q++)
+		bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
+}
+
+static int bcm_sysport_poll(struct napi_struct *napi, int budget)
+{
+	struct bcm_sysport_priv *priv =
+		container_of(napi, struct bcm_sysport_priv, napi);
+	unsigned int work_done = 0;
+
+	work_done = bcm_sysport_desc_rx(priv, budget);
+
+	priv->rx_c_index += work_done;
+	priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
+	rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
+
+	if (work_done < budget) {
+		napi_complete(napi);
+		/* re-enable RX interrupts */
+		intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
+	}
+
+	return work_done;
+}
+
+static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
+{
+	u32 reg;
+
+	/* Stop monitoring MPD interrupt */
+	intrl2_0_mask_set(priv, INTRL2_0_MPD);
+
+	/* Clear the MagicPacket detection logic */
+	reg = umac_readl(priv, UMAC_MPD_CTRL);
+	reg &= ~MPD_EN;
+	umac_writel(priv, reg, UMAC_MPD_CTRL);
+
+	netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
+}
+
+/* RX and misc interrupt routine */
+static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
+			  ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
+	intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
+
+	if (unlikely(priv->irq0_stat == 0)) {
+		netdev_warn(priv->netdev, "spurious RX interrupt\n");
+		return IRQ_NONE;
+	}
+
+	if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
+		if (likely(napi_schedule_prep(&priv->napi))) {
+			/* disable RX interrupts */
+			intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
+			__napi_schedule(&priv->napi);
+		}
+	}
+
+	/* TX ring is full, perform a full reclaim since we do not know
+	 * which one would trigger this interrupt
+	 */
+	if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
+		bcm_sysport_tx_reclaim_all(priv);
+
+	if (priv->irq0_stat & INTRL2_0_MPD) {
+		netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
+		bcm_sysport_resume_from_wol(priv);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/* TX interrupt service routine */
+static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int ring;
+
+	priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
+				~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
+	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+
+	if (unlikely(priv->irq1_stat == 0)) {
+		netdev_warn(priv->netdev, "spurious TX interrupt\n");
+		return IRQ_NONE;
+	}
+
+	for (ring = 0; ring < dev->num_tx_queues; ring++) {
+		if (!(priv->irq1_stat & BIT(ring)))
+			continue;
+
+		bcm_sysport_tx_reclaim(priv, &priv->tx_rings[ring]);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
+{
+	struct bcm_sysport_priv *priv = dev_id;
+
+	pm_wakeup_event(&priv->pdev->dev, 0);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void bcm_sysport_poll_controller(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	disable_irq(priv->irq0);
+	bcm_sysport_rx_isr(priv->irq0, priv);
+	enable_irq(priv->irq0);
+
+	disable_irq(priv->irq1);
+	bcm_sysport_tx_reclaim_all(priv);
+	enable_irq(priv->irq1);
+}
+#endif
+
+static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
+					      struct net_device *dev)
+{
+	struct sk_buff *nskb;
+	struct tsb *tsb;
+	u32 csum_info;
+	u8 ip_proto;
+	u16 csum_start;
+	u16 ip_ver;
+
+	/* Re-allocate SKB if needed */
+	if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
+		nskb = skb_realloc_headroom(skb, sizeof(*tsb));
+		dev_kfree_skb(skb);
+		if (!nskb) {
+			dev->stats.tx_errors++;
+			dev->stats.tx_dropped++;
+			return NULL;
+		}
+		skb = nskb;
+	}
+
+	tsb = (struct tsb *)skb_push(skb, sizeof(*tsb));
+	/* Zero-out TSB by default */
+	memset(tsb, 0, sizeof(*tsb));
+
+	if (skb->ip_summed == CHECKSUM_PARTIAL) {
+		ip_ver = htons(skb->protocol);
+		switch (ip_ver) {
+		case ETH_P_IP:
+			ip_proto = ip_hdr(skb)->protocol;
+			break;
+		case ETH_P_IPV6:
+			ip_proto = ipv6_hdr(skb)->nexthdr;
+			break;
+		default:
+			return skb;
+		}
+
+		/* Get the checksum offset and the L4 (transport) offset */
+		csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
+		csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
+		csum_info |= (csum_start << L4_PTR_SHIFT);
+
+		if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
+			csum_info |= L4_LENGTH_VALID;
+			if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
+				csum_info |= L4_UDP;
+		} else
+			csum_info = 0;
+
+		tsb->l4_ptr_dest_map = csum_info;
+	}
+
+	return skb;
+}
+
+static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
+				    struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	struct bcm_sysport_tx_ring *ring;
+	struct bcm_sysport_cb *cb;
+	struct netdev_queue *txq;
+	unsigned long flags;
+	struct dma_desc *desc;
+	unsigned int skb_len;
+	dma_addr_t mapping;
+	u32 len_status;
+	u16 queue;
+	int ret;
+
+	queue = skb_get_queue_mapping(skb);
+	txq = netdev_get_tx_queue(dev, queue);
+	ring = &priv->tx_rings[queue];
+
+	/* lock against tx reclaim in interrupt context */
+	spin_lock_irqsave(&ring->lock, flags);
+	if (unlikely(ring->desc_count == 0)) {
+		netif_tx_stop_queue(txq);
+		netdev_err(dev, "queue %d awake and ring full!\n", queue);
+		ret = NETDEV_TX_BUSY;
+		goto out;
+	}
+
+	/* The Ethernet switch we are interfaced with needs packets to be at
+	 * least 64 bytes otherwise they will be discarded when they enter
+	 * the switch port logic. When Broadcom tags are enabled, we need to
+	 * make sure that packets are at least 68 bytes because the length
+	 * verification is used after the Broadcom tag is removed.
+	 */
+	if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) {
+		ret = NETDEV_TX_OK;
+		goto out;
+	}
+
+	/* Insert TSB and checksum infos */
+	if (priv->tsb_en) {
+		skb = bcm_sysport_insert_tsb(skb, dev);
+		if (!skb) {
+			ret = NETDEV_TX_OK;
+			goto out;
+		}
+	}
+
+	skb_len = skb->len;
+
+	mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
+	if (dma_mapping_error(kdev, mapping)) {
+		priv->mib.tx_dma_failed++;
+		netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
+				skb->data, skb_len);
+		ret = NETDEV_TX_OK;
+		goto out;
+	}
+
+	/* Remember the SKB for future freeing */
+	cb = &ring->cbs[ring->curr_desc];
+	cb->skb = skb;
+	dma_unmap_addr_set(cb, dma_addr, mapping);
+	dma_unmap_len_set(cb, dma_len, skb_len);
+
+	/* Fetch a descriptor entry from our pool */
+	desc = ring->desc_cpu;
+
+	desc->addr_lo = lower_32_bits(mapping);
+	len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
+	len_status |= (skb_len << DESC_LEN_SHIFT);
+	len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
+			DESC_STATUS_SHIFT;
+	if (skb->ip_summed == CHECKSUM_PARTIAL)
+		len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
+
+	ring->curr_desc++;
+	if (ring->curr_desc == ring->size)
+		ring->curr_desc = 0;
+	ring->desc_count--;
+
+	/* Ensure write completion of the descriptor status/length
+	 * in DRAM before the System Port WRITE_PORT register latches
+	 * the value
+	 */
+	wmb();
+	desc->addr_status_len = len_status;
+	wmb();
+
+	/* Write this descriptor address to the RING write port */
+	tdma_port_write_desc_addr(priv, desc, ring->index);
+
+	/* Check ring space and update SW control flow */
+	if (ring->desc_count == 0)
+		netif_tx_stop_queue(txq);
+
+	netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
+		ring->index, ring->desc_count, ring->curr_desc);
+
+	ret = NETDEV_TX_OK;
+out:
+	spin_unlock_irqrestore(&ring->lock, flags);
+	return ret;
+}
+
+static void bcm_sysport_tx_timeout(struct net_device *dev)
+{
+	netdev_warn(dev, "transmit timeout!\n");
+
+	dev->trans_start = jiffies;
+	dev->stats.tx_errors++;
+
+	netif_tx_wake_all_queues(dev);
+}
+
+/* phylib adjust link callback */
+static void bcm_sysport_adj_link(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	struct phy_device *phydev = priv->phydev;
+	unsigned int changed = 0;
+	u32 cmd_bits = 0, reg;
+
+	if (priv->old_link != phydev->link) {
+		changed = 1;
+		priv->old_link = phydev->link;
+	}
+
+	if (priv->old_duplex != phydev->duplex) {
+		changed = 1;
+		priv->old_duplex = phydev->duplex;
+	}
+
+	switch (phydev->speed) {
+	case SPEED_2500:
+		cmd_bits = CMD_SPEED_2500;
+		break;
+	case SPEED_1000:
+		cmd_bits = CMD_SPEED_1000;
+		break;
+	case SPEED_100:
+		cmd_bits = CMD_SPEED_100;
+		break;
+	case SPEED_10:
+		cmd_bits = CMD_SPEED_10;
+		break;
+	default:
+		break;
+	}
+	cmd_bits <<= CMD_SPEED_SHIFT;
+
+	if (phydev->duplex == DUPLEX_HALF)
+		cmd_bits |= CMD_HD_EN;
+
+	if (priv->old_pause != phydev->pause) {
+		changed = 1;
+		priv->old_pause = phydev->pause;
+	}
+
+	if (!phydev->pause)
+		cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
+
+	if (!changed)
+		return;
+
+	if (phydev->link) {
+		reg = umac_readl(priv, UMAC_CMD);
+		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
+				CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
+				CMD_TX_PAUSE_IGNORE);
+		reg |= cmd_bits;
+		umac_writel(priv, reg, UMAC_CMD);
+
+	}
+
+	phy_print_status(priv->phydev);
+}
+
+static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
+				    unsigned int index)
+{
+	struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
+	struct device *kdev = &priv->pdev->dev;
+	size_t size;
+	void *p;
+	u32 reg;
+
+	/* Simple descriptors partitioning for now */
+	size = 256;
+
+	/* We just need one DMA descriptor which is DMA-able, since writing to
+	 * the port will allocate a new descriptor in its internal linked-list
+	 */
+	p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
+				GFP_KERNEL);
+	if (!p) {
+		netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
+		return -ENOMEM;
+	}
+
+	ring->cbs = kzalloc(sizeof(struct bcm_sysport_cb) * size, GFP_KERNEL);
+	if (!ring->cbs) {
+		netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
+		return -ENOMEM;
+	}
+
+	/* Initialize SW view of the ring */
+	spin_lock_init(&ring->lock);
+	ring->index = index;
+	ring->size = size;
+	ring->alloc_size = ring->size;
+	ring->desc_cpu = p;
+	ring->desc_count = ring->size;
+	ring->curr_desc = 0;
+
+	/* Initialize HW ring */
+	tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
+	tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
+	tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
+	tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
+	tdma_writel(priv, 0, TDMA_DESC_RING_MAPPING(index));
+	tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
+
+	/* Enable ACB algorithm 1 */
+	reg = tdma_readl(priv, TDMA_CONTROL);
+	reg |= ACB_ALGO;
+	tdma_writel(priv, reg, TDMA_CONTROL);
+
+	/* Program the number of descriptors as MAX_THRESHOLD and half of
+	 * its size for the hysteresis trigger
+	 */
+	tdma_writel(priv, ring->size |
+			1 << RING_HYST_THRESH_SHIFT,
+			TDMA_DESC_RING_MAX_HYST(index));
+
+	/* Enable the ring queue in the arbiter */
+	reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
+	reg |= (1 << index);
+	tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
+
+	netif_dbg(priv, hw, priv->netdev,
+		"TDMA cfg, size=%d, desc_cpu=%p\n",
+		ring->size, ring->desc_cpu);
+
+	return 0;
+}
+
+static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
+					unsigned int index)
+{
+	struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
+	struct device *kdev = &priv->pdev->dev;
+	u32 reg;
+
+	/* Caller should stop the TDMA engine */
+	reg = tdma_readl(priv, TDMA_STATUS);
+	if (!(reg & TDMA_DISABLED))
+		netdev_warn(priv->netdev, "TDMA not stopped!\n");
+
+	/* ring->cbs is the last part of bcm_sysport_tx_init() which could fail
+	 * so by checking this pointer we know whether the TX ring was fully
+	 * initialized or not
+	 */
+	if (!ring->cbs)
+		return;
+
+	bcm_sysport_tx_reclaim(priv, ring);
+
+	kfree(ring->cbs);
+	ring->cbs = NULL;
+
+	if (ring->desc_dma) {
+		dma_free_coherent(kdev, sizeof(struct dma_desc),
+				  ring->desc_cpu, ring->desc_dma);
+		ring->desc_dma = 0;
+	}
+	ring->size = 0;
+	ring->alloc_size = 0;
+
+	netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
+}
+
+/* RDMA helper */
+static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
+					unsigned int enable)
+{
+	unsigned int timeout = 1000;
+	u32 reg;
+
+	reg = rdma_readl(priv, RDMA_CONTROL);
+	if (enable)
+		reg |= RDMA_EN;
+	else
+		reg &= ~RDMA_EN;
+	rdma_writel(priv, reg, RDMA_CONTROL);
+
+	/* Poll for RMDA disabling completion */
+	do {
+		reg = rdma_readl(priv, RDMA_STATUS);
+		if (!!(reg & RDMA_DISABLED) == !enable)
+			return 0;
+		usleep_range(1000, 2000);
+	} while (timeout-- > 0);
+
+	netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
+
+	return -ETIMEDOUT;
+}
+
+/* TDMA helper */
+static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
+					unsigned int enable)
+{
+	unsigned int timeout = 1000;
+	u32 reg;
+
+	reg = tdma_readl(priv, TDMA_CONTROL);
+	if (enable)
+		reg |= TDMA_EN;
+	else
+		reg &= ~TDMA_EN;
+	tdma_writel(priv, reg, TDMA_CONTROL);
+
+	/* Poll for TMDA disabling completion */
+	do {
+		reg = tdma_readl(priv, TDMA_STATUS);
+		if (!!(reg & TDMA_DISABLED) == !enable)
+			return 0;
+
+		usleep_range(1000, 2000);
+	} while (timeout-- > 0);
+
+	netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
+
+	return -ETIMEDOUT;
+}
+
+static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
+{
+	struct bcm_sysport_cb *cb;
+	u32 reg;
+	int ret;
+	int i;
+
+	/* Initialize SW view of the RX ring */
+	priv->num_rx_bds = NUM_RX_DESC;
+	priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
+	priv->rx_c_index = 0;
+	priv->rx_read_ptr = 0;
+	priv->rx_cbs = kzalloc(priv->num_rx_bds *
+				sizeof(struct bcm_sysport_cb), GFP_KERNEL);
+	if (!priv->rx_cbs) {
+		netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < priv->num_rx_bds; i++) {
+		cb = priv->rx_cbs + i;
+		cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
+	}
+
+	ret = bcm_sysport_alloc_rx_bufs(priv);
+	if (ret) {
+		netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
+		return ret;
+	}
+
+	/* Initialize HW, ensure RDMA is disabled */
+	reg = rdma_readl(priv, RDMA_STATUS);
+	if (!(reg & RDMA_DISABLED))
+		rdma_enable_set(priv, 0);
+
+	rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
+	rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
+	rdma_writel(priv, 0, RDMA_PROD_INDEX);
+	rdma_writel(priv, 0, RDMA_CONS_INDEX);
+	rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
+			  RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
+	/* Operate the queue in ring mode */
+	rdma_writel(priv, 0, RDMA_START_ADDR_HI);
+	rdma_writel(priv, 0, RDMA_START_ADDR_LO);
+	rdma_writel(priv, 0, RDMA_END_ADDR_HI);
+	rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO);
+
+	rdma_writel(priv, 1, RDMA_MBDONE_INTR);
+
+	netif_dbg(priv, hw, priv->netdev,
+		"RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
+		priv->num_rx_bds, priv->rx_bds);
+
+	return 0;
+}
+
+static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
+{
+	struct bcm_sysport_cb *cb;
+	unsigned int i;
+	u32 reg;
+
+	/* Caller should ensure RDMA is disabled */
+	reg = rdma_readl(priv, RDMA_STATUS);
+	if (!(reg & RDMA_DISABLED))
+		netdev_warn(priv->netdev, "RDMA not stopped!\n");
+
+	for (i = 0; i < priv->num_rx_bds; i++) {
+		cb = &priv->rx_cbs[i];
+		if (dma_unmap_addr(cb, dma_addr))
+			dma_unmap_single(&priv->pdev->dev,
+					dma_unmap_addr(cb, dma_addr),
+					RX_BUF_LENGTH, DMA_FROM_DEVICE);
+		bcm_sysport_free_cb(cb);
+	}
+
+	kfree(priv->rx_cbs);
+	priv->rx_cbs = NULL;
+
+	netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
+}
+
+static void bcm_sysport_set_rx_mode(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	reg = umac_readl(priv, UMAC_CMD);
+	if (dev->flags & IFF_PROMISC)
+		reg |= CMD_PROMISC;
+	else
+		reg &= ~CMD_PROMISC;
+	umac_writel(priv, reg, UMAC_CMD);
+
+	/* No support for ALLMULTI */
+	if (dev->flags & IFF_ALLMULTI)
+		return;
+}
+
+static inline void umac_enable_set(struct bcm_sysport_priv *priv,
+					u32 mask, unsigned int enable)
+{
+	u32 reg;
+
+	reg = umac_readl(priv, UMAC_CMD);
+	if (enable)
+		reg |= mask;
+	else
+		reg &= ~mask;
+	umac_writel(priv, reg, UMAC_CMD);
+
+	/* UniMAC stops on a packet boundary, wait for a full-sized packet
+	 * to be processed
+	 */
+	if (enable == 0)
+		usleep_range(1000, 2000);
+}
+
+static inline void umac_reset(struct bcm_sysport_priv *priv)
+{
+	u32 reg;
+
+	reg = umac_readl(priv, UMAC_CMD);
+	reg |= CMD_SW_RESET;
+	umac_writel(priv, reg, UMAC_CMD);
+	udelay(10);
+	reg = umac_readl(priv, UMAC_CMD);
+	reg &= ~CMD_SW_RESET;
+	umac_writel(priv, reg, UMAC_CMD);
+}
+
+static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
+				unsigned char *addr)
+{
+	umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
+		(addr[2] << 8) | addr[3], UMAC_MAC0);
+	umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
+}
+
+static void topctrl_flush(struct bcm_sysport_priv *priv)
+{
+	topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
+	topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
+	mdelay(1);
+	topctrl_writel(priv, 0, RX_FLUSH_CNTL);
+	topctrl_writel(priv, 0, TX_FLUSH_CNTL);
+}
+
+static int bcm_sysport_change_mac(struct net_device *dev, void *p)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	struct sockaddr *addr = p;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EINVAL;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	/* interface is disabled, changes to MAC will be reflected on next
+	 * open call
+	 */
+	if (!netif_running(dev))
+		return 0;
+
+	umac_set_hw_addr(priv, dev->dev_addr);
+
+	return 0;
+}
+
+static void bcm_sysport_netif_start(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	/* Enable NAPI */
+	napi_enable(&priv->napi);
+
+	/* Enable RX interrupt and TX ring full interrupt */
+	intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
+
+	phy_start(priv->phydev);
+
+	/* Enable TX interrupts for the 32 TXQs */
+	intrl2_1_mask_clear(priv, 0xffffffff);
+
+	/* Last call before we start the real business */
+	netif_tx_start_all_queues(dev);
+}
+
+static void rbuf_init(struct bcm_sysport_priv *priv)
+{
+	u32 reg;
+
+	reg = rbuf_readl(priv, RBUF_CONTROL);
+	reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
+	rbuf_writel(priv, reg, RBUF_CONTROL);
+}
+
+static int bcm_sysport_open(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	int ret;
+
+	clk_prepare_enable(priv->clk);
+
+	/* Reset UniMAC */
+	umac_reset(priv);
+
+	/* Flush TX and RX FIFOs at TOPCTRL level */
+	topctrl_flush(priv);
+
+	/* Disable the UniMAC RX/TX */
+	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
+
+	/* Enable RBUF 2bytes alignment and Receive Status Block */
+	rbuf_init(priv);
+
+	/* Set maximum frame length */
+	umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
+
+	/* Set MAC address */
+	umac_set_hw_addr(priv, dev->dev_addr);
+
+	/* Read CRC forward */
+	priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
+
+	priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
+					0, priv->phy_interface);
+	if (!priv->phydev) {
+		netdev_err(dev, "could not attach to PHY\n");
+		ret = -ENODEV;
+		goto out_clk_disable;
+	}
+
+	/* Reset house keeping link status */
+	priv->old_duplex = -1;
+	priv->old_link = -1;
+	priv->old_pause = -1;
+
+	/* mask all interrupts and request them */
+	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
+	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+	intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
+	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+	intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+
+	ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
+	if (ret) {
+		netdev_err(dev, "failed to request RX interrupt\n");
+		goto out_phy_disconnect;
+	}
+
+	ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev);
+	if (ret) {
+		netdev_err(dev, "failed to request TX interrupt\n");
+		goto out_free_irq0;
+	}
+
+	/* Initialize both hardware and software ring */
+	for (i = 0; i < dev->num_tx_queues; i++) {
+		ret = bcm_sysport_init_tx_ring(priv, i);
+		if (ret) {
+			netdev_err(dev, "failed to initialize TX ring %d\n",
+					i);
+			goto out_free_tx_ring;
+		}
+	}
+
+	/* Initialize linked-list */
+	tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
+
+	/* Initialize RX ring */
+	ret = bcm_sysport_init_rx_ring(priv);
+	if (ret) {
+		netdev_err(dev, "failed to initialize RX ring\n");
+		goto out_free_rx_ring;
+	}
+
+	/* Turn on RDMA */
+	ret = rdma_enable_set(priv, 1);
+	if (ret)
+		goto out_free_rx_ring;
+
+	/* Turn on TDMA */
+	ret = tdma_enable_set(priv, 1);
+	if (ret)
+		goto out_clear_rx_int;
+
+	/* Turn on UniMAC TX/RX */
+	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
+
+	bcm_sysport_netif_start(dev);
+
+	return 0;
+
+out_clear_rx_int:
+	intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
+out_free_rx_ring:
+	bcm_sysport_fini_rx_ring(priv);
+out_free_tx_ring:
+	for (i = 0; i < dev->num_tx_queues; i++)
+		bcm_sysport_fini_tx_ring(priv, i);
+	free_irq(priv->irq1, dev);
+out_free_irq0:
+	free_irq(priv->irq0, dev);
+out_phy_disconnect:
+	phy_disconnect(priv->phydev);
+out_clk_disable:
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+
+static void bcm_sysport_netif_stop(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+
+	/* stop all software from updating hardware */
+	netif_tx_stop_all_queues(dev);
+	napi_disable(&priv->napi);
+	phy_stop(priv->phydev);
+
+	/* mask all interrupts */
+	intrl2_0_mask_set(priv, 0xffffffff);
+	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+	intrl2_1_mask_set(priv, 0xffffffff);
+	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+}
+
+static int bcm_sysport_stop(struct net_device *dev)
+{
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	int ret;
+
+	bcm_sysport_netif_stop(dev);
+
+	/* Disable UniMAC RX */
+	umac_enable_set(priv, CMD_RX_EN, 0);
+
+	ret = tdma_enable_set(priv, 0);
+	if (ret) {
+		netdev_err(dev, "timeout disabling RDMA\n");
+		return ret;
+	}
+
+	/* Wait for a maximum packet size to be drained */
+	usleep_range(2000, 3000);
+
+	ret = rdma_enable_set(priv, 0);
+	if (ret) {
+		netdev_err(dev, "timeout disabling TDMA\n");
+		return ret;
+	}
+
+	/* Disable UniMAC TX */
+	umac_enable_set(priv, CMD_TX_EN, 0);
+
+	/* Free RX/TX rings SW structures */
+	for (i = 0; i < dev->num_tx_queues; i++)
+		bcm_sysport_fini_tx_ring(priv, i);
+	bcm_sysport_fini_rx_ring(priv);
+
+	free_irq(priv->irq0, dev);
+	free_irq(priv->irq1, dev);
+
+	/* Disconnect from PHY */
+	phy_disconnect(priv->phydev);
+
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+static struct ethtool_ops bcm_sysport_ethtool_ops = {
+	.get_settings		= bcm_sysport_get_settings,
+	.set_settings		= bcm_sysport_set_settings,
+	.get_drvinfo		= bcm_sysport_get_drvinfo,
+	.get_msglevel		= bcm_sysport_get_msglvl,
+	.set_msglevel		= bcm_sysport_set_msglvl,
+	.get_link		= ethtool_op_get_link,
+	.get_strings		= bcm_sysport_get_strings,
+	.get_ethtool_stats	= bcm_sysport_get_stats,
+	.get_sset_count		= bcm_sysport_get_sset_count,
+	.get_wol		= bcm_sysport_get_wol,
+	.set_wol		= bcm_sysport_set_wol,
+	.get_coalesce		= bcm_sysport_get_coalesce,
+	.set_coalesce		= bcm_sysport_set_coalesce,
+};
+
+static const struct net_device_ops bcm_sysport_netdev_ops = {
+	.ndo_start_xmit		= bcm_sysport_xmit,
+	.ndo_tx_timeout		= bcm_sysport_tx_timeout,
+	.ndo_open		= bcm_sysport_open,
+	.ndo_stop		= bcm_sysport_stop,
+	.ndo_set_features	= bcm_sysport_set_features,
+	.ndo_set_rx_mode	= bcm_sysport_set_rx_mode,
+	.ndo_set_mac_address	= bcm_sysport_change_mac,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= bcm_sysport_poll_controller,
+#endif
+};
+
+#define REV_FMT	"v%2x.%02x"
+
+static int bcm_sysport_probe(struct platform_device *pdev)
+{
+	struct bcm_sysport_priv *priv;
+	struct device_node *dn;
+	struct net_device *dev;
+	const void *macaddr;
+	struct resource *r;
+	u32 txq, rxq;
+	int ret;
+
+	dn = pdev->dev.of_node;
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	/* Read the Transmit/Receive Queue properties */
+	if (of_property_read_u32(dn, "systemport,num-txq", &txq))
+		txq = TDMA_NUM_RINGS;
+	if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
+		rxq = 1;
+
+	dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
+	if (!dev)
+		return -ENOMEM;
+
+	/* Initialize private members */
+	priv = netdev_priv(dev);
+
+	priv->irq0 = platform_get_irq(pdev, 0);
+	priv->irq1 = platform_get_irq(pdev, 1);
+	priv->wol_irq = platform_get_irq(pdev, 2);
+	if (priv->irq0 <= 0 || priv->irq1 <= 0) {
+		dev_err(&pdev->dev, "invalid interrupts\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	priv->base = devm_request_and_ioremap(&pdev->dev, r);
+	if (!priv->base) {
+		dev_err(&pdev->dev, "register remap failed\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	priv->netdev = dev;
+	priv->pdev = pdev;
+
+	priv->phy_interface = of_get_phy_mode(dn);
+	/* Default to GMII interface mode */
+	if (priv->phy_interface < 0)
+		priv->phy_interface = PHY_INTERFACE_MODE_GMII;
+
+	/* In the case of a fixed PHY, the DT node associated
+	 * to the PHY is the Ethernet MAC DT node.
+	 */
+	if (of_phy_is_fixed_link(dn)) {
+		ret = of_phy_register_fixed_link(dn);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to register fixed PHY\n");
+			goto err;
+		}
+
+		priv->phy_dn = dn;
+	}
+
+	/* Initialize netdevice members */
+	macaddr = of_get_mac_address(dn);
+	if (!macaddr || !is_valid_ether_addr(macaddr)) {
+		dev_warn(&pdev->dev, "using random Ethernet MAC\n");
+		random_ether_addr(dev->dev_addr);
+	} else {
+		memcpy(dev->dev_addr, macaddr, ETH_ALEN);
+	}
+
+	SET_NETDEV_DEV(dev, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, dev);
+	SET_ETHTOOL_OPS(dev, &bcm_sysport_ethtool_ops);
+	dev->netdev_ops = &bcm_sysport_netdev_ops;
+	netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
+
+	/* HW supported features, none enabled by default */
+	dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
+				NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+
+	/* Request the WOL interrupt and advertise suspend if available */
+	priv->wol_irq_disabled = 1;
+	ret = devm_request_irq(&pdev->dev, priv->wol_irq,
+				bcm_sysport_wol_isr, 0, dev->name, priv);
+	if (!ret)
+		device_set_wakeup_capable(&pdev->dev, 1);
+
+	priv->clk = devm_clk_get(&pdev->dev, "sw_sysport");
+	if (IS_ERR(priv->clk)) {
+		dev_warn(&pdev->dev, "failed to request clock\n");
+		priv->clk = NULL;
+	}
+
+	/* Set the needed headroom once and for all */
+	BUILD_BUG_ON(sizeof(struct tsb) != 8);
+	dev->needed_headroom += sizeof(struct tsb);
+
+	clk_prepare_enable(priv->clk);
+
+	priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
+	dev_info(&pdev->dev,
+		"Broadcom SYSTEMPORT" REV_FMT
+		" at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
+		(priv->rev >> 8) & 0xff, priv->rev & 0xff,
+		priv->base, priv->irq0, priv->irq1, txq, rxq);
+
+	clk_disable_unprepare(priv->clk);
+
+	/* libphy will adjust the link state accordingly */
+	netif_carrier_off(dev);
+
+	ret = register_netdev(dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register net_device\n");
+		goto err;
+	}
+
+
+	return 0;
+err:
+	free_netdev(dev);
+	return ret;
+}
+
+static int bcm_sysport_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = dev_get_drvdata(&pdev->dev);
+
+	/* Not much to do, ndo_close has been called
+	 * and we use managed allocations
+	 */
+	unregister_netdev(dev);
+	free_netdev(dev);
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
+{
+	struct net_device *ndev = priv->netdev;
+	unsigned int timeout = 1000;
+	u32 reg;
+
+	/* Password has already been programmed */
+	reg = umac_readl(priv, UMAC_MPD_CTRL);
+	reg |= MPD_EN;
+	reg &= ~PSW_EN;
+	if (priv->wolopts & WAKE_MAGICSECURE)
+		reg |= PSW_EN;
+	umac_writel(priv, reg, UMAC_MPD_CTRL);
+
+	/* Make sure RBUF entered WoL mode as result */
+	do {
+		reg = rbuf_readl(priv, RBUF_STATUS);
+		if (reg & RBUF_WOL_MODE)
+			break;
+
+		udelay(10);
+	} while (timeout-- > 0);
+
+	/* Do not leave the UniMAC RBUF matching only MPD packets */
+	if (!timeout) {
+		reg = umac_readl(priv, UMAC_MPD_CTRL);
+		reg &= ~MPD_EN;
+		umac_writel(priv, reg, UMAC_MPD_CTRL);
+		netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
+		return -ETIMEDOUT;
+	}
+
+	/* UniMAC receive needs to be turned on */
+	umac_enable_set(priv, CMD_RX_EN, 1);
+
+	/* Enable the interrupt wake-up source */
+	intrl2_0_mask_clear(priv, INTRL2_0_MPD);
+
+	netif_dbg(priv, wol, ndev, "entered WOL mode\n");
+
+	return 0;
+}
+
+static int bcm_sysport_suspend(struct device *d)
+{
+	struct net_device *dev = dev_get_drvdata(d);
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	int ret = 0;
+	u32 reg;
+
+	if (!netif_running(dev))
+		return 0;
+
+	bcm_sysport_netif_stop(dev);
+
+	phy_suspend(priv->phydev);
+
+	netif_device_detach(dev);
+
+	/* Disable UniMAC RX */
+	umac_enable_set(priv, CMD_RX_EN, 0);
+
+	ret = rdma_enable_set(priv, 0);
+	if (ret) {
+		netdev_err(dev, "RDMA timeout!\n");
+		return ret;
+	}
+
+	/* Disable RXCHK if enabled */
+	if (priv->rx_chk_en) {
+		reg = rxchk_readl(priv, RXCHK_CONTROL);
+		reg &= ~RXCHK_EN;
+		rxchk_writel(priv, reg, RXCHK_CONTROL);
+	}
+
+	/* Flush RX pipe */
+	if (!priv->wolopts)
+		topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
+
+	ret = tdma_enable_set(priv, 0);
+	if (ret) {
+		netdev_err(dev, "TDMA timeout!\n");
+		return ret;
+	}
+
+	/* Wait for a packet boundary */
+	usleep_range(2000, 3000);
+
+	umac_enable_set(priv, CMD_TX_EN, 0);
+
+	topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
+
+	/* Free RX/TX rings SW structures */
+	for (i = 0; i < dev->num_tx_queues; i++)
+		bcm_sysport_fini_tx_ring(priv, i);
+	bcm_sysport_fini_rx_ring(priv);
+
+	/* Get prepared for Wake-on-LAN */
+	if (device_may_wakeup(d) && priv->wolopts)
+		ret = bcm_sysport_suspend_to_wol(priv);
+
+	clk_disable_unprepare(priv->clk);
+
+	return ret;
+}
+
+static int bcm_sysport_resume(struct device *d)
+{
+	struct net_device *dev = dev_get_drvdata(d);
+	struct bcm_sysport_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	u32 reg;
+	int ret;
+
+	if (!netif_running(dev))
+		return 0;
+
+	clk_prepare_enable(priv->clk);
+
+	umac_reset(priv);
+
+	/* We may have been suspended and never received a WOL event that
+	 * would turn off MPD detection, take care of that now
+	 */
+	bcm_sysport_resume_from_wol(priv);
+
+	/* Initialize both hardware and software ring */
+	for (i = 0; i < dev->num_tx_queues; i++) {
+		ret = bcm_sysport_init_tx_ring(priv, i);
+		if (ret) {
+			netdev_err(dev, "failed to initialize TX ring %d\n",
+					i);
+			goto out_free_tx_rings;
+		}
+	}
+
+	/* Initialize linked-list */
+	tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
+
+	/* Initialize RX ring */
+	ret = bcm_sysport_init_rx_ring(priv);
+	if (ret) {
+		netdev_err(dev, "failed to initialize RX ring\n");
+		goto out_free_rx_ring;
+	}
+
+	netif_device_attach(dev);
+
+	/* RX pipe enable */
+	topctrl_writel(priv, 0, RX_FLUSH_CNTL);
+
+	ret = rdma_enable_set(priv, 1);
+	if (ret) {
+		netdev_err(dev, "failed to enable RDMA\n");
+		goto out_free_rx_ring;
+	}
+
+	/* Enable rxhck */
+	if (priv->rx_chk_en) {
+		reg = rxchk_readl(priv, RXCHK_CONTROL);
+		reg |= RXCHK_EN;
+		rxchk_writel(priv, reg, RXCHK_CONTROL);
+	}
+
+	rbuf_init(priv);
+
+	/* Set maximum frame length */
+	umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
+
+	/* Set MAC address */
+	umac_set_hw_addr(priv, dev->dev_addr);
+
+	umac_enable_set(priv, CMD_RX_EN, 1);
+
+	/* TX pipe enable */
+	topctrl_writel(priv, 0, TX_FLUSH_CNTL);
+
+	umac_enable_set(priv, CMD_TX_EN, 1);
+
+	ret = tdma_enable_set(priv, 1);
+	if (ret) {
+		netdev_err(dev, "TDMA timeout!\n");
+		goto out_free_rx_ring;
+	}
+
+	phy_resume(priv->phydev);
+
+	bcm_sysport_netif_start(dev);
+
+	return 0;
+
+out_free_rx_ring:
+	bcm_sysport_fini_rx_ring(priv);
+out_free_tx_rings:
+	for (i = 0; i < dev->num_tx_queues; i++)
+		bcm_sysport_fini_tx_ring(priv, i);
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
+		bcm_sysport_suspend, bcm_sysport_resume);
+
+static const struct of_device_id bcm_sysport_of_match[] = {
+	{ .compatible = "brcm,systemport-v1.00" },
+	{ .compatible = "brcm,systemport" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver bcm_sysport_driver = {
+	.probe	= bcm_sysport_probe,
+	.remove	= bcm_sysport_remove,
+	.driver =  {
+		.name = "brcm-systemport",
+		.owner = THIS_MODULE,
+		.of_match_table = bcm_sysport_of_match,
+		.pm = &bcm_sysport_pm_ops,
+	},
+};
+module_platform_driver(bcm_sysport_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
+MODULE_ALIAS("platform:brcm-systemport");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.h b/drivers/net/ethernet/broadcom/bcmsysport.h
new file mode 100644
index 000000000000..054994131164
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/bcmsysport.h
@@ -0,0 +1,701 @@
+/*
+ * Broadcom BCM7xxx System Port Ethernet MAC driver
+ *
+ * Copyright (C) 2013-2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __BCM_SYSPORT_H
+#define __BCM_SYSPORT_H
+
+#include <linux/if_vlan.h>
+
+/* Receive/transmit descriptor format */
+#define DESC_ADDR_HI_STATUS_LEN	0x00
+#define  DESC_ADDR_HI_SHIFT	0
+#define  DESC_ADDR_HI_MASK	0xff
+#define  DESC_STATUS_SHIFT	8
+#define  DESC_STATUS_MASK	0x3ff
+#define  DESC_LEN_SHIFT		18
+#define  DESC_LEN_MASK		0x7fff
+#define DESC_ADDR_LO		0x04
+
+/* HW supports 40-bit addressing hence the */
+#define DESC_SIZE		(WORDS_PER_DESC * sizeof(u32))
+
+/* Default RX buffer allocation size */
+#define RX_BUF_LENGTH		2048
+
+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_BRCM_TAG_LEN	4
+#define ENET_PAD		10
+#define UMAC_MAX_MTU_SIZE	(ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
+				 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
+
+/* Transmit status block */
+struct tsb {
+	u32 pcp_dei_vid;
+#define PCP_DEI_MASK		0xf
+#define VID_SHIFT		4
+#define VID_MASK		0xfff
+	u32 l4_ptr_dest_map;
+#define L4_CSUM_PTR_MASK	0x1ff
+#define L4_PTR_SHIFT		9
+#define L4_PTR_MASK		0x1ff
+#define L4_UDP			(1 << 18)
+#define L4_LENGTH_VALID		(1 << 19)
+#define DEST_MAP_SHIFT		20
+#define DEST_MAP_MASK		0x1ff
+};
+
+/* Receive status block uses the same
+ * definitions as the DMA descriptor
+ */
+struct rsb {
+	u32 rx_status_len;
+	u32 brcm_egress_tag;
+};
+
+/* Common Receive/Transmit status bits */
+#define DESC_L4_CSUM		(1 << 7)
+#define DESC_SOP		(1 << 8)
+#define DESC_EOP		(1 << 9)
+
+/* Receive Status bits */
+#define RX_STATUS_UCAST			0
+#define RX_STATUS_BCAST			0x04
+#define RX_STATUS_MCAST			0x08
+#define RX_STATUS_L2_MCAST		0x0c
+#define RX_STATUS_ERR			(1 << 4)
+#define RX_STATUS_OVFLOW		(1 << 5)
+#define RX_STATUS_PARSE_FAIL		(1 << 6)
+
+/* Transmit Status bits */
+#define TX_STATUS_VLAN_NO_ACT		0x00
+#define TX_STATUS_VLAN_PCP_TSB		0x01
+#define TX_STATUS_VLAN_QUEUE		0x02
+#define TX_STATUS_VLAN_VID_TSB		0x03
+#define TX_STATUS_OWR_CRC		(1 << 2)
+#define TX_STATUS_APP_CRC		(1 << 3)
+#define TX_STATUS_BRCM_TAG_NO_ACT	0
+#define TX_STATUS_BRCM_TAG_ZERO		0x10
+#define TX_STATUS_BRCM_TAG_ONE_QUEUE	0x20
+#define TX_STATUS_BRCM_TAG_ONE_TSB	0x30
+#define TX_STATUS_SKIP_BYTES		(1 << 6)
+
+/* Specific register definitions */
+#define SYS_PORT_TOPCTRL_OFFSET		0
+#define REV_CNTL			0x00
+#define  REV_MASK			0xffff
+
+#define RX_FLUSH_CNTL			0x04
+#define  RX_FLUSH			(1 << 0)
+
+#define TX_FLUSH_CNTL			0x08
+#define  TX_FLUSH			(1 << 0)
+
+#define MISC_CNTL			0x0c
+#define  SYS_CLK_SEL			(1 << 0)
+#define  TDMA_EOP_SEL			(1 << 1)
+
+/* Level-2 Interrupt controller offsets and defines */
+#define SYS_PORT_INTRL2_0_OFFSET	0x200
+#define SYS_PORT_INTRL2_1_OFFSET	0x240
+#define INTRL2_CPU_STATUS		0x00
+#define INTRL2_CPU_SET			0x04
+#define INTRL2_CPU_CLEAR		0x08
+#define INTRL2_CPU_MASK_STATUS		0x0c
+#define INTRL2_CPU_MASK_SET		0x10
+#define INTRL2_CPU_MASK_CLEAR		0x14
+
+/* Level-2 instance 0 interrupt bits */
+#define INTRL2_0_GISB_ERR		(1 << 0)
+#define INTRL2_0_RBUF_OVFLOW		(1 << 1)
+#define INTRL2_0_TBUF_UNDFLOW		(1 << 2)
+#define INTRL2_0_MPD			(1 << 3)
+#define INTRL2_0_BRCM_MATCH_TAG		(1 << 4)
+#define INTRL2_0_RDMA_MBDONE		(1 << 5)
+#define INTRL2_0_OVER_MAX_THRESH	(1 << 6)
+#define INTRL2_0_BELOW_HYST_THRESH	(1 << 7)
+#define INTRL2_0_FREE_LIST_EMPTY	(1 << 8)
+#define INTRL2_0_TX_RING_FULL		(1 << 9)
+#define INTRL2_0_DESC_ALLOC_ERR		(1 << 10)
+#define INTRL2_0_UNEXP_PKTSIZE_ACK	(1 << 11)
+
+/* RXCHK offset and defines */
+#define SYS_PORT_RXCHK_OFFSET		0x300
+
+#define RXCHK_CONTROL			0x00
+#define  RXCHK_EN			(1 << 0)
+#define  RXCHK_SKIP_FCS			(1 << 1)
+#define  RXCHK_BAD_CSUM_DIS		(1 << 2)
+#define  RXCHK_BRCM_TAG_EN		(1 << 3)
+#define  RXCHK_BRCM_TAG_MATCH_SHIFT	4
+#define  RXCHK_BRCM_TAG_MATCH_MASK	0xff
+#define  RXCHK_PARSE_TNL		(1 << 12)
+#define  RXCHK_VIOL_EN			(1 << 13)
+#define  RXCHK_VIOL_DIS			(1 << 14)
+#define  RXCHK_INCOM_PKT		(1 << 15)
+#define  RXCHK_V6_DUPEXT_EN		(1 << 16)
+#define  RXCHK_V6_DUPEXT_DIS		(1 << 17)
+#define  RXCHK_ETHERTYPE_DIS		(1 << 18)
+#define  RXCHK_L2_HDR_DIS		(1 << 19)
+#define  RXCHK_L3_HDR_DIS		(1 << 20)
+#define  RXCHK_MAC_RX_ERR_DIS		(1 << 21)
+#define  RXCHK_PARSE_AUTH		(1 << 22)
+
+#define RXCHK_BRCM_TAG0			0x04
+#define RXCHK_BRCM_TAG(i)		((i) * RXCHK_BRCM_TAG0)
+#define RXCHK_BRCM_TAG0_MASK		0x24
+#define RXCHK_BRCM_TAG_MASK(i)		((i) * RXCHK_BRCM_TAG0_MASK)
+#define RXCHK_BRCM_TAG_MATCH_STATUS	0x44
+#define RXCHK_ETHERTYPE			0x48
+#define RXCHK_BAD_CSUM_CNTR		0x4C
+#define RXCHK_OTHER_DISC_CNTR		0x50
+
+/* TXCHCK offsets and defines */
+#define SYS_PORT_TXCHK_OFFSET		0x380
+#define TXCHK_PKT_RDY_THRESH		0x00
+
+/* Receive buffer offset and defines */
+#define SYS_PORT_RBUF_OFFSET		0x400
+
+#define RBUF_CONTROL			0x00
+#define  RBUF_RSB_EN			(1 << 0)
+#define  RBUF_4B_ALGN			(1 << 1)
+#define  RBUF_BRCM_TAG_STRIP		(1 << 2)
+#define  RBUF_BAD_PKT_DISC		(1 << 3)
+#define  RBUF_RESUME_THRESH_SHIFT	4
+#define  RBUF_RESUME_THRESH_MASK	0xff
+#define  RBUF_OK_TO_SEND_SHIFT		12
+#define  RBUF_OK_TO_SEND_MASK		0xff
+#define  RBUF_CRC_REPLACE		(1 << 20)
+#define  RBUF_OK_TO_SEND_MODE		(1 << 21)
+#define  RBUF_RSB_SWAP			(1 << 22)
+#define  RBUF_ACPI_EN			(1 << 23)
+
+#define RBUF_PKT_RDY_THRESH		0x04
+
+#define RBUF_STATUS			0x08
+#define  RBUF_WOL_MODE			(1 << 0)
+#define  RBUF_MPD			(1 << 1)
+#define  RBUF_ACPI			(1 << 2)
+
+#define RBUF_OVFL_DISC_CNTR		0x0c
+#define RBUF_ERR_PKT_CNTR		0x10
+
+/* Transmit buffer offset and defines */
+#define SYS_PORT_TBUF_OFFSET		0x600
+
+#define TBUF_CONTROL			0x00
+#define  TBUF_BP_EN			(1 << 0)
+#define  TBUF_MAX_PKT_THRESH_SHIFT	1
+#define  TBUF_MAX_PKT_THRESH_MASK	0x1f
+#define  TBUF_FULL_THRESH_SHIFT		8
+#define  TBUF_FULL_THRESH_MASK		0x1f
+
+/* UniMAC offset and defines */
+#define SYS_PORT_UMAC_OFFSET		0x800
+
+#define UMAC_CMD			0x008
+#define  CMD_TX_EN			(1 << 0)
+#define  CMD_RX_EN			(1 << 1)
+#define  CMD_SPEED_SHIFT		2
+#define  CMD_SPEED_10			0
+#define  CMD_SPEED_100			1
+#define  CMD_SPEED_1000			2
+#define  CMD_SPEED_2500			3
+#define  CMD_SPEED_MASK			3
+#define  CMD_PROMISC			(1 << 4)
+#define  CMD_PAD_EN			(1 << 5)
+#define  CMD_CRC_FWD			(1 << 6)
+#define  CMD_PAUSE_FWD			(1 << 7)
+#define  CMD_RX_PAUSE_IGNORE		(1 << 8)
+#define  CMD_TX_ADDR_INS		(1 << 9)
+#define  CMD_HD_EN			(1 << 10)
+#define  CMD_SW_RESET			(1 << 13)
+#define  CMD_LCL_LOOP_EN		(1 << 15)
+#define  CMD_AUTO_CONFIG		(1 << 22)
+#define  CMD_CNTL_FRM_EN		(1 << 23)
+#define  CMD_NO_LEN_CHK			(1 << 24)
+#define  CMD_RMT_LOOP_EN		(1 << 25)
+#define  CMD_PRBL_EN			(1 << 27)
+#define  CMD_TX_PAUSE_IGNORE		(1 << 28)
+#define  CMD_TX_RX_EN			(1 << 29)
+#define  CMD_RUNT_FILTER_DIS		(1 << 30)
+
+#define UMAC_MAC0			0x00c
+#define UMAC_MAC1			0x010
+#define UMAC_MAX_FRAME_LEN		0x014
+
+#define UMAC_TX_FLUSH			0x334
+
+#define UMAC_MIB_START			0x400
+
+/* There is a 0xC gap between the end of RX and beginning of TX stats and then
+ * between the end of TX stats and the beginning of the RX RUNT
+ */
+#define UMAC_MIB_STAT_OFFSET		0xc
+
+#define UMAC_MIB_CTRL			0x580
+#define  MIB_RX_CNT_RST			(1 << 0)
+#define  MIB_RUNT_CNT_RST		(1 << 1)
+#define  MIB_TX_CNT_RST			(1 << 2)
+
+#define UMAC_MPD_CTRL			0x620
+#define  MPD_EN				(1 << 0)
+#define  MSEQ_LEN_SHIFT			16
+#define  MSEQ_LEN_MASK			0xff
+#define  PSW_EN				(1 << 27)
+
+#define UMAC_PSW_MS			0x624
+#define UMAC_PSW_LS			0x628
+#define UMAC_MDF_CTRL			0x650
+#define UMAC_MDF_ADDR			0x654
+
+/* Receive DMA offset and defines */
+#define SYS_PORT_RDMA_OFFSET		0x2000
+
+#define RDMA_CONTROL			0x1000
+#define  RDMA_EN			(1 << 0)
+#define  RDMA_RING_CFG			(1 << 1)
+#define  RDMA_DISC_EN			(1 << 2)
+#define  RDMA_BUF_DATA_OFFSET_SHIFT	4
+#define  RDMA_BUF_DATA_OFFSET_MASK	0x3ff
+
+#define RDMA_STATUS			0x1004
+#define  RDMA_DISABLED			(1 << 0)
+#define  RDMA_DESC_RAM_INIT_BUSY	(1 << 1)
+#define  RDMA_BP_STATUS			(1 << 2)
+
+#define RDMA_SCB_BURST_SIZE		0x1008
+
+#define RDMA_RING_BUF_SIZE		0x100c
+#define  RDMA_RING_SIZE_SHIFT		16
+
+#define RDMA_WRITE_PTR_HI		0x1010
+#define RDMA_WRITE_PTR_LO		0x1014
+#define RDMA_PROD_INDEX			0x1018
+#define  RDMA_PROD_INDEX_MASK		0xffff
+
+#define RDMA_CONS_INDEX			0x101c
+#define  RDMA_CONS_INDEX_MASK		0xffff
+
+#define RDMA_START_ADDR_HI		0x1020
+#define RDMA_START_ADDR_LO		0x1024
+#define RDMA_END_ADDR_HI		0x1028
+#define RDMA_END_ADDR_LO		0x102c
+
+#define RDMA_MBDONE_INTR		0x1030
+#define  RDMA_INTR_THRESH_MASK		0x1ff
+#define  RDMA_TIMEOUT_SHIFT		16
+#define  RDMA_TIMEOUT_MASK		0xffff
+
+#define RDMA_XON_XOFF_THRESH		0x1034
+#define  RDMA_XON_XOFF_THRESH_MASK	0xffff
+#define  RDMA_XOFF_THRESH_SHIFT		16
+
+#define RDMA_READ_PTR_HI		0x1038
+#define RDMA_READ_PTR_LO		0x103c
+
+#define RDMA_OVERRIDE			0x1040
+#define  RDMA_LE_MODE			(1 << 0)
+#define  RDMA_REG_MODE			(1 << 1)
+
+#define RDMA_TEST			0x1044
+#define  RDMA_TP_OUT_SEL		(1 << 0)
+#define  RDMA_MEM_SEL			(1 << 1)
+
+#define RDMA_DEBUG			0x1048
+
+/* Transmit DMA offset and defines */
+#define TDMA_NUM_RINGS			32	/* rings = queues */
+#define TDMA_PORT_SIZE			DESC_SIZE /* two 32-bits words */
+
+#define SYS_PORT_TDMA_OFFSET		0x4000
+#define TDMA_WRITE_PORT_OFFSET		0x0000
+#define TDMA_WRITE_PORT_HI(i)		(TDMA_WRITE_PORT_OFFSET + \
+					(i) * TDMA_PORT_SIZE)
+#define TDMA_WRITE_PORT_LO(i)		(TDMA_WRITE_PORT_OFFSET + \
+					sizeof(u32) + (i) * TDMA_PORT_SIZE)
+
+#define TDMA_READ_PORT_OFFSET		(TDMA_WRITE_PORT_OFFSET + \
+					(TDMA_NUM_RINGS * TDMA_PORT_SIZE))
+#define TDMA_READ_PORT_HI(i)		(TDMA_READ_PORT_OFFSET + \
+					(i) * TDMA_PORT_SIZE)
+#define TDMA_READ_PORT_LO(i)		(TDMA_READ_PORT_OFFSET + \
+					sizeof(u32) + (i) * TDMA_PORT_SIZE)
+
+#define TDMA_READ_PORT_CMD_OFFSET	(TDMA_READ_PORT_OFFSET + \
+					(TDMA_NUM_RINGS * TDMA_PORT_SIZE))
+#define TDMA_READ_PORT_CMD(i)		(TDMA_READ_PORT_CMD_OFFSET + \
+					(i) * sizeof(u32))
+
+#define TDMA_DESC_RING_00_BASE		(TDMA_READ_PORT_CMD_OFFSET + \
+					(TDMA_NUM_RINGS * sizeof(u32)))
+
+/* Register offsets and defines relatives to a specific ring number */
+#define RING_HEAD_TAIL_PTR		0x00
+#define  RING_HEAD_MASK			0x7ff
+#define  RING_TAIL_SHIFT		11
+#define  RING_TAIL_MASK			0x7ff
+#define  RING_FLUSH			(1 << 24)
+#define  RING_EN			(1 << 25)
+
+#define RING_COUNT			0x04
+#define  RING_COUNT_MASK		0x7ff
+#define  RING_BUFF_DONE_SHIFT		11
+#define  RING_BUFF_DONE_MASK		0x7ff
+
+#define RING_MAX_HYST			0x08
+#define  RING_MAX_THRESH_MASK		0x7ff
+#define  RING_HYST_THRESH_SHIFT		11
+#define  RING_HYST_THRESH_MASK		0x7ff
+
+#define RING_INTR_CONTROL		0x0c
+#define  RING_INTR_THRESH_MASK		0x7ff
+#define  RING_EMPTY_INTR_EN		(1 << 15)
+#define  RING_TIMEOUT_SHIFT		16
+#define  RING_TIMEOUT_MASK		0xffff
+
+#define RING_PROD_CONS_INDEX		0x10
+#define  RING_PROD_INDEX_MASK		0xffff
+#define  RING_CONS_INDEX_SHIFT		16
+#define  RING_CONS_INDEX_MASK		0xffff
+
+#define RING_MAPPING			0x14
+#define  RING_QID_MASK			0x3
+#define  RING_PORT_ID_SHIFT		3
+#define  RING_PORT_ID_MASK		0x7
+#define  RING_IGNORE_STATUS		(1 << 6)
+#define  RING_FAILOVER_EN		(1 << 7)
+#define  RING_CREDIT_SHIFT		8
+#define  RING_CREDIT_MASK		0xffff
+
+#define RING_PCP_DEI_VID		0x18
+#define  RING_VID_MASK			0x7ff
+#define  RING_DEI			(1 << 12)
+#define  RING_PCP_SHIFT			13
+#define  RING_PCP_MASK			0x7
+#define  RING_PKT_SIZE_ADJ_SHIFT	16
+#define  RING_PKT_SIZE_ADJ_MASK		0xf
+
+#define TDMA_DESC_RING_SIZE		28
+
+/* Defininition for a given TX ring base address */
+#define TDMA_DESC_RING_BASE(i)		(TDMA_DESC_RING_00_BASE + \
+					((i) * TDMA_DESC_RING_SIZE))
+
+/* Ring indexed register addreses */
+#define TDMA_DESC_RING_HEAD_TAIL_PTR(i)	(TDMA_DESC_RING_BASE(i) + \
+					RING_HEAD_TAIL_PTR)
+#define TDMA_DESC_RING_COUNT(i)		(TDMA_DESC_RING_BASE(i) + \
+					RING_COUNT)
+#define TDMA_DESC_RING_MAX_HYST(i)	(TDMA_DESC_RING_BASE(i) + \
+					RING_MAX_HYST)
+#define TDMA_DESC_RING_INTR_CONTROL(i)	(TDMA_DESC_RING_BASE(i) + \
+					RING_INTR_CONTROL)
+#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
+					(TDMA_DESC_RING_BASE(i) + \
+					RING_PROD_CONS_INDEX)
+#define TDMA_DESC_RING_MAPPING(i)	(TDMA_DESC_RING_BASE(i) + \
+					RING_MAPPING)
+#define TDMA_DESC_RING_PCP_DEI_VID(i)	(TDMA_DESC_RING_BASE(i) + \
+					RING_PCP_DEI_VID)
+
+#define TDMA_CONTROL			0x600
+#define  TDMA_EN			(1 << 0)
+#define  TSB_EN				(1 << 1)
+#define  TSB_SWAP			(1 << 2)
+#define  ACB_ALGO			(1 << 3)
+#define  BUF_DATA_OFFSET_SHIFT		4
+#define  BUF_DATA_OFFSET_MASK		0x3ff
+#define  VLAN_EN			(1 << 14)
+#define  SW_BRCM_TAG			(1 << 15)
+#define  WNC_KPT_SIZE_UPDATE		(1 << 16)
+#define  SYNC_PKT_SIZE			(1 << 17)
+#define  ACH_TXDONE_DELAY_SHIFT		18
+#define  ACH_TXDONE_DELAY_MASK		0xff
+
+#define TDMA_STATUS			0x604
+#define  TDMA_DISABLED			(1 << 0)
+#define  TDMA_LL_RAM_INIT_BUSY		(1 << 1)
+
+#define TDMA_SCB_BURST_SIZE		0x608
+#define TDMA_OVER_MAX_THRESH_STATUS	0x60c
+#define TDMA_OVER_HYST_THRESH_STATUS	0x610
+#define TDMA_TPID			0x614
+
+#define TDMA_FREE_LIST_HEAD_TAIL_PTR	0x618
+#define  TDMA_FREE_HEAD_MASK		0x7ff
+#define  TDMA_FREE_TAIL_SHIFT		11
+#define  TDMA_FREE_TAIL_MASK		0x7ff
+
+#define TDMA_FREE_LIST_COUNT		0x61c
+#define  TDMA_FREE_LIST_COUNT_MASK	0x7ff
+
+#define TDMA_TIER2_ARB_CTRL		0x620
+#define  TDMA_ARB_MODE_RR		0
+#define  TDMA_ARB_MODE_WEIGHT_RR	0x1
+#define  TDMA_ARB_MODE_STRICT		0x2
+#define  TDMA_ARB_MODE_DEFICIT_RR	0x3
+#define  TDMA_CREDIT_SHIFT		4
+#define  TDMA_CREDIT_MASK		0xffff
+
+#define TDMA_TIER1_ARB_0_CTRL		0x624
+#define  TDMA_ARB_EN			(1 << 0)
+
+#define TDMA_TIER1_ARB_0_QUEUE_EN	0x628
+#define TDMA_TIER1_ARB_1_CTRL		0x62c
+#define TDMA_TIER1_ARB_1_QUEUE_EN	0x630
+#define TDMA_TIER1_ARB_2_CTRL		0x634
+#define TDMA_TIER1_ARB_2_QUEUE_EN	0x638
+#define TDMA_TIER1_ARB_3_CTRL		0x63c
+#define TDMA_TIER1_ARB_3_QUEUE_EN	0x640
+
+#define TDMA_SCB_ENDIAN_OVERRIDE	0x644
+#define  TDMA_LE_MODE			(1 << 0)
+#define  TDMA_REG_MODE			(1 << 1)
+
+#define TDMA_TEST			0x648
+#define  TDMA_TP_OUT_SEL		(1 << 0)
+#define  TDMA_MEM_TM			(1 << 1)
+
+#define TDMA_DEBUG			0x64c
+
+/* Transmit/Receive descriptor */
+struct dma_desc {
+	u32	addr_status_len;
+	u32	addr_lo;
+};
+
+/* Number of Receive hardware descriptor words */
+#define NUM_HW_RX_DESC_WORDS		1024
+/* Real number of usable descriptors */
+#define NUM_RX_DESC			(NUM_HW_RX_DESC_WORDS / WORDS_PER_DESC)
+
+/* Internal linked-list RAM has up to 1536 entries */
+#define NUM_TX_DESC			1536
+
+#define WORDS_PER_DESC			(sizeof(struct dma_desc) / sizeof(u32))
+
+/* Rx/Tx common counter group.*/
+struct bcm_sysport_pkt_counters {
+	u32	cnt_64;		/* RO Received/Transmited 64 bytes packet */
+	u32	cnt_127;	/* RO Rx/Tx 127 bytes packet */
+	u32	cnt_255;	/* RO Rx/Tx 65-255 bytes packet */
+	u32	cnt_511;	/* RO Rx/Tx 256-511 bytes packet */
+	u32	cnt_1023;	/* RO Rx/Tx 512-1023 bytes packet */
+	u32	cnt_1518;	/* RO Rx/Tx 1024-1518 bytes packet */
+	u32	cnt_mgv;	/* RO Rx/Tx 1519-1522 good VLAN packet */
+	u32	cnt_2047;	/* RO Rx/Tx 1522-2047 bytes packet*/
+	u32	cnt_4095;	/* RO Rx/Tx 2048-4095 bytes packet*/
+	u32	cnt_9216;	/* RO Rx/Tx 4096-9216 bytes packet*/
+};
+
+/* RSV, Receive Status Vector */
+struct bcm_sysport_rx_counters {
+	struct  bcm_sysport_pkt_counters pkt_cnt;
+	u32	pkt;		/* RO (0x428) Received pkt count*/
+	u32	bytes;		/* RO Received byte count */
+	u32	mca;		/* RO # of Received multicast pkt */
+	u32	bca;		/* RO # of Receive broadcast pkt */
+	u32	fcs;		/* RO # of Received FCS error  */
+	u32	cf;		/* RO # of Received control frame pkt*/
+	u32	pf;		/* RO # of Received pause frame pkt */
+	u32	uo;		/* RO # of unknown op code pkt */
+	u32	aln;		/* RO # of alignment error count */
+	u32	flr;		/* RO # of frame length out of range count */
+	u32	cde;		/* RO # of code error pkt */
+	u32	fcr;		/* RO # of carrier sense error pkt */
+	u32	ovr;		/* RO # of oversize pkt*/
+	u32	jbr;		/* RO # of jabber count */
+	u32	mtue;		/* RO # of MTU error pkt*/
+	u32	pok;		/* RO # of Received good pkt */
+	u32	uc;		/* RO # of unicast pkt */
+	u32	ppp;		/* RO # of PPP pkt */
+	u32	rcrc;		/* RO (0x470),# of CRC match pkt */
+};
+
+/* TSV, Transmit Status Vector */
+struct bcm_sysport_tx_counters {
+	struct bcm_sysport_pkt_counters pkt_cnt;
+	u32	pkts;		/* RO (0x4a8) Transmited pkt */
+	u32	mca;		/* RO # of xmited multicast pkt */
+	u32	bca;		/* RO # of xmited broadcast pkt */
+	u32	pf;		/* RO # of xmited pause frame count */
+	u32	cf;		/* RO # of xmited control frame count */
+	u32	fcs;		/* RO # of xmited FCS error count */
+	u32	ovr;		/* RO # of xmited oversize pkt */
+	u32	drf;		/* RO # of xmited deferral pkt */
+	u32	edf;		/* RO # of xmited Excessive deferral pkt*/
+	u32	scl;		/* RO # of xmited single collision pkt */
+	u32	mcl;		/* RO # of xmited multiple collision pkt*/
+	u32	lcl;		/* RO # of xmited late collision pkt */
+	u32	ecl;		/* RO # of xmited excessive collision pkt*/
+	u32	frg;		/* RO # of xmited fragments pkt*/
+	u32	ncl;		/* RO # of xmited total collision count */
+	u32	jbr;		/* RO # of xmited jabber count*/
+	u32	bytes;		/* RO # of xmited byte count */
+	u32	pok;		/* RO # of xmited good pkt */
+	u32	uc;		/* RO (0x0x4f0)# of xmited unitcast pkt */
+};
+
+struct bcm_sysport_mib {
+	struct bcm_sysport_rx_counters rx;
+	struct bcm_sysport_tx_counters tx;
+	u32 rx_runt_cnt;
+	u32 rx_runt_fcs;
+	u32 rx_runt_fcs_align;
+	u32 rx_runt_bytes;
+	u32 rxchk_bad_csum;
+	u32 rxchk_other_pkt_disc;
+	u32 rbuf_ovflow_cnt;
+	u32 rbuf_err_cnt;
+	u32 alloc_rx_buff_failed;
+	u32 rx_dma_failed;
+	u32 tx_dma_failed;
+};
+
+/* HW maintains a large list of counters */
+enum bcm_sysport_stat_type {
+	BCM_SYSPORT_STAT_NETDEV = -1,
+	BCM_SYSPORT_STAT_MIB_RX,
+	BCM_SYSPORT_STAT_MIB_TX,
+	BCM_SYSPORT_STAT_RUNT,
+	BCM_SYSPORT_STAT_RXCHK,
+	BCM_SYSPORT_STAT_RBUF,
+	BCM_SYSPORT_STAT_SOFT,
+};
+
+/* Macros to help define ethtool statistics */
+#define STAT_NETDEV(m) { \
+	.stat_string = __stringify(m), \
+	.stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
+	.stat_offset = offsetof(struct net_device_stats, m), \
+	.type = BCM_SYSPORT_STAT_NETDEV, \
+}
+
+#define STAT_MIB(str, m, _type) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
+	.stat_offset = offsetof(struct bcm_sysport_priv, m), \
+	.type = _type, \
+}
+
+#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
+#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
+#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
+#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
+
+#define STAT_RXCHK(str, m, ofs) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
+	.stat_offset = offsetof(struct bcm_sysport_priv, m), \
+	.type = BCM_SYSPORT_STAT_RXCHK, \
+	.reg_offset = ofs, \
+}
+
+#define STAT_RBUF(str, m, ofs) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
+	.stat_offset = offsetof(struct bcm_sysport_priv, m), \
+	.type = BCM_SYSPORT_STAT_RBUF, \
+	.reg_offset = ofs, \
+}
+
+struct bcm_sysport_stats {
+	char stat_string[ETH_GSTRING_LEN];
+	int stat_sizeof;
+	int stat_offset;
+	enum bcm_sysport_stat_type type;
+	/* reg offset from UMAC base for misc counters */
+	u16 reg_offset;
+};
+
+/* Software house keeping helper structure */
+struct bcm_sysport_cb {
+	struct sk_buff	*skb;		/* SKB for RX packets */
+	void __iomem	*bd_addr;	/* Buffer descriptor PHYS addr */
+	DEFINE_DMA_UNMAP_ADDR(dma_addr);/* DMA cookie */
+	DEFINE_DMA_UNMAP_LEN(dma_len);	/* DMA length */
+};
+
+/* Software view of the TX ring */
+struct bcm_sysport_tx_ring {
+	spinlock_t	lock;		/* Ring lock for tx reclaim/xmit */
+	dma_addr_t	desc_dma;	/* DMA cookie */
+	unsigned int	index;		/* Ring index */
+	unsigned int	size;		/* Ring current size */
+	unsigned int	alloc_size;	/* Ring one-time allocated size */
+	unsigned int	desc_count;	/* Number of descriptors */
+	unsigned int	curr_desc;	/* Current descriptor */
+	unsigned int	c_index;	/* Last consumer index */
+	unsigned int	p_index;	/* Current producer index */
+	struct bcm_sysport_cb *cbs;	/* Transmit control blocks */
+	struct dma_desc	*desc_cpu;	/* CPU view of the descriptor */
+};
+
+/* Driver private structure */
+struct bcm_sysport_priv {
+	void __iomem		*base;
+	u32			irq0_stat;
+	u32			irq0_mask;
+	u32			irq1_stat;
+	u32			irq1_mask;
+	struct napi_struct	napi ____cacheline_aligned;
+	struct net_device	*netdev;
+	struct platform_device	*pdev;
+	int			irq0;
+	int			irq1;
+	int			wol_irq;
+
+	/* Transmit rings */
+	struct bcm_sysport_tx_ring tx_rings[TDMA_NUM_RINGS];
+
+	/* Receive queue */
+	void __iomem		*rx_bds;
+	struct bcm_sysport_cb	*rx_cbs;
+	unsigned int		num_rx_bds;
+	unsigned int		rx_read_ptr;
+	unsigned int		rx_c_index;
+
+	/* PHY device */
+	struct device_node	*phy_dn;
+	struct phy_device	*phydev;
+	phy_interface_t		phy_interface;
+	int			old_pause;
+	int			old_link;
+	int			old_duplex;
+
+	/* Misc fields */
+	unsigned int		rx_chk_en:1;
+	unsigned int		tsb_en:1;
+	unsigned int		crc_fwd:1;
+	u16			rev;
+	u32			wolopts;
+	unsigned int		wol_irq_disabled:1;
+	struct clk		*clk;
+
+	/* MIB related fields */
+	struct bcm_sysport_mib	mib;
+
+	/* Ethtool */
+	u32			msg_enable;
+};
+#endif /* __BCM_SYSPORT_H */
diff --git a/drivers/net/ethernet/broadcom/genet/Makefile b/drivers/net/ethernet/broadcom/genet/Makefile
new file mode 100644
index 000000000000..9b6885efa9e7
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_BCMGENET) += genet.o
+genet-objs := bcmgenet.o bcmmii.o bcmgenet_wol.o
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
new file mode 100644
index 000000000000..8a91a3d784b8
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
@@ -0,0 +1,3461 @@
+/*
+ * Copyright (c) 2002-2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ * File Name  : bcmgenet.c
+ *
+ * Description: This is Linux driver for the Broadcom GENET ethernet MAC core.
+
+*/
+
+#define pr_fmt(fmt)				"bcmgenet: " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/if_ether.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <net/arp.h>
+
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/phy.h>
+#include <linux/platform_data/bcmgenet.h>
+
+#include <asm/unaligned.h>
+
+#include "bcmgenet.h"
+
+/* Maximum number of hardware queues, downsized if needed */
+#define GENET_MAX_MQ_CNT	4
+
+/* Default highest priority queue for multi queue support */
+#define GENET_Q0_PRIORITY	0
+
+#define GENET_DEFAULT_BD_CNT	\
+	(TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
+
+#define RX_BUF_LENGTH		2048
+#define SKB_ALIGNMENT		32
+#define HFB_ARP_LEN		21
+
+/* Tx/Rx DMA register offset, skip 256 descriptors */
+#define WORDS_PER_BD(p)		(p->hw_params->words_per_bd)
+#define DMA_DESC_SIZE		(WORDS_PER_BD(priv) * sizeof(u32))
+
+#define GENET_TDMA_REG_OFF	(priv->hw_params->tdma_offset + \
+				TOTAL_DESC * DMA_DESC_SIZE)
+
+#define GENET_RDMA_REG_OFF	(priv->hw_params->rdma_offset + \
+				TOTAL_DESC * DMA_DESC_SIZE)
+
+static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
+						void __iomem *d, u32 value)
+{
+	__raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
+}
+
+static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
+						void __iomem *d)
+{
+	return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
+}
+
+static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
+				    void __iomem *d,
+				    dma_addr_t addr)
+{
+	__raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
+
+	/* Register writes to GISB bus can take couple hundred nanoseconds
+	 * and are done for each packet, save these expensive writes unless
+	 * the platform is explicitly configured for 64-bits/LPAE.
+	 */
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	if (priv->hw_params->flags & GENET_HAS_40BITS)
+		__raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
+#endif
+}
+
+/* Combined address + length/status setter */
+static inline void dmadesc_set(struct bcmgenet_priv *priv,
+				void __iomem *d, dma_addr_t addr, u32 val)
+{
+	dmadesc_set_addr(priv, d, addr);
+	dmadesc_set_length_status(priv, d, val);
+}
+
+static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
+					  void __iomem *d)
+{
+	dma_addr_t addr;
+
+	addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
+
+	/* Register writes to GISB bus can take couple hundred nanoseconds
+	 * and are done for each packet, save these expensive writes unless
+	 * the platform is explicitly configured for 64-bits/LPAE.
+	 */
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	if (priv->hw_params->flags & GENET_HAS_40BITS)
+		addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
+#endif
+	return addr;
+}
+
+#define GENET_VER_FMT	"%1d.%1d EPHY: 0x%04x"
+
+#define GENET_MSG_DEFAULT	(NETIF_MSG_DRV | NETIF_MSG_PROBE | \
+				NETIF_MSG_LINK)
+
+static int debug = -1;
+module_param(debug, int, 0);
+MODULE_PARM_DESC(debug, "GENET debug level");
+
+enum bcmgenet_version __genet_get_version(struct bcmgenet_priv *priv)
+{
+	return priv->version;
+}
+
+static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
+{
+	if (GENET_IS_V1(priv))
+		return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
+	else
+		return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
+}
+
+static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
+{
+	if (GENET_IS_V1(priv))
+		bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
+	else
+		bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
+}
+
+/* These macros are defined to deal with register map change
+ * between GENET1.1 and GENET2. Only those currently being used
+ * by driver are defined.
+ */
+static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
+{
+	if (GENET_IS_V1(priv))
+		return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
+	else
+		return __raw_readl(priv->base +
+				priv->hw_params->tbuf_offset + TBUF_CTRL);
+}
+
+static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
+{
+	if (GENET_IS_V1(priv))
+		bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
+	else
+		__raw_writel(val, priv->base +
+				priv->hw_params->tbuf_offset + TBUF_CTRL);
+}
+
+static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
+{
+	if (GENET_IS_V1(priv))
+		return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
+	else
+		return __raw_readl(priv->base +
+				priv->hw_params->tbuf_offset + TBUF_BP_MC);
+}
+
+static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
+{
+	if (GENET_IS_V1(priv))
+		bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
+	else
+		__raw_writel(val, priv->base +
+				priv->hw_params->tbuf_offset + TBUF_BP_MC);
+}
+
+/* RX/TX DMA register accessors */
+enum dma_reg {
+	DMA_RING_CFG = 0,
+	DMA_CTRL,
+	DMA_STATUS,
+	DMA_SCB_BURST_SIZE,
+	DMA_ARB_CTRL,
+	DMA_PRIORITY,
+	DMA_RING_PRIORITY,
+	DMA_PRIORITY_0,
+	DMA_PRIORITY_1,
+	DMA_PRIORITY_2,
+	DMA_INDEX2RING_0,
+	DMA_INDEX2RING_1,
+	DMA_INDEX2RING_2,
+	DMA_INDEX2RING_3,
+	DMA_INDEX2RING_4,
+	DMA_INDEX2RING_5,
+	DMA_INDEX2RING_6,
+	DMA_INDEX2RING_7,
+	DMA_RING0_TIMEOUT,
+	DMA_RING1_TIMEOUT,
+	DMA_RING2_TIMEOUT,
+	DMA_RING3_TIMEOUT,
+	DMA_RING4_TIMEOUT,
+	DMA_RING5_TIMEOUT,
+	DMA_RING6_TIMEOUT,
+	DMA_RING7_TIMEOUT,
+	DMA_RING8_TIMEOUT,
+	DMA_RING9_TIMEOUT,
+	DMA_RING10_TIMEOUT,
+	DMA_RING11_TIMEOUT,
+	DMA_RING12_TIMEOUT,
+	DMA_RING13_TIMEOUT,
+	DMA_RING14_TIMEOUT,
+	DMA_RING15_TIMEOUT,
+	DMA_RING16_TIMEOUT,
+};
+
+static const u8 bcmgenet_dma_regs_v3plus[] = {
+	[DMA_RING_CFG]		= 0x00,
+	[DMA_CTRL]		= 0x04,
+	[DMA_STATUS]		= 0x08,
+	[DMA_SCB_BURST_SIZE]	= 0x0C,
+	[DMA_ARB_CTRL]		= 0x2C,
+	[DMA_PRIORITY]		= 0x30,
+	[DMA_RING_PRIORITY]	= 0x38,
+	[DMA_PRIORITY_0]	= 0x30,
+	[DMA_PRIORITY_1]	= 0x34,
+	[DMA_PRIORITY_2]	= 0x38,
+	[DMA_RING0_TIMEOUT]	= 0x2C,
+	[DMA_RING1_TIMEOUT]	= 0x30,
+	[DMA_RING2_TIMEOUT]	= 0x34,
+	[DMA_RING3_TIMEOUT]	= 0x38,
+	[DMA_RING4_TIMEOUT]	= 0x3c,
+	[DMA_RING5_TIMEOUT]	= 0x40,
+	[DMA_RING6_TIMEOUT]	= 0x44,
+	[DMA_RING7_TIMEOUT]	= 0x48,
+	[DMA_RING8_TIMEOUT]	= 0x4c,
+	[DMA_RING9_TIMEOUT]	= 0x50,
+	[DMA_RING10_TIMEOUT]	= 0x54,
+	[DMA_RING11_TIMEOUT]	= 0x58,
+	[DMA_RING12_TIMEOUT]	= 0x5c,
+	[DMA_RING13_TIMEOUT]	= 0x60,
+	[DMA_RING14_TIMEOUT]	= 0x64,
+	[DMA_RING15_TIMEOUT]	= 0x68,
+	[DMA_RING16_TIMEOUT]	= 0x6C,
+	[DMA_INDEX2RING_0]	= 0x70,
+	[DMA_INDEX2RING_1]	= 0x74,
+	[DMA_INDEX2RING_2]	= 0x78,
+	[DMA_INDEX2RING_3]	= 0x7C,
+	[DMA_INDEX2RING_4]	= 0x80,
+	[DMA_INDEX2RING_5]	= 0x84,
+	[DMA_INDEX2RING_6]	= 0x88,
+	[DMA_INDEX2RING_7]	= 0x8C,
+};
+
+static const u8 bcmgenet_dma_regs_v2[] = {
+	[DMA_RING_CFG]		= 0x00,
+	[DMA_CTRL]		= 0x04,
+	[DMA_STATUS]		= 0x08,
+	[DMA_SCB_BURST_SIZE]	= 0x0C,
+	[DMA_ARB_CTRL]		= 0x30,
+	[DMA_PRIORITY]		= 0x34,
+	[DMA_RING_PRIORITY]	= 0x3C,
+	[DMA_PRIORITY_0]	= 0x34,
+	[DMA_PRIORITY_1]	= 0x38,
+	[DMA_PRIORITY_2]	= 0x3C,
+	[DMA_RING0_TIMEOUT]	= 0x2C,
+	[DMA_RING1_TIMEOUT]	= 0x30,
+	[DMA_RING2_TIMEOUT]	= 0x34,
+	[DMA_RING3_TIMEOUT]	= 0x38,
+	[DMA_RING4_TIMEOUT]	= 0x3c,
+	[DMA_RING5_TIMEOUT]	= 0x40,
+	[DMA_RING6_TIMEOUT]	= 0x44,
+	[DMA_RING7_TIMEOUT]	= 0x48,
+	[DMA_RING8_TIMEOUT]	= 0x4c,
+	[DMA_RING9_TIMEOUT]	= 0x50,
+	[DMA_RING10_TIMEOUT]	= 0x54,
+	[DMA_RING11_TIMEOUT]	= 0x58,
+	[DMA_RING12_TIMEOUT]	= 0x5c,
+	[DMA_RING13_TIMEOUT]	= 0x60,
+	[DMA_RING14_TIMEOUT]	= 0x64,
+	[DMA_RING15_TIMEOUT]	= 0x68,
+	[DMA_RING16_TIMEOUT]	= 0x6C,
+};
+
+static const u8 bcmgenet_dma_regs_v1[] = {
+	[DMA_CTRL]		= 0x00,
+	[DMA_STATUS]		= 0x04,
+	[DMA_SCB_BURST_SIZE]	= 0x0C,
+	[DMA_ARB_CTRL]		= 0x30,
+	[DMA_PRIORITY]		= 0x34,
+	[DMA_RING_PRIORITY]	= 0x3C,
+	[DMA_PRIORITY_0]	= 0x34,
+	[DMA_PRIORITY_1]	= 0x38,
+	[DMA_PRIORITY_2]	= 0x3C,
+	[DMA_RING0_TIMEOUT]	= 0x2C,
+	[DMA_RING1_TIMEOUT]	= 0x30,
+	[DMA_RING2_TIMEOUT]	= 0x34,
+	[DMA_RING3_TIMEOUT]	= 0x38,
+	[DMA_RING4_TIMEOUT]	= 0x3c,
+	[DMA_RING5_TIMEOUT]	= 0x40,
+	[DMA_RING6_TIMEOUT]	= 0x44,
+	[DMA_RING7_TIMEOUT]	= 0x48,
+	[DMA_RING8_TIMEOUT]	= 0x4c,
+	[DMA_RING9_TIMEOUT]	= 0x50,
+	[DMA_RING10_TIMEOUT]	= 0x54,
+	[DMA_RING11_TIMEOUT]	= 0x58,
+	[DMA_RING12_TIMEOUT]	= 0x5c,
+	[DMA_RING13_TIMEOUT]	= 0x60,
+	[DMA_RING14_TIMEOUT]	= 0x64,
+	[DMA_RING15_TIMEOUT]	= 0x68,
+	[DMA_RING16_TIMEOUT]	= 0x6C,
+};
+
+/* Set at runtime once bcmgenet version is known */
+static const u8 *bcmgenet_dma_regs;
+
+static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
+{
+	return netdev_priv(dev_get_drvdata(dev));
+}
+
+static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
+					enum dma_reg r)
+{
+	return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
+			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
+}
+
+static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
+					u32 val, enum dma_reg r)
+{
+	__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
+			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
+}
+
+static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
+					enum dma_reg r)
+{
+	return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
+			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
+}
+
+static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
+					u32 val, enum dma_reg r)
+{
+	__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
+			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
+}
+
+/* RDMA/TDMA ring registers and accessors
+ * we merge the common fields and just prefix with T/D the registers
+ * having different meaning depending on the direction
+ */
+enum dma_ring_reg {
+	TDMA_READ_PTR = 0,
+	RDMA_WRITE_PTR = TDMA_READ_PTR,
+	TDMA_READ_PTR_HI,
+	RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
+	TDMA_CONS_INDEX,
+	RDMA_PROD_INDEX = TDMA_CONS_INDEX,
+	TDMA_PROD_INDEX,
+	RDMA_CONS_INDEX = TDMA_PROD_INDEX,
+	DMA_RING_BUF_SIZE,
+	DMA_START_ADDR,
+	DMA_START_ADDR_HI,
+	DMA_END_ADDR,
+	DMA_END_ADDR_HI,
+	DMA_MBUF_DONE_THRESH,
+	TDMA_FLOW_PERIOD,
+	RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
+	TDMA_WRITE_PTR,
+	RDMA_READ_PTR = TDMA_WRITE_PTR,
+	TDMA_WRITE_PTR_HI,
+	RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
+};
+
+/* GENET v4 supports 40-bits pointer addressing
+ * for obvious reasons the LO and HI word parts
+ * are contiguous, but this offsets the other
+ * registers.
+ */
+static const u8 genet_dma_ring_regs_v4[] = {
+	[TDMA_READ_PTR]			= 0x00,
+	[TDMA_READ_PTR_HI]		= 0x04,
+	[TDMA_CONS_INDEX]		= 0x08,
+	[TDMA_PROD_INDEX]		= 0x0C,
+	[DMA_RING_BUF_SIZE]		= 0x10,
+	[DMA_START_ADDR]		= 0x14,
+	[DMA_START_ADDR_HI]		= 0x18,
+	[DMA_END_ADDR]			= 0x1C,
+	[DMA_END_ADDR_HI]		= 0x20,
+	[DMA_MBUF_DONE_THRESH]		= 0x24,
+	[TDMA_FLOW_PERIOD]		= 0x28,
+	[TDMA_WRITE_PTR]		= 0x2C,
+	[TDMA_WRITE_PTR_HI]		= 0x30,
+};
+
+static const u8 genet_dma_ring_regs_v123[] = {
+	[TDMA_READ_PTR]			= 0x00,
+	[TDMA_CONS_INDEX]		= 0x04,
+	[TDMA_PROD_INDEX]		= 0x08,
+	[DMA_RING_BUF_SIZE]		= 0x0C,
+	[DMA_START_ADDR]		= 0x10,
+	[DMA_END_ADDR]			= 0x14,
+	[DMA_MBUF_DONE_THRESH]		= 0x18,
+	[TDMA_FLOW_PERIOD]		= 0x1C,
+	[TDMA_WRITE_PTR]		= 0x20,
+};
+
+/* Set at runtime once GENET version is known */
+static const u8 *genet_dma_ring_regs;
+
+static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
+						unsigned int ring,
+						enum dma_ring_reg r)
+{
+	return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
+			(DMA_RING_SIZE * ring) +
+			genet_dma_ring_regs[r]);
+}
+
+static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
+						unsigned int ring,
+						u32 val,
+						enum dma_ring_reg r)
+{
+	__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
+			(DMA_RING_SIZE * ring) +
+			genet_dma_ring_regs[r]);
+}
+
+static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
+						unsigned int ring,
+						enum dma_ring_reg r)
+{
+	return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
+			(DMA_RING_SIZE * ring) +
+			genet_dma_ring_regs[r]);
+}
+
+static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
+						unsigned int ring,
+						u32 val,
+						enum dma_ring_reg r)
+{
+	__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
+			(DMA_RING_SIZE * ring) +
+			genet_dma_ring_regs[r]);
+}
+
+static int bcmgenet_begin(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	/* Turn on the clock */
+	return clk_prepare_enable(priv->clk);
+}
+
+static void bcmgenet_complete(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	/* Turn off the clock */
+	clk_disable_unprepare(priv->clk);
+}
+
+static int bcmgenet_get_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	return phy_ethtool_gset(priv->phydev, cmd);
+}
+
+static int bcmgenet_set_settings(struct net_device *dev,
+		struct ethtool_cmd *cmd)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	return phy_ethtool_sset(priv->phydev, cmd);
+}
+
+static int bcmgenet_set_rx_csum(struct net_device *dev,
+				netdev_features_t wanted)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 rbuf_chk_ctrl;
+	bool rx_csum_en;
+
+	rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
+
+	rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
+
+	/* enable rx checksumming */
+	if (rx_csum_en)
+		rbuf_chk_ctrl |= RBUF_RXCHK_EN;
+	else
+		rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
+	priv->desc_rxchk_en = rx_csum_en;
+
+	/* If UniMAC forwards CRC, we need to skip over it to get
+	 * a valid CHK bit to be set in the per-packet status word
+	 */
+	if (rx_csum_en && priv->crc_fwd_en)
+		rbuf_chk_ctrl |= RBUF_SKIP_FCS;
+	else
+		rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
+
+	bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
+
+	return 0;
+}
+static int bcmgenet_set_tx_csum(struct net_device *dev,
+				netdev_features_t wanted)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	bool desc_64b_en;
+	u32 tbuf_ctrl, rbuf_ctrl;
+
+	tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
+	rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
+
+	desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
+
+	/* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
+	if (desc_64b_en) {
+		tbuf_ctrl |= RBUF_64B_EN;
+		rbuf_ctrl |= RBUF_64B_EN;
+	} else {
+		tbuf_ctrl &= ~RBUF_64B_EN;
+		rbuf_ctrl &= ~RBUF_64B_EN;
+	}
+	priv->desc_64b_en = desc_64b_en;
+
+	bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
+	bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
+	return 0;
+}
+
+static int bcmgenet_set_features(struct net_device *dev,
+		netdev_features_t features)
+{
+	netdev_features_t changed = features ^ dev->features;
+	netdev_features_t wanted = dev->wanted_features;
+	int ret = 0;
+
+	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
+		ret = bcmgenet_set_tx_csum(dev, wanted);
+	if (changed & (NETIF_F_RXCSUM))
+		ret = bcmgenet_set_rx_csum(dev, wanted);
+
+	return ret;
+}
+
+static u32 bcmgenet_get_msglevel(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	return priv->msg_enable;
+}
+
+static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	priv->msg_enable = level;
+}
+
+static int bcmgenet_get_coalesce(struct net_device *dev,
+				 struct ethtool_coalesce *ec)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	ec->tx_max_coalesced_frames =
+		bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
+					 DMA_MBUF_DONE_THRESH);
+	ec->rx_max_coalesced_frames =
+		bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
+					 DMA_MBUF_DONE_THRESH);
+	ec->rx_coalesce_usecs =
+		bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
+
+	return 0;
+}
+
+static int bcmgenet_set_coalesce(struct net_device *dev,
+				 struct ethtool_coalesce *ec)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	unsigned int i;
+	u32 reg;
+
+	/* Base system clock is 125Mhz, DMA timeout is this reference clock
+	 * divided by 1024, which yields roughly 8.192us, our maximum value
+	 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
+	 */
+	if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
+	    ec->tx_max_coalesced_frames == 0 ||
+	    ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
+	    ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
+		return -EINVAL;
+
+	if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
+		return -EINVAL;
+
+	/* GENET TDMA hardware does not support a configurable timeout, but will
+	 * always generate an interrupt either after MBDONE packets have been
+	 * transmitted, or when the ring is empty.
+	 */
+	if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
+	    ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
+		return -EOPNOTSUPP;
+
+	/* Program all TX queues with the same values, as there is no
+	 * ethtool knob to do coalescing on a per-queue basis
+	 */
+	for (i = 0; i < priv->hw_params->tx_queues; i++)
+		bcmgenet_tdma_ring_writel(priv, i,
+					  ec->tx_max_coalesced_frames,
+					  DMA_MBUF_DONE_THRESH);
+	bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
+				  ec->tx_max_coalesced_frames,
+				  DMA_MBUF_DONE_THRESH);
+
+	for (i = 0; i < priv->hw_params->rx_queues; i++) {
+		bcmgenet_rdma_ring_writel(priv, i,
+					  ec->rx_max_coalesced_frames,
+					  DMA_MBUF_DONE_THRESH);
+
+		reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
+		reg &= ~DMA_TIMEOUT_MASK;
+		reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
+		bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
+	}
+
+	bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
+				  ec->rx_max_coalesced_frames,
+				  DMA_MBUF_DONE_THRESH);
+
+	reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
+	reg &= ~DMA_TIMEOUT_MASK;
+	reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
+	bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
+
+	return 0;
+}
+
+static void bcmgenet_get_pauseparam(struct net_device *dev,
+				struct ethtool_pauseparam *epause)
+{
+	struct bcmgenet_priv *priv;
+	u32 umac_cmd;
+
+	priv = netdev_priv(dev);
+
+	epause->autoneg = !!(priv->pause_flags & BCM_PAUSE_FLAG_AUTO);
+
+	if (priv->old_link > 0) {
+		/* report active state when link is up */
+		umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
+		epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
+		epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
+	} else {
+		/* otherwise report stored settings */
+		epause->rx_pause = !!(priv->pause_flags & BCM_PAUSE_FLAG_RX);
+		epause->tx_pause = !!(priv->pause_flags & BCM_PAUSE_FLAG_TX);
+	}
+}
+
+static int bcmgenet_set_pauseparam(struct net_device *dev,
+				struct ethtool_pauseparam *epause)
+{
+	struct bcmgenet_priv *priv;
+	unsigned int pause_flags = 0;
+	int ret;
+
+	priv = netdev_priv(dev);
+
+	/* Pass parameters to the PHY level to set proper advertisement */
+	ret = bcmgenet_phy_ethtool_set_pauseparam(priv->phydev, epause);
+	if (ret)
+		return ret;
+
+	if (epause->rx_pause)
+		pause_flags |= BCM_PAUSE_FLAG_RX;
+	if (epause->tx_pause)
+		pause_flags |= BCM_PAUSE_FLAG_TX;
+	if (epause->autoneg)
+		pause_flags |= BCM_PAUSE_FLAG_AUTO;
+
+	priv->pause_flags = pause_flags;
+
+	/* Restart the PHY */
+	if (netif_running(dev)) {
+		priv->old_link = -1;
+		phy_start_aneg(priv->phydev);
+	}
+
+	return 0;
+}
+
+/* standard ethtool support functions. */
+enum bcmgenet_stat_type {
+	BCMGENET_STAT_NETDEV = -1,
+	BCMGENET_STAT_MIB_RX,
+	BCMGENET_STAT_MIB_TX,
+	BCMGENET_STAT_RUNT,
+	BCMGENET_STAT_MISC,
+};
+
+struct bcmgenet_stats {
+	char stat_string[ETH_GSTRING_LEN];
+	int stat_sizeof;
+	int stat_offset;
+	enum bcmgenet_stat_type type;
+	/* reg offset from UMAC base for misc counters */
+	u16 reg_offset;
+};
+
+#define STAT_NETDEV(m) { \
+	.stat_string = __stringify(m), \
+	.stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
+	.stat_offset = offsetof(struct net_device_stats, m), \
+	.type = BCMGENET_STAT_NETDEV, \
+}
+
+#define STAT_GENET_MIB(str, m, _type) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
+	.stat_offset = offsetof(struct bcmgenet_priv, m), \
+	.type = _type, \
+}
+
+#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
+#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
+#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
+
+#define STAT_GENET_MISC(str, m, offset) { \
+	.stat_string = str, \
+	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
+	.stat_offset = offsetof(struct bcmgenet_priv, m), \
+	.type = BCMGENET_STAT_MISC, \
+	.reg_offset = offset, \
+}
+
+
+/* There is a 0xC gap between the end of RX and beginning of TX stats and then
+ * between the end of TX stats and the beginning of the RX RUNT
+ */
+#define BCMGENET_STAT_OFFSET	0xc
+
+/* Hardware counters must be kept in sync because the order/offset
+ * is important here (order in structure declaration = order in hardware)
+ */
+static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
+	/* general stats */
+	STAT_NETDEV(rx_packets),
+	STAT_NETDEV(tx_packets),
+	STAT_NETDEV(rx_bytes),
+	STAT_NETDEV(tx_bytes),
+	STAT_NETDEV(rx_errors),
+	STAT_NETDEV(tx_errors),
+	STAT_NETDEV(rx_dropped),
+	STAT_NETDEV(tx_dropped),
+	STAT_NETDEV(multicast),
+	/* UniMAC RSV counters */
+	STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
+	STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
+	STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
+	STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
+	STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
+	STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
+	STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
+	STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
+	STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
+	STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
+	STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
+	STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
+	STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
+	STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
+	STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
+	STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
+	STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
+	STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
+	STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
+	STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
+	STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
+	STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
+	STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
+	STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
+	STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
+	STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
+	STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
+	STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
+	STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
+	/* UniMAC TSV counters */
+	STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
+	STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
+	STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
+	STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
+	STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
+	STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
+	STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
+	STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
+	STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
+	STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
+	STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
+	STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
+	STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
+	STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
+	STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
+	STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
+	STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
+	STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
+	STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
+	STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
+	STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
+	STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
+	STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
+	STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
+	STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
+	STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
+	STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
+	STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
+	STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
+	/* UniMAC RUNT counters */
+	STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
+	STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
+	STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
+	STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
+	/* Misc UniMAC counters */
+	STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
+			UMAC_RBUF_OVFL_CNT),
+	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
+	STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
+	STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
+	STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
+	STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
+};
+
+#define BCMGENET_STATS_LEN	ARRAY_SIZE(bcmgenet_gstrings_stats)
+
+static void bcmgenet_get_drvinfo(struct net_device *dev,
+		struct ethtool_drvinfo *info)
+{
+	strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
+	strlcpy(info->version, VER_STR, sizeof(info->version));
+	info->n_stats = BCMGENET_STATS_LEN;
+
+}
+
+static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
+{
+	switch (string_set) {
+	case ETH_SS_STATS:
+		return BCMGENET_STATS_LEN;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static void bcmgenet_get_strings(struct net_device *dev,
+				u32 stringset, u8 *data)
+{
+	int i;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+			memcpy(data + i * ETH_GSTRING_LEN,
+				bcmgenet_gstrings_stats[i].stat_string,
+				ETH_GSTRING_LEN);
+		}
+		break;
+	}
+}
+
+static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
+{
+	int i, j = 0;
+
+	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+		const struct bcmgenet_stats *s;
+		u32 val = 0;
+		char *p;
+		u8 offset = 0;
+
+		s = &bcmgenet_gstrings_stats[i];
+		switch (s->type) {
+		case BCMGENET_STAT_NETDEV:
+			continue;
+		case BCMGENET_STAT_MIB_RX:
+		case BCMGENET_STAT_MIB_TX:
+		case BCMGENET_STAT_RUNT:
+			if (s->type != BCMGENET_STAT_MIB_RX)
+				offset = BCMGENET_STAT_OFFSET;
+			val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
+								j + offset);
+			break;
+		case BCMGENET_STAT_MISC:
+			val = bcmgenet_umac_readl(priv, s->reg_offset);
+			/* clear if overflowed */
+			if (val == ~0)
+				bcmgenet_umac_writel(priv, 0, s->reg_offset);
+			break;
+		}
+
+		j += s->stat_sizeof;
+		p = (char *)priv + s->stat_offset;
+		*(u32 *)p = val;
+	}
+}
+
+static void bcmgenet_get_ethtool_stats(struct net_device *dev,
+					struct ethtool_stats *stats,
+					u64 *data)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	int i;
+
+	if (netif_running(dev))
+		bcmgenet_update_mib_counters(priv);
+
+	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
+		const struct bcmgenet_stats *s;
+		char *p;
+
+		s = &bcmgenet_gstrings_stats[i];
+		if (s->type == BCMGENET_STAT_NETDEV)
+			p = (char *)&dev->stats;
+		else
+			p = (char *)priv;
+		p += s->stat_offset;
+		data[i] = *(u32 *)p;
+	}
+}
+
+static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
+	u32 reg;
+
+	if (enable && !priv->clk_eee_enabled) {
+		clk_prepare_enable(priv->clk_eee);
+		priv->clk_eee_enabled = true;
+	}
+
+	reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
+	if (enable)
+		reg |= EEE_EN;
+	else
+		reg &= ~EEE_EN;
+	bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
+
+	/* Enable EEE and switch to a 27Mhz clock automatically */
+	reg = __raw_readl(priv->base + off);
+	if (enable)
+		reg |= TBUF_EEE_EN | TBUF_PM_EN;
+	else
+		reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
+	__raw_writel(reg, priv->base + off);
+
+	/* Do the same for thing for RBUF */
+	reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
+	if (enable)
+		reg |= RBUF_EEE_EN | RBUF_PM_EN;
+	else
+		reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
+	bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
+
+	if (!enable && priv->clk_eee_enabled) {
+		clk_disable_unprepare(priv->clk_eee);
+		priv->clk_eee_enabled = false;
+	}
+
+	priv->eee.eee_enabled = enable;
+	priv->eee.eee_active = enable;
+}
+
+static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct ethtool_eee *p = &priv->eee;
+
+	if (GENET_IS_V1(priv))
+		return -EOPNOTSUPP;
+
+	e->eee_enabled = p->eee_enabled;
+	e->eee_active = p->eee_active;
+	e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
+
+	return phy_ethtool_get_eee(priv->phydev, e);
+}
+
+static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct ethtool_eee *p = &priv->eee;
+	int ret = 0;
+
+	if (GENET_IS_V1(priv))
+		return -EOPNOTSUPP;
+
+	p->eee_enabled = e->eee_enabled;
+
+	if (!p->eee_enabled) {
+		bcmgenet_eee_enable_set(dev, false);
+	} else {
+		ret = phy_init_eee(priv->phydev, 0);
+		if (ret) {
+			netif_err(priv, hw, dev, "EEE initialization failed\n");
+			return ret;
+		}
+
+		bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
+		bcmgenet_eee_enable_set(dev, true);
+	}
+
+	return phy_ethtool_set_eee(priv->phydev, e);
+}
+
+static int bcmgenet_nway_reset(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	return genphy_restart_aneg(priv->phydev);
+}
+
+/* standard ethtool support functions. */
+static struct ethtool_ops bcmgenet_ethtool_ops = {
+	.begin			= bcmgenet_begin,
+	.complete		= bcmgenet_complete,
+	.get_strings		= bcmgenet_get_strings,
+	.get_sset_count		= bcmgenet_get_sset_count,
+	.get_ethtool_stats	= bcmgenet_get_ethtool_stats,
+	.get_settings		= bcmgenet_get_settings,
+	.set_settings		= bcmgenet_set_settings,
+	.get_drvinfo		= bcmgenet_get_drvinfo,
+	.get_wol		= bcmgenet_get_wol,
+	.set_wol		= bcmgenet_set_wol,
+	.get_link		= ethtool_op_get_link,
+	.get_msglevel		= bcmgenet_get_msglevel,
+	.set_msglevel		= bcmgenet_set_msglevel,
+	.get_eee		= bcmgenet_get_eee,
+	.set_eee		= bcmgenet_set_eee,
+	.nway_reset		= bcmgenet_nway_reset,
+	.get_coalesce		= bcmgenet_get_coalesce,
+	.set_coalesce		= bcmgenet_set_coalesce,
+	.get_pauseparam		= bcmgenet_get_pauseparam,
+	.set_pauseparam		= bcmgenet_set_pauseparam,
+};
+
+/* Power down the unimac, based on mode. */
+static int bcmgenet_power_down(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode)
+{
+	struct net_device *dev;
+	u32 reg;
+	int ret = 0;
+
+	dev = priv->dev;
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+		reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+		reg |= (EXT_PWR_DOWN_PHY |
+			EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+
+		/* Workaround for putting EPHY in iddq mode. */
+		if (priv->phydev->drv->suspend)
+			ret = priv->phydev->drv->suspend(priv->phydev);
+		if (ret)
+			pr_warn("failed to suspend PHY\n");
+
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		ret = bcmgenet_wol_power_down_cfg(priv, mode);
+		break;
+
+	case GENET_POWER_PASSIVE:
+		/* Power down LED */
+		if (priv->hw_params->flags & GENET_HAS_EXT) {
+			reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+			reg |= (EXT_PWR_DOWN_PHY |
+				EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
+			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+
+			bcmgenet_phy_power_set(priv->dev, false);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static void bcmgenet_power_up(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode)
+{
+	u32 reg;
+
+	switch (mode) {
+	case GENET_POWER_CABLE_SENSE:
+#if 0
+		priv->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_DLL;
+		priv->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_PHY;
+		priv->ext->ext_pwr_mgmt &= ~EXT_PWR_DOWN_BIAS;
+#endif
+		/* enable APD */
+		if (priv->hw_params->flags & GENET_HAS_EXT) {
+			reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+			reg |= EXT_PWR_DN_EN_LD;
+			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+		}
+		break;
+	case GENET_POWER_WOL_MAGIC:
+		bcmgenet_wol_power_up_cfg(priv, mode);
+		break;
+	case GENET_POWER_PASSIVE:
+		if (priv->hw_params->flags & GENET_HAS_EXT) {
+			reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+			reg &= ~EXT_PWR_DOWN_DLL;
+			reg &= ~EXT_PWR_DOWN_PHY;
+			reg &= ~EXT_PWR_DOWN_BIAS;
+			/* enable APD */
+			reg |= EXT_PWR_DN_EN_LD;
+			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+			bcmgenet_phy_power_set(priv->dev, true);
+		}
+	default:
+		break;
+	}
+}
+
+/* ioctl handle special commands that are not present in ethtool. */
+static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	if (!netif_running(dev))
+		return -EINVAL;
+
+	return phy_mii_ioctl(priv->phydev, rq, cmd);
+}
+
+static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
+					 struct bcmgenet_tx_ring *ring)
+{
+	struct enet_cb *tx_cb_ptr;
+
+	tx_cb_ptr = ring->cbs;
+	tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
+	tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
+	/* Advancing local write pointer */
+	if (ring->write_ptr == ring->end_ptr)
+		ring->write_ptr = ring->cb_ptr;
+	else
+		ring->write_ptr++;
+
+	return tx_cb_ptr;
+}
+
+/* Simple helper to free a control block's resources */
+static void bcmgenet_free_cb(struct enet_cb *cb)
+{
+	dev_kfree_skb_any(cb->skb);
+	cb->skb = NULL;
+	dma_unmap_addr_set(cb, dma_addr, 0);
+}
+
+static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
+						  struct bcmgenet_tx_ring *ring)
+{
+	bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
+			INTRL2_CPU_MASK_SET);
+}
+
+static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
+						 struct bcmgenet_tx_ring *ring)
+{
+	bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
+			INTRL2_CPU_MASK_CLEAR);
+}
+
+static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
+						struct bcmgenet_tx_ring *ring)
+{
+	bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
+				 INTRL2_CPU_MASK_CLEAR);
+}
+
+static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
+						struct bcmgenet_tx_ring *ring)
+{
+	bcmgenet_intrl2_1_writel(priv, (1 << ring->index), INTRL2_CPU_MASK_SET);
+}
+
+/* Unlocked version of the reclaim routine */
+static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
+					struct bcmgenet_tx_ring *ring)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	int last_c_index, num_tx_bds;
+	struct enet_cb *tx_cb_ptr;
+	unsigned int pkts_compl = 0;
+	unsigned int bytes_compl = 0;
+	unsigned int c_index;
+	unsigned int txbds_ready;
+	unsigned int txbds_processed = 0;
+
+	/* Clear status before servicing to reduce spurious interrupts */
+	if (ring->index == DESC_INDEX)
+		bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
+					 INTRL2_CPU_CLEAR);
+	else
+		bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
+					 INTRL2_CPU_CLEAR);
+
+	/* Compute how many buffers are transmitted since last xmit call */
+	c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
+
+	last_c_index = ring->c_index;
+	num_tx_bds = ring->size;
+
+	c_index &= (num_tx_bds - 1);
+
+	if (c_index >= last_c_index)
+		txbds_ready = c_index - last_c_index;
+	else
+		txbds_ready = num_tx_bds - last_c_index + c_index;
+
+	netif_dbg(priv, tx_done, dev,
+			"%s index=%d c_index=%d "
+			"txbds_ready=%d tx_last_c_index=%d\n",
+			__func__, ring->index,
+			c_index, txbds_ready, last_c_index);
+
+	/* Reclaim transmitted buffers */
+	while (txbds_processed < txbds_ready) {
+		tx_cb_ptr = ring->cbs + last_c_index;
+		if (tx_cb_ptr->skb) {
+			pkts_compl++;
+			bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
+			dma_unmap_single(kdev,
+					dma_unmap_addr(tx_cb_ptr, dma_addr),
+					dma_unmap_len(tx_cb_ptr, dma_len),
+					DMA_TO_DEVICE);
+			bcmgenet_free_cb(tx_cb_ptr);
+		} else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
+			dma_unmap_page(kdev,
+					dma_unmap_addr(tx_cb_ptr, dma_addr),
+					dma_unmap_len(tx_cb_ptr, dma_len),
+					DMA_TO_DEVICE);
+			dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
+		}
+		txbds_processed++;
+
+		last_c_index++;
+		last_c_index &= (num_tx_bds - 1);
+	}
+
+	ring->free_bds += txbds_processed;
+	ring->c_index = c_index;
+
+	dev->stats.tx_packets += pkts_compl;
+	dev->stats.tx_bytes += bytes_compl;
+
+	return txbds_processed;
+}
+
+static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
+				struct bcmgenet_tx_ring *ring)
+{
+	unsigned int released;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ring->lock, flags);
+	released = __bcmgenet_tx_reclaim(dev, ring);
+	spin_unlock_irqrestore(&ring->lock, flags);
+
+	return released;
+}
+
+static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
+{
+	struct bcmgenet_tx_ring *ring =
+		container_of(napi, struct bcmgenet_tx_ring, napi);
+	unsigned int work_done = 0;
+	struct netdev_queue *txq;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ring->lock, flags);
+	work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
+	if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
+		txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
+		netif_tx_wake_queue(txq);
+	}
+	spin_unlock_irqrestore(&ring->lock, flags);
+
+	if (work_done == 0) {
+		napi_complete(napi);
+		ring->int_enable(ring->priv, ring);
+
+		return 0;
+	}
+
+	return budget;
+}
+
+static void bcmgenet_tx_reclaim_all(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	int i;
+
+	if (netif_is_multiqueue(dev)) {
+		for (i = 0; i < priv->hw_params->tx_queues; i++)
+			bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
+	}
+
+	bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
+}
+
+/* Transmits a single SKB (either head of a fragment or a single SKB)
+ * caller must hold priv->lock
+ */
+static int bcmgenet_xmit_single(struct net_device *dev,
+				struct sk_buff *skb,
+				u16 dma_desc_flags,
+				struct bcmgenet_tx_ring *ring)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	struct enet_cb *tx_cb_ptr;
+	unsigned int skb_len;
+	dma_addr_t mapping;
+	u32 length_status;
+	int ret;
+
+	tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
+
+	if (unlikely(!tx_cb_ptr))
+		BUG();
+
+	tx_cb_ptr->skb = skb;
+
+	skb_len = skb_headlen(skb);
+
+	mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
+	ret = dma_mapping_error(kdev, mapping);
+	if (ret) {
+		priv->mib.tx_dma_failed++;
+		netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
+		dev_kfree_skb(skb);
+		return ret;
+	}
+
+	dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
+	dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
+	length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
+			(priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
+			DMA_TX_APPEND_CRC;
+
+	if (skb->ip_summed == CHECKSUM_PARTIAL)
+		length_status |= DMA_TX_DO_CSUM;
+
+	dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
+
+	/* Decrement total BD count and advance our write pointer */
+	ring->free_bds -= 1;
+	ring->prod_index += 1;
+	ring->prod_index &= DMA_P_INDEX_MASK;
+
+	return 0;
+}
+
+/* Transmit a SKB fragment */
+static int bcmgenet_xmit_frag(struct net_device *dev,
+				skb_frag_t *frag,
+				u16 dma_desc_flags,
+				struct bcmgenet_tx_ring *ring)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	struct enet_cb *tx_cb_ptr;
+	unsigned int frag_size;
+	dma_addr_t mapping;
+	int ret;
+
+	tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
+
+	if (unlikely(!tx_cb_ptr))
+		BUG();
+	tx_cb_ptr->skb = NULL;
+
+	frag_size = skb_frag_size(frag);
+
+	mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
+	ret = dma_mapping_error(kdev, mapping);
+	if (ret) {
+		priv->mib.tx_dma_failed++;
+		netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
+				__func__);
+		/*TODO: Handle frag failure.*/
+		return ret;
+	}
+
+	dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
+	dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
+
+	dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
+			(frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
+			(priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
+
+
+	ring->free_bds -= 1;
+	ring->prod_index += 1;
+	ring->prod_index &= DMA_P_INDEX_MASK;
+
+	return 0;
+}
+
+/* Reallocate the SKB to put enough headroom in front of it and insert
+ * the transmit checksum offsets in the descriptors
+ */
+static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
+					    struct sk_buff *skb)
+{
+	struct status_64 *status = NULL;
+	struct sk_buff *new_skb;
+	u16 offset;
+	u8 ip_proto;
+	u16 ip_ver;
+	u32 tx_csum_info;
+
+	if (unlikely(skb_headroom(skb) < sizeof(*status))) {
+		/* If 64 byte status block enabled, must make sure skb has
+		 * enough headroom for us to insert 64B status block.
+		 */
+		new_skb = skb_realloc_headroom(skb, sizeof(*status));
+		dev_kfree_skb(skb);
+		if (!new_skb) {
+			dev->stats.tx_errors++;
+			dev->stats.tx_dropped++;
+			return NULL;
+		}
+		skb = new_skb;
+	}
+
+	skb_push(skb, sizeof(*status));
+	status = (struct status_64 *)skb->data;
+
+	if (skb->ip_summed  == CHECKSUM_PARTIAL) {
+		ip_ver = htons(skb->protocol);
+		switch (ip_ver) {
+		case ETH_P_IP:
+			ip_proto = ip_hdr(skb)->protocol;
+			break;
+		case ETH_P_IPV6:
+			ip_proto = ipv6_hdr(skb)->nexthdr;
+			break;
+		default:
+			return skb;
+		}
+
+		offset = skb_checksum_start_offset(skb) - sizeof(*status);
+		tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
+				(offset + skb->csum_offset);
+
+		/* Set the length valid bit for TCP and UDP and just set
+		 * the special UDP flag for IPv4, else just set to 0.
+		 */
+		if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
+			tx_csum_info |= STATUS_TX_CSUM_LV;
+			if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
+				tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
+		} else
+			tx_csum_info = 0;
+
+		status->tx_csum_info = tx_csum_info;
+	}
+
+	return skb;
+}
+
+static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct bcmgenet_tx_ring *ring;
+	struct netdev_queue *txq;
+	int i;
+	unsigned long flags;
+	int nr_frags, index;
+	u16 dma_desc_flags;
+	int ret;
+
+	index = skb_get_queue_mapping(skb);
+	/* Mapping strategy:
+	 * queue_mapping = 0, unclassified, packet xmited through ring16
+	 * queue_mapping = 1, goes to ring 0. (highest priority queue
+	 * queue_mapping = 2, goes to ring 1.
+	 * queue_mapping = 3, goes to ring 2.
+	 * queue_mapping = 4, goes to ring 3.
+	 */
+	if (index == 0)
+		index = DESC_INDEX;
+	else
+		index -= 1;
+
+	ring = &priv->tx_rings[index];
+	txq = netdev_get_tx_queue(dev, ring->queue);
+
+	nr_frags = skb_shinfo(skb)->nr_frags;
+
+	spin_lock_irqsave(&ring->lock, flags);
+	if (ring->free_bds <= (nr_frags + 1)) {
+		if (!netif_tx_queue_stopped(txq)) {
+			netif_tx_stop_queue(txq);
+			netdev_err(dev,
+				   "%s: tx ring %d full when queue %d awake\n",
+				   __func__, index, ring->queue);
+		}
+		ret = NETDEV_TX_BUSY;
+		goto out;
+	}
+
+	/* reclaim xmited skb every 8 packets. */
+	if (ring->free_bds < ring->size - 8)
+		__bcmgenet_tx_reclaim(dev, ring);
+
+	if (skb_padto(skb, ETH_ZLEN)) {
+		ret = NETDEV_TX_OK;
+		goto out;
+	}
+
+	/* Retain how many bytes will be sent on the wire, without TSB inserted
+	 * by transmit checksum offload
+	 */
+	GENET_CB(skb)->bytes_sent = skb->len;
+
+	/* set the SKB transmit checksum */
+	if (priv->desc_64b_en) {
+		skb = bcmgenet_put_tx_csum(dev, skb);
+		if (!skb) {
+			ret = NETDEV_TX_OK;
+			goto out;
+		}
+	}
+
+	dma_desc_flags = DMA_SOP;
+	if (nr_frags == 0)
+		dma_desc_flags |= DMA_EOP;
+
+	/* Transmit single SKB or head of fragment list */
+	ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
+	if (ret) {
+		ret = NETDEV_TX_OK;
+		goto out;
+	}
+
+	/* xmit fragment */
+	for (i = 0; i < nr_frags; i++) {
+		/*TODO: Handle frag failure.*/
+		ret = bcmgenet_xmit_frag(dev,
+				&skb_shinfo(skb)->frags[i],
+				(i == nr_frags - 1) ? DMA_EOP : 0, ring);
+		if (ret) {
+			ret = NETDEV_TX_OK;
+			goto out;
+		}
+	}
+
+	if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
+		netif_tx_stop_queue(txq);
+	}
+
+	/* we kept a software copy of how much we should advance the TDMA
+	 * producer index, now write it down to the hardware
+	 */
+	bcmgenet_tdma_ring_writel(priv, ring->index,
+			ring->prod_index, TDMA_PROD_INDEX);
+out:
+	spin_unlock_irqrestore(&ring->lock, flags);
+
+	return ret;
+}
+
+static void bcmgenet_align_skb(struct sk_buff *skb)
+{
+	/* We need the data buffer to be aligned to a 32 bytes boundary.
+	 * We will reserve as many bytes as needed to align the data
+	 * properly. On most GENET versions, this is just a no-op since
+	 * our L1 cache line size is large enough to force this alignment
+	 */
+	skb_reserve(skb, SKB_ALIGNMENT -
+			(((unsigned long)skb->data) & (SKB_ALIGNMENT - 1)));
+}
+
+static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
+				struct enet_cb *cb)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct sk_buff *skb;
+	dma_addr_t mapping;
+	int ret;
+
+	skb = netdev_alloc_skb(priv->dev,
+				priv->rx_buf_len + SKB_ALIGNMENT);
+	if (!skb)
+		return -ENOMEM;
+
+	bcmgenet_align_skb(skb);
+
+	/* a caller did not release this control block */
+	WARN_ON(cb->skb != NULL);
+
+	cb->skb = skb;
+	mapping = dma_map_single(kdev, skb->data,
+			priv->rx_buf_len, DMA_FROM_DEVICE);
+	ret = dma_mapping_error(kdev, mapping);
+	if (ret) {
+		priv->mib.rx_dma_failed++;
+		bcmgenet_free_cb(cb);
+		netif_err(priv, rx_err, priv->dev,
+				"%s DMA map failed\n", __func__);
+		return ret;
+	}
+
+	dma_unmap_addr_set(cb, dma_addr, mapping);
+	/* assign packet, prepare descriptor, and advance pointer */
+
+	dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
+
+	/* turn on the newly assigned BD for DMA to use */
+	priv->rx_bd_assign_index++;
+	priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
+
+	priv->rx_bd_assign_ptr = priv->rx_bds +
+		(priv->rx_bd_assign_index * DMA_DESC_SIZE);
+
+	return 0;
+}
+
+/* bcmgenet_desc_rx - descriptor based rx process.
+ * this could be called from bottom half, or from NAPI polling method.
+ */
+static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
+				     unsigned int budget)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct net_device *dev = priv->dev;
+	struct enet_cb *cb;
+	struct sk_buff *skb;
+	u32 dma_length_status;
+	unsigned long dma_flag;
+	int len, err;
+	unsigned int rxpktprocessed = 0, rxpkttoprocess;
+	unsigned int p_index;
+	unsigned int chksum_ok = 0;
+
+	/* Clear status before servicing to reduce spurious interrupts */
+	bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
+				 INTRL2_CPU_CLEAR);
+
+	p_index = bcmgenet_rdma_ring_readl(priv,
+			DESC_INDEX, RDMA_PROD_INDEX);
+	p_index &= DMA_P_INDEX_MASK;
+
+	if (p_index < priv->rx_c_index)
+		rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
+			priv->rx_c_index + p_index;
+	else
+		rxpkttoprocess = p_index - priv->rx_c_index;
+
+	netif_dbg(priv, rx_status, dev,
+		"RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
+
+	while ((rxpktprocessed < rxpkttoprocess) &&
+			(rxpktprocessed < budget)) {
+
+		/* Unmap the packet contents such that we can use the
+		 * RSV from the 64 bytes descriptor when enabled and save
+		 * a 32-bits register read
+		 */
+		cb = &priv->rx_cbs[priv->rx_read_ptr];
+		skb = cb->skb;
+
+		/* We do not have a backing SKB, so we do not have a
+		 * corresponding DMA mapping for this incoming packet since
+		 * bcmgenet_rx_refill always either has both skb and mapping or
+		 * none.
+		 */
+		if (unlikely(!skb)) {
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+			goto refill;
+		}
+
+		dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
+				priv->rx_buf_len, DMA_FROM_DEVICE);
+
+		if (!priv->desc_64b_en) {
+			dma_length_status = dmadesc_get_length_status(priv,
+							priv->rx_bds +
+							(priv->rx_read_ptr *
+							 DMA_DESC_SIZE));
+		} else {
+			struct status_64 *status;
+			status = (struct status_64 *)skb->data;
+			dma_length_status = status->length_status;
+		}
+
+		/* DMA flags and length are still valid no matter how
+		 * we got the Receive Status Vector (64B RSB or register)
+		 */
+		dma_flag = dma_length_status & 0xffff;
+		len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
+
+		netif_dbg(priv, rx_status, dev,
+			"%s:p_index=%d c_index=%d read_ptr=%d "
+			"len_stat=0x%08x\n",
+			__func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
+			dma_length_status);
+
+		if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
+			netif_err(priv, rx_status, dev,
+					"Dropping fragmented packet!\n");
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+			dev_kfree_skb_any(cb->skb);
+			cb->skb = NULL;
+			goto refill;
+		}
+		/* report errors */
+		if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
+						DMA_RX_OV |
+						DMA_RX_NO |
+						DMA_RX_LG |
+						DMA_RX_RXER))) {
+			netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
+						(unsigned int)dma_flag);
+			if (dma_flag & DMA_RX_CRC_ERROR)
+				dev->stats.rx_crc_errors++;
+			if (dma_flag & DMA_RX_OV)
+				dev->stats.rx_over_errors++;
+			if (dma_flag & DMA_RX_NO)
+				dev->stats.rx_frame_errors++;
+			if (dma_flag & DMA_RX_LG)
+				dev->stats.rx_length_errors++;
+			dev->stats.rx_dropped++;
+			dev->stats.rx_errors++;
+
+			/* discard the packet and advance consumer index.*/
+			dev_kfree_skb_any(cb->skb);
+			cb->skb = NULL;
+			goto refill;
+		} /* error packet */
+
+		chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
+				priv->desc_rxchk_en;
+
+		skb_put(skb, len);
+		if (priv->desc_64b_en) {
+			skb_pull(skb, 64);
+			len -= 64;
+		}
+
+		if (likely(chksum_ok))
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+		/* remove hardware 2bytes added for IP alignment */
+		skb_pull(skb, 2);
+		len -= 2;
+
+		if (priv->crc_fwd_en) {
+			skb_trim(skb, len - ETH_FCS_LEN);
+			len -= ETH_FCS_LEN;
+		}
+
+		/*Finish setting up the received SKB and send it to the kernel*/
+		skb->protocol = eth_type_trans(skb, priv->dev);
+		dev->stats.rx_packets++;
+		dev->stats.rx_bytes += len;
+		if (dma_flag & DMA_RX_MULT)
+			dev->stats.multicast++;
+
+		/* Notify kernel */
+		napi_gro_receive(&priv->napi, skb);
+		cb->skb = NULL;
+		netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
+
+		/* refill RX path on the current control block */
+refill:
+		err = bcmgenet_rx_refill(priv, cb);
+		if (err) {
+			priv->mib.alloc_rx_buff_failed++;
+			netif_err(priv, rx_err, dev, "Rx refill failed\n");
+		}
+
+		rxpktprocessed++;
+		priv->rx_read_ptr++;
+		priv->rx_read_ptr &= (priv->num_rx_bds - 1);
+	}
+
+	return rxpktprocessed;
+}
+
+/* Rx NAPI polling method*/
+static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
+{
+	struct bcmgenet_priv *priv = container_of(napi,
+			struct bcmgenet_priv, napi);
+	unsigned int work_done;
+
+	work_done = bcmgenet_desc_rx(priv, budget);
+	/* Advancing our consumer index*/
+	priv->rx_c_index += work_done;
+	priv->rx_c_index &= DMA_C_INDEX_MASK;
+	bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
+				priv->rx_c_index, RDMA_CONS_INDEX);
+	if (work_done < budget) {
+		napi_complete(napi);
+		bcmgenet_intrl2_0_writel(priv,
+			UMAC_IRQ_RXDMA_DONE, INTRL2_CPU_MASK_CLEAR);
+	}
+
+	return work_done;
+}
+
+/* Assign skb to RX DMA descriptor. */
+static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
+{
+	struct enet_cb *cb;
+	int ret = 0;
+	int i;
+	u32 reg;
+
+	netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
+
+	/* loop here for each buffer needing assign */
+	for (i = 0; i < priv->num_rx_bds; i++) {
+		cb = &priv->rx_cbs[priv->rx_bd_assign_index];
+		if (cb->skb)
+			continue;
+
+		ret = bcmgenet_rx_refill(priv, cb);
+		if (ret)
+			break;
+
+	}
+
+	/* Enable rx DMA incase it was disabled due to running out of rx BD */
+	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
+	reg |= DMA_EN;
+	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
+
+	return ret;
+}
+
+static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct enet_cb *cb;
+	int i;
+
+	for (i = 0; i < priv->num_rx_bds; i++) {
+		cb = &priv->rx_cbs[i];
+
+		if (dma_unmap_addr(cb, dma_addr)) {
+			dma_unmap_single(kdev,
+					dma_unmap_addr(cb, dma_addr),
+					priv->rx_buf_len, DMA_FROM_DEVICE);
+			dma_unmap_addr_set(cb, dma_addr, 0);
+		}
+
+		if (cb->skb)
+			bcmgenet_free_cb(cb);
+	}
+}
+
+static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
+{
+	u32 reg;
+
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	if (enable)
+		reg |= mask;
+	else
+		reg &= ~mask;
+	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+
+	/* UniMAC stops on a packet boundary, wait for a full-size packet
+	 * to be processed
+	 */
+	if (enable == false)
+		usleep_range(1000, 2000);
+}
+
+static int reset_umac(struct bcmgenet_priv *priv)
+{
+	struct device *kdev = &priv->pdev->dev;
+	unsigned int timeout = 0;
+	u32 reg;
+
+	/* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
+	bcmgenet_rbuf_ctrl_set(priv, 0);
+	udelay(10);
+
+	/* disable MAC while updating its registers */
+	bcmgenet_umac_writel(priv, 0, UMAC_CMD);
+
+	/* issue soft reset, wait for it to complete */
+	bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
+	while (timeout++ < 1000) {
+		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+		if (!(reg & CMD_SW_RESET))
+			break;
+		udelay(1);
+	}
+
+	if (timeout == 1000) {
+		dev_err(kdev,
+			"timeout waiting for MAC to come out of reset\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
+{
+	/* Mask all interrupts.*/
+	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
+	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
+	bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
+	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
+	bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+}
+
+/* init_umac: Initializes the uniMac controller */
+static int init_umac(struct bcmgenet_priv *priv)
+{
+	struct device *kdev = &priv->pdev->dev;
+	int ret;
+	u32 reg, cpu_mask_clear = 0;
+
+	dev_dbg(kdev, "bcmgenet: init_umac\n");
+
+	ret = reset_umac(priv);
+	if (ret)
+		return ret;
+
+	bcmgenet_umac_writel(priv, 0, UMAC_CMD);
+	/* clear tx/rx counter */
+	bcmgenet_umac_writel(priv,
+		MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
+	bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
+
+	bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
+	/*
+	 * init rx registers, enable ip header optimization.
+	 */
+	reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
+	reg |= RBUF_ALIGN_2B ;
+	bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
+
+	if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
+		bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
+
+	bcmgenet_intr_disable(priv);
+
+	/* Monitor cable plug/unpluged event for internal PHY */
+	if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+		cpu_mask_clear |= (UMAC_IRQ_LINK_EVENT);
+		/* Turn on ENERGY_DET interrupt in bcmgenet_open()
+		 * TODO: fix me for active standby.
+		 */
+	} else if (priv->ext_phy) {
+		cpu_mask_clear |= (UMAC_IRQ_LINK_EVENT);
+	} else if (priv->phy_type == BRCM_PHY_TYPE_MOCA) {
+		if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
+			cpu_mask_clear |= UMAC_IRQ_LINK_EVENT;
+
+		reg = bcmgenet_bp_mc_get(priv);
+		reg |= BIT(priv->hw_params->bp_in_en_shift);
+
+		/* bp_mask: back pressure mask */
+		if (netif_is_multiqueue(priv->dev))
+			reg |= priv->hw_params->bp_in_mask;
+		else
+			reg &= ~priv->hw_params->bp_in_mask;
+		bcmgenet_bp_mc_set(priv, reg);
+	}
+
+	/* Enable MDIO interrupts on GENET v3+ */
+	if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
+		cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
+
+	bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
+		INTRL2_CPU_MASK_CLEAR);
+
+	/* Enable rx/tx engine.*/
+	dev_dbg(kdev, "done init umac\n");
+
+	return 0;
+}
+
+/* Initialize all house-keeping variables for a TX ring, along
+ * with corresponding hardware registers
+ */
+static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
+				  unsigned int index, unsigned int size,
+				  unsigned int write_ptr, unsigned int end_ptr)
+{
+	struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
+	u32 words_per_bd = WORDS_PER_BD(priv);
+	u32 flow_period_val = 0;
+	unsigned int first_bd;
+
+	spin_lock_init(&ring->lock);
+	ring->priv = priv;
+	ring->index = index;
+	if (index == DESC_INDEX) {
+		ring->queue = 0;
+		ring->int_enable = bcmgenet_tx_ring16_int_enable;
+		ring->int_disable = bcmgenet_tx_ring16_int_disable;
+	} else {
+		ring->queue = index + 1;
+		ring->int_enable = bcmgenet_tx_ring_int_enable;
+		ring->int_disable = bcmgenet_tx_ring_int_disable;
+	}
+	ring->cbs = priv->tx_cbs + write_ptr;
+	ring->size = size;
+	ring->c_index = 0;
+	ring->free_bds = size;
+	ring->write_ptr = write_ptr;
+	ring->cb_ptr = write_ptr;
+	ring->end_ptr = end_ptr - 1;
+	ring->prod_index = 0;
+
+	/* Set flow period for ring != 16 */
+	if (index != DESC_INDEX)
+		flow_period_val = ENET_MAX_MTU_SIZE << 16;
+
+	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
+	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
+	bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
+	/* Disable rate control for now */
+	bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
+			TDMA_FLOW_PERIOD);
+	/* Unclassified traffic goes to ring 16 */
+	bcmgenet_tdma_ring_writel(priv, index,
+			((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
+			DMA_RING_BUF_SIZE);
+
+	first_bd = write_ptr;
+
+	/* Set start and end address, read and write pointers */
+	bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
+			DMA_START_ADDR);
+	bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
+			TDMA_READ_PTR);
+	bcmgenet_tdma_ring_writel(priv, index, first_bd,
+			TDMA_WRITE_PTR);
+	bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
+			DMA_END_ADDR);
+
+	netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
+}
+
+/* Initialize a RDMA ring */
+static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
+				  unsigned int index, unsigned int size)
+{
+	u32 words_per_bd = WORDS_PER_BD(priv);
+	int ret;
+
+	priv->num_rx_bds = TOTAL_DESC;
+	priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
+	priv->rx_bd_assign_ptr = priv->rx_bds;
+	priv->rx_bd_assign_index = 0;
+	priv->rx_c_index = 0;
+	priv->rx_read_ptr = 0;
+	priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
+				GFP_KERNEL);
+	if (!priv->rx_cbs)
+		return -ENOMEM;
+
+	ret = bcmgenet_alloc_rx_buffers(priv);
+	if (ret) {
+		kfree(priv->rx_cbs);
+		return ret;
+	}
+
+	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
+	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
+	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
+	bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
+	bcmgenet_rdma_ring_writel(priv, index,
+		((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
+		DMA_RING_BUF_SIZE);
+	bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
+	bcmgenet_rdma_ring_writel(priv, index,
+		words_per_bd * size - 1, DMA_END_ADDR);
+	bcmgenet_rdma_ring_writel(priv, index,
+			(DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
+			DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
+	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
+
+	netif_napi_add(priv->dev, &priv->napi, bcmgenet_rx_poll, 64);
+
+	return ret;
+}
+
+static void bcmgenet_enable_napi(struct bcmgenet_priv *priv)
+{
+	unsigned int i;
+	u32 int0_enable = 0;
+	u32 int1_enable = 0;
+	struct bcmgenet_tx_ring *ring;
+
+	napi_enable(&priv->napi);
+	int0_enable |= UMAC_IRQ_RXDMA_DONE;
+
+	if (netif_is_multiqueue(priv->dev)) {
+		for (i = 0; i < priv->hw_params->tx_queues; ++i) {
+			ring = &priv->tx_rings[i];
+			napi_enable(&ring->napi);
+			int1_enable |= (1 << i);
+		}
+	}
+
+	ring = &priv->tx_rings[DESC_INDEX];
+	napi_enable(&ring->napi);
+	int0_enable |= UMAC_IRQ_TXDMA_DONE;
+
+	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
+	bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
+}
+
+static void bcmgenet_disable_napi(struct bcmgenet_priv *priv)
+{
+	unsigned int i;
+	u32 int0_disable = UMAC_IRQ_RXDMA_DONE | UMAC_IRQ_TXDMA_DONE;
+	u32 int1_disable = 0xffff;
+	struct bcmgenet_tx_ring *ring;
+
+	bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
+	bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
+
+	napi_disable(&priv->napi);
+
+	if (netif_is_multiqueue(priv->dev)) {
+		for (i = 0; i < priv->hw_params->tx_queues; ++i) {
+			ring = &priv->tx_rings[i];
+			napi_disable(&ring->napi);
+		}
+	}
+
+	ring = &priv->tx_rings[DESC_INDEX];
+	napi_disable(&ring->napi);
+}
+
+static void bcmgenet_fini_napi(struct bcmgenet_priv *priv)
+{
+	unsigned int i;
+	struct bcmgenet_tx_ring *ring;
+
+	netif_napi_del(&priv->napi);
+
+	if (netif_is_multiqueue(priv->dev)) {
+		for (i = 0; i < priv->hw_params->tx_queues; ++i) {
+			ring = &priv->tx_rings[i];
+			netif_napi_del(&ring->napi);
+		}
+	}
+
+	ring = &priv->tx_rings[DESC_INDEX];
+	netif_napi_del(&ring->napi);
+}
+
+/* init multi xmit queues, only available for GENET2
+ * the queue is partitioned as follows:
+ *
+ * queue 0 - 3 is priority based, each one has 32 descriptors,
+ * with queue 0 being the highest priority queue.
+ *
+ * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
+ * descriptors: 256 - (number of tx queues * bds per queues) = 128
+ * descriptors.
+ *
+ * The transmit control block pool is then partitioned as following:
+ * - tx_cbs[0...127] are for queue 16
+ * - tx_ring_cbs[0] points to tx_cbs[128..159]
+ * - tx_ring_cbs[1] points to tx_cbs[160..191]
+ * - tx_ring_cbs[2] points to tx_cbs[192..223]
+ * - tx_ring_cbs[3] points to tx_cbs[224..255]
+ */
+static void bcmgenet_init_multiq(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	unsigned int i, dma_enable;
+	u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
+
+	if (!netif_is_multiqueue(dev)) {
+		netdev_warn(dev, "called with non multi queue aware HW\n");
+		return;
+	}
+
+	dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
+	dma_enable = dma_ctrl & DMA_EN;
+	dma_ctrl &= ~DMA_EN;
+	bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
+
+	/* Enable strict priority arbiter mode */
+	bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
+
+	for (i = 0; i < priv->hw_params->tx_queues; i++) {
+		/* first 64 tx_cbs are reserved for default tx queue
+		 * (ring 16)
+		 */
+		bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
+					i * priv->hw_params->bds_cnt,
+					(i + 1) * priv->hw_params->bds_cnt);
+
+		/* Configure ring as decriptor ring and setup priority */
+		ring_cfg |= (1 << i);
+		dma_priority |= ((GENET_Q0_PRIORITY + i) <<
+				(GENET_MAX_MQ_CNT + 1) * i);
+		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
+	}
+
+	/* Enable rings */
+	reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
+	reg |= ring_cfg;
+	bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
+
+	/* Use configured rings priority and set ring #16 priority */
+	reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
+	reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
+	reg |= dma_priority;
+	bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
+
+	/* Configure ring as descriptor ring and re-enable DMA if enabled */
+	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
+	reg |= dma_ctrl;
+	if (dma_enable)
+		reg |= DMA_EN;
+	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
+}
+
+static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
+{
+	int timeout = 0;
+	u32 reg;
+
+	/* Disable TDMA to stop add more frames in TX DMA */
+	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
+	reg &= ~DMA_EN;
+	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
+
+	/* Check TDMA status register to confirm TDMA is disabled */
+	while (!(bcmgenet_tdma_readl(priv, DMA_STATUS) & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(priv->dev,
+				"Timed out while disabling TX DMA\n");
+			return -ETIMEDOUT;
+		}
+		udelay(1);
+	}
+
+	/* SWLINUX-2252: Workaround for rx flush issue causes rbuf overflow */
+	/* Wait 10ms for packet drain in both tx and rx dma */
+	usleep_range(10000, 20000);
+
+	/* Disable RDMA */
+	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
+	reg &= ~DMA_EN;
+	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
+
+	timeout = 0;
+	/* Check RDMA status register to confirm RDMA is disabled */
+	while (!(bcmgenet_rdma_readl(priv, DMA_STATUS) & DMA_DISABLED)) {
+		if (timeout++ == 5000) {
+			netdev_warn(priv->dev,
+				"Timed out while disabling RX DMA\n");
+			return -ETIMEDOUT;
+		}
+		udelay(1);
+	}
+
+	return 0;
+}
+
+static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
+{
+	int i;
+
+	bcmgenet_fini_napi(priv);
+
+	/* disable DMA */
+	bcmgenet_dma_teardown(priv);
+
+	for (i = 0; i < priv->num_tx_bds; i++) {
+		if (priv->tx_cbs[i].skb != NULL) {
+			dev_kfree_skb(priv->tx_cbs[i].skb);
+			priv->tx_cbs[i].skb = NULL;
+		}
+	}
+	bcmgenet_free_rx_buffers(priv);
+	kfree(priv->rx_cbs);
+	kfree(priv->tx_cbs);
+}
+
+/* Initialize DMA control register */
+static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
+{
+	int ret;
+
+	netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
+
+	/* by default, enable ring 16 (descriptor based) */
+	ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
+	if (ret) {
+		netdev_err(priv->dev, "failed to initialize RX ring\n");
+		return ret;
+	}
+
+	/* init rDma */
+	bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
+
+	/* Init tDma */
+	bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
+
+	/* Initialize common TX ring structures */
+	priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
+	priv->num_tx_bds = TOTAL_DESC;
+	priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
+				GFP_KERNEL);
+	if (!priv->tx_cbs) {
+		bcmgenet_fini_dma(priv);
+		return -ENOMEM;
+	}
+
+	/* initialize multi xmit queue */
+	bcmgenet_init_multiq(priv->dev);
+
+	/* initialize special ring 16 */
+	bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
+			priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
+			TOTAL_DESC);
+
+	return 0;
+}
+
+/* Interrupt bottom half */
+static void bcmgenet_irq_task(struct work_struct *work)
+{
+	struct bcmgenet_priv *priv = container_of(
+			work, struct bcmgenet_priv, bcmgenet_irq_work);
+	struct net_device *dev;
+
+	dev = priv->dev;
+
+	netif_dbg(priv, intr, dev, "%s\n", __func__);
+	/* Cable plugged/unplugged event */
+	if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+		if (priv->irq0_stat & UMAC_IRQ_PHY_DET_R) {
+			priv->irq0_stat &= ~UMAC_IRQ_PHY_DET_R;
+			netif_crit(priv, link, dev,
+				"cable plugged in, powering up\n");
+			bcmgenet_power_up(priv, GENET_POWER_CABLE_SENSE);
+		} else if (priv->irq0_stat & UMAC_IRQ_PHY_DET_F) {
+			priv->irq0_stat &= ~UMAC_IRQ_PHY_DET_F;
+			netif_crit(priv, link, dev,
+				"cable unplugged, powering down\n");
+			bcmgenet_power_down(priv, GENET_POWER_CABLE_SENSE);
+		}
+	}
+	if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
+		priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
+		netif_crit(priv, wol, dev,
+			"magic packet detected, waking up\n");
+		bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
+
+	}
+
+	/* Link UP/DOWN event */
+	if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
+		phy_mac_interrupt(priv->phydev,
+				!!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
+		priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
+	}
+}
+
+/* bcmgenet_isr1: interrupt handler for ring buffer. */
+static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
+{
+	struct bcmgenet_priv *priv = dev_id;
+	struct bcmgenet_tx_ring *tx_ring;
+	unsigned int index;
+
+	/* Save irq status for bottom-half processing. */
+	priv->irq1_stat =
+		bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
+		~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
+	/* clear interrupts*/
+	bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
+
+	netif_dbg(priv, intr, priv->dev,
+		"%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
+	/* Check the MBDONE interrupts.
+	 * packet is done, reclaim descriptors
+	 */
+	if (priv->irq1_stat & 0x0000ffff) {
+		index = 0;
+		for (index = 0; index < 16; index++) {
+			if (!(priv->irq1_stat & (1 << index)))
+				continue;
+
+			tx_ring = &priv->tx_rings[index];
+
+			if (likely(napi_schedule_prep(&tx_ring->napi))) {
+				tx_ring->int_disable(tx_ring->priv, tx_ring);
+				__napi_schedule(&tx_ring->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+/* bcmgenet_isr0: Handle various interrupts. */
+static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
+{
+	struct bcmgenet_priv *priv = dev_id;
+	struct bcmgenet_tx_ring *tx_ring;
+
+	/* Save irq status for bottom-half processing. */
+	priv->irq0_stat =
+		bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
+		~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
+	/* clear interrupts*/
+	bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
+
+	netif_dbg(priv, intr, priv->dev,
+		"IRQ=0x%x\n", priv->irq0_stat);
+
+	if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
+		/* We use NAPI(software interrupt throttling, if
+		 * Rx Descriptor throttling is not used.
+		 * Disable interrupt, will be enabled in the poll method.
+		 */
+		if (likely(napi_schedule_prep(&priv->napi))) {
+			bcmgenet_intrl2_0_writel(priv,
+				UMAC_IRQ_RXDMA_DONE, INTRL2_CPU_MASK_SET);
+			__napi_schedule(&priv->napi);
+		}
+	}
+	if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
+		/* Tx reclaim */
+		tx_ring = &priv->tx_rings[DESC_INDEX];
+
+		if (likely(napi_schedule_prep(&tx_ring->napi))) {
+			tx_ring->int_disable(tx_ring->priv, tx_ring);
+			__napi_schedule(&tx_ring->napi);
+		}
+	}
+	if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
+				UMAC_IRQ_PHY_DET_F |
+				UMAC_IRQ_LINK_EVENT |
+				UMAC_IRQ_HFB_SM |
+				UMAC_IRQ_HFB_MM |
+				UMAC_IRQ_MPD_R)) {
+		/* all other interested interrupts handled in bottom half */
+		schedule_work(&priv->bcmgenet_irq_work);
+	}
+
+	if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
+		priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
+		priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
+		wake_up(&priv->wq);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
+{
+	struct bcmgenet_priv *priv = dev_id;
+
+	pm_wakeup_event(&priv->pdev->dev, 0);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void bcmgenet_poll_controller(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	disable_irq(priv->irq0);
+	bcmgenet_isr0(priv->irq0, priv);
+	enable_irq(priv->irq0);
+
+	bcmgenet_tx_reclaim_all(dev);
+}
+#endif
+
+static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
+{
+	u32 reg;
+
+	reg = bcmgenet_rbuf_ctrl_get(priv);
+	reg |= BIT(1);
+	bcmgenet_rbuf_ctrl_set(priv, reg);
+	udelay(10);
+
+	reg &= ~BIT(1);
+	bcmgenet_rbuf_ctrl_set(priv, reg);
+	udelay(10);
+}
+
+static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
+				  unsigned char *addr)
+{
+	bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
+			(addr[2] << 8) | addr[3], UMAC_MAC0);
+	bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
+}
+
+/* Returns a reusable dma control register value */
+static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
+{
+	u32 reg;
+	u32 dma_ctrl;
+
+	/* disable DMA */
+	dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
+	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
+	reg &= ~dma_ctrl;
+	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
+
+	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
+	reg &= ~dma_ctrl;
+	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
+
+	bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
+	udelay(10);
+	bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
+
+	return dma_ctrl;
+}
+
+static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
+{
+	u32 reg;
+
+	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
+	reg |= dma_ctrl;
+	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
+
+	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
+	reg |= dma_ctrl;
+	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
+}
+
+static void bcmgenet_netif_start(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	/* Start the network engine */
+	bcmgenet_enable_napi(priv);
+
+	umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
+
+	netif_tx_start_all_queues(dev);
+
+	phy_start(priv->phydev);
+}
+
+static int bcmgenet_open(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	unsigned long dma_ctrl;
+	u32 reg;
+	int ret;
+
+	netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
+
+	/* Turn on the clock */
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		return ret;
+
+	/* If this is an internal GPHY, power it back on now, before UniMAC is
+	 * brought out of reset as absolutely no UniMAC activity is allowed
+	 */
+	if (priv->phy_type == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
+	/* take MAC out of reset */
+	bcmgenet_umac_reset(priv);
+
+	ret = init_umac(priv);
+	if (ret)
+		goto err_clk_disable;
+
+	/* disable ethernet MAC while updating its registers */
+	umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
+
+	/* Make sure we reflect the value of CRC_CMD_FWD */
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
+
+	bcmgenet_set_hw_addr(priv, dev->dev_addr);
+
+	if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+		reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+		reg |= EXT_ENERGY_DET_MASK;
+		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+	}
+
+	/* Disable RX/TX DMA and flush TX queues */
+	dma_ctrl = bcmgenet_dma_disable(priv);
+
+	/* Reinitialize TDMA and RDMA and SW housekeeping */
+	ret = bcmgenet_init_dma(priv);
+	if (ret) {
+		netdev_err(dev, "failed to initialize DMA\n");
+		goto err_fini_dma;
+	}
+
+	/* Always enable ring 16 - descriptor ring */
+	bcmgenet_enable_dma(priv, dma_ctrl);
+
+	ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
+			dev->name, priv);
+	if (ret < 0) {
+		netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
+		goto err_fini_dma;
+	}
+
+	ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
+				dev->name, priv);
+	if (ret < 0) {
+		netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
+		goto err_irq0;
+	}
+
+	ret = bcmgenet_mii_probe(dev);
+	if (ret)
+		goto err_irq1;
+
+	bcmgenet_netif_start(dev);
+
+	return 0;
+
+err_irq1:
+	free_irq(priv->irq1, priv);
+err_irq0:
+	free_irq(priv->irq0, priv);
+err_fini_dma:
+	bcmgenet_fini_dma(priv);
+err_clk_disable:
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+
+static void bcmgenet_netif_stop(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	netif_tx_stop_all_queues(dev);
+	bcmgenet_disable_napi(priv);
+	phy_stop(priv->phydev);
+
+	bcmgenet_intr_disable(priv);
+
+	cancel_work_sync(&priv->bcmgenet_irq_work);
+
+	priv->old_link = -1;
+	priv->old_speed = -1;
+	priv->old_duplex = -1;
+	priv->old_pause = -1;
+}
+
+static int bcmgenet_close(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	int ret;
+
+	netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
+
+	bcmgenet_netif_stop(dev);
+
+	/* Really kill the PHY state machine and disconnect from it */
+	phy_disconnect(priv->phydev);
+
+	/* Disable MAC receive */
+	umac_enable_set(priv, CMD_RX_EN, false);
+
+	ret = bcmgenet_dma_teardown(priv);
+	if (ret)
+		return ret;
+
+	/* Disable MAC transmit. TX DMA disabled must be done before this */
+	umac_enable_set(priv, CMD_TX_EN, false);
+
+	/* tx reclaim */
+	bcmgenet_tx_reclaim_all(dev);
+	bcmgenet_fini_dma(priv);
+
+	free_irq(priv->irq0, priv);
+	free_irq(priv->irq1, priv);
+
+	if (priv->phy_type == BRCM_PHY_TYPE_INT)
+		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
+
+	clk_disable_unprepare(priv->clk);
+
+	return ret;
+}
+
+static void bcmgenet_timeout(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+
+	netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
+
+	dev->trans_start = jiffies;
+
+	dev->stats.tx_errors++;
+
+	netif_tx_wake_all_queues(dev);
+}
+
+#define MAX_MC_COUNT	16
+
+static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
+					 unsigned char *addr,
+					 int *i,
+					 int *mc)
+{
+	u32 reg;
+
+	bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
+			UMAC_MDF_ADDR + (*i * 4));
+	bcmgenet_umac_writel(priv,
+			addr[2] << 24 | addr[3] << 16 |
+			addr[4] << 8 | addr[5],
+			UMAC_MDF_ADDR + ((*i + 1) * 4));
+	reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
+	reg |= (1 << (MAX_MC_COUNT - *mc));
+	bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
+	*i += 2;
+	(*mc)++;
+}
+
+static void bcmgenet_set_rx_mode(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct netdev_hw_addr *ha;
+	int i, mc;
+	u32 reg;
+
+	netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
+
+	/* Promiscuous mode */
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	if (dev->flags & IFF_PROMISC) {
+		reg |= CMD_PROMISC;
+		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+		bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
+		return;
+	} else {
+		reg &= ~CMD_PROMISC;
+		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+	}
+
+	/* UniMac doesn't support ALLMULTI */
+	if (dev->flags & IFF_ALLMULTI)
+		return;
+
+	/* update MDF filter */
+	i = 0;
+	mc = 0;
+	/* Broadcast */
+	bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
+	/* my own address.*/
+	bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
+	/* Unicast list*/
+	if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
+		return;
+
+	if (!netdev_uc_empty(dev))
+		netdev_for_each_uc_addr(ha, dev)
+			bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
+	/* Multicast */
+	if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
+		return;
+
+	netdev_for_each_mc_addr(ha, dev)
+		bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
+}
+
+/* Set the hardware MAC address. */
+static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
+{
+	struct sockaddr *addr = p;
+
+	if (netif_running(dev))
+		return -EBUSY;
+
+	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+
+	return 0;
+}
+
+static u16 bcmgenet_select_queue(struct net_device *dev,
+				 struct sk_buff *skb,
+				 void *accel_priv,
+				 select_queue_fallback_t fallback)
+{
+	/* If multi-queue support is enabled, and NET_ACT_SKBEDIT is not
+	 * defined, this function simply returns current queue_mapping set
+	 * inside skb, this means other modules, (netaccel, for example),
+	 * must provide a mechanism to set the queue_mapping before trying
+	 * to send a packet.
+	 */
+	return netif_is_multiqueue(dev) ? skb->queue_mapping : 0;
+}
+
+static const struct net_device_ops bcmgenet_netdev_ops = {
+	.ndo_open		= bcmgenet_open,
+	.ndo_stop		= bcmgenet_close,
+	.ndo_start_xmit		= bcmgenet_xmit,
+	.ndo_select_queue	= bcmgenet_select_queue,
+	.ndo_tx_timeout		= bcmgenet_timeout,
+	.ndo_set_rx_mode	= bcmgenet_set_rx_mode,
+	.ndo_set_mac_address	= bcmgenet_set_mac_addr,
+	.ndo_do_ioctl		= bcmgenet_ioctl,
+	.ndo_set_features	= bcmgenet_set_features,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= bcmgenet_poll_controller,
+#endif
+};
+
+/* Array of GENET hardware parameters/characteristics */
+static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
+	[GENET_V1] = {
+		.tx_queues = 0,
+		.rx_queues = 0,
+		.bds_cnt = 0,
+		.bp_in_en_shift = 16,
+		.bp_in_mask = 0xffff,
+		.hfb_filter_cnt = 16,
+		.qtag_mask = 0x1F,
+		.hfb_offset = 0x1000,
+		.rdma_offset = 0x2000,
+		.tdma_offset = 0x3000,
+		.words_per_bd = 2,
+	},
+	[GENET_V2] = {
+		.tx_queues = 4,
+		.rx_queues = 4,
+		.bds_cnt = 32,
+		.bp_in_en_shift = 16,
+		.bp_in_mask = 0xffff,
+		.hfb_filter_cnt = 16,
+		.qtag_mask = 0x1F,
+		.tbuf_offset = 0x0600,
+		.hfb_offset = 0x1000,
+		.hfb_reg_offset = 0x2000,
+		.rdma_offset = 0x3000,
+		.tdma_offset = 0x4000,
+		.words_per_bd = 2,
+		.flags = GENET_HAS_EXT,
+	},
+	[GENET_V3] = {
+		.tx_queues = 4,
+		.rx_queues = 4,
+		.bds_cnt = 32,
+		.bp_in_en_shift = 17,
+		.bp_in_mask = 0x1ffff,
+		.hfb_filter_cnt = 48,
+		.qtag_mask = 0x3F,
+		.tbuf_offset = 0x0600,
+		.hfb_offset = 0x8000,
+		.hfb_reg_offset = 0xfc00,
+		.rdma_offset = 0x10000,
+		.tdma_offset = 0x11000,
+		.words_per_bd = 2,
+		.flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
+			 GENET_HAS_MOCA_LINK_DET,
+	},
+	[GENET_V4] = {
+		.tx_queues = 4,
+		.rx_queues = 4,
+		.bds_cnt = 32,
+		.bp_in_en_shift = 17,
+		.bp_in_mask = 0x1ffff,
+		.hfb_filter_cnt = 48,
+		.qtag_mask = 0x3F,
+		.tbuf_offset = 0x0600,
+		.hfb_offset = 0x8000,
+		.hfb_reg_offset = 0xfc00,
+		.rdma_offset = 0x2000,
+		.tdma_offset = 0x4000,
+		.words_per_bd = 3,
+		.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
+			 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
+	},
+};
+
+/* Infer hardware parameters from the detected GENET version */
+static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
+{
+	struct bcmgenet_hw_params *params;
+	u32 reg;
+	u8 major;
+	u16 gphy_rev;
+
+	if (GENET_IS_V4(priv)) {
+		bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
+		genet_dma_ring_regs = genet_dma_ring_regs_v4;
+		priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
+		priv->version = GENET_V4;
+	} else if (GENET_IS_V3(priv)) {
+		bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
+		genet_dma_ring_regs = genet_dma_ring_regs_v123;
+		priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
+		priv->version = GENET_V3;
+	} else if (GENET_IS_V2(priv)) {
+		bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
+		genet_dma_ring_regs = genet_dma_ring_regs_v123;
+		priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
+		priv->version = GENET_V2;
+	} else if (GENET_IS_V1(priv)) {
+		bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
+		genet_dma_ring_regs = genet_dma_ring_regs_v123;
+		priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
+		priv->version = GENET_V1;
+	}
+
+	/* enum genet_version starts at 1 */
+	priv->hw_params = &bcmgenet_hw_params[priv->version];
+	params = priv->hw_params;
+
+	/* Read GENET HW version */
+	reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
+	major = (reg >> 24 & 0x0f);
+	if (major == 5)
+		major = 4;
+	else if (major == 0)
+		major = 1;
+	if (major != priv->version) {
+		dev_err(&priv->pdev->dev,
+			"GENET version mismatch, got: %d, configured for: %d\n",
+			major, priv->version);
+	}
+
+	/* Print the GENET core version */
+	dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
+		major, (reg >> 16) & 0x0f, reg & 0xffff);
+
+	/* Store the integrated PHY revision for the MDIO probing function
+	 * to pass this information to the PHY driver. The PHY driver expects
+	 * to find the PHY major revision in bits 15:8 while the GENET register
+	 * stores that information in bits 7:0, account for that.
+	 *
+	 * On newer chips, starting with PHY revision G0, a new scheme is
+	 * deployed similar to the Starfighter 2 switch with GPHY major
+	 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
+	 * is reserved as well as special value 0x01ff, we have a small
+	 * heuristic to check for the new GPHY revision and re-arrange things
+	 * so the GPHY driver is happy.
+	 */
+	gphy_rev = reg & 0xffff;
+
+	/* This is the good old scheme, just GPHY major, no minor nor patch */
+	if ((gphy_rev & 0xf0) != 0)
+		priv->gphy_rev = gphy_rev << 8;
+
+	/* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
+	else if ((gphy_rev & 0xff00) != 0)
+		priv->gphy_rev = gphy_rev;
+
+	/* This is reserved so should require special treatment */
+	else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
+		pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
+		return;
+	}
+
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	if (!(params->flags & GENET_HAS_40BITS))
+		pr_warn("GENET does not support 40-bits PA\n");
+#endif
+
+	pr_debug("Configuration for version: %d\n"
+		"TXq: %1d, RXq: %1d, BDs: %1d\n"
+		"BP << en: %2d, BP msk: 0x%05x\n"
+		"HFB count: %2d, QTAQ msk: 0x%05x\n"
+		"TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
+		"RDMA: 0x%05x, TDMA: 0x%05x\n"
+		"Words/BD: %d\n",
+		priv->version,
+		params->tx_queues, params->rx_queues, params->bds_cnt,
+		params->bp_in_en_shift, params->bp_in_mask,
+		params->hfb_filter_cnt, params->qtag_mask,
+		params->tbuf_offset, params->hfb_offset,
+		params->hfb_reg_offset,
+		params->rdma_offset, params->tdma_offset,
+		params->words_per_bd);
+}
+
+#ifdef CONFIG_OF
+static void bcmgenet_of_parse(struct device_node *dn,
+				struct bcmgenet_priv *priv)
+{
+	u32 propval;
+
+	priv->phy_type = BRCM_PHY_TYPE_INT;
+	priv->phy_addr = 10;
+	priv->phy_speed = SPEED_1000;
+	if (!of_property_read_u32(dn, "phy-type", &propval))
+		priv->phy_type = propval;
+	if (!of_property_read_u32(dn, "phy-id", &propval))
+		priv->phy_addr = propval;
+	if (!of_property_read_u32(dn, "phy-speed", &propval))
+		priv->phy_speed = propval;
+
+	if (!of_property_read_u32(dn, "ethsw-type", &propval)) {
+		/* one-shot initialization; never poll for link status */
+		priv->sw_type = propval;
+
+		/* switch pseudo-PHY is stored in sw_addr */
+		priv->sw_addr = priv->phy_addr;
+		/* switch real MDIO bus PHY id is 0 */
+		if (priv->phy_addr != BRCM_PHY_ID_NONE)
+			priv->phy_addr = 0;
+	}
+}
+#else
+static void bcmgenet_pd_parse(struct bcmgenet_priv *priv)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct bcmgenet_platform_data *pd = kdev->platform_data;
+
+	switch (pd->phy_interface) {
+	case PHY_INTERFACE_MODE_NA:
+		priv->phy_type = BRCM_PHY_TYPE_INT;
+		break;
+	case PHY_INTERFACE_MODE_MOCA:
+		priv->phy_type = BRCM_PHY_TYPE_MOCA;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		priv->phy_type = BRCM_PHY_TYPE_EXT_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_MII:
+		priv->phy_type = BRCM_PHY_TYPE_EXT_MII;
+		break;
+	case PHY_INTERFACE_MODE_REVMII:
+		priv->phy_type = BRCM_PHY_TYPE_EXT_RVMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		priv->phy_type = BRCM_PHY_TYPE_EXT_RGMII_NO_ID;
+		break;
+	default:
+		dev_err(kdev, "unsupported PHY interface\n");
+		return;
+	}
+}
+#endif
+
+static const struct of_device_id bcmgenet_match[] = {
+	{ .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
+	{ .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
+	{ .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
+	{ .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
+	{ },
+};
+
+
+static const char *bcmgenet_clock_names[] = {
+#ifdef CONFIG_OF
+	"sw_genet", "sw_genetwol", "sw_geneteee",
+#else
+	"enet", "enet-wol", "enet-eee",
+#endif
+};
+
+static int bcmgenet_drv_probe(struct platform_device *pdev)
+{
+	struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
+	struct device_node *dn = pdev->dev.of_node;
+	const struct of_device_id *of_id = NULL;
+	struct bcmgenet_priv *priv;
+	struct net_device *dev;
+	const void *macaddr;
+	struct resource *r;
+	int err = -EIO;
+
+	/* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
+	dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
+	if (!dev) {
+		dev_err(&pdev->dev, "can't allocate net device\n");
+		return -ENOMEM;
+	}
+
+	if (dn) {
+		of_id = of_match_node(bcmgenet_match, dn);
+		if (!of_id)
+			return -EINVAL;
+	}
+
+	priv = netdev_priv(dev);
+	priv->irq0 = platform_get_irq(pdev, 0);
+	priv->irq1 = platform_get_irq(pdev, 1);
+	priv->wol_irq = platform_get_irq(pdev, 2);
+	if (!priv->irq0 || !priv->irq1) {
+		dev_err(&pdev->dev, "can't find IRQs\n");
+		err = -EINVAL;
+		goto err;
+	}
+
+	if (dn) {
+		macaddr = of_get_mac_address(dn);
+		if (!macaddr) {
+			dev_err(&pdev->dev, "can't find MAC address\n");
+			err = -EINVAL;
+			goto err;
+		}
+	} else {
+		macaddr = pd->mac_address;
+	}
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_request_and_ioremap(&pdev->dev, r);
+	if (!priv->base) {
+		dev_err(&pdev->dev, "can't ioremap\n");
+		err = -EINVAL;
+		goto err;
+	}
+
+	SET_NETDEV_DEV(dev, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, dev);
+	memcpy(dev->dev_addr, macaddr, ETH_ALEN);
+	dev->watchdog_timeo = 2 * HZ;
+	dev->ethtool_ops = &bcmgenet_ethtool_ops;
+	dev->netdev_ops = &bcmgenet_netdev_ops;
+
+	priv->msg_enable = netif_msg_init(debug, GENET_MSG_DEFAULT);
+
+	/* Set hardware features */
+	dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
+		NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
+
+	/* Request the WOL interrupt line and advertise suspend if available */
+	priv->wol_irq_disabled = 1;
+	err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
+				dev->name, priv);
+	if (!err)
+		device_set_wakeup_capable(&pdev->dev, 1);
+
+	/* Set the needed headroom to account for any possible
+	 * features enabling/disabling at runtime
+	 */
+	dev->needed_headroom += 64;
+
+	netdev_boot_setup_check(dev);
+
+	priv->dev = dev;
+	priv->pdev = pdev;
+	if (of_id)
+		priv->version = (enum bcmgenet_version)of_id->data;
+	else
+		priv->version = pd->genet_version;
+
+	priv->clk = devm_clk_get(&priv->pdev->dev, bcmgenet_clock_names[0]);
+	if (IS_ERR(priv->clk)) {
+		dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
+		priv->clk = NULL;
+	}
+
+	err = clk_prepare_enable(priv->clk);
+	if (err) {
+		dev_err(&priv->pdev->dev, "failed to prepare enet clock\n");
+		goto err;
+	}
+
+	bcmgenet_set_hw_params(priv);
+
+	/* Mii wait queue */
+	init_waitqueue_head(&priv->wq);
+	/* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
+	priv->rx_buf_len = RX_BUF_LENGTH;
+	INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
+
+#ifdef CONFIG_OF
+	bcmgenet_of_parse(dn, priv);
+#else
+	bcmgenet_pd_parse(priv);
+#endif
+
+	priv->clk_wol = devm_clk_get(&priv->pdev->dev, bcmgenet_clock_names[1]);
+	if (IS_ERR(priv->clk_wol)) {
+		dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
+		priv->clk_wol = NULL;
+	}
+
+	priv->clk_eee = devm_clk_get(&priv->pdev->dev, bcmgenet_clock_names[2]);
+	if (IS_ERR(priv->clk_eee)) {
+		dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
+		priv->clk_eee = NULL;
+	}
+
+	/* If this is an internal GPHY, power it on now, before UniMAC is
+	 * brought out of reset as absolutely no UniMAC activity is allowed
+	 */
+	if (priv->phy_type == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
+	err = reset_umac(priv);
+	if (err)
+		goto err_clk_disable;
+
+	err = bcmgenet_mii_init(dev);
+	if (err) {
+		dev_err(&priv->pdev->dev, "MII initialization failed!\n");
+		goto err_clk_disable;
+	}
+
+	/* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
+	 * just the ring 16 descriptor based TX
+	 */
+	netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
+	netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
+
+	/* SWLINUX-1813: EXT block is not available on MOCA_GENET */
+	if (priv->hw_params->flags & GENET_HAS_EXT) {
+#if !defined(CONFIG_BCM7125)
+		if (priv->pdev->id == 1)
+#endif
+			priv->hw_params->flags &= ~GENET_HAS_EXT;
+	}
+
+	/* We report link status through the PHY library */
+	netif_carrier_off(dev);
+
+	/* Turn off the clocks */
+	clk_disable_unprepare(priv->clk);
+
+	err = register_netdev(dev);
+	if (err)
+		goto err_clk_disable;
+
+	return err;
+
+err_clk_disable:
+	clk_disable_unprepare(priv->clk);
+err:
+	free_netdev(dev);
+	return err;
+}
+
+static int bcmgenet_drv_remove(struct platform_device *pdev)
+{
+	struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	unregister_netdev(priv->dev);
+	bcmgenet_mii_exit(priv->dev);
+	free_netdev(priv->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int bcmgenet_suspend(struct device *d)
+{
+	struct net_device *dev = dev_get_drvdata(d);
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	int ret;
+
+	if (!netif_running(dev))
+		return 0;
+
+	bcmgenet_netif_stop(dev);
+
+	phy_suspend(priv->phydev);
+
+	netif_device_detach(dev);
+
+	/* Disable MAC receive */
+	umac_enable_set(priv, CMD_RX_EN, 0);
+
+	ret = bcmgenet_dma_teardown(priv);
+	if (ret)
+		return ret;
+
+	/* Disable MAC transmit. TX DMA disabled must be done before this */
+	umac_enable_set(priv, CMD_TX_EN, 0);
+
+	/* tx reclaim */
+	bcmgenet_tx_reclaim_all(dev);
+	bcmgenet_fini_dma(priv);
+
+	/* Prepare the device for Wake-on-LAN */
+	if (device_may_wakeup(d) && priv->wolopts) {
+		ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
+		clk_prepare_enable(priv->clk_wol);
+	} else if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
+	}
+
+	/* Turn off the clocks */
+	clk_disable_unprepare(priv->clk);
+
+	return ret;
+}
+
+static int bcmgenet_resume(struct device *d)
+{
+	struct net_device *dev = dev_get_drvdata(d);
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	unsigned long dma_ctrl;
+	int ret = 0;
+	u32 reg;
+
+	if (!netif_running(dev))
+		return 0;
+
+	/* Turn on the clock */
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		return ret;
+
+	/* If this is an internal GPHY, power it back on now, before UniMAC is
+	 * brought out of reset as absolutely no UniMAC activity is allowed
+	 */
+	if (priv->phy_type == BRCM_PHY_TYPE_INT)
+		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
+
+	bcmgenet_umac_reset(priv);
+
+	ret = init_umac(priv);
+	if (ret)
+		goto out_clk_disable;
+
+	/* From WOL-enabled suspend, switch to regular clock */
+	if (priv->wolopts)
+		clk_disable_unprepare(priv->clk_wol);
+
+	/* Speed settings must be restored */
+	bcmgenet_mii_config(priv->dev);
+
+	/* disable ethernet MAC while updating its registers */
+	umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, 0);
+
+	bcmgenet_set_hw_addr(priv, dev->dev_addr);
+
+	if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+		reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+		reg |= EXT_ENERGY_DET_MASK;
+		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+	}
+
+	if (priv->wolopts)
+		bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
+
+	/* Disable RX/TX DMA and flush TX queues */
+	dma_ctrl = bcmgenet_dma_disable(priv);
+
+	/* Reinitialize TDMA and RDMA and SW housekeeping */
+	ret = bcmgenet_init_dma(priv);
+	if (ret) {
+		netdev_err(dev, "failed to initialize DMA\n");
+		goto out_clk_disable;
+	}
+
+	/* Always enable ring 16 - descriptor ring */
+	bcmgenet_enable_dma(priv, dma_ctrl);
+
+	netif_device_attach(dev);
+
+	phy_resume(priv->phydev);
+
+	if (priv->eee.eee_enabled)
+		bcmgenet_eee_enable_set(dev, true);
+
+	bcmgenet_netif_start(dev);
+
+	return 0;
+
+out_clk_disable:
+	clk_disable_unprepare(priv->clk);
+	return ret;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
+
+static struct platform_driver bcmgenet_plat_drv = {
+	.probe	= bcmgenet_drv_probe,
+	.remove	= bcmgenet_drv_remove,
+	.driver	= {
+		.name	= "bcmgenet",
+		.owner	= THIS_MODULE,
+		.of_match_table = bcmgenet_match,
+		.pm	= &bcmgenet_pm_ops,
+	},
+};
+module_platform_driver(bcmgenet_plat_drv);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
+MODULE_ALIAS("platform:bcmgenet");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
new file mode 100644
index 000000000000..ec67850203c8
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h
@@ -0,0 +1,704 @@
+/*
+ *
+ * Copyright (c) 2002-2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+*/
+#ifndef __BCMGENET_H__
+#define __BCMGENET_H__
+
+#define VERSION     "2.0"
+#define VER_STR     "v" VERSION
+
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+#include <linux/clk.h>
+#include <linux/mii.h>
+#include <linux/if_vlan.h>
+#include <linux/phy.h>
+
+/* BCMGENET device tree properties */
+#define BRCM_PHY_ID_AUTO	0x100
+#define BRCM_PHY_ID_NONE	0x101
+
+#define BRCM_PHY_TYPE_INT	1
+#define BRCM_PHY_TYPE_EXT_MII	2
+#define BRCM_PHY_TYPE_EXT_RVMII	3
+#define BRCM_PHY_TYPE_EXT_RGMII	4
+#define BRCM_PHY_TYPE_EXT_RGMII_IBS	5
+#define BRCM_PHY_TYPE_EXT_RGMII_NO_ID	6
+#define BRCM_PHY_TYPE_MOCA	7
+
+
+/* total number of Buffer Descriptors, same for Rx/Tx */
+#define TOTAL_DESC				256
+/* which ring is descriptor based */
+#define DESC_INDEX				16
+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_BRCM_TAG_LEN	6
+#define ENET_PAD		8
+#define ENET_MAX_MTU_SIZE	(ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
+				 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
+#define DMA_MAX_BURST_LENGTH    0x10
+
+/* misc. configuration */
+#define CLEAR_ALL_HFB			0xFF
+#define DMA_FC_THRESH_HI		(TOTAL_DESC >> 4)
+#define DMA_FC_THRESH_LO		5
+
+/* 64B status Block */
+struct status_64 {
+	u32	length_status;		/* length and peripheral status */
+	u32	ext_status;		/* Extended status*/
+	u32	rx_csum;		/* partial rx checksum */
+	u32	unused1[9];		/* unused */
+	u32	tx_csum_info;		/* Tx checksum info. */
+	u32	unused2[3];		/* unused */
+};
+
+
+/* Rx status bits */
+#define STATUS_RX_EXT_MASK		0x1FFFFF
+#define STATUS_RX_CSUM_MASK		0xFFFF
+#define STATUS_RX_CSUM_OK		0x10000
+#define STATUS_RX_CSUM_FR		0x20000
+#define STATUS_RX_PROTO_TCP		0
+#define STATUS_RX_PROTO_UDP		1
+#define STATUS_RX_PROTO_ICMP		2
+#define STATUS_RX_PROTO_OTHER		3
+#define STATUS_RX_PROTO_MASK		3
+#define STATUS_RX_PROTO_SHIFT		18
+#define STATUS_FILTER_INDEX_MASK	0xFFFF
+/* Tx status bits */
+#define STATUS_TX_CSUM_START_MASK	0X7FFF
+#define STATUS_TX_CSUM_START_SHIFT	16
+#define STATUS_TX_CSUM_PROTO_UDP	0x8000
+#define STATUS_TX_CSUM_OFFSET_MASK	0x7FFF
+#define STATUS_TX_CSUM_LV		0x80000000
+
+/* DMA Descriptor */
+#define DMA_DESC_LENGTH_STATUS	0x00	/* in bytes of data in buffer */
+#define DMA_DESC_ADDRESS_LO	0x04	/* lower bits of PA */
+#define DMA_DESC_ADDRESS_HI	0x08	/* upper 32 bits of PA, GENETv4+ */
+
+/* Rx/Tx common counter group.*/
+struct bcmgenet_pkt_counters {
+	u32	cnt_64;		/* RO Received/Transmited 64 bytes packet */
+	u32	cnt_127;	/* RO Rx/Tx 127 bytes packet */
+	u32	cnt_255;	/* RO Rx/Tx 65-255 bytes packet */
+	u32	cnt_511;	/* RO Rx/Tx 256-511 bytes packet */
+	u32	cnt_1023;	/* RO Rx/Tx 512-1023 bytes packet */
+	u32	cnt_1518;	/* RO Rx/Tx 1024-1518 bytes packet */
+	u32	cnt_mgv;	/* RO Rx/Tx 1519-1522 good VLAN packet */
+	u32	cnt_2047;	/* RO Rx/Tx 1522-2047 bytes packet*/
+	u32	cnt_4095;	/* RO Rx/Tx 2048-4095 bytes packet*/
+	u32	cnt_9216;	/* RO Rx/Tx 4096-9216 bytes packet*/
+};
+
+/* RSV, Receive Status Vector */
+struct bcmgenet_rx_counters {
+	struct  bcmgenet_pkt_counters pkt_cnt;
+	u32	pkt;		/* RO (0x428) Received pkt count*/
+	u32	bytes;		/* RO Received byte count */
+	u32	mca;		/* RO # of Received multicast pkt */
+	u32	bca;		/* RO # of Receive broadcast pkt */
+	u32	fcs;		/* RO # of Received FCS error  */
+	u32	cf;		/* RO # of Received control frame pkt*/
+	u32	pf;		/* RO # of Received pause frame pkt */
+	u32	uo;		/* RO # of unknown op code pkt */
+	u32	aln;		/* RO # of alignment error count */
+	u32	flr;		/* RO # of frame length out of range count */
+	u32	cde;		/* RO # of code error pkt */
+	u32	fcr;		/* RO # of carrier sense error pkt */
+	u32	ovr;		/* RO # of oversize pkt*/
+	u32	jbr;		/* RO # of jabber count */
+	u32	mtue;		/* RO # of MTU error pkt*/
+	u32	pok;		/* RO # of Received good pkt */
+	u32	uc;		/* RO # of unicast pkt */
+	u32	ppp;		/* RO # of PPP pkt */
+	u32	rcrc;		/* RO (0x470),# of CRC match pkt */
+};
+
+/* TSV, Transmit Status Vector */
+struct bcmgenet_tx_counters {
+	struct bcmgenet_pkt_counters pkt_cnt;
+	u32	pkts;		/* RO (0x4a8) Transmited pkt */
+	u32	mca;		/* RO # of xmited multicast pkt */
+	u32	bca;		/* RO # of xmited broadcast pkt */
+	u32	pf;		/* RO # of xmited pause frame count */
+	u32	cf;		/* RO # of xmited control frame count */
+	u32	fcs;		/* RO # of xmited FCS error count */
+	u32	ovr;		/* RO # of xmited oversize pkt */
+	u32	drf;		/* RO # of xmited deferral pkt */
+	u32	edf;		/* RO # of xmited Excessive deferral pkt*/
+	u32	scl;		/* RO # of xmited single collision pkt */
+	u32	mcl;		/* RO # of xmited multiple collision pkt*/
+	u32	lcl;		/* RO # of xmited late collision pkt */
+	u32	ecl;		/* RO # of xmited excessive collision pkt*/
+	u32	frg;		/* RO # of xmited fragments pkt*/
+	u32	ncl;		/* RO # of xmited total collision count */
+	u32	jbr;		/* RO # of xmited jabber count*/
+	u32	bytes;		/* RO # of xmited byte count */
+	u32	pok;		/* RO # of xmited good pkt */
+	u32	uc;		/* RO (0x0x4f0)# of xmited unitcast pkt */
+};
+
+struct bcmgenet_mib_counters {
+	struct bcmgenet_rx_counters rx;
+	struct bcmgenet_tx_counters tx;
+	u32	rx_runt_cnt;
+	u32	rx_runt_fcs;
+	u32	rx_runt_fcs_align;
+	u32	rx_runt_bytes;
+	u32	rbuf_ovflow_cnt;
+	u32	rbuf_err_cnt;
+	u32	mdf_err_cnt;
+	u32	alloc_rx_buff_failed;
+	u32	rx_dma_failed;
+	u32	tx_dma_failed;
+};
+
+#define UMAC_HD_BKP_CTRL		0x004
+#define	 HD_FC_EN			(1 << 0)
+#define  HD_FC_BKOFF_OK			(1 << 1)
+#define  IPG_CONFIG_RX_SHIFT		2
+#define  IPG_CONFIG_RX_MASK		0x1F
+
+#define UMAC_CMD			0x008
+#define  CMD_TX_EN			(1 << 0)
+#define  CMD_RX_EN			(1 << 1)
+#define  UMAC_SPEED_10			0
+#define  UMAC_SPEED_100			1
+#define  UMAC_SPEED_1000		2
+#define  UMAC_SPEED_2500		3
+#define  CMD_SPEED_SHIFT		2
+#define  CMD_SPEED_MASK			3
+#define  CMD_PROMISC			(1 << 4)
+#define  CMD_PAD_EN			(1 << 5)
+#define  CMD_CRC_FWD			(1 << 6)
+#define  CMD_PAUSE_FWD			(1 << 7)
+#define  CMD_RX_PAUSE_IGNORE		(1 << 8)
+#define  CMD_TX_ADDR_INS		(1 << 9)
+#define  CMD_HD_EN			(1 << 10)
+#define  CMD_SW_RESET			(1 << 13)
+#define  CMD_LCL_LOOP_EN		(1 << 15)
+#define  CMD_AUTO_CONFIG		(1 << 22)
+#define  CMD_CNTL_FRM_EN		(1 << 23)
+#define  CMD_NO_LEN_CHK			(1 << 24)
+#define  CMD_RMT_LOOP_EN		(1 << 25)
+#define  CMD_PRBL_EN			(1 << 27)
+#define  CMD_TX_PAUSE_IGNORE		(1 << 28)
+#define  CMD_TX_RX_EN			(1 << 29)
+#define  CMD_RUNT_FILTER_DIS		(1 << 30)
+
+#define UMAC_MAC0			0x00C
+#define UMAC_MAC1			0x010
+#define UMAC_MAX_FRAME_LEN		0x014
+
+#define UMAC_EEE_CTRL			0x064
+#define  EN_LPI_RX_PAUSE		(1 << 0)
+#define  EN_LPI_TX_PFC			(1 << 1)
+#define  EN_LPI_TX_PAUSE		(1 << 2)
+#define  EEE_EN				(1 << 3)
+#define  RX_FIFO_CHECK			(1 << 4)
+#define  EEE_TX_CLK_DIS			(1 << 5)
+#define  DIS_EEE_10M			(1 << 6)
+#define  LP_IDLE_PREDICTION_MODE	(1 << 7)
+
+#define UMAC_EEE_LPI_TIMER		0x068
+#define UMAC_EEE_WAKE_TIMER		0x06C
+#define UMAC_EEE_REF_COUNT		0x070
+#define  EEE_REFERENCE_COUNT_MASK	0xffff
+
+#define UMAC_TX_FLUSH			0x334
+
+#define UMAC_MIB_START			0x400
+
+#define UMAC_MDIO_CMD			0x614
+#define  MDIO_START_BUSY		(1 << 29)
+#define  MDIO_READ_FAIL			(1 << 28)
+#define  MDIO_RD			(2 << 26)
+#define  MDIO_WR			(1 << 26)
+#define  MDIO_PMD_SHIFT			21
+#define  MDIO_PMD_MASK			0x1F
+#define  MDIO_REG_SHIFT			16
+#define  MDIO_REG_MASK			0x1F
+
+#define UMAC_RBUF_OVFL_CNT		0x61C
+
+#define UMAC_MPD_CTRL			0x620
+#define  MPD_EN				(1 << 0)
+#define  MPD_PW_EN			(1 << 27)
+#define  MPD_MSEQ_LEN_SHIFT		16
+#define  MPD_MSEQ_LEN_MASK		0xFF
+
+#define UMAC_MPD_PW_MS			0x624
+#define UMAC_MPD_PW_LS			0x628
+#define UMAC_RBUF_ERR_CNT		0x634
+#define UMAC_MDF_ERR_CNT		0x638
+#define UMAC_MDF_CTRL			0x650
+#define UMAC_MDF_ADDR			0x654
+#define UMAC_MIB_CTRL			0x580
+#define  MIB_RESET_RX			(1 << 0)
+#define  MIB_RESET_RUNT			(1 << 1)
+#define  MIB_RESET_TX			(1 << 2)
+
+#define RBUF_CTRL			0x00
+#define  RBUF_64B_EN			(1 << 0)
+#define  RBUF_ALIGN_2B			(1 << 1)
+#define  RBUF_BAD_DIS			(1 << 2)
+
+#define RBUF_STATUS			0x0C
+#define  RBUF_STATUS_WOL		(1 << 0)
+#define  RBUF_STATUS_MPD_INTR_ACTIVE	(1 << 1)
+#define  RBUF_STATUS_ACPI_INTR_ACTIVE	(1 << 2)
+
+#define RBUF_CHK_CTRL			0x14
+#define  RBUF_RXCHK_EN			(1 << 0)
+#define  RBUF_SKIP_FCS			(1 << 4)
+
+#define RBUF_ENERGY_CTRL		0x9c
+#define  RBUF_EEE_EN			(1 << 0)
+#define  RBUF_PM_EN			(1 << 1)
+
+#define RBUF_TBUF_SIZE_CTRL		0xb4
+
+#define RBUF_HFB_CTRL_V1		0x38
+#define  RBUF_HFB_FILTER_EN_SHIFT	16
+#define  RBUF_HFB_FILTER_EN_MASK	0xffff0000
+#define  RBUF_HFB_EN			(1 << 0)
+#define  RBUF_HFB_256B			(1 << 1)
+#define  RBUF_ACPI_EN			(1 << 2)
+
+#define RBUF_HFB_LEN_V1			0x3C
+#define  RBUF_FLTR_LEN_MASK		0xFF
+#define  RBUF_FLTR_LEN_SHIFT		8
+
+#define TBUF_CTRL			0x00
+#define TBUF_BP_MC			0x0C
+#define TBUF_ENERGY_CTRL		0x14
+#define  TBUF_EEE_EN			(1 << 0)
+#define  TBUF_PM_EN			(1 << 1)
+
+#define TBUF_CTRL_V1			0x80
+#define TBUF_BP_MC_V1			0xA0
+
+#define HFB_CTRL			0x00
+#define HFB_FLT_ENABLE_V3PLUS		0x04
+#define HFB_FLT_LEN_V2			0x04
+#define HFB_FLT_LEN_V3PLUS		0x1C
+
+/* uniMac intrl2 registers */
+#define INTRL2_CPU_STAT			0x00
+#define INTRL2_CPU_SET			0x04
+#define INTRL2_CPU_CLEAR		0x08
+#define INTRL2_CPU_MASK_STATUS		0x0C
+#define INTRL2_CPU_MASK_SET		0x10
+#define INTRL2_CPU_MASK_CLEAR		0x14
+
+/* INTRL2 instance 0 definitions */
+#define UMAC_IRQ_SCB			(1 << 0)
+#define UMAC_IRQ_EPHY			(1 << 1)
+#define UMAC_IRQ_PHY_DET_R		(1 << 2)
+#define UMAC_IRQ_PHY_DET_F		(1 << 3)
+#define UMAC_IRQ_LINK_UP		(1 << 4)
+#define UMAC_IRQ_LINK_DOWN		(1 << 5)
+#define UMAC_IRQ_LINK_EVENT		(UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
+#define UMAC_IRQ_UMAC			(1 << 6)
+#define UMAC_IRQ_UMAC_TSV		(1 << 7)
+#define UMAC_IRQ_TBUF_UNDERRUN		(1 << 8)
+#define UMAC_IRQ_RBUF_OVERFLOW		(1 << 9)
+#define UMAC_IRQ_HFB_SM			(1 << 10)
+#define UMAC_IRQ_HFB_MM			(1 << 11)
+#define UMAC_IRQ_MPD_R			(1 << 12)
+#define UMAC_IRQ_RXDMA_MBDONE		(1 << 13)
+#define UMAC_IRQ_RXDMA_PDONE		(1 << 14)
+#define UMAC_IRQ_RXDMA_BDONE		(1 << 15)
+#define UMAC_IRQ_RXDMA_DONE		UMAC_IRQ_RXDMA_MBDONE
+#define UMAC_IRQ_TXDMA_MBDONE		(1 << 16)
+#define UMAC_IRQ_TXDMA_PDONE		(1 << 17)
+#define UMAC_IRQ_TXDMA_BDONE		(1 << 18)
+#define UMAC_IRQ_TXDMA_DONE		UMAC_IRQ_TXDMA_MBDONE
+
+/* Only valid for GENETv3+ */
+#define UMAC_IRQ_MDIO_DONE		(1 << 23)
+#define UMAC_IRQ_MDIO_ERROR		(1 << 24)
+
+/* Register block offset */
+#define GENET_SYS_OFF			0x0000
+#define GENET_GR_BRIDGE_OFF		0x0040
+#define GENET_EXT_OFF			0x0080
+#define GENET_INTRL2_0_OFF		0x0200
+#define GENET_INTRL2_1_OFF		0x0240
+#define GENET_RBUF_OFF			0x0300
+#define GENET_UMAC_OFF			0x0800
+
+/* SYS block offsets and register definitions */
+#define SYS_REV_CTRL			0x00
+#define SYS_PORT_CTRL			0x04
+#define  PORT_MODE_INT_EPHY		0
+#define  PORT_MODE_INT_GPHY		1
+#define  PORT_MODE_EXT_EPHY		2
+#define  PORT_MODE_EXT_GPHY		3
+#define  PORT_MODE_EXT_RVMII_25		(4 | BIT(4))
+#define  PORT_MODE_EXT_RVMII_50		4
+#define  LED_ACT_SOURCE_MAC		(1 << 9)
+
+#define SYS_RBUF_FLUSH_CTRL		0x08
+#define SYS_TBUF_FLUSH_CTRL		0x0C
+#define RBUF_FLUSH_CTRL_V1		0x04
+
+/* Ext block register offsets and definitions */
+#define EXT_EXT_PWR_MGMT		0x00
+#define  EXT_PWR_DOWN_BIAS		(1 << 0)
+#define  EXT_PWR_DOWN_DLL		(1 << 1)
+#define  EXT_PWR_DOWN_PHY		(1 << 2)
+#define  EXT_PWR_DN_EN_LD		(1 << 3)
+#define  EXT_ENERGY_DET			(1 << 4)
+#define  EXT_IDDQ_FROM_PHY		(1 << 5)
+#define  EXT_PHY_RESET			(1 << 8)
+#define  EXT_ENERGY_DET_MASK		(1 << 12)
+
+#define EXT_RGMII_OOB_CTRL		0x0C
+#define  RGMII_LINK			(1 << 4)
+#define  OOB_DISABLE			(1 << 5)
+#define  RGMII_MODE_EN			(1 << 6)
+#define  ID_MODE_DIS			(1 << 16)
+
+#define EXT_GPHY_CTRL			0x1C
+#define  EXT_CFG_IDDQ_BIAS		(1 << 0)
+#define  EXT_CFG_PWR_DOWN		(1 << 1)
+#define  EXT_CK25_DIS			(1 << 4)
+#define  EXT_GPHY_RESET			(1 << 5)
+
+/* DMA rings size */
+#define DMA_RING_SIZE			(0x40)
+#define DMA_RINGS_SIZE			(DMA_RING_SIZE * 17)
+
+/* DMA registers common definitions */
+#define DMA_RW_POINTER_MASK		0x1FF
+#define DMA_P_INDEX_DISCARD_CNT_MASK	0xFFFF
+#define DMA_P_INDEX_DISCARD_CNT_SHIFT	16
+#define DMA_BUFFER_DONE_CNT_MASK	0xFFFF
+#define DMA_BUFFER_DONE_CNT_SHIFT	16
+#define DMA_P_INDEX_MASK		0xFFFF
+#define DMA_C_INDEX_MASK		0xFFFF
+
+/* DMA ring size register */
+#define DMA_RING_SIZE_MASK		0xFFFF
+#define DMA_RING_SIZE_SHIFT		16
+#define DMA_RING_BUFFER_SIZE_MASK	0xFFFF
+
+/* DMA interrupt threshold register */
+#define DMA_INTR_THRESHOLD_MASK		0x01FF
+
+/* DMA XON/XOFF register */
+#define DMA_XON_THREHOLD_MASK		0xFFFF
+#define DMA_XOFF_THRESHOLD_MASK		0xFFFF
+#define DMA_XOFF_THRESHOLD_SHIFT	16
+
+/* DMA flow period register */
+#define DMA_FLOW_PERIOD_MASK		0xFFFF
+#define DMA_MAX_PKT_SIZE_MASK		0xFFFF
+#define DMA_MAX_PKT_SIZE_SHIFT		16
+
+
+/* DMA control register */
+#define DMA_EN				(1 << 0)
+#define DMA_RING_BUF_EN_SHIFT		0x01
+#define DMA_RING_BUF_EN_MASK		0xFFFF
+#define DMA_TSB_SWAP_EN			(1 << 20)
+
+/* DMA status register */
+#define DMA_DISABLED			(1 << 0)
+#define DMA_DESC_RAM_INIT_BUSY		(1 << 1)
+
+/* DMA SCB burst size register */
+#define DMA_SCB_BURST_SIZE_MASK		0x1F
+
+/* DMA activity vector register */
+#define DMA_ACTIVITY_VECTOR_MASK	0x1FFFF
+
+/* DMA backpressure mask register */
+#define DMA_BACKPRESSURE_MASK		0x1FFFF
+#define DMA_PFC_ENABLE			(1 << 31)
+
+/* DMA backpressure status register */
+#define DMA_BACKPRESSURE_STATUS_MASK	0x1FFFF
+
+/* DMA override register */
+#define DMA_LITTLE_ENDIAN_MODE		(1 << 0)
+#define DMA_REGISTER_MODE		(1 << 1)
+
+/* DMA timeout register */
+#define DMA_TIMEOUT_MASK		0xFFFF
+
+/* TDMA rate limiting control register */
+#define DMA_RATE_LIMIT_EN_MASK		0xFFFF
+
+/* TDMA arbitration control register */
+#define DMA_ARBITER_MODE_MASK		0x03
+#define DMA_RING_BUF_PRIORITY_MASK	0x1F
+#define DMA_RING_BUF_PRIORITY_SHIFT	5
+#define DMA_RATE_ADJ_MASK		0xFF
+
+/* Tx/Rx Dma Descriptor common bits*/
+#define DMA_BUFLENGTH_MASK		0x0fff
+#define DMA_BUFLENGTH_SHIFT		16
+#define DMA_OWN				0x8000
+#define DMA_EOP				0x4000
+#define DMA_SOP				0x2000
+#define DMA_WRAP			0x1000
+/* Tx specific Dma descriptor bits */
+#define DMA_TX_UNDERRUN			0x0200
+#define DMA_TX_APPEND_CRC		0x0040
+#define DMA_TX_OW_CRC			0x0020
+#define DMA_TX_DO_CSUM			0x0010
+#define DMA_TX_QTAG_SHIFT		7
+
+/* Rx Specific Dma descriptor bits */
+#define DMA_RX_CHK_V3PLUS		0x8000
+#define DMA_RX_CHK_V12			0x1000
+#define DMA_RX_BRDCAST			0x0040
+#define DMA_RX_MULT			0x0020
+#define DMA_RX_LG			0x0010
+#define DMA_RX_NO			0x0008
+#define DMA_RX_RXER			0x0004
+#define DMA_RX_CRC_ERROR		0x0002
+#define DMA_RX_OV			0x0001
+#define DMA_RX_FI_MASK			0x001F
+#define DMA_RX_FI_SHIFT			0x0007
+#define DMA_DESC_ALLOC_MASK		0x00FF
+
+#define DMA_ARBITER_RR			0x00
+#define DMA_ARBITER_WRR			0x01
+#define DMA_ARBITER_SP			0x02
+
+struct enet_cb {
+	struct sk_buff      *skb;
+	void __iomem *bd_addr;
+	DEFINE_DMA_UNMAP_ADDR(dma_addr);
+	DEFINE_DMA_UNMAP_LEN(dma_len);
+};
+
+/* power management mode */
+enum bcmgenet_power_mode {
+	GENET_POWER_CABLE_SENSE = 0,
+	GENET_POWER_WOL_MAGIC,
+	GENET_POWER_PASSIVE,
+};
+
+struct bcmgenet_priv;
+
+/* We support both runtime GENET detection and compile-time
+ * to optimize code-paths for a given hardware
+ */
+enum bcmgenet_version {
+	GENET_V1 = 1,
+	GENET_V2,
+	GENET_V3,
+	GENET_V4
+};
+
+#define GENET_IS_V1(p)		((p)->version == GENET_V1)
+#define GENET_IS_V2(p)		((p)->version == GENET_V2)
+#define GENET_IS_V3(p)		((p)->version == GENET_V3)
+#define GENET_IS_V4(p)		((p)->version == GENET_V4)
+
+/* Hardware flags */
+#define GENET_HAS_40BITS	(1 << 0)
+#define GENET_HAS_EXT		(1 << 1)
+#define GENET_HAS_MDIO_INTR	(1 << 2)
+#define GENET_HAS_MOCA_LINK_DET	(1 << 3)
+
+/* BCMGENET hardware parameters, keep this structure nicely aligned
+ * since it is going to be used in hot paths
+ */
+struct bcmgenet_hw_params {
+	u8		tx_queues;
+	u8		rx_queues;
+	u8		bds_cnt;
+	u8		bp_in_en_shift;
+	u32		bp_in_mask;
+	u8		hfb_filter_cnt;
+	u8		qtag_mask;
+	u16		tbuf_offset;
+	u32		hfb_offset;
+	u32		hfb_reg_offset;
+	u32		rdma_offset;
+	u32		tdma_offset;
+	u32		words_per_bd;
+	u32		flags;
+};
+
+struct bcmgenet_skb_cb {
+	unsigned int bytes_sent;	/* bytes on the wire (no TSB) */
+};
+
+#define GENET_CB(skb)	((struct bcmgenet_skb_cb *)((skb)->cb))
+
+struct bcmgenet_tx_ring {
+	spinlock_t	lock;		/* ring lock */
+	struct napi_struct napi;	/* NAPI per tx queue */
+	unsigned int	index;		/* ring index */
+	unsigned int	queue;		/* queue index */
+	struct enet_cb	*cbs;		/* tx ring buffer control block*/
+	unsigned int	size;		/* size of each tx ring */
+	unsigned int	c_index;	/* last consumer index of each ring*/
+	unsigned int	free_bds;	/* # of free bds for each ring */
+	unsigned int	write_ptr;	/* Tx ring write pointer SW copy */
+	unsigned int	prod_index;	/* Tx ring producer index SW copy */
+	unsigned int	cb_ptr;		/* Tx ring initial CB ptr */
+	unsigned int	end_ptr;	/* Tx ring end CB ptr */
+	void (*int_enable)(struct bcmgenet_priv *priv,
+				struct bcmgenet_tx_ring *);
+	void (*int_disable)(struct bcmgenet_priv *priv,
+				struct bcmgenet_tx_ring *);
+	struct bcmgenet_priv *priv;
+};
+
+/* context pause flags */
+#define BCM_PAUSE_FLAG_AUTO	(1 << 2)
+#define BCM_PAUSE_FLAG_RX	(1 << 1)
+#define BCM_PAUSE_FLAG_TX	(1 << 0)
+
+/* device context */
+struct bcmgenet_priv {
+	void __iomem *base;
+	enum bcmgenet_version version;
+	struct net_device *dev;	/* ptr to net_device */
+
+	/* NAPI for descriptor based rx */
+	struct napi_struct napi ____cacheline_aligned;
+
+	/* transmit variables */
+	void __iomem *tx_bds;	/* location of tx Dma BD ring */
+	struct enet_cb *tx_cbs;	/* locaation of tx control block pool */
+	int	num_tx_bds;		/* number of transmit bds */
+
+	struct bcmgenet_tx_ring tx_rings[17];
+
+	/* receive variables */
+	void __iomem *rx_bds;	/* location of rx bd ring */
+	void __iomem *rx_bd_assign_ptr;	/*next rx bd to assign buffer*/
+	int rx_bd_assign_index;	/* next rx bd to assign, index from rx_bds */
+	struct enet_cb *rx_cbs;	/* location of rx control block pool */
+	int	num_rx_bds;	/* number of receive bds */
+	int	rx_buf_len;	/* size of rx buffers for DMA */
+	unsigned int rx_read_ptr; /* Rx read pointer SW copy */
+	unsigned int rx_c_index;  /* Rx consumer index SW copy */
+
+	/* other misc variables */
+	struct bcmgenet_hw_params *hw_params;
+	wait_queue_head_t	wq;		/* mii wait queue */
+	struct phy_device *phydev;
+	struct device_node *phy_dn;
+	struct device_node *mdio_dn;
+	struct mii_bus *mii_bus;
+	u16 gphy_rev;
+	struct clk *clk_eee;
+	bool clk_eee_enabled;
+
+	/* PHY device variables */
+	int old_link;
+	int old_speed;
+	int old_duplex;
+	int old_pause;
+	phy_interface_t phy_interface;
+	u32 phy_supported;
+	int irq0;	/* regular IRQ */
+	int	irq1;	/* ring buf IRQ */
+	int	phy_addr;
+	int	phy_type;
+	int	phy_speed;
+	int	ext_phy;
+	int	sw_addr;
+	int	sw_type;
+	unsigned int irq0_stat;	/* sw copy of irq0 status, for IRQ BH */
+	unsigned int irq1_stat;	/* sw copy of irq1 status, for NAPI rx */
+	unsigned int desc_64b_en;
+	unsigned int desc_rxchk_en;
+	unsigned int dma_rx_chk_bit;
+	unsigned int crc_fwd_en;
+	unsigned int pause_flags;
+	u32 msg_enable;
+
+	struct work_struct bcmgenet_irq_work;	/* bottom half work */
+	struct clk *clk;
+	struct platform_device *pdev;
+	unsigned int old_dt_binding;
+
+	/* WOL */
+	struct	clk *clk_wol;
+	u32	wolopts;
+	int	wol_irq;
+	unsigned int wol_irq_disabled;
+
+	struct bcmgenet_mib_counters mib;
+
+	struct ethtool_eee eee;
+};
+
+#define GENET_IO_MACRO(name, offset)					\
+static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv,	\
+						u32 off)		\
+{									\
+	return __raw_readl(priv->base + offset + off);			\
+}									\
+static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv,	\
+					u32 val, u32 off)		\
+{									\
+	__raw_writel(val, priv->base + offset + off);			\
+}
+
+GENET_IO_MACRO(ext, GENET_EXT_OFF);
+GENET_IO_MACRO(umac, GENET_UMAC_OFF);
+GENET_IO_MACRO(sys, GENET_SYS_OFF);
+
+/* interrupt l2 registers accessors */
+GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
+GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
+
+/* HFB register accessors  */
+GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
+
+/* GENET v2+ HFB control and filter len helpers */
+GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
+
+/* RBUF register accessors */
+GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
+
+
+void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
+int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
+int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode);
+void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode);
+
+int bcmgenet_mii_init(struct net_device *dev);
+int bcmgenet_mii_config(struct net_device *dev);
+int bcmgenet_mii_probe(struct net_device *dev);
+void bcmgenet_mii_exit(struct net_device *dev);
+void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
+void bcmgenet_mii_setup(struct net_device *dev);
+int bcmgenet_phy_ethtool_set_pauseparam(struct phy_device *phydev,
+				struct ethtool_pauseparam *epause);
+
+#endif /* __BCMGENET_H__ */
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
new file mode 100644
index 000000000000..b7002196ea9e
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2002-2008 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define pr_fmt(fmt)				"bcmgenet_wol: " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <linux/platform_device.h>
+#include <net/arp.h>
+
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/phy.h>
+
+#include "bcmgenet.h"
+
+/* ethtool function - get WOL (Wake on LAN) settings, Only Magic Packet
+ * Detection is supported through ethtool
+ */
+void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
+	wol->wolopts = priv->wolopts;
+	memset(wol->sopass, 0, sizeof(wol->sopass));
+
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_MS);
+		put_unaligned_be16(reg, &wol->sopass[0]);
+		reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_LS);
+		put_unaligned_be32(reg, &wol->sopass[2]);
+	}
+}
+
+/* ethtool function - set WOL (Wake on LAN) settings.
+ * Only for magic packet detection mode.
+ */
+int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device *kdev = &priv->pdev->dev;
+	u32 reg;
+
+	if (!device_can_wakeup(kdev))
+		return -ENOTSUPP;
+
+	if (wol->wolopts & ~(WAKE_MAGIC | WAKE_MAGICSECURE))
+		return -EINVAL;
+
+	reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
+	if (wol->wolopts & WAKE_MAGICSECURE) {
+		bcmgenet_umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
+					UMAC_MPD_PW_MS);
+		bcmgenet_umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
+					UMAC_MPD_PW_LS);
+		reg |= MPD_PW_EN;
+	} else {
+		reg &= ~MPD_PW_EN;
+	}
+	bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
+
+	/* Flag the device and relevant IRQ as wakeup capable */
+	if (wol->wolopts) {
+		device_set_wakeup_enable(kdev, 1);
+		/* Avoid unbalanced enable_irq calls */
+		if (priv->wol_irq_disabled)
+			enable_irq_wake(priv->wol_irq);
+		priv->wol_irq_disabled = 0;
+	} else {
+		device_set_wakeup_enable(kdev, 0);
+		/* Avoid unbalanced disable_irq_wake calls */
+		if (!priv->wol_irq_disabled)
+			disable_irq_wake(priv->wol_irq);
+		priv->wol_irq_disabled = 1;
+	}
+
+	priv->wolopts = wol->wolopts;
+
+	return 0;
+}
+
+static int bcmgenet_poll_wol_status(struct bcmgenet_priv *priv)
+{
+	struct net_device *dev = priv->dev;
+	int retries = 0;
+
+	while (!(bcmgenet_rbuf_readl(priv, RBUF_STATUS)
+		& RBUF_STATUS_WOL)) {
+		retries++;
+		if (retries > 5) {
+			netdev_crit(dev, "polling wol mode timeout\n");
+			return -ETIMEDOUT;
+		}
+		mdelay(1);
+	}
+
+	return retries;
+}
+
+int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode)
+{
+	struct net_device *dev = priv->dev;
+	u32 cpu_mask_clear;
+	int retries = 0;
+	u32 reg;
+
+	if (mode != GENET_POWER_WOL_MAGIC) {
+		netif_err(priv, wol, dev, "unsupported mode: %d\n", mode);
+		return -EINVAL;
+	}
+
+	/* disable RX */
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	reg &= ~CMD_RX_EN;
+	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+	mdelay(10);
+
+	reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
+	reg |= MPD_EN;
+	bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
+
+	/* Do not leave UniMAC in MPD mode only */
+	retries = bcmgenet_poll_wol_status(priv);
+	if (retries < 0) {
+		reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
+		reg &= ~MPD_EN;
+		bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
+		return retries;
+	}
+
+	netif_dbg(priv, wol, dev, "MPD WOL-ready status set after %d msec\n",
+			retries);
+
+	/* Enable CRC forward */
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	priv->crc_fwd_en = 1;
+	reg |= CMD_CRC_FWD;
+
+	/* Receiver must be enabled for WOL MP detection */
+	reg |= CMD_RX_EN;
+	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+
+	if (priv->hw_params->flags & GENET_HAS_EXT) {
+		reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
+		reg &= ~EXT_ENERGY_DET_MASK;
+		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
+	}
+
+	/* Enable the MPD interrupt */
+	cpu_mask_clear = UMAC_IRQ_MPD_R;
+
+	bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
+
+	return 0;
+}
+
+void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
+				enum bcmgenet_power_mode mode)
+{
+	u32 cpu_mask_set;
+	u32 reg;
+
+	if (mode != GENET_POWER_WOL_MAGIC) {
+		netif_err(priv, wol, priv->dev, "invalid mode: %d\n", mode);
+		return;
+	}
+
+	reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL);
+	reg &= ~MPD_EN;
+	bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL);
+
+	/* Disable CRC Forward */
+	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+	reg &= ~CMD_CRC_FWD;
+	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+	priv->crc_fwd_en = 0;
+
+	/* Stop monitoring magic packet IRQ */
+	cpu_mask_set = UMAC_IRQ_MPD_R;
+
+	/* Stop monitoring magic packet IRQ */
+	bcmgenet_intrl2_0_writel(priv, cpu_mask_set, INTRL2_CPU_MASK_SET);
+}
diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c
new file mode 100644
index 000000000000..c3496ed579b0
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
@@ -0,0 +1,822 @@
+/*
+ *
+ * Copyright (c) 2002-2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *
+ *File Name  : bcmmii.c
+ *
+ *Description: Broadcom PHY/GPHY/Ethernet Switch Configuration
+ *Revision:	09/25/2008, L.Sun created.
+*/
+
+#include "bcmgenet.h"
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/brcmphy.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/platform_data/bcmgenet.h>
+
+/* read a value from the MII */
+static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
+{
+	int ret;
+	struct net_device *dev = bus->priv;
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
+	/* Start MDIO transaction*/
+	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
+	reg |= MDIO_START_BUSY;
+	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
+	wait_event_timeout(priv->wq,
+			!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
+				& MDIO_START_BUSY),
+			HZ/100);
+	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
+
+	/* Don't check error codes from switches, as some of them are
+	 * known to return MDIO_READ_FAIL on good transactions
+	 */
+	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) &&
+	    (ret & MDIO_READ_FAIL)) {
+		netif_dbg(priv, hw, dev, "MDIO read failure\n");
+		ret = 0;
+	}
+	return ret & 0xffff;
+}
+
+/* write a value to the MII */
+static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
+			int location, u16 val)
+{
+	struct net_device *dev = bus->priv;
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 reg;
+
+	bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+			(location << MDIO_REG_SHIFT) | (0xffff & val)),
+			UMAC_MDIO_CMD);
+	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
+	reg |= MDIO_START_BUSY;
+	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
+	wait_event_timeout(priv->wq,
+			!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
+				MDIO_START_BUSY),
+			HZ/100);
+
+	return 0;
+}
+
+static u32 _flow_control_autoneg(struct phy_device *phydev)
+{
+	u32 cmd_bits;
+
+	if (phydev->pause && (phydev->advertising & ADVERTISED_Pause)) {
+		/* Symmetric Flow Control */
+		cmd_bits = 0;
+	} else {
+		/* Not Symmetric so default to no flow control */
+		cmd_bits = CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
+
+		/* Check for Asymmetric */
+		if (phydev->asym_pause &&
+			phydev->advertising & ADVERTISED_Asym_Pause) {
+			if (phydev->advertising & ADVERTISED_Pause)
+				cmd_bits &= ~CMD_RX_PAUSE_IGNORE;
+			else if (phydev->pause)
+				cmd_bits &= ~CMD_TX_PAUSE_IGNORE;
+		}
+	}
+
+	return cmd_bits;
+}
+
+/* setup netdev link state when PHY link status change and
+ * update UMAC and RGMII block when link up
+ */
+void bcmgenet_mii_setup(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct phy_device *phydev = priv->phydev;
+	u32 reg, cmd_bits = 0;
+	bool status_changed = false;
+
+	if (priv->old_link != phydev->link) {
+		status_changed = 1;
+		priv->old_link = phydev->link;
+	}
+
+	if (phydev->link) {
+		/* check speed/duplex/pause changes */
+		if (priv->old_speed != phydev->speed) {
+			status_changed = true;
+			priv->old_speed = phydev->speed;
+		}
+
+		if (priv->old_duplex != phydev->duplex) {
+			status_changed = true;
+			priv->old_duplex = phydev->duplex;
+		}
+
+		if (priv->old_pause != phydev->pause) {
+			status_changed = true;
+			priv->old_pause = phydev->pause;
+		}
+
+		/* done if nothing has changed */
+		if (!status_changed)
+			return;
+
+		/* program UMAC and RGMII block based on established link
+		 * speed, pause, and duplex.
+		 * the speed set in umac->cmd tell RGMII block which clock
+		 * 25MHz(100Mbps)/125MHz(1Gbps) to use for transmit.
+		 * receive clock is provided by PHY.
+		 */
+		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
+		reg &= ~OOB_DISABLE;
+		reg |= RGMII_LINK;
+		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
+
+		/* speed */
+		if (phydev->speed == SPEED_1000)
+			cmd_bits = UMAC_SPEED_1000;
+		else if (phydev->speed == SPEED_100)
+			cmd_bits = UMAC_SPEED_100;
+		else
+			cmd_bits = UMAC_SPEED_10;
+		cmd_bits <<= CMD_SPEED_SHIFT;
+
+		/* duplex */
+		if (phydev->duplex != DUPLEX_FULL) {
+			cmd_bits |= CMD_HD_EN |
+				CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
+		} else {
+			/* pause capability defaults to Symmetric */
+			if (priv->pause_flags & BCM_PAUSE_FLAG_AUTO)
+				cmd_bits |= _flow_control_autoneg(phydev);
+
+			/* Manual override */
+			if (!(priv->pause_flags & BCM_PAUSE_FLAG_RX))
+				cmd_bits |= CMD_RX_PAUSE_IGNORE;
+			if (!(priv->pause_flags & BCM_PAUSE_FLAG_TX))
+				cmd_bits |= CMD_TX_PAUSE_IGNORE;
+		}
+
+		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
+		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
+			 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
+			 CMD_TX_PAUSE_IGNORE);
+		reg |= cmd_bits;
+		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
+	} else {
+		/* done if nothing has changed */
+		if (!status_changed)
+			return;
+
+		/* needed for MoCA fixed PHY to reflect correct link status */
+		netif_carrier_off(dev);
+	}
+
+	phy_print_status(phydev);
+}
+
+/* This functionality really belongs in genphy_config_advert(), but is here
+ * because there is no mechanism for saving the ethtool pause settings in a
+ * generic PHY device yet
+ */
+static void _phy_pause_set(struct phy_device *phydev, unsigned int flags)
+{
+	unsigned int advertise;
+
+	advertise = phydev->advertising &
+		~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
+
+	if (flags & BCM_PAUSE_FLAG_AUTO) {
+		if (flags & BCM_PAUSE_FLAG_RX)
+			advertise |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
+		else if (flags & BCM_PAUSE_FLAG_TX)
+			advertise |= ADVERTISED_Asym_Pause;
+	}
+
+	advertise &= phydev->supported;
+	phydev->advertising = advertise;
+}
+
+/* This function is trapped here because no generic implementation exists */
+int bcmgenet_phy_ethtool_set_pauseparam(struct phy_device *phydev,
+				struct ethtool_pauseparam *epause)
+{
+	unsigned int pause_flags = 0;
+
+	if (epause->rx_pause)
+		pause_flags |= BCM_PAUSE_FLAG_RX;
+	if (epause->tx_pause)
+		pause_flags |= BCM_PAUSE_FLAG_TX;
+	if (epause->autoneg)
+		pause_flags |= BCM_PAUSE_FLAG_AUTO;
+
+	_phy_pause_set(phydev, pause_flags);
+
+	return 0;
+}
+
+/* 7366a0 EXT GPHY block comes with the CFG_IDDQ_BIAS and CFG_EXT_PWR_DOWN
+ * bits set to 1 at reset, they need to be cleared. A reset must also be
+ * issued. An initial reset value of 1500 micro seconds was not enough, 2000
+ * micro seconds always works. The post-reset delay of 20 micro seconds could
+ * be eliminated but better be safe than sorry.
+ */
+void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	u32 reg = 0;
+
+	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
+	if (!GENET_IS_V4(priv))
+		return;
+
+	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
+	if (enable) {
+		reg &= ~EXT_CK25_DIS;
+		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+		mdelay(1);
+
+		reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
+		reg |= EXT_GPHY_RESET;
+		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+		mdelay(1);
+
+		reg &= ~EXT_GPHY_RESET;
+	} else {
+		reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
+		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+		mdelay(1);
+		reg |= EXT_CK25_DIS;
+	}
+	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
+	udelay(60);
+}
+
+int bcmgenet_mii_probe(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device_node *dn = priv->pdev->dev.of_node;
+	struct phy_device *phydev;
+	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *fixed_bus = NULL;
+	int phy_addr = priv->phy_addr;
+	u32 phy_flags;
+	int ret;
+
+	if (priv->old_dt_binding) {
+		/* Bind to fixed-0 for MOCA and switches */
+		if (priv->phy_type == BRCM_PHY_TYPE_MOCA ||
+			priv->phy_addr == BRCM_PHY_ID_NONE) {
+			fixed_bus = "fixed-0";
+		}
+
+		/* Use the second fixed PHY */
+		if (priv->phy_addr == BRCM_PHY_ID_NONE)
+			phy_addr = 1;
+
+		/* Connect either on the real MII bus or on the fixed one */
+		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
+			fixed_bus ? fixed_bus : priv->mii_bus->id,
+		phy_addr);
+	}
+
+	phy_flags = priv->gphy_rev;
+
+	/* Initialize link state variables that bcmgenet_mii_setup() uses */
+	priv->old_link = -1;
+	priv->old_speed = -1;
+	priv->old_duplex = -1;
+	priv->old_pause = -1;
+
+	if (dn && priv->old_dt_binding) {
+		phydev = phy_connect(dev, phy_id, bcmgenet_mii_setup,
+				priv->phy_interface);
+	} else if (dn) {
+		phydev = of_phy_connect(dev, priv->phy_dn,
+					bcmgenet_mii_setup, phy_flags,
+					priv->phy_interface);
+	} else {
+		phydev = priv->phydev;
+		phydev->dev_flags = phy_flags;
+
+		ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
+					 priv->phy_interface);
+		if (ret) {
+			pr_err("could not attach to PHY\n");
+			return -ENODEV;
+		}
+	}
+
+	if (!phydev) {
+		pr_err("could not attach to PHY\n");
+		return -ENODEV;
+	}
+
+	priv->phydev = phydev;
+
+	ret = bcmgenet_mii_config(dev);
+	if (ret) {
+		phy_disconnect(phydev);
+		return ret;
+	}
+
+	/*
+	 * The device-tree processing of the child nodes of the mdio bus by
+	 * of_mdiobus_register resets the supported pause features in an effort
+	 * to choose "sane defaults".
+	 *
+	 * Since bcmgenet can support pause without requiring phydev support,
+	 * but pause support cannot be advertised unless the phydev indicates
+	 * support for it, reenable the pause flags here.
+	 *
+	 * However, allow bcmgenet_mii_config() to override them.
+	 */
+	phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+	phydev->supported &= priv->phy_supported;
+
+	/* Adjust advertised speeds based on configured speed */
+	if (priv->phy_speed == SPEED_1000)
+		phydev->advertising = PHY_GBIT_FEATURES;
+	else
+		phydev->advertising = PHY_BASIC_FEATURES;
+	_phy_pause_set(phydev, priv->pause_flags);
+
+	return 0;
+}
+
+/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
+ * their internal MDIO management controller making them fail to successfully
+ * be read from or written to for the first transaction.  We insert a dummy
+ * BMSR read here to make sure that phy_get_device() and get_phy_id() can
+ * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
+ * PHY device for this peripheral.
+ *
+ * Once the PHY driver is registered, we can workaround subsequent reads from
+ * there (e.g: during system-wide power management).
+ *
+ * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
+ * therefore the right location to stick that workaround. Since we do not want
+ * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
+ * Device Tree scan to limit the search area.
+ */
+static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
+{
+	struct net_device *dev = bus->priv;
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	struct device_node *np = priv->mdio_dn;
+	struct device_node *child = NULL;
+	u32 read_mask = 0;
+	int addr = 0;
+
+	if (!np) {
+		read_mask = 1 << priv->phy_addr;
+	} else {
+		for_each_available_child_of_node(np, child) {
+			addr = of_mdio_parse_addr(&dev->dev, child);
+			if (addr < 0)
+				continue;
+
+			read_mask |= 1 << addr;
+		}
+	}
+
+	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+		if (read_mask & 1 << addr) {
+			dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
+			mdiobus_read(bus, addr, MII_BMSR);
+		}
+	}
+
+	return 0;
+}
+
+static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
+{
+	struct mii_bus *bus;
+	int ret = 0;
+
+	if (priv->mii_bus)
+		return 0;
+
+	priv->mii_bus = mdiobus_alloc();
+	if (!priv->mii_bus) {
+		pr_err("failed to allocate\n");
+		return -ENOMEM;
+	}
+
+	bus = priv->mii_bus;
+	bus->priv = priv->dev;
+	bus->name = "bcmgenet MII bus";
+	bus->parent = &priv->pdev->dev;
+	bus->read = bcmgenet_mii_read;
+	bus->write = bcmgenet_mii_write;
+	bus->reset = bcmgenet_mii_bus_reset;
+	if (priv->old_dt_binding)
+		bus->phy_mask = ~(1 << priv->phy_addr);
+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
+			priv->pdev->name, priv->pdev->id);
+
+	bus->irq = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!bus->irq) {
+		ret = -ENOMEM;
+		goto out_mdio_free;
+	}
+
+	/* This is the correct thing to do, but libphy needs fixing
+	 * with respect to ignoring interrupts
+	 */
+	if (priv->phy_addr < PHY_MAX_ADDR) {
+		if (priv->phy_type == BRCM_PHY_TYPE_INT)
+			bus->irq[priv->phy_addr] = PHY_IGNORE_INTERRUPT;
+		else
+			bus->irq[priv->phy_addr] = PHY_POLL;
+	}
+
+	return 0;
+
+out_mdio_free:
+	mdiobus_free(priv->mii_bus);
+	return ret;
+}
+
+static void bcmgenet_mii_free(struct bcmgenet_priv *priv)
+{
+	mdiobus_unregister(priv->mii_bus);
+	kfree(priv->mii_bus->irq);
+	mdiobus_free(priv->mii_bus);
+}
+
+static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
+					  struct fixed_phy_status *status)
+{
+	if (dev && dev->phydev && status)
+		status->link = dev->phydev->link;
+
+	return 0;
+}
+
+static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
+{
+	u32 reg;
+
+	/* Speed settings are set in bcmgenet_mii_setup() */
+	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
+	reg |= LED_ACT_SOURCE_MAC;
+	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
+
+	/* Register a fixed PHY link_update callback for this interface */
+	if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
+		fixed_phy_set_link_update(priv->phydev,
+					  bcmgenet_fixed_phy_link_update);
+}
+
+int bcmgenet_mii_config(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	const char *phy_name = NULL;
+	u32 id_mode_dis = 0;
+	u32 port_ctrl;
+	u32 reg;
+
+	priv->ext_phy = (priv->phy_type != BRCM_PHY_TYPE_INT) &&
+			(priv->phy_type != BRCM_PHY_TYPE_MOCA);
+
+	switch (priv->phy_interface) {
+	case PHY_INTERFACE_MODE_NA:
+	case PHY_INTERFACE_MODE_MOCA:
+		phy_name = "internal PHY";
+		/* Irrespective of the actually configured PHY speed (100 or
+		 * 1000) GENETv4 only has an internal GPHY so we will just end
+		 * up masking the Gigabit features from what we support, not
+		 * switching to the EPHY
+		 */
+		if (GENET_IS_V4(priv)) {
+			priv->phy_supported = PHY_GBIT_FEATURES;
+			port_ctrl = PORT_MODE_INT_GPHY;
+		} else {
+			priv->phy_supported = PHY_BASIC_FEATURES;
+			port_ctrl = PORT_MODE_INT_EPHY;
+		}
+
+		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
+
+		if (priv->phy_type == BRCM_PHY_TYPE_INT) {
+			priv->phy_supported |=
+				SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+		} else if (priv->phy_type == BRCM_PHY_TYPE_MOCA) {
+			phy_name = "MoCA";
+			bcmgenet_moca_phy_setup(priv);
+			priv->phy_supported = PHY_GBIT_FEATURES;
+		}
+		break;
+
+	case PHY_INTERFACE_MODE_MII:
+		phy_name = "external MII";
+		priv->phy_supported = PHY_BASIC_FEATURES;
+		bcmgenet_sys_writel(priv,
+				PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
+		break;
+
+	case PHY_INTERFACE_MODE_REVMII:
+		phy_name = "external RvMII";
+		if (priv->phy_speed == SPEED_100) {
+			priv->phy_supported = PHY_BASIC_FEATURES;
+			port_ctrl = PORT_MODE_EXT_RVMII_25;
+		} else {
+			priv->phy_supported = PHY_GBIT_FEATURES;
+			port_ctrl = PORT_MODE_EXT_RVMII_50;
+		}
+		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+		/*
+		 * RGMII_NO_ID: TXC transitions at the same time as TXD
+		 *              (requires PCB or receiver-side delay)
+		 * RGMII:       Add 2ns delay on TXC (90 degree shift)
+		 *
+		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
+		 */
+		id_mode_dis = BIT(16);
+		/* fall through */
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		if (id_mode_dis)
+			phy_name = "external RGMII (no delay)";
+		else
+			phy_name = "external RGMII (TX delay)";
+		bcmgenet_sys_writel(priv,
+				PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
+		priv->phy_supported = PHY_GBIT_FEATURES;
+		/*
+		 * setup mii based on configure speed and RGMII txclk is set in
+		 * umac->cmd, mii_setup() after link established.
+		 */
+		break;
+	default:
+		dev_err(&priv->pdev->dev, "unknown phy_interface: %d\n",
+			priv->phy_interface);
+		return -EINVAL;
+	}
+
+	/* This is an external PHY, aka xMII, so we need to enable the RGMII
+	 * block for the interface to work
+	 */
+	if (priv->ext_phy) {
+		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
+		reg |= RGMII_MODE_EN | id_mode_dis;
+		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
+	}
+
+	pr_info_once("%s: configuring instance for %s\n",
+		     dev_name(&priv->pdev->dev), phy_name);
+
+	return 0;
+}
+
+static int bcmgenet_mii_new_dt_init(struct bcmgenet_priv *priv)
+{
+	struct device_node *dn = priv->pdev->dev.of_node;
+	struct device *kdev = &priv->pdev->dev;
+	const char *phy_mode_str = NULL;
+	struct phy_device *phydev;
+	u32 propval;
+	int phy_mode;
+	int ret;
+
+	priv->mdio_dn = of_get_next_child(dn, NULL);
+	if (!priv->mdio_dn) {
+		dev_err(kdev, "unable to find MDIO bus node\n");
+		return -ENODEV;
+	}
+
+	ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
+	if (ret) {
+		dev_err(kdev, "failed to register MDIO bus\n");
+		return ret;
+	}
+
+	/* Check if we have an internal or external PHY */
+	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
+	if (priv->phy_dn) {
+		if (!of_property_read_u32(priv->phy_dn, "max-speed", &propval))
+			priv->phy_speed = propval;
+	} else {
+		if (of_phy_is_fixed_link(dn)) {
+			ret = of_phy_register_fixed_link(dn);
+			if (ret)
+				return ret;
+		}
+
+		priv->phy_dn = of_node_get(dn);
+	}
+
+	/* Get the link mode */
+	phy_mode = of_get_phy_mode(dn);
+	priv->phy_interface = phy_mode;
+
+	/* This is not a standard "phy-mode" do an explicit look */
+	if (phy_mode < 0) {
+		ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
+		if (ret < 0) {
+			dev_err(kdev, "invalid PHY mode property\n");
+			return ret;
+		}
+
+		priv->phy_interface = PHY_INTERFACE_MODE_NA;
+		if (!strcasecmp(phy_mode_str, "internal"))
+			priv->phy_type = BRCM_PHY_TYPE_INT;
+		else {
+			dev_err(kdev, "invalid PHY mode: %s\n", phy_mode_str);
+			return ret;
+		}
+	}
+
+	if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
+		priv->phy_type = BRCM_PHY_TYPE_MOCA;
+
+		/* Make sure we initialize MoCA PHY with a link down */
+		phydev = of_phy_find_device(dn);
+		if (phydev)
+			phydev->link = 0;
+	}
+
+
+	return 0;
+}
+
+static int bcmgenet_mii_old_dt_init(struct bcmgenet_priv *priv)
+{
+	int ret;
+
+	ret = mdiobus_register(priv->mii_bus);
+	if (ret) {
+		kfree(priv->mii_bus->irq);
+		return ret;
+	}
+
+	/* Ensure we set a correct phy_type to phy_interface
+	 * translation
+	 */
+	switch (priv->phy_type) {
+	case BRCM_PHY_TYPE_MOCA:
+		priv->phy_addr = 0;
+		/* fall-through */
+	case BRCM_PHY_TYPE_INT:
+	default:
+		priv->phy_interface = PHY_INTERFACE_MODE_NA;
+		break;
+
+	case BRCM_PHY_TYPE_EXT_MII:
+		priv->phy_interface = PHY_INTERFACE_MODE_MII;
+		break;
+
+	case BRCM_PHY_TYPE_EXT_RVMII:
+		priv->phy_interface = PHY_INTERFACE_MODE_REVMII;
+		break;
+
+	case BRCM_PHY_TYPE_EXT_RGMII_NO_ID:
+		priv->phy_interface = PHY_INTERFACE_MODE_RGMII;
+		break;
+
+	case BRCM_PHY_TYPE_EXT_RGMII:
+	case BRCM_PHY_TYPE_EXT_RGMII_IBS:
+		priv->phy_interface = PHY_INTERFACE_MODE_RGMII_TXID;
+		break;
+	}
+
+	return 0;
+}
+
+static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
+{
+	struct device *kdev = &priv->pdev->dev;
+	struct bcmgenet_platform_data *pd = kdev->platform_data;
+	struct mii_bus *mdio = priv->mii_bus;
+	struct phy_device *phydev;
+	int ret;
+
+	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
+		/*
+		 * Internal or external PHY with MDIO access
+		 */
+		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
+			mdio->phy_mask = ~(1 << pd->phy_address);
+		else
+			mdio->phy_mask = 0;
+
+		ret = mdiobus_register(mdio);
+		if (ret) {
+			dev_err(kdev, "failed to register MDIO bus\n");
+			return ret;
+		}
+
+		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
+			phydev = mdio->phy_map[pd->phy_address];
+		else
+			phydev = phy_find_first(mdio);
+
+		if (!phydev) {
+			dev_err(kdev, "failed to register PHY device\n");
+			mdiobus_unregister(mdio);
+			return -ENODEV;
+		}
+	} else {
+		/*
+		 * MoCA port or no MDIO access.
+		 * Use fixed PHY to represent the link layer.
+		 */
+		struct fixed_phy_status fphy_status = {
+			.link = 1,
+			.speed = pd->phy_speed,
+			.duplex = pd->phy_duplex,
+			.pause = 0,
+			.asym_pause = 0,
+		};
+
+		priv->phy_speed = pd->phy_speed;
+
+		phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
+		if (!phydev || IS_ERR(phydev)) {
+			dev_err(kdev, "failed to register fixed PHY device\n");
+			return -ENODEV;
+		}
+	}
+
+	priv->phydev = phydev;
+	priv->phy_interface = pd->phy_interface;
+
+	return 0;
+}
+
+static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
+{
+	struct device_node *dn = priv->pdev->dev.of_node;
+	int ret = 0;
+
+	if (dn) {
+		if (priv->old_dt_binding)
+			ret = bcmgenet_mii_old_dt_init(priv);
+		else
+			ret = bcmgenet_mii_new_dt_init(priv);
+	} else {
+		ret = bcmgenet_mii_pd_init(priv);
+	}
+
+	return ret;
+}
+
+int bcmgenet_mii_init(struct net_device *dev)
+{
+	struct bcmgenet_priv *priv = netdev_priv(dev);
+	int ret;
+
+	ret = bcmgenet_mii_alloc(priv);
+	if (ret)
+		return ret;
+
+	ret = bcmgenet_mii_bus_init(priv);
+	if (ret)
+		goto out;
+
+	return 0;
+out:
+	bcmgenet_mii_free(priv);
+	return ret;
+}
+
+void bcmgenet_mii_exit(struct net_device *dev)
+{
+	bcmgenet_mii_free(netdev_priv(dev));
+}
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 9b5d46c03eed..b1557de245f4 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -65,12 +65,24 @@ config BROADCOM_PHY
 	  Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481
 	  and BCM5482 PHYs.
 
+config BCM531XX_PHY
+	tristate "Drivers for Broadcom BCM531XX switches"
+	---help---
+	  Currently supports the Broadcom BCM53101 and BCM53125 external
+	  switches.
+
 config BCM63XX_PHY
 	tristate "Drivers for Broadcom 63xx SOCs internal PHY"
 	depends on BCM63XX
 	---help---
 	  Currently supports the 6348 and 6358 PHYs.
 
+config BCM7XXX_PHY
+	tristate "Drivers for Broadcom 7xxx SOCs internal PHY"
+	depends on BRCMSTB
+	---help---
+	  Currently supports the 65, 40 and 28nm 7xxx SoCs.
+
 config BCM87XX_PHY
 	tristate "Driver for Broadcom BCM8706 and BCM8727 PHYs"
 	help
@@ -193,6 +205,12 @@ config MDIO_BUS_MUX_MMIOREG
 
 	  Currently, only 8-bit registers are supported.
 
+config MDIO_UNIMAC
+	tristate "Broadcom UniMAC MDIO bus controller"
+	help
+	  This module provides a driver for the Broadcom UniMAC MDIO busses.
+	  It is required by the Broadcom GENET Ethernet device drivers.
+
 endif # PHYLIB
 
 config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9013dfa12aa3..6ce9cf797387 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -11,7 +11,9 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
 obj-$(CONFIG_SMSC_PHY)		+= smsc.o
 obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o
 obj-$(CONFIG_BROADCOM_PHY)	+= broadcom.o
+obj-$(CONFIG_BCM531XX_PHY)	+= ethsw.o
 obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
+obj-$(CONFIG_BCM7XXX_PHY)	+= bcm7xxx.o
 obj-$(CONFIG_BCM87XX_PHY)	+= bcm87xx.o
 obj-$(CONFIG_ICPLUS_PHY)	+= icplus.o
 obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
@@ -32,3 +34,4 @@ obj-$(CONFIG_MDIO_BUS_MUX_GPIO)	+= mdio-mux-gpio.o
 obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
 obj-$(CONFIG_MDIO_SUN4I)	+= mdio-sun4i.o
 obj-$(CONFIG_MDIO_MOXART)	+= mdio-moxart.o
+obj-$(CONFIG_MDIO_UNIMAC)	+= mdio-unimac.o
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
new file mode 100644
index 000000000000..eeec49c7da10
--- /dev/null
+++ b/drivers/net/phy/bcm7xxx.c
@@ -0,0 +1,443 @@
+/*
+ * Broadcom BCM7xxx internal transceivers support.
+ *
+ * Copyright (C) 2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/delay.h>
+#include <linux/mdio.h>
+#include <linux/brcmphy.h>
+#include <linux/clk.h>
+
+struct bcm7xxx_phy_priv {
+	struct clk	*clk;
+};
+
+static int bcm7xxx_apd_enable(struct phy_device *phydev)
+{
+	int val;
+
+	/* Enable powering down of the DLL during auto-power down */
+	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
+	if (val < 0)
+		return val;
+
+	val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
+	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
+
+	/* Enable auto-power down */
+	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
+	if (val < 0)
+		return val;
+
+	val |= BCM54XX_SHD_APD_EN;
+	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
+}
+
+static int bcm7xxx_eee_enable(struct phy_device *phydev)
+{
+	int val;
+
+	val = phy_read_mmd_indirect(phydev->bus, CL45VEN_EEE_CONTROL,
+				    MDIO_MMD_AN, phydev->addr);
+	if (val < 0)
+		return val;
+
+	/* Enable general EEE feature at the PHY level */
+	val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
+
+	phy_write_mmd_indirect(phydev->bus, CL45VEN_EEE_CONTROL,
+			       MDIO_MMD_AN, phydev->addr, val);
+
+	/* Advertise supported modes */
+	val = phy_read_mmd_indirect(phydev->bus, MDIO_AN_EEE_ADV,
+				    MDIO_MMD_AN, phydev->addr);
+
+	val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
+	phy_write_mmd_indirect(phydev->bus, MDIO_AN_EEE_ADV,
+			       MDIO_MMD_AN, phydev->addr, val);
+
+	return 0;
+}
+
+static void phy_write_exp(struct phy_device *phydev,
+					u16 reg, u16 value)
+{
+	phy_write(phydev, 0x17, 0xf00 | reg);
+	phy_write(phydev, 0x15, value);
+}
+
+static void phy_write_misc(struct phy_device *phydev,
+					u16 reg, u16 chl, u16 value)
+{
+	int tmp;
+
+	phy_write(phydev, 0x18, 0x7);
+
+	tmp = phy_read(phydev, 0x18);
+	tmp |= 0x800;
+	phy_write(phydev, 0x18, tmp);
+
+	tmp = (chl * 0x2000) | reg;
+	phy_write(phydev, 0x17, tmp);
+
+	phy_write(phydev, 0x15, value);
+}
+
+static void r_rc_cal_reset(struct phy_device *phydev)
+{
+	/* Reset R_CAL/RC_CAL Engine */
+	phy_write_exp(phydev, 0x00b0, 0x0010);
+
+	/* Disable Reset R_AL/RC_CAL Engine */
+	phy_write_exp(phydev, 0x00b0, 0x0000);
+}
+
+static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
+{
+	/* Increase VCO range to prevent unlocking problem of PLL at low
+	 * temp
+	 */
+	phy_write_misc(phydev, 0x0032, 0x0001, 0x0048);
+
+	/* Change Ki to 011 */
+	phy_write_misc(phydev, 0x0032, 0x0002, 0x021b);
+
+	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
+	 * to 111
+	 */
+	phy_write_misc(phydev, 0x0033, 0x0000, 0x0e20);
+
+	/* Adjust bias current trim by -3 */
+	phy_write_misc(phydev, 0x000a, 0x0000, 0x690b);
+
+	/* Switch to CORE_BASE1E */
+	phy_write(phydev, 0x1e, 0xd);
+
+	r_rc_cal_reset(phydev);
+
+	/* write AFE_RXCONFIG_0 */
+	phy_write_misc(phydev, 0x38, 0x0000, 0xeb19);
+
+	/* write AFE_RXCONFIG_1 */
+	phy_write_misc(phydev, 0x38, 0x0001, 0x9a3f);
+
+	/* write AFE_RX_LP_COUNTER */
+	phy_write_misc(phydev, 0x38, 0x0003, 0x7fc0);
+
+	/* write AFE_HPF_TRIM_OTHERS */
+	phy_write_misc(phydev, 0x3A, 0x0000, 0x000b);
+
+	/* write AFTE_TX_CONFIG */
+	phy_write_misc(phydev, 0x39, 0x0000, 0x0800);
+
+	return 0;
+}
+
+static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
+{
+	/* AFE_RXCONFIG_0 */
+	phy_write_misc(phydev, 0x0038, 0x0000, 0xeb15);
+
+	/* AFE_RXCONFIG_1 */
+	phy_write_misc(phydev, 0x0038, 0x0001, 0x9b2f);
+
+	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
+	phy_write_misc(phydev, 0x0038, 0x0002, 0x2003);
+
+	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
+	phy_write_misc(phydev, 0x0038, 0x0003, 0x7fc0);
+
+	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
+	phy_write_misc(phydev, 0x0039, 0x0000, 0x0431);
+
+	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
+	phy_write_misc(phydev, 0x0039, 0x0001, 0xa7da);
+
+	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
+	phy_write_misc(phydev, 0x0039, 0x0003, 0xa020);
+
+	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
+	 * offset for HT=0 code
+	 */
+	phy_write_misc(phydev, 0x003a, 0x0000, 0x00e3);
+
+	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
+	phy_write(phydev, 0x001e, 0x0010);
+
+	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
+	phy_write_misc(phydev, 0x000a, 0x0000, 0x011b);
+
+	/* Reset R_CAL/RC_CAL engine */
+	r_rc_cal_reset(phydev);
+
+	return 0;
+}
+
+static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
+{
+	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement on ATE */
+	phy_write_misc(phydev, 0x0038, 0x0001, 0x9b2f);
+
+	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
+	phy_write_misc(phydev, 0x0039, 0x0000, 0x0431);
+
+	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
+	phy_write_misc(phydev, 0x0039, 0x0001, 0xa7da);
+
+	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
+	 * offset for HT=0 code
+	 */
+	phy_write_misc(phydev, 0x003a, 0x0000, 0x00e3);
+
+	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
+	phy_write(phydev, 0x001e, 0x0010);
+
+	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
+	phy_write_misc(phydev, 0x000a, 0x0000, 0x011b);
+
+	/* Reset R_CAL/RC_CAL engine */
+	r_rc_cal_reset(phydev);
+
+	return 0;
+}
+
+static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
+{
+	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
+	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
+	int ret = 0;
+
+	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
+		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);
+
+	/* Dummy read to a register to workaround an issue upon reset where the
+	 * internal inverter may not allow the first MDIO transaction to pass
+	 * the MDIO management controller and make us return 0xffff for such
+	 * reads.
+	 */
+	phy_read(phydev, MII_BMSR);
+
+	switch (rev) {
+	case 0xb0:
+		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
+		break;
+	case 0xd0:
+		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
+		break;
+	case 0xe0:
+	case 0xf0:
+	/* Rev G0 introduces a roll over */
+	case 0x10:
+		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
+		break;
+	default:
+		break;
+	}
+
+	if (ret)
+		return ret;
+
+	ret = bcm7xxx_eee_enable(phydev);
+	if (ret)
+		return ret;
+
+	return bcm7xxx_apd_enable(phydev);
+}
+
+static int bcm7xxx_28nm_resume(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = bcm7xxx_28nm_config_init(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_config_aneg(phydev);
+}
+
+static int phy_set_clr_bits(struct phy_device *dev, int location,
+					int set_mask, int clr_mask)
+{
+	int v, ret;
+
+	v = phy_read(dev, location);
+	if (v < 0)
+		return v;
+
+	v &= ~clr_mask;
+	v |= set_mask;
+
+	ret = phy_write(dev, location, v);
+	if (ret < 0)
+		return ret;
+
+	return v;
+}
+
+static int bcm7xxx_config_init(struct phy_device *phydev)
+{
+	/* Enable 64 clock MDIO */
+	phy_write(phydev, 0x1d, 0x1000);
+	phy_read(phydev, 0x1d);
+
+	/* Workaround only required for 100Mbits/sec capable PHYs */
+	if (phydev->supported & PHY_GBIT_FEATURES)
+		return 0;
+
+	/* set shadow mode 2 */
+	phy_set_clr_bits(phydev, 0x1f, 0x0004, 0x0004);
+
+	/* Workaround for SWLINUX-2281: explicitly reset IDDQ_CLKBIAS
+	 * in the Shadow 2 regset, due to power sequencing issues.
+	 */
+	/* set iddq_clkbias */
+	phy_write(phydev, 0x14, 0x0F00);
+	udelay(10);
+	/* reset iddq_clkbias */
+	phy_write(phydev, 0x14, 0x0C00);
+
+	/* Workaround for SWLINUX-2056: fix timing issue between the ephy
+	 * digital and the ephy analog blocks.  This clock inversion will
+	 * inherently fix any setup and hold issue.
+	 */
+	phy_write(phydev, 0x13, 0x7555);
+
+	/* reset shadow mode 2 */
+	phy_set_clr_bits(phydev, 0x1f, 0x0004, 0);
+
+	return 0;
+}
+
+/* Workaround for putting the PHY in IDDQ mode, required
+ * for all BCM7XXX 40nm and 65nm PHYs
+ */
+static int bcm7xxx_suspend(struct phy_device *phydev)
+{
+	int ret;
+	const struct bcm7xxx_regs {
+		int reg;
+		u16 value;
+	} bcm7xxx_suspend_cfg[] = {
+		{ 0x1f, 0x008b },
+		{ 0x10, 0x01c0 },
+		{ 0x14, 0x7000 },
+		{ 0x1f, 0x000f },
+		{ 0x10, 0x20d0 },
+		{ 0x1f, 0x000b },
+	};
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
+		ret = phy_write(phydev,
+				bcm7xxx_suspend_cfg[i].reg,
+				bcm7xxx_suspend_cfg[i].value);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
+{
+	return 0;
+}
+
+static int bcm7xxx_28nm_probe(struct phy_device *phydev)
+{
+	struct bcm7xxx_phy_priv *priv;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	phydev->priv = priv;
+
+	priv->clk = clk_get(&phydev->dev, "sw_gphy");
+	if (IS_ERR(priv->clk)) {
+		dev_err(&phydev->dev, "failed to request GPHY clock\n");
+		priv->clk = NULL;
+	}
+
+	clk_prepare_enable(priv->clk);
+
+	return 0;
+}
+
+static void bcm7xxx_28nm_remove(struct phy_device *phydev)
+{
+	struct bcm7xxx_phy_priv *priv = phydev->priv;
+
+	clk_disable_unprepare(priv->clk);
+	clk_put(priv->clk);
+	kfree(priv);
+	phydev->priv = NULL;
+}
+
+#define BCM7XXX_28NM_GPHY(_oui, _name)					\
+{									\
+	.phy_id		= (_oui),					\
+	.phy_id_mask	= 0xfffffff0,					\
+	.name		= _name,					\
+	.features	= PHY_GBIT_FEATURES |				\
+			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\
+	.flags		= PHY_IS_INTERNAL,				\
+	.probe		= bcm7xxx_28nm_probe,				\
+	.remove		= bcm7xxx_28nm_remove,				\
+	.config_init	= bcm7xxx_28nm_config_init,			\
+	.config_aneg	= genphy_config_aneg,				\
+	.read_status	= genphy_read_status,				\
+	.resume		= bcm7xxx_28nm_resume,				\
+	.driver		= { .owner = THIS_MODULE },			\
+}
+
+static struct phy_driver bcm7xxx_driver[] = {
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
+	BCM7XXX_28NM_GPHY(PHY_ID_BCM7455, "Broadcom BCM7455"),
+};
+
+static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
+	{ PHY_ID_BCM7250, 0xfffffff0, },
+	{ PHY_ID_BCM7364, 0xfffffff0, },
+	{ PHY_ID_BCM7366, 0xfffffff0, },
+	{ PHY_ID_BCM74371, 0xfffffff0, },
+	{ PHY_ID_BCM7439, 0xfffffff0, },
+	{ PHY_ID_BCM7445, 0xfffffff0, },
+	{ PHY_ID_BCM7455, 0xfffffff0, },
+	{ }
+};
+
+static int __init bcm7xxx_phy_init(void)
+{
+	return phy_drivers_register(bcm7xxx_driver,
+			ARRAY_SIZE(bcm7xxx_driver));
+}
+
+static void __exit bcm7xxx_phy_exit(void)
+{
+	phy_drivers_unregister(bcm7xxx_driver,
+			ARRAY_SIZE(bcm7xxx_driver));
+}
+
+module_init(bcm7xxx_phy_init);
+module_exit(bcm7xxx_phy_exit);
+
+MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
+
+MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 7a1ff5797f12..b15e6a26c4ab 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -25,183 +25,10 @@
 #define BRCM_PHY_REV(phydev) \
 	((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
 
-
-#define MII_BCM54XX_ECR		0x10	/* BCM54xx extended control register */
-#define MII_BCM54XX_ECR_IM	0x1000	/* Interrupt mask */
-#define MII_BCM54XX_ECR_IF	0x0800	/* Interrupt force */
-
-#define MII_BCM54XX_ESR		0x11	/* BCM54xx extended status register */
-#define MII_BCM54XX_ESR_IS	0x1000	/* Interrupt status */
-
-#define MII_BCM54XX_EXP_DATA	0x15	/* Expansion register data */
-#define MII_BCM54XX_EXP_SEL	0x17	/* Expansion register select */
-#define MII_BCM54XX_EXP_SEL_SSD	0x0e00	/* Secondary SerDes select */
-#define MII_BCM54XX_EXP_SEL_ER	0x0f00	/* Expansion register select */
-
-#define MII_BCM54XX_AUX_CTL	0x18	/* Auxiliary control register */
-#define MII_BCM54XX_ISR		0x1a	/* BCM54xx interrupt status register */
-#define MII_BCM54XX_IMR		0x1b	/* BCM54xx interrupt mask register */
-#define MII_BCM54XX_INT_CRCERR	0x0001	/* CRC error */
-#define MII_BCM54XX_INT_LINK	0x0002	/* Link status changed */
-#define MII_BCM54XX_INT_SPEED	0x0004	/* Link speed change */
-#define MII_BCM54XX_INT_DUPLEX	0x0008	/* Duplex mode changed */
-#define MII_BCM54XX_INT_LRS	0x0010	/* Local receiver status changed */
-#define MII_BCM54XX_INT_RRS	0x0020	/* Remote receiver status changed */
-#define MII_BCM54XX_INT_SSERR	0x0040	/* Scrambler synchronization error */
-#define MII_BCM54XX_INT_UHCD	0x0080	/* Unsupported HCD negotiated */
-#define MII_BCM54XX_INT_NHCD	0x0100	/* No HCD */
-#define MII_BCM54XX_INT_NHCDL	0x0200	/* No HCD link */
-#define MII_BCM54XX_INT_ANPR	0x0400	/* Auto-negotiation page received */
-#define MII_BCM54XX_INT_LC	0x0800	/* All counters below 128 */
-#define MII_BCM54XX_INT_HC	0x1000	/* Counter above 32768 */
-#define MII_BCM54XX_INT_MDIX	0x2000	/* MDIX status change */
-#define MII_BCM54XX_INT_PSERR	0x4000	/* Pair swap error */
-
-#define MII_BCM54XX_SHD		0x1c	/* 0x1c shadow registers */
-#define MII_BCM54XX_SHD_WRITE	0x8000
-#define MII_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
-#define MII_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)
-
-/*
- * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
- */
-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000
-#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB		0x0400
-#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800
-
-#define MII_BCM54XX_AUXCTL_MISC_WREN	0x8000
-#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200
-#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000
-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007
-
-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000
-
-
-/*
- * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
- * BCM5482, and possibly some others.
- */
-#define BCM_LED_SRC_LINKSPD1	0x0
-#define BCM_LED_SRC_LINKSPD2	0x1
-#define BCM_LED_SRC_XMITLED	0x2
-#define BCM_LED_SRC_ACTIVITYLED	0x3
-#define BCM_LED_SRC_FDXLED	0x4
-#define BCM_LED_SRC_SLAVE	0x5
-#define BCM_LED_SRC_INTR	0x6
-#define BCM_LED_SRC_QUALITY	0x7
-#define BCM_LED_SRC_RCVLED	0x8
-#define BCM_LED_SRC_MULTICOLOR1	0xa
-#define BCM_LED_SRC_OPENSHORT	0xb
-#define BCM_LED_SRC_OFF		0xe	/* Tied high */
-#define BCM_LED_SRC_ON		0xf	/* Tied low */
-
-
-/*
- * BCM5482: Shadow registers
- * Shadow values go into bits [14:10] of register 0x1c to select a shadow
- * register to access.
- */
-/* 00101: Spare Control Register 3 */
-#define BCM54XX_SHD_SCR3		0x05
-#define  BCM54XX_SHD_SCR3_DEF_CLK125	0x0001
-#define  BCM54XX_SHD_SCR3_DLLAPD_DIS	0x0002
-#define  BCM54XX_SHD_SCR3_TRDDAPD	0x0004
-
-/* 01010: Auto Power-Down */
-#define BCM54XX_SHD_APD			0x0a
-#define  BCM54XX_SHD_APD_EN		0x0020
-
-#define BCM5482_SHD_LEDS1	0x0d	/* 01101: LED Selector 1 */
-					/* LED3 / ~LINKSPD[2] selector */
-#define BCM5482_SHD_LEDS1_LED3(src)	((src & 0xf) << 4)
-					/* LED1 / ~LINKSPD[1] selector */
-#define BCM5482_SHD_LEDS1_LED1(src)	((src & 0xf) << 0)
-#define BCM54XX_SHD_RGMII_MODE	0x0b	/* 01011: RGMII Mode Selector */
-#define BCM5482_SHD_SSD		0x14	/* 10100: Secondary SerDes control */
-#define BCM5482_SHD_SSD_LEDM	0x0008	/* SSD LED Mode enable */
-#define BCM5482_SHD_SSD_EN	0x0001	/* SSD enable */
-#define BCM5482_SHD_MODE	0x1f	/* 11111: Mode Control Register */
-#define BCM5482_SHD_MODE_1000BX	0x0001	/* Enable 1000BASE-X registers */
-
-
-/*
- * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
- */
-#define MII_BCM54XX_EXP_AADJ1CH0		0x001f
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN	0x0200
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF	0x0100
-#define MII_BCM54XX_EXP_AADJ1CH3		0x601f
-#define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ	0x0002
-#define MII_BCM54XX_EXP_EXP08			0x0F08
-#define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ	0x0001
-#define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE	0x0200
-#define MII_BCM54XX_EXP_EXP75			0x0f75
-#define  MII_BCM54XX_EXP_EXP75_VDACCTRL		0x003c
-#define  MII_BCM54XX_EXP_EXP75_CM_OSC		0x0001
-#define MII_BCM54XX_EXP_EXP96			0x0f96
-#define  MII_BCM54XX_EXP_EXP96_MYST		0x0010
-#define MII_BCM54XX_EXP_EXP97			0x0f97
-#define  MII_BCM54XX_EXP_EXP97_MYST		0x0c0c
-
-/*
- * BCM5482: Secondary SerDes registers
- */
-#define BCM5482_SSD_1000BX_CTL		0x00	/* 1000BASE-X Control */
-#define BCM5482_SSD_1000BX_CTL_PWRDOWN	0x0800	/* Power-down SSD */
-#define BCM5482_SSD_SGMII_SLAVE		0x15	/* SGMII Slave Register */
-#define BCM5482_SSD_SGMII_SLAVE_EN	0x0002	/* Slave mode enable */
-#define BCM5482_SSD_SGMII_SLAVE_AD	0x0001	/* Slave auto-detection */
-
-
-/*****************************************************************************/
-/* Fast Ethernet Transceiver definitions. */
-/*****************************************************************************/
-
-#define MII_BRCM_FET_INTREG		0x1a	/* Interrupt register */
-#define MII_BRCM_FET_IR_MASK		0x0100	/* Mask all interrupts */
-#define MII_BRCM_FET_IR_LINK_EN		0x0200	/* Link status change enable */
-#define MII_BRCM_FET_IR_SPEED_EN	0x0400	/* Link speed change enable */
-#define MII_BRCM_FET_IR_DUPLEX_EN	0x0800	/* Duplex mode change enable */
-#define MII_BRCM_FET_IR_ENABLE		0x4000	/* Interrupt enable */
-
-#define MII_BRCM_FET_BRCMTEST		0x1f	/* Brcm test register */
-#define MII_BRCM_FET_BT_SRE		0x0080	/* Shadow register enable */
-
-
-/*** Shadow register definitions ***/
-
-#define MII_BRCM_FET_SHDW_MISCCTRL	0x10	/* Shadow misc ctrl */
-#define MII_BRCM_FET_SHDW_MC_FAME	0x4000	/* Force Auto MDIX enable */
-
-#define MII_BRCM_FET_SHDW_AUXMODE4	0x1a	/* Auxiliary mode 4 */
-#define MII_BRCM_FET_SHDW_AM4_LED_MASK	0x0003
-#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
-
-#define MII_BRCM_FET_SHDW_AUXSTAT2	0x1b	/* Auxiliary status 2 */
-#define MII_BRCM_FET_SHDW_AS2_APDE	0x0020	/* Auto power down enable */
-
-
 MODULE_DESCRIPTION("Broadcom PHY driver");
 MODULE_AUTHOR("Maciej W. Rozycki");
 MODULE_LICENSE("GPL");
 
-/*
- * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
- * 0x1c shadow registers.
- */
-static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
-{
-	phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
-	return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
-}
-
-static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
-{
-	return phy_write(phydev, MII_BCM54XX_SHD,
-			 MII_BCM54XX_SHD_WRITE |
-			 MII_BCM54XX_SHD_VAL(shadow) |
-			 MII_BCM54XX_SHD_DATA(val));
-}
 
 /* Indirect register access functions for the Expansion Registers */
 static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
diff --git a/drivers/net/phy/ethsw.c b/drivers/net/phy/ethsw.c
new file mode 100644
index 000000000000..b63e39c4e889
--- /dev/null
+++ b/drivers/net/phy/ethsw.c
@@ -0,0 +1,798 @@
+/*
+ * Copyright (c) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/netdevice.h>
+#include <linux/proc_fs.h>
+#include <linux/ctype.h>
+#include <linux/stddef.h>
+#include <linux/phy.h>
+#include <linux/brcmphy.h>
+#include <linux/module.h>
+
+#define BCM53125_PHY_ID		0x03625f20
+#define BCM53101_PHY_ID		0x03625ed0
+
+static unsigned char swdata[16];
+static struct proc_dir_entry *p;
+
+#define REG_PSEUDO_PHY_MII_REG16                          0x10
+    #define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT        8
+    #define REG_PPM_REG16_MDIO_ENABLE                     0x01
+#define REG_PSEUDO_PHY_MII_REG17                          0x11
+
+    #define REG_PPM_REG17_REG_NUMBER_SHIFT                8
+    #define REG_PPM_REG17_OP_DONE                         0x00
+    #define REG_PPM_REG17_OP_WRITE                        0x01
+    #define REG_PPM_REG17_OP_READ                         0x02
+
+#define REG_PSEUDO_PHY_MII_REG24                          0x18
+#define REG_PSEUDO_PHY_MII_REG25                          0x19
+#define REG_PSEUDO_PHY_MII_REG26                          0x1a
+#define REG_PSEUDO_PHY_MII_REG27                          0x1b
+
+#define PAGE_CONTROL                                      0x00
+    #define REG_PORT_CTRL                                 0x00
+    #define REG_IMP_PORT_CONTROL                          0x08
+
+        #define REG_IMP_PORT_CONTROL_RX_UCST_EN           0x10
+        #define REG_IMP_PORT_CONTROL_RX_MCST_EN           0x08
+        #define REG_IMP_PORT_CONTROL_RX_BCST_EN           0x04
+    #define REG_SWITCH_MODE                               0x0b
+
+        #define REG_SWITCH_MODE_FRAME_MANAGE_MODE         0x01
+        #define REG_SWITCH_MODE_SW_FWDG_EN                0x02
+    #define REG_CONTROL_IMP_PORT_STATE_OVERRIDE           0x0e
+
+        #define REG_CONTROL_MPSO_MII_SW_OVERRIDE          0x80
+        #define REG_CONTROL_MPSO_TX_FLOW_CONTROL          0x20
+        #define REG_CONTROL_MPSO_RX_FLOW_CONTROL          0x10
+        #define REG_CONTROL_MPSO_SPEED1000                0x08
+        #define REG_CONTROL_MPSO_SPEED100                 0x04
+        #define REG_CONTROL_MPSO_FDX                      0x02
+        #define REG_CONTROL_MPSO_LINKPASS                 0x01
+
+    #define REG_SWITCH_CTRL				  0x20
+	#define REG_MII_DUMB_FWD_EN			  0x01 /* 53101 only */
+
+    #define REG_PORT_FORWARD                              0x21 /* 5397 only */
+
+        #define REG_PORT_FORWARD_MCST                     0x80
+        #define REG_PORT_FORWARD_UCST                     0x40
+        #define REG_PORT_FORWARD_IPMC                     0x01
+
+    #define REG_UCST_LOOKUP_FAIL                          0x32
+
+    #define REG_RGMII_CTRL_IMP                            0x60
+
+    #define REG_RGMII_CTRL_P5                             0x65
+
+        #define REG_RGMII_CTRL_ENABLE_GMII                0x80
+        #define REG_RGMII_CTRL_TIMING_SEL                 0x04
+        #define REG_RGMII_CTRL_DLL_RXC                    0x02
+        #define REG_RGMII_CTRL_DLL_TXC                    0x01
+
+#define SWITCH_PORT_MAP_IMP                               0x0100
+
+#define PAGE_MANAGEMENT                                   0x02
+
+    #define REG_GLOBAL_CONFIG                             0x00
+#define PAGE_PORT_BASED_VLAN                              0x31
+
+    #define REG_VLAN_CTRL_P0                              0x00
+    #define REG_VLAN_CTRL_P1                              0x02
+    #define REG_VLAN_CTRL_P2                              0x04
+    #define REG_VLAN_CTRL_P3                              0x06
+    #define REG_VLAN_CTRL_P4                              0x08
+    #define REG_VLAN_CTRL_P5                              0x0a
+    #define REG_VLAN_CTRL_P6                              0x0c
+    #define REG_VLAN_CTRL_P7                              0x0e
+    #define REG_VLAN_CTRL_P8                              0x10
+
+#define BE64(x) \
+({ \
+	uint64_t __x = (x); \
+	((uint64_t)( \
+		(((uint64_t)(__x) & (uint64_t)0x00000000000000ffUL) << 56) | \
+		(((uint64_t)(__x) & (uint64_t)0x000000000000ff00UL) << 40) | \
+		(((uint64_t)(__x) & (uint64_t)0x0000000000ff0000UL) << 24) | \
+		(((uint64_t)(__x) & (uint64_t)0x00000000ff000000UL) << 8) | \
+		(((uint64_t)(__x) & (uint64_t)0x000000ff00000000UL) >> 8) | \
+		(((uint64_t)(__x) & (uint64_t)0x0000ff0000000000UL) >> 24) | \
+		(((uint64_t)(__x) & (uint64_t)0x00ff000000000000UL) >> 40) | \
+		(((uint64_t)(__x) & (uint64_t)0xff00000000000000UL) >> 56) )); \
+})
+#define BE32(x) \
+({ \
+	uint32_t __x = (x); \
+	((uint32_t)( \
+		(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
+		(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \
+		(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \
+		(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )); \
+})
+#define BE16(x) \
+({ \
+	uint16_t __x = (x); \
+	((uint16_t)( \
+		(((uint16_t)(__x) & (uint16_t)0x00ffUL) << 8) | \
+		(((uint16_t)(__x) & (uint16_t)0xff00UL) >>  8) )); \
+})
+
+static void ethsw_mdio_rreg(struct phy_device *phydev, int page, int reg,
+				unsigned char *data, int len)
+{
+	int phy_id;
+	int v, vm[4];
+	int i;
+
+	phy_id = BRCM_PSEUDO_PHY_ADDR;
+	v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+
+	v = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_READ;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG17, v);
+
+	for (i = 0; i < 5; i++)
+	{
+		v = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG17);
+
+		if ((v & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+			break;
+
+		udelay(10);
+	}
+
+	if (i == 5)
+	{
+		printk("ethsw_mdio_rreg: timeout!\n");
+		return;
+	}
+
+	switch (len)
+	{
+		case 1:
+			v = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			data[0] = (unsigned char)v;
+			break;
+		case 2:
+			v = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)v;
+			break;
+		case 4:
+			vm[0] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			vm[1] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			((unsigned short *)data)[0] = (unsigned short)vm[0];
+			((unsigned short *)data)[1] = (unsigned short)vm[1];
+			break;
+		case 6:
+			vm[0] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG26);
+			vm[1] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			vm[2] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)vm[2];
+			((unsigned short *)data)[1] = (unsigned short)vm[1];
+			((unsigned short *)data)[2] = (unsigned short)vm[0];
+			break;
+		case 8:
+			vm[0] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG27);
+			vm[1] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG26);
+			vm[2] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25);
+			vm[3] = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24);
+			((unsigned short *)data)[0] = (unsigned short)vm[3];
+			((unsigned short *)data)[1] = (unsigned short)vm[2];
+			((unsigned short *)data)[2] = (unsigned short)vm[1];
+			((unsigned short *)data)[3] = (unsigned short)vm[0];
+			break;
+	}
+	v = page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+}
+
+static void ethsw_mdio_wreg(struct phy_device *phydev, int page, int reg,
+				unsigned char *data, int len)
+{
+	int phy_id;
+	int v;
+	int i;
+
+	phy_id = BRCM_PSEUDO_PHY_ADDR;
+	v = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+
+	switch (len)
+	{
+		case 1:
+			v = data[0];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			break;
+		case 2:
+			v = ((unsigned short *)data)[0];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			break;
+		case 4:
+			v = ((unsigned short *)data)[0];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			break;
+		case 6:
+			v = ((unsigned short *)data)[0];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			v = ((unsigned short *)data)[2];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG26, v);
+			break;
+		case 8:
+			v = ((unsigned short *)data)[0];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG24, v);
+			v = ((unsigned short *)data)[1];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG25, v);
+			v = ((unsigned short *)data)[2];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG26, v);
+			v = ((unsigned short *)data)[3];
+			mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG27, v);
+			break;
+	}
+
+	v = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_WRITE;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG17, v);
+
+	for (i = 0; i < 5; i++)
+	{
+		v = mdiobus_read(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG17);
+
+		if ((v & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+			break;
+
+		udelay(10);
+	}
+
+	if (i == 5)
+		printk("ethsw_mdio_wreg: timeout!\n");
+
+	v = page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT;
+	mdiobus_write(phydev->bus, phy_id, REG_PSEUDO_PHY_MII_REG16, v);
+}
+
+static void ethsw_rreg(struct phy_device *phydev, int page, int reg,
+			unsigned char *data, int len)
+{
+	if (((len != 1) && (len % 2) != 0) || len > 8)
+		panic("ethsw_rreg: wrong length!\n");
+
+	ethsw_mdio_rreg(phydev, page, reg, data, len);
+}
+
+static void ethsw_wreg(struct phy_device *phydev, int page, int reg,
+			unsigned char *data, int len)
+{
+	if (((len != 1) && (len % 2) != 0) || len > 8)
+		panic("ethsw_wreg: wrong length!\n");
+
+	ethsw_mdio_wreg(phydev, page, reg, data, len);
+}
+
+static int ethsw_config_learning(struct phy_device *phydev)
+{
+	unsigned char v8;
+	unsigned short v16;
+
+	// Forward lookup failure to CPU
+	v8 = (REG_PORT_FORWARD_MCST | REG_PORT_FORWARD_UCST | REG_PORT_FORWARD_IPMC);
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_PORT_FORWARD, (unsigned char *)&v8, sizeof(v8));
+	// Forward unlearned unicast frames to the MIPS
+	v16 = SWITCH_PORT_MAP_IMP;
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_UCST_LOOKUP_FAIL, (unsigned char *)&v16, sizeof(v16));
+
+	return 0;
+}
+
+static void ethsw_switch_unmanage_mode(struct phy_device *phydev)
+{
+	unsigned char v8;
+	unsigned short v16;
+
+	ethsw_rreg(phydev, PAGE_CONTROL, REG_SWITCH_MODE, &v8, sizeof(v8));
+	v8 &= ~REG_SWITCH_MODE_FRAME_MANAGE_MODE;
+	v8 |= REG_SWITCH_MODE_SW_FWDG_EN;
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_SWITCH_MODE, &v8, sizeof(v8));
+
+	/* BCM53101 requires this MII_DUMB_FWD_EN to be set to forward frames
+	 * towards the host CPU
+	 */
+	if ((phydev->drv->phy_id & phydev->drv->phy_id_mask) == BCM53101_PHY_ID) {
+		v8 = REG_MII_DUMB_FWD_EN;
+		ethsw_wreg(phydev, PAGE_CONTROL, REG_SWITCH_CTRL, &v8, sizeof(v8));
+	}
+
+	v8 = 0;
+	ethsw_wreg(phydev, PAGE_MANAGEMENT, REG_GLOBAL_CONFIG, &v8, sizeof(v8));
+
+	/* Delete port-based VLAN */
+	v16 = 0x01ff;
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P0, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P1, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P2, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P3, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P4, (unsigned char *)&v16, sizeof(v16));
+	ethsw_wreg(phydev, PAGE_PORT_BASED_VLAN, REG_VLAN_CTRL_P8, (unsigned char *)&v16, sizeof(v16));
+}
+
+static int ethsw_force_speed(struct phy_device *phydev)
+{
+	unsigned char v8;
+
+	v8 = 0;
+	v8 |= (REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS);
+	if (phydev->advertising & (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half))
+		v8 |= REG_CONTROL_MPSO_SPEED1000;
+	else if (phydev->advertising & (SUPPORTED_100baseT_Full | SUPPORTED_100baseT_Half))
+		v8 |= REG_CONTROL_MPSO_SPEED100;
+	else
+		v8 &= ~(REG_CONTROL_MPSO_SPEED1000 | REG_CONTROL_MPSO_SPEED100);
+	v8 |= (REG_CONTROL_MPSO_RX_FLOW_CONTROL|REG_CONTROL_MPSO_FDX);
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_CONTROL_IMP_PORT_STATE_OVERRIDE, &v8, sizeof(v8));
+
+	/* checking Switch functional */
+	v8 = 0;
+	ethsw_rreg(phydev, PAGE_CONTROL, REG_CONTROL_IMP_PORT_STATE_OVERRIDE, &v8, sizeof(v8));
+	if ((v8 & (REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS)) !=
+		(REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_LINKPASS) ||
+		(v8 == 0xff)) {
+		printk(KERN_ERR "error on Ethernet Switch setup 0x%x\n", v8);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int ethsw_reset_ports(struct phy_device *phydev)
+{
+	unsigned long flags;
+	int i;
+	unsigned char v8;
+
+	local_irq_save(flags);
+
+	/* MAC level reset */
+	v8 = 0; /* No spanning tree and tx/rx enable */
+	for (i = 0; i < 5; i++)
+	{
+		ethsw_wreg(phydev, PAGE_CONTROL, REG_PORT_CTRL + i, &v8, 1);
+	}
+
+	/* Config IMP port RGMII clock delay by DLL disabled and tx_clk aligned
+	 * timing (restoring to reset defaults)
+	 */
+	ethsw_rreg(phydev, PAGE_CONTROL, REG_RGMII_CTRL_IMP, &v8, sizeof(v8));
+	v8 &= ~(REG_RGMII_CTRL_DLL_RXC | REG_RGMII_CTRL_DLL_TXC);
+	v8 &= ~REG_RGMII_CTRL_TIMING_SEL;
+
+	/* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make sure
+	 * that we enable the IMP Port TX clock internal delay to account for
+	 * this internal delay that is inserted, otherwise the switch won't be
+	 * able to receive correctly.
+	 *
+	 * PHY_INTERFACE_MODE_RGMII means that we are not introducing any delay
+	 * neither on transmission nor reception, so the BCM53125 must also be
+	 * configured accordingly to account for the lack of delay and
+	 * introduce
+	 *
+	 * The BCM53125 switch has its RX clock and TX clock control swapped,
+	 * hence the reason why we modify the TX clock path in the "RGMII" case
+	 */
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+		v8 |= REG_RGMII_CTRL_DLL_TXC;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
+		v8 |= REG_RGMII_CTRL_DLL_TXC | REG_RGMII_CTRL_DLL_RXC;
+	v8 |= REG_RGMII_CTRL_TIMING_SEL;
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_RGMII_CTRL_IMP, &v8, sizeof(v8));
+
+	/* Set IMP port RMII mode */
+	v8 = 0;
+	v8 |= REG_IMP_PORT_CONTROL_RX_UCST_EN;
+	v8 |= REG_IMP_PORT_CONTROL_RX_MCST_EN;
+	v8 |= REG_IMP_PORT_CONTROL_RX_BCST_EN;
+	ethsw_wreg(phydev, PAGE_CONTROL, REG_IMP_PORT_CONTROL, &v8, 1);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+
+static void ethsw_print_reg(struct phy_device *phydev, int reg_page, int reg_addr, int reg_len, char *reg_name)
+{
+	unsigned char swdata[8];
+	unsigned int val;
+	int i;
+
+	ethsw_rreg(phydev, reg_page, reg_addr, swdata, reg_len);
+	printk("%s [%02x:%02x] = ", reg_name, reg_page, reg_addr);
+	switch(reg_len) {
+		case 2:
+			*(uint16_t *)&swdata[0] = BE16(*(uint16_t *)&swdata[0]);
+			break;
+		case 4:
+			*(uint32_t *)&swdata[0] = BE32(*(uint32_t *)&swdata[0]);
+			break;
+		case 8:
+			val = BE32(*(uint32_t *)&swdata[0]);
+			*(uint32_t *)&swdata[0] = BE32(*(uint32_t *)&swdata[4]);
+			*(uint32_t *)&swdata[4] = val;
+			break;
+	}
+	for (i = 0; i < reg_len; i ++)
+		printk("%02x ", swdata[i]);
+	printk("\n");
+}
+
+static int ethsw_dump_mib(struct phy_device *phydev, int port)
+{
+	int reg_page;
+
+	if (port > 8) {
+		printk("Invalid port number \n");
+		return -1;
+	}
+
+	printk("\n");
+	printk("dump port %d MIB counter\n", port);
+	reg_page = 0x20 + port;
+	/* Display Tx statistics */
+	ethsw_print_reg(phydev, reg_page, 0, 8, "TxOctets");
+	ethsw_print_reg(phydev, reg_page, 8, 4, "TxDropPkts");
+	ethsw_print_reg(phydev, reg_page, 0x10, 4, "TxBroadcastPkts");
+	ethsw_print_reg(phydev, reg_page, 0x14, 4, "TxMulticastPkts");
+	ethsw_print_reg(phydev, reg_page, 0x18, 4, "TxUnicastPkts");
+	ethsw_print_reg(phydev, reg_page, 0x1c, 4, "TxCollisions");
+	ethsw_print_reg(phydev, reg_page, 0x58, 4, "RxUndersizePkts");
+	ethsw_print_reg(phydev, reg_page, 0x60, 4, "Pkt64Octets");
+	ethsw_print_reg(phydev, reg_page, 0x64, 4, "Pkt65to127Octets");
+	ethsw_print_reg(phydev, reg_page, 0x68, 4, "Pkt128to255Octets");
+	ethsw_print_reg(phydev, reg_page, 0x6C, 4, "Pkt256to511Octets");
+	ethsw_print_reg(phydev, reg_page, 0x70, 4, "Pkt512to1023Octets");
+	ethsw_print_reg(phydev, reg_page, 0x74, 4, "Pkts1024toMaxPktOctets");
+	ethsw_print_reg(phydev, reg_page, 0x78, 4, "RxOversizePkts");
+	ethsw_print_reg(phydev, reg_page, 0x80, 4, "RxAlignmentErros");
+	ethsw_print_reg(phydev, reg_page, 0x84, 4, "RXFCSErrors");
+	ethsw_print_reg(phydev, reg_page, 0x88, 4, "RxGoodOctets");
+	ethsw_print_reg(phydev, reg_page, 0x90, 4, "RxDropPkts");
+	ethsw_print_reg(phydev, reg_page, 0x94, 4, "RxUnicastPkts");
+	ethsw_print_reg(phydev, reg_page, 0x98, 4, "RxMulticastPkts");
+	ethsw_print_reg(phydev, reg_page, 0x9C, 4, "RxBroadcastPkts");
+	ethsw_print_reg(phydev, reg_page, 0xA8, 4, "JumboPkt");
+	ethsw_print_reg(phydev, reg_page, 0xAC, 4, "RXSymbolError");
+	ethsw_print_reg(phydev, reg_page, 0xB4, 4, "OutofRangeError");
+
+	return 0;
+}
+
+static void str_to_num(char* in, char* out, int len)
+{
+	int i;
+	memset(out, 0, len);
+
+	for (i = 0; i < len * 2; i ++)
+	{
+		if ((*in >= '0') && (*in <= '9'))
+			*out += (*in - '0');
+		else if ((*in >= 'a') && (*in <= 'f'))
+			*out += (*in - 'a') + 10;
+		else if ((*in >= 'A') && (*in <= 'F'))
+			*out += (*in - 'A') + 10;
+		else
+			*out += 0;
+
+		if ((i % 2) == 0)
+			*out *= 16;
+		else
+			out ++;
+
+		in ++;
+	}
+	return;
+}
+
+static int proc_get_sw_param(struct seq_file *m, void *v)
+{
+	struct phy_device *phydev = m->private;
+	int reg_page  = swdata[0];
+	int reg_addr  = swdata[1];
+	int reg_len   = swdata[2];
+	int i = 0;
+	int r = 0;
+	unsigned int val;
+
+	if (reg_len == 0)
+		return 0;
+
+	if (!v)
+		return 0;
+
+#if 0
+	if (reg_page == 0xfe) {
+		if (reg_len == 6)
+			show_arl((struct phy_device *)data, swdata[1], swdata + 3);
+		else
+			show_arl((struct phy_device *)data, swdata[1], NULL);
+		return 0;
+	}
+#endif
+	if (reg_page == 0xff) {
+		for (i = 0; i < 8; i++) {
+			if ((0x01 << i) & reg_addr)
+				ethsw_dump_mib(phydev, i);
+		}
+		ethsw_dump_mib(phydev, 8);
+		return 0;
+	}
+	ethsw_rreg(phydev, reg_page, reg_addr, swdata + 3, reg_len);
+
+	seq_printf(m, "[%02x:%02x] = ", swdata[0], swdata[1]);
+	switch(reg_len) {
+		case 2:
+			*(uint16_t *)&swdata[3] = BE16(*(uint16_t *)&swdata[3]);
+			break;
+		case 4:
+			*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[3]);
+			break;
+		case 6:
+			val = BE32(*(uint32_t *)&swdata[5]);
+			*(uint16_t *)&swdata[7] = BE16(*(uint32_t *)&swdata[3]);
+			*(uint32_t *)&swdata[3] = val;
+			break;
+		case 8:
+			val = BE32(*(uint32_t *)&swdata[3]);
+			*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[7]);
+			*(uint32_t *)&swdata[7] = val;
+			break;
+	}
+
+	for (i = 0; i < reg_len; i ++)
+		r += seq_printf(m, "%02x ", swdata[3 + i]);
+
+	seq_printf(m, "\n");
+
+	return 0;
+}
+
+static int proc_set_sw_param(struct file *f, const char *buf, size_t cnt, loff_t *data)
+{
+	struct phy_device *phydev = PDE_DATA(file_inode(f));
+	char input[32];
+	int i;
+	int r;
+	int num_of_octets;
+
+	int reg_page;
+	int reg_addr;
+	int reg_len;
+	unsigned int val;
+
+	if (cnt > 32)
+		cnt = 32;
+
+	if (copy_from_user(input, buf, cnt) != 0)
+		return -EFAULT;
+
+	r = cnt;
+
+	for (i = 0; i < r; i ++)
+	{
+		if (!isxdigit(input[i]))
+		{
+			memmove(&input[i], &input[i + 1], r - i - 1);
+			r --;
+			i --;
+		}
+	}
+
+	num_of_octets = r / 2;
+
+	if (num_of_octets < 3) // page, addr, len
+		return -EFAULT;
+
+	str_to_num(input, swdata, num_of_octets);
+
+	reg_page  = swdata[0];
+	reg_addr  = swdata[1];
+	reg_len   = swdata[2];
+
+	if (((reg_len != 1) && (reg_len % 2) != 0) || reg_len > 8)
+	{
+		memset(swdata, 0, sizeof(swdata));
+		return -EFAULT;
+	}
+
+	if ((num_of_octets > 3) && (num_of_octets != reg_len + 3))
+	{
+		memset(swdata, 0, sizeof(swdata));
+		return -EFAULT;
+	}
+
+	if ((num_of_octets > 3) && (reg_page < 0xfe)) {
+		switch(reg_len) {
+			case 2:
+				*(uint16_t *)&swdata[3] = BE16(*(uint16_t *)&swdata[3]);
+				break;
+			case 4:
+				*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[3]);
+				break;
+			case 6:
+				val = BE32(*(uint32_t *)&swdata[5]);
+				*(uint16_t *)&swdata[7] = BE16(*(uint32_t *)&swdata[3]);
+				*(uint32_t *)&swdata[3] = val;
+				break;
+			case 8:
+				val = BE32(*(uint32_t *)&swdata[3]);
+				*(uint32_t *)&swdata[3] = BE32(*(uint32_t *)&swdata[7]);
+				*(uint32_t *)&swdata[7] = val;
+				break;
+		}
+		ethsw_wreg(phydev, reg_page, reg_addr, swdata + 3, reg_len);
+	}
+	return cnt;
+}
+
+static int ethsw_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, proc_get_sw_param, PDE_DATA(inode));
+}
+
+static struct file_operations ethsw_fops = {
+	.open	= ethsw_open,
+	.read	= seq_read,
+	.write	= proc_set_sw_param,
+	.llseek	= seq_lseek,
+	.release = seq_release,
+};
+
+static int ethsw_add_proc_files(struct phy_device *phydev)
+{
+	p = proc_create_data("switch", 0644, NULL, &ethsw_fops, phydev);
+	if (p == NULL) {
+		pr_err("%s: unable to create proc entry\n", __func__);
+		return -1;
+	}
+
+	memset(swdata, 0, sizeof(swdata));
+
+	return 0;
+}
+
+static int bcm53x25_ethsw_init(struct phy_device *phydev)
+{
+	ethsw_reset_ports(phydev);
+	ethsw_switch_unmanage_mode(phydev);
+	ethsw_config_learning(phydev);
+
+	return 0;
+}
+
+static int bcm53x25_ethsw_resume(struct phy_device *phydev)
+{
+	bcm53x25_ethsw_init(phydev);
+	return ethsw_force_speed(phydev);
+}
+
+static int bcm53x25_config_aneg(struct phy_device *phydev)
+{
+	return ethsw_force_speed(phydev);
+}
+
+static int bcm53x25_read_status(struct phy_device *phydev)
+{
+	phydev->duplex = DUPLEX_FULL;
+
+	if (phydev->advertising & (SUPPORTED_1000baseT_Half |
+				SUPPORTED_1000baseT_Full))
+		phydev->speed = SPEED_1000;
+	else if (phydev->advertising & (SUPPORTED_100baseT_Half |
+				SUPPORTED_100baseT_Full))
+		phydev->speed = SPEED_100;
+	else
+		phydev->speed = SPEED_10;
+
+	phydev->link = 1;
+	phydev->state = PHY_RUNNING;
+
+	netif_carrier_on(phydev->attached_dev);
+	phydev->adjust_link(phydev->attached_dev);
+
+	return 0;
+}
+
+static int bcm53x25_probe(struct phy_device *phydev)
+{
+	/* Make sure that we match either the pseudo-PHY addreess or
+	 * address 0 as this is the default PHY addressing supported
+	 * for BCM53xxx switches
+	 */
+	if (phydev->addr != BRCM_PSEUDO_PHY_ADDR && phydev->addr != 0) {
+		dev_err(&phydev->dev, "invalid PHY address %d\n",
+			phydev->addr);
+		return -ENODEV;
+	}
+
+	if (p) {
+		remove_proc_entry("switch", NULL);
+		p = NULL;
+	}
+	ethsw_add_proc_files(phydev);
+
+	/* Tell the MDIO bus controller that this switch's pseudo-PHY has a
+	 * broken turn-around and it should ignore read failures. See ING JIRA
+	 * SF-357.
+	 */
+	phydev->bus->phy_ignore_ta_mask |= 1 << BRCM_PSEUDO_PHY_ADDR;
+
+	return 0;
+}
+
+static void bcm53x25_remove(struct phy_device *phydev)
+{
+	remove_proc_entry("switch", NULL);
+}
+
+static struct phy_driver bcm53x25_driver[] = {
+	{
+		/* Match all BCM53125 revisions */
+		.phy_id		= BCM53125_PHY_ID,
+		.phy_id_mask 	= 0x1ffffff0,
+		.name		= "Broadcom BCM53125",
+		.features	= PHY_GBIT_FEATURES,
+		.probe		= bcm53x25_probe,
+		.remove		= bcm53x25_remove,
+		.config_init	= bcm53x25_ethsw_init,
+		.config_aneg	= bcm53x25_config_aneg,
+		.read_status	= bcm53x25_read_status,
+		.resume		= bcm53x25_ethsw_resume,
+		.driver		= { .owner = THIS_MODULE },
+	},
+	{
+		.phy_id		= BCM53101_PHY_ID,
+		.phy_id_mask	= 0x1ffffff0,
+		.name		= "Broadcom BCM53101",
+		.features	= PHY_BASIC_FEATURES,
+		.probe		= bcm53x25_probe,
+		.remove		= bcm53x25_remove,
+		.config_init	= bcm53x25_ethsw_init,
+		.config_aneg	= bcm53x25_config_aneg,
+		.read_status	= bcm53x25_read_status,
+		.resume		= bcm53x25_ethsw_resume,
+		.driver		= { .owner = THIS_MODULE },
+	},
+};
+
+static int __init bcm53x25_init(void)
+{
+	return phy_drivers_register(bcm53x25_driver,
+			ARRAY_SIZE(bcm53x25_driver));
+}
+
+module_init(bcm53x25_init);
+
+MODULE_DESCRIPTION("Broadcom BCM53x25 switch driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index ba55adfc7aae..da79b62825f3 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -21,6 +21,7 @@
 #include <linux/phy_fixed.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #define MII_REGS_NUM 29
 
@@ -31,7 +32,7 @@ struct fixed_mdio_bus {
 };
 
 struct fixed_phy {
-	int id;
+	int addr;
 	u16 regs[MII_REGS_NUM];
 	struct phy_device *phydev;
 	struct fixed_phy_status status;
@@ -104,8 +105,8 @@ static int fixed_phy_update_regs(struct fixed_phy *fp)
 	if (fp->status.asym_pause)
 		lpa |= LPA_PAUSE_ASYM;
 
-	fp->regs[MII_PHYSID1] = fp->id >> 16;
-	fp->regs[MII_PHYSID2] = fp->id;
+	fp->regs[MII_PHYSID1] = 0;
+	fp->regs[MII_PHYSID2] = 0;
 
 	fp->regs[MII_BMSR] = bmsr;
 	fp->regs[MII_BMCR] = bmcr;
@@ -115,7 +116,7 @@ static int fixed_phy_update_regs(struct fixed_phy *fp)
 	return 0;
 }
 
-static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
+static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
 {
 	struct fixed_mdio_bus *fmb = bus->priv;
 	struct fixed_phy *fp;
@@ -123,8 +124,19 @@ static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
 	if (reg_num >= MII_REGS_NUM)
 		return -1;
 
+	/* We do not support Clause 45 register in Clause 22 compatibility mode
+	 * reject those
+	 */
+	switch (reg_num) {
+	case MII_MMD_CTRL:
+	case MII_MMD_DATA:
+		return -1;
+	default:
+		break;
+	}
+
 	list_for_each_entry(fp, &fmb->phys, node) {
-		if (fp->id == phy_id) {
+		if (fp->addr == phy_addr) {
 			/* Issue callback if user registered it. */
 			if (fp->link_update) {
 				fp->link_update(fp->phydev->attached_dev,
@@ -138,7 +150,7 @@ static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
 	return 0xFFFF;
 }
 
-static int fixed_mdio_write(struct mii_bus *bus, int phy_id, int reg_num,
+static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num,
 			    u16 val)
 {
 	return 0;
@@ -160,7 +172,7 @@ int fixed_phy_set_link_update(struct phy_device *phydev,
 		return -EINVAL;
 
 	list_for_each_entry(fp, &fmb->phys, node) {
-		if (fp->id == phydev->phy_id) {
+		if (fp->addr == phydev->addr) {
 			fp->link_update = link_update;
 			fp->phydev = phydev;
 			return 0;
@@ -171,7 +183,7 @@ int fixed_phy_set_link_update(struct phy_device *phydev,
 }
 EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
 
-int fixed_phy_add(unsigned int irq, int phy_id,
+int fixed_phy_add(unsigned int irq, int phy_addr,
 		  struct fixed_phy_status *status)
 {
 	int ret;
@@ -184,9 +196,9 @@ int fixed_phy_add(unsigned int irq, int phy_id,
 
 	memset(fp->regs, 0xFF,  sizeof(fp->regs[0]) * MII_REGS_NUM);
 
-	fmb->irqs[phy_id] = irq;
+	fmb->irqs[phy_addr] = irq;
 
-	fp->id = phy_id;
+	fp->addr = phy_addr;
 	fp->status = *status;
 
 	ret = fixed_phy_update_regs(fp);
@@ -203,6 +215,66 @@ err_regs:
 }
 EXPORT_SYMBOL_GPL(fixed_phy_add);
 
+void fixed_phy_del(int phy_addr)
+{
+	struct fixed_mdio_bus *fmb = &platform_fmb;
+	struct fixed_phy *fp, *tmp;
+
+	list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
+		if (fp->addr == phy_addr) {
+			list_del(&fp->node);
+			kfree(fp);
+			return;
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(fixed_phy_del);
+
+static int phy_fixed_addr;
+static DEFINE_SPINLOCK(phy_fixed_addr_lock);
+
+struct phy_device *fixed_phy_register(unsigned int irq,
+				      struct fixed_phy_status *status,
+				      struct device_node *np)
+{
+	struct fixed_mdio_bus *fmb = &platform_fmb;
+	struct phy_device *phy;
+	int phy_addr;
+	int ret;
+
+	/* Get the next available PHY address, up to PHY_MAX_ADDR */
+	spin_lock(&phy_fixed_addr_lock);
+	if (phy_fixed_addr == PHY_MAX_ADDR) {
+		spin_unlock(&phy_fixed_addr_lock);
+		return ERR_PTR(-ENOSPC);
+	}
+	phy_addr = phy_fixed_addr++;
+	spin_unlock(&phy_fixed_addr_lock);
+
+	ret = fixed_phy_add(PHY_POLL, phy_addr, status);
+	if (ret < 0)
+		return ERR_PTR(ret);
+
+	phy = get_phy_device(fmb->mii_bus, phy_addr, false);
+	if (!phy || IS_ERR(phy)) {
+		fixed_phy_del(phy_addr);
+		return ERR_PTR(-EINVAL);
+	}
+
+	of_node_get(np);
+	phy->dev.of_node = np;
+
+	ret = phy_device_register(phy);
+	if (ret) {
+		phy_device_free(phy);
+		of_node_put(np);
+		fixed_phy_del(phy_addr);
+		return ERR_PTR(ret);
+	}
+
+	return phy;
+}
+
 static int __init fixed_mdio_bus_init(void)
 {
 	struct fixed_mdio_bus *fmb = &platform_fmb;
diff --git a/drivers/net/phy/mdio-bitbang.c b/drivers/net/phy/mdio-bitbang.c
index daec9b05d168..61a543c788cc 100644
--- a/drivers/net/phy/mdio-bitbang.c
+++ b/drivers/net/phy/mdio-bitbang.c
@@ -165,8 +165,11 @@ static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
 
 	ctrl->ops->set_mdio_dir(ctrl, 0);
 
-	/* check the turnaround bit: the PHY should be driving it to zero */
-	if (mdiobb_get_bit(ctrl) != 0) {
+	/* check the turnaround bit: the PHY should be driving it to zero, if this
+	 * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
+	 */
+	if (mdiobb_get_bit(ctrl) != 0 &&
+	    !(bus->phy_ignore_ta_mask & (1 << phy))) {
 		/* PHY didn't drive TA low -- flush any bits it
 		 * may be trying to send.
 		 */
diff --git a/drivers/net/phy/mdio-unimac.c b/drivers/net/phy/mdio-unimac.c
new file mode 100644
index 000000000000..ac16cb698791
--- /dev/null
+++ b/drivers/net/phy/mdio-unimac.c
@@ -0,0 +1,253 @@
+/*
+ * Broadcom UniMAC MDIO bus controller driver
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_mdio.h>
+
+#define MDIO_CMD		0x00
+#define  MDIO_START_BUSY	(1 << 29)
+#define  MDIO_READ_FAIL		(1 << 28)
+#define  MDIO_RD		(2 << 26)
+#define  MDIO_WR		(1 << 26)
+#define  MDIO_PMD_SHIFT		21
+#define  MDIO_PMD_MASK		0x1F
+#define  MDIO_REG_SHIFT		16
+#define  MDIO_REG_MASK		0x1F
+
+#define MDIO_CFG		0x04
+#define  MDIO_C22		(1 << 0)
+#define  MDIO_C45		0
+#define  MDIO_CLK_DIV_SHIFT	4
+#define  MDIO_CLK_DIV_MASK	0x3F
+#define  MDIO_SUPP_PREAMBLE	(1 << 12)
+
+struct unimac_mdio_priv {
+	struct mii_bus		*mii_bus;
+	void __iomem		*base;
+	unsigned int		complete_handler;
+};
+
+static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
+{
+	u32 reg;
+
+	reg = __raw_readl(priv->base + MDIO_CMD);
+	reg |= MDIO_START_BUSY;
+	__raw_writel(reg, priv->base + MDIO_CMD);
+}
+
+static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
+{
+	return __raw_readl(priv->base + MDIO_CMD) & MDIO_START_BUSY;
+}
+
+static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
+{
+	struct unimac_mdio_priv *priv = bus->priv;
+	unsigned int timeout = 1000;
+	u32 cmd;
+
+	/* Prepare the read operation */
+	cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
+	__raw_writel(cmd, priv->base + MDIO_CMD);
+
+	/* Start MDIO transaction */
+	unimac_mdio_start(priv);
+
+	do {
+		if (!unimac_mdio_busy(priv))
+			break;
+
+		usleep_range(1000, 2000);
+	} while (timeout--);
+
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	cmd = __raw_readl(priv->base + MDIO_CMD);
+	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
+		return -EIO;
+
+	return cmd & 0xffff;
+}
+
+static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
+			int reg, u16 val)
+{
+	struct unimac_mdio_priv *priv = bus->priv;
+	unsigned int timeout = 1000;
+	u32 cmd;
+
+	/* Prepare the write operation */
+	cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+		(reg << MDIO_REG_SHIFT) | (0xffff & val);
+	__raw_writel(cmd, priv->base + MDIO_CMD);
+
+	unimac_mdio_start(priv);
+
+	do {
+		if (!unimac_mdio_busy(priv))
+			break;
+
+		usleep_range(1000, 2000);
+	} while (timeout--);
+
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
+ * their internal MDIO management controller making them fail to successfully
+ * be read from or written to for the first transaction.  We insert a dummy
+ * BMSR read here to make sure that phy_get_device() and get_phy_id() can
+ * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
+ * PHY device for this peripheral.
+ *
+ * Once the PHY driver is registered, we can workaround subsequent reads from
+ * there (e.g: during system-wide power management).
+ *
+ * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
+ * therefore the right location to stick that workaround. Since we do not want
+ * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
+ * Device Tree scan to limit the search area.
+ */
+static int unimac_mdio_reset(struct mii_bus *bus)
+{
+	struct device_node *np = bus->dev.of_node;
+	struct device_node *child;
+	u32 read_mask = 0;
+	int addr;
+
+	if (!np) {
+		read_mask = ~bus->phy_mask;
+	} else {
+		for_each_available_child_of_node(np, child) {
+			addr = of_mdio_parse_addr(&bus->dev, child);
+			if (addr < 0)
+				continue;
+
+			read_mask |= 1 << addr;
+		}
+	}
+
+	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+		if (read_mask & 1 << addr)
+			mdiobus_read(bus, addr, MII_BMSR);
+	}
+
+	return 0;
+}
+
+static int unimac_mdio_probe(struct platform_device *pdev)
+{
+	struct unimac_mdio_priv *priv;
+	struct device_node *np;
+	struct mii_bus *bus;
+	struct resource *r;
+	int ret;
+
+	np = pdev->dev.of_node;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	/* Just ioremap, as this MDIO block is usually integrated into an
+	 * Ethernet MAC controller register range
+	 */
+	priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!priv->base) {
+		dev_err(&pdev->dev, "failed to remap register\n");
+		return -ENOMEM;
+	}
+
+	priv->mii_bus = mdiobus_alloc();
+	if (!priv->mii_bus)
+		return -ENOMEM;
+
+	bus = priv->mii_bus;
+	bus->priv = priv;
+	bus->name = "unimac MII bus";
+	bus->parent = &pdev->dev;
+	bus->read = unimac_mdio_read;
+	bus->write = unimac_mdio_write;
+	bus->reset = unimac_mdio_reset;
+	snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
+
+	bus->irq = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!bus->irq) {
+		ret = -ENOMEM;
+		goto out_mdio_free;
+	}
+
+	ret = of_mdiobus_register(bus, np);
+	if (ret) {
+		dev_err(&pdev->dev, "MDIO bus registration failed\n");
+		goto out_mdio_irq;
+	}
+
+	platform_set_drvdata(pdev, priv);
+
+	dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
+
+	return 0;
+
+out_mdio_irq:
+	kfree(bus->irq);
+out_mdio_free:
+	mdiobus_free(bus);
+	return ret;
+}
+
+static int unimac_mdio_remove(struct platform_device *pdev)
+{
+	struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
+
+	mdiobus_unregister(priv->mii_bus);
+	kfree(priv->mii_bus->irq);
+	mdiobus_free(priv->mii_bus);
+
+	return 0;
+}
+
+static struct of_device_id unimac_mdio_ids[] = {
+	{ .compatible = "brcm,genet-mdio-v4", },
+	{ .compatible = "brcm,unimac-mdio", },
+};
+
+static struct platform_driver unimac_mdio_driver = {
+	.driver = {
+		.name = "unimac-mdio",
+		.owner = THIS_MODULE,
+		.of_match_table = unimac_mdio_ids,
+	},
+	.probe	= unimac_mdio_probe,
+	.remove	= unimac_mdio_remove,
+};
+module_platform_driver(unimac_mdio_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:unimac-mdio");
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 71e49000fbf3..fc7068604461 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -326,9 +326,13 @@ static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 	if (!drv || !phydrv->suspend)
 		return false;
 
-	/* PHY not attached? May suspend. */
+	/* PHY not attached? May suspend if the PHY has not already been
+	 * suspended as part of a prior call to phy_disconnect() ->
+	 * phy_detach() -> phy_suspend() because the parent netdev might be the
+	 * MDIO bus driver and clock gated at this point.
+	 */
 	if (!netdev)
-		return true;
+		return !phydev->suspended;
 
 	/* Don't suspend PHY if the attched netdev parent may wakeup.
 	 * The parent may point to a PCI device, as in tg3 driver.
@@ -348,7 +352,6 @@ static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
 
 static int mdio_bus_suspend(struct device *dev)
 {
-	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
 
 	/* We must stop the state machine manually, otherwise it stops out of
@@ -362,19 +365,18 @@ static int mdio_bus_suspend(struct device *dev)
 	if (!mdio_bus_phy_may_suspend(phydev))
 		return 0;
 
-	return phydrv->suspend(phydev);
+	return phy_suspend(phydev);
 }
 
 static int mdio_bus_resume(struct device *dev)
 {
-	struct phy_driver *phydrv = to_phy_driver(dev->driver);
 	struct phy_device *phydev = to_phy_device(dev);
 	int ret;
 
 	if (!mdio_bus_phy_may_suspend(phydev))
 		goto no_resume;
 
-	ret = phydrv->resume(phydev);
+	ret = phy_resume(phydev);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 65cfc5a436c7..5da2b711bbf1 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -302,7 +302,10 @@ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
 
 	ethtool_cmd_speed_set(cmd, phydev->speed);
 	cmd->duplex = phydev->duplex;
-	cmd->port = PORT_MII;
+	if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
+		cmd->port = PORT_BNC;
+	else
+		cmd->port = PORT_MII;
 	cmd->phy_address = phydev->addr;
 	cmd->transceiver = phy_is_internal(phydev) ?
 		XCVR_INTERNAL : XCVR_EXTERNAL;
@@ -326,6 +329,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
 {
 	struct mii_ioctl_data *mii_data = if_mii(ifr);
 	u16 val = mii_data->val_in;
+	bool change_autoneg = false;
 
 	switch (cmd) {
 	case SIOCGMIIPHY:
@@ -341,22 +345,29 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
 		if (mii_data->phy_id == phydev->addr) {
 			switch (mii_data->reg_num) {
 			case MII_BMCR:
-				if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0)
+				if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
+					if (phydev->autoneg == AUTONEG_ENABLE)
+						change_autoneg = true;
 					phydev->autoneg = AUTONEG_DISABLE;
-				else
+					if (val & BMCR_FULLDPLX)
+						phydev->duplex = DUPLEX_FULL;
+					else
+						phydev->duplex = DUPLEX_HALF;
+					if (val & BMCR_SPEED1000)
+						phydev->speed = SPEED_1000;
+					else if (val & BMCR_SPEED100)
+						phydev->speed = SPEED_100;
+					else phydev->speed = SPEED_10;
+				}
+				else {
+					if (phydev->autoneg == AUTONEG_DISABLE)
+						change_autoneg = true;
 					phydev->autoneg = AUTONEG_ENABLE;
-				if (!phydev->autoneg && (val & BMCR_FULLDPLX))
-					phydev->duplex = DUPLEX_FULL;
-				else
-					phydev->duplex = DUPLEX_HALF;
-				if (!phydev->autoneg && (val & BMCR_SPEED1000))
-					phydev->speed = SPEED_1000;
-				else if (!phydev->autoneg &&
-					 (val & BMCR_SPEED100))
-					phydev->speed = SPEED_100;
+				}
 				break;
 			case MII_ADVERTISE:
-				phydev->advertising = val;
+				phydev->advertising = mii_adv_to_ethtool_adv_t(val);
+				change_autoneg = true;
 				break;
 			default:
 				/* do nothing */
@@ -370,6 +381,10 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
 		if (mii_data->reg_num == MII_BMCR &&
 		    val & BMCR_RESET)
 			return phy_init_hw(phydev);
+
+		if (change_autoneg)
+			return phy_start_aneg(phydev);
+
 		return 0;
 
 	case SIOCSHWTSTAMP:
@@ -401,6 +416,9 @@ int phy_start_aneg(struct phy_device *phydev)
 	if (AUTONEG_DISABLE == phydev->autoneg)
 		phy_sanitize_settings(phydev);
 
+	/* Invalidate LP advertising flags */
+	phydev->lp_advertising = 0;
+
 	err = phydev->drv->config_aneg(phydev);
 	if (err < 0)
 		goto out_unlock;
@@ -917,7 +935,7 @@ static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Read  reg 14 // Read MMD data
  */
-static int phy_read_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
+int phy_read_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
 				 int addr)
 {
 	mmd_phy_indirect(bus, prtad, devad, addr);
@@ -925,6 +943,7 @@ static int phy_read_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
 	/* Read the content of the MMD's selected register */
 	return bus->read(bus, addr, MII_MMD_DATA);
 }
+EXPORT_SYMBOL(phy_read_mmd_indirect);
 
 /**
  * phy_write_mmd_indirect - writes data to the MMD registers
@@ -942,7 +961,7 @@ static int phy_read_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Write reg 14 // Write MMD data
  */
-static void phy_write_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
+void phy_write_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
 				   int addr, u32 data)
 {
 	mmd_phy_indirect(bus, prtad, devad, addr);
@@ -950,6 +969,7 @@ static void phy_write_mmd_indirect(struct mii_bus *bus, int prtad, int devad,
 	/* Write the data into MMD's selected register */
 	bus->write(bus, addr, MII_MMD_DATA, data);
 }
+EXPORT_SYMBOL(phy_write_mmd_indirect);
 
 /**
  * phy_init_eee - init and check the EEE feature
@@ -970,7 +990,8 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
 	 */
 	if ((phydev->duplex == DUPLEX_FULL) &&
 	    ((phydev->interface == PHY_INTERFACE_MODE_MII) ||
-	    (phydev->interface == PHY_INTERFACE_MODE_GMII) ||
+	     (phydev->interface == PHY_INTERFACE_MODE_GMII) ||
+	     phy_is_internal(phydev) ||
 	     (phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
 	      phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID))) {
 		int eee_lp, eee_cap, eee_adv;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 62c3fb91e76f..9b970240ea72 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -684,6 +684,7 @@ int phy_suspend(struct phy_device *phydev)
 {
 	struct phy_driver *phydrv = to_phy_driver(phydev->dev.driver);
 	struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+	int ret = 0;
 
 	/* If the device has WOL enabled, we cannot suspend the PHY */
 	phy_ethtool_get_wol(phydev, &wol);
@@ -691,16 +692,29 @@ int phy_suspend(struct phy_device *phydev)
 		return -EBUSY;
 
 	if (phydrv->suspend)
-		return phydrv->suspend(phydev);
+		ret = phydrv->suspend(phydev);
+
+	if (ret)
+		return ret;
+
+	phydev->suspended = true;
+
 	return 0;
 }
 
 int phy_resume(struct phy_device *phydev)
 {
 	struct phy_driver *phydrv = to_phy_driver(phydev->dev.driver);
+	int ret = 0;
 
 	if (phydrv->resume)
-		return phydrv->resume(phydev);
+		ret = phydrv->resume(phydev);
+
+	if (ret)
+		return ret;
+
+	phydev->suspended = false;
+
 	return 0;
 }
 
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index a35d1dedeffb..7b86d906f302 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -311,7 +311,7 @@ static struct usb_device_id rtl8192c_usb_ids[] = {
 	{RTL_USB_DEVICE(0x050d, 0x1102, rtl92cu_hal_cfg)}, /*Belkin - Edimax*/
 	{RTL_USB_DEVICE(0x050d, 0x11f2, rtl92cu_hal_cfg)}, /*Belkin - ISY*/
 	{RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/
-	{RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/
+//	{RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/
 	{RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/
 	{RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/
 	{RTL_USB_DEVICE(0x0846, 0x9043, rtl92cu_hal_cfg)}, /*NG WNA1000Mv2*/
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index c6973f101a3e..30a7d87a8077 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -75,4 +75,10 @@ config OF_MTD
 	depends on MTD
 	def_bool y
 
+config OF_RESERVED_MEM
+	depends on OF_EARLY_FLATTREE
+	bool
+	help
+	  Helpers to allow for reservation of memory regions
+
 endmenu # OF
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index efd05102c405..ed9660adad77 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
 obj-$(CONFIG_OF_PCI)	+= of_pci.o
 obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
 obj-$(CONFIG_OF_MTD)	+= of_mtd.o
+obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
diff --git a/drivers/of/base.c b/drivers/of/base.c
index e99f329c905e..b869b8b4ff68 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -904,6 +904,38 @@ struct device_node *of_find_node_by_phandle(phandle handle)
 EXPORT_SYMBOL(of_find_node_by_phandle);
 
 /**
+ * of_property_count_elems_of_size - Count the number of elements in a property
+ *
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ * @elem_size:	size of the individual element
+ *
+ * Search for a property in a device node and count the number of elements of
+ * size elem_size in it. Returns number of elements on sucess, -EINVAL if the
+ * property does not exist or its length does not match a multiple of elem_size
+ * and -ENODATA if the property does not have a value.
+ */
+int of_property_count_elems_of_size(const struct device_node *np,
+				const char *propname, int elem_size)
+{
+	struct property *prop = of_find_property(np, propname, NULL);
+
+	if (!prop)
+		return -EINVAL;
+	if (!prop->value)
+		return -ENODATA;
+
+	if (prop->length % elem_size != 0) {
+		pr_err("size of %s in node %s is not a multiple of %d\n",
+		       propname, np->full_name, elem_size);
+		return -EINVAL;
+	}
+
+	return prop->length / elem_size;
+}
+EXPORT_SYMBOL_GPL(of_property_count_elems_of_size);
+
+/**
  * of_find_property_value_of_size
  *
  * @np:		device node from which the property value is to be read.
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 758b4f8b30b7..de3c0c623c4f 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -15,6 +15,8 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_fdt.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/sizes.h>
 #include <linux/string.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
@@ -436,10 +438,133 @@ int __initdata dt_root_addr_cells;
 int __initdata dt_root_size_cells;
 
 struct boot_param_header *initial_boot_params;
+#ifdef CONFIG_BRCMSTB
+EXPORT_SYMBOL(initial_boot_params);
+#endif
 
 #ifdef CONFIG_OF_EARLY_FLATTREE
 
 /**
+ * res_mem_reserve_reg() - reserve all memory described in 'reg' property
+ */
+static int __init __reserved_mem_reserve_reg(unsigned long node,
+					     const char *uname)
+{
+	int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
+	phys_addr_t base, size;
+	unsigned long len;
+	__be32 *prop;
+	int nomap, first = 1;
+
+	prop = of_get_flat_dt_prop(node, "reg", &len);
+	if (!prop)
+		return -ENOENT;
+
+	if (len && len % t_len != 0) {
+		pr_err("Reserved memory: invalid reg property in '%s', skipping node.\n",
+		       uname);
+		return -EINVAL;
+	}
+
+	nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
+
+	while (len >= t_len) {
+		base = dt_mem_next_cell(dt_root_addr_cells, &prop);
+		size = dt_mem_next_cell(dt_root_size_cells, &prop);
+
+		if (size &&
+		    early_init_dt_reserve_memory_arch(base, size, nomap) == 0)
+			pr_debug("Reserved memory: reserved region for node '%s': base %pa, size %ld MiB\n",
+				uname, &base, (unsigned long)size / SZ_1M);
+		else
+			pr_info("Reserved memory: failed to reserve memory for node '%s': base %pa, size %ld MiB\n",
+				uname, &base, (unsigned long)size / SZ_1M);
+
+		len -= t_len;
+		if (first) {
+			fdt_reserved_mem_save_node(node, uname, base, size);
+			first = 0;
+		}
+	}
+	return 0;
+}
+
+/**
+ * __reserved_mem_check_root() - check if #size-cells, #address-cells provided
+ * in /reserved-memory matches the values supported by the current implementation,
+ * also check if ranges property has been provided
+ */
+static int __reserved_mem_check_root(unsigned long node)
+{
+	__be32 *prop;
+
+	prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
+	if (!prop || be32_to_cpup(prop) != dt_root_size_cells)
+		return -EINVAL;
+
+	prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
+	if (!prop || be32_to_cpup(prop) != dt_root_addr_cells)
+		return -EINVAL;
+
+	prop = of_get_flat_dt_prop(node, "ranges", NULL);
+	if (!prop)
+		return -EINVAL;
+	return 0;
+}
+
+/**
+ * fdt_scan_reserved_mem() - scan a single FDT node for reserved memory
+ */
+static int __init __fdt_scan_reserved_mem(unsigned long node, const char *uname,
+					  int depth, void *data)
+{
+	static int found;
+	const char *status;
+	int err;
+
+	if (!found && depth == 1 && strcmp(uname, "reserved-memory") == 0) {
+		if (__reserved_mem_check_root(node) != 0) {
+			pr_err("Reserved memory: unsupported node format, ignoring\n");
+			/* break scan */
+			return 1;
+		}
+		found = 1;
+		/* scan next node */
+		return 0;
+	} else if (!found) {
+		/* scan next node */
+		return 0;
+	} else if (found && depth < 2) {
+		/* scanning of /reserved-memory has been finished */
+		return 1;
+	}
+
+	status = of_get_flat_dt_prop(node, "status", NULL);
+	if (status && strcmp(status, "okay") != 0 && strcmp(status, "ok") != 0)
+		return 0;
+
+	err = __reserved_mem_reserve_reg(node, uname);
+	if (err == -ENOENT && of_get_flat_dt_prop(node, "size", NULL))
+		fdt_reserved_mem_save_node(node, uname, 0, 0);
+
+	/* scan next node */
+	return 0;
+}
+
+/**
+ * early_init_fdt_scan_reserved_mem() - create reserved memory regions
+ *
+ * This function grabs memory from early allocator for device exclusive use
+ * defined in device tree structures. It should be called by arch specific code
+ * once the early allocator (i.e. memblock) has been fully activated.
+ */
+void __init early_init_fdt_scan_reserved_mem(void)
+{
+	of_scan_flat_dt(__fdt_scan_reserved_mem, NULL);
+	fdt_init_reserved_mem();
+}
+
+/**
  * of_scan_flat_dt - scan flattened tree blob and call callback on each.
  * @it: callback function
  * @data: context data pointer
@@ -856,6 +981,16 @@ void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
 	memblock_add(base, size);
 }
 
+int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base,
+					phys_addr_t size, bool nomap)
+{
+	if (memblock_is_region_reserved(base, size))
+		return -EBUSY;
+	if (nomap)
+		return memblock_remove(base, size);
+	return memblock_reserve(base, size);
+}
+
 /*
  * called from unflatten_device_tree() to bootstrap devicetree itself
  * Architectures can override this definition if memblock isn't used
@@ -864,6 +999,14 @@ void * __init __weak early_init_dt_alloc_memory_arch(u64 size, u64 align)
 {
 	return __va(memblock_alloc(size, align));
 }
+#else
+int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base,
+					phys_addr_t size, bool nomap)
+{
+	pr_err("Reserved memory not supported, ignoring range 0x%llx - 0x%llx%s\n",
+		  base, size, nomap ? " (nomap)" : "");
+	return -ENOSYS;
+}
 #endif
 
 bool __init early_init_dt_scan(void *params)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 5b3c24f3cde5..29a7537a7705 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -14,6 +14,7 @@
 #include <linux/netdevice.h>
 #include <linux/err.h>
 #include <linux/phy.h>
+#include <linux/phy_fixed.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_mdio.h>
@@ -68,6 +69,9 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi
 			phy->irq = mdio->irq[addr];
 	}
 
+	if (of_property_read_bool(child, "broken-turn-around"))
+		mdio->phy_ignore_ta_mask |= 1 << addr;
+
 	/* Associate the OF node with the device structure so it
 	 * can be looked up later */
 	of_node_get(child);
@@ -93,6 +97,28 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi
 	return 0;
 }
 
+int of_mdio_parse_addr(struct device *dev, const struct device_node *np)
+{
+	u32 addr;
+	int ret;
+
+	ret = of_property_read_u32(np, "reg", &addr);
+	if (ret < 0) {
+		dev_err(dev, "%s has invalid PHY address\n", np->full_name);
+		return ret;
+	}
+
+	/* A PHY must have a reg property in the range [0-31] */
+	if (addr >= PHY_MAX_ADDR) {
+		dev_err(dev, "%s PHY address %i is too large\n",
+			np->full_name, addr);
+		return -EINVAL;
+	}
+
+	return addr;
+}
+EXPORT_SYMBOL(of_mdio_parse_addr);
+
 /**
  * of_mdiobus_register - Register mii_bus and create PHYs from the device tree
  * @mdio: pointer to mii_bus structure
@@ -105,9 +131,8 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
 {
 	struct device_node *child;
 	const __be32 *paddr;
-	u32 addr;
 	bool scanphys = false;
-	int rc, i, len;
+	int addr, rc, i;
 
 	/* Mask out all PHYs from auto probing.  Instead the PHYs listed in
 	 * the device tree are populated after the bus has been registered */
@@ -127,19 +152,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
 
 	/* Loop over the child nodes and register a phy_device for each one */
 	for_each_available_child_of_node(np, child) {
-		/* A PHY must have a reg property in the range [0-31] */
-		paddr = of_get_property(child, "reg", &len);
-		if (!paddr || len < sizeof(*paddr)) {
+		addr = of_mdio_parse_addr(&mdio->dev, child);
+		if (addr < 0) {
 			scanphys = true;
-			dev_err(&mdio->dev, "%s has invalid PHY address\n",
-				child->full_name);
-			continue;
-		}
-
-		addr = be32_to_cpup(paddr);
-		if (addr >= PHY_MAX_ADDR) {
-			dev_err(&mdio->dev, "%s PHY address %i is too large\n",
-				child->full_name, addr);
 			continue;
 		}
 
@@ -154,7 +169,7 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
 	/* auto scan for PHYs with empty reg property */
 	for_each_available_child_of_node(np, child) {
 		/* Skip PHYs with reg property set */
-		paddr = of_get_property(child, "reg", &len);
+		paddr = of_get_property(child, "reg", NULL);
 		if (paddr)
 			continue;
 
@@ -219,6 +234,8 @@ struct phy_device *of_phy_connect(struct net_device *dev,
 	if (!phy)
 		return NULL;
 
+	phy->dev_flags = flags;
+
 	return phy_connect_direct(dev, phy, hndlr, iface) ? NULL : phy;
 }
 EXPORT_SYMBOL(of_phy_connect);
@@ -251,6 +268,9 @@ struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
 		return NULL;
 
 	phy_id = of_get_property(net_np, "fixed-link", &sz);
+	if (!phy_id)
+		phy_id = of_get_property(dev->dev.of_node, "fixed-link", &sz);
+
 	if (!phy_id || sz < sizeof(*phy_id))
 		return NULL;
 
@@ -280,3 +300,74 @@ struct phy_device *of_phy_attach(struct net_device *dev,
 	return phy_attach_direct(dev, phy, flags, iface) ? NULL : phy;
 }
 EXPORT_SYMBOL(of_phy_attach);
+
+#if defined(CONFIG_FIXED_PHY)
+/*
+ * of_phy_is_fixed_link() and of_phy_register_fixed_link() must
+ * support two DT bindings:
+ * - the old DT binding, where 'fixed-link' was a property with 5
+ *   cells encoding various informations about the fixed PHY
+ * - the new DT binding, where 'fixed-link' is a sub-node of the
+ *   Ethernet device.
+ */
+bool of_phy_is_fixed_link(struct device_node *np)
+{
+	struct device_node *dn;
+	int len;
+
+	/* New binding */
+	dn = of_get_child_by_name(np, "fixed-link");
+	if (dn) {
+		of_node_put(dn);
+		return true;
+	}
+
+	/* Old binding */
+	if (of_get_property(np, "fixed-link", &len) &&
+	    len == (5 * sizeof(__be32)))
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL(of_phy_is_fixed_link);
+
+int of_phy_register_fixed_link(struct device_node *np)
+{
+	struct fixed_phy_status status = {};
+	struct device_node *fixed_link_node;
+	const __be32 *fixed_link_prop;
+	int len;
+	struct phy_device *phy;
+
+	/* New binding */
+	fixed_link_node = of_get_child_by_name(np, "fixed-link");
+	if (fixed_link_node) {
+		status.link = 1;
+		status.duplex = of_property_read_bool(fixed_link_node,
+						      "full-duplex");
+		if (of_property_read_u32(fixed_link_node, "speed", &status.speed))
+			return -EINVAL;
+		status.pause = of_property_read_bool(fixed_link_node, "pause");
+		status.asym_pause = of_property_read_bool(fixed_link_node,
+							  "asym-pause");
+		of_node_put(fixed_link_node);
+		phy = fixed_phy_register(PHY_POLL, &status, np);
+		return IS_ERR(phy) ? PTR_ERR(phy) : 0;
+	}
+
+	/* Old binding */
+	fixed_link_prop = of_get_property(np, "fixed-link", &len);
+	if (fixed_link_prop && len == (5 * sizeof(__be32))) {
+		status.link = 1;
+		status.duplex = be32_to_cpu(fixed_link_prop[1]);
+		status.speed = be32_to_cpu(fixed_link_prop[2]);
+		status.pause = be32_to_cpu(fixed_link_prop[3]);
+		status.asym_pause = be32_to_cpu(fixed_link_prop[4]);
+		phy = fixed_phy_register(PHY_POLL, &status, np);
+		return IS_ERR(phy) ? PTR_ERR(phy) : 0;
+	}
+
+	return -ENODEV;
+}
+EXPORT_SYMBOL(of_phy_register_fixed_link);
+#endif
diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index a208a457558c..959091492324 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -31,6 +31,7 @@ static const char *phy_modes[] = {
 	[PHY_INTERFACE_MODE_RTBI]	= "rtbi",
 	[PHY_INTERFACE_MODE_SMII]	= "smii",
 	[PHY_INTERFACE_MODE_XGMII]	= "xgmii",
+	[PHY_INTERFACE_MODE_MOCA]	= "moca",
 };
 
 /**
diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
new file mode 100644
index 000000000000..12e450e2d153
--- /dev/null
+++ b/drivers/of/of_reserved_mem.c
@@ -0,0 +1,217 @@
+/*
+ * Device tree based initialization code for reserved memory.
+ *
+ * Copyright (c) 2013, The Linux Foundation. All Rights Reserved.
+ * Copyright (c) 2013,2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ * Author: Josh Cartwright <joshc@codeaurora.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License or (at your optional) any later version of the license.
+ */
+
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/mm.h>
+#include <linux/sizes.h>
+#include <linux/of_reserved_mem.h>
+
+#define MAX_RESERVED_REGIONS	16
+static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS];
+static int reserved_mem_count;
+
+#if defined(CONFIG_HAVE_MEMBLOCK)
+#include <linux/memblock.h>
+int __init __weak early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
+	phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap,
+	phys_addr_t *res_base)
+{
+	/*
+	 * We use __memblock_alloc_base() because memblock_alloc_base()
+	 * panic()s on allocation failure.
+	 */
+	phys_addr_t base = __memblock_alloc_base(size, align, end);
+	if (!base)
+		return -ENOMEM;
+
+	/*
+	 * Check if the allocated region fits in to start..end window
+	 */
+	if (base < start) {
+		memblock_free(base, size);
+		return -ENOMEM;
+	}
+
+	*res_base = base;
+	if (nomap)
+		return memblock_remove(base, size);
+	return 0;
+}
+#else
+int __init __weak early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
+	phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap,
+	phys_addr_t *res_base)
+{
+	pr_err("Reserved memory not supported, ignoring region 0x%llx%s\n",
+		  size, nomap ? " (nomap)" : "");
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * res_mem_save_node() - save fdt node for second pass initialization
+ */
+void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
+				      phys_addr_t base, phys_addr_t size)
+{
+	struct reserved_mem *rmem = &reserved_mem[reserved_mem_count];
+
+	if (reserved_mem_count == ARRAY_SIZE(reserved_mem)) {
+		pr_err("Reserved memory: not enough space all defined regions.\n");
+		return;
+	}
+
+	rmem->fdt_node = node;
+	rmem->name = uname;
+	rmem->base = base;
+	rmem->size = size;
+
+	reserved_mem_count++;
+	return;
+}
+
+/**
+ * res_mem_alloc_size() - allocate reserved memory described by 'size', 'align'
+ *			  and 'alloc-ranges' properties
+ */
+static int __init __reserved_mem_alloc_size(unsigned long node,
+	const char *uname, phys_addr_t *res_base, phys_addr_t *res_size)
+{
+	int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
+	phys_addr_t start = 0, end = 0;
+	phys_addr_t base = 0, align = 0, size;
+	unsigned long len;
+	__be32 *prop;
+	int nomap;
+	int ret;
+
+	prop = of_get_flat_dt_prop(node, "size", &len);
+	if (!prop)
+		return -EINVAL;
+
+	if (len != dt_root_size_cells * sizeof(__be32)) {
+		pr_err("Reserved memory: invalid size property in '%s' node.\n",
+				uname);
+		return -EINVAL;
+	}
+	size = dt_mem_next_cell(dt_root_size_cells, &prop);
+
+	nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
+
+	prop = of_get_flat_dt_prop(node, "alignment", &len);
+	if (prop) {
+		if (len != dt_root_addr_cells * sizeof(__be32)) {
+			pr_err("Reserved memory: invalid alignment property in '%s' node.\n",
+				uname);
+			return -EINVAL;
+		}
+		align = dt_mem_next_cell(dt_root_addr_cells, &prop);
+	}
+
+	prop = of_get_flat_dt_prop(node, "alloc-ranges", &len);
+	if (prop) {
+
+		if (len % t_len != 0) {
+			pr_err("Reserved memory: invalid alloc-ranges property in '%s', skipping node.\n",
+			       uname);
+			return -EINVAL;
+		}
+
+		base = 0;
+
+		while (len > 0) {
+			start = dt_mem_next_cell(dt_root_addr_cells, &prop);
+			end = start + dt_mem_next_cell(dt_root_size_cells,
+						       &prop);
+
+			ret = early_init_dt_alloc_reserved_memory_arch(size,
+					align, start, end, nomap, &base);
+			if (ret == 0) {
+				pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n",
+					uname, &base,
+					(unsigned long)size / SZ_1M);
+				break;
+			}
+			len -= t_len;
+		}
+
+	} else {
+		ret = early_init_dt_alloc_reserved_memory_arch(size, align,
+							0, 0, nomap, &base);
+		if (ret == 0)
+			pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n",
+				uname, &base, (unsigned long)size / SZ_1M);
+	}
+
+	if (base == 0) {
+		pr_info("Reserved memory: failed to allocate memory for node '%s'\n",
+			uname);
+		return -ENOMEM;
+	}
+
+	*res_base = base;
+	*res_size = size;
+
+	return 0;
+}
+
+static const struct of_device_id __rmem_of_table_sentinel
+	__used __section(__reservedmem_of_table_end);
+
+/**
+ * res_mem_init_node() - call region specific reserved memory init code
+ */
+static int __init __reserved_mem_init_node(struct reserved_mem *rmem)
+{
+	extern const struct of_device_id __reservedmem_of_table[];
+	const struct of_device_id *i;
+
+	for (i = __reservedmem_of_table; i < &__rmem_of_table_sentinel; i++) {
+		reservedmem_of_init_fn initfn = i->data;
+		const char *compat = i->compatible;
+
+		if (!of_flat_dt_is_compatible(rmem->fdt_node, compat))
+			continue;
+
+		if (initfn(rmem) == 0) {
+			pr_info("Reserved memory: initialized node %s, compatible id %s\n",
+				rmem->name, compat);
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+/**
+ * fdt_init_reserved_mem - allocate and init all saved reserved memory regions
+ */
+void __init fdt_init_reserved_mem(void)
+{
+	int i;
+	for (i = 0; i < reserved_mem_count; i++) {
+		struct reserved_mem *rmem = &reserved_mem[i];
+		unsigned long node = rmem->fdt_node;
+		int err = 0;
+
+		if (rmem->size == 0)
+			err = __reserved_mem_alloc_size(node, rmem->name,
+						 &rmem->base, &rmem->size);
+		if (err == 0)
+			__reserved_mem_init_node(rmem);
+	}
+}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 78c65d327e33..2c0f13db6550 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -528,6 +528,7 @@ static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 {
 	u16 pmcsr;
+	u32 vendor;
 	bool need_restore = false;
 
 	/* Check if we're already there */
@@ -556,6 +557,11 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 	   || (state == PCI_D2 && !dev->d2_support))
 		return -EIO;
 
+	/* Allow for CRS Software Visibility */
+	if (dev->current_state >= PCI_D3hot
+	    && !pci_bus_read_dev_vendor_id(dev->bus, dev->devfn, &vendor, 1000))
+		return -EIO;
+
 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 
 	/* If we're (effectively) in D3, force entire word to 0.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c25371cca..970bf2bfcc2b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_BCM_KONA_USB2_PHY)		+= phy-bcm-kona-usb2.o
+obj-$(CONFIG_BRCM_USB_PHY)		+= phy-brcm-usb.o
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)	+= phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
diff --git a/drivers/phy/phy-brcm-usb.c b/drivers/phy/phy-brcm-usb.c
new file mode 100644
index 000000000000..f0c07a6677ae
--- /dev/null
+++ b/drivers/phy/phy-brcm-usb.c
@@ -0,0 +1,234 @@
+/*
+ * phy-brcm-usb.c - Broadcom USB Phy Driver
+ *
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include "../drivers/usb/host/usb-brcm-common-init.h"
+
+
+enum brcm_usb_phy_id {
+	BRCM_USB_PHY_2_0,
+	BRCM_USB_PHY_3_0,
+	BRCM_USB_PHY_ID_MAX
+};
+
+struct brcm_usb_phy_data {
+	void __iomem		*ctrl_regs;
+	void __iomem		*xhci_ec_regs;
+	int			ioc;
+	int			ipp;
+	int			has_xhci;
+	int			device_mode;
+	struct clk		*usb_20_clk;
+	struct clk		*usb_30_clk;
+	int			num_phys;
+	struct brcm_usb_phy {
+		struct phy *phy;
+		unsigned int index;
+	} phys[BRCM_USB_PHY_ID_MAX];
+};
+
+#define to_brcm_usb_phy_data(phy) \
+	container_of((phy), struct brcm_usb_phy_data, phys[(phy)->index])
+
+static struct phy_ops brcm_usb_phy_ops = {
+	.owner		= THIS_MODULE,
+};
+
+static struct phy *brcm_usb_phy_xlate(struct device *dev,
+				struct of_phandle_args *args)
+{
+	struct brcm_usb_phy_data *data = dev_get_drvdata(dev);
+
+	if (args->args[0] >= data->num_phys)
+		return ERR_PTR(-ENODEV);
+
+	return data->phys[args->args[0]].phy;
+}
+
+static int brcm_usb_phy_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	struct brcm_usb_phy_data *priv;
+	struct phy *gphy;
+	struct phy_provider *phy_provider;
+	struct device_node *dn = pdev->dev.of_node;
+	const u32 *prop;
+	int i;
+	int err;
+	struct brcm_usb_common_init_params params;
+	const char *device_mode;
+	char err_msg_ioremap[] = "can't map register space\n";
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, priv);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "can't get USB_CTRL base address\n");
+		return -EINVAL;
+	}
+	priv->ctrl_regs = devm_request_and_ioremap(&pdev->dev, res);
+	if (!priv->ctrl_regs) {
+		dev_err(&pdev->dev, err_msg_ioremap);
+		return -EINVAL;
+	}
+
+	/* The XHCI EC registers are optional */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res != NULL) {
+		priv->xhci_ec_regs =
+			devm_request_and_ioremap(&pdev->dev, res);
+		if (!priv->xhci_ec_regs) {
+			dev_err(&pdev->dev, err_msg_ioremap);
+			return -EINVAL;
+		}
+	}
+
+	of_property_read_u32(dn, "ipp", &priv->ipp);
+	of_property_read_u32(dn, "ioc", &priv->ioc);
+
+	priv->device_mode = USB_CTLR_DEVICE_OFF;
+	err = of_property_read_string(dn, "device", &device_mode);
+	if (err == 0) {
+		if (strcmp(device_mode, "on") == 0)
+			priv->device_mode = USB_CTLR_DEVICE_ON;
+		if (strcmp(device_mode, "dual") == 0)
+			priv->device_mode = USB_CTLR_DEVICE_DUAL;
+	}
+
+	prop = of_get_property(dn, "has_xhci", NULL);
+	if (prop) {
+		priv->has_xhci = 1;
+		priv->num_phys = 2;
+	} else {
+		priv->num_phys = 1;
+	}
+
+	for (i = 0; i < priv->num_phys; i++) {
+		gphy = devm_phy_create(dev, &brcm_usb_phy_ops, NULL);
+		if (IS_ERR(gphy)) {
+			dev_err(dev, "failed to create PHY %d\n", i);
+			return PTR_ERR(gphy);
+		}
+		priv->phys[i].phy = gphy;
+		priv->phys[i].index = i;
+		phy_set_drvdata(gphy, &priv->phys[i]);
+	}
+	phy_provider = devm_of_phy_provider_register(dev,
+			brcm_usb_phy_xlate);
+	if (IS_ERR(phy_provider))
+		return PTR_ERR(phy_provider);
+
+	priv->usb_20_clk = of_clk_get_by_name(dn, "sw_usb");
+	if (IS_ERR(priv->usb_20_clk)) {
+		dev_err(&pdev->dev, "Clock not found in Device Tree\n");
+		priv->usb_20_clk = NULL;
+	}
+	err = clk_prepare_enable(priv->usb_20_clk);
+	if (err)
+		return err;
+
+	/* Get the USB3.0 clocks if we have XHCI */
+	if (priv->has_xhci) {
+		priv->usb_30_clk = of_clk_get_by_name(dn, "sw_usb3");
+		if (IS_ERR(priv->usb_30_clk)) {
+			/* Older device-trees are missing this clock */
+			dev_info(&pdev->dev,
+				"USB3.0 clock not found in Device Tree\n");
+			priv->usb_30_clk = NULL;
+		}
+		err = clk_prepare_enable(priv->usb_30_clk);
+		if (err)
+			return err;
+	}
+
+	params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+	params.ioc = priv->ioc;
+	params.ipp = priv->ipp;
+	params.has_xhci = priv->has_xhci;
+	params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+	params.device_mode = priv->device_mode;
+	brcm_usb_common_init(&params);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcm_usb_phy_suspend(struct device *dev)
+{
+	struct brcm_usb_phy_data *priv = dev_get_drvdata(dev);
+
+	clk_disable(priv->usb_20_clk);
+	clk_disable(priv->usb_30_clk);
+	return 0;
+}
+
+static int brcm_usb_phy_resume(struct device *dev)
+{
+	struct brcm_usb_common_init_params params;
+	struct brcm_usb_phy_data *priv = dev_get_drvdata(dev);
+
+	clk_enable(priv->usb_20_clk);
+	clk_enable(priv->usb_30_clk);
+	params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+	params.ioc = priv->ioc;
+	params.ipp = priv->ipp;
+	params.has_xhci = priv->has_xhci;
+	params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+	params.device_mode = priv->device_mode;
+	brcm_usb_common_init(&params);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops brcm_usb_phy_pm_ops = {
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(brcm_usb_phy_suspend, brcm_usb_phy_resume)
+};
+
+static const struct of_device_id brcm_usb_dt_ids[] = {
+	{ .compatible = "brcm,usb-phy" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, brcm_usb_dt_ids);
+
+static struct platform_driver brcm_usb_driver = {
+	.probe		= brcm_usb_phy_probe,
+	.driver		= {
+		.name	= "brcm-usb-phy",
+		.owner	= THIS_MODULE,
+		.pm = &brcm_usb_phy_pm_ops,
+		.of_match_table = brcm_usb_dt_ids,
+	},
+};
+
+module_platform_driver(brcm_usb_driver);
+
+MODULE_ALIAS("platform:brcm-usb-phy");
+MODULE_AUTHOR("Al Cooper <acooper@broadcom.com>");
+MODULE_DESCRIPTION("BRCM USB PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 6d452a78b19c..edc13633a775 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -12,6 +12,17 @@ config POWER_RESET_AS3722
 	help
 	  This driver supports turning off board via a ams AS3722 power-off.
 
+config POWER_RESET_BRCMSTB
+	bool "Broadcom STB reset driver"
+	select MFD_SYSCON
+	depends on POWER_RESET && ARCH_BRCMSTB
+	help
+	  This driver provides restart support for ARM-based Broadcom STB
+	  boards.
+
+	  Say Y here if you have an ARM-based Broadcom STB board and you wish
+	  to have restart support.
+
 config POWER_RESET_GPIO
 	bool "GPIO power-off driver"
 	depends on OF_GPIO && POWER_RESET
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index a5b4a77d1a41..72bb94f43f08 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
 obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
 obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o
+obj-$(CONFIG_POWER_RESET_BRCMSTB) += brcmstb-reboot.o
diff --git a/drivers/power/reset/brcmstb-reboot.c b/drivers/power/reset/brcmstb-reboot.c
new file mode 100644
index 000000000000..3f236924742a
--- /dev/null
+++ b/drivers/power/reset/brcmstb-reboot.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/system_misc.h>
+
+#define RESET_SOURCE_ENABLE_REG 1
+#define SW_MASTER_RESET_REG 2
+
+static struct regmap *regmap;
+static u32 rst_src_en;
+static u32 sw_mstr_rst;
+
+static void brcmstb_reboot(enum reboot_mode mode, const char *cmd)
+{
+	int rc;
+	u32 tmp;
+
+	rc = regmap_write(regmap, rst_src_en, 1);
+	if (rc) {
+		pr_err("failed to write rst_src_en (%d)\n", rc);
+		return;
+	}
+
+	rc = regmap_read(regmap, rst_src_en, &tmp);
+	if (rc) {
+		pr_err("failed to read rst_src_en (%d)\n", rc);
+		return;
+	}
+
+	rc = regmap_write(regmap, sw_mstr_rst, 1);
+	if (rc) {
+		pr_err("failed to write sw_mstr_rst (%d)\n", rc);
+		return;
+	}
+
+	rc = regmap_read(regmap, sw_mstr_rst, &tmp);
+	if (rc) {
+		pr_err("failed to read sw_mstr_rst (%d)\n", rc);
+		return;
+	}
+
+	while (1)
+		;
+}
+
+static int brcmstb_reboot_probe(struct platform_device *pdev)
+{
+	int rc;
+	struct device_node *np = pdev->dev.of_node;
+
+	regmap = syscon_regmap_lookup_by_phandle(np, "syscon");
+	if (IS_ERR(regmap)) {
+		pr_err("failed to get syscon phandle\n");
+		return -EINVAL;
+	}
+
+	rc = of_property_read_u32_index(np, "syscon", RESET_SOURCE_ENABLE_REG,
+					&rst_src_en);
+	if (rc) {
+		pr_err("can't get rst_src_en offset (%d)\n", rc);
+		return -EINVAL;
+	}
+
+	rc = of_property_read_u32_index(np, "syscon", SW_MASTER_RESET_REG,
+					&sw_mstr_rst);
+	if (rc) {
+		pr_err("can't get sw_mstr_rst offset (%d)\n", rc);
+		return -EINVAL;
+	}
+
+	arm_pm_restart = brcmstb_reboot;
+
+	return 0;
+}
+
+static const struct of_device_id of_match[] = {
+	{ .compatible = "brcm,brcmstb-reboot", },
+	{},
+};
+
+static struct platform_driver brcmstb_reboot_driver = {
+	.probe = brcmstb_reboot_probe,
+	.driver = {
+		.name = "brcmstb-reboot",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match,
+	},
+};
+
+static int __init brcmstb_reboot_init(void)
+{
+	return platform_driver_probe(&brcmstb_reboot_driver,
+					brcmstb_reboot_probe);
+}
+subsys_initcall(brcmstb_reboot_init);
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 22f2f2857b82..a41924fd92a0 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -71,6 +71,16 @@ config PWM_BFIN
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-bfin.
 
+config PWM_BRCMSTB
+	tristate "Broadcom STB PWM support"
+	depends on ARCH_BRCMSTB
+	help
+	  Generic PWM framework driver for the Broadcom Set-top-Box
+	  SoCs (BCM7xxx).
+
+	  To compile this driver as a module, choose M Here: the module
+	  will be called pwm-brcmstb.c.
+
 config PWM_EP93XX
 	tristate "Cirrus Logic EP93xx PWM support"
 	depends on ARCH_EP93XX
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index d8906ec69976..206149438817 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PWM_AB8500)	+= pwm-ab8500.o
 obj-$(CONFIG_PWM_ATMEL)		+= pwm-atmel.o
 obj-$(CONFIG_PWM_ATMEL_TCB)	+= pwm-atmel-tcb.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
+obj-$(CONFIG_PWM_BRCMSTB)	+= pwm-brcmstb.o
 obj-$(CONFIG_PWM_EP93XX)	+= pwm-ep93xx.o
 obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o
 obj-$(CONFIG_PWM_JZ4740)	+= pwm-jz4740.o
diff --git a/drivers/pwm/pwm-brcmstb.c b/drivers/pwm/pwm-brcmstb.c
new file mode 100644
index 000000000000..86ab6a5025a0
--- /dev/null
+++ b/drivers/pwm/pwm-brcmstb.c
@@ -0,0 +1,345 @@
+/*
+ * Broadcom BCM7038 PWM driver
+ * Author: Florian Fainelli
+ *
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+
+#include <linux/clk.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/spinlock.h>
+
+#define PWM_CTRL		0x00
+#define  CTRL_START		BIT(0)
+#define  CTRL_OEB		BIT(1)
+#define  CTRL_FORCE_HIGH	BIT(2)
+#define  CTRL_OPENDRAIN		BIT(3)
+#define  CTRL_CHAN_OFFS		4
+
+#define PWM_CTRL2		0x04
+#define  CTRL2_OUT_SELECT	BIT(0)
+
+#define PWM_CH_SIZE		0x8
+
+#define PWM_CWORD_MSB(ch)	(0x08 + ((ch) * PWM_CH_SIZE))
+#define PWM_CWORD_LSB(ch)	(0x0C + ((ch) * PWM_CH_SIZE))
+
+/* Number of bits for the CWORD value */
+#define CWORD_BIT_SIZE		16
+
+/*
+ * Maximum control word value allowed when variable-frequency PWM is used as a
+ * clock for the constant-frequency PMW.
+ */
+#define CONST_VAR_F_MAX		32768
+#define CONST_VAR_F_MIN		1
+
+#define PWM_ON(ch)		(0x18 + ((ch) * PWM_CH_SIZE))
+#define  PWM_ON_MIN		1
+#define PWM_PERIOD(ch)		(0x1C + ((ch) * PWM_CH_SIZE))
+#define  PWM_PERIOD_MIN		0
+
+#define PWM_ON_PERIOD_MAX	0xff
+
+struct brcmstb_pwm_dev {
+	void __iomem *base;
+	spinlock_t lock;
+	struct clk *clk;
+	struct pwm_chip chip;
+};
+
+static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm_dev *p, u32 off)
+{
+	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		return __raw_readl(p->base + off);
+	else
+		return readl_relaxed(p->base + off);
+}
+
+static inline void brcmstb_pwm_writel(struct brcmstb_pwm_dev *p,
+				      u32 val, u32 off)
+{
+	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		__raw_writel(val, p->base + off);
+	else
+		writel_relaxed(val, p->base + off);
+}
+
+static inline struct brcmstb_pwm_dev *to_brcmstb_pwm(struct pwm_chip *ch)
+{
+	return container_of(ch, struct brcmstb_pwm_dev, chip);
+}
+
+/*
+ * Fv is derived from the variable frequency output. The variable frequency
+ * output is configured using this formula:
+ *
+ * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
+ *
+ * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
+ *
+ * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
+ *
+ * The PWM core framework specifies that the "duty_ns" parameter is in fact the
+ * "on" time, so this translates directly into our HW programming here.
+ */
+static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+			      int duty_ns, int period_ns)
+{
+	struct brcmstb_pwm_dev *p = to_brcmstb_pwm(chip);
+	unsigned long pc, dc, cword = CONST_VAR_F_MAX;
+	unsigned int ch = pwm->hwpwm;
+	u64 val, rate;
+	u32 reg;
+
+	/*
+	 * If asking for a duty_ns equal to period_ns, we need to substract
+	 * the period value by 1 to make it shorter than the "on" time and
+	 * produce a flat 100% duty cycle signal, and max out the "on" time
+	 */
+	if (duty_ns == period_ns) {
+		dc = PWM_ON_PERIOD_MAX;
+		pc = PWM_ON_PERIOD_MAX - 1;
+		goto done;
+	}
+
+	while (1) {
+		/*
+		 * Calculate the base rate from base frequency and current
+		 * cword
+		 */
+		rate = (u64)clk_get_rate(p->clk) * (u64)cword;
+		do_div(rate, 1 << CWORD_BIT_SIZE);
+
+		val = period_ns * rate;
+		do_div(val, NSEC_PER_SEC);
+		pc = val;
+
+		val = (duty_ns + 1) * rate;
+		do_div(val, NSEC_PER_SEC);
+		dc = val;
+
+		/*
+		 * We can be called with separate duty and period updates,
+		 * so do not reject dc == 0 right away
+		 */
+		if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
+			return -EINVAL;
+
+		/* We converged on a calculation */
+		if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
+			break;
+
+		/*
+		 * The cword needs to be a power of 2 for the variable
+		 * frequency generator to output a 50% duty cycle variable
+		 * frequency which is used as input clock to the fixed
+		 * frequency generator.
+		 */
+		cword >>= 1;
+
+		/*
+		 * Desired periods are too large, we do not have a divider
+		 * for them
+		 */
+		if (cword < CONST_VAR_F_MIN)
+			return -EINVAL;
+	}
+
+done:
+	/*
+	 * Configure the defined "cword" value to have the variable frequency
+	 * generator output a base frequency for the constant frequency
+	 * generator to derive from.
+	 */
+	spin_lock(&p->lock);
+	brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(ch));
+	brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(ch));
+
+	/* Select constant frequency signal output */
+	reg = brcmstb_pwm_readl(p, PWM_CTRL2);
+	reg |= CTRL2_OUT_SELECT << (ch * CTRL_CHAN_OFFS);
+	brcmstb_pwm_writel(p, reg, PWM_CTRL2);
+
+	/* Configure on and period value */
+	brcmstb_pwm_writel(p, pc, PWM_PERIOD(ch));
+	brcmstb_pwm_writel(p, dc, PWM_ON(ch));
+	spin_unlock(&p->lock);
+
+	return 0;
+}
+
+static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm_dev *p,
+					  unsigned int ch, bool enable)
+{
+	unsigned int ofs = ch * CTRL_CHAN_OFFS;
+	u32 reg;
+
+	spin_lock(&p->lock);
+	reg = brcmstb_pwm_readl(p, PWM_CTRL);
+	if (enable) {
+		reg &= ~(CTRL_OEB << ofs);
+		reg |= (CTRL_START | CTRL_OPENDRAIN) << ofs;
+	} else {
+		reg &= ~((CTRL_START | CTRL_OPENDRAIN) << ofs);
+		reg |= CTRL_OEB << ofs;
+	}
+	brcmstb_pwm_writel(p, reg, PWM_CTRL);
+	spin_unlock(&p->lock);
+}
+
+static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct brcmstb_pwm_dev *p = to_brcmstb_pwm(chip);
+
+	brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
+
+	return 0;
+}
+
+static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct brcmstb_pwm_dev *p = to_brcmstb_pwm(chip);
+
+	brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
+}
+
+static const struct pwm_ops brcmstb_pwm_ops = {
+	.config	= brcmstb_pwm_config,
+	.enable	= brcmstb_pwm_enable,
+	.disable = brcmstb_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static const struct of_device_id brcmstb_pwm_of_match[] = {
+	{ .compatible = "brcm,bcm7038-pwm", },
+	{ /* sentinel */ }
+};
+
+static int brcmstb_pwm_probe(struct platform_device *pdev)
+{
+	struct brcmstb_pwm_dev *p;
+	struct resource *r;
+	int ret;
+
+	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return -ENOMEM;
+
+	spin_lock_init(&p->lock);
+
+	/*
+	 * Try to grab the clock and its rate, if not available, default
+	 * to the base 27Mhz clock domain this block comes from.
+	 */
+	p->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(p->clk)) {
+		dev_err(&pdev->dev, "fail to obtain clock\n");
+		return PTR_ERR(p->clk);
+	}
+
+	clk_prepare_enable(p->clk);
+
+	platform_set_drvdata(pdev, p);
+
+	p->chip.dev = &pdev->dev;
+	p->chip.ops = &brcmstb_pwm_ops;
+	/* Dynamically assign a PWM base */
+	p->chip.base = -1;
+	/* Static number of PWM channels for this controller */
+	p->chip.npwm = 2;
+	p->chip.can_sleep = true;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	p->base = devm_ioremap_resource(&pdev->dev, r);
+	if (!p->base) {
+		ret = -ENOMEM;
+		goto out_clk;
+	}
+
+	ret = pwmchip_add(&p->chip);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
+		goto out_clk;
+	}
+
+	return ret;
+
+out_clk:
+	clk_disable_unprepare(p->clk);
+	return ret;
+}
+
+static int brcmstb_pwm_remove(struct platform_device *pdev)
+{
+	struct brcmstb_pwm_dev *p = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = pwmchip_remove(&p->chip);
+	if (ret)
+		return ret;
+
+	clk_disable_unprepare(p->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_pwm_suspend(struct device *d)
+{
+	struct platform_device *pdev = to_platform_device(d);
+	struct brcmstb_pwm_dev *p = platform_get_drvdata(pdev);
+
+	clk_disable(p->clk);
+
+	return 0;
+}
+
+static int brcmstb_pwm_resume(struct device *d)
+{
+	struct platform_device *pdev = to_platform_device(d);
+	struct brcmstb_pwm_dev *p = platform_get_drvdata(pdev);
+
+	clk_enable(p->clk);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops,
+			 brcmstb_pwm_suspend, brcmstb_pwm_resume);
+
+static struct platform_driver brcmstb_pwm_driver = {
+	.probe	= brcmstb_pwm_probe,
+	.remove	= brcmstb_pwm_remove,
+	.driver	= {
+		.name = "pwm-brcmstb",
+		.of_match_table = brcmstb_pwm_of_match,
+		.pm = &brcmstb_pwm_pm_ops,
+	},
+};
+module_platform_driver(brcmstb_pwm_driver);
+
+MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
+MODULE_DESCRIPTION("Broadcom STB PWM driver");
+MODULE_ALIAS("platform:pwm-brcmstb");
+MODULE_LICENSE("GPL");
diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c
index e11ca1f7bef6..2e407d702974 100644
--- a/drivers/scsi/scsi_error.c
+++ b/drivers/scsi/scsi_error.c
@@ -521,12 +521,13 @@ static int scsi_check_sense(struct scsi_cmnd *scmd)
 		 */
 		if (scmd->device->expecting_cc_ua) {
 			/*
-			 * Because some device does not queue unit
+			 * Because some CDROM drives do not queue unit
 			 * attentions correctly, we carefully check
 			 * additional sense code and qualifier so as
 			 * not to squash media change unit attention.
 			 */
-			if (sshdr.asc != 0x28 || sshdr.ascq != 0x00) {
+			if ((sdev->type != TYPE_ROM) ||
+				(sshdr.asc != 0x28 || sshdr.ascq != 0x00)) {
 				scmd->device->expecting_cc_ua = 0;
 				return NEEDS_RETRY;
 			}
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
new file mode 100644
index 000000000000..74cc7dc549c7
--- /dev/null
+++ b/drivers/soc/Kconfig
@@ -0,0 +1,5 @@
+menu "SOC (System On Chip) specific Drivers"
+
+source "drivers/soc/brcmstb/Kconfig"
+
+endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
new file mode 100644
index 000000000000..9e057eaec64d
--- /dev/null
+++ b/drivers/soc/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Linux Kernel SOC specific device drivers.
+#
+
+obj-$(CONFIG_SOC_BRCMSTB)	+= brcmstb/
diff --git a/drivers/soc/brcmstb/Kconfig b/drivers/soc/brcmstb/Kconfig
new file mode 100644
index 000000000000..9d1149c653fc
--- /dev/null
+++ b/drivers/soc/brcmstb/Kconfig
@@ -0,0 +1,92 @@
+config SOC_BRCMSTB
+	bool
+
+menu "Broadcom STB SoC drivers"
+	depends on SOC_BRCMSTB
+
+config BRCMSTB_IRQ0_STUB
+	bool "Enable stub IRQ0 driver"
+	default y
+	depends on !BCM7120_L2_IRQ
+	help
+	  This enables the stub IRQ0 driver, for configuring the IRQ0
+	  forwarding mask to enable the UARTs, but not do anything else with
+	  the IRQ0 block. This driver is really a hack, and it exists solely
+	  because Nexus wants to share the IRQ0 registers without telling
+	  Linux.
+
+	  It is highly recommended to either enable this or BCM7120_L2_IRQ.
+
+config BRCMSTB_BMEM
+	bool "Enable BMEM reserved A/V memory"
+	depends on HAVE_MEMBLOCK && ARCH_BRCMSTB && BRCMSTB_MEMORY_API
+	help
+	  The A/V peripherals (managed by the PI/Nexus middleware) require
+	  large, contiguous memory regions to be set aside at boot time.  This
+	  option sets those up in a default config that reserves most of
+	  memory.  Also allows the user to manually define region sizes and
+	  locations using the 'bmem' command line param.  Allows for O_DIRECT
+	  I/O using these regions, mmap() from user programs, and
+	  ioremap() from kernel drivers.
+
+	  If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_CMA
+	bool "Broadcom STB CMA"
+	depends on ARCH_BRCMSTB && ARM && CMA && BRCMSTB_MEMORY_API
+	help
+	  This driver provides the ioctls for manipulating with the reserved
+	  areas used by Broadcom middleware, as well as the functions for the
+	  kernel interface.  It also provides register and reserve functions
+	  for setting up the CMA regions it uses at early boot.
+
+	  If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_MEMORY_API
+	bool "Enable BRCMSTB memory API"
+	depends on HAVE_MEMBLOCK && ARCH_BRCMSTB
+	select LIBFDT
+	help
+	  This provides information on how system memory is arranged so that
+	  Broadcom STB middleware can determine how to set up its memory heaps.
+
+	  If you are planning to use Broadcom middleware, choose Y here.
+
+config BRCMSTB_PM
+	bool "Support suspend/resume for STB platforms"
+	default y
+	depends on PM
+	depends on ARM && ARCH_BRCMSTB
+
+config BRCMSTB_PM_DEBUG
+	bool "Add debugfs interface for STB suspend/resume driver"
+	default y
+	depends on BRCMSTB_PM && PM_DEBUG && DEBUG_FS
+	help
+	  This option enables debugfs support for the STB suspend/resume
+	  driver. Specifically, for memory regions to be included or excluded
+	  from hashing.
+
+	  If you are unsure, choose Y here.
+
+config BRCMSTB_SRPD
+	tristate "Support enabling DDR self-refresh modes"
+	help
+	  Provides a sysfs interface for setting the self-refresh timeout
+	  value on Broadcom STB memory controllers.
+
+config BRCMSTB_WKTMR
+	depends on !DREAMBOX
+	tristate "Support wake-up timer"
+
+# Perform memory hashing before entering S3, using XPT DMA
+config BRCMSTB_XPT_HASH
+	bool
+
+config BRCMSTB_NEXUS_API
+	tristate "Support for Nexus APIs"
+	help
+	   Provides APIs for Nexus kernel-mode driver to facilitate
+	   sharing of resources: IRQs, GPIOs, Pinmuxing etc.
+
+endmenu
diff --git a/drivers/soc/brcmstb/Makefile b/drivers/soc/brcmstb/Makefile
new file mode 100644
index 000000000000..d59bb099578c
--- /dev/null
+++ b/drivers/soc/brcmstb/Makefile
@@ -0,0 +1,12 @@
+obj-$(CONFIG_BRCMSTB_PM)	+= pm/
+
+obj-y				+= common.o biuctrl.o
+obj-$(CONFIG_BRCMSTB_BMEM)	+= bmem.o
+obj-$(CONFIG_BRCMSTB_CMA)	+= cma_driver.o
+obj-$(CONFIG_BRCMSTB_IRQ0_STUB)	+= irq0-stub.o
+obj-$(CONFIG_BRCMSTB_MEMORY_API) += memory.o
+obj-$(CONFIG_BRCMSTB_SRPD)	+= srpd.o
+obj-$(CONFIG_BRCMSTB_WKTMR)	+= wktmr.o
+obj-$(CONFIG_BRCMSTB_NEXUS_API)	+= nexus/
+
+CFLAGS_memory.o += -I$(src)/../../../scripts/dtc/libfdt
diff --git a/drivers/soc/brcmstb/biuctrl.c b/drivers/soc/brcmstb/biuctrl.c
new file mode 100644
index 000000000000..d45b8071983b
--- /dev/null
+++ b/drivers/soc/brcmstb/biuctrl.c
@@ -0,0 +1,96 @@
+/*
+ * Broadcom STB SoCs Bus Unit Interface controls
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#define CPU_CREDIT_REG_OFFSET 0x184
+#define  CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
+
+static void __iomem *cpubiuctrl_base;
+static unsigned int mcp_wr_pairing_en;
+
+/*
+ * HW7445-1920: On affected chips, disable MCP write pairing to improve
+ * stability on long term stress test.
+ */
+static int __init mcp_write_pairing_set(void)
+{
+	u32 creds = 0;
+
+	if (!cpubiuctrl_base)
+		return -1;
+
+	creds = __raw_readl(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+	if (mcp_wr_pairing_en) {
+		pr_info("MCP: Enabling write pairing\n");
+		__raw_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
+			     cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+	} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
+		pr_info("MCP: Disabling write pairing\n");
+		__raw_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
+				cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+	} else {
+		pr_info("MCP: Write pairing already disabled\n");
+	}
+
+	return 0;
+}
+
+static void __init setup_hifcpubiuctrl_regs(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+	if (!np)
+		pr_err("missing BIU control node\n");
+
+	cpubiuctrl_base = of_iomap(np, 0);
+	if (!cpubiuctrl_base)
+		pr_err("failed to remap BIU control base\n");
+
+	mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
+
+	of_node_put(np);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static u32 cpu_credit_reg_dump;  /* for save/restore */
+
+static int brcmstb_cpu_credit_reg_suspend(void)
+{
+	if (cpubiuctrl_base)
+		cpu_credit_reg_dump =
+			__raw_readl(cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+	return 0;
+}
+
+static void brcmstb_cpu_credit_reg_resume(void)
+{
+	if (cpubiuctrl_base)
+		__raw_writel(cpu_credit_reg_dump,
+				cpubiuctrl_base + CPU_CREDIT_REG_OFFSET);
+}
+
+static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
+	.suspend = brcmstb_cpu_credit_reg_suspend,
+	.resume = brcmstb_cpu_credit_reg_resume,
+};
+#endif
+
+
+void __init brcmstb_biuctrl_init(void)
+{
+	setup_hifcpubiuctrl_regs();
+	if (mcp_write_pairing_set())
+		pr_err("MCP: Unable to disable write pairing!\n");
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
+#endif
+}
diff --git a/drivers/soc/brcmstb/bmem.c b/drivers/soc/brcmstb/bmem.c
new file mode 100644
index 000000000000..45df1c27a014
--- /dev/null
+++ b/drivers/soc/brcmstb/bmem.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#define pr_fmt(fmt) "bmem: " fmt
+
+#include <asm/setup.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/memblock.h>
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/brcmstb/bmem.h>
+#include <linux/brcmstb/memory_api.h>
+
+#if 0
+#define DBG pr_info
+#else
+#define DBG(...) /* */
+#endif
+
+#define MAX_BMEM_REGIONS	8
+
+struct bmem_region {
+	phys_addr_t		addr;
+	phys_addr_t		size;
+	bool			valid;
+};
+
+static struct bmem_region bmem_regions[MAX_BMEM_REGIONS];
+static struct platform_device *brcmstb_pdev;
+static unsigned int n_bmem_regions;
+static bool bmem_disabled;
+
+/***********************************************************************
+ * BMEM (reserved A/V buffer memory) support
+ ***********************************************************************/
+
+static int __init __bmem_setup(phys_addr_t addr, phys_addr_t size)
+{
+	if (n_bmem_regions == MAX_BMEM_REGIONS) {
+		pr_warn_once("too many regions, ignoring extras\n");
+		return -E2BIG;
+	}
+
+	bmem_regions[n_bmem_regions].addr = addr;
+	bmem_regions[n_bmem_regions].size = size;
+	n_bmem_regions++;
+	return 0;
+}
+
+/*
+ * Parses command line for bmem= options
+ */
+static int __init bmem_setup(char *str)
+{
+	phys_addr_t addr = 0, size;
+	char *orig_str = str;
+	int ret;
+
+	size = memparse(str, &str);
+	if (*str == '@')
+		addr = memparse(str + 1, &str);
+
+	if ((addr & ~PAGE_MASK) || (size & ~PAGE_MASK)) {
+		pr_warn("ignoring invalid range '%s' (is it missing an 'M' suffix?)\n",
+				orig_str);
+		return 0;
+	}
+
+	if (size == 0) {
+		pr_info("disabling reserved memory\n");
+		bmem_disabled = true;
+		return 0;
+	}
+
+	ret = __bmem_setup(addr, size);
+	if (!ret)
+		brcmstb_memory_override_defaults = true;
+	return ret;
+}
+early_param("bmem", bmem_setup);
+
+/*
+ * Returns index if the supplied range falls entirely within a bmem region
+ */
+int bmem_find_region(phys_addr_t addr, phys_addr_t size)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if ((addr >= bmem_regions[i].addr) &&
+		    ((addr + size) <=
+			(bmem_regions[i].addr + bmem_regions[i].size))) {
+			return idx;
+		}
+		idx++;
+	}
+	return -ENOENT;
+}
+
+/*
+ * Finds the IDX'th valid bmem region, and fills in addr/size if it exists.
+ * Returns 0 on success, <0 on failure.
+ * Can pass in NULL for addr and/or size if you only care about return value.
+ */
+int bmem_region_info(int idx, phys_addr_t *addr, phys_addr_t *size)
+{
+	int i;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		if (!bmem_regions[i].valid)
+			continue;
+		if (!idx) {
+			if (addr)
+				*addr = bmem_regions[i].addr;
+			if (size)
+				*size = bmem_regions[i].size;
+			return 0;
+		}
+		idx--;
+	}
+	return -ENOENT;
+}
+EXPORT_SYMBOL(bmem_region_info);
+
+static void __init bmem_setup_defaults(void)
+{
+	int iter;
+
+	for_each_bank(iter, &meminfo) {
+		phys_addr_t start, size;
+
+		if (n_bmem_regions == MAX_BMEM_REGIONS) {
+			pr_warn_once("%s: too many regions, ignoring extras\n",
+					__func__);
+			return;
+		}
+
+		/* fill in start and size */
+		if (brcmstb_memory_get_default_reserve(iter, &start, &size))
+			continue;
+
+		__bmem_setup(start, size);
+	}
+}
+
+void __init bmem_reserve(void)
+{
+	int i;
+	int ret;
+
+	if (bmem_disabled) {
+		n_bmem_regions = 0;
+		return;
+	}
+
+	if (brcmstb_default_reserve == BRCMSTB_RESERVE_BMEM &&
+			!n_bmem_regions &&
+			!brcmstb_memory_override_defaults)
+		bmem_setup_defaults();
+
+	for (i = 0; i < n_bmem_regions; ++i) {
+		ret = memblock_reserve(bmem_regions[i].addr,
+				bmem_regions[i].size);
+		if (ret) {
+			pr_err("memblock_reserve(%pa, %pa) failed: %d\n",
+					&bmem_regions[i].addr,
+					&bmem_regions[i].size, ret);
+		} else {
+			bmem_regions[i].valid = true;
+			pr_info("Reserved %lu MiB at %pa\n",
+				(unsigned long) bmem_regions[i].size / SZ_1M,
+				&bmem_regions[i].addr);
+
+			/*
+			 * Reserve the PAGE_SIZE memory preceeding each
+			 * BMEM region so it's unusable by the kernel.
+			 * This is to workaround a bug in the USB hardware
+			 * that may pre-fetch beyond the end of a DMA buffer
+			 * and read into BMEM and cause MRC errors.
+			 * See: SWLINUX-3996.
+			 */
+			memblock_reserve(bmem_regions[i].addr - PAGE_SIZE,
+					PAGE_SIZE);
+		}
+	}
+}
+
+/*
+ * Create /proc/iomem entries for bmem
+ */
+static int __init bmem_region_setup(void)
+{
+	int i, idx = 0;
+
+	for (i = 0; i < n_bmem_regions; i++) {
+		struct resource *r;
+		char *name;
+
+		if (!bmem_regions[i].valid)
+			continue;
+
+		r = kzalloc(sizeof(*r), GFP_KERNEL);
+		name = kzalloc(16, GFP_KERNEL);
+		if (!r || !name)
+			break;
+
+		sprintf(name, "bmem.%d", idx);
+		r->start = bmem_regions[i].addr;
+		r->end = bmem_regions[i].addr + bmem_regions[i].size - 1;
+		r->flags = IORESOURCE_MEM;
+		r->name = name;
+
+		insert_resource(&iomem_resource, r);
+		idx++;
+	}
+	return 0;
+}
+arch_initcall(bmem_region_setup);
+
+static ssize_t show_bmem(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	unsigned long idx = 0;
+	phys_addr_t addr = 0, size = 0;
+	const char *name = attr->attr.name;
+	int ret;
+
+	while (*name != 0) {
+		if (isdigit(*name)) {
+			ret = kstrtoul(name, 10, &idx);
+			if (ret)
+				return ret;
+			break;
+		}
+		name++;
+	}
+	bmem_region_info(idx, &addr, &size);
+
+	return snprintf(buf, PAGE_SIZE, "%pa %pa\n", &addr, &size);
+}
+
+static int __init brcm_pdev_init(void)
+{
+	struct device *dev;
+	int i;
+
+	brcmstb_pdev = platform_device_alloc("brcmstb", -1);
+	if (brcmstb_pdev == NULL) {
+		pr_err("%s: can't allocate device\n", __func__);
+		return -ENODEV;
+	}
+	platform_device_add(brcmstb_pdev);
+	dev = &brcmstb_pdev->dev;
+
+	/* create an attribute for each bmem region */
+	for (i = 0; ; i++) {
+		phys_addr_t addr, size;
+		struct device_attribute *attr;
+		char *name;
+
+		if (bmem_region_info(i, &addr, &size) < 0)
+			break;
+		attr = kzalloc(sizeof(*attr), GFP_KERNEL);
+		if (attr == NULL)
+			break;
+
+		name = kzalloc(16, GFP_KERNEL);
+		if (name == NULL)
+			break;
+		snprintf(name, 16, "bmem.%d", i);
+
+		sysfs_attr_init(&attr->attr);
+		attr->attr.name = name;
+		attr->attr.mode = 0444;
+		attr->show = show_bmem;
+
+		if (device_create_file(dev, attr) != 0)
+			WARN(1, "Can't create sysfs file\n");
+	}
+
+	return 0;
+}
+arch_initcall(brcm_pdev_init);
diff --git a/drivers/soc/brcmstb/cma_driver.c b/drivers/soc/brcmstb/cma_driver.c
new file mode 100644
index 000000000000..b006f0e8b36a
--- /dev/null
+++ b/drivers/soc/brcmstb/cma_driver.c
@@ -0,0 +1,918 @@
+/*
+ *  cma_driver.c - Broadcom STB platform CMA driver
+ *
+ *  Copyright © 2009 - 2015 Broadcom Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  A copy of the GPL is available at
+ *  http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ *  Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#define pr_fmt(fmt) "cma_driver: " fmt
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/cdev.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/brcmstb/cma_driver.h>
+#include <linux/brcmstb/memory_api.h>
+#include <linux/mmzone.h>
+#include <linux/memblock.h>
+#include <linux/device.h>
+#include <linux/bitmap.h>
+#include <linux/highmem.h>
+#include <linux/dma-contiguous.h>
+#include <linux/cma.h>
+#include <linux/sizes.h>
+#include <linux/vme.h>
+#include <asm/div64.h>
+#include <asm/setup.h>
+
+struct cma_devs_list {
+	struct list_head list;
+	struct cma_dev *cma_dev;
+};
+
+struct cma_root_dev {
+	u32 mmap_type;
+	struct cdev cdev;
+	struct device *dev;
+	struct cma_devs_list cma_devs;
+};
+
+struct cma_pdev_data {
+	phys_addr_t start;
+	phys_addr_t size;
+	int do_prealloc;
+	struct cma *cma_area;
+};
+
+struct cma_region_rsv_data {
+	int nr_regions_valid;
+	struct cma_pdev_data regions[NR_BANKS];
+	long long unsigned prm_low_lim_mb;
+	int prm_low_kern_rsv_pct;
+};
+
+struct cma_rsv_region {
+	phys_addr_t addr;
+	phys_addr_t size;
+};
+
+static struct cma_rsv_region cma_rsv_setup_data[MAX_CMA_AREAS];
+static unsigned int n_cma_regions;
+static bool cma_disabled;
+
+/* CMA region reservation */
+
+static struct cma_region_rsv_data cma_data __initdata = {
+	.prm_low_lim_mb = 32 << 20,
+	.prm_low_kern_rsv_pct = 20,
+};
+
+enum scan_bitmap_op {
+	GET_NUM_REGIONS = 0,
+	GET_REGION_INFO,
+};
+
+/*
+ * The lowest low-memory memblock size needed in order to reserve a cma region
+ * on systems with no high-memory.
+ */
+static int __init cma_mb_low_lim_set(char *p)
+{
+	cma_data.prm_low_lim_mb = memparse(p, NULL);
+	return !cma_data.prm_low_lim_mb ? -EINVAL : 0;
+}
+early_param("brcm_cma_mb_low_lim", cma_mb_low_lim_set);
+
+/*
+ * The percentage of memory reserved for the kernel on systems with no
+ * high-memory.
+ */
+static int __init cma_low_kern_rsv_pct_set(char *p)
+{
+	return (get_option(&p, &cma_data.prm_low_kern_rsv_pct) == 0) ?
+		-EINVAL : 0;
+}
+early_param("brcm_cma_low_kern_rsv_pct", cma_low_kern_rsv_pct_set);
+
+static int __init __cma_rsv_setup(phys_addr_t addr, phys_addr_t size)
+{
+	if (n_cma_regions == MAX_CMA_AREAS) {
+		pr_warn_once("%s: too many regions, ignoring extras\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	cma_rsv_setup_data[n_cma_regions].addr = addr;
+	cma_rsv_setup_data[n_cma_regions].size = size;
+	n_cma_regions++;
+	return 0;
+}
+
+/*
+ * We don't do too much checking here because it will be handled by the CMA
+ * reservation code
+ */
+static int __init cma_rsv_setup(char *str)
+{
+	phys_addr_t addr = 0;
+	phys_addr_t size = 0;
+	int ret;
+
+	size = (phys_addr_t) memparse(str, &str);
+	if (*str == '@')
+		addr = (phys_addr_t)memparse(str + 1, &str);
+
+	if (size == 0) {
+		pr_info("disabling reserved memory\n");
+		cma_disabled = true;
+		return 0;
+	}
+
+	ret = __cma_rsv_setup(addr, size);
+	if (!ret)
+		brcmstb_memory_override_defaults = true;
+	return ret;
+}
+early_param("brcm_cma", cma_rsv_setup);
+
+static void __init cma_reserve_one(struct membank *bank, int region_idx)
+{
+	struct cma_rsv_region *region = &cma_rsv_setup_data[region_idx];
+	struct cma *tmp_cma_area;
+	phys_addr_t base;
+	phys_addr_t size;
+	int rc;
+
+	if ((bank->start <= region->addr) &&
+			((bank->start + bank->size) >=
+			 (region->addr + region->size))) {
+		base = region->addr;
+		size = region->size;
+		pr_debug("reserve: %pa, %pa\n", &base, &size);
+		rc = dma_contiguous_reserve_area(size, base, 0,
+				&tmp_cma_area, 1);
+		if (rc) {
+			pr_err("reservation failed (base=%pa,size=%pa,rc=%d)\n",
+					&base, &size, rc);
+			/*
+			 * This will help us see if a stray memory reservation
+			 * is fragmenting the memblock when 'debug' is passed
+			 * to the kernel at boot.
+			 */
+			memblock_dump_all();
+		} else {
+			struct cma_pdev_data *pd =
+				&cma_data.regions[cma_data.nr_regions_valid];
+			pd->start = PFN_PHYS(tmp_cma_area->base_pfn);
+			pd->size = size;
+			/* Pre-allocate all regions */
+			pd->do_prealloc = 1;
+			pd->cma_area = tmp_cma_area;
+			cma_data.nr_regions_valid++;
+		}
+	}
+}
+
+void __init cma_setup_defaults(void)
+{
+	int iter;
+
+	for_each_bank(iter, &meminfo) {
+		phys_addr_t start, size;
+
+		/* fill in start and size */
+		if (brcmstb_memory_get_default_reserve(iter, &start, &size))
+			continue;
+
+		(void) __cma_rsv_setup(start, size);
+	}
+}
+
+void __init cma_reserve(void)
+{
+	int iter;
+
+	if (cma_disabled) {
+		n_cma_regions = 0;
+		return;
+	}
+
+	if (brcmstb_default_reserve == BRCMSTB_RESERVE_CMA &&
+			!n_cma_regions &&
+			!brcmstb_memory_override_defaults)
+		cma_setup_defaults();
+
+	for_each_bank(iter, &meminfo) {
+		int i;
+
+		for (i = 0; i < n_cma_regions; ++i)
+			cma_reserve_one(&meminfo.bank[iter], i);
+	}
+}
+
+static struct platform_device * __init cma_register_dev_one(int id,
+	int region_idx)
+{
+	struct platform_device *pdev;
+
+	pdev = platform_device_register_data(NULL, "brcm-cma", id,
+		&cma_data.regions[region_idx], sizeof(struct cma_pdev_data));
+	if (!pdev) {
+		pr_err("couldn't register pdev for %d,0x%pa,0x%pa\n", id,
+			&cma_data.regions[region_idx].start,
+			&cma_data.regions[region_idx].size);
+	}
+
+	return pdev;
+}
+
+/*
+ * Registers platform devices for the regions that were reserved in earlyboot.
+ *
+ * This function should be called from machine initialization.
+ */
+void __init cma_register(void)
+{
+	int i;
+	int id = 0;
+	struct platform_device *pdev;
+
+	for (i = 0; i < cma_data.nr_regions_valid; i++) {
+		pdev = cma_register_dev_one(id, i);
+		if (!pdev) {
+			pr_err("couldn't register device");
+			continue;
+		}
+
+		id++;
+	}
+}
+
+/* CMA driver implementation */
+
+/* Mutex for serializing accesses to private variables */
+static DEFINE_SPINLOCK(cma_dev_lock);
+static dev_t cma_dev_devno;
+static struct class *cma_dev_class;
+static struct cma_root_dev *cma_root_dev;
+
+static int cma_dev_open(struct inode *inode, struct file *filp)
+{
+	dev_dbg(cma_root_dev->dev, "opened cma root device\n");
+	return 0;
+}
+
+static int cma_dev_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static void cma_dev_vma_open(struct vm_area_struct *vma)
+{
+	dev_dbg(cma_root_dev->dev, "%s: VA=0x%lx PA=0x%lx\n", __func__,
+		vma->vm_start, vma->vm_pgoff << PAGE_SHIFT);
+}
+
+static void cma_dev_vma_close(struct vm_area_struct *vma)
+{
+	dev_dbg(cma_root_dev->dev, "%s: VA=0x%lx PA=0x%lx\n", __func__,
+		vma->vm_start, vma->vm_pgoff << PAGE_SHIFT);
+}
+
+static struct vm_operations_struct cma_dev_vm_ops = {
+	.open  = cma_dev_vma_open,
+	.close = cma_dev_vma_close,
+};
+
+static int cma_dev_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	switch (cma_root_dev->mmap_type) {
+	case MMAP_TYPE_NORMAL:
+		break;
+	case MMAP_TYPE_UNCACHED:
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+		break;
+	case MMAP_TYPE_WC:
+#if defined(__arm__)
+		/*
+		 * ARM has an explicit setting for WC. Use default for other
+		 * architectures.
+		 */
+		vma->vm_page_prot = __pgprot_modify(vma->vm_page_prot,
+				    L_PTE_MT_MASK, L_PTE_MT_DEV_WC);
+#endif
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			    vma->vm_end - vma->vm_start,
+			    vma->vm_page_prot)) {
+		return -EAGAIN;
+	} else {
+		vma->vm_ops = &cma_dev_vm_ops;
+		cma_dev_vma_open(vma);
+	}
+
+	return 0;
+}
+
+/**
+ * cma_dev_get_cma_dev() - Get a cma_dev * by memc index
+ *
+ * @memc: The MEMC index
+ *
+ * Return: a pointer to the associated CMA device, or NULL if no such
+ * device.
+ */
+struct cma_dev *cma_dev_get_cma_dev(int memc)
+{
+	struct list_head *pos;
+	struct cma_dev *cma_dev = NULL;
+	unsigned long flags;
+
+	if (!cma_root_dev)
+		return NULL;
+
+	spin_lock_irqsave(&cma_dev_lock, flags);
+
+	list_for_each(pos, &cma_root_dev->cma_devs.list) {
+		struct cma_dev *curr_cma_dev;
+		curr_cma_dev = list_entry(pos, struct cma_dev, list);
+		BUG_ON(curr_cma_dev == NULL);
+		if (curr_cma_dev->cma_dev_index == memc) {
+			cma_dev = curr_cma_dev;
+			break;
+		}
+	}
+
+	spin_unlock_irqrestore(&cma_dev_lock, flags);
+
+	dev_dbg(cma_root_dev->dev, "cma_dev index %d not in list\n", memc);
+	return cma_dev;
+}
+EXPORT_SYMBOL(cma_dev_get_cma_dev);
+
+/**
+ * cma_dev_get_mem() - Carve out physical memory
+ *
+ * @cma_dev: The CMA device
+ * @addr: Out pointer which will be populated with the start
+ * physical address of the contiguous region that was carved out
+ * @len: Number of bytes to allocate
+ * @align: Byte alignment
+ *
+ * Return: 0 on success, negative on failure.
+ */
+int cma_dev_get_mem(struct cma_dev *cma_dev, u64 *addr, u32 len,
+			u32 align)
+{
+	int status = 0;
+	struct page *page;
+	struct device *dev = cma_dev->dev;
+
+	if ((len & ~PAGE_MASK) || (len == 0)) {
+		dev_dbg(dev, "bad length (0x%x)\n", len);
+		status = -EINVAL;
+		goto done;
+	}
+
+	if (align & ~PAGE_MASK) {
+		dev_dbg(dev, "bad alignment (0x%x)\n", align);
+		status = -EINVAL;
+		goto done;
+	}
+
+	if (align <= PAGE_SIZE)
+		page = dma_alloc_from_contiguous(dev, len >> PAGE_SHIFT, 0);
+	else
+		page = dma_alloc_from_contiguous(dev, len >> PAGE_SHIFT,
+				get_order(align));
+
+	if (page == NULL) {
+		status = -ENOMEM;
+		goto done;
+	}
+
+	*addr = page_to_phys(page);
+
+done:
+	return status;
+}
+EXPORT_SYMBOL(cma_dev_get_mem);
+
+/**
+ * cma_dev_put_mem() - Return carved out physical memory
+ *
+ * @cma_dev: The CMA device
+ * @addr: Start physical address of allocated region
+ * @len: Number of bytes that were allocated (this must match with get_mem
+ * call!)
+ *
+ * Return: 0 on success, negative on failure.
+ */
+int cma_dev_put_mem(struct cma_dev *cma_dev, u64 addr, u32 len)
+{
+	struct page *page = phys_to_page(addr);
+	struct device *dev = cma_dev->dev;
+
+	if (page == NULL) {
+		dev_dbg(cma_root_dev->dev, "bad addr (0x%llx)\n", addr);
+		return -EINVAL;
+	}
+
+	if (len % PAGE_SIZE) {
+		dev_dbg(cma_root_dev->dev, "bad length (0x%x)\n", len);
+		return -EINVAL;
+	}
+
+	if (!dma_release_from_contiguous(dev, page, len / PAGE_SIZE))
+		return -EIO;
+
+	return 0;
+}
+EXPORT_SYMBOL(cma_dev_put_mem);
+
+static int scan_alloc_bitmap(struct cma_dev *cma_dev, int op, int *region_count,
+			     int region_num, s32 *memc, u64 *addr,
+			     u32 *num_bytes)
+{
+	/* Get information about n-th contiguous chunk */
+	unsigned long i = 0, pos_head = 0, pos_tail;
+	int count = 0, head_found = 0;
+	struct cma *cma = dev_get_cma_area(cma_dev->dev);
+
+	if (!cma)
+		return -EFAULT;
+
+	/* Count the number of contiguous chunks */
+	do {
+		if (head_found) {
+			pos_tail = find_next_zero_bit(cma->bitmap, cma->count,
+						      i);
+
+			if (op == GET_NUM_REGIONS)
+				count++;
+			else if (op == GET_REGION_INFO) {
+				if (count == region_num) {
+					*memc = (s32)cma_dev->memc;
+					*addr = cma_dev->range.base +
+						(pos_head * PAGE_SIZE);
+					*num_bytes = (pos_tail - pos_head) *
+						PAGE_SIZE;
+					return 0;
+				} else
+					count++;
+			}
+
+			head_found = 0;
+			i = pos_tail + 1;
+
+		} else {
+			pos_head = find_next_bit(cma->bitmap, cma->count, i);
+			i = pos_head + 1;
+			head_found = 1;
+		}
+	} while (i < cma->count);
+
+	if (op == GET_NUM_REGIONS) {
+		*region_count = count;
+		return 0;
+	} else
+		return -EINVAL;
+}
+
+/**
+ * cma_dev_get_num_regions() - Get number of allocated regions
+ *
+ * @cma_dev: The CMA device
+ *
+ * Return: 0 on success, negative on failure
+ */
+int cma_dev_get_num_regions(struct cma_dev *cma_dev)
+{
+	int count;
+	int rc = scan_alloc_bitmap(cma_dev, GET_NUM_REGIONS, &count, 0, NULL,
+				   NULL, NULL);
+	return rc ? rc : count;
+}
+EXPORT_SYMBOL(cma_dev_get_num_regions);
+
+/**
+ * cma_dev_get_region_info() - Get information about allocate region
+ *
+ * @cma_dev: The CMA device
+ * @region_num: Region index
+ * @memc: MEMC index associated with the region
+ * @addr: Physical address of region
+ * @num_bytes: Size of region in bytes
+ *
+ * Return: 0 on success, negative on failure.
+ */
+int cma_dev_get_region_info(struct cma_dev *cma_dev, int region_num,
+			    s32 *memc, u64 *addr, u32 *num_bytes)
+{
+	int rc = scan_alloc_bitmap(cma_dev, GET_REGION_INFO, NULL, region_num,
+				   memc, addr, num_bytes);
+	return rc;
+}
+EXPORT_SYMBOL(cma_dev_get_region_info);
+
+static int cma_dev_ioctl_check_cmd(unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+
+	if (_IOC_TYPE(cmd) != CMA_DEV_MAGIC)
+		return -ENOTTY;
+
+	if (_IOC_NR(cmd) > CMA_DEV_IOC_MAXNR)
+		return -ENOTTY;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		ret = !access_ok(VERIFY_WRITE, (void __user *)arg,
+				 _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		ret = !access_ok(VERIFY_READ, (void __user *)arg,
+				 _IOC_SIZE(cmd));
+
+	if (ret)
+		return -EFAULT;
+
+	return 0;
+}
+
+static long cma_dev_ioctl(struct file *filp, unsigned int cmd,
+			  unsigned long arg)
+{
+	int ret = 0;
+	struct device *dev = cma_root_dev->dev;
+	struct cma_dev *cma_dev;
+	struct ioc_params p;
+
+	ret = cma_dev_ioctl_check_cmd(cmd, arg);
+	if (ret)
+		return ret;
+
+	if (cmd < CMA_DEV_IOC_GET_PG_PROT) {
+		if (copy_from_user(&p, (void __user *)(arg), sizeof(p)))
+			return -EFAULT;
+	}
+
+	switch (cmd) {
+	case CMA_DEV_IOC_GETMEM: {
+		ret = -EINVAL;
+
+		cma_dev = cma_dev_get_cma_dev(p.cma_dev_index);
+		if (cma_dev == NULL)
+			break;
+
+		p.status = cma_dev_get_mem(cma_dev, &p.addr, p.num_bytes,
+						p.align_bytes);
+
+		ret = 0;
+
+		break;
+	}
+	case CMA_DEV_IOC_PUTMEM: {
+		ret = -EINVAL;
+
+		cma_dev = cma_dev_get_cma_dev(p.cma_dev_index);
+		if (cma_dev == NULL)
+			break;
+
+		p.status = cma_dev_put_mem(cma_dev, p.addr, p.num_bytes);
+
+		ret = 0;
+
+		break;
+	}
+	case CMA_DEV_IOC_GETPHYSINFO: {
+		ret = -EINVAL;
+
+		cma_dev = cma_dev_get_cma_dev(p.cma_dev_index);
+		if (cma_dev == NULL)
+			break;
+
+		p.addr = cma_dev->range.base;
+		p.num_bytes = cma_dev->range.size;
+		p.memc = (s32)cma_dev->memc;
+		p.status = 0;
+
+		ret = 0;
+
+		break;
+	}
+	case CMA_DEV_IOC_GETNUMREGS: {
+		ret = -EINVAL;
+
+		cma_dev = cma_dev_get_cma_dev(p.cma_dev_index);
+		if (cma_dev == NULL)
+			break;
+
+		p.num_regions = cma_dev_get_num_regions(cma_dev);
+
+		ret = 0;
+
+		break;
+	}
+	case CMA_DEV_IOC_GETREGINFO: {
+		ret = -EINVAL;
+
+		cma_dev = cma_dev_get_cma_dev(p.cma_dev_index);
+		if (cma_dev == NULL)
+			break;
+
+		p.status = cma_dev_get_region_info(cma_dev, p.region, &p.memc,
+							&p.addr, &p.num_bytes);
+
+		ret = 0;
+
+		break;
+	}
+	case CMA_DEV_IOC_GET_PG_PROT: {
+		__put_user(cma_root_dev->mmap_type, (u32 __user *)arg);
+		break;
+	}
+	case CMA_DEV_IOC_SET_PG_PROT: {
+		int mmap_type;
+
+		__get_user(mmap_type, (u32 __user *)arg);
+
+		if (mmap_type > MMAP_TYPE_WC) {
+			dev_err(dev, "bad mmap_type (%d)\n", mmap_type);
+			ret = -EINVAL;
+		} else
+			cma_root_dev->mmap_type = mmap_type;
+
+		break;
+	}
+	case CMA_DEV_IOC_VERSION: {
+		__put_user(CMA_DRIVER_VERSION, (__u32 __user *)arg);
+		break;
+	}
+	default: {
+		return -ENOTTY;
+	}
+	}
+
+	if (cmd < CMA_DEV_IOC_GET_PG_PROT) {
+		if (copy_to_user((void __user *)(arg), &p, sizeof(p)))
+			return -EFAULT;
+	}
+
+	return ret;
+}
+
+static const struct file_operations cma_dev_fops = {
+	.owner          = THIS_MODULE,
+	.open           = cma_dev_open,
+	.release        = cma_dev_release,
+	.mmap           = cma_dev_mmap,
+	.unlocked_ioctl = cma_dev_ioctl,
+};
+
+static int cma_drvr_alloc_devno(struct device *dev)
+{
+	int ret = 0;
+
+	if (MAJOR(cma_dev_devno) == 0) {
+		ret = alloc_chrdev_region(&cma_dev_devno, 0, CMA_DEV_MAX,
+					  CMA_DEV_NAME);
+	}
+
+	if (ret) {
+		dev_err(dev, "couldn't alloc major devno\n");
+		return ret;
+	}
+
+	dev_dbg(dev, "maj=%d min=%d\n", MAJOR(cma_dev_devno),
+	MINOR(cma_dev_devno));
+
+	return ret;
+}
+
+static int cma_drvr_test_cma_dev(struct device *dev)
+{
+	struct page *page;
+
+	/* Do a dummy alloc to ensure the CMA device is truly ready */
+	page = dma_alloc_from_contiguous(dev, 1, 0);
+	if (page == NULL)
+		return -EINVAL;
+
+	if (!dma_release_from_contiguous(dev, page, 1)) {
+		dev_err(dev, "test dma release failed!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int __init cma_drvr_config_platdev(struct platform_device *pdev,
+					struct cma_dev *cma_dev)
+{
+	struct device *dev = &pdev->dev;
+	struct cma_pdev_data *data =
+		(struct cma_pdev_data *)dev->platform_data;
+
+	if (!data) {
+		dev_err(dev, "platform data not initialized\n");
+		return -EINVAL;
+	}
+
+	cma_dev->range.base = data->start;
+	cma_dev->range.size = data->size;
+	cma_dev->cma_dev_index = pdev->id;
+	cma_dev->memc = brcmstb_memory_phys_addr_to_memc(data->start);
+
+	if (!data->cma_area) {
+		pr_err("null cma area\n");
+		return -EINVAL;
+	}
+	dev_set_cma_area(dev, data->cma_area);
+
+	if (cma_drvr_test_cma_dev(dev)) {
+		dev_err(dev, "CMA testing failed!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int cma_drvr_init_root_dev(struct device *dev)
+{
+	int ret;
+	struct device *dev2;
+	struct cma_root_dev *my_cma_root_dev;
+	struct cdev *cdev;
+	int minor = 0;
+
+	my_cma_root_dev = devm_kzalloc(dev, sizeof(*my_cma_root_dev),
+					GFP_KERNEL);
+	if (my_cma_root_dev == NULL)
+		return -ENOMEM;
+
+	/* Initialize list of CMA devices referenced by the root CMA device */
+	INIT_LIST_HEAD(&my_cma_root_dev->cma_devs.list);
+
+	/* Setup character device */
+	cdev = &my_cma_root_dev->cdev;
+	cdev_init(cdev, &cma_dev_fops);
+	cdev->owner = THIS_MODULE;
+	ret = cdev_add(cdev, cma_dev_devno + minor, 1);
+	if (ret) {
+		dev_err(dev, "cdev_add() failed (%d)\n", ret);
+		goto free_cma_root_dev;
+	}
+
+	if (cma_dev_class == NULL)
+		cma_dev_class = class_create(THIS_MODULE, CMA_CLASS_NAME);
+
+	/* Setup device */
+	dev2 = device_create(cma_dev_class, dev, cma_dev_devno + minor, NULL,
+			     CMA_DEV_NAME"%d", minor);
+	if (IS_ERR(dev2)) {
+		dev_err(dev, "error creating device (%d)\n", ret);
+		ret = PTR_ERR(dev2);
+		goto del_cdev;
+	}
+
+	my_cma_root_dev->dev = dev2;
+	cma_root_dev = my_cma_root_dev;
+
+	dev_info(dev, "Initialized Broadcom CMA root device\n");
+
+	goto done;
+
+del_cdev:
+	cdev_del(cdev);
+
+free_cma_root_dev:
+	devm_kfree(dev, cma_root_dev);
+
+done:
+	return ret;
+}
+
+static int __init cma_drvr_do_prealloc(struct device *dev,
+	struct cma_dev *cma_dev)
+{
+	int ret;
+	u64 addr;
+	u32 size;
+
+	size = cma_dev->range.size;
+
+	ret = cma_dev_get_mem(cma_dev, &addr, size, 0);
+	if (ret)
+		dev_err(dev, "Unable to pre-allocate 0x%x bytes (%d)", size,
+			ret);
+	else
+		dev_info(dev, "Pre-allocated 0x%x bytes @ 0x%llx", size, addr);
+
+	return ret;
+}
+
+static int __init cma_drvr_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cma_dev *cma_dev = NULL;
+	int ret = 0;
+	struct cma_pdev_data *data =
+		(struct cma_pdev_data *)dev->platform_data;
+
+	/* Prepare a major number for the devices if not already done */
+	ret = cma_drvr_alloc_devno(dev);
+	if (ret)
+		goto free_cma_dev;
+
+	/* Initialize the root device only once */
+	if (cma_root_dev == NULL)
+		ret = cma_drvr_init_root_dev(dev);
+
+	if (ret)
+		goto done;
+
+	cma_dev = devm_kzalloc(dev, sizeof(*cma_dev), GFP_KERNEL);
+	if (cma_dev == NULL) {
+		dev_err(dev, "can't alloc cma_dev\n");
+		ret = -ENOMEM;
+		goto done;
+	}
+
+	ret = cma_drvr_config_platdev(pdev, cma_dev);
+	if (ret)
+		goto free_cma_dev;
+
+	cma_dev->dev = dev;
+
+	/*
+	 * Keep a pointer to all of the devs so we don't have to search for it
+	 * elsewhere.
+	 */
+	INIT_LIST_HEAD(&cma_dev->list);
+	list_add(&cma_dev->list, &cma_root_dev->cma_devs.list);
+	dev_info(dev, "Added CMA device @ PA=0x%llx LEN=0x%x\n",
+		 cma_dev->range.base, cma_dev->range.size);
+
+	if (data->do_prealloc) {
+		/*
+		 * Pre-allocation failure isn't truly a probe error because the
+		 * device has been initialized at this point. An error will be
+		 * logged if there is a failure.
+		 */
+		cma_drvr_do_prealloc(dev, cma_dev);
+	}
+
+	goto done;
+
+free_cma_dev:
+	devm_kfree(dev, cma_dev);
+
+done:
+	return ret;
+}
+
+int cma_drvr_is_ready(void)
+{
+	return cma_root_dev != NULL;
+}
+
+static struct platform_driver cma_driver = {
+	.driver = {
+		.name = "brcm-cma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init cma_drvr_init(void)
+{
+	return platform_driver_probe(&cma_driver, cma_drvr_probe);
+}
+module_init(cma_drvr_init);
+
+static void __exit cma_drvr_exit(void)
+{
+	platform_driver_unregister(&cma_driver);
+}
+module_exit(cma_drvr_exit);
diff --git a/drivers/soc/brcmstb/common.c b/drivers/soc/brcmstb/common.c
new file mode 100644
index 000000000000..298762e85da0
--- /dev/null
+++ b/drivers/soc/brcmstb/common.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright © 2014 NVIDIA Corporation
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/soc/brcmstb/brcmstb.h>
+#include <linux/sys_soc.h>
+
+#include <soc/brcmstb/common.h>
+
+static u32 family_id;
+static u32 product_id;
+
+static const struct of_device_id brcmstb_machine_match[] = {
+	{ .compatible = "brcm,brcmstb", },
+	{ }
+};
+
+bool soc_is_brcmstb(void)
+{
+	struct device_node *root;
+
+	root = of_find_node_by_path("/");
+	if (!root)
+		return false;
+
+	return of_match_node(brcmstb_machine_match, root) != NULL;
+}
+
+u32 brcmstb_get_family_id(void)
+{
+	return family_id;
+}
+EXPORT_SYMBOL(brcmstb_get_family_id);
+
+u32 brcmstb_get_product_id(void)
+{
+	return product_id;
+}
+EXPORT_SYMBOL(brcmstb_get_product_id);
+
+static const struct of_device_id sun_top_ctrl_match[] = {
+	{ .compatible = "brcm,brcmstb-sun-top-ctrl", },
+	{ }
+};
+
+static int __init brcmstb_soc_device_init(void)
+{
+	struct soc_device_attribute *soc_dev_attr;
+	struct soc_device *soc_dev;
+	struct device_node *sun_top_ctrl;
+	void __iomem *sun_top_ctrl_base;
+
+	sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
+	if (!sun_top_ctrl)
+		return -ENODEV;
+
+	sun_top_ctrl_base = of_iomap(sun_top_ctrl, 0);
+	if (!sun_top_ctrl_base)
+		return -ENODEV;
+
+	family_id = readl(sun_top_ctrl_base);
+	product_id = readl(sun_top_ctrl_base + 0x4);
+
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		return -ENOMEM;
+
+	soc_dev_attr->family = kasprintf(GFP_KERNEL, "%x",
+					family_id >> 28 ?
+					family_id >> 16 : family_id >> 8);
+	soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%x",
+					product_id >> 28 ?
+					product_id >> 16 : product_id >> 8);
+	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c%d",
+					   (char)(((product_id & 0xff) >> 4) + 65),
+					   product_id & 0xf);
+
+	soc_dev = soc_device_register(soc_dev_attr);
+	if (IS_ERR(soc_dev)) {
+		kfree(soc_dev_attr->family);
+		kfree(soc_dev_attr->soc_id);
+		kfree(soc_dev_attr->revision);
+		kfree(soc_dev_attr);
+		return -1;
+	}
+
+	return 0;
+}
+arch_initcall(brcmstb_soc_device_init);
diff --git a/drivers/soc/brcmstb/irq0-stub.c b/drivers/soc/brcmstb/irq0-stub.c
new file mode 100644
index 000000000000..9a8a0063e42e
--- /dev/null
+++ b/drivers/soc/brcmstb/irq0-stub.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/syscore_ops.h>
+#include <soc/brcmstb/common.h>
+
+static void __brcmstb_irq0_init(void)
+{
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+	);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static struct syscore_ops brcmstb_irq0_syscore_ops = {
+	.resume         = __brcmstb_irq0_init,
+};
+#endif
+
+static int brcmstb_irq0_init(void)
+{
+	if (!soc_is_brcmstb())
+		return 0;
+
+	__brcmstb_irq0_init();
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&brcmstb_irq0_syscore_ops);
+#endif
+
+	return 0;
+}
+early_initcall(brcmstb_irq0_init);
diff --git a/drivers/soc/brcmstb/memory.c b/drivers/soc/brcmstb/memory.c
new file mode 100644
index 000000000000..247401045f22
--- /dev/null
+++ b/drivers/soc/brcmstb/memory.c
@@ -0,0 +1,687 @@
+/*
+ * Copyright © 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <asm/page.h>
+#include <asm/setup.h>  /* for meminfo */
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/memblock.h>
+#include <linux/mm.h>   /* for high_memory */
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/vme.h>
+#include <linux/brcmstb/bmem.h>
+#include <linux/brcmstb/cma_driver.h>
+#include <linux/brcmstb/memory_api.h>
+
+/* -------------------- Constants -------------------- */
+
+#define DEFAULT_LOWMEM_PCT	20  /* used if only one membank */
+
+/* Macros to help extract property data */
+#define U8TOU32(b, offs) \
+	((((u32)b[0+offs] << 0)  & 0x000000ff) | \
+	 (((u32)b[1+offs] << 8)  & 0x0000ff00) | \
+	 (((u32)b[2+offs] << 16) & 0x00ff0000) | \
+	 (((u32)b[3+offs] << 24) & 0xff000000))
+
+#define DT_PROP_DATA_TO_U32(b, offs) (fdt32_to_cpu(U8TOU32(b, offs)))
+
+/* Constants used when retrieving memc info */
+#define NUM_BUS_RANGES 10
+#define BUS_RANGE_ULIMIT_SHIFT 4
+#define BUS_RANGE_LLIMIT_SHIFT 4
+#define BUS_RANGE_PA_SHIFT 12
+
+enum {
+	BUSNUM_MCP0 = 0x4,
+	BUSNUM_MCP1 = 0x5,
+	BUSNUM_MCP2 = 0x6,
+};
+
+/* -------------------- Shared and local vars -------------------- */
+
+const enum brcmstb_reserve_type brcmstb_default_reserve = BRCMSTB_RESERVE_BMEM;
+bool brcmstb_memory_override_defaults = false;
+
+static struct {
+	struct brcmstb_range range[MAX_BRCMSTB_RESERVED_RANGE];
+	int count;
+} reserved_init;
+
+/* -------------------- Functions -------------------- */
+
+/*
+ * If the DT nodes are handy, determine which MEMC holds the specified
+ * physical address.
+ */
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+	int memc = -1;
+	int i;
+	struct device_node *np;
+	void __iomem *cpubiuctrl = NULL;
+	void __iomem *curr;
+
+	np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+	if (!np)
+		goto cleanup;
+
+	cpubiuctrl = of_iomap(np, 0);
+	if (!cpubiuctrl)
+		goto cleanup;
+
+	for (i = 0, curr = cpubiuctrl; i < NUM_BUS_RANGES; i++, curr += 8) {
+		const u64 ulimit_raw = readl(curr);
+		const u64 llimit_raw = readl(curr + 4);
+		const u64 ulimit =
+			((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT)
+			 << BUS_RANGE_PA_SHIFT) | 0xfff;
+		const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT)
+				   << BUS_RANGE_PA_SHIFT;
+		const u32 busnum = (u32)(ulimit_raw & 0xf);
+
+		if (pa >= llimit && pa <= ulimit) {
+			if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) {
+				memc = busnum - BUSNUM_MCP0;
+				break;
+			}
+		}
+	}
+
+cleanup:
+	if (cpubiuctrl)
+		iounmap(cpubiuctrl);
+
+	of_node_put(np);
+
+	return memc;
+}
+
+static int populate_memc(struct brcmstb_memory *mem, int addr_cells,
+		int size_cells)
+{
+	const void *fdt = initial_boot_params;
+	const int mem_offset = fdt_path_offset(fdt, "/memory");
+	const struct fdt_property *prop;
+	int proplen, cellslen;
+	int i;
+
+	if (mem_offset < 0) {
+		pr_err("No memory node?\n");
+		return -EINVAL;
+	}
+
+	prop = fdt_get_property(fdt, mem_offset, "reg", &proplen);
+	cellslen = (int)sizeof(u32) * (addr_cells + size_cells);
+	if ((proplen % cellslen) != 0) {
+		pr_err("Invalid length of reg prop: %d\n", proplen);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < proplen / cellslen; ++i) {
+		u64 addr = 0;
+		u64 size = 0;
+		int memc_idx;
+		int range_idx;
+		int j;
+
+		for (j = 0; j < addr_cells; ++j) {
+			int offset = (cellslen * i) + (sizeof(u32) * j);
+			addr |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+				((addr_cells - j - 1) * 32);
+		}
+		for (j = 0; j < size_cells; ++j) {
+			int offset = (cellslen * i) +
+				(sizeof(u32) * (j + addr_cells));
+			size |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+				((size_cells - j - 1) * 32);
+		}
+
+		if ((phys_addr_t)addr != addr) {
+			pr_err("phys_addr_t is smaller than provided address 0x%llx!\n",
+					addr);
+			return -EINVAL;
+		}
+
+		memc_idx = brcmstb_memory_phys_addr_to_memc((phys_addr_t)addr);
+		if (memc_idx == -1) {
+			pr_err("address 0x%llx does not appear to be in any memc\n",
+					addr);
+			return -EINVAL;
+		}
+
+		range_idx = mem->memc[memc_idx].count;
+		if (mem->memc[memc_idx].count >= MAX_BRCMSTB_RANGE)
+			pr_warn("%s: Exceeded max ranges for memc%d\n",
+					__func__, memc_idx);
+		else {
+			mem->memc[memc_idx].range[range_idx].addr = addr;
+			mem->memc[memc_idx].range[range_idx].size = size;
+		}
+		++mem->memc[memc_idx].count;
+	}
+
+	return 0;
+}
+
+static int populate_lowmem(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_ARM
+	mem->lowmem.range[0].addr = __pa(PAGE_OFFSET);
+	mem->lowmem.range[0].size = (unsigned long)high_memory - PAGE_OFFSET;
+	++mem->lowmem.count;
+	return 0;
+#else
+	return -ENOSYS;
+#endif
+}
+
+static int populate_bmem(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_BRCMSTB_BMEM
+	phys_addr_t addr, size;
+	int i;
+
+	for (i = 0; i < MAX_BRCMSTB_RANGE; ++i) {
+		if (bmem_region_info(i, &addr, &size))
+			break;  /* no more regions */
+		mem->bmem.range[i].addr = addr;
+		mem->bmem.range[i].size = size;
+		++mem->bmem.count;
+	}
+	if (i >= MAX_BRCMSTB_RANGE) {
+		while (bmem_region_info(i, &addr, &size) == 0) {
+			pr_warn("%s: Exceeded max ranges\n", __func__);
+			++mem->bmem.count;
+		}
+	}
+
+	return 0;
+#else
+	return -ENOSYS;
+#endif
+}
+
+static int populate_cma(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_BRCMSTB_CMA
+	int i;
+
+	for (i = 0; i < CMA_NUM_RANGES; ++i) {
+		struct cma_dev *cdev = cma_dev_get_cma_dev(i);
+		if (cdev == NULL)
+			break;
+		if (i >= MAX_BRCMSTB_RANGE)
+			pr_warn("%s: Exceeded max ranges\n", __func__);
+		else {
+			mem->cma.range[i].addr = cdev->range.base;
+			mem->cma.range[i].size = cdev->range.size;
+		}
+		++mem->cma.count;
+	}
+
+	return 0;
+#else
+	return -ENOSYS;
+#endif
+}
+
+static int populate_reserved(struct brcmstb_memory *mem)
+{
+#ifdef CONFIG_HAVE_MEMBLOCK
+	memcpy(&mem->reserved, &reserved_init, sizeof(reserved_init));
+	return 0;
+#else
+	return -ENOSYS;
+#endif
+}
+
+/**
+ * brcmstb_memory_get_default_reserve() - find default reservation for given ID
+ * @bank_nr: bank index
+ * @pstart: pointer to the start address (output)
+ * @psize: pointer to the size address (output)
+ *
+ * NOTE: This interface will change in future kernels that do not have meminfo
+ *
+ * This takes in the bank number and determines the size and address of the
+ * default region reserved for refsw within the bank.
+ */
+int __init brcmstb_memory_get_default_reserve(int bank_nr,
+		phys_addr_t *pstart, phys_addr_t *psize)
+{
+	/* min alignment for mm core */
+	const phys_addr_t alignment =
+		PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+	struct membank *bank = &meminfo.bank[bank_nr];
+	phys_addr_t start = bank->start;
+	phys_addr_t size = 0, adj = 0;
+	phys_addr_t newstart, newsize;
+	int i;
+
+	if (!pstart || !psize)
+		return -EFAULT;
+
+	if (bank_nr == 0) {
+		if (meminfo.nr_banks == 1) {
+			u32 rem;
+			u64 tmp;
+
+			BUG_ON(bank->highmem);
+			if (bank->size < SZ_32M) {
+				pr_err("low memory too small for default bmem\n");
+				return -EINVAL;
+			}
+
+			if (brcmstb_default_reserve == BRCMSTB_RESERVE_BMEM) {
+				if (bank->size <= SZ_128M)
+					return -EINVAL;
+
+				adj = SZ_128M;
+			}
+
+			/* kernel reserves X percent, bmem gets the rest */
+			tmp = ((u64)(bank->size - adj)) * (100 - DEFAULT_LOWMEM_PCT);
+			rem = do_div(tmp, 100);
+			size = tmp + rem;
+			start = bank->start + bank->size - size;
+		} else {
+			/* If more than one bank, don't use first bank */
+			return -EINVAL;
+		}
+	} else if (bank->start >= VME_A32_MAX && bank->size > SZ_64M) {
+		/*
+		 * Nexus doesn't use the address extension range yet, just
+		 * reserve 64 MiB in these areas until we have a firmer
+		 * specification
+		 */
+		size = SZ_64M;
+	} else {
+		size = bank->size;
+	}
+
+	/*
+	 * To keep things simple, we only handle the case where reserved memory
+	 * is at the start or end of a region.
+	 */
+	i = 0;
+	while (i < memblock.reserved.cnt) {
+		struct memblock_region *region = &memblock.reserved.regions[i];
+		newstart = start;
+		newsize = size;
+
+		if (start >= region->base &&
+				start < region->base + region->size) {
+			/* adjust for reserved region at beginning */
+			newstart = region->base + region->size;
+			newsize = size - (newstart - start);
+		} else if (start < region->base) {
+			if (start + size >
+					region->base + region->size) {
+				/* unhandled condition */
+				pr_err("%s: Split region %pa@%pa, reserve will fail\n",
+						__func__, &size, &start);
+				/* enable 'memblock=debug' for dump output */
+				memblock_dump_all();
+				return -EINVAL;
+			}
+			/* adjust for reserved region at end */
+			newsize = min(region->base - start, size);
+		}
+		/* see if we had any modifications */
+		if (newsize != size || newstart != start) {
+			pr_debug("%s: moving default region from %pa@%pa to %pa@%pa\n",
+					__func__, &size, &start, &newsize,
+					&newstart);
+			size = newsize;
+			start = newstart;
+			i = 0; /* start over */
+		} else {
+			++i;
+		}
+	}
+
+	/* Fix up alignment */
+	newstart = ALIGN(start, alignment);
+	if (newstart != start) {
+		pr_debug("adjusting start from %pa to %pa\n",
+				&start, &newstart);
+		start = newstart;
+	}
+	newsize = round_down(size, alignment);
+	if (newsize != size) {
+		pr_debug("adjusting size from %pa to %pa\n",
+				&size, &newsize);
+		size = newsize;
+	}
+
+	if (size == 0) {
+		pr_debug("size available in bank was 0 - skipping\n");
+		return -EINVAL;
+	}
+
+	*pstart = start;
+	*psize = size;
+
+	return 0;
+}
+
+/**
+ * brcmstb_memory_reserve() - fill in static brcmstb_memory structure
+ *
+ * This is a boot-time initialization function used to copy the information
+ * stored in the memblock reserve function that is discarded after boot.
+ */
+void __init brcmstb_memory_reserve(void)
+{
+#ifdef CONFIG_HAVE_MEMBLOCK
+	struct memblock_type *type = &memblock.reserved;
+	int i;
+
+	for (i = 0; i < type->cnt; ++i) {
+		struct memblock_region *region = &type->regions[i];
+
+		if (i >= MAX_BRCMSTB_RESERVED_RANGE)
+			pr_warn_once("%s: Exceeded max ranges\n", __func__);
+		else {
+			reserved_init.range[i].addr = region->base;
+			reserved_init.range[i].size = region->size;
+		}
+		++reserved_init.count;
+	}
+#else
+	pr_err("No memblock, cannot get reserved range\n");
+#endif
+}
+
+/*
+ * brcmstb_memory_get() - fill in brcmstb_memory structure
+ * @mem: pointer to allocated struct brcmstb_memory to fill
+ *
+ * The brcmstb_memory struct is required by the brcmstb middleware to
+ * determine how to set up its memory heaps.  This function expects that the
+ * passed pointer is valid.  The struct does not need to have be zeroed
+ * before calling.
+ */
+int brcmstb_memory_get(struct brcmstb_memory *mem)
+{
+	const void *fdt = initial_boot_params;
+	const struct fdt_property *prop;
+	int addr_cells = 1, size_cells = 1;
+	int proplen;
+	int ret;
+
+	if (!mem)
+		return -EFAULT;
+
+	if (!fdt) {
+		pr_err("No device tree?\n");
+		return -EINVAL;
+	}
+
+	/* Get root size and address cells if specified */
+	prop = fdt_get_property(fdt, 0, "#size-cells", &proplen);
+	if (prop)
+		size_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+	pr_debug("size_cells = %x\n", size_cells);
+
+	prop = fdt_get_property(fdt, 0, "#address-cells", &proplen);
+	if (prop)
+		addr_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+	pr_debug("address_cells = %x\n", addr_cells);
+
+	memset(mem, 0, sizeof(*mem));
+
+	ret = populate_memc(mem, addr_cells, size_cells);
+	if (ret)
+		return ret;
+
+	ret = populate_lowmem(mem);
+	if (ret)
+		return ret;
+
+	ret = populate_bmem(mem);
+	if (ret)
+		pr_debug("bmem is disabled\n");
+
+	ret = populate_cma(mem);
+	if (ret)
+		pr_debug("cma is disabled\n");
+
+	ret = populate_reserved(mem);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(brcmstb_memory_get);
+
+static int pte_callback(pte_t *pte, unsigned long x, unsigned long y,
+			struct mm_walk *walk)
+{
+	const pgprot_t pte_prot = __pgprot(*pte);
+	const pgprot_t req_prot = *((pgprot_t *)walk->private);
+	const pgprot_t prot_msk = L_PTE_MT_MASK | L_PTE_VALID;
+	return (((pte_prot ^ req_prot) & prot_msk) == 0) ? 0 : -1;
+}
+
+static void *page_to_virt_contig(const struct page *page, unsigned int pg_cnt,
+					pgprot_t pgprot)
+{
+	int rc;
+	struct mm_walk walk;
+	unsigned long pfn;
+	unsigned long pfn_start;
+	unsigned long pfn_end;
+	unsigned long va_start;
+	unsigned long va_end;
+
+	if ((page == NULL) || !pg_cnt)
+		return ERR_PTR(-EINVAL);
+
+	pfn_start = page_to_pfn(page);
+	pfn_end = pfn_start + pg_cnt;
+	for (pfn = pfn_start; pfn < pfn_end; pfn++) {
+		const struct page *cur_pg = pfn_to_page(pfn);
+		phys_addr_t pa;
+
+		/* Verify range is in low memory only */
+		if (PageHighMem(cur_pg))
+			return NULL;
+
+		/* Must be mapped */
+		pa = page_to_phys(cur_pg);
+		if (page_address(cur_pg) == NULL)
+			return NULL;
+	}
+
+	/*
+	 * Aliased mappings with different cacheability attributes on ARM can
+	 * lead to trouble!
+	 */
+	memset(&walk, 0, sizeof(walk));
+	walk.pte_entry = &pte_callback;
+	walk.private = (void *)&pgprot;
+	walk.mm = current->mm;
+	va_start = (unsigned long)page_address(page);
+	va_end = (unsigned long)(page_address(page) + (pg_cnt << PAGE_SHIFT));
+	rc = walk_page_range(va_start,
+			     va_end,
+			     &walk);
+	if (rc)
+		pr_debug("cacheability mismatch\n");
+
+	return rc ? NULL : page_address(page);
+}
+
+static struct page **get_pages(struct page *page, int num_pages)
+{
+	struct page **pages;
+	long pfn;
+	int i;
+
+	if (num_pages == 0) {
+		pr_err("bad count\n");
+		return NULL;
+	}
+
+	if (page == NULL) {
+		pr_err("bad page\n");
+		return NULL;
+	}
+
+	pages = vmalloc(sizeof(struct page *) * num_pages);
+	if (pages == NULL)
+		return NULL;
+
+	pfn = page_to_pfn(page);
+	for (i = 0; i < num_pages; i++) {
+		/*
+		 * pfn_to_page() should resolve to simple arithmetic for the
+		 * FLATMEM memory model.
+		 */
+		pages[i] = pfn_to_page(pfn++);
+	}
+
+	return pages;
+}
+
+/*
+ * Basically just vmap() without checking that count < totalram_pages,
+ * since we want to be able to map pages that aren't managed by Linux
+ */
+static void *brcmstb_memory_vmap(struct page **pages, unsigned int count,
+		unsigned long flags, pgprot_t prot)
+{
+	struct vm_struct *area;
+
+	might_sleep();
+
+	area = get_vm_area_caller((count << PAGE_SHIFT), flags,
+					__builtin_return_address(0));
+	if (!area)
+		return NULL;
+
+	if (map_vm_area(area, prot, &pages)) {
+		vunmap(area->addr);
+		return NULL;
+	}
+
+	return area->addr;
+}
+
+/**
+ * brcmstb_memory_kva_map() - Map page(s) to a kernel virtual address
+ *
+ * @page: A struct page * that points to the beginning of a chunk of physical
+ * contiguous memory.
+ * @num_pages: Number of pages
+ * @pgprot: Page protection bits
+ *
+ * Return: pointer to mapping, or NULL on failure
+ */
+void *brcmstb_memory_kva_map(struct page *page, int num_pages, pgprot_t pgprot)
+{
+	void *va;
+
+	/* get the virtual address for this range if it exists */
+	va = page_to_virt_contig(page, num_pages, pgprot);
+	if (IS_ERR(va)) {
+		pr_debug("page_to_virt_contig() failed (%ld)\n", PTR_ERR(va));
+		return NULL;
+	} else if (va == NULL || is_vmalloc_addr(va)) {
+		struct page **pages;
+
+		pages = get_pages(page, num_pages);
+		if (pages == NULL) {
+			pr_err("couldn't get pages\n");
+			return NULL;
+		}
+
+		va = brcmstb_memory_vmap(pages, num_pages, 0, pgprot);
+
+		vfree(pages);
+
+		if (va == NULL) {
+			pr_err("vmap failed (num_pgs=%d)\n", num_pages);
+			return NULL;
+		}
+	}
+
+	return va;
+}
+EXPORT_SYMBOL(brcmstb_memory_kva_map);
+
+/**
+ * brcmstb_memory_kva_map_phys() - map phys range to kernel virtual address
+ *
+ * @phys: physical address base
+ * @size: size of range to map
+ * @cached: whether to use cached or uncached mapping
+ *
+ * Return: NULL on failure, err on success
+ */
+void *brcmstb_memory_kva_map_phys(phys_addr_t phys, size_t size, bool cached)
+{
+	void *addr = NULL;
+	unsigned long pfn = PFN_DOWN(phys);
+
+	if (!cached) {
+		/*
+		 * This could be supported for MIPS by using ioremap instead,
+		 * but that cannot be done on ARM if you want O_DIRECT support
+		 * because having multiple mappings to the same memory with
+		 * different cacheability will result in undefined behavior.
+		 */
+		return NULL;
+	}
+
+	if (pfn_valid(pfn)) {
+		addr = brcmstb_memory_kva_map(pfn_to_page(pfn),
+				size / PAGE_SIZE, PAGE_KERNEL);
+	}
+	return addr;
+}
+EXPORT_SYMBOL(brcmstb_memory_kva_map_phys);
+
+/**
+ * brcmstb_memory_kva_unmap() - Unmap a kernel virtual address associated
+ * to physical pages mapped by brcmstb_memory_kva_map()
+ *
+ * @kva: Kernel virtual address previously mapped by brcmstb_memory_kva_map()
+ *
+ * Return: 0 on success, negative on failure.
+ */
+int brcmstb_memory_kva_unmap(const void *kva)
+{
+	if (kva == NULL)
+		return -EINVAL;
+
+	if (!is_vmalloc_addr(kva)) {
+		/* unmapping not necessary for low memory VAs */
+		return 0;
+	}
+
+	vunmap(kva);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcmstb_memory_kva_unmap);
diff --git a/drivers/soc/brcmstb/nexus/Makefile b/drivers/soc/brcmstb/nexus/Makefile
new file mode 100644
index 000000000000..e77e1cc304f4
--- /dev/null
+++ b/drivers/soc/brcmstb/nexus/Makefile
@@ -0,0 +1,3 @@
+obj-y	:=	irq.o \
+		gpio.o \
+		reg.o
diff --git a/drivers/soc/brcmstb/nexus/gpio.c b/drivers/soc/brcmstb/nexus/gpio.c
new file mode 100644
index 000000000000..8dd2a951be50
--- /dev/null
+++ b/drivers/soc/brcmstb/nexus/gpio.c
@@ -0,0 +1,266 @@
+/*
+ * Nexus GPIO(s) resolution API
+ *
+ * Copyright (C) 2015-2016, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/gpio.h>
+#include <linux/bitmap.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/basic_mmio_gpio.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/brcmstb/gpio_api.h>
+
+#include "gpio.h"
+#define GIO_DATA_OFFSET 4
+#define GIO_DIR_OFFSET	8
+
+static const char *brcmstb_gpio_compat = GPIO_DT_COMPAT;
+
+static int brcmstb_gpio_chip_find(struct gpio_chip *chip, void *data)
+{
+	struct device_node *dn = data;
+
+	if (chip->of_node == dn)
+		return 1;
+
+	return 0;
+}
+
+/* Keep an additional bitmap of which GPIOs are requested by Nexus to
+ * maintain Linux/Nexus GPIO exclusive ownership managed via gpio_request().
+ * We do want multiple consecutive calls to brcmstb_gpio_irq() not to fail
+ * because the first one claimed ownernship already.
+ */
+static DECLARE_BITMAP(brcmstb_gpio_requested, CONFIG_ARCH_NR_GPIO);
+
+static int brcmstb_gpio_request(unsigned int gpio)
+{
+	int ret = 0;
+
+	/* Request the GPIO to flag that Nexus now owns it, but
+	 * also keep it requested in our local bitmap to avoid
+	 * subsequent gpio_request() calls to the same GPIO
+	 */
+	if (!test_bit(gpio, brcmstb_gpio_requested)) {
+		ret = gpio_request(gpio, "nexus");
+		if (ret) {
+			pr_err("%s: GPIO request failed\n", __func__);
+			return ret;
+		}
+
+		/* We could get ownership, so flag it now */
+		set_bit(gpio, brcmstb_gpio_requested);
+	}
+
+	return ret;
+}
+
+static int brcmstb_gpio_find_base_by_addr(uint32_t addr, phys_addr_t *start)
+{
+	struct device_node *dn;
+	struct gpio_chip *gc;
+	struct resource res;
+	int ret;
+
+	for_each_compatible_node(dn, NULL, brcmstb_gpio_compat) {
+		ret = of_address_to_resource(dn, 0, &res);
+		if (ret) {
+			pr_err("%s: unable to translate resource\n", __func__);
+			continue;
+		}
+
+		if (res.flags != IORESOURCE_MEM) {
+			pr_err("%s: invalid resource type\n", __func__);
+			continue;
+		}
+
+		/* Mask address with the physical offset, since the address has
+		 * already been translated based on the busing hierarchy
+		 */
+		res.start &= ~BCHP_PHYSICAL_OFFSET;
+		res.end &= ~BCHP_PHYSICAL_OFFSET;
+
+		/* Verify address in the resource range, if not, go to the
+		 * other GPIO controllers
+		 */
+		if (addr < res.start || addr >= res.end)
+			continue;
+
+		gc = gpiochip_find(dn, brcmstb_gpio_chip_find);
+		if (!gc) {
+			pr_err("%s: unable to find gpio chip\n", __func__);
+			continue;
+		}
+
+		if (start)
+			*start = (phys_addr_t)res.start;
+
+		return gc->base;
+	}
+
+	return -ENODEV;
+
+}
+
+static int brcmstb_gpio_find_by_addr(uint32_t addr, unsigned int shift)
+{
+	int gpio, gpio_base;
+	phys_addr_t start, bank_offset;
+
+	gpio_base = brcmstb_gpio_find_base_by_addr(addr, &start);
+	if (gpio_base >= 0) {
+		/* Now find out what GPIO bank this pin belongs to */
+		bank_offset = ((phys_addr_t)addr - start) / GIO_BANK_SIZE;
+
+		gpio = gpio_base + shift + bank_offset * GPIO_PER_BANK;
+
+		pr_debug("%s: xlate base=%d, offset=%d, shift=%d, gpio=%d\n",
+			__func__, (int)gpio_base, (int)bank_offset, shift,
+			(int)(gpio - gpio_base));
+
+		return gpio;
+	}
+
+	return gpio_base;
+}
+
+int brcmstb_gpio_update32(uint32_t addr, uint32_t mask, uint32_t value)
+{
+	struct bgpio_chip *bgc;
+	struct gpio_chip *gc;
+	int ret, bit, gpio_base;
+	phys_addr_t start, offset, bank_offset;
+	unsigned long flags;
+	uint32_t ivalue;
+	void __iomem *reg;
+
+	gpio_base = brcmstb_gpio_find_base_by_addr(addr, &start);
+	if (gpio_base < 0) {
+		pr_err("%s: addr is not in GPIO range\n", __func__);
+		return -EPERM;
+	}
+
+	/* Now find out what GPIO bank this pin belongs to */
+	offset = (phys_addr_t)addr - start;
+	bank_offset = offset / GIO_BANK_SIZE;
+	offset -= bank_offset * GIO_BANK_SIZE;
+
+	pr_debug("%s: xlate base=%d, offset=%d, gpio=%d\n",
+		__func__, (int)gpio_base, (int)bank_offset,
+		(int)(bank_offset * GPIO_PER_BANK));
+
+	gpio_base += bank_offset * GPIO_PER_BANK;
+
+	for (bit = 0; bit < GPIO_PER_BANK; bit++) {
+		/* Ignore bits which are not in mask */
+		if (!((1 << bit) & mask))
+			continue;
+
+		ret = brcmstb_gpio_request(gpio_base + bit);
+		if (ret < 0) {
+			pr_err("%s: unable to request gpio %d\n",
+				__func__, gpio_base + bit);
+			return ret;
+		}
+	}
+
+	/* We got full access to the entire mask, do the write */
+
+	pr_debug("%s: offset=0x%08x mask=0x%08x, value=0x%08x\n",
+		__func__, addr, mask, value);
+
+	gc = gpiod_to_chip(gpio_to_desc(gpio_base));
+	if (gc == NULL) {
+		pr_err("%s: unable to resolve gpio chip\n", __func__);
+		return -EPERM;
+	}
+	bgc = to_bgpio_chip(gc);
+	reg = bgc->reg_dat;
+	if (reg == 0) {
+		pr_err("%s: unable to resolve GIO mapped address\n", __func__);
+		return -EPERM;
+	}
+
+	spin_lock_irqsave(&bgc->lock, flags);
+	ivalue = bgc->read_reg(reg + offset - GIO_DATA_OFFSET);
+	ivalue &= ~(mask);
+	ivalue |= (value & mask);
+
+	/* update shadows */
+	switch (offset) {
+	case GIO_DATA_OFFSET:
+		bgc->data = ivalue;
+		break;
+	case GIO_DIR_OFFSET:
+		bgc->dir = ivalue;
+		break;
+	default:
+		break;
+	}
+
+	bgc->write_reg(reg + offset - GIO_DATA_OFFSET, ivalue);
+	spin_unlock_irqrestore(&bgc->lock, flags);
+
+	return 0;
+}
+
+int brcmstb_gpio_irq(uint32_t addr, unsigned int shift)
+{
+	int gpio, ret;
+
+	gpio = brcmstb_gpio_find_by_addr(addr, shift);
+	if (gpio < 0)
+		return gpio;
+
+	ret = brcmstb_gpio_request(gpio);
+	if (ret < 0)
+		return ret;
+
+	ret = gpio_to_irq(gpio);
+	if (ret < 0) {
+		gpio_free(gpio);
+		pr_err("%s: unable to map GPIO%d to irq, ret=%d\n",
+		       __func__, gpio, ret);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(brcmstb_gpio_irq);
+
+static void brcmstb_gpio_free(unsigned int gpio)
+{
+    if (test_bit(gpio, brcmstb_gpio_requested)) {
+        gpio_free(gpio);
+        clear_bit(gpio, brcmstb_gpio_requested);
+    }
+}
+
+void brcmstb_gpio_remove(void)
+{
+    unsigned i;
+
+    for (i = 0; i < CONFIG_ARCH_NR_GPIO; i++)
+    {
+        brcmstb_gpio_free(i);
+    }
+}
+EXPORT_SYMBOL(brcmstb_gpio_remove);
diff --git a/drivers/soc/brcmstb/nexus/gpio.h b/drivers/soc/brcmstb/nexus/gpio.h
new file mode 100644
index 000000000000..f885a6c60689
--- /dev/null
+++ b/drivers/soc/brcmstb/nexus/gpio.h
@@ -0,0 +1,10 @@
+#ifndef __NEXUS_INTERNAL_GPIO_H
+#define __NEXUS_INTERNAL_GPIO_H
+
+#define GPIO_DT_COMPAT	"brcm,brcmstb-gpio"
+#define GIO_BANK_SIZE	0x20
+#define GPIO_PER_BANK	32
+
+int brcmstb_gpio_update32(uint32_t addr, uint32_t mask, uint32_t value);
+
+#endif /* __NEXUS_INTERNAL_GPIO_H */
diff --git a/drivers/soc/brcmstb/nexus/irq.c b/drivers/soc/brcmstb/nexus/irq.c
new file mode 100644
index 000000000000..3f264a6a557e
--- /dev/null
+++ b/drivers/soc/brcmstb/nexus/irq.c
@@ -0,0 +1,148 @@
+/*
+ * Nexus interrupt(s) resolution API
+ *
+ * Copyright (C) 2015-2016, Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+
+#include <linux/brcmstb/irq_api.h>
+
+#define BUILD_IRQ_NAME(_name)			\
+	case brcmstb_l2_irq_##_name:		\
+		return __stringify(_name);	\
+
+static const char *brcmstb_l2_irq_to_name(brcmstb_l2_irq irq)
+{
+	switch (irq) {
+	BUILD_IRQ_NAME(gio);
+	BUILD_IRQ_NAME(gio_aon);
+	BUILD_IRQ_NAME(iica);
+	BUILD_IRQ_NAME(iicb);
+	BUILD_IRQ_NAME(iicc);
+	BUILD_IRQ_NAME(iicd);
+	BUILD_IRQ_NAME(iice);
+	BUILD_IRQ_NAME(iicf);
+	BUILD_IRQ_NAME(iicg);
+	BUILD_IRQ_NAME(irb);
+	BUILD_IRQ_NAME(icap);
+	BUILD_IRQ_NAME(kbd1);
+	BUILD_IRQ_NAME(kbd2);
+	BUILD_IRQ_NAME(kbd3);
+	BUILD_IRQ_NAME(ldk);
+	BUILD_IRQ_NAME(spi);
+	BUILD_IRQ_NAME(ua);
+	BUILD_IRQ_NAME(ub);
+	BUILD_IRQ_NAME(uc);
+	default:
+		return NULL;
+	}
+
+	return NULL;
+}
+
+static int brcmstb_resolve_l2_irq(struct device_node *np, brcmstb_l2_irq irq)
+{
+	int i, num_elems, ret;
+	const char *int_name, *irq_name;
+	u32 hwirq;
+
+	irq_name = brcmstb_l2_irq_to_name(irq);
+	if (!irq_name)
+		return -EINVAL;
+
+	/* Special case for AON interrupt names, search the other node for the
+	 * same name
+	 */
+	if (strstr(irq_name, "aon") && !strstr(np->name, "aon"))
+		return -EAGAIN;
+
+	pr_debug("%s: resolving on node %s\n", __func__, np->full_name);
+
+	num_elems = of_property_count_strings(np, "interrupt-names");
+	if (num_elems <= 0) {
+		pr_err("Unable to find an interrupt-names property, check DT\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < num_elems; i++) {
+		ret = of_property_read_u32_index(np, "interrupts", i,
+						 &hwirq);
+		if (ret < 0)
+			return ret;
+
+		ret = of_property_read_string_index(np,
+						    "interrupt-names",
+						    i, &int_name);
+		if (ret < 0)
+			return ret;
+
+		/* We may be requesting to match, eg: "gio" with "gio_aon" */
+		if (!strncasecmp(int_name, irq_name, strlen(int_name)))
+			break;
+	}
+
+	if (i == num_elems) {
+		pr_debug("%s: exceeded search for %s\n", __func__, irq_name);
+		return -ENOENT;
+	}
+
+	pr_debug("%s IRQ name: %s Node: %s @%d mapped to: %d\n", __func__,
+		 irq_name, np->full_name, i, hwirq);
+
+	ret = of_irq_get(np, i);
+	if (ret < 0) {
+#ifndef CONFIG_BCM7120_L2_IRQ
+		if (ret == -EPROBE_DEFER)
+			pr_warn("Could't get IRQ. Enable CONFIG_BCM7120_L2_IRQ"
+				" if you want \"%s\" interrupt support\n",
+				irq_name);
+#endif
+	}
+
+	return ret;
+}
+
+static const char *nexus_irq0_node_names[] = { "nexus-irq0", "nexus-irq0_aon" };
+
+int brcmstb_get_l2_irq_id(brcmstb_l2_irq irq)
+{
+	struct device_node *np;
+	int ret = -ENOENT;
+	int i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(nexus_irq0_node_names); i++) {
+		np = of_find_node_by_name(NULL, nexus_irq0_node_names[i]);
+		if (!np)
+			continue;
+
+		ret = brcmstb_resolve_l2_irq(np, irq);
+		if (ret < 0)
+			continue;
+
+		if (ret == 0)
+			return -EBUSY;
+
+		if (ret > 0)
+			break;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(brcmstb_get_l2_irq_id);
diff --git a/drivers/soc/brcmstb/nexus/reg.c b/drivers/soc/brcmstb/nexus/reg.c
new file mode 100644
index 000000000000..6f536a2e7dc2
--- /dev/null
+++ b/drivers/soc/brcmstb/nexus/reg.c
@@ -0,0 +1,31 @@
+/*
+ * Nexus Register(s) API
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/brcmstb/reg_api.h>
+
+#include "gpio.h"
+
+int brcmstb_update32(uint32_t addr, uint32_t mask, uint32_t value)
+{
+	return brcmstb_gpio_update32(addr, mask, value);
+}
+EXPORT_SYMBOL(brcmstb_update32);
diff --git a/drivers/soc/brcmstb/pm/Makefile b/drivers/soc/brcmstb/pm/Makefile
new file mode 100644
index 000000000000..5bb9d550d4de
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/Makefile
@@ -0,0 +1,2 @@
+obj-y				+= pm.o s2.o regsave.o
+obj-$(CONFIG_BRCMSTB_XPT_HASH)	+= xpt_dma.o
diff --git a/drivers/soc/brcmstb/pm/aon_defs.h b/drivers/soc/brcmstb/pm/aon_defs.h
new file mode 100644
index 000000000000..805b16da6246
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/aon_defs.h
@@ -0,0 +1,100 @@
+/*
+ * Always ON (AON) register interface between bootloader and Linux
+ *
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_AON_DEFS_H__
+#define __BRCMSTB_AON_DEFS_H__
+
+#include <linux/compiler.h>
+
+/* Magic number in upper 16-bits */
+#define BRCMSTB_S3_MAGIC_MASK                   0xffff0000
+#define BRCMSTB_S3_MAGIC_SHORT                  0x5AFE0000
+
+enum {
+	/* Restore random key for AES memory verification (off = fixed key) */
+	S3_FLAG_LOAD_RANDKEY		= (1 << 0),
+
+	/* Scratch buffer page table is present */
+	S3_FLAG_SCRATCH_BUFFER_TABLE	= (1 << 1),
+};
+
+#define BRCMSTB_HASH_LEN		(128 / 8) /* 128-bit hash */
+
+#define AON_REG_MAGIC_FLAGS			0x00
+#define AON_REG_CONTROL_LOW			0x04
+#define AON_REG_CONTROL_HIGH			0x08
+#define AON_REG_S3_HASH				0x0c /* hash of S3 params */
+#define AON_REG_CONTROL_HASH_LEN		0x1c
+#define AON_REG_PANIC				0x20
+
+#define BRCMSTB_S3_MAGIC		0x5AFEB007
+#define BRCMSTB_PANIC_MAGIC		0x512E115E
+#define BOOTLOADER_SCRATCH_SIZE		64
+#define IMAGE_DESCRIPTORS_BUFSIZE	(2 * 1024)
+/*
+ * Store up to 64 4KB page entries; this number is flexible, as long as
+ * brcmstb_bootloader_scratch_table::num_entries is adjusted accordingly
+ */
+#define BRCMSTB_SCRATCH_BUF_SIZE	(256 * 1024)
+
+struct brcmstb_bootloader_scratch_table {
+	/* System page size, in KB; likely 4 (i.e., 4KB) */
+	uint32_t page_size;
+	/*
+	 * Number of page entries in this table. Provided for flexibility, but
+	 * should be BRCMSTB_SCRATCH_BUF_SIZE / PAGE_SIZE
+	 */
+	uint16_t num_entries;
+	uint16_t reserved;
+	struct {
+		uint32_t upper;
+		uint32_t lower;
+	} entries[];
+} __packed;
+
+struct brcmstb_s3_params {
+	/* scratch memory for bootloader */
+	uint8_t scratch[BOOTLOADER_SCRATCH_SIZE];
+
+	uint32_t magic; /* BRCMSTB_S3_MAGIC */
+	uint64_t reentry; /* PA */
+
+	/* descriptors */
+	uint32_t hash[BRCMSTB_HASH_LEN / 4];
+
+	/*
+	 * If 0, then ignore this parameter (there is only one set of
+	 *   descriptors)
+	 *
+	 * If non-0, then a second set of descriptors is stored at:
+	 *
+	 *   descriptors + desc_offset_2
+	 *
+	 * The MAC result of both descriptors is XOR'd and stored in @hash
+	 */
+	uint32_t desc_offset_2;
+
+	/*
+	 * (Physical) address of a brcmstb_bootloader_scratch_table, for
+	 * providing a large DRAM buffer to the bootloader
+	 */
+	uint64_t buffer_table;
+
+	uint32_t spare[70];
+
+	uint8_t descriptors[IMAGE_DESCRIPTORS_BUFSIZE];
+} __packed;
+
+#endif /* __BRCMSTB_AON_DEFS_H__ */
diff --git a/drivers/soc/brcmstb/pm/pm.c b/drivers/soc/brcmstb/pm/pm.c
new file mode 100644
index 000000000000..b6a20faa37b4
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/pm.c
@@ -0,0 +1,1128 @@
+/*
+ * ARM-specific support for Broadcom STB S2/S3/S5 power management
+ *
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "brcmstb-pm: " fmt
+
+#ifdef CONFIG_BRCMSTB_PM_DEBUG
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#endif
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/suspend.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/compiler.h>
+#include <linux/pm.h>
+#include <linux/bitops.h>
+#include <linux/dma-mapping.h>
+#include <linux/sizes.h>
+#include <linux/kconfig.h>
+#include <linux/sort.h>
+#include <linux/notifier.h>
+#include <asm/fncpy.h>
+#include <asm/suspend.h>
+#include <asm/setup.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <soc/brcmstb/common.h>
+
+#include "pm.h"
+#include "aon_defs.h"
+#include "xpt_dma.h"
+
+#define BRCMSTB_DDR_PHY_PLL_STATUS	0x04
+
+#define SHIMPHY_DDR_PAD_CNTRL		0x8c
+#define SHIMPHY_PAD_PLL_SEQUENCE	BIT(8)
+#define SHIMPHY_PAD_GATE_PLL_S3		BIT(9)
+
+#define MAX_NUM_MEMC			3
+
+/* Capped for performance reasons */
+#define MAX_HASH_SIZE			SZ_256M
+/* Max per bank, to keep some fairness */
+#define MAX_HASH_SIZE_BANK		SZ_64M
+
+struct brcmstb_memc {
+	void __iomem *ddr_phy_base;
+	void __iomem *ddr_shimphy_base;
+};
+
+struct brcmstb_pm_control {
+	void __iomem *aon_ctrl_base;
+	void __iomem *aon_sram;
+	size_t aon_sram_len;
+	struct brcmstb_memc memcs[MAX_NUM_MEMC];
+
+	void __iomem *boot_sram;
+	size_t boot_sram_len;
+
+	bool support_warm_boot;
+	int num_memc;
+
+	struct brcmstb_s3_params *s3_params;
+	dma_addr_t s3_params_pa;
+};
+
+enum bsp_initiate_command {
+	BSP_CLOCK_STOP		= 0x00,
+	BSP_GEN_RANDOM_KEY	= 0x4A,
+	BSP_RESTORE_RANDOM_KEY	= 0x55,
+	BSP_GEN_FIXED_KEY	= 0x63,
+};
+
+#define PM_INITIATE		0x01
+#define PM_INITIATE_SUCCESS	0x00
+#define PM_INITIATE_FAIL	0xfe
+
+/* Several chips have an old PM_INITIATE interface that doesn't ACK commands */
+#define PM_INITIATE_NO_ACK	IS_ENABLED(CONFIG_BCM74371A0)
+
+static struct brcmstb_pm_control ctrl;
+static suspend_state_t suspend_state;
+
+#define MAX_EXCLUDE				16
+#define MAX_REGION				16
+#define MAX_EXTRA				8
+static int num_exclusions;
+static int num_regions;
+static struct dma_region exclusions[MAX_EXCLUDE];
+static struct dma_region regions[MAX_REGION];
+
+extern const unsigned long brcmstb_pm_do_s2_sz;
+extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
+		void __iomem *ddr_phy_pll_status);
+
+static int (*brcmstb_pm_do_s2_sram)(void __iomem *aon_ctrl_base,
+		void __iomem *ddr_phy_pll_status);
+
+#ifdef CONFIG_BRCMSTB_PM_DEBUG
+
+#define BRCMSTB_PM_DEBUG_NAME	"brcmstb-pm"
+
+struct sysfs_data {
+	struct dma_region *region;
+	unsigned len;
+};
+
+static int brcm_pm_debug_show(struct seq_file *s, void *data)
+{
+	int i;
+	struct sysfs_data *sysfs_data = s->private;
+
+	if (!sysfs_data) {
+		seq_puts(s, "--- No region pointer ---\n");
+		return 0;
+	}
+	if (sysfs_data->len == 0) {
+		seq_puts(s, "--- Nothing to display ---\n");
+		return 0;
+	}
+	if (!sysfs_data->region) {
+		seq_printf(s, "--- Pointer is NULL, but length is %u ---\n",
+			sysfs_data->len);
+		return 0;
+	}
+
+	for (i = 0; i < sysfs_data->len; i++) {
+		unsigned long addr = sysfs_data->region[i].addr;
+		unsigned long len = sysfs_data->region[i].len;
+		unsigned long end = (addr > 0 || len > 0) ? addr + len - 1 : 0;
+
+		seq_printf(s, "%3d\t0x%08lx\t%12lu\t0x%08lx\n", i, addr, len,
+			end);
+	}
+	return 0;
+}
+
+static ssize_t brcm_pm_seq_write(struct file *file, const char __user *buf,
+	size_t size, loff_t *ppos)
+{
+	unsigned long start_addr, len;
+	int ret;
+	char str[128];
+	char *len_ptr;
+	struct seq_file *s = file->private_data;
+	struct sysfs_data *sysfs_data = s->private;
+	bool is_exclusion;
+
+	if (!sysfs_data)
+		return -ENOMEM;
+
+	if (size >= sizeof(str))
+		return -E2BIG;
+
+	is_exclusion = (sysfs_data->region == exclusions);
+
+	memset(str, 0, sizeof(str));
+	ret = copy_from_user(str, buf, size);
+	if (ret)
+		return ret;
+
+	/* Strip trailing newline */
+	len_ptr = str + strlen(str) - 1;
+	while (*len_ptr == '\r' || *len_ptr == '\n')
+		*len_ptr-- = '\0';
+
+	/* Special command "clear" empties the exclusions or regions list. */
+	if (strcmp(str, "clear") == 0) {
+		int region_len = sysfs_data->len * sizeof(*sysfs_data->region);
+
+		if (is_exclusion)
+			num_exclusions = 0;
+		else
+			num_regions = 0;
+		memset(sysfs_data->region, 0, region_len);
+		return size;
+	}
+
+	/*
+	 * We expect userland input to be in the format
+	 *     <start-address> <length>
+	 * where start-address and length are separated by one or more spaces.
+	 * Both must be valid numbers. We do accept decimal, hexadecimal and
+	 * octal numbers.
+	 */
+	len_ptr = strchr(str, ' ');
+	if (!len_ptr)
+		return -EINVAL;
+	*len_ptr = '\0';
+	do {
+		len_ptr++;
+	} while (*len_ptr == ' ');
+
+	if (kstrtoul(str, 0, &start_addr) != 0)
+		return -EINVAL;
+	if (kstrtoul(len_ptr, 0, &len) != 0)
+		return -EINVAL;
+
+	if (is_exclusion)
+		ret = brcmstb_pm_mem_exclude(start_addr, len);
+	else
+		ret = brcmstb_pm_mem_region(start_addr, len);
+
+	return ret < 0 ? ret : size;
+}
+
+static int brcm_pm_debug_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, brcm_pm_debug_show, inode->i_private);
+}
+
+static const struct file_operations brcm_pm_debug_ops = {
+	.open		= brcm_pm_debug_open,
+	.read		= seq_read,
+	.write		= brcm_pm_seq_write,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int brcm_pm_debug_init(void)
+{
+	struct dentry *dir;
+	struct sysfs_data *exclusion_data, *region_data;
+
+	dir = debugfs_create_dir(BRCMSTB_PM_DEBUG_NAME, NULL);
+	if (IS_ERR_OR_NULL(dir))
+		return IS_ERR(dir) ? PTR_ERR(dir) : -ENOENT;
+
+	/*
+	 * This driver has no "exit" function, so we don't worry about freeing
+	 * these memory areas if setup succeeds.
+	 */
+	exclusion_data = kmalloc(sizeof(*exclusion_data), GFP_KERNEL);
+	if (!exclusion_data)
+		return -ENOMEM;
+	region_data = kmalloc(sizeof(*region_data), GFP_KERNEL);
+	if (!region_data) {
+		kfree(exclusion_data);
+		return -ENOMEM;
+	}
+
+	exclusion_data->region = exclusions;
+	exclusion_data->len = ARRAY_SIZE(exclusions);
+	region_data->region = regions;
+	region_data->len = ARRAY_SIZE(regions);
+
+	debugfs_create_file("exclusions", S_IFREG | S_IRUGO | S_IWUSR, dir,
+		exclusion_data, &brcm_pm_debug_ops);
+	debugfs_create_file("regions", S_IFREG | S_IRUGO | S_IWUSR, dir,
+		region_data, &brcm_pm_debug_ops);
+
+	return 0;
+}
+
+fs_initcall(brcm_pm_debug_init);
+
+#endif /* CONFIG_BRCMSTB_PM_DEBUG */
+
+static int brcmstb_init_sram(struct device_node *dn)
+{
+	void __iomem *sram;
+	struct resource res;
+	int ret;
+
+	ret = of_address_to_resource(dn, 0, &res);
+	if (ret)
+		return ret;
+
+	/* Cached, executable remapping of SRAM */
+	sram = __arm_ioremap_exec(res.start, resource_size(&res), true);
+	if (!sram)
+		return -ENOMEM;
+
+	ctrl.boot_sram = sram;
+	ctrl.boot_sram_len = resource_size(&res);
+
+	return 0;
+}
+
+/*
+ * Latch into the BRCM SRAM compatible property here to be more specific than
+ * the standard "mmio-sram"
+ *
+ * FIXME: As of Linux 3.10, upstream's drivers/misc/sram.c should support
+ * allocating SRAM via genalloc
+ */
+static struct of_device_id sram_dt_ids[] = {
+	{ .compatible = "brcm,boot-sram" },
+	{}
+};
+
+static int do_bsp_initiate_command(enum bsp_initiate_command cmd)
+{
+	void __iomem *base = ctrl.aon_ctrl_base;
+	int ret;
+	int timeo = 1000 * 1000; /* 1 second */
+
+	__raw_writel(0, base + AON_CTRL_PM_INITIATE);
+	(void)__raw_readl(base + AON_CTRL_PM_INITIATE);
+
+	/* Go! */
+	__raw_writel((cmd << 1) | PM_INITIATE, base + AON_CTRL_PM_INITIATE);
+
+	/*
+	 * If firmware doesn't support the 'ack', then just assume it's done
+	 * after 10ms. Note that this only works for command 0, BSP_CLOCK_STOP
+	 */
+	if (PM_INITIATE_NO_ACK) {
+		(void)__raw_readl(base + AON_CTRL_PM_INITIATE);
+		mdelay(10);
+		return 0;
+	}
+
+	for (;;) {
+		ret = __raw_readl(base + AON_CTRL_PM_INITIATE);
+		if (!(ret & PM_INITIATE))
+			break;
+		if (timeo <= 0) {
+			pr_err("error: timeout waiting for BSP (%x)\n", ret);
+			break;
+		}
+		timeo -= 50;
+		udelay(50);
+	}
+
+	return (ret & 0xff) != PM_INITIATE_SUCCESS;
+}
+
+static int brcmstb_pm_handshake(void)
+{
+	void __iomem *base = ctrl.aon_ctrl_base;
+	u32 tmp;
+	int ret;
+
+	/* BSP power handshake, v1 */
+	tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
+	tmp &= ~1UL;
+	__raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS);
+	(void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS);
+
+	ret = do_bsp_initiate_command(BSP_CLOCK_STOP);
+	if (ret)
+		pr_err("BSP handshake failed\n");
+
+	/*
+	 * HACK: BSP may have internal race on the CLOCK_STOP command.
+	 * Avoid touching the BSP for a few milliseconds.
+	 */
+	mdelay(3);
+
+	return ret;
+}
+
+/*
+ * Run a Power Management State Machine (PMSM) shutdown command and put the CPU
+ * into a low-power mode
+ */
+static void brcmstb_do_pmsm_power_down(unsigned long base_cmd)
+{
+	void __iomem *base = ctrl.aon_ctrl_base;
+
+	/* pm_start_pwrdn transition 0->1 */
+	__raw_writel(base_cmd, base + AON_CTRL_PM_CTRL);
+	(void)__raw_readl(base + AON_CTRL_PM_CTRL);
+
+	__raw_writel(base_cmd | PM_PWR_DOWN, base + AON_CTRL_PM_CTRL);
+	(void)__raw_readl(base + AON_CTRL_PM_CTRL);
+
+	wfi();
+}
+
+/* Support S5 cold boot out of "poweroff" */
+static void brcmstb_pm_poweroff(void)
+{
+	brcmstb_pm_handshake();
+
+	/* Clear magic S3 warm-boot value */
+	__raw_writel(0, ctrl.aon_sram + AON_REG_MAGIC_FLAGS);
+	(void)__raw_readl(ctrl.aon_sram + AON_REG_MAGIC_FLAGS);
+
+	/* Skip wait-for-interrupt signal; just use a countdown */
+	__raw_writel(0x10, ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT);
+	(void)__raw_readl(ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT);
+
+	brcmstb_do_pmsm_power_down(PM_COLD_CONFIG);
+}
+
+static void *brcmstb_pm_copy_to_sram(void *fn, size_t len)
+{
+	unsigned int size = ALIGN(len, FNCPY_ALIGN);
+
+	if (ctrl.boot_sram_len < size) {
+		pr_err("standby code will not fit in SRAM\n");
+		return NULL;
+	}
+
+	return fncpy(ctrl.boot_sram, fn, size);
+}
+
+static int brcmstb_pm_s2(void)
+{
+	brcmstb_pm_do_s2_sram = brcmstb_pm_copy_to_sram(&brcmstb_pm_do_s2,
+			brcmstb_pm_do_s2_sz);
+	if (!brcmstb_pm_do_s2_sram)
+		return -EINVAL;
+
+	return brcmstb_pm_do_s2_sram(ctrl.aon_ctrl_base,
+			ctrl.memcs[0].ddr_phy_base +
+			BRCMSTB_DDR_PHY_PLL_STATUS);
+}
+
+static int brcmstb_pm_s3_control_hash(struct brcmstb_s3_params *params,
+		phys_addr_t params_pa)
+{
+	size_t hash_len = sizeof(*params) - BOOTLOADER_SCRATCH_SIZE;
+	struct dma_region region[] = {
+		{
+			.addr	= params_pa + BOOTLOADER_SCRATCH_SIZE,
+			.len	= hash_len,
+		},
+	};
+	uint32_t hash[BRCMSTB_HASH_LEN / 4];
+	int i, ret;
+
+	/* Co-opt bootloader scratch area temporarily */
+	ret = memdma_prepare_descs((struct mcpb_dma_desc *)params->scratch,
+				   params_pa, region, ARRAY_SIZE(region), true);
+	if (ret)
+		return ret;
+
+	dma_sync_single_for_device(NULL, params_pa, sizeof(*params),
+				   DMA_TO_DEVICE);
+
+	ret = memdma_run(params_pa, 0, false);
+	if (ret)
+		return ret;
+
+	get_hash(hash, false);
+
+	/* Store hash in AON */
+	for (i = 0; i < BRCMSTB_HASH_LEN / 4; i++)
+		__raw_writel(hash[i], ctrl.aon_sram + AON_REG_S3_HASH + i * 4);
+	__raw_writel(hash_len, ctrl.aon_sram + AON_REG_CONTROL_HASH_LEN);
+
+	return 0;
+}
+
+static inline int region_collision(struct dma_region *reg1,
+				   struct dma_region *reg2)
+{
+	return (reg1->addr + reg1->len > reg2->addr) &&
+	       (reg2->addr + reg2->len > reg1->addr);
+}
+
+/**
+ * Check if @regions[0] collides with regions in @exceptions, and modify
+ * regions[0..(max-1)] to ensure that they they exclude any area in @exceptions
+ *
+ * Note that the regions in @exceptions must be sorted into ascending order
+ * prior to calling this function
+ *
+ * Returns the number of @regions used
+ *
+ * e.g., if @regions[0] and @exceptions do not overlap, return 1 and do nothing
+ *       if @exceptions contains two ranges and both are entirely contained
+ *          within @regions[0], split @regions[0] into @regions[0],
+ *          @regions[1], and @regions[2], and return 3
+ */
+static int region_handle_collisions(struct dma_region *regions, int max,
+				struct dma_region *exceptions, int num_except)
+{
+	int i;
+	struct dma_region *reg = &regions[0];
+	int reg_count = 1;
+
+	/*
+	 * Since the list of regions is ordered in ascending order we need only
+	 * to compare the last entry in regions against each exception region
+	 */
+	for (i = 0; i < num_except; i++) {
+		struct dma_region *except = &exceptions[i];
+		dma_addr_t start = reg->addr;
+		dma_addr_t end = reg->addr + reg->len;
+
+		if (!region_collision(reg, except))
+			/* No collision */
+			continue;
+
+		if (start < except->addr && end > except->addr + except->len) {
+			reg->len = except->addr - start;
+			if (reg_count < max) {
+				/* Split in 2 */
+				reg++;
+				reg_count++;
+				reg->addr = except->addr + except->len;
+				reg->len = end - reg->addr;
+			} else {
+				pr_warn("Not enough space to split region\n");
+				break;
+			}
+		} else if (start < except->addr) {
+			/* Overlap at right edge; truncate end of 'reg' */
+			reg->len = except->addr - start;
+		} else if (end > except->addr + except->len) {
+			/* Overlap at left edge; truncate beginning of 'reg' */
+			reg->addr = except->addr + except->len;
+			reg->len = end - reg->addr;
+		} else {
+			/*
+			 * 'reg' is entirely contained within 'except'?  This
+			 * should not happen, but trim to zero-length just in
+			 * case
+			 */
+			reg->len = 0;
+			reg_count--;
+			break;
+		}
+	}
+
+	return reg_count;
+}
+
+static int dma_region_compare(const void *a, const void *b)
+{
+	struct dma_region *reg_a = (struct dma_region *)a;
+	struct dma_region *reg_b = (struct dma_region *)b;
+
+	if (reg_a->addr < reg_b->addr)
+		return -1;
+	if (reg_a->addr > reg_b->addr)
+		return 1;
+	return 0;
+}
+
+/* Initialize the DMA region list and return the number of regions */
+static int configure_main_hash(struct dma_region *regions, int max,
+			       struct dma_region *exclude, int num_exclude)
+{
+	int idx = 0, bank_nr;
+	size_t total = 0;
+
+	/*
+	 * First sort the excluded regions in ascending order. This makes things
+	 * easier when we come to adding the regions since we avoid having to
+	 * add entries in the middle of the region list
+	 */
+	sort(exclude, num_exclude, sizeof(exclude[0]), &dma_region_compare,
+			NULL);
+
+	/*
+	 * Hash up to MAX_HASH_SIZE_BANK from each memory bank, with a
+	 * total limit of MAX_HASH_SIZE. Account for collisions with the
+	 * 'exclude' regions.
+	 */
+	for_each_bank(bank_nr, &meminfo) {
+		const struct membank *bank = &meminfo.bank[bank_nr];
+		struct dma_region *reg = &regions[idx];
+		int i, count;
+		size_t bank_total = 0;
+
+		reg->addr = bank->start;
+		reg->len = bank->size;
+
+		/*
+		 * Check for collisions with the excluded regions.  'reg' may be
+		 * split into 0 to (num_exclude + 1) segments, so account
+		 * accordingly
+		 */
+		count = region_handle_collisions(reg, max - idx, exclude,
+						 num_exclude);
+
+		/*
+		 * Add region length(s) to total. Cap at MAX_HASH_SIZE_BANK
+		 * per bank and MAX_HASH_SIZE total.
+		 */
+		for (i = 0; i < count; i++) {
+			/* Don't create 0-sized regions */
+			if (total >= MAX_HASH_SIZE)
+				break;
+			if (bank_total >= MAX_HASH_SIZE_BANK)
+				break;
+			if (total + reg[i].len > MAX_HASH_SIZE)
+				reg[i].len = MAX_HASH_SIZE - total;
+			if (bank_total + reg[i].len > MAX_HASH_SIZE_BANK)
+				reg[i].len = MAX_HASH_SIZE_BANK - bank_total;
+			total += reg[i].len;
+			bank_total += reg[i].len;
+		}
+
+		idx += i;
+
+		if (idx >= max)
+			break;
+
+		/* Apply total cap */
+		if (total >= MAX_HASH_SIZE)
+			break;
+	}
+
+	return idx;
+}
+
+/*
+ * Run a DMA hash on the given regions, splitting evenly into two channels if
+ * possible
+ *
+ * If 2 channels were run, return the byte offset of the second (from descs_pa)
+ * If 1 channel was run, return 0
+ * Otherwise (on errors) return negative
+ */
+static int run_dual_hash(struct dma_region *regions, int numregions,
+		struct mcpb_dma_desc *descs, phys_addr_t descs_pa,
+		uint32_t *hash)
+{
+	phys_addr_t pa1, pa2;
+	struct mcpb_dma_desc *desc1, *desc2;
+	int regions1, regions2;
+	int ret;
+
+	/* Split regions into 2 partitions */
+	regions2 = numregions / 2;
+	regions1 = numregions - regions2;
+	desc1 = descs;
+	desc2 = desc1 + regions1;
+	pa1 = descs_pa;
+	pa2 = pa1 + regions1 * sizeof(*desc1);
+
+	/* Prepare both sets of descriptors */
+	ret = memdma_prepare_descs(desc1, pa1, &regions[0], regions1, true);
+	if (ret)
+		return ret;
+	ret = memdma_prepare_descs(desc2, pa2, &regions[regions1], regions2,
+		false);
+	if (ret)
+		return ret;
+
+	dma_sync_single_for_device(NULL, pa1, sizeof(*desc1) * numregions,
+				   DMA_TO_DEVICE);
+
+	/* Go! */
+	ret = memdma_run(pa1, pa2, !!regions2);
+	if (ret)
+		return ret;
+
+	get_hash(hash, !!regions2);
+
+	if (regions2)
+		return regions1 * sizeof(*desc1);
+	else
+		return 0;
+}
+
+static int brcmstb_pm_s3_main_memory_hash(struct brcmstb_s3_params *params,
+		phys_addr_t params_pa, struct dma_region *except,
+		int num_except)
+{
+	struct dma_region combined_regions[MAX_EXCLUDE + MAX_REGION + MAX_EXTRA];
+	phys_addr_t descs_pa;
+	struct mcpb_dma_desc *descs;
+	int nregs, ret, i;
+	const int max = ARRAY_SIZE(combined_regions);
+
+	memset(&combined_regions, 0, sizeof(combined_regions));
+	nregs = configure_main_hash(combined_regions, max, except, num_except);
+	if (nregs < 0)
+		return nregs;
+
+	for (i = 0; i < num_regions && nregs + i < max; i++)
+		combined_regions[nregs + i] = regions[i];
+	nregs += i;
+
+	/* Flush out before hashing main memory */
+	flush_cache_all();
+
+	/* Get base pointers */
+	descs_pa = params_pa + offsetof(struct brcmstb_s3_params, descriptors);
+	descs = (struct mcpb_dma_desc *)params->descriptors;
+
+	/* Split, run hash */
+	ret = run_dual_hash(combined_regions, nregs, descs, descs_pa,
+		params->hash);
+	if (ret < 0)
+		return ret;
+	params->desc_offset_2 = ret;
+
+	return 0;
+}
+
+int brcmstb_pm_mem_exclude(phys_addr_t addr, size_t len)
+{
+	if (num_exclusions >= MAX_EXCLUDE) {
+		pr_err("exclusion list is full\n");
+		return -ENOSPC;
+	}
+
+	exclusions[num_exclusions].addr = addr;
+	exclusions[num_exclusions].len = len;
+	num_exclusions++;
+
+	return 0;
+}
+EXPORT_SYMBOL(brcmstb_pm_mem_exclude);
+
+int brcmstb_pm_mem_region(phys_addr_t addr, size_t len)
+{
+	if (num_regions >= MAX_REGION) {
+		pr_err("regions list is full\n");
+		return -ENOSPC;
+	}
+
+	regions[num_regions].addr = addr;
+	regions[num_regions].len = len;
+	num_regions++;
+
+	return 0;
+}
+EXPORT_SYMBOL(brcmstb_pm_mem_region);
+
+/*
+ * This function is called on a new stack, so don't allow inlining (which will
+ * generate stack references on the old stack)
+ */
+static noinline int brcmstb_pm_s3_finish(void)
+{
+	struct brcmstb_s3_params *params = ctrl.s3_params;
+	phys_addr_t params_pa = ctrl.s3_params_pa;
+	phys_addr_t reentry = virt_to_phys(&cpu_resume);
+	u32 flags = 0;
+	enum bsp_initiate_command cmd;
+	int i, ret, num_exclude;
+
+	ret = brcmstb_pm_mem_exclude(params_pa, sizeof(*params));
+	if (ret) {
+		pr_err("failed to add parameter exclusion region\n");
+		return ret;
+	}
+
+	/* Clear parameter structure */
+	memset(params, 0, sizeof(*params));
+
+	flags |= S3_FLAG_LOAD_RANDKEY; /* TODO: make this selectable */
+
+	/* Load random / fixed key */
+	if (flags & S3_FLAG_LOAD_RANDKEY)
+		cmd = BSP_GEN_RANDOM_KEY;
+	else
+		cmd = BSP_GEN_FIXED_KEY;
+	if (do_bsp_initiate_command(cmd)) {
+		pr_info("key loading failed\n");
+		return -EIO;
+	}
+
+	/* Reset exclusion regions */
+	num_exclude = num_exclusions;
+	num_exclusions = 0;
+
+	/* Hash main memory */
+	ret = brcmstb_pm_s3_main_memory_hash(params, params_pa, exclusions,
+					     num_exclude);
+	if (ret)
+		return ret;
+
+	params->magic = BRCMSTB_S3_MAGIC;
+	params->reentry = reentry;
+
+	/* No more writes to DRAM */
+	flush_cache_all();
+
+	/* Hash S3 saved parameters */
+	ret = brcmstb_pm_s3_control_hash(params, params_pa);
+	if (ret)
+		return ret;
+
+	flags |= BRCMSTB_S3_MAGIC_SHORT;
+
+	__raw_writel(flags, ctrl.aon_sram + AON_REG_MAGIC_FLAGS);
+	__raw_writel(lower_32_bits(params_pa),
+		     ctrl.aon_sram + AON_REG_CONTROL_LOW);
+	__raw_writel(upper_32_bits(params_pa),
+		     ctrl.aon_sram + AON_REG_CONTROL_HIGH);
+
+	/* gate PLL | S3 */
+	for (i = 0; i < ctrl.num_memc; i++) {
+		u32 tmp;
+		tmp = __raw_readl(ctrl.memcs[i].ddr_shimphy_base +
+				SHIMPHY_DDR_PAD_CNTRL);
+		tmp |= SHIMPHY_PAD_GATE_PLL_S3 | SHIMPHY_PAD_PLL_SEQUENCE;
+		__raw_writel(tmp, ctrl.memcs[i].ddr_shimphy_base +
+				SHIMPHY_DDR_PAD_CNTRL);
+	}
+
+	brcmstb_do_pmsm_power_down(PM_WARM_CONFIG);
+
+	/* Must have been interrupted from wfi()? */
+	return -EINTR;
+}
+
+#define SWAP_STACK(new_sp, saved_sp) \
+	__asm__ __volatile__ ( \
+		 "mov	%[save], sp\n" \
+		 "mov	sp, %[new]\n" \
+		 : [save] "=&r" (saved_sp) \
+		 : [new] "r" (new_sp) \
+		)
+
+static int brcmstb_pm_do_s3(unsigned long sp)
+{
+	unsigned long save_sp;
+	int ret;
+
+	/* Move to a new stack */
+	SWAP_STACK(sp, save_sp);
+
+	/* should not return */
+	ret = brcmstb_pm_s3_finish();
+
+	SWAP_STACK(save_sp, sp);
+
+	pr_err("Could not enter S3\n");
+
+	return ret;
+}
+
+static int brcmstb_pm_s3(void)
+{
+	void __iomem *sp = ctrl.boot_sram + ctrl.boot_sram_len - 8;
+
+	return cpu_suspend((unsigned long)sp, brcmstb_pm_do_s3);
+}
+
+static int brcmstb_pm_standby(bool deep_standby)
+{
+	int ret;
+
+	if (brcmstb_pm_handshake())
+		return -EIO;
+
+	if (deep_standby)
+		ret = brcmstb_pm_s3();
+	else
+		ret = brcmstb_pm_s2();
+	if (ret)
+		pr_err("%s: standby failed\n", __func__);
+
+	return ret;
+}
+
+static int brcmstb_pm_begin(suspend_state_t state)
+{
+	suspend_state = state;
+	return 0;
+}
+
+static int brcmstb_pm_prepare(void)
+{
+	/* TODO: initialize memory hashing (for S3) here? */
+	return 0;
+}
+
+static int brcmstb_pm_enter(suspend_state_t unused)
+{
+	int ret = -EINVAL;
+
+	switch (suspend_state) {
+	case PM_SUSPEND_STANDBY:
+		ret = brcmstb_pm_standby(false);
+		break;
+	case PM_SUSPEND_MEM:
+		ret = brcmstb_pm_standby(true);
+		break;
+	}
+
+	return ret;
+}
+
+static void brcmstb_pm_end(void)
+{
+	suspend_state = PM_SUSPEND_ON;
+}
+
+static int brcmstb_pm_valid(suspend_state_t state)
+{
+	switch (state) {
+	case PM_SUSPEND_STANDBY:
+		return true;
+	case PM_SUSPEND_MEM:
+		return ctrl.support_warm_boot;
+	default:
+		return false;
+	}
+}
+
+static const struct platform_suspend_ops brcmstb_pm_ops = {
+	.begin		= brcmstb_pm_begin,
+	.end		= brcmstb_pm_end,
+	.prepare	= brcmstb_pm_prepare,
+	.enter		= brcmstb_pm_enter,
+	.valid		= brcmstb_pm_valid,
+};
+
+static struct of_device_id aon_ctrl_dt_ids[] = {
+	{ .compatible = "brcm,brcmstb-aon-ctrl" },
+	{}
+};
+
+struct ddr_phy_ofdata {
+	bool supports_warm_boot;
+};
+
+static struct ddr_phy_ofdata ddr_phy_225_1 = { .supports_warm_boot = false, };
+static struct ddr_phy_ofdata ddr_phy_240_1 = { .supports_warm_boot = true, };
+
+static struct of_device_id ddr_phy_dt_ids[] = {
+	{
+		.compatible = "brcm,brcmstb-ddr-phy-v225.1",
+		.data = &ddr_phy_225_1,
+	},
+	{
+		.compatible = "brcm,brcmstb-ddr-phy-v240.1",
+		.data = &ddr_phy_240_1,
+	},
+	{
+		/* Same as v240.1, for the registers we care about */
+		.compatible = "brcm,brcmstb-ddr-phy-v240.2",
+		.data = &ddr_phy_240_1,
+	},
+	{}
+};
+
+static struct of_device_id ddr_shimphy_dt_ids[] = {
+	{ .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" },
+	{}
+};
+
+static void __iomem *brcmstb_ioremap_node(struct device_node *dn, int index,
+		size_t *retlen)
+{
+	struct resource res, *res2;
+	int ret;
+	void __iomem *base;
+	size_t len;
+
+	if (retlen)
+		*retlen = 0;
+
+	ret = of_address_to_resource(dn, index, &res);
+	if (ret < 0)
+		return ERR_PTR(ret);
+
+	len = resource_size(&res);
+
+	res2 = request_mem_region(res.start, len, dn->full_name);
+	if (!res2)
+		return ERR_PTR(-EIO);
+
+	base = ioremap(res2->start, resource_size(res2));
+	if (!base) {
+		release_mem_region(res.start, len);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	if (retlen)
+		*retlen = len;
+
+	return base;
+}
+
+static void __iomem *brcmstb_ioremap_match(struct of_device_id *matches,
+					    int index, size_t *retlen,
+					    const void **ofdata)
+{
+	struct device_node *dn;
+	const struct of_device_id *match;
+	void __iomem *base;
+
+	dn = of_find_matching_node_and_match(NULL, matches, &match);
+	if (!dn)
+		return ERR_PTR(-EINVAL);
+
+	base = brcmstb_ioremap_node(dn, index, retlen);
+
+	if (ofdata)
+		*ofdata = match->data;
+
+	return base;
+}
+
+static int brcmstb_pm_panic_notify(struct notifier_block *nb,
+		unsigned long action, void *data)
+{
+	__raw_writel(BRCMSTB_PANIC_MAGIC,
+		ctrl.aon_sram + AON_REG_PANIC);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block brcmstb_pm_panic_nb = {
+	.notifier_call = brcmstb_pm_panic_notify,
+};
+
+static int brcmstb_pm_init(void)
+{
+	struct device_node *dn;
+	void __iomem *base;
+	int ret, i;
+	const struct ddr_phy_ofdata *ddr_phy_data;
+
+	if (!soc_is_brcmstb())
+		return 0;
+
+	/* AON ctrl registers */
+	base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL, NULL);
+	if (IS_ERR_OR_NULL(base)) {
+		pr_err("error mapping AON_CTRL\n");
+		return PTR_ERR(base);
+	}
+	ctrl.aon_ctrl_base = base;
+
+	/* AON SRAM registers */
+	base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, &ctrl.aon_sram_len,
+				     NULL);
+	if (IS_ERR_OR_NULL(base)) {
+		/* Assume standard offset */
+		ctrl.aon_sram = ctrl.aon_ctrl_base +
+				     AON_CTRL_SYSTEM_DATA_RAM_OFS;
+	} else {
+		ctrl.aon_sram = base;
+	}
+
+	__raw_writel(0, ctrl.aon_sram + AON_REG_PANIC);
+
+	/* DDR PHY registers */
+	base = brcmstb_ioremap_match(ddr_phy_dt_ids, 0, NULL,
+				     (const void **)&ddr_phy_data);
+	if (IS_ERR_OR_NULL(base)) {
+		pr_err("error mapping DDR PHY\n");
+		return PTR_ERR(base);
+	}
+	ctrl.support_warm_boot = ddr_phy_data->supports_warm_boot;
+	/* Only need DDR PHY 0 for now? */
+	ctrl.memcs[0].ddr_phy_base = base;
+
+	/* DDR SHIM-PHY registers */
+	for_each_matching_node(dn, ddr_shimphy_dt_ids) {
+		i = ctrl.num_memc;
+		if (i >= MAX_NUM_MEMC) {
+			pr_warn("too many MEMCs (max %d)\n", MAX_NUM_MEMC);
+			break;
+		}
+		base = brcmstb_ioremap_node(dn, 0, NULL);
+		if (IS_ERR_OR_NULL(base)) {
+			if (!ctrl.support_warm_boot)
+				break;
+
+			pr_err("error mapping DDR SHIMPHY %d\n", i);
+			return PTR_ERR(base);
+		}
+		ctrl.memcs[i].ddr_shimphy_base = base;
+		ctrl.num_memc++;
+	}
+
+	dn = of_find_matching_node(NULL, sram_dt_ids);
+	if (!dn) {
+		pr_err("SRAM not found\n");
+		return -EINVAL;
+	}
+
+	ret = brcmstb_init_sram(dn);
+	if (ret) {
+		pr_err("error setting up SRAM for PM\n");
+		return ret;
+	}
+
+	ctrl.s3_params = kmalloc(sizeof(*ctrl.s3_params), GFP_KERNEL);
+	if (!ctrl.s3_params)
+		return -ENOMEM;
+	ctrl.s3_params_pa = dma_map_single(NULL, ctrl.s3_params,
+					   sizeof(*ctrl.s3_params),
+					   DMA_TO_DEVICE);
+	if (dma_mapping_error(NULL, ctrl.s3_params_pa)) {
+		pr_err("error mapping DMA memory\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = brcmstb_regsave_init();
+	if (ret)
+		goto out2;
+
+	atomic_notifier_chain_register(&panic_notifier_list,
+				       &brcmstb_pm_panic_nb);
+
+	pm_power_off = brcmstb_pm_poweroff;
+	suspend_set_ops(&brcmstb_pm_ops);
+	return 0;
+
+out2:
+	dma_unmap_single(NULL, ctrl.s3_params_pa, sizeof(*ctrl.s3_params),
+			 DMA_TO_DEVICE);
+out:
+	kfree(ctrl.s3_params);
+
+	pr_warn("PM: initialization failed with code %d\n", ret);
+
+	return ret;
+}
+
+arch_initcall(brcmstb_pm_init);
diff --git a/drivers/soc/brcmstb/pm/pm.h b/drivers/soc/brcmstb/pm/pm.h
new file mode 100644
index 000000000000..fadab6dc424a
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/pm.h
@@ -0,0 +1,40 @@
+/*
+ * Definitions for Broadcom STB power management / Always ON (AON) block
+ *
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_PM_H__
+#define __BRCMSTB_PM_H__
+
+#define AON_CTRL_RESET_CTRL		0x00
+#define AON_CTRL_PM_CTRL		0x04
+#define AON_CTRL_PM_STATUS		0x08
+#define AON_CTRL_PM_CPU_WAIT_COUNT	0x10
+#define AON_CTRL_PM_INITIATE		0x88
+#define AON_CTRL_HOST_MISC_CMDS		0x8c
+#define AON_CTRL_SYSTEM_DATA_RAM_OFS	0x200
+
+/* PM_CTRL bitfield */
+#define PM_FAST_PWRDOWN			(1 << 6)
+#define PM_WARM_BOOT			(1 << 5)
+#define PM_DEEP_STANDBY			(1 << 4)
+#define PM_CPU_PWR			(1 << 3)
+#define PM_USE_CPU_RDY			(1 << 2)
+#define PM_PLL_PWRDOWN			(1 << 1)
+#define PM_PWR_DOWN			(1 << 0)
+
+#define PM_S2_COMMAND	(PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN)
+#define PM_COLD_CONFIG	(PM_PLL_PWRDOWN | PM_DEEP_STANDBY)
+#define PM_WARM_CONFIG	(PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT)
+
+#endif /* __BRCMSTB_PM_H__ */
diff --git a/drivers/soc/brcmstb/pm/regsave.c b/drivers/soc/brcmstb/pm/regsave.c
new file mode 100644
index 000000000000..9d7b363ed222
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/regsave.c
@@ -0,0 +1,148 @@
+/*
+ * Support for Broadcom STB reg save for power management
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+
+struct brcmstb_reg_group {
+	void __iomem *regs;
+	unsigned int count;
+};
+static struct brcmstb_reg_group *reg_groups;
+static int num_reg_groups;
+static u32 *reg_mem;
+
+static int reg_save(void)
+{
+	int i;
+	unsigned int j, total;
+
+	if (0 == num_reg_groups)
+		return 0;
+
+	for (i = 0, total = 0; i < num_reg_groups; i++) {
+		struct brcmstb_reg_group *p = &reg_groups[i];
+		for (j = 0; j < p->count; j++)
+			reg_mem[total++] = __raw_readl(p->regs + (j * 4));
+	}
+	return 0;
+}
+
+
+static void reg_restore(void)
+{
+	int i;
+	unsigned int j, total;
+
+	if (0 == num_reg_groups)
+		return;
+
+	for (i = 0, total = 0; i < num_reg_groups; i++) {
+		struct brcmstb_reg_group *p = &reg_groups[i];
+		for (j = 0; j < p->count; j++)
+			__raw_writel(reg_mem[total++], p->regs + (j * 4));
+	}
+}
+
+
+static struct syscore_ops regsave_pm_ops = {
+	.suspend        = reg_save,
+	.resume         = reg_restore,
+};
+
+
+int brcmstb_regsave_init(void)
+{
+	struct resource res;
+	struct device_node *dn, *pp;
+	int ret = 0, len, num_phandles = 0, i;
+	unsigned int total;
+	resource_size_t size;
+	const char *name;
+
+
+	dn = of_find_node_by_name(NULL, "s3");
+	if (!dn)
+		/* FIXME: return -EINVAL when all bolts have 's3' node */
+		goto fail;
+
+	if (of_get_property(dn, "syscon-refs", &len))
+		name = "syscon-refs";
+	else if (of_get_property(dn, "regsave-refs", &len))
+		name = "regsave-refs";
+	else
+		/* FIXME: return -EINVAL when all bolts have 'syscon-refs' */
+		goto fail;
+
+	num_phandles = len / 4;
+	reg_groups = kzalloc(num_phandles * sizeof(struct brcmstb_reg_group),
+			    GFP_KERNEL);
+	if (reg_groups == NULL) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	for (i = 0; i < num_phandles; i++) {
+		void __iomem *regs;
+
+		pp = of_parse_phandle(dn, name, i);
+		if (!pp) {
+			ret = -EIO;
+			goto fail;
+		}
+		ret = of_address_to_resource(pp, 0, &res);
+		if (ret)
+			goto fail;
+		size = resource_size(&res);
+		regs = ioremap(res.start, size);
+		if (!regs) {
+			ret = -EIO;
+			goto fail;
+		}
+
+		reg_groups[num_reg_groups].regs = regs;
+		reg_groups[num_reg_groups].count = (unsigned) (size >> 2);
+		num_reg_groups++;
+	};
+
+	for (i = 0, total = 0; i < num_reg_groups; i++)
+		total += reg_groups[i].count;
+	reg_mem = kmalloc(total * sizeof(u32), GFP_KERNEL);
+	if (!reg_mem) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+	of_node_put(dn);
+	register_syscore_ops(&regsave_pm_ops);
+	return 0;
+fail:
+	if (reg_groups) {
+		for (i = 0; i < num_phandles; i++)
+			if (reg_groups[i].regs)
+				iounmap(reg_groups[i].regs);
+			else
+				break;
+		kfree(reg_groups);
+	}
+	kfree(reg_mem);
+	of_node_put(dn);
+	return ret;
+}
diff --git a/drivers/soc/brcmstb/pm/s2.S b/drivers/soc/brcmstb/pm/s2.S
new file mode 100644
index 000000000000..704c4ecb6f6f
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/s2.S
@@ -0,0 +1,73 @@
+/*
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#include "pm.h"
+
+	.text
+	.align	3
+
+#define AON_CTRL_REG		r10
+#define DDR_PHY_STATUS_REG	r11
+
+/*
+ * r0: AON_CTRL base address
+ * r1: DDRY PHY PLL status register address
+ */
+ENTRY(brcmstb_pm_do_s2)
+	stmfd	sp!, {r4-r11, lr}
+	mov	AON_CTRL_REG, r0
+	mov	DDR_PHY_STATUS_REG, r1
+
+	/* Flush memory transactions */
+	dsb
+
+	/* power down request */
+	ldr	r0, =PM_S2_COMMAND
+	ldr	r1, =0
+	str	r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+	ldr	r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+	str	r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+	ldr	r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+
+	/* Wait for interrupt */
+	wfi
+	nop
+
+	/* Bring MEMC back up */
+1:	ldr	r0, [DDR_PHY_STATUS_REG]
+	ands	r0, #1
+	beq	1b
+
+	/* Power-up handshake */
+	ldr	r0, =1
+	str	r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
+	ldr	r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
+
+	ldr	r0, =0
+	str	r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+	ldr	r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
+
+	/* Return to caller */
+	ldr	r0, =0
+	ldmfd	sp!, {r4-r11, pc}
+
+	ENDPROC(brcmstb_pm_do_s2)
+
+	/* Place literal pool here */
+	.ltorg
+
+ENTRY(brcmstb_pm_do_s2_sz)
+	.word   . - brcmstb_pm_do_s2
diff --git a/drivers/soc/brcmstb/pm/xpt_dma.c b/drivers/soc/brcmstb/pm/xpt_dma.c
new file mode 100644
index 000000000000..2da990feab03
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/xpt_dma.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+
+#include "xpt_dma.h"
+
+/* descriptor flags and shifts */
+#define MCPB_DW2_LAST_DESC		(1 << 0)
+
+#define MCPB_DW4_PUSH_PARTIAL_PKT	(1 << 28)
+
+#define MCPB_DW5_ENDIAN_STRAP_INV  (1 << 21)
+#define MCPB_DW5_PID_CHANNEL_VALID (1 << 19)
+#define MCPB_DW5_SCRAM_END         (1 << 18)
+#define MCPB_DW5_SCRAM_START       (1 << 17)
+#define MCPB_DW5_SCRAM_INIT        (1 << 16)
+
+#define MEMDMA_DRAM_REQ_SIZE	256
+
+#define XPT_MAC_OFFSET		0x14
+
+#define MCPB_CHx_SPACING(channel) \
+	((BCHP_XPT_MEMDMA_MCPB_CH1_REG_START - \
+	 BCHP_XPT_MEMDMA_MCPB_CH0_REG_START) * (channel))
+
+#define XPT_CHANNEL_A	0
+#define XPT_CHANNEL_B	1
+
+#define PID_CHANNEL_A	1022
+#define PID_CHANNEL_B	1023
+
+#define XPT_MAC_A	0
+#define XPT_MAC_B	1
+
+#define MAX_HASH_WAIT_US	(15 * 1000 * 1000) /* 15 seconds */
+
+static inline void xpt_set_power(int on)
+{
+#ifdef BCHP_XPT_PMU_FE_SP_PD_MEM_PWR_DN_CTRL
+	uint32_t val = on ? 0 : ~0;
+
+	/* Power on/off everything */
+	BDEV_WR(BCHP_XPT_PMU_FE_SP_PD_MEM_PWR_DN_CTRL, val);
+	BDEV_WR(BCHP_XPT_PMU_MCPB_SP_PD_MEM_PWR_DN_CTRL, val);
+	BDEV_WR(BCHP_XPT_PMU_MEMDMA_SP_PD_MEM_PWR_DN_CTRL, val);
+#endif
+}
+
+static void mcpb_run(int enable, int channel)
+{
+	BDEV_WR_RB(BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR,
+			(!!enable << 8) | channel);
+}
+
+static int mcpb_soft_init(void)
+{
+	int timeo = 1000 * 1000; /* 1 second timeout */
+
+	BDEV_WR(BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT,
+			1 << 1); /* MEMDMA */
+	BDEV_WR(BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET,
+			1 << 1); /* MEMDMA */
+
+	for (;;) {
+		if (!BDEV_RD_F(XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS,
+					MEMDMA_MCPB_SOFT_INIT_STATUS))
+			break;
+		if (timeo <= 0)
+			return -EIO;
+
+		timeo -= 10;
+		udelay(10);
+	}
+
+	BDEV_WR(BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR,
+			1 << 1); /* MEMDMA */
+	return 0;
+}
+
+static void memdma_init_mcpb_channel(int channel)
+{
+	unsigned long offs = MCPB_CHx_SPACING(channel);
+	unsigned long parser_ctrl = BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL + offs;
+	unsigned long packet_len = BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN + offs;
+	unsigned long dma_buf_ctrl = BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL + offs;
+	unsigned long dma_data_ctrl = BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL + offs;
+
+	mcpb_run(0, channel);
+
+	/* setup for block mode */
+	BDEV_WR(parser_ctrl,
+			(1 << 0) |		/* parser enable */
+			(6 << 1) |		/* block mode */
+			(channel << 6) |	/* band ID */
+			(1 << 14));		/* select playback parser */
+	BDEV_WR(packet_len, 208); /* packet length */
+	BDEV_WR(dma_buf_ctrl, 224); /* stream feed size */
+	BDEV_WR(dma_data_ctrl, (MEMDMA_DRAM_REQ_SIZE << 0) |
+			       (0 << 11));	/* disable run version match */
+}
+
+static void xpt_init_ctx(unsigned int channel, unsigned int pid_channel)
+{
+	/* configure PID channel */
+	BDEV_WR(BCHP_XPT_FE_PID_TABLE_i_ARRAY_BASE + 4 * pid_channel,
+			(1 << 14) |		/* enable PID channel */
+			(channel << 16) |	/* input parser band */
+			(1 << 23) |		/* playback parser */
+			(1 << 28));		/* direct to XPT security */
+
+	BDEV_WR(BCHP_XPT_FE_SPID_TABLE_i_ARRAY_BASE + 4 * pid_channel, 0);
+
+	BDEV_WR(BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_BASE +
+		     4 * pid_channel, 1); /* G pipe */
+}
+
+static void memdma_init_hw(int channel, int pid)
+{
+	memdma_init_mcpb_channel(channel);
+	xpt_init_ctx(channel, pid);
+}
+
+static int mcpb_init_desc(struct mcpb_dma_desc *desc, dma_addr_t next,
+		dma_addr_t buf, size_t len, int first, int last,
+		unsigned int pid_channel)
+{
+	memset(desc, 0, sizeof(*desc));
+
+	/* 5 LSBs must be 0; can only handle 32-bit addresses */
+	if (WARN_ON((next & 0x1f) || (upper_32_bits(next) != 0)))
+		return -EINVAL;
+
+	desc->buf_hi = upper_32_bits(buf);
+	desc->buf_lo = lower_32_bits(buf); /* BUFF_ST_RD_ADDR [31:0] */
+	desc->next_offs = lower_32_bits(next); /* NEXT_DESC_ADDR [31:5] */
+	desc->size = len; /* BUFF_SIZE [31:0] */
+	desc->opts2 = MCPB_DW5_PID_CHANNEL_VALID | MCPB_DW5_ENDIAN_STRAP_INV;
+	desc->pid_channel = pid_channel;
+
+	if (first)
+		desc->opts2 |= (MCPB_DW5_SCRAM_INIT | MCPB_DW5_SCRAM_START);
+
+	if (last) {
+		desc->next_offs = MCPB_DW2_LAST_DESC;
+		desc->opts1 |= MCPB_DW4_PUSH_PARTIAL_PKT;
+		desc->opts2 |= MCPB_DW5_SCRAM_END;
+	}
+
+	return 0;
+}
+
+/*
+ * memdma_prepare_descs - prepare a MEMDMA descriptor chain
+ *
+ * @descs: array of descriptors
+ * @descs_pa: physical address of @descs
+ * @regions: the address ranges to set up for MEMDMA
+ * @numregions: number of regions (in @descs and @regions)
+ * @channel_A: if true, use the first MAC channel (a.k.a. "channel A"); if
+ *     false, use the second MAC channel (a.k.a. "channel B")
+ */
+int memdma_prepare_descs(struct mcpb_dma_desc *descs, dma_addr_t descs_pa,
+		struct dma_region *regions, int numregions, bool channel_A)
+{
+	int i;
+	int pid = channel_A ? PID_CHANNEL_A : PID_CHANNEL_B;
+	dma_addr_t next_pa = descs_pa;
+	int ret;
+
+	for (i = 0; i < numregions; i++) {
+		int first = (i == 0);
+		int last = (i == (numregions - 1));
+
+		if (last)
+			next_pa = 0;
+		else
+			next_pa += sizeof(*descs);
+
+		ret = mcpb_init_desc(&descs[i], next_pa, regions[i].addr,
+				     regions[i].len, first, last, pid);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static bool hash_is_ready(int mac)
+{
+	if (mac)
+		return BDEV_RD_F(XPT_SECURITY_NS_INTR2_0_CPU_STATUS, MAC1_READY);
+	else
+		return BDEV_RD_F(XPT_SECURITY_NS_INTR2_0_CPU_STATUS, MAC0_READY);
+}
+
+static void clear_hash_interrupt(int mac)
+{
+	if (mac)
+		BDEV_WR_F(XPT_SECURITY_NS_INTR2_0_CPU_CLEAR, MAC1_READY, 1);
+	else
+		BDEV_WR_F(XPT_SECURITY_NS_INTR2_0_CPU_CLEAR, MAC0_READY, 1);
+}
+
+static int memdma_wait_for_hash(int mac)
+{
+	int timeo = MAX_HASH_WAIT_US;
+	for (;;) {
+		if (hash_is_ready(mac))
+			break;
+		if (timeo <= 0) {
+			pr_err("error: timeout waiting for MAC%d\n", mac);
+			return -EIO;
+		}
+
+		timeo -= 10;
+		udelay(10);
+	}
+
+	/* Clear status */
+	clear_hash_interrupt(mac);
+
+	return 0;
+}
+
+static void memdma_start(dma_addr_t desc, int channel)
+{
+	unsigned long reg = BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL +
+		MCPB_CHx_SPACING(channel);
+
+	BDEV_WR(reg, (uint32_t)desc);
+	mcpb_run(1, channel);
+}
+
+/*
+ * memdma_run - Run the MEMDMA MAC on up to 2 DMA descriptor chains
+ *
+ * @desc1: the physical address of the first descriptor chain
+ * @desc2: the physical address of the second descriptor chain (optional)
+ * @dual_channel: if true, then use desc2 with a second DMA channel; otherwise,
+ *     ignore desc2
+ */
+int memdma_run(dma_addr_t desc1, dma_addr_t desc2, bool dual_channel)
+{
+	int ret, ret2 = 0;
+
+	xpt_set_power(1);
+
+	ret = mcpb_soft_init();
+	if (ret)
+		goto out;
+
+	memdma_init_hw(0, PID_CHANNEL_A);
+	mb();
+	memdma_start(desc1, XPT_CHANNEL_A);
+
+	if (dual_channel) {
+		memdma_init_hw(1, PID_CHANNEL_B);
+		mb();
+		memdma_start(desc2, XPT_CHANNEL_B);
+	}
+
+	ret = memdma_wait_for_hash(XPT_MAC_A);
+	if (dual_channel)
+		ret2 = memdma_wait_for_hash(XPT_MAC_B);
+
+	/* Report the 1st non-zero return code */
+	if (!ret)
+		ret = ret2;
+
+out:
+	xpt_set_power(0);
+
+	return ret;
+}
+
+static uint32_t get_hash_idx(int mac_num, int word)
+{
+	int len = 128 / 32;
+	unsigned long reg_base;
+
+	if (word >= len)
+		return 0;
+
+	reg_base = BCHP_XPT_SECURITY_NS_MAC0_0 + mac_num * XPT_MAC_OFFSET;
+	return BDEV_RD(reg_base + word * 4);
+}
+
+void get_hash(uint32_t *hash, bool dual_channel)
+{
+	/* 128-bit AES CMAC hash */
+	int i, len = 128 / 8;
+
+	/* MAC0 */
+	for (i = 0; i < len / sizeof(*hash); i++)
+		hash[i] = get_hash_idx(0, i);
+
+	if (dual_channel)
+		/* MAC1 */
+		for (i = 0; i < len / sizeof(*hash); i++)
+			hash[i] ^= get_hash_idx(1, i);
+}
diff --git a/drivers/soc/brcmstb/pm/xpt_dma.h b/drivers/soc/brcmstb/pm/xpt_dma.h
new file mode 100644
index 000000000000..a7ee1efa6dd5
--- /dev/null
+++ b/drivers/soc/brcmstb/pm/xpt_dma.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __XPT_DMA_H__
+#define __XPT_DMA_H__
+
+#include <linux/types.h>
+
+struct dma_region {
+	dma_addr_t addr;
+	size_t len;
+};
+
+struct mcpb_dma_desc {
+	uint32_t buf_hi;
+	uint32_t buf_lo;
+	uint32_t next_offs; /* or 00001b for "last descriptor" */
+	uint32_t size;
+	uint32_t opts1;
+	uint32_t opts2;
+	uint32_t pid_channel;
+	uint32_t reserved;
+};
+
+#ifdef CONFIG_BRCMSTB_XPT_HASH
+int memdma_prepare_descs(struct mcpb_dma_desc *descs, dma_addr_t descs_pa,
+		struct dma_region *regions, int numregions, bool channel_A);
+
+int memdma_run(dma_addr_t desc1, dma_addr_t desc2, bool dual_channel);
+
+void get_hash(uint32_t *hash, bool dual_channel);
+#else
+static inline int memdma_prepare_descs(struct mcpb_dma_desc *descs,
+		dma_addr_t descs_pa, struct dma_region *regions,
+		int numregions, bool channel_A)
+{
+	return -ENOSYS;
+}
+
+static int memdma_run(dma_addr_t desc1, dma_addr_t desc2, bool dual_channel)
+{
+	return -ENOSYS;
+}
+
+static inline void get_hash(uint32_t *hash, bool dual_channel)
+{
+}
+#endif /* CONFIG_BRCMSTB_XPT_HASH */
+
+#endif /* __XPT_DMA_H__ */
diff --git a/drivers/soc/brcmstb/srpd.c b/drivers/soc/brcmstb/srpd.c
new file mode 100644
index 000000000000..50c50dbf7024
--- /dev/null
+++ b/drivers/soc/brcmstb/srpd.c
@@ -0,0 +1,169 @@
+/*
+ * DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
+ *
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/io.h>
+
+#define REG_SRPD_CONFIG			0x3c
+ #define INACT_COUNT_SHIFT		0
+ #define INACT_COUNT_MASK		0xffff
+ #define SRPD_EN_SHIFT			16
+ #define SRPD_EN_MASK			0x10000
+
+#define REG_POWER_DOWN_STATUS		0x44
+ #define SRPD_STATUS_SHIFT		1
+ #define SRPD_STATUS_MASK		0x2
+
+struct brcmstb_memc {
+	struct device *dev;
+	void __iomem *ddr_ctrl;
+	unsigned int timeout_cycles;
+	u32 frequency;
+};
+
+static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
+				    unsigned int cycles)
+{
+	void __iomem *cfg = memc->ddr_ctrl + REG_SRPD_CONFIG;
+	u32 val;
+
+	/* Max timeout supported in HW */
+	if (cycles > INACT_COUNT_MASK)
+		return -EINVAL;
+
+	memc->timeout_cycles = cycles;
+
+	val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK;
+	if (cycles)
+		val |= (1 << SRPD_EN_SHIFT);
+
+	__raw_writel(val, cfg);
+	(void)__raw_readl(cfg);
+
+	return 0;
+}
+
+static ssize_t show_attr_freq(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	struct brcmstb_memc *memc = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", memc->frequency);
+}
+
+static ssize_t show_attr_srpd(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	struct brcmstb_memc *memc = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", memc->timeout_cycles);
+}
+
+static ssize_t store_attr_srpd(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct brcmstb_memc *memc = dev_get_drvdata(dev);
+	unsigned int val;
+	int ret;
+
+	ret = kstrtouint(buf, 10, &val);
+	if (ret < 0)
+		return ret;
+
+	ret = brcmstb_memc_srpd_config(memc, val);
+	if (ret)
+		return ret;
+
+	return count;
+}
+
+static DEVICE_ATTR(frequency, S_IRUGO, show_attr_freq, NULL);
+static DEVICE_ATTR(srpd, S_IRUSR | S_IWUSR, show_attr_srpd, store_attr_srpd);
+
+static struct attribute *dev_attrs[] = {
+	&dev_attr_frequency.attr,
+	&dev_attr_srpd.attr,
+	NULL,
+};
+
+static struct attribute_group dev_attr_group = {
+	.attrs = dev_attrs,
+};
+
+static int brcmstb_memc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct brcmstb_memc *memc;
+	struct resource *res;
+	int ret;
+
+	memc = devm_kzalloc(dev, sizeof(*memc), GFP_KERNEL);
+	if (!memc)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, memc);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	memc->ddr_ctrl = devm_ioremap_resource(dev, res);
+	if (IS_ERR(memc->ddr_ctrl))
+		return PTR_ERR(memc->ddr_ctrl);
+
+	of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+			     &memc->frequency);
+
+	ret = sysfs_create_group(&dev->kobj, &dev_attr_group);
+	if (ret) {
+		dev_err(dev, "failed to create attribute group (%d)\n", ret);
+		return ret;
+	}
+
+	dev_info(dev, "registered\n");
+
+	return 0;
+}
+
+static int brcmstb_memc_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	sysfs_remove_group(&dev->kobj, &dev_attr_group);
+
+	return 0;
+}
+
+static const struct of_device_id brcmstb_memc_of_match[] = {
+	{ .compatible = "brcm,brcmstb-memc-ddr" },
+	{},
+};
+
+static struct platform_driver brcmstb_memc_driver = {
+	.probe = brcmstb_memc_probe,
+	.remove = brcmstb_memc_remove,
+	.driver = {
+		.name		= "brcmstb_memc",
+		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(brcmstb_memc_of_match),
+	},
+};
+module_platform_driver(brcmstb_memc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("DDR SRPD driver for Broadcom STB chips");
diff --git a/drivers/soc/brcmstb/wktmr.c b/drivers/soc/brcmstb/wktmr.c
new file mode 100644
index 000000000000..8c547461c227
--- /dev/null
+++ b/drivers/soc/brcmstb/wktmr.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright © 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/stat.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/suspend.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/pm_wakeup.h>
+#include <linux/reboot.h>
+#include <linux/rtc.h>
+
+#include <asm/mach/time.h>
+
+#define DRV_NAME	"brcm-waketimer"
+
+static struct brcmstb_waketmr {
+	struct rtc_device *rtc;
+	struct device *dev;
+	void __iomem *base;
+	unsigned int irq;
+	int wake_timeout;
+	struct notifier_block reboot_notifier;
+	bool alarm_is_active;
+	bool alarm_set_from_sysfs;
+} wktimer;
+
+/* No timeout */
+#define BRCMSTB_WKTMR_DEFAULT_TIMEOUT	(-1)
+
+#define BRCMSTB_WKTMR_EVENT		0x00
+#define BRCMSTB_WKTMR_COUNTER		0x04
+#define BRCMSTB_WKTMR_ALARM		0x08
+#define BRCMSTB_WKTMR_PRESCALER		0x0C
+#define BRCMSTB_WKTMR_PRESCALER_VAL	0x10
+
+static inline void brcmstb_waketmr_clear_alarm(struct brcmstb_waketmr *timer)
+{
+	writel_relaxed(1, timer->base + BRCMSTB_WKTMR_EVENT);
+	(void)readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT);
+	timer->alarm_is_active = false;
+}
+
+static void brcmstb_waketmr_set_alarm(struct brcmstb_waketmr *timer,
+		unsigned int secs)
+{
+	unsigned int t = 0;
+
+	brcmstb_waketmr_clear_alarm(timer);
+
+	if (timer->alarm_set_from_sysfs)
+		t = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER);
+	writel_relaxed(t + secs + 1, timer->base + BRCMSTB_WKTMR_ALARM);
+	timer->alarm_is_active = true;
+}
+
+static irqreturn_t brcmstb_waketmr_irq(int irq, void *data)
+{
+	struct brcmstb_waketmr *timer = data;
+	pm_wakeup_event(timer->dev, 0);
+	timer->alarm_is_active = false;
+	return IRQ_HANDLED;
+}
+
+/* Fixed 27Mhz frequency since WKTMR is in the UPG clock domain. This
+ * information should come from Device Tree eventually
+ */
+#define WKTMR_FREQ		27000000
+
+struct wktmr_time {
+	u32			sec;
+	u32			pre;
+};
+
+static void wktmr_read(struct wktmr_time *t)
+{
+	u32 tmp;
+
+	do {
+		t->sec = readl_relaxed(wktimer.base + BRCMSTB_WKTMR_COUNTER);
+		tmp = readl_relaxed(wktimer.base + BRCMSTB_WKTMR_PRESCALER_VAL);
+	} while (tmp >= WKTMR_FREQ);
+
+	t->pre = WKTMR_FREQ - tmp;
+}
+
+static void brcmstb_waketmr_read_persistent_clock(struct timespec *ts)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+
+	ts->tv_sec = now.sec;
+	ts->tv_nsec = now.pre * (1000000000 / WKTMR_FREQ);
+}
+
+static ssize_t brcmstb_waketmr_timeout_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", timer->wake_timeout);
+}
+
+static ssize_t brcmstb_waketmr_timeout_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+	int timeout;
+	int ret;
+
+#ifdef CONFIG_RTC_CLASS
+	dev_warn(dev, "Using sysfs attributes, consider using 'rtcwake'\n");
+#endif
+	ret = kstrtoint(buf, 0, &timeout);
+	if (ret < 0)
+		return ret;
+
+	/* Allow -1 as "no timeout" */
+	if (timeout < -1)
+		return -EINVAL;
+
+	timer->wake_timeout = timeout;
+	timer->alarm_set_from_sysfs = true;
+
+	return count;
+}
+
+static const DEVICE_ATTR(timeout, S_IRUGO | S_IWUSR,
+		brcmstb_waketmr_timeout_show,
+		brcmstb_waketmr_timeout_store);
+
+static int brcmstb_waketmr_prepare_suspend(struct brcmstb_waketmr *timer)
+{
+	struct device *dev = timer->dev;
+	int ret;
+
+	if (device_may_wakeup(dev) && timer->wake_timeout >= 0) {
+		dev_dbg(dev, "enable wake IRQ\n");
+		ret = enable_irq_wake(timer->irq);
+		if (ret) {
+			dev_err(dev, "failed to enable wake-up interrupt\n");
+			return ret;
+		}
+
+		/*
+		 * Using the ioctl() interface, the alarm timer will have
+		 * already been enabled in brcmstb_waketmr_setalarm().
+		 * However, using the sysfs interface, we have to enable it
+		 * here, because brcmstb_waketmr_setalarm() isn't called.
+		 */
+		if (!timer->alarm_is_active)
+			brcmstb_waketmr_set_alarm(timer, timer->wake_timeout);
+	} else {
+		dev_dbg(dev, "nothing to do: wake_timeout: %d\n",
+				timer->wake_timeout);
+	}
+	return 0;
+}
+
+/* If enabled as a wakeup-source, arm the timer when powering off */
+static int brcmstb_waketmr_reboot(struct notifier_block *nb,
+		unsigned long action, void *data)
+{
+	struct brcmstb_waketmr *timer;
+	timer = container_of(nb, struct brcmstb_waketmr, reboot_notifier);
+
+	/* Set timer for cold boot */
+	if (action == SYS_POWER_OFF)
+		brcmstb_waketmr_prepare_suspend(timer);
+
+	return NOTIFY_DONE;
+}
+
+#ifdef CONFIG_RTC_CLASS
+static int brcmstb_waketmr_gettime(struct device *dev,
+				   struct rtc_time *tm)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+
+	rtc_time_to_tm(now.sec, tm);
+
+	return 0;
+}
+
+static int brcmstb_waketmr_settime(struct device *dev,
+				   struct rtc_time *tm)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+	unsigned long sec;
+	int ret;
+
+	ret = rtc_valid_tm(tm);
+	if (ret)
+		return ret;
+
+	rtc_tm_to_time(tm, &sec);
+
+	dev_dbg(dev, "%s: sec=%ld\n", __FUNCTION__, sec);
+	writel_relaxed(sec, timer->base + BRCMSTB_WKTMR_COUNTER);
+
+	return 0;
+}
+
+static int brcmstb_waketmr_getalarm(struct device *dev,
+				    struct rtc_wkalrm *alarm)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+	unsigned long sec;
+	u32 reg;
+
+	sec = readl_relaxed(timer->base + BRCMSTB_WKTMR_ALARM);
+	if (sec == 0) {
+		/* Alarm is disabled */
+		alarm->enabled = 0;
+		alarm->time.tm_mon = -1;
+		alarm->time.tm_mday = -1;
+		alarm->time.tm_year = -1;
+		alarm->time.tm_hour = -1;
+		alarm->time.tm_min = -1;
+		alarm->time.tm_sec = -1;
+		dev_dbg(dev, "%s: alarm is disabled\n", __FUNCTION__);
+	} else {
+		/* Alarm is enabled */
+		alarm->enabled = 1;
+		rtc_time_to_tm(sec, &alarm->time);
+		dev_dbg(dev, "%s: alarm is enabled\n", __FUNCTION__);
+	}
+
+	reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT);
+	alarm->pending = !!(reg & 1);
+	dev_dbg(dev, "%s: alarm pending=%d\n", __FUNCTION__, alarm->pending);
+
+	return 0;
+}
+
+static int brcmstb_waketmr_setalarm(struct device *dev,
+				     struct rtc_wkalrm *alarm)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+	unsigned long sec;
+
+	if (alarm->enabled)
+		rtc_tm_to_time(&alarm->time, &sec);
+	else
+		sec = 0;
+
+	timer->wake_timeout = sec;
+	timer->alarm_set_from_sysfs = false;
+	dev_dbg(dev, "%s: timeout=%ld\n", __FUNCTION__, sec);
+	brcmstb_waketmr_set_alarm(timer, sec);
+
+	return 0;
+}
+
+/*
+ * Does not do much but keep the RTC class happy. We always support
+ * alarms.
+ */
+static int brcmstb_waketmr_alarm_enable(struct device *dev,
+					unsigned int enabled)
+{
+	dev_dbg(dev, "%s: enabled=%d\n", __FUNCTION__, enabled);
+	return 0;
+}
+
+static const struct rtc_class_ops brcmstb_waketmr_ops = {
+	.read_time	= brcmstb_waketmr_gettime,
+	.set_time	= brcmstb_waketmr_settime,
+	.read_alarm	= brcmstb_waketmr_getalarm,
+	.set_alarm	= brcmstb_waketmr_setalarm,
+	.alarm_irq_enable = brcmstb_waketmr_alarm_enable,
+};
+#endif /* CONFIG_RTC_CLASS */
+
+static int __init brcmstb_waketmr_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct brcmstb_waketmr *timer = &wktimer;
+	struct resource *res;
+	int ret;
+
+	platform_set_drvdata(pdev, timer);
+
+	if (timer->dev)
+		return -EBUSY;
+
+	timer->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	timer->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(timer->base))
+		return PTR_ERR(timer->base);
+
+	/*
+	 * Set wakeup capability before requesting wakeup interrupt, so we can
+	 * process boot-time "wakeups" (e.g., from S5 soft-off)
+	 */
+	device_set_wakeup_capable(dev, true);
+	device_wakeup_enable(dev);
+
+	timer->irq = platform_get_irq(pdev, 0);
+	if ((int)timer->irq < 0)
+		return -ENODEV;
+
+	ret = devm_request_irq(dev, timer->irq, brcmstb_waketmr_irq, 0,
+			                DRV_NAME, timer);
+	if (ret < 0)
+		return ret;
+
+	timer->reboot_notifier.notifier_call = brcmstb_waketmr_reboot;
+	register_reboot_notifier(&timer->reboot_notifier);
+
+	timer->wake_timeout = BRCMSTB_WKTMR_DEFAULT_TIMEOUT;
+#ifdef CONFIG_RTC_CLASS
+	timer->rtc = rtc_device_register("brcmstb-waketmr", dev,
+					 &brcmstb_waketmr_ops, THIS_MODULE);
+	if (IS_ERR(timer->rtc)) {
+		dev_err(dev, "unable to register device\n");
+		return PTR_ERR(timer->rtc);
+	}
+#endif
+
+	ret = device_create_file(dev, &dev_attr_timeout);
+	if (ret) {
+		unregister_reboot_notifier(&timer->reboot_notifier);
+		return ret;
+	}
+
+	register_persistent_clock(NULL, brcmstb_waketmr_read_persistent_clock);
+
+	dev_info(dev, "registered, with irq %d\n", timer->irq);
+	return ret;
+}
+
+static int brcmstb_waketmr_remove(struct platform_device *pdev)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(&pdev->dev);
+
+	device_remove_file(&pdev->dev, &dev_attr_timeout);
+	unregister_reboot_notifier(&timer->reboot_notifier);
+#ifdef CONFIG_RTC_CLASS
+	rtc_device_unregister(timer->rtc);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcmstb_waketmr_suspend(struct device *dev)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+
+	return brcmstb_waketmr_prepare_suspend(timer);
+}
+
+static int brcmstb_waketmr_resume(struct device *dev)
+{
+	struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
+	int ret;
+
+	if (!device_may_wakeup(dev) || timer->wake_timeout < 0)
+		return 0;
+
+	ret = disable_irq_wake(timer->irq);
+
+	brcmstb_waketmr_clear_alarm(timer);
+
+	return ret;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(brcmstb_waketmr_pm_ops, brcmstb_waketmr_suspend,
+		brcmstb_waketmr_resume);
+
+static const struct of_device_id brcmstb_waketmr_of_match[] = {
+	{ .compatible = "brcm,brcmstb-waketimer" },
+	{},
+};
+
+static struct platform_driver brcmstb_waketmr_driver = {
+	.remove			= brcmstb_waketmr_remove,
+	.driver = {
+		.name		= DRV_NAME,
+		.owner		= THIS_MODULE,
+		.pm		= &brcmstb_waketmr_pm_ops,
+		.of_match_table	= of_match_ptr(brcmstb_waketmr_of_match),
+	}
+};
+
+static int __init brcmstb_waketmr_init(void)
+{
+	return platform_driver_probe(&brcmstb_waketmr_driver,
+				     brcmstb_waketmr_probe);
+}
+
+static void __exit brcmstb_waketmr_exit(void)
+{
+	platform_driver_unregister(&brcmstb_waketmr_driver);
+}
+
+module_init(brcmstb_waketmr_init);
+module_exit(brcmstb_waketmr_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Wake-up timer driver for STB chips");
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 581ee2a8856b..90d59f93ba47 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -138,6 +138,13 @@ config SPI_BITBANG
 	  need it.  You only need to select this explicitly to support driver
 	  modules that aren't part of this kernel tree.
 
+config SPI_BRCMSTB_MSPI
+	tristate "Broadcom MSPI master support for STB chips"
+	depends on (ARCH_BRCMSTB && BCM7120_L2_IRQ) || COMPILE_TEST
+	help
+	  Enables support for the Broadcom MSPI controller.  Currently only
+	  supports BRCMSTB, but that should change soon.
+
 config SPI_BUTTERFLY
 	tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)"
 	depends on PARPORT
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95af48d2d360..1b2a6451a7f7 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_SPI_BFIN5XX)		+= spi-bfin5xx.o
 obj-$(CONFIG_SPI_BFIN_V3)               += spi-bfin-v3.o
 obj-$(CONFIG_SPI_BFIN_SPORT)		+= spi-bfin-sport.o
 obj-$(CONFIG_SPI_BITBANG)		+= spi-bitbang.o
+obj-$(CONFIG_SPI_BRCMSTB)		+= spi-brcmstb.o
+obj-$(CONFIG_SPI_BRCMSTB_MSPI)		+= spi-brcmstb-mspi.o
 obj-$(CONFIG_SPI_BUTTERFLY)		+= spi-butterfly.o
 obj-$(CONFIG_SPI_CLPS711X)		+= spi-clps711x.o
 obj-$(CONFIG_SPI_COLDFIRE_QSPI)		+= spi-coldfire-qspi.o
diff --git a/drivers/spi/spi-brcmstb-mspi.c b/drivers/spi/spi-brcmstb-mspi.c
new file mode 100644
index 000000000000..b21203d80bca
--- /dev/null
+++ b/drivers/spi/spi-brcmstb-mspi.c
@@ -0,0 +1,806 @@
+/*
+ * Copyright (C) 2009-2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+#define DBG(...)			pr_debug(__VA_ARGS__)
+
+/* These defaults are used if not provided in device tree or board file */
+#define NUM_CHIPSELECT		4
+#define MSPI_BASE_FREQ		27000000UL
+
+#define SPBR_MIN		8U
+#define SPBR_MAX		255U
+
+/*
+ * The registers controlling these parameters are shared across all chip
+ * selects and so must be updated when they differ across CS, not just when
+ * a change is requested.
+ */
+struct bcmspi_parms {
+	u32			speed_hz;
+	u8			mode;
+	u8			bits_per_word;
+};
+
+static struct bcmspi_parms bcmspi_default_parms_cs0 = {
+	.mode			= SPI_MODE_3,
+	.bits_per_word		= 8,
+};
+
+struct position {
+	struct spi_transfer	*trans;
+	int			byte;
+};
+
+#define NUM_TXRAM		32
+#define NUM_RXRAM		32
+#define NUM_CDRAM		16
+
+#define CDRAM_OUTP	(1 << 8)   /* data direction for half-duplex */
+#define CDRAM_CONT	(1 << 7)   /* continue driving SSb after transfer */
+#define CDRAM_BITSE	(1 << 6)   /* bits per transfer (0 = 8 bits,
+			              1 = use SPCR0_MSB) */
+#define CDRAM_DT	(1 << 5)   /* Delay after transfer (0 = 32 clks,
+			              1 = use SPCR1_LSB */
+#define CDRAM_DSCK	(1 << 4)   /* PCS to SCK delay (0 = 1/2 SCK, 1 =
+				    SPCR1_MSB determines */
+#define CDRAM_PCS	0xf      /* Peripheral chip selects, active low */
+
+#define BRCM_MSPI_REG_NONE  U16_MAX
+
+enum brcm_mspi_reg {
+	BRCM_MSPI_SPCR0_LSB = 0,
+	BRCM_MSPI_SPCR0_MSB,
+	BRCM_MSPI_SPCR1_LSB,
+	BRCM_MSPI_SPCR1_MSB,
+	BRCM_MSPI_NEWQP,
+	BRCM_MSPI_ENDQP,
+	BRCM_MSPI_SPCR2,
+	BRCM_MSPI_MSPI_STATUS,
+	BRCM_MSPI_CPTQP,
+	BRCM_MSPI_TXRAM,
+	BRCM_MSPI_RXRAM,
+	BRCM_MSPI_CDRAM,
+	BRCM_MSPI_WRITE_LOCK,  /* only when paired with BSPI */
+	/* below added in MSPI v1.5 */
+	BRCM_MSPI_SPCR3,
+	BRCM_MSPI_REVISION,
+};
+
+/* Older MSPI versions that don't have a revision reg */
+static const u16 brcm_mspi_regs_legacy[] = {
+	[BRCM_MSPI_SPCR0_LSB]		= 0x000,
+	[BRCM_MSPI_SPCR0_MSB]		= 0x004,
+	[BRCM_MSPI_SPCR1_LSB]		= 0x008,
+	[BRCM_MSPI_SPCR1_MSB]		= 0x00c,
+	[BRCM_MSPI_NEWQP]		= 0x010,
+	[BRCM_MSPI_ENDQP]		= 0x014,
+	[BRCM_MSPI_SPCR2]		= 0x018,
+	[BRCM_MSPI_MSPI_STATUS]		= 0x020,
+	[BRCM_MSPI_CPTQP]		= 0x024,
+	[BRCM_MSPI_SPCR3]		= BRCM_MSPI_REG_NONE,
+	[BRCM_MSPI_REVISION]		= BRCM_MSPI_REG_NONE,
+	[BRCM_MSPI_TXRAM]		= 0x040,
+	[BRCM_MSPI_RXRAM]		= 0x0c0,
+	[BRCM_MSPI_CDRAM]		= 0x140,
+	[BRCM_MSPI_WRITE_LOCK]		= 0x180,
+};
+
+/* MSPI v1.5 */
+static const u16 brcm_mspi_regs_v1_5[] = {
+	[BRCM_MSPI_SPCR0_LSB]		= 0x000,
+	[BRCM_MSPI_SPCR0_MSB]		= 0x004,
+	[BRCM_MSPI_SPCR1_LSB]		= 0x008,
+	[BRCM_MSPI_SPCR1_MSB]		= 0x00c,
+	[BRCM_MSPI_NEWQP]		= 0x010,
+	[BRCM_MSPI_ENDQP]		= 0x014,
+	[BRCM_MSPI_SPCR2]		= 0x018,
+	[BRCM_MSPI_MSPI_STATUS]		= 0x020,
+	[BRCM_MSPI_CPTQP]		= 0x024,
+	[BRCM_MSPI_SPCR3]		= 0x028,
+	[BRCM_MSPI_REVISION]		= 0x02c,
+	[BRCM_MSPI_TXRAM]		= 0x040,
+	[BRCM_MSPI_RXRAM]		= 0x0c0,
+	[BRCM_MSPI_CDRAM]		= 0x140,
+	[BRCM_MSPI_WRITE_LOCK]		= 0x180,
+};
+
+/* BSPI registers */
+#define BSPI_MAST_N_BOOT_CTRL			0x08
+
+#define STATE_IDLE		0
+#define STATE_RUNNING		1
+#define STATE_SHUTDOWN		2
+
+struct bcmspi_priv {
+	struct platform_device	*pdev;
+	struct spi_master	*master;
+	struct clk		*clk;
+	u8			revision;
+	const u16		*reg_offsets;
+	unsigned long		base_freq;
+	struct bcmspi_parms	last_parms;
+	struct position		pos;
+	int			next_udelay;
+	int			cs_change;
+	unsigned long		max_speed_hz;
+	void __iomem		*mspi_base;
+	void __iomem		*bspi;
+
+	struct completion	done;
+};
+
+static inline bool has_bspi(struct bcmspi_priv *priv)
+{
+	return priv->bspi;
+}
+
+static inline u32 brcm_mspi_readl(void __iomem *addr)
+{
+	/*
+	 * MIPS endianness is configured by boot strap, which also reverses all
+	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
+	 * endian I/O).
+	 *
+	 * Other architectures (e.g., ARM) either do not support big endian, or
+	 * else leave I/O in little endian mode.
+	 */
+	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		return __raw_readl(addr);
+	else
+		return readl_relaxed(addr);
+}
+
+static inline void brcm_mspi_writel(u32 val, void __iomem *addr)
+{
+	/* See brcm_mspi_readl() comments */
+	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		__raw_writel(val, addr);
+	else
+		writel_relaxed(val, addr);
+}
+
+static inline u32 brcm_mspi_readl_offset(struct bcmspi_priv *priv, u32 offset)
+{
+	return brcm_mspi_readl(priv->mspi_base + offset);
+}
+
+static inline void brcm_mspi_writel_offset(struct bcmspi_priv *priv, u32 offset,
+				u32 val)
+{
+	return brcm_mspi_writel(val, priv->mspi_base + offset);
+}
+
+static inline u32 brcm_mspi_readreg(struct bcmspi_priv *priv,
+		enum brcm_mspi_reg reg)
+{
+	u16 offset = priv->reg_offsets[reg];
+
+	if (offset == BRCM_MSPI_REG_NONE)
+		return 0;
+	else
+		return brcm_mspi_readl_offset(priv, offset);
+}
+
+static inline void brcm_mspi_writereg(struct bcmspi_priv *priv,
+		enum brcm_mspi_reg reg, u32 val)
+{
+	u16 offset = priv->reg_offsets[reg];
+
+	if (offset != BRCM_MSPI_REG_NONE)
+		brcm_mspi_writel_offset(priv, offset, val);
+}
+
+/* True if parms changed, false if not */
+static bool bcmspi_parms_did_change(const struct bcmspi_parms * const cur,
+		const struct bcmspi_parms * const prev)
+{
+	return (cur->speed_hz != prev->speed_hz) ||
+		(cur->mode != prev->mode) ||
+		(cur->bits_per_word != prev->bits_per_word);
+}
+
+static void bcmspi_hw_set_parms(struct bcmspi_priv *priv,
+	const struct bcmspi_parms *xp)
+{
+	u32 val;
+
+	if (!bcmspi_parms_did_change(xp, &priv->last_parms))
+		return;
+
+	if (xp->speed_hz) {
+		unsigned int spbr = priv->base_freq / (2 * xp->speed_hz);
+
+		val = max(min(spbr, SPBR_MAX), SPBR_MIN);
+	} else {
+		/* go as fast as possible */
+		val = SPBR_MIN;
+	}
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR0_LSB, val);
+
+	val =
+#ifdef CONFIG_BRCM_MSPI_LEGACY
+		0x80 |	/* MSTR bit */
+#endif
+		((xp->bits_per_word ? xp->bits_per_word : 8) << 2) |
+		(xp->mode & 3);
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR0_MSB, val);
+	priv->last_parms = *xp;
+}
+
+static void bcmspi_update_parms(struct bcmspi_priv *priv,
+	struct spi_device *spidev, struct spi_transfer *trans)
+{
+	struct bcmspi_parms xp;
+
+	/* transfer can override spidev-level speed */
+	xp.speed_hz = min(trans->speed_hz ? trans->speed_hz :
+		(spidev->max_speed_hz ? spidev->max_speed_hz :
+		 priv->max_speed_hz),
+		priv->max_speed_hz);
+	xp.mode = spidev->mode;
+	xp.bits_per_word = trans->bits_per_word ? trans->bits_per_word :
+		(spidev->bits_per_word ? spidev->bits_per_word : 8);
+
+	bcmspi_hw_set_parms(priv, &xp);
+}
+
+
+static int bcmspi_setup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp;
+	struct bcmspi_priv *priv = spi_master_get_devdata(spi->master);
+
+	if (spi->bits_per_word > 16)
+		return -EINVAL;
+
+	xp = spi_get_ctldata(spi);
+	if (!xp) {
+		xp = kzalloc(sizeof(*xp), GFP_KERNEL);
+		if (!xp)
+			return -ENOMEM;
+		spi_set_ctldata(spi, xp);
+	}
+	if (spi->max_speed_hz < priv->max_speed_hz)
+		xp->speed_hz = spi->max_speed_hz;
+	else
+		xp->speed_hz = 0;
+
+	xp->mode = spi->mode;
+	xp->bits_per_word = spi->bits_per_word ? spi->bits_per_word : 8;
+
+	return 0;
+}
+
+/* stop at end of transfer, no other reason */
+#define FNB_BREAK_NONE			0
+/* stop at end of spi_message */
+#define FNB_BREAK_EOM			1
+/* stop at end of spi_transfer if delay */
+#define FNB_BREAK_DELAY			2
+/* stop at end of spi_transfer if cs_change */
+#define FNB_BREAK_CS_CHANGE		4
+/* stop if we run out of bytes */
+#define FNB_BREAK_NO_BYTES		8
+
+/* events that make us stop filling TX slots */
+#define FNB_BREAK_TX			(FNB_BREAK_EOM | FNB_BREAK_DELAY | \
+					 FNB_BREAK_CS_CHANGE)
+
+/* events that make us deassert CS */
+#define FNB_BREAK_DESELECT		(FNB_BREAK_EOM | FNB_BREAK_CS_CHANGE)
+
+
+/**
+ * find_next_byte() - advance byte and check what flags should be set
+ * @priv: pointer to bcmspi private struct
+ * @p: pointer to current position pointer
+ * @flags: flags to take into account at the end of a spi_transfer
+ *
+ * Advances to the next byte, incrementing the byte in the position pointer p.
+ * If any flags are passed in and we're at the end of a transfer, those are
+ * applied to the return value if applicable to the spi_transfer.
+ *
+ * Return: flags describing the break condition or FNB_BREAK_NONE.
+ */
+static int find_next_byte(struct bcmspi_priv *priv, struct position *p,
+			  int flags)
+{
+	int ret = FNB_BREAK_NONE;
+
+	if (p->trans->bits_per_word <= 8)
+		p->byte++;
+	else
+		p->byte += 2;
+
+	if (p->byte >= p->trans->len) {
+		/* we're at the end of the spi_transfer */
+
+		/* in TX mode, need to pause for a delay or CS change */
+		if (p->trans->delay_usecs && (flags & FNB_BREAK_DELAY))
+			ret |= FNB_BREAK_DELAY;
+		if (p->trans->cs_change && (flags & FNB_BREAK_CS_CHANGE))
+			ret |= FNB_BREAK_CS_CHANGE;
+		if (ret)
+			goto done;
+
+		DBG("find_next_byte: advance msg exit\n");
+		if (spi_transfer_is_last(priv->master, p->trans))
+			ret = FNB_BREAK_EOM;
+		else
+			ret = FNB_BREAK_NO_BYTES;
+		/* FIXME: we probably need to check for NULL values in other
+		 * parts of the code */
+		p->trans = NULL;
+	}
+
+done:
+	DBG("find_next_byte: trans %p len %d byte %d ret %x\n",
+		p->trans, p->trans ? p->trans->len : 0, p->byte, ret);
+	return ret;
+}
+
+static inline u8 read_rxram_slot_u8(struct bcmspi_priv *priv, int slot)
+{
+	u16 slot_offset = priv->reg_offsets[BRCM_MSPI_RXRAM] +
+			 (slot << 3) + 0x4;
+
+	/* mask out reserved bits */
+	return brcm_mspi_readl_offset(priv, slot_offset) & 0xff;
+}
+
+static inline u16 read_rxram_slot_u16(struct bcmspi_priv *priv, int slot)
+{
+	u16 reg_offset = priv->reg_offsets[BRCM_MSPI_RXRAM];
+	u16 lsb_offset = reg_offset + (slot << 3) + 0x4;
+	u16 msb_offset = reg_offset + (slot << 3);
+
+	return (brcm_mspi_readl_offset(priv, lsb_offset) & 0xff) |
+		((brcm_mspi_readl_offset(priv, msb_offset) & 0xff) << 8);
+}
+
+static void read_from_hw(struct bcmspi_priv *priv, int slots)
+{
+	struct position p;
+	int slot;
+
+	if (slots > NUM_CDRAM) {
+		/* should never happen */
+		dev_err(&priv->pdev->dev, "%s: too many slots!\n", __func__);
+		return;
+	}
+
+	p = priv->pos;
+
+	for (slot = 0; slot < slots; slot++) {
+		if (p.trans->bits_per_word <= 8) {
+			u8 *buf = p.trans->rx_buf;
+
+			if (buf)
+				buf[p.byte] = read_rxram_slot_u8(priv, slot);
+			DBG("RD %02x\n", buf ? buf[p.byte] : 0xff);
+		} else {
+			u16 *buf = p.trans->rx_buf;
+
+			if (buf)
+				buf[p.byte / 2] = read_rxram_slot_u16(priv, slot);
+			DBG("RD %04x\n", buf ? buf[p.byte] : 0xffff);
+		}
+
+		find_next_byte(priv, &p, FNB_BREAK_NONE);
+	}
+
+	priv->pos = p;
+}
+
+static inline void write_txram_slot_u8(struct bcmspi_priv *priv, int slot,
+		u8 val)
+{
+	u16 reg_offset = priv->reg_offsets[BRCM_MSPI_TXRAM] +
+			 (slot << 3);
+
+	/* mask out reserved bits */
+	brcm_mspi_writel_offset(priv, reg_offset, val);
+}
+
+static inline void write_txram_slot_u16(struct bcmspi_priv *priv, int slot,
+		u16 val)
+{
+	u16 reg_offset = priv->reg_offsets[BRCM_MSPI_TXRAM];
+	u16 msb_offset = reg_offset + (slot << 3);
+	u16 lsb_offset = reg_offset + (slot << 3) + 0x4;
+
+	brcm_mspi_writel_offset(priv, msb_offset, (val >> 8));
+	brcm_mspi_writel_offset(priv, lsb_offset, val & 0xff);
+}
+
+static inline u32 read_cdram_slot(struct bcmspi_priv *priv, int slot)
+{
+	return brcm_mspi_readl_offset(priv,
+			priv->reg_offsets[BRCM_MSPI_CDRAM] + (slot << 2));
+}
+
+static inline void write_cdram_slot(struct bcmspi_priv *priv, int slot, u32 val)
+{
+	u16 reg_offset = priv->reg_offsets[BRCM_MSPI_CDRAM] + (slot << 2);
+
+	brcm_mspi_writel_offset(priv, reg_offset, val);
+}
+
+/* Return number of slots written */
+static int write_to_hw(struct bcmspi_priv *priv, struct spi_device *spidev)
+{
+	struct position p;
+	int slot = 0, fnb = 0;
+
+	p = priv->pos;
+
+	bcmspi_update_parms(priv, spidev, p.trans);
+
+	/*
+	 * TODO: would be nice to have some sanity checking for testing only
+	 * _just_ in case some parameters change out from under us
+	 */
+
+	/* Run until end of transfer or reached the max data */
+	while (!fnb && slot < NUM_CDRAM) {
+		if (p.trans->bits_per_word <= 8) {
+			const u8 *buf = p.trans->tx_buf;
+			u8 val = buf ? buf[p.byte] : 0xff;
+
+			write_txram_slot_u8(priv, slot, val);
+			DBG("WR %02x\n", val);
+		} else {
+			const u16 *buf = p.trans->tx_buf;
+			u16 val = buf ? buf[p.byte / 2] : 0xffff;
+
+			write_txram_slot_u16(priv, slot, val);
+			DBG("WR %04x\n", val);
+		}
+		write_cdram_slot(priv, slot,
+			(CDRAM_CONT |
+			 (~(1 << spidev->chip_select) & CDRAM_PCS)) |
+			((p.trans->bits_per_word <= 8) ? 0 : CDRAM_BITSE));
+
+		/* NOTE: This can update p.trans */
+		fnb = find_next_byte(priv, &p, FNB_BREAK_TX);
+		slot++;
+	}
+	if (!slot) {
+		dev_err(&priv->pdev->dev, "%s: no data to send?", __func__);
+		goto done;
+	}
+
+	/* in TX mode, need to pause for a delay or CS change */
+	if (fnb & FNB_BREAK_CS_CHANGE)
+		priv->cs_change = 1;
+	if (fnb & FNB_BREAK_DELAY)
+		priv->next_udelay = p.trans->delay_usecs;
+
+	DBG("submitting %d slots\n", slot);
+	brcm_mspi_writereg(priv, BRCM_MSPI_NEWQP, 0);
+	brcm_mspi_writereg(priv, BRCM_MSPI_ENDQP, slot - 1);
+
+	/* deassert CS on the final byte */
+	if (fnb & FNB_BREAK_DESELECT)
+		write_cdram_slot(priv, slot - 1,
+				read_cdram_slot(priv, slot - 1) & ~CDRAM_CONT);
+
+	if (has_bspi(priv))
+		brcm_mspi_writereg(priv, BRCM_MSPI_WRITE_LOCK, 1);
+
+	/* Must flush previous writes before starting MSPI operation */
+	mb();
+	/* Set cont | spe | spifie */
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR2, 0xe0);
+
+done:
+	return slot;
+}
+
+static void hw_stop(struct bcmspi_priv *priv)
+{
+	if (has_bspi(priv))
+		brcm_mspi_writereg(priv, BRCM_MSPI_WRITE_LOCK, 0);
+}
+
+static int bcmspi_transfer_one(struct spi_master *master,
+		struct spi_device *spidev, struct spi_transfer *trans)
+{
+	struct bcmspi_priv *priv = spi_master_get_devdata(master);
+	int slots;
+
+	priv->pos.trans = trans;
+	priv->pos.byte = 0;
+
+	while (priv->pos.byte < trans->len) {
+		reinit_completion(&priv->done);
+
+		slots = write_to_hw(priv, spidev);
+
+		if (!wait_for_completion_timeout(&priv->done, HZ)) {
+			dev_err(&priv->pdev->dev, "timeout waiting for MSPI\n");
+			return -EIO;
+		}
+
+		if (priv->next_udelay) {
+			udelay(priv->next_udelay);
+			priv->next_udelay = 0;
+		}
+
+		read_from_hw(priv, slots);
+		if (priv->cs_change) {
+			udelay(10);
+			priv->cs_change = 0;
+		}
+	}
+
+	if (spi_transfer_is_last(master, trans))
+		hw_stop(priv);
+
+	/* 0 indicates transfer complete */
+	return 0;
+}
+
+static void bcmspi_cleanup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp = spi_get_ctldata(spi);
+
+	kfree(xp);
+}
+
+static irqreturn_t bcmspi_interrupt(int irq, void *dev_id)
+{
+	struct bcmspi_priv *priv = dev_id;
+	u32 status = brcm_mspi_readreg(priv, BRCM_MSPI_MSPI_STATUS);
+
+	if (status & 1) {
+		/* clear interrupt */
+		brcm_mspi_writereg(priv, BRCM_MSPI_MSPI_STATUS, status & ~1);
+		complete(&priv->done);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+/* requires priv->max_speed_hz to be initialized */
+static void bcmspi_hw_init(struct bcmspi_priv *priv)
+{
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR1_LSB, 0);
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR1_MSB, 0);
+	brcm_mspi_writereg(priv, BRCM_MSPI_NEWQP, 0);
+	brcm_mspi_writereg(priv, BRCM_MSPI_ENDQP, 0);
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR2, 0x20);  /* spifie */
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR3, 0);
+
+	bcmspi_default_parms_cs0.speed_hz = priv->max_speed_hz;
+	bcmspi_hw_set_parms(priv, &bcmspi_default_parms_cs0);
+}
+
+static void bcmspi_hw_uninit(struct bcmspi_priv *priv)
+{
+	/* disable irq and enable bits */
+	brcm_mspi_writereg(priv, BRCM_MSPI_SPCR2, 0);
+}
+
+static int bcmspi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct bcmspi_priv *priv;
+	struct spi_master *master;
+	struct resource *res;
+	int ret;
+	u32 temp;
+	int irq;
+
+	if (!dev->of_node)
+		return -ENODEV;
+
+	master = spi_alloc_master(dev, sizeof(struct bcmspi_priv));
+	if (!master) {
+		dev_err(&pdev->dev, "error allocating spi_master\n");
+		return -ENOMEM;
+	}
+
+	priv = spi_master_get_devdata(master);
+
+	priv->pdev = pdev;
+	priv->master = master;
+
+	master->bus_num = pdev->id;
+	if (!of_property_read_u32(dev->of_node, "num-cs", &temp)) {
+		master->num_chipselect = temp;
+	} else {
+		/* Not provided by device-tree; use default */
+		master->num_chipselect = NUM_CHIPSELECT;
+	}
+	master->mode_bits = SPI_MODE_3;
+
+	master->setup = bcmspi_setup;
+	master->transfer_one = bcmspi_transfer_one;
+	master->cleanup = bcmspi_cleanup;
+	master->dev.of_node = dev->of_node;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "can't get resource 0\n");
+		ret = -EIO;
+		goto err2;
+	}
+	/* MSPI register range */
+	priv->mspi_base = devm_ioremap(&pdev->dev, res->start,
+			res->end - res->start);
+	if (!priv->mspi_base) {
+		dev_err(&pdev->dev, "can't ioremap\n");
+		ret = -EIO;
+		goto err2;
+	}
+
+	/* Optional: BSPI */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
+	if (res) {
+		priv->bspi = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(priv->bspi)) {
+			ret = PTR_ERR(priv->bspi);
+			goto err2;
+		}
+		dev_info(&pdev->dev, "has BSPI\n");
+	}
+
+	/* Start in MSPI mode */
+	if (has_bspi(priv))
+		__raw_writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL);
+
+	/* IRQ */
+	irq = platform_get_irq_byname(pdev, "mspi_done");
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no mspi_done IRQ defined\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	ret = devm_request_irq(&pdev->dev, irq, bcmspi_interrupt, 0,
+			"spi_brcmstb", priv);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "unable to allocate IRQ\n");
+		goto err2;
+	}
+
+	/* Clock */
+	priv->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_warn(&pdev->dev, "unable to get clock\n");
+		/* Ignore, if we don't have any clocks to get */
+		priv->clk = NULL;
+		priv->base_freq = MSPI_BASE_FREQ;
+	} else {
+		ret = clk_prepare_enable(priv->clk);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to prepare clock\n");
+			goto err2;
+		}
+		priv->base_freq = clk_get_rate(priv->clk);
+	}
+	priv->max_speed_hz = priv->base_freq / (SPBR_MIN * 2);
+
+#ifdef CONFIG_BRCM_MSPI_LEGACY
+	/*
+	 * Legacy MSPI does not have a revision register, so we need this
+	 * ifdef---there's no way to tell what version you have at runtime.
+	 */
+	priv->reg_offsets = brcm_mspi_regs_legacy;
+	priv->revision = 0;
+#else
+	/* Ideally we should read the revision first and determine what
+	 * registers are present, but right now at least there's only one
+	 * supported revision */
+	priv->reg_offsets = brcm_mspi_regs_v1_5;
+	priv->revision = brcm_mspi_readreg(priv, BRCM_MSPI_REVISION);
+#endif
+
+	bcmspi_hw_init(priv);
+	init_completion(&priv->done);
+	platform_set_drvdata(pdev, priv);
+
+	ret = devm_spi_register_master(&pdev->dev, master);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "can't register master\n");
+		goto err1;
+	}
+
+	return 0;
+
+err1:
+	bcmspi_hw_uninit(priv);
+	clk_disable_unprepare(priv->clk);
+err2:
+	spi_master_put(master);
+	return ret;
+}
+
+static int bcmspi_remove(struct platform_device *pdev)
+{
+	struct bcmspi_priv *priv = platform_get_drvdata(pdev);
+
+	bcmspi_hw_uninit(priv);
+	clk_disable_unprepare(priv->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int bcmspi_suspend(struct device *dev)
+{
+	struct bcmspi_priv *priv = dev_get_drvdata(dev);
+
+	clk_disable(priv->clk);
+	return 0;
+};
+
+static int bcmspi_resume(struct device *dev)
+{
+	struct bcmspi_priv *priv = dev_get_drvdata(dev);
+
+	bcmspi_hw_init(priv);
+
+	return clk_enable(priv->clk);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(bcmspi_pm_ops, bcmspi_suspend, bcmspi_resume);
+
+static const struct of_device_id spi_brcmstb_of_match[] = {
+#ifndef CONFIG_SPI_BRCMSTB
+	/*
+	 * With this ifdef, this driver (which does not support BSPI) will not
+	 * be used for MSPI+BSPI configurations unless the driver that supports
+	 * both is disabled.
+	 */
+	{ .compatible = "brcm,spi-brcmstb" },
+#endif
+	{ .compatible = "brcm,spi-brcmstb-mspi" },
+	{},
+};
+
+static struct platform_driver spi_brcmstb_driver = {
+	.driver = {
+		.name = "spi-brcmstb-mspi",
+		.bus = &platform_bus_type,
+		.pm		= &bcmspi_pm_ops,
+		.of_match_table = spi_brcmstb_of_match,
+	},
+	.probe = bcmspi_probe,
+	.remove = bcmspi_remove,
+};
+
+module_platform_driver(spi_brcmstb_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom MSPI SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-brcmstb.c b/drivers/spi/spi-brcmstb.c
new file mode 100644
index 000000000000..7bb4c2c099a5
--- /dev/null
+++ b/drivers/spi/spi-brcmstb.c
@@ -0,0 +1,1700 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+#define DBG pr_debug
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+#define BSPI_HAS_4BYTE_ADDRESS
+#define BSPI_HAS_FLEX_MODE
+#endif
+
+#define BSPI_LR_TIMEOUT			(1000)
+
+#define BSPI_LR_INTERRUPTS_DATA \
+	(BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK)
+
+#define BSPI_LR_INTERRUPTS_ERROR \
+	(BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK	| \
+	 BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK)
+
+#define BSPI_LR_INTERRUPTS_ALL \
+	(BSPI_LR_INTERRUPTS_ERROR | \
+	 BSPI_LR_INTERRUPTS_DATA)
+
+#define NUM_CHIPSELECT		4
+#define MSPI_BASE_FREQ		27000000UL
+#define SPBR_MIN		8U
+#define SPBR_MAX		255U
+#define MAX_SPEED_HZ		(MSPI_BASE_FREQ / (SPBR_MIN * 2))
+#define BSPI_BASE_ADDR		KSEG1ADDR(0x1f000000)
+
+#define OPCODE_RDID		0x9f
+#define OPCODE_WREN		0x06
+#define OPCODE_WRR		0x01
+#define OPCODE_RCR		0x35
+#define OPCODE_READ		0x03
+#define OPCODE_RDSR		0x05
+#define OPCODE_WRSR		0x01
+#define OPCODE_FAST_READ	0x0B
+#define OPCODE_DOR		0x3B
+#define OPCODE_QOR		0x6B
+#define OPCODE_FAST_READ_4B	0x0C
+#define OPCODE_DOR_4B		0x3C
+#define OPCODE_QOR_4B		0x6C
+
+#define OPCODE_DIOR		0xBB
+#define OPCODE_QIOR		0xEB
+#define OPCODE_DIOR_4B		0xBC
+#define OPCODE_QIOR_4B		0xEC
+
+#define OPCODE_PP		0x02
+#define OPCODE_PP_4B		0x12
+#define OPCODE_EN4B		0xB7
+#define OPCODE_EX4B		0xE9
+#define OPCODE_BRWR		0x17
+
+#define	BSPI_WIDTH_1BIT		1
+#define BSPI_WIDTH_2BIT		2
+#define BSPI_WIDTH_4BIT		4
+
+#define	BSPI_ADDRLEN_3BYTES	3
+#define	BSPI_ADDRLEN_4BYTES	4
+#define BSPI_BR_EXTADD		BIT(7)
+#define BSPI_FLASH_TYPE_SPANSION	0
+#define BSPI_FLASH_TYPE_MACRONIX	1
+#define BSPI_FLASH_TYPE_NUMONYX		2
+#define BSPI_FLASH_TYPE_SST		3
+#define BSPI_FLASH_TYPE_UNKNOWN		-1
+
+static int nobspi;
+module_param(nobspi, int, 0444);
+
+static int bspi_width  = BSPI_WIDTH_1BIT;
+module_param(bspi_width, int, 0444);
+
+static int bspi_addrlen  = BSPI_ADDRLEN_3BYTES;
+module_param(bspi_addrlen, int, 0444);
+
+static int bspi_hp;
+module_param(bspi_hp, int, 0444);
+
+static int bspi_flash = BSPI_FLASH_TYPE_UNKNOWN;
+module_param(bspi_flash, int, 0444);
+
+struct bcmspi_parms {
+	u32			speed_hz;
+	u8			chip_select;
+	u8			mode;
+	u8			bits_per_word;
+};
+
+static const struct bcmspi_parms bcmspi_default_parms_cs0 = {
+	.speed_hz		= MAX_SPEED_HZ,
+	.chip_select		= 0,
+	.mode			= SPI_MODE_3,
+	.bits_per_word		= 8,
+};
+
+struct position {
+	struct spi_message	*msg;
+	struct spi_transfer	*trans;
+	int			byte;
+};
+
+#define NUM_TXRAM		32
+#define NUM_RXRAM		32
+#define NUM_CDRAM		16
+
+struct bcm_mspi_hw {
+	u32			spcr0_lsb;		/* 0x000 */
+	u32			spcr0_msb;		/* 0x004 */
+	u32			spcr1_lsb;		/* 0x008 */
+	u32			spcr1_msb;		/* 0x00c */
+	u32			newqp;			/* 0x010 */
+	u32			endqp;			/* 0x014 */
+	u32			spcr2;			/* 0x018 */
+	u32			reserved0;		/* 0x01c */
+	u32			mspi_status;		/* 0x020 */
+	u32			cptqp;			/* 0x024 */
+
+#ifdef CONFIG_BRCM_MSPI_LEGACY
+	u32			reserved1[6];		/* 0x028 */
+#else
+	/* MSPI v1.5 has a revision register */
+	u32			spcr3;			/* 0x028 */
+	u32			revision;		/* 0x02c */
+	u32			reserved1[4];		/* 0x030 */
+#endif
+
+	u32			txram[NUM_TXRAM];	/* 0x040 */
+	u32			rxram[NUM_RXRAM];	/* 0x0c0 */
+	u32			cdram[NUM_CDRAM];	/* 0x140 */
+};
+
+struct bcm_bspi_hw {
+	u32			revision_id;		/* 0x000 */
+	u32			scratch;		/* 0x004 */
+	u32			mast_n_boot_ctrl;	/* 0x008 */
+	u32			busy_status;		/* 0x00c */
+	u32			intr_status;		/* 0x010 */
+	u32			b0_status;		/* 0x014 */
+	u32			b0_ctrl;		/* 0x018 */
+	u32			b1_status;		/* 0x01c */
+	u32			b1_ctrl;		/* 0x020 */
+	u32			strap_override_ctrl;	/* 0x024 */
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+	u32			flex_mode_enable;	/* 0x028 */
+	u32			bits_per_cycle;		/* 0x02C */
+	u32			bits_per_phase;		/* 0x030 */
+	u32			cmd_and_mode_byte;	/* 0x034 */
+	u32			flash_upper_addr_byte;	/* 0x038 */
+	u32			xor_value;		/* 0x03C */
+	u32			xor_enable;		/* 0x040 */
+	u32			pio_mode_enable;	/* 0x044 */
+	u32			pio_iodir;		/* 0x048 */
+	u32			pio_data;		/* 0x04C */
+#endif
+};
+
+struct bcm_bspi_raf {
+	u32			start_address;		/* 0x00 */
+	u32			num_words;		/* 0x04 */
+	u32			ctrl;			/* 0x08 */
+	u32			fullness;		/* 0x0C */
+	u32			watermark;		/* 0x10 */
+	u32			status;			/* 0x14 */
+	u32			read_data;		/* 0x18 */
+	u32			word_cnt;		/* 0x1C */
+	u32			curr_addr;		/* 0x20 */
+};
+
+struct bcm_flex_mode {
+	int			width;
+	int			addrlen;
+	int			hp;
+};
+
+#define STATE_IDLE		0
+#define STATE_RUNNING		1
+#define STATE_SHUTDOWN		2
+#define STATE_SUSPEND		3
+
+struct bcmspi_priv {
+	struct platform_device	*pdev;
+	struct spi_master	*master;
+	struct clk		*clk;
+	spinlock_t		lock;
+	struct bcmspi_parms	last_parms;
+	struct position		pos;
+	struct list_head	msg_queue;
+	int			state;
+	int			outstanding_bytes;
+	int			next_udelay;
+	int			cs_change;
+	unsigned int		max_speed_hz;
+	volatile struct bcm_mspi_hw *mspi_hw;
+	int			irq;
+	struct tasklet_struct	tasklet;
+	int			curr_cs;
+
+	/* BSPI */
+	volatile struct bcm_bspi_hw *bspi_hw;
+	int			bspi_enabled;
+	/* all chip selects controlled by BSPI */
+	int			bspi_chip_select;
+
+	/* LR */
+	volatile struct bcm_bspi_raf *bspi_hw_raf;
+	struct spi_transfer	*cur_xfer;
+	u32			cur_xfer_idx;
+	u32			cur_xfer_len;
+	u32			xfer_status;
+	struct spi_message	*cur_msg;
+	u32			actual_length;
+
+	/* current flex mode settings */
+	struct bcm_flex_mode	flex_mode;
+
+	/* S3 warm boot context save */
+	u32			s3_intr2_mask;
+	u32			s3_strap_override_ctrl;
+};
+
+static void bcmspi_enable_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR, mask);
+}
+
+static void bcmspi_disable_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_SET, mask);
+}
+
+static void bcmspi_clear_interrupt(u32 mask)
+{
+	BDEV_SET_RB(BCHP_HIF_SPI_INTR2_CPU_CLEAR, mask);
+}
+
+static u32 bcmspi_read_interrupt(void)
+{
+	return BDEV_RD(BCHP_HIF_SPI_INTR2_CPU_STATUS);
+}
+
+static int bcmspi_busy_poll(struct bcmspi_priv *priv)
+{
+	int i;
+
+	/* this should normally finish within 10us */
+	for (i = 0; i < 1000; i++) {
+		if ((priv->bspi_hw->busy_status & 1) == 0)
+			return 0;
+		udelay(1);
+	}
+	dev_warn(&priv->pdev->dev, "timeout waiting for !busy_status\n");
+	return -EIO;
+}
+
+static void bcmspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
+{
+	/* SWLINUX-2407: avoid flushing if B1 prefetch is still active */
+	bcmspi_busy_poll(priv);
+
+	/* Force rising edge for the b0/b1 'flush' field */
+	priv->bspi_hw->b0_ctrl = 1;
+	priv->bspi_hw->b1_ctrl = 1;
+	priv->bspi_hw->b0_ctrl = 0;
+	priv->bspi_hw->b1_ctrl = 0;
+}
+
+static int bcmspi_lr_is_fifo_empty(struct bcmspi_priv *priv)
+{
+	return priv->bspi_hw_raf->status & BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK;
+}
+
+/* BSPI v3 LR is LE only, convert data to host endianness */
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+#define BSPI_DATA(a) (a)
+#else
+#define BSPI_DATA(a) le32_to_cpu(a)
+#endif
+
+static inline u32 bcmspi_lr_read_fifo(struct bcmspi_priv *priv)
+{
+	return BSPI_DATA(priv->bspi_hw_raf->read_data);
+}
+
+static inline void bcmspi_lr_start(struct bcmspi_priv *priv)
+{
+	priv->bspi_hw_raf->ctrl = BCHP_BSPI_RAF_CTRL_START_MASK;
+}
+
+static inline void bcmspi_lr_clear(struct bcmspi_priv *priv)
+{
+	priv->bspi_hw_raf->ctrl = BCHP_BSPI_RAF_CTRL_CLEAR_MASK;
+	bcmspi_flush_prefetch_buffers(priv);
+}
+
+static inline int bcmspi_is_4_byte_mode(struct bcmspi_priv *priv)
+{
+	return priv->flex_mode.addrlen == BSPI_ADDRLEN_4BYTES;
+}
+
+static int bcmspi_set_override_ctrl(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	u32 strap_override = priv->bspi_hw->strap_override_ctrl;
+
+	switch (width) {
+	case BSPI_WIDTH_4BIT:
+		strap_override &= ~0x2; /* clear dual mode */
+		strap_override |= 0x9; /* set quad mode + override */
+		break;
+	case BSPI_WIDTH_2BIT:
+		strap_override &= ~0x8; /* clear quad mode */
+		strap_override |= 0x3; /* set dual mode + override */
+		break;
+	case BSPI_WIDTH_1BIT:
+		strap_override &= ~0xA; /* clear quad/dual mode */
+		strap_override |= 1; /* set override */
+		break;
+	default:
+		break;
+	}
+
+	if (addrlen == BSPI_ADDRLEN_4BYTES) {
+		strap_override |= 0x5; /* set 4byte + override */
+	} else {
+		strap_override &= ~0x4; /* clear 4 byte */
+		strap_override |= 0x1; /* set override */
+	}
+
+	priv->bspi_hw->strap_override_ctrl = strap_override;
+
+	return 0;
+}
+
+#ifdef BSPI_HAS_FLEX_MODE
+static int bcmbspi_flash_type(struct bcmspi_priv *priv);
+
+static int bcmspi_set_flex_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	int bpc = 0, bpp = 0, command;
+	int flex_mode = 1, error = 0;
+
+	if (priv->bspi_hw->strap_override_ctrl & 0x1 ||
+		priv->s3_strap_override_ctrl & 0x1) {
+		flex_mode = 0;
+		command = OPCODE_FAST_READ;
+		error = bcmspi_set_override_ctrl(priv, width, addrlen, hp);
+		goto override;
+	}
+
+	switch (width) {
+	case BSPI_WIDTH_1BIT:
+		bpp = 8; /* dummy cycles */
+		if (addrlen == BSPI_ADDRLEN_3BYTES) {
+			/* default mode, does not need flex_cmd */
+			flex_mode = 0;
+			command = OPCODE_FAST_READ;
+		} else {
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+			command = OPCODE_FAST_READ_4B;
+		}
+		break;
+	case BSPI_WIDTH_2BIT:
+		bpc = 0x00000001; /* only data is 2-bit */
+		if (hp) {
+			bpc |= 0x00010100; /* address and mode are 2-bit too */
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK;
+			command = OPCODE_DIOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_DIOR_4B;
+			}
+		} else {
+			bpp = 8; /* dummy cycles */
+			command = OPCODE_DOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_DOR_4B;
+			}
+		}
+		break;
+	case BSPI_WIDTH_4BIT:
+		bpc = 0x00000002; /* only data is 4-bit */
+		if (hp) {
+			bpc |= 0x00020200; /* address and mode are 4-bit too */
+			bpp = 4; /* dummy cycles */
+			bpp |= BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK;
+			command = OPCODE_QIOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_QIOR_4B;
+			}
+		} else {
+			bpp = 8; /* dummy cycles */
+			command = OPCODE_QOR;
+			if (addrlen == BSPI_ADDRLEN_4BYTES) {
+				bpp |=
+				 BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK;
+				command = OPCODE_QOR_4B;
+			}
+		}
+		break;
+	default:
+		error = 1;
+		break;
+	}
+
+override:
+	if (!error) {
+		priv->bspi_hw->flex_mode_enable = 0;
+		priv->bspi_hw->bits_per_cycle = bpc;
+		priv->bspi_hw->bits_per_phase = bpp;
+		priv->bspi_hw->cmd_and_mode_byte = command;
+		priv->bspi_hw->flex_mode_enable = flex_mode ?
+			BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK
+			: 0;
+		DBG("%s: width=%d addrlen=%d hp=%d\n",
+			__func__, width, addrlen, hp);
+		DBG("%s: fme=%08x bpc=%08x bpp=%08x cmd=%08x\n", __func__,
+			priv->bspi_hw->flex_mode_enable,
+			priv->bspi_hw->bits_per_cycle,
+			priv->bspi_hw->bits_per_phase,
+			priv->bspi_hw->cmd_and_mode_byte);
+	}
+
+	return error;
+}
+#else
+static int bcmspi_set_flex_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	return bcmspi_set_override_ctrl(priv, width, addrlen, hp);
+}
+#endif
+
+static void bcmspi_set_mode(struct bcmspi_priv *priv,
+	int width, int addrlen, int hp)
+{
+	int error = 0;
+
+	if (width == -1)
+		width = priv->flex_mode.width;
+	if (addrlen == -1)
+		addrlen = priv->flex_mode.addrlen;
+	if (hp == -1)
+		hp = priv->flex_mode.hp;
+
+	error = bcmspi_set_flex_mode(priv, width, addrlen, hp);
+
+	if (!error) {
+		priv->flex_mode.width = width;
+		priv->flex_mode.addrlen = addrlen;
+		priv->flex_mode.hp = hp;
+		dev_info(&priv->pdev->dev,
+			"%d-lane output, %d-byte address%s\n",
+			priv->flex_mode.width,
+			priv->flex_mode.addrlen,
+			priv->flex_mode.hp ? ", high-performance mode" : "");
+	} else
+		dev_warn(&priv->pdev->dev,
+			"INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
+			width, addrlen, hp);
+}
+
+static void bcmspi_set_chip_select(struct bcmspi_priv *priv, int cs)
+{
+	if (priv->curr_cs != cs) {
+		DBG("Switching CS%1d => CS%1d\n",
+			priv->curr_cs, cs);
+		BDEV_WR_RB(BCHP_EBI_CS_SPI_SELECT,
+			(BDEV_RD(BCHP_EBI_CS_SPI_SELECT) & ~0xff) |
+			(1 << cs));
+		udelay(10);
+	}
+	priv->curr_cs = cs;
+
+}
+
+static inline int is_bspi_chip_select(struct bcmspi_priv *priv, u8 cs)
+{
+	return priv->bspi_chip_select & (1 << cs);
+}
+
+static void bcmspi_disable_bspi(struct bcmspi_priv *priv)
+{
+	if (!priv->bspi_hw || !priv->bspi_enabled)
+		return;
+
+	priv->bspi_enabled = 0;
+	if ((priv->bspi_hw->mast_n_boot_ctrl & 1) == 1)
+		return;
+
+	DBG("disabling bspi\n");
+	bcmspi_busy_poll(priv);
+	priv->bspi_hw->mast_n_boot_ctrl = 1;
+	udelay(1);
+}
+
+static void bcmspi_enable_bspi(struct bcmspi_priv *priv)
+{
+	if (!priv->bspi_hw || priv->bspi_enabled)
+		return;
+	if ((priv->bspi_hw->mast_n_boot_ctrl & 1) == 0) {
+		priv->bspi_enabled = 1;
+		return;
+	}
+
+	DBG("enabling bspi\n");
+	bcmspi_flush_prefetch_buffers(priv);
+	udelay(1);
+	priv->bspi_hw->mast_n_boot_ctrl = 0;
+	priv->bspi_enabled = 1;
+}
+
+static void bcmspi_hw_set_parms(struct bcmspi_priv *priv,
+	const struct bcmspi_parms *xp)
+{
+	if (xp->speed_hz) {
+		unsigned int spbr = MSPI_BASE_FREQ / (2 * xp->speed_hz);
+
+		priv->mspi_hw->spcr0_lsb = max(min(spbr, SPBR_MAX), SPBR_MIN);
+	} else {
+		priv->mspi_hw->spcr0_lsb = SPBR_MIN;
+	}
+	priv->mspi_hw->spcr0_msb =
+#ifdef CONFIG_BRCM_MSPI_LEGACY
+		0x80 |	/* MSTR bit */
+#endif
+		((xp->bits_per_word ? xp->bits_per_word : 8) << 2) |
+		(xp->mode & 3);
+	priv->last_parms = *xp;
+}
+
+#define PARMS_NO_OVERRIDE		0
+#define PARMS_OVERRIDE			1
+
+static int bcmspi_update_parms(struct bcmspi_priv *priv,
+	struct spi_device *spidev, struct spi_transfer *trans, int override)
+{
+	struct bcmspi_parms xp;
+
+	xp.speed_hz = min(trans->speed_hz ? trans->speed_hz :
+		(spidev->max_speed_hz ? spidev->max_speed_hz : MAX_SPEED_HZ),
+		MAX_SPEED_HZ);
+	xp.chip_select = spidev->chip_select;
+	xp.mode = spidev->mode;
+	xp.bits_per_word = trans->bits_per_word ? trans->bits_per_word :
+		(spidev->bits_per_word ? spidev->bits_per_word : 8);
+
+	if ((override == PARMS_OVERRIDE) ||
+		((xp.speed_hz == priv->last_parms.speed_hz) &&
+		 (xp.chip_select == priv->last_parms.chip_select) &&
+		 (xp.mode == priv->last_parms.mode) &&
+		 (xp.bits_per_word == priv->last_parms.bits_per_word))) {
+		bcmspi_hw_set_parms(priv, &xp);
+		return 0;
+	}
+	/* no override, and parms do not match */
+	return 1;
+}
+
+
+static int bcmspi_setup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp;
+	struct bcmspi_priv *priv = spi_master_get_devdata(spi->master);
+
+	DBG("%s\n", __func__);
+
+	if (spi->bits_per_word > 16)
+		return -EINVAL;
+
+	xp = spi_get_ctldata(spi);
+	if (!xp) {
+		xp = kzalloc(sizeof(struct bcmspi_parms), GFP_KERNEL);
+		if (!xp)
+			return -ENOMEM;
+		spi_set_ctldata(spi, xp);
+	}
+	if (spi->max_speed_hz < priv->max_speed_hz)
+		xp->speed_hz = spi->max_speed_hz;
+	else
+		xp->speed_hz = 0;
+
+	xp->chip_select = spi->chip_select;
+	xp->mode = spi->mode;
+	xp->bits_per_word = spi->bits_per_word ? spi->bits_per_word : 8;
+
+	return 0;
+}
+
+/* stop at end of transfer, no other reason */
+#define FNB_BREAK_NONE			0
+/* stop at end of spi_message */
+#define FNB_BREAK_EOM			1
+/* stop at end of spi_transfer if delay */
+#define FNB_BREAK_DELAY			2
+/* stop at end of spi_transfer if cs_change */
+#define FNB_BREAK_CS_CHANGE		4
+/* stop if we run out of bytes */
+#define FNB_BREAK_NO_BYTES		8
+
+/* events that make us stop filling TX slots */
+#define FNB_BREAK_TX			(FNB_BREAK_EOM | FNB_BREAK_DELAY | \
+					 FNB_BREAK_CS_CHANGE)
+
+/* events that make us deassert CS */
+#define FNB_BREAK_DESELECT		(FNB_BREAK_EOM | FNB_BREAK_CS_CHANGE)
+
+
+static int find_next_byte(struct bcmspi_priv *priv, struct position *p,
+	struct list_head *completed, int flags)
+{
+	int ret = FNB_BREAK_NONE;
+
+	p->byte++;
+
+	while (p->byte >= p->trans->len) {
+		/* we're at the end of the spi_transfer */
+
+		/* in TX mode, need to pause for a delay or CS change */
+		if (p->trans->delay_usecs && (flags & FNB_BREAK_DELAY))
+			ret |= FNB_BREAK_DELAY;
+		if (p->trans->cs_change && (flags & FNB_BREAK_CS_CHANGE))
+			ret |= FNB_BREAK_CS_CHANGE;
+		if (ret)
+			return ret;
+
+		/* advance to next spi_message? */
+		if (list_is_last(&p->trans->transfer_list,
+				&p->msg->transfers)) {
+			struct spi_message *next_msg = NULL;
+
+			/* TX breaks at the end of each message as well */
+			if (!completed || (flags & FNB_BREAK_EOM)) {
+				DBG("find_next_byte: advance msg exit\n");
+				return FNB_BREAK_EOM;
+			}
+			if (!list_is_last(&p->msg->queue, &priv->msg_queue)) {
+				next_msg = list_entry(p->msg->queue.next,
+					struct spi_message, queue);
+			}
+			/* delete from run queue, add to completion queue */
+			list_del(&p->msg->queue);
+			list_add_tail(&p->msg->queue, completed);
+
+			p->msg = next_msg;
+			p->byte = 0;
+			if (p->msg == NULL) {
+				p->trans = NULL;
+				ret = FNB_BREAK_NO_BYTES;
+				break;
+			}
+
+			/*
+			 * move on to the first spi_transfer of the new
+			 * spi_message
+			 */
+			p->trans = list_entry(p->msg->transfers.next,
+				struct spi_transfer, transfer_list);
+		} else {
+			/* or just advance to the next spi_transfer */
+			p->trans = list_entry(p->trans->transfer_list.next,
+				struct spi_transfer, transfer_list);
+			p->byte = 0;
+		}
+	}
+	DBG("find_next_byte: msg %p trans %p len %d byte %d ret %x\n",
+		p->msg, p->trans, p->trans ? p->trans->len : 0, p->byte, ret);
+	return ret;
+}
+
+static void read_from_hw(struct bcmspi_priv *priv, struct list_head *completed)
+{
+	struct position p;
+	int slot = 0, n = priv->outstanding_bytes;
+
+	DBG("%s\n", __func__);
+
+	p = priv->pos;
+
+	while (n > 0) {
+		BUG_ON(p.msg == NULL);
+
+		if (p.trans->bits_per_word <= 8) {
+			u8 *buf = p.trans->rx_buf;
+
+			if (buf) {
+				buf[p.byte] =
+					priv->mspi_hw->rxram[(slot << 1) + 1]
+						& 0xff;
+			}
+			DBG("RD %02x\n", buf ? buf[p.byte] : 0xff);
+		} else {
+			u16 *buf = p.trans->rx_buf;
+
+			if (buf) {
+				buf[p.byte] =
+					((priv->mspi_hw->rxram[(slot << 1) + 1]
+						& 0xff) << 0) |
+					((priv->mspi_hw->rxram[(slot << 1) + 0]
+						& 0xff) << 8);
+			}
+		}
+		slot++;
+		n--;
+		p.msg->actual_length++;
+
+		find_next_byte(priv, &p, completed, FNB_BREAK_NONE);
+	}
+
+	priv->pos = p;
+	priv->outstanding_bytes = 0;
+}
+
+static void write_to_hw(struct bcmspi_priv *priv)
+{
+	struct position p;
+	int slot = 0, fnb = 0;
+	struct spi_message *msg = NULL;
+
+	DBG("%s\n", __func__);
+
+	bcmspi_disable_bspi(priv);
+
+	p = priv->pos;
+
+	while (1) {
+		if (p.msg == NULL)
+			break;
+		if (!msg) {
+			msg = p.msg;
+			bcmspi_update_parms(priv, msg->spi, p.trans,
+				PARMS_OVERRIDE);
+		} else {
+			/* break if the speed, bits, etc. changed */
+			if (bcmspi_update_parms(priv, msg->spi, p.trans,
+				PARMS_NO_OVERRIDE)) {
+				DBG("parms don't match, breaking\n");
+				break;
+			}
+		}
+		if (p.trans->bits_per_word <= 8) {
+			const u8 *buf = p.trans->tx_buf;
+
+			priv->mspi_hw->txram[slot << 1] = buf ?
+				(buf[p.byte] & 0xff) : 0xff;
+			DBG("WR %02x\n", buf ? buf[p.byte] : 0xff);
+		} else {
+			const u16 *buf = p.trans->tx_buf;
+
+			priv->mspi_hw->txram[(slot << 1) + 0] = buf ?
+				(buf[p.byte] >> 8) : 0xff;
+			priv->mspi_hw->txram[(slot << 1) + 1] = buf ?
+				(buf[p.byte] & 0xff) : 0xff;
+		}
+		priv->mspi_hw->cdram[slot] =
+			((p.trans->bits_per_word <= 8) ? 0x8e : 0xce);
+		slot++;
+
+		fnb = find_next_byte(priv, &p, NULL, FNB_BREAK_TX);
+
+		if (fnb & FNB_BREAK_CS_CHANGE)
+			priv->cs_change = 1;
+		if (fnb & FNB_BREAK_DELAY)
+			priv->next_udelay = p.trans->delay_usecs;
+		if (fnb || (slot == NUM_CDRAM))
+			break;
+	}
+	if (slot) {
+		DBG("submitting %d slots\n", slot);
+		priv->mspi_hw->newqp = 0;
+		priv->mspi_hw->endqp = slot - 1;
+
+		/* deassert CS on the final byte */
+		if (fnb & FNB_BREAK_DESELECT)
+			priv->mspi_hw->cdram[slot - 1] &= ~0x80;
+
+		/* tell HIF_MSPI which CS to use */
+		bcmspi_set_chip_select(priv, msg->spi->chip_select);
+
+		BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock, 1);
+		priv->mspi_hw->spcr2 = 0xe0;	/* cont | spe | spifie */
+
+		priv->state = STATE_RUNNING;
+		priv->outstanding_bytes = slot;
+	} else {
+		BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock, 0);
+		priv->state = STATE_IDLE;
+	}
+}
+
+#define DWORD_ALIGNED(a) (!(((unsigned long)(a)) & 3))
+#define ADDR_TO_4MBYTE_SEGMENT(addr)	(((u32)(addr)) >> 22)
+
+static int bcmspi_emulate_flash_read(struct bcmspi_priv *priv,
+	struct spi_message *msg)
+{
+	struct spi_transfer *trans;
+	u32 addr, len, len_in_dwords;
+	u8 *buf;
+	unsigned long flags;
+	int idx;
+
+#ifndef BSPI_HAS_4BYTE_ADDRESS
+	/* 4-byte address mode is not supported through BSPI */
+	if (bcmspi_is_4_byte_mode(priv))
+		return -1;
+#endif
+
+	/* acquire lock when the MSPI is idle */
+	while (1) {
+		spin_lock_irqsave(&priv->lock, flags);
+		if (priv->state == STATE_IDLE)
+			break;
+		spin_unlock_irqrestore(&priv->lock, flags);
+		if (priv->state == STATE_SHUTDOWN)
+			return -EIO;
+		udelay(1);
+	}
+	bcmspi_set_chip_select(priv, msg->spi->chip_select);
+
+	/* first transfer - OPCODE_READ + {3,4}-byte address */
+	trans = list_entry(msg->transfers.next, struct spi_transfer,
+		transfer_list);
+	buf = (void *)trans->tx_buf;
+
+	idx = 1;
+
+#ifdef BSPI_HAS_4BYTE_ADDRESS
+	if (bcmspi_is_4_byte_mode(priv))
+		priv->bspi_hw->flash_upper_addr_byte = buf[idx++] << 24;
+	else
+		priv->bspi_hw->flash_upper_addr_byte = 0;
+#endif
+
+	addr = (buf[idx] << 16) | (buf[idx+1] << 8) | buf[idx+2];
+	addr |= priv->bspi_hw->flash_upper_addr_byte;
+
+	/* second transfer - read result into buffer */
+	trans = list_entry(msg->transfers.next->next, struct spi_transfer,
+		transfer_list);
+
+	buf = (void *)trans->rx_buf;
+	len = trans->len;
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS < 4
+	/*
+	 * The address coming into this function is a raw flash offset.  But
+	 * for BSPI <= V3, we need to convert it to a remapped BSPI address.
+	 * If it crosses a 4MB boundary, just revert back to using MSPI.
+	 */
+	addr = (addr + 0xc00000) & 0xffffff;
+
+	if (ADDR_TO_4MBYTE_SEGMENT(addr) ^
+	    ADDR_TO_4MBYTE_SEGMENT(addr + len - 1)) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -1;
+	}
+#endif
+
+	/* non-aligned and very short transfers are handled by MSPI */
+	if (unlikely(!DWORD_ALIGNED(addr) ||
+		     !DWORD_ALIGNED(buf) ||
+		     len < sizeof(u32) ||
+		     !priv->bspi_hw_raf)) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -1;
+	}
+
+	bcmspi_enable_bspi(priv);
+
+	len_in_dwords = (len + 3) >> 2;
+
+	/* initialize software parameters */
+	priv->xfer_status = 0;
+	priv->cur_xfer = trans;
+	priv->cur_xfer_idx = 0;
+	priv->cur_xfer_len = len;
+	priv->cur_msg = msg;
+	priv->actual_length = idx + 4 + trans->len;
+
+	/* setup hardware */
+	/* address must be 4-byte aligned */
+	priv->bspi_hw_raf->start_address = addr;
+	priv->bspi_hw_raf->num_words = len_in_dwords;
+	priv->bspi_hw_raf->watermark = 0;
+
+	DBG("READ: %08x %08x (%08x)\n", addr, len_in_dwords, trans->len);
+
+	bcmspi_clear_interrupt(0xffffffff);
+	bcmspi_enable_interrupt(BSPI_LR_INTERRUPTS_ALL);
+	bcmspi_lr_start(priv);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static int bcmspi_transfer(struct spi_device *spi, struct spi_message *msg)
+{
+	struct bcmspi_priv *priv = spi_master_get_devdata(spi->master);
+	unsigned long flags;
+
+	if (is_bspi_chip_select(priv, msg->spi->chip_select)) {
+		struct spi_transfer *trans;
+
+		trans = list_entry(msg->transfers.next,
+			struct spi_transfer, transfer_list);
+		if (trans && trans->len && trans->tx_buf) {
+			u8 command = ((u8 *)trans->tx_buf)[0];
+			switch (command) {
+			case OPCODE_FAST_READ_4B:
+				if (!bcmspi_is_4_byte_mode(priv))
+					bcmspi_set_mode(priv, -1,
+						 BSPI_ADDRLEN_4BYTES, -1);
+				/* fall through */
+			case OPCODE_FAST_READ:
+				if (bcmspi_emulate_flash_read(priv, msg) == 0)
+					return 0;
+				break;
+			case OPCODE_QIOR_4B:
+			case OPCODE_QOR_4B:
+			case OPCODE_QOR:
+				if (bcmspi_emulate_flash_read(priv, msg) == 0)
+					return 0;
+				break;
+			case OPCODE_EN4B:
+				DBG("ENABLE 4-BYTE MODE\n");
+				bcmspi_set_mode(priv, -1,
+					BSPI_ADDRLEN_4BYTES, -1);
+				break;
+			case OPCODE_EX4B:
+				DBG("DISABLE 4-BYTE MODE\n");
+				bcmspi_set_mode(priv, -1,
+					BSPI_ADDRLEN_3BYTES, -1);
+				break;
+			case OPCODE_BRWR:
+				{
+					u8 enable = ((u8 *)trans->tx_buf)[1];
+					DBG("%s 4-BYTE MODE\n",
+					    enable ? "ENABLE" : "DISABLE");
+					bcmspi_set_mode(priv, -1,
+						enable ? BSPI_ADDRLEN_4BYTES :
+						BSPI_ADDRLEN_3BYTES, -1);
+				}
+				break;
+			case OPCODE_PP:
+				DBG("Program page 2-3Byte addressing command:\n");
+				break;
+			case OPCODE_PP_4B:
+				DBG("Program page 4Byte addressing command:\n");
+				break;
+
+			default:
+				break;
+			}
+		}
+	}
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	if (priv->state == STATE_SHUTDOWN) {
+		spin_unlock_irqrestore(&priv->lock, flags);
+		return -EIO;
+	}
+
+	msg->actual_length = 0;
+
+	list_add_tail(&msg->queue, &priv->msg_queue);
+
+	if (priv->state == STATE_IDLE) {
+		BUG_ON(priv->pos.msg != NULL);
+		priv->pos.msg = msg;
+		priv->pos.trans = list_entry(msg->transfers.next,
+			struct spi_transfer, transfer_list);
+		priv->pos.byte = 0;
+
+		write_to_hw(priv);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static void bcmspi_cleanup(struct spi_device *spi)
+{
+	struct bcmspi_parms *xp = spi_get_ctldata(spi);
+
+	DBG("%s\n", __func__);
+
+	kfree(xp);
+}
+
+static irqreturn_t bcmspi_interrupt(int irq, void *dev_id)
+{
+	struct bcmspi_priv *priv = dev_id;
+
+	if (priv->bspi_enabled && priv->cur_xfer) {
+		int done = 0;
+		u32 status = bcmspi_read_interrupt();
+		u32 *buf = (u32 *)priv->cur_xfer->rx_buf;
+		if (status & BSPI_LR_INTERRUPTS_DATA) {
+			while (!bcmspi_lr_is_fifo_empty(priv)) {
+				u32 data = bcmspi_lr_read_fifo(priv);
+				if (likely(priv->cur_xfer_len >= 4)) {
+					buf[priv->cur_xfer_idx++] = data;
+					priv->cur_xfer_len -= 4;
+				} else {
+					/*
+					 * Read out remaining bytes, make sure
+					 * we do not cross the buffer boundary
+					 */
+					u8 *cbuf =
+						(u8 *)&buf[priv->cur_xfer_idx];
+					data = cpu_to_le32(data);
+					while (priv->cur_xfer_len) {
+						*cbuf++ = (u8)data;
+						data >>= 8;
+						priv->cur_xfer_len--;
+					}
+				}
+			}
+		}
+		if (status & BSPI_LR_INTERRUPTS_ERROR) {
+			dev_err(&priv->pdev->dev, "ERROR %02x\n", status);
+			priv->xfer_status = -EIO;
+		} else if (!priv->cur_xfer_len)
+			done = 1;
+		if (done) {
+			priv->cur_xfer = NULL;
+			bcmspi_disable_interrupt(BSPI_LR_INTERRUPTS_ALL);
+
+			if (priv->xfer_status) {
+				bcmspi_lr_clear(priv);
+			} else {
+				bcmspi_flush_prefetch_buffers(priv);
+
+				if (priv->cur_msg) {
+					priv->cur_msg->actual_length =
+						priv->actual_length;
+					priv->cur_msg->complete(
+						priv->cur_msg->context);
+					priv->cur_msg->status = 0;
+				}
+			}
+			priv->cur_msg = NULL;
+		}
+		bcmspi_clear_interrupt(status);
+		return IRQ_HANDLED;
+	}
+
+	if (priv->mspi_hw->mspi_status & 1) {
+		/* clear interrupt */
+		priv->mspi_hw->mspi_status &= ~1;
+		bcmspi_clear_interrupt(
+			BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
+
+		tasklet_schedule(&priv->tasklet);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+static void bcmspi_tasklet(unsigned long param)
+{
+	struct bcmspi_priv *priv = (void *)param;
+	struct list_head completed;
+	struct spi_message *msg;
+	unsigned long flags;
+
+	INIT_LIST_HEAD(&completed);
+	spin_lock_irqsave(&priv->lock, flags);
+
+	if (priv->next_udelay) {
+		udelay(priv->next_udelay);
+		priv->next_udelay = 0;
+	}
+
+	msg = priv->pos.msg;
+
+	read_from_hw(priv, &completed);
+	if (priv->cs_change) {
+		udelay(10);
+		priv->cs_change = 0;
+	}
+
+	write_to_hw(priv);
+
+	while (!list_empty(&completed)) {
+		msg = list_first_entry(&completed, struct spi_message, queue);
+		list_del(&msg->queue);
+		msg->status = 0;
+		if (msg->complete)
+			msg->complete(msg->context);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void bcmspi_complete(void *arg)
+{
+	complete(arg);
+}
+
+static int bcmspi_simple_transaction(struct bcmspi_priv *priv,
+	const void *tx_buf, int tx_len, void *rx_buf, int rx_len)
+{
+	struct bcmspi_parms *xp = &priv->last_parms;
+	DECLARE_COMPLETION_ONSTACK(fini);
+	struct spi_message m;
+	struct spi_transfer t_tx, t_rx;
+	struct spi_device spi;
+	int ret;
+
+	memset(&spi, 0, sizeof(spi));
+	spi.max_speed_hz = xp->speed_hz;
+	spi.chip_select = xp->chip_select;
+	spi.mode = xp->mode;
+	spi.bits_per_word = xp->bits_per_word;
+	spi.master = priv->master;
+
+	spi_message_init(&m);
+	m.complete = bcmspi_complete;
+	m.context = &fini;
+	m.spi = &spi;
+
+	memset(&t_tx, 0, sizeof(t_tx));
+	memset(&t_rx, 0, sizeof(t_rx));
+	t_tx.tx_buf = tx_buf;
+	t_tx.len = tx_len;
+	t_rx.rx_buf = rx_buf;
+	t_rx.len = rx_len;
+
+	if (tx_len)
+		spi_message_add_tail(&t_tx, &m);
+	if (rx_len)
+		spi_message_add_tail(&t_rx, &m);
+
+	ret = bcmspi_transfer(&spi, &m);
+	if (!ret)
+		wait_for_completion(&fini);
+	return ret;
+}
+
+static void bcmspi_hw_init(struct bcmspi_priv *priv)
+{
+	priv->mspi_hw->spcr1_lsb = 0;
+	priv->mspi_hw->spcr1_msb = 0;
+	priv->mspi_hw->newqp = 0;
+	priv->mspi_hw->endqp = 0;
+	priv->mspi_hw->spcr2 = 0x20;	/* spifie */
+#ifndef CONFIG_BRCM_MSPI_LEGACY
+	priv->mspi_hw->spcr3 = 0;
+#endif
+
+	bcmspi_hw_set_parms(priv, &bcmspi_default_parms_cs0);
+
+	if (!priv->bspi_hw)
+		return;
+
+	priv->bspi_enabled = 1;
+	bcmspi_disable_bspi(priv);
+
+#if CONFIG_BRCM_BSPI_MAJOR_VERS >= 4
+	/* Force a sane 1:1 mapping of BSPI address -> flash offset */
+	priv->bspi_hw->xor_enable = 1;
+	priv->bspi_hw->xor_value = 0;
+#endif
+
+	priv->bspi_hw->b0_ctrl = 0;
+	priv->bspi_hw->b1_ctrl = 0;
+}
+
+static void bcmspi_hw_uninit(struct bcmspi_priv *priv)
+{
+	priv->mspi_hw->spcr2 = 0x0;	/* disable irq and enable bits */
+	bcmspi_enable_bspi(priv);
+}
+
+static int bcmbspi_flash_type(struct bcmspi_priv *priv)
+{
+	char tx_buf[4];
+	unsigned char jedec_id[5] = {0};
+
+	/* command line override */
+	if (bspi_flash != BSPI_FLASH_TYPE_UNKNOWN)
+		return bspi_flash;
+
+	/* Read ID */
+	tx_buf[0] = OPCODE_RDID;
+	bcmspi_simple_transaction(priv, tx_buf, 1, &jedec_id, 5);
+
+	switch (jedec_id[0]) {
+	case 0x01: /* Spansion */
+	case 0xef:
+		bspi_flash = BSPI_FLASH_TYPE_SPANSION;
+		break;
+	case 0xc2: /* Macronix */
+		bspi_flash = BSPI_FLASH_TYPE_MACRONIX;
+		break;
+	case 0xbf: /* SST */
+		bspi_flash = BSPI_FLASH_TYPE_SST;
+		break;
+	case 0x89: /* Numonyx */
+		bspi_flash = BSPI_FLASH_TYPE_NUMONYX;
+		break;
+	default:
+		bspi_flash = BSPI_FLASH_TYPE_UNKNOWN;
+		break;
+	}
+	return bspi_flash;
+}
+
+static int bcmspi_set_quad_mode(struct bcmspi_priv *priv, int _enable)
+{
+	char tx_buf[4];
+	unsigned char cfg_reg, sts_reg, sr1_reg;
+
+	switch (bcmbspi_flash_type(priv)) {
+	case BSPI_FLASH_TYPE_SPANSION:
+		/* RSR1 */
+		tx_buf[0] = OPCODE_RDSR;
+		bcmspi_simple_transaction(priv, tx_buf, 1, &sr1_reg, 1);
+		/* RCR */
+		tx_buf[0] = OPCODE_RCR;
+		bcmspi_simple_transaction(priv, tx_buf, 1, &cfg_reg, 1);
+		if (_enable)
+			cfg_reg |= 0x2;
+		else
+			cfg_reg &= ~0x2;
+		/* WREN */
+		tx_buf[0] = OPCODE_WREN;
+		bcmspi_simple_transaction(priv, tx_buf, 1, NULL, 0);
+		/* WRR */
+		tx_buf[0] = OPCODE_WRR;
+		tx_buf[1] = sr1_reg; /* status register */
+		tx_buf[2] = cfg_reg; /* configuration register */
+		bcmspi_simple_transaction(priv, tx_buf, 3, NULL, 0);
+		/* wait till ready */
+		do {
+			tx_buf[0] = OPCODE_RDSR;
+			bcmspi_simple_transaction(priv, tx_buf, 1, &sts_reg,
+						  1);
+			udelay(1);
+		} while (sts_reg & 1);
+		break;
+	case BSPI_FLASH_TYPE_MACRONIX:
+		/* RDSR */
+		tx_buf[0] = OPCODE_RDSR;
+		bcmspi_simple_transaction(priv, tx_buf, 1, &cfg_reg, 1);
+		if (_enable)
+			cfg_reg |= 0x40;
+		else
+			cfg_reg &= ~0x40;
+		/* WREN */
+		tx_buf[0] = OPCODE_WREN;
+		bcmspi_simple_transaction(priv, tx_buf, 1, NULL, 0);
+		/* WRSR */
+		tx_buf[0] = OPCODE_WRSR;
+		tx_buf[1] = cfg_reg; /* status register */
+		bcmspi_simple_transaction(priv, tx_buf, 2, NULL, 0);
+		/* wait till ready */
+		do {
+			tx_buf[0] = OPCODE_RDSR;
+			bcmspi_simple_transaction(priv, tx_buf, 1, &sts_reg,
+						  1);
+			udelay(1);
+		} while (sts_reg & 1);
+		/* RDSR */
+		tx_buf[0] = OPCODE_RDSR;
+		bcmspi_simple_transaction(priv, tx_buf, 1, &cfg_reg, 1);
+		break;
+	case BSPI_FLASH_TYPE_SST:
+	case BSPI_FLASH_TYPE_NUMONYX:
+		/* TODO - send Quad mode control command */
+		break;
+	default:
+		if (_enable)
+			dev_err(&priv->pdev->dev,
+				"Unrecognized flash type, no QUAD MODE support");
+		return _enable ? -1 : 0;
+	}
+
+	return 0;
+}
+
+static int bcmspi_enable_disable_4byte_addressing(struct bcmspi_priv *priv,
+						  int _enable)
+{
+	char tx_buf[4];
+	int ret = 0;
+
+	switch (bcmbspi_flash_type(priv)) {
+	case BSPI_FLASH_TYPE_SPANSION:
+		tx_buf[0] = OPCODE_BRWR;
+		if (_enable)
+			tx_buf[1] = BSPI_BR_EXTADD;
+		else
+			tx_buf[1] = 0;
+		ret = bcmspi_simple_transaction(priv, tx_buf, 2, NULL, 0);
+		break;
+	case BSPI_FLASH_TYPE_SST:
+	case BSPI_FLASH_TYPE_NUMONYX:
+	case BSPI_FLASH_TYPE_MACRONIX:
+		/* enable write by sending WREN */
+		tx_buf[0] = OPCODE_WREN;
+		ret = bcmspi_simple_transaction(priv, tx_buf, 1, NULL, 0);
+		if (ret != 0)
+			return ret;
+
+		if (_enable)
+			tx_buf[0] = OPCODE_EN4B;
+		else
+			tx_buf[0] = OPCODE_EX4B;
+		ret = bcmspi_simple_transaction(priv, tx_buf, 1, NULL, 0);
+		break;
+	default:
+		if (_enable)
+			dev_err(&priv->pdev->dev,
+				"4-byte addressing not supported\n");
+		return _enable ? -1 : 0;
+	}
+
+	if (ret != 0)
+		dev_err(&priv->pdev->dev,
+			"Unable to enter/exit 4-byte address mode\n");
+
+	return ret;
+}
+
+/* Configure the BSPI chip-select */
+static int bcmspi_bspi_config_cs(struct bcmspi_priv *priv)
+{
+	struct platform_device *pdev = priv->pdev;
+	struct device *dev = &pdev->dev;
+	struct device_node *dn = dev->of_node, *childnode;
+	struct spi_master *master = priv->master;
+	struct brcmspi_platform_data *pdata;
+
+	pdata = (struct brcmspi_platform_data *)pdev->dev.platform_data;
+
+	if (!priv->bspi_hw) {
+		priv->bspi_chip_select = 0;
+		return 0;
+	}
+
+	priv->bspi_chip_select = 0;
+	for_each_child_of_node(dn, childnode) {
+		if (of_find_property(childnode, "use-bspi", NULL)) {
+			const u32 *regp;
+			int size;
+
+			/* "reg" field holds chip-select number */
+			regp = of_get_property(childnode, "reg", &size);
+			if (!regp || size != sizeof(*regp))
+				return -EINVAL;
+			if (regp[0] < master->num_chipselect)
+				priv->bspi_chip_select |= (1 << regp[0]);
+		}
+	}
+
+	if (pdata)
+		priv->bspi_chip_select = (priv->bspi_hw && pdata) ? pdata->flash_cs : 0;
+
+	return 0;
+}
+
+static int bcmspi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct bcmspi_priv *priv;
+	struct spi_master *master;
+	struct resource *res;
+	int ret;
+	u32 temp;
+
+	DBG("bcmspi_probe\n");
+
+	BDEV_WR_RB(BCHP_BSPI_MAST_N_BOOT_CTRL, 1);
+	bcmspi_disable_interrupt(0xffffffff);
+	bcmspi_clear_interrupt(0xffffffff);
+	bcmspi_enable_interrupt(BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
+
+	master = spi_alloc_master(dev, sizeof(struct bcmspi_priv));
+	if (!master) {
+		dev_err(&pdev->dev, "error allocating spi_master\n");
+		return -ENOMEM;
+	}
+
+	priv = spi_master_get_devdata(master);
+
+	priv->pdev = pdev;
+	priv->state = STATE_IDLE;
+	priv->pos.msg = NULL;
+	priv->master = master;
+
+	master->bus_num = pdev->id;
+	if (!of_property_read_u32(dev->of_node, "num-cs", &temp)) {
+		master->num_chipselect = temp;
+	} else {
+		/* Not provided by device-tree; use default */
+		master->num_chipselect = NUM_CHIPSELECT;
+	}
+	master->mode_bits = SPI_MODE_3;
+
+	master->setup = bcmspi_setup;
+	master->transfer = bcmspi_transfer;
+	master->cleanup = bcmspi_cleanup;
+	master->dev.of_node = dev->of_node;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "can't get resource 0\n");
+		ret = -EIO;
+		goto err2;
+	}
+	/* MSPI register range */
+	priv->mspi_hw = (volatile void *)devm_ioremap(&pdev->dev,
+		res->start, res->end - res->start);
+	if (!priv->mspi_hw) {
+		dev_err(&pdev->dev, "can't ioremap\n");
+		ret = -EIO;
+		goto err2;
+	}
+
+	/* IRQ */
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ defined\n");
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	ret = devm_request_irq(&pdev->dev, priv->irq, bcmspi_interrupt, 0,
+			"spi_brcmstb", priv);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "unable to allocate IRQ\n");
+		goto err2;
+	}
+
+	/* BSPI register range (not supported on all platforms) */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res && !nobspi) {
+		priv->bspi_hw = (volatile void *)devm_ioremap(&pdev->dev,
+			res->start, res->end - res->start);
+		if (!priv->bspi_hw) {
+			dev_err(&pdev->dev, "can't ioremap BSPI range\n");
+			ret = -EIO;
+			goto err2;
+		}
+	} else
+		priv->bspi_hw = NULL;
+
+	/* BSPI_RAF register range */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	if (res && !nobspi) {
+		priv->bspi_hw_raf = (volatile void *)devm_ioremap(&pdev->dev,
+			res->start, res->end - res->start);
+		if (!priv->bspi_hw_raf) {
+			dev_err(&pdev->dev, "can't ioremap BSPI_RAF range\n");
+			ret = -EIO;
+			goto err2;
+		}
+	} else
+		priv->bspi_hw_raf = NULL;
+
+	/* Clock */
+	priv->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(&pdev->dev, "unable to get clock\n");
+		/* Ignore, if we don't have any clocks to get */
+		priv->clk = NULL;
+	}
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to prepare clock\n");
+		goto err2;
+	}
+
+	bcmspi_hw_init(priv);
+	priv->curr_cs = -1;
+
+	ret = bcmspi_bspi_config_cs(priv);
+	if (ret) {
+		dev_err(&pdev->dev, "error detecting chip-select\n");
+		goto err1;
+	}
+
+#ifdef BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK
+	if (BDEV_RD(BCHP_SUN_TOP_CTRL_STRAP_VALUE_0) &
+		BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK) {
+		/* BSPI is disabled if the board is strapped for NAND */
+		priv->bspi_chip_select = 0;
+	}
+#endif /* BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_boot_MASK */
+
+
+	INIT_LIST_HEAD(&priv->msg_queue);
+	spin_lock_init(&priv->lock);
+
+	platform_set_drvdata(pdev, priv);
+
+	tasklet_init(&priv->tasklet, bcmspi_tasklet, (unsigned long)priv);
+
+	/* default values - undefined */
+	priv->flex_mode.width =
+	priv->flex_mode.addrlen =
+	priv->flex_mode.hp = -1;
+
+	if (priv->bspi_chip_select) {
+		if (bspi_width == BSPI_WIDTH_4BIT ||
+		   ((BDEV_RD(BCHP_BSPI_STRAP_OVERRIDE_CTRL) &
+		     BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK))) {
+			if (bcmspi_set_quad_mode(priv, BSPI_WIDTH_4BIT))
+				bspi_width = BSPI_WIDTH_1BIT;
+			else
+				bspi_width = BSPI_WIDTH_4BIT;
+		}
+		bcmspi_set_mode(priv, bspi_width, bspi_addrlen, bspi_hp);
+	}
+
+	if (bcmspi_is_4_byte_mode(priv))
+	    bcmspi_enable_disable_4byte_addressing(priv, BSPI_ADDRLEN_4BYTES);
+
+	ret = spi_register_master(master);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "can't register master\n");
+		goto err1;
+	}
+
+	return 0;
+
+err1:
+	bcmspi_hw_uninit(priv);
+	clk_disable_unprepare(priv->clk);
+err2:
+	spi_master_put(master);
+	return ret;
+}
+
+static int bcmspi_remove(struct platform_device *pdev)
+{
+	struct bcmspi_priv *priv = platform_get_drvdata(pdev);
+	unsigned long flags;
+
+	/* acquire lock when the MSPI is idle */
+	while (1) {
+		spin_lock_irqsave(&priv->lock, flags);
+		if (priv->state == STATE_IDLE)
+			break;
+		spin_unlock_irqrestore(&priv->lock, flags);
+		udelay(100);
+	}
+	priv->state = STATE_SHUTDOWN;
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	tasklet_kill(&priv->tasklet);
+	platform_set_drvdata(pdev, NULL);
+	bcmspi_hw_uninit(priv);
+	clk_disable_unprepare(priv->clk);
+	spi_unregister_master(priv->master);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int bcmspi_suspend(struct device *dev)
+{
+	struct bcmspi_priv *priv = dev_get_drvdata(dev);
+	unsigned long flags;
+
+	/* acquire lock when the MSPI is idle */
+	while (1) {
+		spin_lock_irqsave(&priv->lock, flags);
+		if (priv->state == STATE_IDLE) {
+			BDEV_WR_F_RB(HIF_MSPI_WRITE_LOCK, WriteLock, 0);
+			priv->state = STATE_SUSPEND;
+			break;
+		}
+		spin_unlock_irqrestore(&priv->lock, flags);
+		if (priv->state == STATE_SHUTDOWN)
+			return -EIO;
+		udelay(1);
+	}
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	priv->s3_intr2_mask = BDEV_RD(BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS);
+	priv->s3_strap_override_ctrl = BDEV_RD(BCHP_BSPI_STRAP_OVERRIDE_CTRL);
+
+	clk_disable(priv->clk);
+	bcmspi_hw_uninit(priv);
+	return 0;
+};
+
+static int bcmspi_resume(struct device *dev)
+{
+	struct bcmspi_priv *priv = dev_get_drvdata(dev);
+	int curr_cs = priv->curr_cs;
+	int width = -1, addrlen = -1;
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+	priv->state = STATE_IDLE;
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	ret = clk_enable(priv->clk);
+	if (ret != 0)
+		return ret;
+
+	bcmspi_hw_init(priv);
+	priv->curr_cs = -1;
+	bcmspi_set_chip_select(priv, curr_cs);
+	BDEV_WR_RB(BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR, ~priv->s3_intr2_mask);
+
+	if (bcmspi_is_4_byte_mode(priv) ||
+	    (priv->s3_strap_override_ctrl &
+	     BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK))
+		addrlen = BSPI_ADDRLEN_4BYTES;
+
+	if (bspi_width == BSPI_WIDTH_4BIT ||
+	    (priv->s3_strap_override_ctrl &
+	     BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK)) {
+		width = BSPI_WIDTH_4BIT;
+
+		if (bcmspi_set_quad_mode(priv, width))
+			bspi_width = BSPI_WIDTH_1BIT;
+	}
+
+	bcmspi_set_mode(priv, width, addrlen, -1);
+	if (bcmspi_is_4_byte_mode(priv))
+	    bcmspi_enable_disable_4byte_addressing(priv, BSPI_ADDRLEN_4BYTES);
+
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(bcmspi_pm_ops, bcmspi_suspend, bcmspi_resume);
+
+static const struct of_device_id spi_brcmstb_of_match[] = {
+	{ .compatible = "brcm,spi-brcmstb" },
+	{},
+};
+
+static struct platform_driver spi_brcmstb_driver = {
+	.driver = {
+		.name = "spi_brcmstb",
+		.bus = &platform_bus_type,
+		.owner = THIS_MODULE,
+		.pm		= &bcmspi_pm_ops,
+		.of_match_table = spi_brcmstb_of_match,
+	},
+	.probe = bcmspi_probe,
+	.remove = bcmspi_remove,
+};
+
+module_platform_driver(spi_brcmstb_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("MSPI/HIF SPI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c
index c771b37967b2..df255269f247 100644
--- a/drivers/staging/android/ion/ion.c
+++ b/drivers/staging/android/ion/ion.c
@@ -1189,6 +1189,7 @@ static long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 		struct ion_allocation_data allocation;
 		struct ion_handle_data handle;
 		struct ion_custom_data custom;
+		struct ion_phys_data phys;
 	} data;
 
 	dir = ion_ioctl_dir(cmd);
@@ -1265,6 +1266,23 @@ static long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 						data.custom.arg);
 		break;
 	}
+	case ION_IOC_PHYS:
+	{
+		struct ion_handle *handle;
+		ion_phys_addr_t addr;
+		size_t len;
+
+		handle = ion_handle_get_by_id(client, data.phys.handle);
+		if (IS_ERR(handle))
+			return PTR_ERR(handle);
+		ret = ion_phys(client, handle, &addr, &len);
+		ion_handle_put(handle);
+		if (ret == 0) {
+			data.phys.addr = addr;
+			data.phys.len = len;
+		}
+		break;
+	}
 	default:
 		return -ENOTTY;
 	}
@@ -1470,6 +1488,7 @@ void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap)
 #endif
 	up_write(&dev->lock);
 }
+EXPORT_SYMBOL(ion_device_add_heap);
 
 struct ion_device *ion_device_create(long (*custom_ioctl)
 				     (struct ion_client *client,
@@ -1505,6 +1524,7 @@ struct ion_device *ion_device_create(long (*custom_ioctl)
 	idev->clients = RB_ROOT;
 	return idev;
 }
+EXPORT_SYMBOL(ion_device_create);
 
 void ion_device_destroy(struct ion_device *dev)
 {
@@ -1512,6 +1532,7 @@ void ion_device_destroy(struct ion_device *dev)
 	/* XXX need to free the heaps and clients ? */
 	kfree(dev);
 }
+EXPORT_SYMBOL(ion_device_destroy);
 
 void __init ion_reserve(struct ion_platform_data *data)
 {
diff --git a/drivers/staging/android/ion/ion_heap.c b/drivers/staging/android/ion/ion_heap.c
index 37e64d51394c..d114c79d39cc 100644
--- a/drivers/staging/android/ion/ion_heap.c
+++ b/drivers/staging/android/ion/ion_heap.c
@@ -60,12 +60,14 @@ void *ion_heap_map_kernel(struct ion_heap *heap,
 
 	return vaddr;
 }
+EXPORT_SYMBOL(ion_heap_map_kernel);
 
 void ion_heap_unmap_kernel(struct ion_heap *heap,
 			   struct ion_buffer *buffer)
 {
 	vunmap(buffer->vaddr);
 }
+EXPORT_SYMBOL(ion_heap_unmap_kernel);
 
 int ion_heap_map_user(struct ion_heap *heap, struct ion_buffer *buffer,
 		      struct vm_area_struct *vma)
@@ -101,6 +103,7 @@ int ion_heap_map_user(struct ion_heap *heap, struct ion_buffer *buffer,
 	}
 	return 0;
 }
+EXPORT_SYMBOL(ion_heap_map_user);
 
 static int ion_heap_clear_pages(struct page **pages, int num, pgprot_t pgprot)
 {
@@ -289,6 +292,7 @@ struct ion_heap *ion_heap_create(struct ion_platform_heap *heap_data)
 	heap->id = heap_data->id;
 	return heap;
 }
+EXPORT_SYMBOL(ion_heap_create);
 
 void ion_heap_destroy(struct ion_heap *heap)
 {
@@ -316,3 +320,4 @@ void ion_heap_destroy(struct ion_heap *heap)
 		       heap->type);
 	}
 }
+EXPORT_SYMBOL(ion_heap_destroy);
diff --git a/drivers/staging/android/uapi/ion.h b/drivers/staging/android/uapi/ion.h
index f09e7c154d69..3af51b4188ff 100644
--- a/drivers/staging/android/uapi/ion.h
+++ b/drivers/staging/android/uapi/ion.h
@@ -127,6 +127,12 @@ struct ion_custom_data {
 	unsigned long arg;
 };
 
+struct ion_phys_data {
+	ion_user_handle_t handle;
+	unsigned long addr;
+	size_t len;
+};
+
 #define ION_IOC_MAGIC		'I'
 
 /**
@@ -193,4 +199,6 @@ struct ion_custom_data {
  */
 #define ION_IOC_CUSTOM		_IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
 
+#define ION_IOC_PHYS		_IOWR(ION_IOC_MAGIC, 8, struct ion_phys_data)
+
 #endif /* _UAPI_LINUX_ION_H */
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 5f88d767671e..2d5d51b2e81c 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -189,8 +189,7 @@ config DB8500_CPUFREQ_COOLING
 config INTEL_POWERCLAMP
 	tristate "Intel PowerClamp idle injection driver"
 	depends on THERMAL
-	depends on X86
-	depends on CPU_SUP_INTEL
+	depends on (X86 && CPU_SUP_INTEL) || ARM
 	help
 	  Enable this to enable Intel PowerClamp idle injection driver. This
 	  enforce idle time which results in more package C-state residency. The
@@ -222,6 +221,10 @@ config ACPI_INT3403_THERMAL
 	  the Intel Thermal Daemon can use this information to allow the user
 	  to select his laptop to run without turning on the fans.
 
+config BRCMSTB_THERMAL
+	tristate "Broadcom STB AVS TMON thermal driver"
+	depends on ARCH_BRCMSTB
+
 menu "Texas Instruments thermal drivers"
 source "drivers/thermal/ti-soc-thermal/Kconfig"
 endmenu
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 54e4ec9eb5df..b8a66a429d98 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_INTEL_POWERCLAMP)	+= intel_powerclamp.o
 obj-$(CONFIG_X86_PKG_TEMP_THERMAL)	+= x86_pkg_temp_thermal.o
 obj-$(CONFIG_TI_SOC_THERMAL)	+= ti-soc-thermal/
 obj-$(CONFIG_ACPI_INT3403_THERMAL)	+= int3403_thermal.o
+obj-$(CONFIG_BRCMSTB_THERMAL)	+= brcmstb_thermal.o
diff --git a/drivers/thermal/brcmstb_thermal.c b/drivers/thermal/brcmstb_thermal.c
new file mode 100644
index 000000000000..12cc0728de22
--- /dev/null
+++ b/drivers/thermal/brcmstb_thermal.c
@@ -0,0 +1,427 @@
+/*
+ * Broadcom STB AVS TMON thermal sensor driver
+ *
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define DRV_NAME	"brcmstb_thermal"
+
+#define pr_fmt(fmt)	DRV_NAME ": " fmt
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irqreturn.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/thermal.h>
+
+#define AVS_TMON_STATUS			0x00
+ #define AVS_TMON_STATUS_valid_msk	BIT(11)
+ #define AVS_TMON_STATUS_data_msk	GENMASK(10, 1)
+ #define AVS_TMON_STATUS_data_shift	1
+
+#define AVS_TMON_EN_OVERTEMP_RESET	0x04
+ #define AVS_TMON_EN_OVERTEMP_RESET_msk	BIT(0)
+
+#define AVS_TMON_RESET_THRESH		0x08
+ #define AVS_TMON_RESET_THRESH_msk	GENMASK(10, 1)
+ #define AVS_TMON_RESET_THRESH_shift	1
+
+#define AVS_TMON_INT_IDLE_TIME		0x10
+
+#define AVS_TMON_EN_TEMP_INT_SRCS	0x14
+ #define AVS_TMON_EN_TEMP_INT_SRCS_high	BIT(1)
+ #define AVS_TMON_EN_TEMP_INT_SRCS_low	BIT(0)
+
+#define AVS_TMON_INT_THRESH		0x18
+ #define AVS_TMON_INT_THRESH_high_msk	GENMASK(26, 17)
+ #define AVS_TMON_INT_THRESH_high_shift	17
+ #define AVS_TMON_INT_THRESH_low_msk	GENMASK(10, 1)
+ #define AVS_TMON_INT_THRESH_low_shift	1
+
+#define AVS_TMON_TEMP_INT_CODE		0x1c
+#define AVS_TMON_TP_TEST_ENABLE		0x20
+
+enum avs_tmon_trip_type {
+	TMON_TRIP_TYPE_LOW = 0,
+	TMON_TRIP_TYPE_HIGH,
+	TMON_TRIP_TYPE_RESET,
+	TMON_TRIP_TYPE_MAX,
+};
+
+struct avs_tmon_trip {
+	/* HW bit to enable the trip */
+	u32 enable_offs;
+	u32 enable_mask;
+
+	/* HW field to read the trip temperature */
+	u32 reg_offs;
+	u32 reg_msk;
+	int reg_shift;
+};
+
+static struct avs_tmon_trip avs_tmon_trips[] = {
+	/* Trips when temperature is below threshold */
+	[TMON_TRIP_TYPE_LOW] = {
+		.enable_offs	= AVS_TMON_EN_TEMP_INT_SRCS,
+		.enable_mask	= AVS_TMON_EN_TEMP_INT_SRCS_low,
+		.reg_offs	= AVS_TMON_INT_THRESH,
+		.reg_msk	= AVS_TMON_INT_THRESH_low_msk,
+		.reg_shift	= AVS_TMON_INT_THRESH_low_shift,
+	},
+	/* Trips when temperature is above threshold */
+	[TMON_TRIP_TYPE_HIGH] = {
+		.enable_offs	= AVS_TMON_EN_TEMP_INT_SRCS,
+		.enable_mask	= AVS_TMON_EN_TEMP_INT_SRCS_high,
+		.reg_offs	= AVS_TMON_INT_THRESH,
+		.reg_msk	= AVS_TMON_INT_THRESH_high_msk,
+		.reg_shift	= AVS_TMON_INT_THRESH_high_shift,
+	},
+	/* Automatically resets chip when above threshold */
+	[TMON_TRIP_TYPE_RESET] = {
+		.enable_offs	= AVS_TMON_EN_OVERTEMP_RESET,
+		.enable_mask	= AVS_TMON_EN_OVERTEMP_RESET_msk,
+		.reg_offs	= AVS_TMON_RESET_THRESH,
+		.reg_msk	= AVS_TMON_RESET_THRESH_msk,
+		.reg_shift	= AVS_TMON_RESET_THRESH_shift,
+	},
+};
+
+enum {
+	/*
+	 * Using the of-thermal framework
+	 */
+	AVS_TMON_OF_SENSOR_DRIVER,
+
+	/*
+	 * Old DT bindings didn't include the of-sensor framework, so support a
+	 * full zone implementation temporarily
+	 */
+	AVS_TMON_ZONE_DRIVER,
+};
+
+struct brcmstb_thermal_priv {
+	void __iomem *tmon_base;
+	struct device *dev;
+	struct thermal_zone_device *thermal;
+
+	/*
+	 * When .thermal is non-zero this member indicates whether
+	 * this driver registered as a sensor (AVS_TMON_OF_SENSOR_DRIVER)
+	 * or as a zone (AVS_TMON_ZONE_DRIVER)
+	 */
+	int regtype;
+};
+
+/* Convert a HW code to a temperature reading (millidegree celsius) */
+static inline int avs_tmon_code_to_temp(u32 code)
+{
+	return (410040 - (int)((code & 0x3FF) * 487));
+}
+
+/*
+ * Convert a temperature value (millidegree celsius) to a HW code
+ *
+ * @temp: temperature to convert
+ * @low: if true, round toward the low side
+ */
+static inline u32 avs_tmon_temp_to_code(int temp, bool low)
+{
+	if (temp < -88161)
+		return 0x3FF;	/* Maximum code value */
+
+	if (temp >= 410040)
+		return 0;	/* Minimum code value */
+
+	if (low)
+		return (u32)(DIV_ROUND_UP(410040 - temp, 487));
+	else
+		return (u32)((410040 - temp) / 487);
+}
+
+static int brcmstb_get_temp(void *data, long *temp)
+{
+	struct brcmstb_thermal_priv *priv = data;
+	u32 val;
+	long t;
+
+	val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS);
+
+	if (!(val & AVS_TMON_STATUS_valid_msk)) {
+		dev_err(priv->dev, "reading not valid\n");
+
+		return -EIO;
+	}
+
+	val = (val & AVS_TMON_STATUS_data_msk) >> AVS_TMON_STATUS_data_shift;
+
+	t = avs_tmon_code_to_temp(val);
+	if (t < 0)
+		*temp = 0;
+	else
+		*temp = t;
+
+	return 0;
+}
+
+/*
+ * Active when the of-thermal framework is not used
+ */
+static int brcmstb_get_zone_temp(struct thermal_zone_device *thermal,
+				 unsigned long *temp)
+{
+	return brcmstb_get_temp(thermal->devdata, temp);
+}
+
+static void avs_tmon_trip_enable(struct brcmstb_thermal_priv *priv,
+				 enum avs_tmon_trip_type type, int en)
+{
+	struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+	u32 val = __raw_readl(priv->tmon_base + trip->enable_offs);
+
+	pr_debug("%s trip, type %d\n", en ? "enable" : "disable", type);
+
+	if (en)
+		val |= trip->enable_mask;
+	else
+		val &= ~trip->enable_mask;
+
+	__raw_writel(val, priv->tmon_base + trip->enable_offs);
+}
+
+static int avs_tmon_get_trip_temp(struct brcmstb_thermal_priv *priv,
+				  enum avs_tmon_trip_type type)
+{
+	struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+	u32 val = __raw_readl(priv->tmon_base + trip->reg_offs);
+
+	val &= trip->reg_msk;
+	val >>= trip->reg_shift;
+
+	return avs_tmon_code_to_temp(val);
+}
+
+static void avs_tmon_set_trip_temp(struct brcmstb_thermal_priv *priv,
+				   enum avs_tmon_trip_type type,
+				   int temp)
+{
+	struct avs_tmon_trip *trip = &avs_tmon_trips[type];
+	u32 val, orig;
+
+	pr_debug("set temp %d to %d\n", type, temp);
+
+	/* round toward low temp for the low interrupt */
+	val = avs_tmon_temp_to_code(temp, type == TMON_TRIP_TYPE_LOW);
+
+	/* TODO: Check for overflow? */
+	val <<= trip->reg_shift;
+	val &= trip->reg_msk;
+
+	orig = __raw_readl(priv->tmon_base + trip->reg_offs);
+	orig &= ~trip->reg_msk;
+	orig |= val;
+	__raw_writel(orig, priv->tmon_base + trip->reg_offs);
+}
+
+static int avs_tmon_get_intr_temp(struct brcmstb_thermal_priv *priv)
+{
+	u32 val;
+
+	val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE);
+	return avs_tmon_code_to_temp(val);
+}
+
+static irqreturn_t brcmstb_tmon_irq_thread(int irq, void *data)
+{
+	struct brcmstb_thermal_priv *priv = data;
+	int low, high, intr;
+
+	low = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_LOW);
+	high = avs_tmon_get_trip_temp(priv, TMON_TRIP_TYPE_HIGH);
+	intr = avs_tmon_get_intr_temp(priv);
+
+	dev_dbg(priv->dev, "low/intr/high: %d/%d/%d\n",
+			low, intr, high);
+
+	/* Disable high-temp until next threshold shift */
+	if (intr >= high)
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
+	/* Disable low-temp until next threshold shift */
+	if (intr <= low)
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
+
+	/*
+	 * Notify using the interrupt temperature, in case the temperature
+	 * changes before it can next be read out
+	 */
+	thermal_zone_device_update_temp(priv->thermal, intr);
+
+	return IRQ_HANDLED;
+}
+
+static int brcmstb_set_trips(void *data, unsigned long low, unsigned long high)
+{
+	struct brcmstb_thermal_priv *priv = data;
+
+	pr_debug("set trips %lu <--> %lu\n", low, high);
+
+	if (low) {
+		if (low > INT_MAX) {
+			low = INT_MAX;
+		}
+		avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_LOW, (int)low);
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 1);
+	} else {
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_LOW, 0);
+	}
+
+	if (high < ULONG_MAX) {
+		if (high > INT_MAX) {
+			high = INT_MAX;
+		}
+		avs_tmon_set_trip_temp(priv, TMON_TRIP_TYPE_HIGH, (int)high);
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 1);
+	} else {
+		avs_tmon_trip_enable(priv, TMON_TRIP_TYPE_HIGH, 0);
+	}
+
+	return 0;
+}
+
+static struct thermal_zone_device_ops zone_ops = {
+	.get_temp	= brcmstb_get_zone_temp,
+};
+
+static struct thermal_zone_of_device_ops of_ops = {
+	.get_temp	= brcmstb_get_temp,
+	.set_trips	= brcmstb_set_trips,
+};
+
+static const struct of_device_id brcmstb_thermal_id_table[] = {
+	{ .compatible = "brcm,avs-tmon" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcmstb_thermal_id_table);
+
+/*
+ * Deprecated: we should be using the of-thermal framework, rather than
+ * registering our own thermal zone. This is provided as a temporary help, in
+ * case of an old device tree which does not include the thermal-zones node and
+ * sensor phandles.
+ */
+static int brcmstb_thermal_zone_probe(struct platform_device *pdev,
+				      struct brcmstb_thermal_priv *priv)
+{
+	struct thermal_zone_device *thermal;
+
+	thermal = thermal_zone_device_register("avs_tmon", 0, 0, priv,
+					       &zone_ops, NULL, 0, 0);
+	if (IS_ERR(thermal)) {
+		dev_err(&pdev->dev, "failed to register zone device\n");
+		return PTR_ERR(thermal);
+	}
+
+	priv->regtype = AVS_TMON_ZONE_DRIVER;
+	priv->thermal = thermal;
+	dev_info(&pdev->dev, "registered AVS TMON zone driver\n");
+
+	return 0;
+}
+
+static int brcmstb_thermal_probe(struct platform_device *pdev)
+{
+	struct thermal_zone_device *thermal;
+	struct brcmstb_thermal_priv *priv;
+	struct resource *res;
+	int irq, ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->tmon_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->tmon_base))
+		return PTR_ERR(priv->tmon_base);
+
+	priv->dev = &pdev->dev;
+	platform_set_drvdata(pdev, priv);
+
+	thermal = thermal_zone_of_sensor_register(&pdev->dev, 0, priv, &of_ops);
+	if (IS_ERR(thermal))
+		/*
+		 * Fall back to registering our own zone, for legacy purposes
+		 */
+		return brcmstb_thermal_zone_probe(pdev, priv);
+
+	priv->regtype = AVS_TMON_OF_SENSOR_DRIVER;
+	priv->thermal = thermal;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "could not get IRQ\n");
+		ret = irq;
+		goto err;
+	}
+	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+					brcmstb_tmon_irq_thread, IRQF_ONESHOT,
+					DRV_NAME, priv);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "could not request IRQ: %d\n", ret);
+		goto err;
+	}
+
+	dev_info(&pdev->dev, "registered AVS TMON of-sensor driver\n");
+
+	return 0;
+
+err:
+	thermal_zone_of_sensor_unregister(&pdev->dev, priv->thermal);
+	return ret;
+}
+
+static int brcmstb_thermal_exit(struct platform_device *pdev)
+{
+	struct brcmstb_thermal_priv *priv = platform_get_drvdata(pdev);
+	struct thermal_zone_device *thermal = priv->thermal;
+
+	if (thermal) {
+		if (priv->regtype == AVS_TMON_ZONE_DRIVER)
+			thermal_zone_device_unregister(thermal);
+		else
+			thermal_zone_of_sensor_unregister(&pdev->dev,
+							  priv->thermal);
+	}
+
+	return 0;
+}
+
+static struct platform_driver brcmstb_thermal_driver = {
+	.probe = brcmstb_thermal_probe,
+	.remove = brcmstb_thermal_exit,
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = brcmstb_thermal_id_table,
+	},
+};
+module_platform_driver(brcmstb_thermal_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Brian Norris");
+MODULE_DESCRIPTION("Broadcom STB AVS TMON thermal driver");
diff --git a/drivers/thermal/fair_share.c b/drivers/thermal/fair_share.c
index 944ba2f340c8..6e0a3fbfae86 100644
--- a/drivers/thermal/fair_share.c
+++ b/drivers/thermal/fair_share.c
@@ -23,6 +23,7 @@
  */
 
 #include <linux/thermal.h>
+#include <trace/events/thermal.h>
 
 #include "thermal_core.h"
 
@@ -34,6 +35,7 @@ static int get_trip_level(struct thermal_zone_device *tz)
 {
 	int count = 0;
 	unsigned long trip_temp;
+	enum thermal_trip_type trip_type;
 
 	if (tz->trips == 0 || !tz->ops->get_trip_temp)
 		return 0;
@@ -43,6 +45,16 @@ static int get_trip_level(struct thermal_zone_device *tz)
 		if (tz->temperature < trip_temp)
 			break;
 	}
+
+	/*
+	 * count > 0 only if temperature is greater than first trip
+	 * point, in which case, trip_point = count - 1
+	 */
+	if (count > 0) {
+		tz->ops->get_trip_type(tz, count - 1, &trip_type);
+		trace_thermal_zone_trip(tz, count - 1, trip_type);
+	}
+
 	return count;
 }
 
diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c
index 6e75177915fa..ecb7d232e253 100644
--- a/drivers/thermal/intel_powerclamp.c
+++ b/drivers/thermal/intel_powerclamp.c
@@ -52,12 +52,18 @@
 #include <linux/seq_file.h>
 #include <linux/sched/rt.h>
 
+#include <asm/hardirq.h>
+#ifdef CONFIG_X86
 #include <asm/nmi.h>
 #include <asm/msr.h>
 #include <asm/mwait.h>
 #include <asm/cpu_device_id.h>
 #include <asm/idle.h>
-#include <asm/hardirq.h>
+
+static unsigned int target_mwait;
+#elif CONFIG_ARM
+#include <asm/proc-fns.h>
+#endif
 
 #define MAX_TARGET_RATIO (50U)
 /* For each undisturbed clamping period (no extra wake ups during idle time),
@@ -71,7 +77,6 @@
  */
 #define DEFAULT_DURATION_JIFFIES (6)
 
-static unsigned int target_mwait;
 static struct dentry *debug_dir;
 
 /* user selected target */
@@ -178,6 +183,7 @@ MODULE_PARM_DESC(window_size, "sliding window in number of clamping cycles\n"
 	"\twindow size results in slower response time but more smooth\n"
 	"\tclamping results. default to 2.");
 
+#ifdef CONFIG_X86
 static void find_target_mwait(void)
 {
 	unsigned int eax, ebx, ecx, edx;
@@ -255,6 +261,7 @@ static u64 pkg_state_counter(void)
 
 	return count;
 }
+#endif
 
 static void noop_timer(unsigned long foo)
 {
@@ -325,6 +332,28 @@ static void adjust_compensation(int target_ratio, unsigned int win)
 	}
 }
 
+#ifdef CONFIG_X86
+static void inline powerclamp_get_cstate_inform(u64 *msr_now, u64 *tsc_now)
+{
+	*msr_now = pkg_state_counter();
+	rdtscll(*tsc_now);
+}
+#elif CONFIG_ARM
+static void inline powerclamp_get_cstate_inform(u64 *idle, u64 *wall)
+{
+	u64 _wall;
+	int cpu;
+
+	*idle = 0;
+	*wall = 0;
+
+	for_each_online_cpu(cpu) {
+		*idle += get_cpu_idle_time_us(cpu, &_wall);
+		*wall += _wall;
+	}
+}
+#endif
+
 static bool powerclamp_adjust_controls(unsigned int target_ratio,
 				unsigned int guard, unsigned int win)
 {
@@ -333,8 +362,7 @@ static bool powerclamp_adjust_controls(unsigned int target_ratio,
 	u64 val64;
 
 	/* check result for the last window */
-	msr_now = pkg_state_counter();
-	rdtscll(tsc_now);
+	powerclamp_get_cstate_inform(&msr_now, &tsc_now);
 
 	/* calculate pkg cstate vs tsc ratio */
 	if (!msr_last || !tsc_last)
@@ -362,6 +390,32 @@ static bool powerclamp_adjust_controls(unsigned int target_ratio,
 	return set_target_ratio + guard <= current_ratio;
 }
 
+#ifdef CONFIG_X86
+static void powerclamp_enter_idle(void)
+{
+	unsigned long ecx = 1;
+	unsigned long eax = target_mwait;
+
+	/*
+	 * REVISIT: may call enter_idle() to notify drivers who
+	 * can save power during cpu idle. same for exit_idle()
+	 */
+	local_touch_nmi();
+	stop_critical_timings();
+	mwait_idle_with_hints(eax, ecx);
+	start_critical_timings();
+	atomic_inc(&idle_wakeup_counter);
+}
+#elif CONFIG_ARM
+static void  powerclamp_enter_idle(void)
+{
+	stop_critical_timings();
+	cpu_do_idle();
+	start_critical_timings();
+	atomic_inc(&idle_wakeup_counter);
+}
+#endif
+
 static int clamp_thread(void *arg)
 {
 	int cpunr = (unsigned long)arg;
@@ -436,20 +490,8 @@ static int clamp_thread(void *arg)
 		 */
 		preempt_disable();
 		/* mwait until target jiffies is reached */
-		while (time_before(jiffies, target_jiffies)) {
-			unsigned long ecx = 1;
-			unsigned long eax = target_mwait;
-
-			/*
-			 * REVISIT: may call enter_idle() to notify drivers who
-			 * can save power during cpu idle. same for exit_idle()
-			 */
-			local_touch_nmi();
-			stop_critical_timings();
-			mwait_idle_with_hints(eax, ecx);
-			start_critical_timings();
-			atomic_inc(&idle_wakeup_counter);
-		}
+		while (time_before(jiffies, target_jiffies))
+			powerclamp_enter_idle();
 		preempt_enable();
 	}
 	del_timer_sync(&wakeup_timer);
@@ -470,13 +512,12 @@ static void poll_pkg_cstate(struct work_struct *dummy)
 	static u64 tsc_last;
 	static unsigned long jiffies_last;
 
-	u64 msr_now;
+	u64 msr_now = 0;
 	unsigned long jiffies_now;
-	u64 tsc_now;
+	u64 tsc_now = 0;
 	u64 val64;
 
-	msr_now = pkg_state_counter();
-	rdtscll(tsc_now);
+	powerclamp_get_cstate_inform(&msr_now, &tsc_now);
 	jiffies_now = jiffies;
 
 	/* calculate pkg cstate vs tsc ratio */
@@ -504,11 +545,13 @@ static int start_power_clamp(void)
 	unsigned long cpu;
 	struct task_struct *thread;
 
+#ifdef CONFIG_X86
 	/* check if pkg cstate counter is completely 0, abort in this case */
 	if (!has_pkg_state_counter()) {
 		pr_err("pkg cstate counter not functional, abort\n");
 		return -EINVAL;
 	}
+#endif
 
 	set_target_ratio = clamp(set_target_ratio, 0U, MAX_TARGET_RATIO - 1);
 	/* prevent cpu hotplug */
@@ -666,6 +709,7 @@ static struct thermal_cooling_device_ops powerclamp_cooling_ops = {
 	.set_cur_state = powerclamp_set_cur_state,
 };
 
+#ifdef CONFIG_X86
 /* runs on Nehalem and later */
 static const struct x86_cpu_id intel_powerclamp_ids[] = {
 	{ X86_VENDOR_INTEL, 6, 0x1a},
@@ -688,9 +732,11 @@ static const struct x86_cpu_id intel_powerclamp_ids[] = {
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_powerclamp_ids);
+#endif
 
 static int powerclamp_probe(void)
 {
+#ifdef CONFIG_X86
 	if (!x86_match_cpu(intel_powerclamp_ids)) {
 		pr_err("Intel powerclamp does not run on family %d model %d\n",
 				boot_cpu_data.x86, boot_cpu_data.x86_model);
@@ -704,7 +750,7 @@ static int powerclamp_probe(void)
 
 	/* find the deepest mwait value */
 	find_target_mwait();
-
+#endif
 	return 0;
 }
 
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
index 04b1be7fa018..50a9599080e9 100644
--- a/drivers/thermal/of-thermal.c
+++ b/drivers/thermal/of-thermal.c
@@ -30,27 +30,13 @@
 #include <linux/err.h>
 #include <linux/export.h>
 #include <linux/string.h>
+#include <linux/thermal.h>
 
 #include "thermal_core.h"
 
 /***   Private data structures to represent thermal device tree data ***/
 
 /**
- * struct __thermal_trip - representation of a point in temperature domain
- * @np: pointer to struct device_node that this trip point was created from
- * @temperature: temperature value in miliCelsius
- * @hysteresis: relative hysteresis in miliCelsius
- * @type: trip point type
- */
-
-struct __thermal_trip {
-	struct device_node *np;
-	unsigned long int temperature;
-	unsigned long int hysteresis;
-	enum thermal_trip_type type;
-};
-
-/**
  * struct __thermal_bind_param - a match between trip and cooling device
  * @cooling_device: a pointer to identify the referred cooling device
  * @trip_id: the trip point index
@@ -77,8 +63,7 @@ struct __thermal_bind_params {
  * @num_tbps: number of thermal bind params
  * @tbps: an array of thermal bind params (0..num_tbps - 1)
  * @sensor_data: sensor private data used while reading temperature and trend
- * @get_temp: sensor callback to read temperature
- * @get_trend: sensor callback to read temperature trend
+ * @ops: set of callbacks to handle the thermal zone based on DT
  */
 
 struct __thermal_zone {
@@ -88,7 +73,7 @@ struct __thermal_zone {
 
 	/* trip data */
 	int ntrips;
-	struct __thermal_trip *trips;
+	struct thermal_trip *trips;
 
 	/* cooling binding data */
 	int num_tbps;
@@ -96,8 +81,7 @@ struct __thermal_zone {
 
 	/* sensor interface */
 	void *sensor_data;
-	int (*get_temp)(void *, long *);
-	int (*get_trend)(void *, long *);
+	const struct thermal_zone_of_device_ops *ops;
 };
 
 /***   DT thermal zone device callbacks   ***/
@@ -107,34 +91,122 @@ static int of_thermal_get_temp(struct thermal_zone_device *tz,
 {
 	struct __thermal_zone *data = tz->devdata;
 
-	if (!data->get_temp)
+	if (!data->ops)
 		return -EINVAL;
 
-	return data->get_temp(data->sensor_data, temp);
+	return data->ops->get_temp(data->sensor_data, temp);
+}
+
+static int of_thermal_set_trips(struct thermal_zone_device *tz,
+			       unsigned long low, unsigned long high)
+{
+	struct __thermal_zone *data = tz->devdata;
+
+	if (!data->ops || !data->ops->set_trips)
+		return -ENOSYS;
+
+	return data->ops->set_trips(data->sensor_data, low, high);
+}
+
+/**
+ * of_thermal_get_ntrips - function to export number of available trip
+ *			   points.
+ * @tz: pointer to a thermal zone
+ *
+ * This function is a globally visible wrapper to get number of trip points
+ * stored in the local struct __thermal_zone
+ *
+ * Return: number of available trip points, -ENODEV when data not available
+ */
+int of_thermal_get_ntrips(struct thermal_zone_device *tz)
+{
+	struct __thermal_zone *data = tz->devdata;
+
+	if (!data || IS_ERR(data))
+		return -ENODEV;
+
+	return data->ntrips;
+}
+EXPORT_SYMBOL_GPL(of_thermal_get_ntrips);
+
+/**
+ * of_thermal_is_trip_valid - function to check if trip point is valid
+ *
+ * @tz:	pointer to a thermal zone
+ * @trip:	trip point to evaluate
+ *
+ * This function is responsible for checking if passed trip point is valid
+ *
+ * Return: true if trip point is valid, false otherwise
+ */
+bool of_thermal_is_trip_valid(struct thermal_zone_device *tz, int trip)
+{
+	struct __thermal_zone *data = tz->devdata;
+
+	if (!data || trip >= data->ntrips || trip < 0)
+		return false;
+
+	return true;
+}
+EXPORT_SYMBOL_GPL(of_thermal_is_trip_valid);
+
+/**
+ * of_thermal_get_trip_points - function to get access to a globally exported
+ *				trip points
+ *
+ * @tz:	pointer to a thermal zone
+ *
+ * This function provides a pointer to trip points table
+ *
+ * Return: pointer to trip points table, NULL otherwise
+ */
+const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *tz)
+{
+	struct __thermal_zone *data = tz->devdata;
+
+	if (!data)
+		return NULL;
+
+	return data->trips;
+}
+EXPORT_SYMBOL_GPL(of_thermal_get_trip_points);
+
+/**
+ * of_thermal_set_emul_temp - function to set emulated temperature
+ *
+ * @tz:	pointer to a thermal zone
+ * @temp:	temperature to set
+ *
+ * This function gives the ability to set emulated value of temperature,
+ * which is handy for debugging
+ *
+ * Return: zero on success, error code otherwise
+ */
+static int of_thermal_set_emul_temp(struct thermal_zone_device *tz,
+				    unsigned long temp)
+{
+	struct __thermal_zone *data = tz->devdata;
+
+	if (!data->ops || !data->ops->set_emul_temp)
+		return -ENOSYS;
+
+	return data->ops->set_emul_temp(data->sensor_data, temp);
 }
 
 static int of_thermal_get_trend(struct thermal_zone_device *tz, int trip,
 				enum thermal_trend *trend)
 {
 	struct __thermal_zone *data = tz->devdata;
-	long dev_trend;
 	int r;
 
-	if (!data->get_trend)
-		return -EINVAL;
+	if (!data->ops || !data->ops->get_trend)
+		return -ENOSYS;
 
-	r = data->get_trend(data->sensor_data, &dev_trend);
+	r = data->ops->get_trend(data->sensor_data, trip, trend);
 	if (r)
 		return r;
 
-	/* TODO: These intervals might have some thresholds, but in core code */
-	if (dev_trend > 0)
-		*trend = THERMAL_TREND_RAISING;
-	else if (dev_trend < 0)
-		*trend = THERMAL_TREND_DROPPING;
-	else
-		*trend = THERMAL_TREND_STABLE;
-
 	return 0;
 }
 
@@ -156,8 +228,8 @@ static int of_thermal_bind(struct thermal_zone_device *thermal,
 
 			ret = thermal_zone_bind_cooling_device(thermal,
 						tbp->trip_id, cdev,
-						tbp->min,
-						tbp->max);
+						tbp->max,
+						tbp->min);
 			if (ret)
 				return ret;
 		}
@@ -304,7 +376,12 @@ static int of_thermal_get_crit_temp(struct thermal_zone_device *tz,
 	return -EINVAL;
 }
 
-static struct thermal_zone_device_ops of_thermal_ops = {
+static const struct thermal_zone_device_ops of_thermal_ops = {
+	.get_temp = of_thermal_get_temp,
+	.set_trips = of_thermal_set_trips,
+	.get_trend = of_thermal_get_trend,
+	.set_emul_temp = of_thermal_set_emul_temp,
+
 	.get_mode = of_thermal_get_mode,
 	.set_mode = of_thermal_set_mode,
 
@@ -324,8 +401,7 @@ static struct thermal_zone_device_ops of_thermal_ops = {
 static struct thermal_zone_device *
 thermal_zone_of_add_sensor(struct device_node *zone,
 			   struct device_node *sensor, void *data,
-			   int (*get_temp)(void *, long *),
-			   int (*get_trend)(void *, long *))
+			   const struct thermal_zone_of_device_ops *ops)
 {
 	struct thermal_zone_device *tzd;
 	struct __thermal_zone *tz;
@@ -336,13 +412,16 @@ thermal_zone_of_add_sensor(struct device_node *zone,
 
 	tz = tzd->devdata;
 
+	if (!ops)
+		return ERR_PTR(-EINVAL);
+
+	if (!ops->get_temp)
+		return ERR_PTR(-EINVAL);
+
 	mutex_lock(&tzd->lock);
-	tz->get_temp = get_temp;
-	tz->get_trend = get_trend;
+	tz->ops = ops;
 	tz->sensor_data = data;
 
-	tzd->ops->get_temp = of_thermal_get_temp;
-	tzd->ops->get_trend = of_thermal_get_trend;
 	mutex_unlock(&tzd->lock);
 
 	return tzd;
@@ -356,8 +435,7 @@ thermal_zone_of_add_sensor(struct device_node *zone,
  *             than one sensors
  * @data: a private pointer (owned by the caller) that will be passed
  *        back, when a temperature reading is needed.
- * @get_temp: a pointer to a function that reads the sensor temperature.
- * @get_trend: a pointer to a function that reads the sensor temperature trend.
+ * @ops: struct thermal_zone_of_device_ops *. Must contain at least .get_temp.
  *
  * This function will search the list of thermal zones described in device
  * tree and look for the zone that refer to the sensor device pointed by
@@ -382,25 +460,31 @@ thermal_zone_of_add_sensor(struct device_node *zone,
  * check the return value with help of IS_ERR() helper.
  */
 struct thermal_zone_device *
-thermal_zone_of_sensor_register(struct device *dev, int sensor_id,
-				void *data, int (*get_temp)(void *, long *),
-				int (*get_trend)(void *, long *))
+thermal_zone_of_sensor_register(struct device *dev, int sensor_id, void *data,
+				const struct thermal_zone_of_device_ops *ops)
 {
 	struct device_node *np, *child, *sensor_np;
+	struct thermal_zone_device *tzd = ERR_PTR(-ENODEV);
 
 	np = of_find_node_by_name(NULL, "thermal-zones");
 	if (!np)
 		return ERR_PTR(-ENODEV);
 
-	if (!dev || !dev->of_node)
+	if (!dev || !dev->of_node) {
+		of_node_put(np);
 		return ERR_PTR(-EINVAL);
+	}
 
-	sensor_np = dev->of_node;
+	sensor_np = of_node_get(dev->of_node);
 
 	for_each_child_of_node(np, child) {
 		struct of_phandle_args sensor_specs;
 		int ret, id;
 
+		/* Check whether child is enabled or not */
+		if (!of_device_is_available(child))
+			continue;
+
 		/* For now, thermal framework supports only 1 sensor per zone */
 		ret = of_parse_phandle_with_args(child, "thermal-sensors",
 						 "#thermal-sensor-cells",
@@ -418,16 +502,22 @@ thermal_zone_of_sensor_register(struct device *dev, int sensor_id,
 		}
 
 		if (sensor_specs.np == sensor_np && id == sensor_id) {
-			of_node_put(np);
-			return thermal_zone_of_add_sensor(child, sensor_np,
-							  data,
-							  get_temp,
-							  get_trend);
+			tzd = thermal_zone_of_add_sensor(child, sensor_np,
+							 data, ops);
+			if (!IS_ERR(tzd))
+				tzd->ops->set_mode(tzd, THERMAL_DEVICE_ENABLED);
+
+			of_node_put(sensor_specs.np);
+			of_node_put(child);
+			goto exit;
 		}
+		of_node_put(sensor_specs.np);
 	}
+exit:
+	of_node_put(sensor_np);
 	of_node_put(np);
 
-	return ERR_PTR(-ENODEV);
+	return tzd;
 }
 EXPORT_SYMBOL_GPL(thermal_zone_of_sensor_register);
 
@@ -461,11 +551,7 @@ void thermal_zone_of_sensor_unregister(struct device *dev,
 		return;
 
 	mutex_lock(&tzd->lock);
-	tzd->ops->get_temp = NULL;
-	tzd->ops->get_trend = NULL;
-
-	tz->get_temp = NULL;
-	tz->get_trend = NULL;
+	tz->ops = NULL;
 	tz->sensor_data = NULL;
 	mutex_unlock(&tzd->lock);
 }
@@ -489,7 +575,7 @@ EXPORT_SYMBOL_GPL(thermal_zone_of_sensor_unregister);
  */
 static int thermal_of_populate_bind_params(struct device_node *np,
 					   struct __thermal_bind_params *__tbp,
-					   struct __thermal_trip *trips,
+					   struct thermal_trip *trips,
 					   int ntrips)
 {
 	struct of_phandle_args cooling_spec;
@@ -592,7 +678,7 @@ static int thermal_of_get_trip_type(struct device_node *np,
  * Return: 0 on success, proper error code otherwise
  */
 static int thermal_of_populate_trip(struct device_node *np,
-				    struct __thermal_trip *trip)
+				    struct thermal_trip *trip)
 {
 	int prop;
 	int ret;
@@ -619,6 +705,7 @@ static int thermal_of_populate_trip(struct device_node *np,
 
 	/* Required for cooling map matching */
 	trip->np = np;
+	of_node_get(np);
 
 	return 0;
 }
@@ -712,11 +799,12 @@ thermal_of_build_thermal_zone(struct device_node *np)
 	}
 
 	i = 0;
-	for_each_child_of_node(child, gchild)
+	for_each_child_of_node(child, gchild) {
 		ret = thermal_of_populate_bind_params(gchild, &tz->tbps[i++],
 						      tz->trips, tz->ntrips);
 		if (ret)
 			goto free_tbps;
+	}
 
 finish:
 	of_node_put(child);
@@ -725,9 +813,14 @@ finish:
 	return tz;
 
 free_tbps:
+	for (i = 0; i < tz->num_tbps; i++)
+		of_node_put(tz->tbps[i].cooling_device);
 	kfree(tz->tbps);
 free_trips:
+	for (i = 0; i < tz->ntrips; i++)
+		of_node_put(tz->trips[i].np);
 	kfree(tz->trips);
+	of_node_put(gchild);
 free_tz:
 	kfree(tz);
 	of_node_put(child);
@@ -737,7 +830,13 @@ free_tz:
 
 static inline void of_thermal_free_zone(struct __thermal_zone *tz)
 {
+	int i;
+
+	for (i = 0; i < tz->num_tbps; i++)
+		of_node_put(tz->tbps[i].cooling_device);
 	kfree(tz->tbps);
+	for (i = 0; i < tz->ntrips; i++)
+		of_node_put(tz->trips[i].np);
 	kfree(tz->trips);
 	kfree(tz);
 }
@@ -758,7 +857,6 @@ int __init of_parse_thermal_zones(void)
 {
 	struct device_node *np, *child;
 	struct __thermal_zone *tz;
-	struct thermal_zone_device_ops *ops;
 
 	np = of_find_node_by_name(NULL, "thermal-zones");
 	if (!np) {
@@ -770,6 +868,10 @@ int __init of_parse_thermal_zones(void)
 		struct thermal_zone_device *zone;
 		struct thermal_zone_params *tzp;
 
+		/* Check whether child is enabled or not */
+		if (!of_device_is_available(child))
+			continue;
+
 		tz = thermal_of_build_thermal_zone(child);
 		if (IS_ERR(tz)) {
 			pr_err("failed to build thermal zone %s: %ld\n",
@@ -778,37 +880,33 @@ int __init of_parse_thermal_zones(void)
 			continue;
 		}
 
-		ops = kmemdup(&of_thermal_ops, sizeof(*ops), GFP_KERNEL);
-		if (!ops)
-			goto exit_free;
-
 		tzp = kzalloc(sizeof(*tzp), GFP_KERNEL);
-		if (!tzp) {
-			kfree(ops);
+		if (!tzp)
 			goto exit_free;
-		}
 
 		/* No hwmon because there might be hwmon drivers registering */
 		tzp->no_hwmon = true;
 
 		zone = thermal_zone_device_register(child->name, tz->ntrips,
 						    0, tz,
-						    ops, tzp,
+						    &of_thermal_ops, tzp,
 						    tz->passive_delay,
 						    tz->polling_delay);
 		if (IS_ERR(zone)) {
 			pr_err("Failed to build %s zone %ld\n", child->name,
 			       PTR_ERR(zone));
 			kfree(tzp);
-			kfree(ops);
 			of_thermal_free_zone(tz);
 			/* attempting to build remaining zones still */
 		}
 	}
+	of_node_put(np);
 
 	return 0;
 
 exit_free:
+	of_node_put(child);
+	of_node_put(np);
 	of_thermal_free_zone(tz);
 
 	/* no memory available, so free what we have built */
@@ -837,6 +935,10 @@ void of_thermal_destroy_zones(void)
 	for_each_child_of_node(np, child) {
 		struct thermal_zone_device *zone;
 
+		/* Check whether child is enabled or not */
+		if (!of_device_is_available(child))
+			continue;
+
 		zone = thermal_zone_get_zone_by_name(child->name);
 		if (IS_ERR(zone))
 			continue;
@@ -846,4 +948,5 @@ void of_thermal_destroy_zones(void)
 		kfree(zone->ops);
 		of_thermal_free_zone(zone->devdata);
 	}
+	of_node_put(np);
 }
diff --git a/drivers/thermal/step_wise.c b/drivers/thermal/step_wise.c
index c501eba601da..698896226254 100644
--- a/drivers/thermal/step_wise.c
+++ b/drivers/thermal/step_wise.c
@@ -23,6 +23,7 @@
  */
 
 #include <linux/thermal.h>
+#include <trace/events/thermal.h>
 
 #include "thermal_core.h"
 
@@ -129,8 +130,10 @@ static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip)
 
 	trend = get_tz_trend(tz, trip);
 
-	if (tz->temperature >= trip_temp)
+	if (tz->temperature >= trip_temp) {
 		throttle = true;
+		trace_thermal_zone_trip(tz, trip, trip_type);
+	}
 
 	dev_dbg(&tz->device, "Trip%d[type=%d,temp=%ld]:trend=%d,throttle=%d\n",
 				trip, trip_type, trip_temp, trend, throttle);
diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
index 284733e1fb6f..4c8fdfc8d938 100644
--- a/drivers/thermal/thermal_core.c
+++ b/drivers/thermal/thermal_core.c
@@ -38,6 +38,9 @@
 #include <net/netlink.h>
 #include <net/genetlink.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/thermal.h>
+
 #include "thermal_core.h"
 #include "thermal_hwmon.h"
 
@@ -365,9 +368,11 @@ static void handle_critical_trips(struct thermal_zone_device *tz,
 	tz->ops->get_trip_temp(tz, trip, &trip_temp);
 
 	/* If we have not crossed the trip_temp, we do not care. */
-	if (tz->temperature < trip_temp)
+	if (trip_temp <= 0 || tz->temperature < trip_temp)
 		return;
 
+	trace_thermal_zone_trip(tz, trip, trip_type);
+
 	if (tz->ops->notify)
 		tz->ops->notify(tz, trip, trip_type);
 
@@ -408,76 +413,139 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip)
  */
 int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
 {
-	int ret = -EINVAL;
-#ifdef CONFIG_THERMAL_EMULATION
-	int count;
-	unsigned long crit_temp = -1UL;
-	enum thermal_trip_type type;
-#endif
+	int ret;
 
-	if (!tz || IS_ERR(tz) || !tz->ops->get_temp)
-		goto exit;
+	if (!tz || IS_ERR(tz))
+		return -EINVAL;
+
+	if (!tz->ops->get_temp)
+		return -ENOSYS;
 
 	mutex_lock(&tz->lock);
 
 	ret = tz->ops->get_temp(tz, temp);
-#ifdef CONFIG_THERMAL_EMULATION
-	if (!tz->emul_temperature)
-		goto skip_emul;
-
-	for (count = 0; count < tz->trips; count++) {
-		ret = tz->ops->get_trip_type(tz, count, &type);
-		if (!ret && type == THERMAL_TRIP_CRITICAL) {
-			ret = tz->ops->get_trip_temp(tz, count, &crit_temp);
-			break;
-		}
-	}
 
-	if (ret)
-		goto skip_emul;
-
-	if (*temp < crit_temp)
+	if (IS_ENABLED(CONFIG_THERMAL_EMULATION) && tz->emul_temperature)
 		*temp = tz->emul_temperature;
-skip_emul:
-#endif
+
 	mutex_unlock(&tz->lock);
-exit:
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(thermal_zone_get_temp);
 
-static void update_temperature(struct thermal_zone_device *tz)
+/*
+ * If not implemented, return -ENOSYS
+ * Otherwise:
+ *   Return trip point number (>= 0) if triggered
+ *   Return invalid trip number (tz->trips) if not triggered
+ */
+static int thermal_zone_set_trips(struct thermal_zone_device *tz)
 {
-	long temp;
-	int ret;
+	unsigned long low = 0;
+	unsigned long high = ULONG_MAX;
+	unsigned long trip_temp, hysteresis;
+	unsigned long temp = tz->temperature;
+	unsigned long last = tz->last_temperature;
+	unsigned long notify_temp = 0; /* minimum */
+	int notify_trip = tz->trips; /* maximum */
+	int i;
 
-	ret = thermal_zone_get_temp(tz, &temp);
-	if (ret) {
-		dev_warn(&tz->device, "failed to read out thermal zone %d\n",
-			 tz->id);
-		return;
+	if (!tz->ops->set_trips)
+		return -ENOSYS;
+
+	/* No need to change trip points */
+	if (temp > tz->prev_low_trip && temp < tz->prev_high_trip)
+		return notify_trip;
+
+	for (i = 0; i < tz->trips; i++) {
+		unsigned long trip_low;
+
+		tz->ops->get_trip_temp(tz, i, &trip_temp);
+		tz->ops->get_trip_hyst(tz, i, &hysteresis);
+
+		trip_low = trip_temp - hysteresis;
+
+		if (trip_low < temp && trip_low > low)
+			low = trip_low;
+
+		if (trip_temp > temp && trip_temp < high)
+			high = trip_temp;
+
+		/* Report only when traversing a trip point */
+		if (trip_low > notify_temp && last > trip_low
+					   && trip_low > temp) {
+			notify_trip = i;
+			notify_temp = trip_low;
+		} else if (trip_temp > notify_temp && last < trip_temp
+						   && trip_temp < temp) {
+			notify_trip = i;
+			notify_temp = trip_temp;
+		}
 	}
 
+	tz->prev_low_trip = low;
+	tz->prev_high_trip = high;
+
+	dev_dbg(&tz->device, "new temperature boundaries: %lu < x < %lu\n",
+			low, high);
+
+	tz->ops->set_trips(tz, low, high);
+
+	return notify_trip;
+}
+
+/*
+ * Equivalent to thermal_zone_device_update(), except that the notifier can
+ * provide the temperature directly. This is useful in case the update is
+ * driven by a hardware interrupt, and we don't want to risk a race between the
+ * notification and the next temperature reading.
+ */
+void thermal_zone_device_update_temp(struct thermal_zone_device *tz,
+				     long temp)
+{
+	int count, trip;
+
 	mutex_lock(&tz->lock);
 	tz->last_temperature = tz->temperature;
 	tz->temperature = temp;
 	mutex_unlock(&tz->lock);
 
+	trace_thermal_temperature(tz);
 	dev_dbg(&tz->device, "last_temperature=%d, current_temperature=%d\n",
 				tz->last_temperature, tz->temperature);
+
+	trip = thermal_zone_set_trips(tz);
+
+	if (trip < 0) {
+		/* Update isn't targeting a particular trip */
+		for (count = 0; count < tz->trips; count++)
+			handle_thermal_trip(tz, count);
+	} else if (trip < tz->trips) {
+		handle_thermal_trip(tz, trip);
+	} else {
+		dev_dbg(&tz->device, "update didn't target any trip point\n");
+	}
 }
+EXPORT_SYMBOL_GPL(thermal_zone_device_update_temp);
 
 void thermal_zone_device_update(struct thermal_zone_device *tz)
 {
-	int count;
+	long temp;
+	int ret;
 
-	if (!tz->ops->get_temp)
+	ret = thermal_zone_get_temp(tz, &temp);
+
+	if (ret == -ENOSYS)
 		return;
 
-	update_temperature(tz);
+	if (ret) {
+		dev_warn(&tz->device, "failed to read out thermal zone %d\n",
+			 tz->id);
+		return;
+	}
 
-	for (count = 0; count < tz->trips; count++)
-		handle_thermal_trip(tz, count);
+	thermal_zone_device_update_temp(tz, temp);
 }
 EXPORT_SYMBOL_GPL(thermal_zone_device_update);
 
@@ -751,6 +819,7 @@ policy_store(struct device *dev, struct device_attribute *attr,
 	snprintf(name, sizeof(name), "%s", buf);
 
 	mutex_lock(&thermal_governor_lock);
+	mutex_lock(&tz->lock);
 
 	gov = __find_governor(strim(name));
 	if (!gov)
@@ -760,6 +829,7 @@ policy_store(struct device *dev, struct device_attribute *attr,
 	ret = count;
 
 exit:
+	mutex_unlock(&tz->lock);
 	mutex_unlock(&thermal_governor_lock);
 	return ret;
 }
@@ -780,16 +850,42 @@ emul_temp_store(struct device *dev, struct device_attribute *attr,
 	struct thermal_zone_device *tz = to_thermal_zone(dev);
 	int ret = 0;
 	unsigned long temperature;
+	int trip;
+	unsigned long crit_temp;
+	enum thermal_trip_type type;
 
 	if (kstrtoul(buf, 10, &temperature))
 		return -EINVAL;
 
-	if (!tz->ops->set_emul_temp) {
+	for (trip = 0; trip < tz->trips; trip++) {
+		ret = tz->ops->get_trip_type(tz, trip, &type);
+		if (ret)
+			return ret;
+
+		if (type != THERMAL_TRIP_CRITICAL)
+			continue;
+
+		ret = tz->ops->get_trip_temp(tz, trip, &crit_temp);
+		if (ret)
+			return ret;
+
+		if (temperature >= crit_temp) {
+			dev_err(&tz->device, "Will not emulate critical temperature %luC (tcrit=%luC)\n",
+					temperature / 1000, crit_temp / 1000);
+			return -EINVAL;
+		}
+	}
+
+	if (tz->ops->set_emul_temp)
+		ret = tz->ops->set_emul_temp(tz, temperature);
+	else
+		ret = -ENOSYS;
+
+	if (ret == -ENOSYS) {
 		mutex_lock(&tz->lock);
 		tz->emul_temperature = temperature;
 		mutex_unlock(&tz->lock);
-	} else {
-		ret = tz->ops->set_emul_temp(tz, temperature);
+		ret = 0;
 	}
 
 	if (!ret)
@@ -922,7 +1018,7 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz,
 	struct thermal_zone_device *pos1;
 	struct thermal_cooling_device *pos2;
 	unsigned long max_state;
-	int result;
+	int result, ret;
 
 	if (trip >= tz->trips || (trip < 0 && trip != THERMAL_TRIPS_NONE))
 		return -EINVAL;
@@ -939,7 +1035,9 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz,
 	if (tz != pos1 || cdev != pos2)
 		return -EINVAL;
 
-	cdev->ops->get_max_state(cdev, &max_state);
+	ret = cdev->ops->get_max_state(cdev, &max_state);
+	if (ret)
+		return ret;
 
 	/* lower default 0, upper default max_state */
 	lower = lower == THERMAL_NO_LIMIT ? 0 : lower;
@@ -1287,6 +1385,7 @@ void thermal_cdev_update(struct thermal_cooling_device *cdev)
 	mutex_unlock(&cdev->lock);
 	cdev->ops->set_cur_state(cdev, target);
 	cdev->updated = true;
+	trace_cdev_update(cdev, target);
 	dev_dbg(&cdev->device, "set to state %lu\n", target);
 }
 EXPORT_SYMBOL(thermal_cdev_update);
@@ -1443,7 +1542,7 @@ static void remove_trip_attrs(struct thermal_zone_device *tz)
  */
 struct thermal_zone_device *thermal_zone_device_register(const char *type,
 	int trips, int mask, void *devdata,
-	struct thermal_zone_device_ops *ops,
+	const struct thermal_zone_device_ops *ops,
 	const struct thermal_zone_params *tzp,
 	int passive_delay, int polling_delay)
 {
@@ -1563,13 +1662,9 @@ struct thermal_zone_device *thermal_zone_device_register(const char *type,
 
 	INIT_DELAYED_WORK(&(tz->poll_queue), thermal_zone_device_check);
 
-	if (!tz->ops->get_temp)
-		thermal_zone_device_set_polling(tz, 0);
-
 	thermal_zone_device_update(tz);
 
-	if (!result)
-		return tz;
+	return tz;
 
 unregister:
 	release_idr(&thermal_tz_idr, &thermal_idr_lock, tz->id);
diff --git a/drivers/thermal/thermal_core.h b/drivers/thermal/thermal_core.h
index 3db339fb636f..65f2fb45ca3b 100644
--- a/drivers/thermal/thermal_core.h
+++ b/drivers/thermal/thermal_core.h
@@ -81,9 +81,27 @@ static inline void thermal_gov_user_space_unregister(void) {}
 #ifdef CONFIG_THERMAL_OF
 int of_parse_thermal_zones(void);
 void of_thermal_destroy_zones(void);
+int of_thermal_get_ntrips(struct thermal_zone_device *);
+bool of_thermal_is_trip_valid(struct thermal_zone_device *, int);
+const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *);
 #else
 static inline int of_parse_thermal_zones(void) { return 0; }
 static inline void of_thermal_destroy_zones(void) { }
+static inline int of_thermal_get_ntrips(struct thermal_zone_device *tz)
+{
+	return 0;
+}
+static inline bool of_thermal_is_trip_valid(struct thermal_zone_device *tz,
+					    int trip)
+{
+	return 0;
+}
+static inline const struct thermal_trip * const
+of_thermal_get_trip_points(struct thermal_zone_device *tz)
+{
+	return NULL;
+}
 #endif
 
 #endif /* __THERMAL_CORE_H__ */
diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
index 9eec26dc0448..8a712b43e487 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
@@ -239,7 +239,7 @@ static int ti_thermal_get_trip_temp(struct thermal_zone_device *thermal,
 	return 0;
 }
 
-static int __ti_thermal_get_trend(void *p, long *trend)
+static int __ti_thermal_get_trend(void *p, int trip, enum thermal_trend *trend)
 {
 	struct ti_thermal_data *data = p;
 	struct ti_bandgap *bgp;
@@ -252,22 +252,6 @@ static int __ti_thermal_get_trend(void *p, long *trend)
 	if (ret)
 		return ret;
 
-	*trend = tr;
-
-	return 0;
-}
-
-/* Get the temperature trend callback functions for thermal zone */
-static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
-				int trip, enum thermal_trend *trend)
-{
-	int ret;
-	long tr;
-
-	ret = __ti_thermal_get_trend(thermal->devdata, &tr);
-	if (ret)
-		return ret;
-
 	if (tr > 0)
 		*trend = THERMAL_TREND_RAISING;
 	else if (tr < 0)
@@ -278,6 +262,13 @@ static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
 	return 0;
 }
 
+/* Get the temperature trend callback functions for thermal zone */
+static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
+				int trip, enum thermal_trend *trend)
+{
+	return __ti_thermal_get_trend(thermal->devdata, trip, trend);
+}
+
 /* Get critical temperature callback functions for thermal zone */
 static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal,
 				    unsigned long *temp)
@@ -286,6 +277,11 @@ static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal,
 	return ti_thermal_get_trip_temp(thermal, OMAP_TRIP_NUMBER - 1, temp);
 }
 
+static const struct thermal_zone_of_device_ops ti_of_thermal_ops = {
+	.get_temp = __ti_thermal_get_temp,
+	.get_trend = __ti_thermal_get_trend,
+};
+
 static struct thermal_zone_device_ops ti_thermal_ops = {
 	.get_temp = ti_thermal_get_temp,
 	.get_trend = ti_thermal_get_trend,
@@ -333,8 +329,7 @@ int ti_thermal_expose_sensor(struct ti_bandgap *bgp, int id,
 
 	/* in case this is specified by DT */
 	data->ti_thermal = thermal_zone_of_sensor_register(bgp->dev, id,
-					data, __ti_thermal_get_temp,
-					__ti_thermal_get_trend);
+					data, &ti_of_thermal_ops);
 	if (IS_ERR(data->ti_thermal)) {
 		/* Create thermal zone */
 		data->ti_thermal = thermal_zone_device_register(domain,
diff --git a/drivers/thermal/user_space.c b/drivers/thermal/user_space.c
index 10adcddc8821..61118d48db67 100644
--- a/drivers/thermal/user_space.c
+++ b/drivers/thermal/user_space.c
@@ -22,6 +22,8 @@
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
+#include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/thermal.h>
 
 #include "thermal_core.h"
@@ -34,10 +36,25 @@
  */
 static int notify_user_space(struct thermal_zone_device *tz, int trip)
 {
+	char *envp[] = { NULL, NULL, NULL };
+	int ret = 0;
+
+	envp[0] = kasprintf(GFP_KERNEL, "TRIPNUM=%u", trip);
+	envp[1] = kasprintf(GFP_KERNEL, "TEMPERATURE=%d", tz->temperature);
+	if (!envp[0] || !envp[1]) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
 	mutex_lock(&tz->lock);
-	kobject_uevent(&tz->device.kobj, KOBJ_CHANGE);
+	kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
 	mutex_unlock(&tz->lock);
-	return 0;
+
+out:
+	kfree(envp[0]);
+	kfree(envp[1]);
+
+	return ret;
 }
 
 static struct thermal_governor thermal_gov_user_space = {
diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index 1ebf8538b4fa..34c3cd1df480 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -110,6 +110,8 @@ static inline void serial_dl_write(struct uart_8250_port *up, int value)
 	up->dl_write(up, value);
 }
 
+struct uart_8250_port *serial8250_get_port(int line);
+
 #if defined(__alpha__) && !defined(CONFIG_PCI)
 /*
  * Digital did something really horribly wrong with the OUT1 and OUT2
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 9fffc7295af1..de301926093f 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -158,8 +158,13 @@ static const struct serial8250_config uart_config[] = {
 	},
 	[PORT_16550A] = {
 		.name		= "16550A",
+#ifdef CONFIG_BCM7439
+		.fifo_size	= 32,
+		.tx_loadsz	= 32,
+#else
 		.fifo_size	= 16,
 		.tx_loadsz	= 16,
+#endif
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 		.flags		= UART_CAP_FIFO,
 	},
@@ -1401,8 +1406,14 @@ serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
 			else if (lsr & UART_LSR_FE)
 				flag = TTY_FRAME;
 		}
-		if (uart_handle_sysrq_char(port, ch))
-			goto ignore_char;
+#ifdef CONFIG_DREAMBOX_DM9X0
+		/* this caused kernel oops on dm900 boot when the debug mini usb port is not powered */
+		if (serial_index(port) != 0 || (up->ier & (UART_IER_RLSI | UART_IER_RDI)) == (UART_IER_RLSI | UART_IER_RDI))
+#endif
+		{
+			if (uart_handle_sysrq_char(port, ch))
+				goto ignore_char;
+		}
 
 		uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
 
@@ -1422,6 +1433,31 @@ void serial8250_tx_chars(struct uart_8250_port *up)
 	struct circ_buf *xmit = &port->state->xmit;
 	int count;
 
+#ifdef CONFIG_DREAMBOX_DM9X0
+	if (serial_index(port) == 0 && (up->ier & (UART_IER_RLSI | UART_IER_RDI)) != (UART_IER_RLSI | UART_IER_RDI))
+	{
+		if (port->x_char) {
+			port->icount.tx++;
+			port->x_char = 0;
+			return;
+		}
+
+		if (uart_tx_stopped(port)) {
+			serial8250_stop_tx(port);
+			return;
+		}
+
+		while (!uart_circ_empty(xmit)) {
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx++;
+		}
+
+		__stop_tx(up);
+
+		return;
+	}
+#endif
+
 	if (port->x_char) {
 		serial_out(up, UART_TX, port->x_char);
 		port->icount.tx++;
@@ -1466,20 +1502,31 @@ unsigned int serial8250_modem_status(struct uart_8250_port *up)
 	struct uart_port *port = &up->port;
 	unsigned int status = serial_in(up, UART_MSR);
 
-	status |= up->msr_saved_flags;
-	up->msr_saved_flags = 0;
-	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
-	    port->state != NULL) {
-		if (status & UART_MSR_TERI)
-			port->icount.rng++;
-		if (status & UART_MSR_DDSR)
-			port->icount.dsr++;
-		if (status & UART_MSR_DDCD)
-			uart_handle_dcd_change(port, status & UART_MSR_DCD);
-		if (status & UART_MSR_DCTS)
-			uart_handle_cts_change(port, status & UART_MSR_CTS);
-
-		wake_up_interruptible(&port->state->port.delta_msr_wait);
+#ifdef CONFIG_DREAMBOX_DM9X0
+	if (serial_index(port) == 0) {
+		if (status & 1) {
+			up->ier = status & 0x10 ? (UART_IER_RLSI | UART_IER_RDI | UART_IER_MSI) : UART_IER_MSI;
+			serial_port_out(port, UART_IER, up->ier);
+		}
+	}
+	else
+#endif
+	{
+		status |= up->msr_saved_flags;
+		up->msr_saved_flags = 0;
+		if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
+		    port->state != NULL) {
+			if (status & UART_MSR_TERI)
+				port->icount.rng++;
+			if (status & UART_MSR_DDSR)
+				port->icount.dsr++;
+			if (status & UART_MSR_DDCD)
+				uart_handle_dcd_change(port, status & UART_MSR_DCD);
+			if (status & UART_MSR_DCTS)
+				uart_handle_cts_change(port, status & UART_MSR_CTS);
+
+			wake_up_interruptible(&port->state->port.delta_msr_wait);
+		}
 	}
 
 	return status;
@@ -1941,7 +1988,13 @@ static int serial8250_startup(struct uart_port *port)
 	unsigned long flags;
 	unsigned char lsr, iir;
 	int retval;
-
+#if defined(CONFIG_DREAMBOX_DM9X0) && !defined(CONFIG_SERIAL_8250_CONSOLE)
+	if (serial_index(port) == 0) {
+		volatile uint32_t *p = ioremap_nocache(0xf0404120, PAGE_SIZE);
+		*p |= 0x200;
+		iounmap(p);
+	}
+#endif
 	if (port->type == PORT_8250_CIR)
 		return -ENODEV;
 
@@ -2172,6 +2225,16 @@ dont_test_tx_en:
 	 * anyway, so we don't enable them here.
 	 */
 	up->ier = UART_IER_RLSI | UART_IER_RDI;
+
+#ifdef CONFIG_DREAMBOX_DM9X0
+	if (serial_index(port) == 0) {
+		if (serial_port_in(port, UART_MSR) & 0x10)
+			up->ier |= UART_IER_MSI;
+		else
+			up->ier = UART_IER_MSI;
+	}
+#endif
+
 	serial_port_out(port, UART_IER, up->ier);
 
 	if (port->flags & UPF_FOURPORT) {
@@ -2375,13 +2438,19 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 	if ((termios->c_cflag & CREAD) == 0)
 		port->ignore_status_mask |= UART_LSR_DR;
 
-	/*
-	 * CTS flow control flag and modem status interrupts
-	 */
-	up->ier &= ~UART_IER_MSI;
-	if (!(up->bugs & UART_BUG_NOMSR) &&
-			UART_ENABLE_MS(&up->port, termios->c_cflag))
-		up->ier |= UART_IER_MSI;
+#ifdef CONFIG_DREAMBOX_DM9X0
+	if (serial_index(port) != 0)
+#endif
+	{
+		/*
+		 * CTS flow control flag and modem status interrupts
+		 */
+		up->ier &= ~UART_IER_MSI;
+		if (!(up->bugs & UART_BUG_NOMSR) &&
+				UART_ENABLE_MS(&up->port, termios->c_cflag))
+			up->ier |= UART_IER_MSI;
+	}
+
 	if (up->capabilities & UART_CAP_UUE)
 		up->ier |= UART_IER_UUE;
 	if (up->capabilities & UART_CAP_RTOIE)
@@ -2748,6 +2817,24 @@ static struct uart_ops serial8250_pops = {
 
 static struct uart_8250_port serial8250_ports[UART_NR];
 
+/**
+ * serial8250_get_port - retrieve struct uart_8250_port
+ * @line: serial line number
+ *
+ * This function retrieves struct uart_8250_port for the specific line.
+ * This struct *must* *not* be used to perform a 8250 or serial core operation
+ * which is not accessible otherwise. Its only purpose is to make the struct
+ * accessible to the runtime-pm callbacks for context suspend/restore.
+ * The lock assumption made here is none because runtime-pm suspend/resume
+ * callbacks should not be invoked if there is any operation performed on the
+ * port.
+ */
+struct uart_8250_port *serial8250_get_port(int line)
+{
+	return &serial8250_ports[line];
+}
+EXPORT_SYMBOL_GPL(serial8250_get_port);
+
 static void (*serial8250_isa_config)(int port, struct uart_port *up,
 	unsigned short *capabilities);
 
@@ -2935,9 +3022,29 @@ static int __init serial8250_console_setup(struct console *co, char *options)
 	if (co->index >= nr_uarts)
 		co->index = 0;
 	port = &serial8250_ports[co->index].port;
+
 	if (!port->iobase && !port->membase)
 		return -ENODEV;
 
+#ifdef CONFIG_DREAMBOX_DM9X0
+	if (serial_index(port) == 0) {
+		volatile uint32_t *p = ioremap_nocache(0xf0404120, PAGE_SIZE);
+		*p |= 0x200;
+		iounmap(p);
+
+		udelay(1);
+
+		if (!(serial_in(&serial8250_ports[co->index], UART_MSR) & 0x10)) {
+			/*
+			 * workaround for magic boot delay when serial console is enabled and no cable is plugged to mini usb port
+			 * so disable the console when no cable is plugged
+			 *
+			 */
+			return -ENODEV;
+		}
+	}
+#endif
+
 	if (options)
 		uart_parse_options(options, &baud, &parity, &bits, &flow);
 
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 9dd8a71fff9e..aba541616fb8 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -9,6 +9,7 @@
  *  2 of the License, or (at your option) any later version.
  *
  */
+#include <linux/console.h>
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
@@ -158,7 +159,7 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
 	if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
 		return -EBUSY;
 
-	info = kmalloc(sizeof(*info), GFP_KERNEL);
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
 	if (info == NULL)
 		return -ENOMEM;
 
@@ -239,6 +240,70 @@ static int of_platform_serial_remove(struct platform_device *ofdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_SERIAL_8250
+static void of_serial_suspend_8250(struct of_serial_info *info)
+{
+	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
+	struct uart_port *port = &port8250->port;
+
+	serial8250_suspend_port(info->line);
+	if (info->clk && (!uart_console(port) || console_suspend_enabled))
+		clk_disable_unprepare(info->clk);
+}
+
+static void of_serial_resume_8250(struct of_serial_info *info)
+{
+	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
+	struct uart_port *port = &port8250->port;
+
+	if (info->clk && (!uart_console(port) || console_suspend_enabled))
+		clk_prepare_enable(info->clk);
+
+	serial8250_resume_port(info->line);
+}
+#else
+static inline void of_serial_suspend_8250(struct of_serial_info *info)
+{
+}
+
+static inline void of_serial_resume_8250(struct of_serial_info *info)
+{
+}
+#endif
+
+static int of_serial_suspend(struct device *dev)
+{
+	struct of_serial_info *info = dev_get_drvdata(dev);
+
+	switch (info->type) {
+	case PORT_8250 ... PORT_MAX_8250:
+		of_serial_suspend_8250(info);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int of_serial_resume(struct device *dev)
+{
+	struct of_serial_info *info = dev_get_drvdata(dev);
+
+	switch (info->type) {
+	case PORT_8250 ... PORT_MAX_8250:
+		of_serial_resume_8250(info);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+#endif
+static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
+
 /*
  * A few common types, add more as needed.
  */
@@ -269,6 +334,7 @@ static struct platform_driver of_platform_serial_driver = {
 		.name = "of_serial",
 		.owner = THIS_MODULE,
 		.of_match_table = of_platform_serial_table,
+		.pm = &of_serial_pm_ops,
 	},
 	.probe = of_platform_serial_probe,
 	.remove = of_platform_serial_remove,
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 1ae2bf39d84b..067dcf828390 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_USB_DWC2)		+= dwc2/
 obj-$(CONFIG_USB_MON)		+= mon/
 
 obj-$(CONFIG_PCI)		+= host/
+obj-$(CONFIG_BRCMSTB)		+= host/
 obj-$(CONFIG_USB_EHCI_HCD)	+= host/
 obj-$(CONFIG_USB_ISP116X_HCD)	+= host/
 obj-$(CONFIG_USB_OHCI_HCD)	+= host/
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index a5f77367386d..52df2ad1d8e2 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -3205,7 +3205,7 @@ static int finish_port_resume(struct usb_device *udev)
 /*
  * There are some SS USB devices which take longer time for link training.
  * XHCI specs 4.19.4 says that when Link training is successful, port
- * sets CSC bit to 1. So if SW reads port status before successful link
+ * sets CCS bit to 1. So if SW reads port status before successful link
  * training, then it will not find device to be present.
  * USB Analyzer log with such buggy devices show that in some cases
  * device switch on the RX termination after long delay of host enabling
@@ -3216,14 +3216,17 @@ static int finish_port_resume(struct usb_device *udev)
  * routine implements a 2000 ms timeout for link training. If in a case
  * link trains before timeout, loop will exit earlier.
  *
+ * There are also some 2.0 hard drive based devices and 3.0 thumb
+ * drives that, when plugged into a 2.0 only port, take a long
+ * time to set CCS after VBUS enable.
+ *
  * FIXME: If a device was connected before suspend, but was removed
  * while system was asleep, then the loop in the following routine will
  * only exit at timeout.
  *
- * This routine should only be called when persist is enabled for a SS
- * device.
+ * This routine should only be called when persist is enabled.
  */
-static int wait_for_ss_port_enable(struct usb_device *udev,
+static int wait_for_connected(struct usb_device *udev,
 		struct usb_hub *hub, int *port1,
 		u16 *portchange, u16 *portstatus)
 {
@@ -3236,6 +3239,7 @@ static int wait_for_ss_port_enable(struct usb_device *udev,
 		delay_ms += 20;
 		status = hub_port_status(hub, *port1, portstatus, portchange);
 	}
+	dev_dbg(&udev->dev, "Waited %dms for CONNECT\n", delay_ms);
 	return status;
 }
 
@@ -3341,8 +3345,8 @@ int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 
 	clear_bit(port1, hub->busy_bits);
 
-	if (udev->persist_enabled && hub_is_superspeed(hub->hdev))
-		status = wait_for_ss_port_enable(udev, hub, &port1, &portchange,
+	if (udev->persist_enabled)
+		status = wait_for_connected(udev, hub, &port1, &portchange,
 				&portstatus);
 
 	status = check_port_resume_type(udev,
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index fd13ef0a96c9..e7095c44f487 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -362,6 +362,8 @@ config USB_M66592
 	   dynamically linked module called "m66592_udc" and force all
 	   gadget drivers to also be dynamically linked.
 
+source "drivers/usb/gadget/bdc/Kconfig"
+
 #
 # Controllers available only in discrete form (and all PCI controllers)
 #
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5f150bc1b4bc..6a681b41731d 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_FUSB300)	+= fusb300_udc.o
 obj-$(CONFIG_USB_FOTG210_UDC)	+= fotg210-udc.o
 obj-$(CONFIG_USB_MV_U3D)	+= mv_u3d_core.o
 obj-$(CONFIG_USB_GR_UDC)	+= gr_udc.o
+obj-$(CONFIG_USB_BDC_UDC)	+= bdc/
 
 # USB Functions
 usb_f_acm-y			:= f_acm.o
diff --git a/drivers/usb/gadget/bdc/Kconfig b/drivers/usb/gadget/bdc/Kconfig
new file mode 100644
index 000000000000..0d7b8c9f72fd
--- /dev/null
+++ b/drivers/usb/gadget/bdc/Kconfig
@@ -0,0 +1,21 @@
+config USB_BDC_UDC
+	tristate "Broadcom USB3.0 device controller IP driver(BDC)"
+	depends on USB_GADGET && HAS_DMA
+
+	help
+	BDC is Broadcom's USB3.0 device controller IP. If your SOC has a BDC IP
+	then select this driver.
+
+	Say "y" here to link the driver statically, or "m" to build a dynamically
+	linked module called "bdc".
+
+if USB_BDC_UDC
+
+comment "Platform Support"
+config	USB_BDC_PCI
+	tristate "BDC support for PCIe based platforms"
+	depends on PCI
+	default USB_BDC_UDC
+	help
+		Enable support for platforms which have BDC connected through PCIe, such as Lego3 FPGA platform.
+endif
diff --git a/drivers/usb/gadget/bdc/Makefile b/drivers/usb/gadget/bdc/Makefile
new file mode 100644
index 000000000000..5cf6a3bcdf0f
--- /dev/null
+++ b/drivers/usb/gadget/bdc/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_USB_BDC_UDC)	+= bdc.o
+bdc-y	:= bdc_core.o bdc_cmd.o bdc_ep.o bdc_udc.o
+
+ifneq ($(CONFIG_USB_GADGET_VERBOSE),)
+	bdc-y			+= bdc_dbg.o
+endif
+
+obj-$(CONFIG_USB_BDC_PCI)	+= bdc_pci.o
diff --git a/drivers/usb/gadget/bdc/bdc.h b/drivers/usb/gadget/bdc/bdc.h
new file mode 100644
index 000000000000..56c059ff8d99
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc.h
@@ -0,0 +1,490 @@
+/*
+ * bdc.h - header for the BRCM BDC USB3.0 device controller
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef	__LINUX_BDC_H__
+#define	__LINUX_BDC_H__
+
+#include <linux/kernel.h>
+#include <linux/usb.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/debugfs.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <asm/unaligned.h>
+
+#define BRCM_BDC_NAME "bdc_usb3"
+#define BRCM_BDC_DESC "BDC device controller driver"
+
+#define DMA_ADDR_INVALID        (~(dma_addr_t)0)
+
+/* BDC command operation timeout in usec*/
+#define BDC_CMD_TIMEOUT	1000
+/* BDC controller operation timeout in usec*/
+#define BDC_COP_TIMEOUT	500
+
+/*
+ * Maximum size of ep0 response buffer for ch9 requests,
+ * the set_sel request uses 6 so far, the max.
+*/
+#define EP0_RESPONSE_BUFF  6
+/* Start with SS as default */
+#define EP0_MAX_PKT_SIZE 512
+
+/* 64 entries in a SRR */
+#define NUM_SR_ENTRIES	64
+
+/* Num of bds per table */
+#define NUM_BDS_PER_TABLE	32
+
+/* Num of tables in bd list for control,bulk and Int ep */
+#define NUM_TABLES	2
+
+/* Num of tables in bd list for Isoch ep */
+#define NUM_TABLES_ISOCH	6
+
+/* U1 Timeout default: 248usec */
+#define U1_TIMEOUT	0xf8
+
+/* Interrupt coalescence in usec */
+#define	INT_CLS	500
+
+/* Register offsets */
+/* Configuration and Capability registers */
+#define BDC_BDCCFG0	0x00
+#define BDC_BDCCFG1	0x04
+#define BDC_BDCCAP0	0x08
+#define BDC_BDCCAP1	0x0c
+#define BDC_CMDPAR0	0x10
+#define BDC_CMDPAR1	0x14
+#define BDC_CMDPAR2	0x18
+#define BDC_CMDSC	0x1c
+#define BDC_USPC	0x20
+#define BDC_USPPMS	0x28
+#define BDC_USPPM2	0x2c
+#define BDC_SPBBAL	0x38
+#define BDC_SPBBAH	0x3c
+#define BDC_BDCSC	0x40
+#define BDC_XSFNTF	0x4c
+
+#define BDC_DVCSA	0x50
+#define BDC_DVCSB	0x54
+#define BDC_EPSTS0	0x60
+#define BDC_EPSTS1	0x64
+#define BDC_EPSTS2	0x68
+#define BDC_EPSTS3	0x6c
+#define BDC_EPSTS4	0x70
+#define BDC_EPSTS5	0x74
+#define BDC_EPSTS6	0x78
+#define BDC_EPSTS7	0x7c
+#define BDC_SRRBAL(n)	(0x200 + (n * 0x10))
+#define BDC_SRRBAH(n)	(0x204 + (n * 0x10))
+#define BDC_SRRINT(n)	(0x208 + (n * 0x10))
+#define BDC_INTCTLS(n)	(0x20c + (n * 0x10))
+
+/* Extended capability regs */
+#define BDC_FSCNOC	0xcd4
+#define BDC_FSCNIC	0xce4
+#define NUM_NCS(p)	(p >> 28)
+
+/* Register bit fields and Masks */
+/* BDC Configuration 0 */
+#define BDC_PGS(p)	(((p) & (0x7 << 8)) >> 8)
+#define BDC_SPB(p)	(p & 0x7)
+
+/* BDC Capability1 */
+#define BDC_P64		(1 << 0)
+
+/* BDC Command register */
+#define BDC_CMD_FH	0xe
+#define BDC_CMD_DNC	0x6
+#define BDC_CMD_EPO	0x4
+#define BDC_CMD_BLA	0x3
+#define BDC_CMD_EPC	0x2
+#define BDC_CMD_DVC	0x1
+#define BDC_CMD_CWS		(0x1 << 5)
+#define BDC_CMD_CST(p)		(((p) & (0xf << 6))>>6)
+#define BDC_CMD_EPN(p)		((p & 0x1f) << 10)
+#define BDC_SUB_CMD_ADD		(0x1 << 17)
+#define BDC_SUB_CMD_FWK		(0x4 << 17)
+/* Reset sequence number */
+#define BDC_CMD_EPO_RST_SN	(0x1 << 16)
+#define BDC_CMD_EP0_XSD		(0x1 << 16)
+#define BDC_SUB_CMD_ADD_EP	(0x1 << 17)
+#define BDC_SUB_CMD_DRP_EP	(0x2 << 17)
+#define BDC_SUB_CMD_EP_STP	(0x2 << 17)
+#define BDC_SUB_CMD_EP_STL	(0x4 << 17)
+#define BDC_SUB_CMD_EP_RST	(0x1 << 17)
+#define BDC_CMD_SRD		(1 << 27)
+
+/* CMD completion status */
+#define BDC_CMDS_SUCC	0x1
+#define BDC_CMDS_PARA	0x3
+#define BDC_CMDS_STAT	0x4
+#define BDC_CMDS_FAIL	0x5
+#define BDC_CMDS_INTL	0x6
+#define BDC_CMDS_BUSY	0xf
+
+/* CMDSC Param 2 shifts */
+#define EPT_SHIFT	22
+#define MP_SHIFT	10
+#define MB_SHIFT	6
+#define EPM_SHIFT	4
+
+/* BDC USPSC */
+#define BDC_VBC		(1 << 31)
+#define BDC_PRC		(1 << 30)
+#define BDC_PCE		(1 << 29)
+#define BDC_CFC		(1 << 28)
+#define BDC_PCC		(1 << 27)
+#define BDC_PSC		(1 << 26)
+#define BDC_VBS		(1 << 25)
+#define BDC_PRS		(1 << 24)
+#define BDC_PCS		(1 << 23)
+#define BDC_PSP(p)	(((p) & (0x7 << 20))>>20)
+#define BDC_SCN		(1 << 8)
+#define BDC_SDC		(1 << 7)
+#define BDC_SWS		(1 << 4)
+
+#define BDC_USPSC_RW	(BDC_SCN|BDC_SDC|BDC_SWS|0xf)
+#define BDC_PSP(p)	(((p) & (0x7 << 20))>>20)
+
+#define BDC_SPEED_FS	0x1
+#define BDC_SPEED_LS	0x2
+#define BDC_SPEED_HS	0x3
+#define BDC_SPEED_SS	0x4
+
+#define BDC_PST(p)	(p & 0xf)
+#define BDC_PST_MASK	0xf
+
+/* USPPMS */
+#define BDC_U2E		(0x1 << 31)
+#define BDC_U1E		(0x1 << 30)
+#define BDC_U2A		(0x1 << 29)
+#define BDC_PORT_W1S	(0x1 << 17)
+#define BDC_U1T(p)	((p) & 0xff)
+#define BDC_U2T(p)	(((p) & 0xff) << 8)
+#define BDC_U1T_MASK	0xff
+
+/* USBPM2 */
+/* Hardware LPM Enable */
+#define BDC_HLE		(1 << 16)
+
+/* BDC Status and Control */
+#define BDC_COP_RST	(1 << 29)
+#define BDC_COP_RUN	(2 << 29)
+#define BDC_COP_STP	(4 << 29)
+
+#define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
+
+#define BDC_COS		(1 << 28)
+#define BDC_CSTS(p)	(((p) & (0x7 << 20)) >> 20)
+#define BDC_MASK_MCW	(1 << 7)
+#define BDC_GIE		(1 << 1)
+#define BDC_GIP		(1 << 0)
+
+#define BDC_HLT	1
+#define BDC_NOR	2
+#define BDC_OIP	7
+
+/* Buffer descriptor and Status report bit fields and masks */
+#define BD_TYPE_BITMASK	(0xf)
+#define BD_CHAIN	0xf
+
+#define BD_TFS_SHIFT	4
+#define BD_SOT		(1 << 26)
+#define BD_EOT		(1 << 27)
+#define BD_ISP		(1 << 29)
+#define BD_IOC		(1 << 30)
+#define BD_SBF		(1 << 31)
+
+#define BD_INTR_TARGET(p)	(((p) & 0x1f) << 27)
+
+#define BDC_SRR_RWS		(1 << 4)
+#define BDC_SRR_RST		(1 << 3)
+#define BDC_SRR_ISR		(1 << 2)
+#define BDC_SRR_IE		(1 << 1)
+#define BDC_SRR_IP		(1 << 0)
+#define BDC_SRR_EPI(p)	(((p) & (0xff << 24)) >> 24)
+#define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
+#define BDC_SRR_DPI_MASK	0x00ff0000
+
+#define MARK_CHAIN_BD	(BD_CHAIN|BD_EOT|BD_SOT)
+
+/* Control transfer BD specific fields */
+#define BD_DIR_IN		(1 << 25)
+
+#define BDC_PTC_MASK	0xf0000000
+
+/* status report defines */
+#define SR_XSF		0
+#define SR_USPC		4
+#define SR_BD_LEN(p)    (p & 0xffffff)
+
+#define XSF_SUCC	0x1
+#define XSF_SHORT	0x3
+#define XSF_BABB	0x4
+#define XSF_SETUP_RECV	0x6
+#define XSF_DATA_START	0x7
+#define XSF_STATUS_START 0x8
+
+#define XSF_STS(p) (((p) >> 28) & 0xf)
+
+/* Transfer BD fields */
+#define BD_LEN(p) ((p) & 0x1ffff)
+#define BD_LTF		(1 << 25)
+#define BD_TYPE_DS	0x1
+#define BD_TYPE_SS	0x2
+
+#define BDC_EP_ENABLED     (1 << 0)
+#define BDC_EP_STALL       (1 << 1)
+#define BDC_EP_STOP        (1 << 2)
+
+/* One BD can transfer max 65536 bytes */
+#define BD_MAX_BUFF_SIZE	(1 << 16)
+/* Maximum bytes in one XFR, Refer to BDC spec */
+#define MAX_XFR_LEN		16777215
+
+/* defines for Force Header command */
+#define DEV_NOTF_TYPE 6
+#define FWK_SUBTYPE  1
+#define TRA_PACKET   4
+
+#define to_bdc_ep(e)		container_of(e, struct bdc_ep, usb_ep)
+#define to_bdc_req(r)		container_of(r, struct bdc_req, usb_req)
+#define gadget_to_bdc(g)	container_of(g, struct bdc, gadget)
+
+/* FUNCTION WAKE DEV NOTIFICATION interval, USB3 spec table 8.13 */
+#define BDC_TNOTIFY 2500 /*in ms*/
+/* Devstatus bitfields */
+#define REMOTE_WAKEUP_ISSUED	(1 << 16)
+#define DEVICE_SUSPENDED	(1 << 17)
+#define FUNC_WAKE_ISSUED	(1 << 18)
+#define REMOTE_WAKE_ENABLE	(1 << USB_DEVICE_REMOTE_WAKEUP)
+
+/* On disconnect, preserve these bits and clear rest */
+#define DEVSTATUS_CLEAR		(1 << USB_DEVICE_SELF_POWERED)
+/* Hardware and software Data structures */
+
+/* Endpoint bd: buffer descriptor */
+struct bdc_bd {
+	__le32 offset[4];
+};
+
+/* Status report in Status report ring(srr) */
+struct bdc_sr {
+	__le32 offset[4];
+};
+
+/* bd_table: contigous bd's in a table */
+struct bd_table {
+	struct bdc_bd *start_bd;
+	/* dma address of start bd of table*/
+	dma_addr_t dma;
+};
+
+/*
+ * Each endpoint has a bdl(buffer descriptor list), bdl consists of 1 or more bd
+ * table's chained to each other through a chain bd, every table has equal
+ * number of bds. the software uses bdi(bd index) to refer to particular bd in
+ * the list.
+ */
+struct bd_list {
+	/* Array of bd table pointers*/
+	struct bd_table **bd_table_array;
+	/* How many tables chained to each other */
+	int num_tabs;
+	/* Max_bdi = num_tabs * num_bds_table - 1 */
+	int max_bdi;
+	/* current enq bdi from sw point of view */
+	int eqp_bdi;
+	/* current deq bdi from sw point of view */
+	int hwd_bdi;
+	/* numbers of bds per table */
+	int num_bds_table;
+};
+
+struct bdc_req;
+
+/* Representation of a transfer, one transfer can have multiple bd's */
+struct bd_transfer {
+	struct bdc_req *req;
+	/* start bd index */
+	int start_bdi;
+	/* this will be the next hw dqp when this transfer completes */
+	int next_hwd_bdi;
+	/* number of bds in this transfer */
+	int num_bds;
+};
+
+/*
+ * Representation of a gadget request, every gadget request is contained
+ * by 1 bd_transfer.
+ */
+struct bdc_req {
+	struct usb_request	usb_req;
+	struct list_head	queue;
+	struct bdc_ep		*ep;
+	/* only one Transfer per request */
+	struct bd_transfer bd_xfr;
+	int	epnum;
+};
+
+/* scratchpad buffer needed by bdc hardware */
+struct bdc_scratchpad {
+	dma_addr_t sp_dma;
+	void *buff;
+	u32 size;
+};
+
+/* endpoint representation */
+struct bdc_ep {
+	struct usb_ep	usb_ep;
+	struct list_head queue;
+	struct bdc *bdc;
+	u8  ep_type;
+	u8  dir;
+	u8  ep_num;
+	const struct usb_ss_ep_comp_descriptor	*comp_desc;
+	const struct usb_endpoint_descriptor	*desc;
+	unsigned int flags;
+	char name[20];
+	/* endpoint bd list*/
+	struct bd_list bd_list;
+	/*
+	 * HW generates extra event for multi bd tranfers, this flag helps in
+	 * ignoring the extra event
+	 */
+	bool ignore_next_sr;
+};
+
+/* bdc cmmand parameter structure */
+struct bdc_cmd_params {
+	u32	param2;
+	u32	param1;
+	u32	param0;
+};
+
+/* status report ring(srr), currently one srr is supported for entire system */
+struct srr {
+	struct bdc_sr *sr_bds;
+	u16	eqp_index;
+	u16	dqp_index;
+	dma_addr_t	dma_addr;
+};
+
+/* EP0 states */
+enum bdc_ep0_state {
+	WAIT_FOR_SETUP = 0,
+	WAIT_FOR_DATA_START,
+	WAIT_FOR_DATA_XMIT,
+	WAIT_FOR_STATUS_START,
+	WAIT_FOR_STATUS_XMIT,
+	STATUS_PENDING
+};
+
+/* Link states */
+enum bdc_link_state {
+	BDC_LINK_STATE_U0	= 0x00,
+	BDC_LINK_STATE_U3	= 0x03,
+	BDC_LINK_STATE_RX_DET	= 0x05,
+	BDC_LINK_STATE_RESUME	= 0x0f
+};
+
+/* representation of bdc */
+struct bdc {
+	struct usb_gadget	gadget;
+	struct usb_gadget_driver	*gadget_driver;
+	struct device	*dev;
+	/* device lock */
+	spinlock_t	lock;
+
+	/* num of endpoints for a particular instantiation of IP */
+	unsigned int num_eps;
+	/*
+	 * Array of ep's, it uses the same index covention as bdc hw i.e.
+	 * 1 for ep0, 2 for 1out,3 for 1in ....
+	 */
+	struct bdc_ep		**bdc_ep_array;
+	void __iomem		*regs;
+	struct bdc_scratchpad	scratchpad;
+	u32	sp_buff_size;
+	/* current driver supports 1 status ring */
+	struct srr	srr;
+	/* Last received setup packet */
+	struct	usb_ctrlrequest setup_pkt;
+	struct	bdc_req ep0_req;
+	struct	bdc_req status_req;
+	enum	bdc_ep0_state ep0_state;
+	bool	delayed_status;
+	bool	zlp_needed;
+	bool	reinit;
+	bool	pullup;
+	/* Bits 0-15 are standard and 16-31 for proprietary information */
+	u32	devstatus;
+	int	irq;
+	void	*mem;
+	u32	dev_addr;
+	/* DMA pools */
+	struct dma_pool	*bd_table_pool;
+	u8		test_mode;
+	/* array of callbacks for various status report handlers */
+	void (*sr_handler[2])(struct bdc *, struct bdc_sr *);
+	/* ep0 callback handlers */
+	void (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);
+	/* ep0 response buffer for ch9 requests like GET_STATUS and SET_SEL */
+	unsigned char		ep0_response_buff[EP0_RESPONSE_BUFF];
+	/*
+	 * Timer to check if host resumed transfer after bdc sent Func wake
+	 * notification  packet after a remote wakeup. if not, then resend the
+	 * Func Wake packet every 2.5 secs. Refer to USB3 spec section 8.5.6.4
+	 */
+	struct delayed_work	func_wake_notify;
+};
+
+static inline u32 bdc_readl(void __iomem *base, u32 offset)
+{
+	return readl(base + offset);
+}
+
+static inline void bdc_writel(void __iomem *base, u32 offset, u32 value)
+{
+	writel(value, base + offset);
+}
+
+/* Buffer descriptor list operations */
+void bdc_notify_xfr(struct bdc *, u32);
+void bdc_softconn(struct bdc *);
+void bdc_softdisconn(struct bdc *);
+int bdc_run(struct bdc *);
+int bdc_stop(struct bdc *);
+int bdc_reset(struct bdc *);
+int bdc_udc_init(struct bdc *);
+void bdc_udc_exit(struct bdc *);
+int bdc_reinit(struct bdc *);
+
+/* Status report handlers */
+/* Upstream port status change sr */
+void bdc_sr_uspc(struct bdc *, struct bdc_sr *);
+/* transfer sr */
+void bdc_sr_xsf(struct bdc *, struct bdc_sr *);
+/* EP0 XSF handlers */
+void bdc_xsf_ep0_setup_recv(struct bdc *, struct bdc_sr *);
+void bdc_xsf_ep0_data_start(struct bdc *, struct bdc_sr *);
+void bdc_xsf_ep0_status_start(struct bdc *, struct bdc_sr *);
+
+#endif /* __LINUX_BDC_H__ */
diff --git a/drivers/usb/gadget/bdc/bdc_cmd.c b/drivers/usb/gadget/bdc/bdc_cmd.c
new file mode 100644
index 000000000000..6a4155c4bd86
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_cmd.c
@@ -0,0 +1,376 @@
+/*
+ * bdc_cmd.c - BRCM BDC USB3.0 device controller
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+
+#include "bdc.h"
+#include "bdc_cmd.h"
+#include "bdc_dbg.h"
+
+/* Issues a cmd to cmd processor and waits for cmd completion */
+static int bdc_issue_cmd(struct bdc *bdc, u32 cmd_sc, u32 param0,
+							u32 param1, u32 param2)
+{
+	u32 timeout = BDC_CMD_TIMEOUT;
+	u32 cmd_status;
+	u32 temp;
+
+	bdc_writel(bdc->regs, BDC_CMDPAR0, param0);
+	bdc_writel(bdc->regs, BDC_CMDPAR1, param1);
+	bdc_writel(bdc->regs, BDC_CMDPAR2, param2);
+
+	/* Issue the cmd */
+	/* Make sure the cmd params are written before asking HW to exec cmd */
+	wmb();
+	bdc_writel(bdc->regs, BDC_CMDSC, cmd_sc | BDC_CMD_CWS | BDC_CMD_SRD);
+	do {
+		temp = bdc_readl(bdc->regs, BDC_CMDSC);
+		dev_dbg_ratelimited(bdc->dev, "cmdsc=%x", temp);
+		cmd_status =  BDC_CMD_CST(temp);
+		if (cmd_status != BDC_CMDS_BUSY)  {
+			dev_dbg(bdc->dev,
+				"command completed cmd_sts:%x\n", cmd_status);
+			return cmd_status;
+		}
+		udelay(1);
+	} while (timeout--);
+
+	dev_err(bdc->dev,
+		"command operation timedout cmd_status=%d\n", cmd_status);
+
+	return cmd_status;
+}
+
+/* Submits cmd and analyze the return value of bdc_issue_cmd */
+static int bdc_submit_cmd(struct bdc *bdc, u32 cmd_sc,
+					u32 param0, u32 param1,	u32 param2)
+{
+	u32 temp, cmd_status;
+	int reset_bdc = 0;
+	int ret;
+
+	temp = bdc_readl(bdc->regs, BDC_CMDSC);
+	dev_dbg(bdc->dev,
+		"%s:CMDSC:%08x cmdsc:%08x param0=%08x param1=%08x param2=%08x\n",
+		 __func__, temp, cmd_sc, param0, param1, param2);
+
+	cmd_status = BDC_CMD_CST(temp);
+	if (cmd_status  ==  BDC_CMDS_BUSY) {
+		dev_err(bdc->dev, "command processor busy: %x\n", cmd_status);
+		return -EBUSY;
+	}
+	ret = bdc_issue_cmd(bdc, cmd_sc, param0, param1, param2);
+	switch (ret) {
+	case BDC_CMDS_SUCC:
+		dev_dbg(bdc->dev, "command completed successfully\n");
+		ret = 0;
+		break;
+
+	case BDC_CMDS_PARA:
+		dev_err(bdc->dev, "command parameter error\n");
+		ret = -EINVAL;
+		break;
+
+	case BDC_CMDS_STAT:
+		dev_err(bdc->dev, "Invalid device/ep state\n");
+		ret = -EINVAL;
+		break;
+
+	case BDC_CMDS_FAIL:
+		dev_err(bdc->dev, "Command failed?\n");
+		ret = -EAGAIN;
+		break;
+
+	case BDC_CMDS_INTL:
+		dev_err(bdc->dev, "BDC Internal error\n");
+		reset_bdc = 1;
+		ret = -ECONNRESET;
+		break;
+
+	case BDC_CMDS_BUSY:
+		dev_err(bdc->dev,
+			"command timedout waited for %dusec\n",
+			BDC_CMD_TIMEOUT);
+		reset_bdc = 1;
+		ret = -ECONNRESET;
+		break;
+	default:
+		dev_dbg(bdc->dev, "Unknown command completion code:%x\n", ret);
+	}
+
+	return ret;
+}
+
+/* Deconfigure the endpoint from HW */
+int bdc_dconfig_ep(struct bdc *bdc, struct bdc_ep *ep)
+{
+	u32 cmd_sc;
+
+	cmd_sc = BDC_SUB_CMD_DRP_EP|BDC_CMD_EPN(ep->ep_num)|BDC_CMD_EPC;
+	dev_dbg(bdc->dev, "%s ep->ep_num =%d cmd_sc=%x\n", __func__,
+							ep->ep_num, cmd_sc);
+
+	return bdc_submit_cmd(bdc, cmd_sc, 0, 0, 0);
+}
+
+/* Reinitalize the bdlist after config ep command */
+static void ep_bd_list_reinit(struct bdc_ep *ep)
+{
+	struct bdc *bdc = ep->bdc;
+	struct bdc_bd *bd;
+
+	ep->bd_list.eqp_bdi = 0;
+	ep->bd_list.hwd_bdi = 0;
+	bd = ep->bd_list.bd_table_array[0]->start_bd;
+	dev_dbg(bdc->dev, "%s ep:%p bd:%p\n", __func__, ep, bd);
+	memset(bd, 0, sizeof(struct bdc_bd));
+	bd->offset[3] |= cpu_to_le32(BD_SBF);
+}
+
+/* Configure an endpoint */
+int bdc_config_ep(struct bdc *bdc, struct bdc_ep *ep)
+{
+	const struct usb_ss_ep_comp_descriptor *comp_desc;
+	const struct usb_endpoint_descriptor	*desc;
+	u32 param0, param1, param2, cmd_sc;
+	u32 mps, mbs, mul, si;
+	int ret;
+
+	desc = ep->desc;
+	comp_desc = ep->comp_desc;
+	cmd_sc = mul = mbs = param2 = 0;
+	param0 = lower_32_bits(ep->bd_list.bd_table_array[0]->dma);
+	param1 = upper_32_bits(ep->bd_list.bd_table_array[0]->dma);
+	cpu_to_le32s(&param0);
+	cpu_to_le32s(&param1);
+
+	dev_dbg(bdc->dev, "%s: param0=%08x param1=%08x",
+						__func__, param0, param1);
+	si = desc->bInterval;
+	si = clamp_val(si, 1, 16) - 1;
+
+	mps = usb_endpoint_maxp(desc);
+	mps &= 0x7ff;
+	param2 |= mps << MP_SHIFT;
+	param2 |= usb_endpoint_type(desc) << EPT_SHIFT;
+
+	switch (bdc->gadget.speed) {
+	case USB_SPEED_SUPER:
+		if (usb_endpoint_xfer_int(desc) ||
+					usb_endpoint_xfer_isoc(desc)) {
+			param2 |= si;
+			if (usb_endpoint_xfer_isoc(desc) && comp_desc)
+					mul = comp_desc->bmAttributes;
+
+		}
+		param2 |= mul << EPM_SHIFT;
+		if (comp_desc)
+			mbs = comp_desc->bMaxBurst;
+		param2 |= mbs << MB_SHIFT;
+		break;
+
+	case USB_SPEED_HIGH:
+		if (usb_endpoint_xfer_isoc(desc) ||
+					usb_endpoint_xfer_int(desc)) {
+			param2 |= si;
+
+			mbs = (usb_endpoint_maxp(desc) & 0x1800) >> 11;
+			param2 |= mbs << MB_SHIFT;
+		}
+		break;
+
+	case USB_SPEED_FULL:
+	case USB_SPEED_LOW:
+		/* the hardware accepts SI in 125usec range */
+		if (usb_endpoint_xfer_isoc(desc))
+			si += 3;
+
+		/*
+		 * FS Int endpoints can have si of 1-255ms but the controller
+		 * accepts 2^bInterval*125usec, so convert ms to nearest power
+		 * of 2
+		 */
+		if (usb_endpoint_xfer_int(desc))
+			si = fls(desc->bInterval * 8) - 1;
+
+		param2 |= si;
+		break;
+	default:
+		dev_err(bdc->dev, "UNKNOWN speed ERR\n");
+		return -EINVAL;
+	}
+
+	cmd_sc |= BDC_CMD_EPC|BDC_CMD_EPN(ep->ep_num)|BDC_SUB_CMD_ADD_EP;
+
+	dev_dbg(bdc->dev, "cmd_sc=%x param2=%08x\n", cmd_sc, param2);
+	ret = bdc_submit_cmd(bdc, cmd_sc, param0, param1, param2);
+	if (ret) {
+		dev_err(bdc->dev, "command failed :%x\n", ret);
+		return ret;
+	}
+	ep_bd_list_reinit(ep);
+
+	return ret;
+}
+
+/*
+ * Change the HW deq pointer, if this command is successful, HW will start
+ * fetching the next bd from address dma_addr.
+ */
+int bdc_ep_bla(struct bdc *bdc, struct bdc_ep *ep, dma_addr_t dma_addr)
+{
+	u32 param0, param1;
+	u32 cmd_sc = 0;
+
+	dev_dbg(bdc->dev, "%s: add=%08llx\n", __func__,
+				(unsigned long long)(dma_addr));
+	param0 = lower_32_bits(dma_addr);
+	param1 = upper_32_bits(dma_addr);
+	cpu_to_le32s(&param0);
+	cpu_to_le32s(&param1);
+
+	cmd_sc |= BDC_CMD_EPN(ep->ep_num)|BDC_CMD_BLA;
+	dev_dbg(bdc->dev, "cmd_sc=%x\n", cmd_sc);
+
+	return bdc_submit_cmd(bdc, cmd_sc, param0, param1, 0);
+}
+
+/* Set the address sent bu Host in SET_ADD request */
+int bdc_address_device(struct bdc *bdc, u32 add)
+{
+	u32 cmd_sc = 0;
+	u32 param2;
+
+	dev_dbg(bdc->dev, "%s: add=%d\n", __func__, add);
+	cmd_sc |=  BDC_SUB_CMD_ADD|BDC_CMD_DVC;
+	param2 = add & 0x7f;
+
+	return bdc_submit_cmd(bdc, cmd_sc, 0, 0, param2);
+}
+
+/* Send a Function Wake notification packet using FH command */
+int bdc_function_wake_fh(struct bdc *bdc, u8 intf)
+{
+	u32 param0, param1;
+	u32 cmd_sc = 0;
+
+	param0 = param1 = 0;
+	dev_dbg(bdc->dev, "%s intf=%d\n", __func__, intf);
+	cmd_sc  |=  BDC_CMD_FH;
+	param0 |= TRA_PACKET;
+	param0 |= (bdc->dev_addr << 25);
+	param1 |= DEV_NOTF_TYPE;
+	param1 |= (FWK_SUBTYPE<<4);
+	dev_dbg(bdc->dev, "param0=%08x param1=%08x\n", param0, param1);
+
+	return bdc_submit_cmd(bdc, cmd_sc, param0, param1, 0);
+}
+
+/* Send a Function Wake notification packet using DNC command */
+int bdc_function_wake(struct bdc *bdc, u8 intf)
+{
+	u32 cmd_sc = 0;
+	u32 param2 = 0;
+
+	dev_dbg(bdc->dev, "%s intf=%d", __func__, intf);
+	param2 |= intf;
+	cmd_sc |= BDC_SUB_CMD_FWK|BDC_CMD_DNC;
+
+	return bdc_submit_cmd(bdc, cmd_sc, 0, 0, param2);
+}
+
+/* Stall the endpoint */
+int bdc_ep_set_stall(struct bdc *bdc, int epnum)
+{
+	u32 cmd_sc = 0;
+
+	dev_dbg(bdc->dev, "%s epnum=%d\n", __func__, epnum);
+	/* issue a stall endpoint command */
+	cmd_sc |=  BDC_SUB_CMD_EP_STL | BDC_CMD_EPN(epnum) | BDC_CMD_EPO;
+
+	return bdc_submit_cmd(bdc, cmd_sc, 0, 0, 0);
+}
+
+/* resets the endpoint, called when host sends CLEAR_FEATURE(HALT) */
+int bdc_ep_clear_stall(struct bdc *bdc, int epnum)
+{
+	struct bdc_ep *ep;
+	u32 cmd_sc = 0;
+	int ret;
+
+	dev_dbg(bdc->dev, "%s: epnum=%d\n", __func__, epnum);
+	ep = bdc->bdc_ep_array[epnum];
+	/*
+	 * If we are not in stalled then stall Endpoint and issue clear stall,
+	 * his will reset the seq number for non EP0.
+	 */
+	if (epnum != 1) {
+		/* if the endpoint it not stallled */
+		if (!(ep->flags & BDC_EP_STALL)) {
+			ret = bdc_ep_set_stall(bdc, epnum);
+				if (ret)
+					return ret;
+		}
+	}
+	/* Preserve the seq number for ep0 only */
+	if (epnum != 1)
+		cmd_sc |= BDC_CMD_EPO_RST_SN;
+
+	/* issue a reset endpoint command */
+	cmd_sc |=  BDC_SUB_CMD_EP_RST | BDC_CMD_EPN(epnum) | BDC_CMD_EPO;
+
+	ret = bdc_submit_cmd(bdc, cmd_sc, 0, 0, 0);
+	if (ret) {
+		dev_err(bdc->dev, "command failed:%x\n", ret);
+		return ret;
+	}
+	bdc_notify_xfr(bdc, epnum);
+
+	return ret;
+}
+
+/* Stop the endpoint, called when software wants to dequeue some request */
+int bdc_stop_ep(struct bdc *bdc, int epnum)
+{
+	struct bdc_ep *ep;
+	u32 cmd_sc = 0;
+	int ret;
+
+	ep = bdc->bdc_ep_array[epnum];
+	dev_dbg(bdc->dev, "%s: ep:%s ep->flags:%08x\n", __func__,
+						ep->name, ep->flags);
+	/* Endpoint has to be in running state to execute stop ep command */
+	if (!(ep->flags & BDC_EP_ENABLED)) {
+		dev_err(bdc->dev, "stop endpoint called for disabled ep\n");
+		return   -EINVAL;
+	}
+	if ((ep->flags & BDC_EP_STALL) || (ep->flags & BDC_EP_STOP))
+		return 0;
+
+	/* issue a stop endpoint command */
+	cmd_sc |= BDC_CMD_EP0_XSD | BDC_SUB_CMD_EP_STP
+				| BDC_CMD_EPN(epnum) | BDC_CMD_EPO;
+
+	ret = bdc_submit_cmd(bdc, cmd_sc, 0, 0, 0);
+	if (ret) {
+		dev_err(bdc->dev,
+			"stop endpoint command didn't complete:%d ep:%s\n",
+			ret, ep->name);
+		return ret;
+	}
+	ep->flags |= BDC_EP_STOP;
+	bdc_dump_epsts(bdc);
+
+	return ret;
+}
diff --git a/drivers/usb/gadget/bdc/bdc_cmd.h b/drivers/usb/gadget/bdc/bdc_cmd.h
new file mode 100644
index 000000000000..61d0e3bf9853
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_cmd.h
@@ -0,0 +1,29 @@
+/*
+ * bdc_cmd.h - header for the BDC debug functions
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __LINUX_BDC_CMD_H__
+#define __LINUX_BDC_CMD_H__
+
+/* Command operations */
+int bdc_address_device(struct bdc *, u32);
+int bdc_config_ep(struct bdc *, struct bdc_ep *);
+int bdc_dconfig_ep(struct bdc *, struct bdc_ep *);
+int bdc_stop_ep(struct bdc *, int);
+int bdc_ep_set_stall(struct bdc *, int);
+int bdc_ep_clear_stall(struct bdc *, int);
+int bdc_ep_set_halt(struct bdc_ep *, u32 , int);
+int bdc_ep_bla(struct bdc *, struct bdc_ep *, dma_addr_t);
+int bdc_function_wake(struct bdc*, u8);
+int bdc_function_wake_fh(struct bdc*, u8);
+
+#endif /* __LINUX_BDC_CMD_H__ */
diff --git a/drivers/usb/gadget/bdc/bdc_core.c b/drivers/usb/gadget/bdc/bdc_core.c
new file mode 100644
index 000000000000..0ee2560ba36b
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_core.c
@@ -0,0 +1,556 @@
+/*
+ * bdc_core.c - BRCM BDC USB3.0 device controller core operations
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/of.h>
+#include <linux/moduleparam.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include "bdc.h"
+#include "bdc_dbg.h"
+
+/* Poll till controller status is not OIP */
+static int poll_oip(struct bdc *bdc, int usec)
+{
+	u32 status;
+	/* Poll till STS!= OIP */
+	while (usec) {
+		status = bdc_readl(bdc->regs, BDC_BDCSC);
+		if (BDC_CSTS(status) != BDC_OIP) {
+			dev_dbg(bdc->dev,
+				"poll_oip complete status=%d",
+				BDC_CSTS(status));
+			return 0;
+		}
+		udelay(10);
+		usec -= 10;
+	}
+	dev_err(bdc->dev, "Err: operation timedout BDCSC: 0x%08x\n", status);
+
+	return -ETIMEDOUT;
+}
+
+/* Stop the BDC controller */
+int bdc_stop(struct bdc *bdc)
+{
+	int ret;
+	u32 temp;
+
+	dev_dbg(bdc->dev, "%s ()\n\n", __func__);
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	/* Check if BDC is already halted */
+	if (BDC_CSTS(temp) == BDC_HLT) {
+		dev_vdbg(bdc->dev, "BDC already halted\n");
+		return 0;
+	}
+	temp &= ~BDC_COP_MASK;
+	temp |= BDC_COS|BDC_COP_STP;
+	bdc_writel(bdc->regs, BDC_BDCSC, temp);
+
+	ret = poll_oip(bdc, BDC_COP_TIMEOUT);
+	if (ret)
+		dev_err(bdc->dev, "bdc stop operation failed");
+
+	return ret;
+}
+
+/* Issue a reset to BDC controller */
+int bdc_reset(struct bdc *bdc)
+{
+	u32 temp;
+	int ret;
+
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	/* First halt the controller */
+	ret = bdc_stop(bdc);
+	if (ret)
+		return ret;
+
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	temp &= ~BDC_COP_MASK;
+	temp |= BDC_COS|BDC_COP_RST;
+	bdc_writel(bdc->regs, BDC_BDCSC, temp);
+	ret = poll_oip(bdc, BDC_COP_TIMEOUT);
+	if (ret)
+		dev_err(bdc->dev, "bdc reset operation failed");
+
+	return ret;
+}
+
+/* Run the BDC controller */
+int bdc_run(struct bdc *bdc)
+{
+	u32 temp;
+	int ret;
+
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	/* if BDC is already in running state then do not do anything */
+	if (BDC_CSTS(temp) == BDC_NOR) {
+		dev_warn(bdc->dev, "bdc is already in running state\n");
+		return 0;
+	}
+	temp &= ~BDC_COP_MASK;
+	temp |= BDC_COP_RUN;
+	temp |= BDC_COS;
+	bdc_writel(bdc->regs, BDC_BDCSC, temp);
+	ret = poll_oip(bdc, BDC_COP_TIMEOUT);
+	if (ret) {
+		dev_err(bdc->dev, "bdc run operation failed:%d", ret);
+		return ret;
+	}
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	if (BDC_CSTS(temp) != BDC_NOR) {
+		dev_err(bdc->dev, "bdc not in normal mode after RUN op :%d\n",
+								BDC_CSTS(temp));
+		return -ESHUTDOWN;
+	}
+
+	return 0;
+}
+
+/*
+ * Present the termination to the host, typically called from upstream port
+ * event with Vbus present =1
+ */
+void bdc_softconn(struct bdc *bdc)
+{
+	u32 uspc;
+
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	uspc &= ~BDC_PST_MASK;
+	uspc |= BDC_LINK_STATE_RX_DET;
+	uspc |= BDC_SWS;
+	dev_dbg(bdc->dev, "%s () uspc=%08x\n", __func__, uspc);
+	bdc_writel(bdc->regs, BDC_USPC, uspc);
+}
+
+/* Remove the termination */
+void bdc_softdisconn(struct bdc *bdc)
+{
+	u32 uspc;
+
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	uspc |= BDC_SDC;
+	uspc &= ~BDC_SCN;
+	dev_dbg(bdc->dev, "%s () uspc=%x\n", __func__, uspc);
+	bdc_writel(bdc->regs, BDC_USPC, uspc);
+}
+
+/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
+static int scratchpad_setup(struct bdc *bdc)
+{
+	int sp_buff_size;
+	u32 low32;
+	u32 upp32;
+
+	sp_buff_size = BDC_SPB(bdc_readl(bdc->regs, BDC_BDCCFG0));
+	dev_dbg(bdc->dev, "%s() sp_buff_size=%d\n", __func__, sp_buff_size);
+	if (!sp_buff_size) {
+		dev_dbg(bdc->dev, "Scratchpad buffer not needed\n");
+		return 0;
+	}
+	/* Refer to BDC spec, Table 4 for description of SPB */
+	sp_buff_size = 1 << (sp_buff_size + 5);
+	dev_dbg(bdc->dev, "Allocating %d bytes for scratchpad\n", sp_buff_size);
+	bdc->scratchpad.buff  =  dma_zalloc_coherent(bdc->dev, sp_buff_size,
+					&bdc->scratchpad.sp_dma, GFP_KERNEL);
+
+	if (!bdc->scratchpad.buff)
+		goto fail;
+
+	bdc->sp_buff_size = sp_buff_size;
+	bdc->scratchpad.size = sp_buff_size;
+	low32 = lower_32_bits(bdc->scratchpad.sp_dma);
+	upp32 = upper_32_bits(bdc->scratchpad.sp_dma);
+	cpu_to_le32s(&low32);
+	cpu_to_le32s(&upp32);
+	bdc_writel(bdc->regs, BDC_SPBBAL, low32);
+	bdc_writel(bdc->regs, BDC_SPBBAH, upp32);
+	return 0;
+
+fail:
+	bdc->scratchpad.buff = NULL;
+
+	return -ENOMEM;
+}
+
+/* Allocate the status report ring */
+static int setup_srr(struct bdc *bdc, int interrupter)
+{
+	dev_dbg(bdc->dev, "%s() NUM_SR_ENTRIES:%d\n", __func__, NUM_SR_ENTRIES);
+	/* Reset the SRR */
+	bdc_writel(bdc->regs, BDC_SRRINT(0), BDC_SRR_RWS | BDC_SRR_RST);
+	bdc->srr.dqp_index = 0;
+	/* allocate the status report descriptors */
+	bdc->srr.sr_bds = dma_zalloc_coherent(
+					bdc->dev,
+					NUM_SR_ENTRIES * sizeof(struct bdc_bd),
+					&bdc->srr.dma_addr,
+					GFP_KERNEL);
+	if (!bdc->srr.sr_bds)
+		return -ENOMEM;
+
+	return 0;
+}
+
+/* Initialize the HW regs and internal data structures */
+static void bdc_mem_init(struct bdc *bdc, bool reinit)
+{
+	u8 size = 0;
+	u32 usb2_pm;
+	u32 low32;
+	u32 upp32;
+	u32 temp;
+
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	bdc->ep0_state = WAIT_FOR_SETUP;
+	bdc->dev_addr = 0;
+	bdc->srr.eqp_index = 0;
+	bdc->srr.dqp_index = 0;
+	bdc->zlp_needed = false;
+	bdc->delayed_status = false;
+
+	bdc_writel(bdc->regs, BDC_SPBBAL, bdc->scratchpad.sp_dma);
+	/* Init the SRR */
+	temp = BDC_SRR_RWS | BDC_SRR_RST;
+	/* Reset the SRR */
+	bdc_writel(bdc->regs, BDC_SRRINT(0), temp);
+	dev_dbg(bdc->dev, "bdc->srr.sr_bds =%p\n", bdc->srr.sr_bds);
+	temp = lower_32_bits(bdc->srr.dma_addr);
+	size = fls(NUM_SR_ENTRIES) - 2;
+	temp |= size;
+	dev_dbg(bdc->dev, "SRRBAL[0]=%08x NUM_SR_ENTRIES:%d size:%d\n",
+						temp, NUM_SR_ENTRIES, size);
+
+	low32 = lower_32_bits(temp);
+	upp32 = upper_32_bits(bdc->srr.dma_addr);
+	cpu_to_le32s(&low32);
+	cpu_to_le32s(&upp32);
+
+	/* Write the dma addresses into regs*/
+	bdc_writel(bdc->regs, BDC_SRRBAL(0), low32);
+	bdc_writel(bdc->regs, BDC_SRRBAH(0), upp32);
+
+	temp = bdc_readl(bdc->regs, BDC_SRRINT(0));
+	temp |= BDC_SRR_IE;
+	temp &= ~(BDC_SRR_RST | BDC_SRR_RWS);
+	bdc_writel(bdc->regs, BDC_SRRINT(0), temp);
+
+	/* Set the Interrupt Coalescence ~500 usec */
+	temp = bdc_readl(bdc->regs, BDC_INTCTLS(0));
+	temp &= ~0xffff;
+	temp |= INT_CLS;
+	bdc_writel(bdc->regs, BDC_INTCTLS(0), temp);
+
+	usb2_pm = bdc_readl(bdc->regs, BDC_USPPM2);
+	dev_dbg(bdc->dev, "usb2_pm=%08x", usb2_pm);
+	/* Enable hardware LPM Enable */
+	usb2_pm |= BDC_HLE;
+	bdc_writel(bdc->regs, BDC_USPPM2, usb2_pm);
+
+	/* readback for debug */
+	usb2_pm = bdc_readl(bdc->regs, BDC_USPPM2);
+	dev_dbg(bdc->dev, "usb2_pm=%08x\n", usb2_pm);
+
+	/* Disable any unwanted SR's on SRR */
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	/* We don't want Microframe counter wrap SR */
+	temp |= BDC_MASK_MCW;
+	bdc_writel(bdc->regs, BDC_BDCSC, temp);
+
+	/*
+	 * In some error cases, driver has to reset the entire BDC controller
+	 * in that case reinit is passed as 1
+	 */
+	if (reinit) {
+		/* Enable interrupts */
+		temp = bdc_readl(bdc->regs, BDC_BDCSC);
+		temp |= BDC_GIE;
+		bdc_writel(bdc->regs, BDC_BDCSC, temp);
+		/* Init scratchpad to 0 */
+		memset(bdc->scratchpad.buff, 0, bdc->sp_buff_size);
+		/* Initialize SRR to 0 */
+		memset(bdc->srr.sr_bds, 0,
+					NUM_SR_ENTRIES * sizeof(struct bdc_bd));
+	} else {
+		/* One time initiaization only */
+		/* Enable status report function pointers */
+		bdc->sr_handler[0] = bdc_sr_xsf;
+		bdc->sr_handler[1] = bdc_sr_uspc;
+
+		/* EP0 status report function pointers */
+		bdc->sr_xsf_ep0[0] = bdc_xsf_ep0_setup_recv;
+		bdc->sr_xsf_ep0[1] = bdc_xsf_ep0_data_start;
+		bdc->sr_xsf_ep0[2] = bdc_xsf_ep0_status_start;
+	}
+}
+
+/* Free the dynamic memory */
+static void bdc_mem_free(struct bdc *bdc)
+{
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	/* Free SRR */
+	if (bdc->srr.sr_bds)
+		dma_free_coherent(bdc->dev,
+					NUM_SR_ENTRIES * sizeof(struct bdc_bd),
+					bdc->srr.sr_bds, bdc->srr.dma_addr);
+
+	/* Free scratchpad */
+	if (bdc->scratchpad.buff)
+		dma_free_coherent(bdc->dev, bdc->sp_buff_size,
+				bdc->scratchpad.buff, bdc->scratchpad.sp_dma);
+
+	/* Destroy the dma pools */
+	if (bdc->bd_table_pool)
+		dma_pool_destroy(bdc->bd_table_pool);
+
+	/* Free the bdc_ep array */
+	kfree(bdc->bdc_ep_array);
+
+	bdc->srr.sr_bds = NULL;
+	bdc->scratchpad.buff = NULL;
+	bdc->bd_table_pool = NULL;
+	bdc->bdc_ep_array = NULL;
+}
+
+/*
+ * bdc reinit gives a controller reset and reinitialize the registers,
+ * called from disconnect/bus reset scenario's, to ensure proper HW cleanup
+ */
+int bdc_reinit(struct bdc *bdc)
+{
+	int ret;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	ret = bdc_stop(bdc);
+	if (ret)
+		goto out;
+
+	ret = bdc_reset(bdc);
+	if (ret)
+		goto out;
+
+	/* the reinit flag is 1 */
+	bdc_mem_init(bdc, true);
+	ret = bdc_run(bdc);
+out:
+	bdc->reinit = false;
+
+	return ret;
+}
+
+/* Allocate all the dyanmic memory */
+static int bdc_mem_alloc(struct bdc *bdc)
+{
+	u32 page_size;
+	unsigned int num_ieps, num_oeps;
+
+	dev_dbg(bdc->dev,
+		"%s() NUM_BDS_PER_TABLE:%d\n", __func__,
+		NUM_BDS_PER_TABLE);
+	page_size = BDC_PGS(bdc_readl(bdc->regs, BDC_BDCCFG0));
+	/* page size is 2^pgs KB */
+	page_size = 1 << page_size;
+	/* KB */
+	page_size <<= 10;
+	dev_dbg(bdc->dev, "page_size=%d\n", page_size);
+
+	/* Create a pool of bd tables */
+	bdc->bd_table_pool =
+	    dma_pool_create("BDC BD tables", bdc->dev, NUM_BDS_PER_TABLE * 16,
+								16, page_size);
+
+	if (!bdc->bd_table_pool)
+		goto fail;
+
+	if (scratchpad_setup(bdc))
+		goto fail;
+
+	/* read from regs */
+	num_ieps = NUM_NCS(bdc_readl(bdc->regs, BDC_FSCNIC));
+	num_oeps = NUM_NCS(bdc_readl(bdc->regs, BDC_FSCNOC));
+	/* +2: 1 for ep0 and the other is rsvd i.e. bdc_ep[0] is rsvd */
+	bdc->num_eps = num_ieps + num_oeps + 2;
+	dev_dbg(bdc->dev,
+		"ieps:%d eops:%d num_eps:%d\n",
+		num_ieps, num_oeps, bdc->num_eps);
+	/* allocate array of ep pointers */
+	bdc->bdc_ep_array = kcalloc(bdc->num_eps, sizeof(struct bdc_ep *),
+								GFP_KERNEL);
+	if (!bdc->bdc_ep_array)
+		goto fail;
+
+	dev_dbg(bdc->dev, "Allocating sr report0\n");
+	if (setup_srr(bdc, 0))
+		goto fail;
+
+	return 0;
+fail:
+	dev_warn(bdc->dev, "Couldn't initialize memory\n");
+	bdc_mem_free(bdc);
+
+	return -ENOMEM;
+}
+
+/* opposite to bdc_hw_init */
+static void bdc_hw_exit(struct bdc *bdc)
+{
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	bdc_mem_free(bdc);
+}
+
+/* Initialize the bdc HW and memory */
+static int bdc_hw_init(struct bdc *bdc)
+{
+	int ret;
+
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	ret = bdc_reset(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "err resetting bdc abort bdc init%d\n", ret);
+		return ret;
+	}
+	ret = bdc_mem_alloc(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "Mem alloc failed, aborting\n");
+		return -ENOMEM;
+	}
+	bdc_mem_init(bdc, 0);
+	bdc_dbg_regs(bdc);
+	dev_dbg(bdc->dev, "HW Init done\n");
+
+	return 0;
+}
+
+static int bdc_probe(struct platform_device *pdev)
+{
+	struct bdc *bdc;
+	struct resource *res;
+	int ret = -ENOMEM;
+	int irq;
+	u32 temp;
+	struct device *dev = &pdev->dev;
+
+	dev_dbg(dev, "%s()\n", __func__);
+	bdc = devm_kzalloc(dev, sizeof(*bdc), GFP_KERNEL);
+	if (!bdc)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	bdc->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(bdc->regs)) {
+		dev_err(dev, "ioremap error\n");
+		return -ENOMEM;
+	}
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(dev, "platform_get_irq failed:%d\n", irq);
+		return irq;
+	}
+	spin_lock_init(&bdc->lock);
+	platform_set_drvdata(pdev, bdc);
+	bdc->irq = irq;
+	bdc->dev = dev;
+	dev_dbg(bdc->dev, "bdc->regs: %p irq=%d\n", bdc->regs, bdc->irq);
+
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	if ((temp & BDC_P64) &&
+			!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) {
+		dev_dbg(bdc->dev, "Using 64-bit address\n");
+	} else {
+		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+		if (ret) {
+			dev_err(bdc->dev, "No suitable DMA config available, abort\n");
+			return -ENOTSUPP;
+		}
+		dev_dbg(bdc->dev, "Using 32-bit address\n");
+	}
+	ret = bdc_hw_init(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "BDC init failure:%d\n", ret);
+		return ret;
+	}
+	ret = bdc_udc_init(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "BDC Gadget init failure:%d\n", ret);
+		goto cleanup;
+	}
+	return 0;
+
+cleanup:
+	bdc_hw_exit(bdc);
+
+	return ret;
+}
+
+static int bdc_remove(struct platform_device *pdev)
+{
+	struct bdc *bdc;
+
+	bdc  = platform_get_drvdata(pdev);
+	dev_dbg(bdc->dev, "%s ()\n", __func__);
+	bdc_udc_exit(bdc);
+	bdc_hw_exit(bdc);
+
+	return 0;
+}
+
+static int bdc_resume(struct platform_device *pdev)
+{
+	struct bdc *bdc = platform_get_drvdata(pdev);
+	int ret;
+
+	ret = bdc_reinit(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "err in bdc reinit\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id bdc_of_match[] = {
+	{ .compatible = "brcm,bdc-udc-v0.16" },
+	{ .compatible = "brcm,bdc-udc" },
+	{ .compatible = "brcm,bdc-udc-v2" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver bdc_driver = {
+	.driver		= {
+		.name	= BRCM_BDC_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table	= bdc_of_match,
+	},
+	.probe		= bdc_probe,
+	.remove		= bdc_remove,
+	.resume		= bdc_resume,
+};
+
+module_platform_driver(bdc_driver);
+MODULE_AUTHOR("Ashwini Pahuja <ashwini.linux@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION(BRCM_BDC_DESC);
diff --git a/drivers/usb/gadget/bdc/bdc_dbg.c b/drivers/usb/gadget/bdc/bdc_dbg.c
new file mode 100644
index 000000000000..ac98f6f681b7
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_dbg.c
@@ -0,0 +1,123 @@
+/*
+ * bdc_dbg.c - BRCM BDC USB3.0 device controller debug functions
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include "bdc.h"
+#include "bdc_dbg.h"
+
+void bdc_dbg_regs(struct bdc *bdc)
+{
+	u32 temp;
+
+	dev_vdbg(bdc->dev, "bdc->regs:%p\n", bdc->regs);
+	temp = bdc_readl(bdc->regs, BDC_BDCCFG0);
+	dev_vdbg(bdc->dev, "bdccfg0:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_BDCCFG1);
+	dev_vdbg(bdc->dev, "bdccfg1:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_BDCCAP0);
+	dev_vdbg(bdc->dev, "bdccap0:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_BDCCAP1);
+	dev_vdbg(bdc->dev, "bdccap1:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_USPC);
+	dev_vdbg(bdc->dev, "uspc:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_DVCSA);
+	dev_vdbg(bdc->dev, "dvcsa:0x%08x\n", temp);
+	temp = bdc_readl(bdc->regs, BDC_DVCSB);
+	dev_vdbg(bdc->dev, "dvcsb:0x%x08\n", temp);
+}
+
+void bdc_dump_epsts(struct bdc *bdc)
+{
+	u32 temp;
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS0);
+	dev_vdbg(bdc->dev, "BDC_EPSTS0:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS1);
+	dev_vdbg(bdc->dev, "BDC_EPSTS1:0x%x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS2);
+	dev_vdbg(bdc->dev, "BDC_EPSTS2:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS3);
+	dev_vdbg(bdc->dev, "BDC_EPSTS3:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS4);
+	dev_vdbg(bdc->dev, "BDC_EPSTS4:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS5);
+	dev_vdbg(bdc->dev, "BDC_EPSTS5:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS6);
+	dev_vdbg(bdc->dev, "BDC_EPSTS6:0x%08x\n", temp);
+
+	temp = bdc_readl(bdc->regs, BDC_EPSTS7);
+	dev_vdbg(bdc->dev, "BDC_EPSTS7:0x%08x\n", temp);
+}
+
+void bdc_dbg_srr(struct bdc *bdc, u32 srr_num)
+{
+	struct bdc_sr *sr;
+	dma_addr_t addr;
+	int i;
+
+	sr = bdc->srr.sr_bds;
+	addr = bdc->srr.dma_addr;
+	dev_vdbg(bdc->dev, "bdc_dbg_srr sr:%p dqp_index:%d\n",
+						sr, bdc->srr.dqp_index);
+	for (i = 0; i < NUM_SR_ENTRIES; i++) {
+		sr = &bdc->srr.sr_bds[i];
+		dev_vdbg(bdc->dev, "%llx %08x %08x %08x %08x\n",
+					(unsigned long long)addr,
+					le32_to_cpu(sr->offset[0]),
+					le32_to_cpu(sr->offset[1]),
+					le32_to_cpu(sr->offset[2]),
+					le32_to_cpu(sr->offset[3]));
+		addr += sizeof(*sr);
+	}
+}
+
+void bdc_dbg_bd_list(struct bdc *bdc, struct bdc_ep *ep)
+{
+	struct bd_list *bd_list = &ep->bd_list;
+	struct bd_table *bd_table;
+	struct bdc_bd *bd;
+	int tbi, bdi, gbdi;
+	dma_addr_t dma;
+
+	gbdi = 0;
+	dev_vdbg(bdc->dev,
+		"Dump bd list for %s epnum:%d\n",
+		ep->name, ep->ep_num);
+
+	dev_vdbg(bdc->dev,
+		"tabs:%d max_bdi:%d eqp_bdi:%d hwd_bdi:%d num_bds_table:%d\n",
+		bd_list->num_tabs, bd_list->max_bdi, bd_list->eqp_bdi,
+		bd_list->hwd_bdi, bd_list->num_bds_table);
+
+	for (tbi = 0; tbi < bd_list->num_tabs; tbi++) {
+		bd_table = bd_list->bd_table_array[tbi];
+		for (bdi = 0; bdi < bd_list->num_bds_table; bdi++) {
+			bd =  bd_table->start_bd + bdi;
+			dma = bd_table->dma + (sizeof(struct bdc_bd) * bdi);
+			dev_vdbg(bdc->dev,
+				"tbi:%2d bdi:%2d gbdi:%2d virt:%p phys:%llx %08x %08x %08x %08x\n",
+				tbi, bdi, gbdi++, bd, (unsigned long long)dma,
+				le32_to_cpu(bd->offset[0]),
+				le32_to_cpu(bd->offset[1]),
+				le32_to_cpu(bd->offset[2]),
+				le32_to_cpu(bd->offset[3]));
+		}
+		dev_vdbg(bdc->dev, "\n\n");
+	}
+}
diff --git a/drivers/usb/gadget/bdc/bdc_dbg.h b/drivers/usb/gadget/bdc/bdc_dbg.h
new file mode 100644
index 000000000000..338a6c701315
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_dbg.h
@@ -0,0 +1,37 @@
+/*
+ * bdc_dbg.h - header for the BDC debug functions
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __LINUX_BDC_DBG_H__
+#define __LINUX_BDC_DBG_H__
+
+#include "bdc.h"
+
+#ifdef CONFIG_USB_GADGET_VERBOSE
+void bdc_dbg_bd_list(struct bdc *, struct bdc_ep*);
+void bdc_dbg_srr(struct bdc *, u32);
+void bdc_dbg_regs(struct bdc *);
+void bdc_dump_epsts(struct bdc *);
+#else
+static inline void bdc_dbg_regs(struct bdc *bdc)
+{ }
+
+static inline void bdc_dbg_srr(struct bdc *bdc, u32 srr_num)
+{ }
+
+static inline void bdc_dbg_bd_list(struct bdc *bdc, struct bdc_ep *ep)
+{ }
+
+static inline void bdc_dump_epsts(struct bdc *bdc)
+{ }
+#endif /* CONFIG_USB_GADGET_VERBOSE */
+#endif /* __LINUX_BDC_DBG_H__ */
diff --git a/drivers/usb/gadget/bdc/bdc_ep.c b/drivers/usb/gadget/bdc/bdc_ep.c
new file mode 100644
index 000000000000..e5d1a1355da8
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_ep.c
@@ -0,0 +1,2025 @@
+/*
+ * bdc_ep.c - BRCM BDC USB3.0 device controller endpoint related functions
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * Based on drivers under drivers/usb/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/dmapool.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/unaligned.h>
+#include <linux/platform_device.h>
+#include <linux/usb/composite.h>
+
+#include "bdc.h"
+#include "bdc_ep.h"
+#include "bdc_cmd.h"
+#include "bdc_dbg.h"
+
+static const char * const ep0_state_string[] =  {
+	"WAIT_FOR_SETUP",
+	"WAIT_FOR_DATA_START",
+	"WAIT_FOR_DATA_XMIT",
+	"WAIT_FOR_STATUS_START",
+	"WAIT_FOR_STATUS_XMIT",
+	"STATUS_PENDING"
+};
+
+/* Free the bdl during ep disable */
+static void ep_bd_list_free(struct bdc_ep *ep, u32 num_tabs)
+{
+	struct bd_list *bd_list = &ep->bd_list;
+	struct bdc *bdc = ep->bdc;
+	struct bd_table *bd_table;
+	int index;
+
+	dev_dbg(bdc->dev, "%s ep:%s num_tabs:%d\n",
+				 __func__, ep->name, num_tabs);
+
+	if (!bd_list->bd_table_array) {
+		dev_dbg(bdc->dev, "%s already freed\n", ep->name);
+		return;
+	}
+	for (index = 0; index < num_tabs; index++) {
+		/*
+		 * check if the bd_table struct is allocated ?
+		 * if yes, then check if bd memory has been allocated, then
+		 * free the dma_pool and also the bd_table struct memory
+		*/
+		bd_table = bd_list->bd_table_array[index];
+		dev_dbg(bdc->dev, "bd_table:%p index:%d\n", bd_table, index);
+		if (!bd_table) {
+			dev_dbg(bdc->dev, "bd_table not allocated\n");
+			continue;
+		}
+		if (!bd_table->start_bd) {
+			dev_dbg(bdc->dev, "bd dma pool not allocted\n");
+			continue;
+		}
+
+		dev_dbg(bdc->dev,
+				"Free dma pool start_bd:%p dma:%llx\n",
+				bd_table->start_bd,
+				(unsigned long long)bd_table->dma);
+
+		dma_pool_free(bdc->bd_table_pool,
+				bd_table->start_bd,
+				bd_table->dma);
+		/* Free the bd_table structure */
+		kfree(bd_table);
+	}
+	/* Free the bd table array */
+	kfree(ep->bd_list.bd_table_array);
+}
+
+/*
+ * chain the tables, by insteting a chain bd at the end of prev_table, pointing
+ * to next_table
+ */
+static inline void chain_table(struct bd_table *prev_table,
+					struct bd_table *next_table,
+					u32 bd_p_tab)
+{
+	/* Chain the prev table to next table */
+	prev_table->start_bd[bd_p_tab-1].offset[0] =
+				cpu_to_le32(lower_32_bits(next_table->dma));
+
+	prev_table->start_bd[bd_p_tab-1].offset[1] =
+				cpu_to_le32(upper_32_bits(next_table->dma));
+
+	prev_table->start_bd[bd_p_tab-1].offset[2] =
+				0x0;
+
+	prev_table->start_bd[bd_p_tab-1].offset[3] =
+				cpu_to_le32(MARK_CHAIN_BD);
+}
+
+/* Allocate the bdl for ep, during config ep */
+static int ep_bd_list_alloc(struct bdc_ep *ep)
+{
+	struct bd_table *prev_table = NULL;
+	int index, num_tabs, bd_p_tab;
+	struct bdc *bdc = ep->bdc;
+	struct bd_table *bd_table;
+	dma_addr_t dma;
+
+	if (usb_endpoint_xfer_isoc(ep->desc))
+		num_tabs = NUM_TABLES_ISOCH;
+	else
+		num_tabs = NUM_TABLES;
+
+	bd_p_tab = NUM_BDS_PER_TABLE;
+	/* if there is only 1 table in bd list then loop chain to self */
+	dev_dbg(bdc->dev,
+		"%s ep:%p num_tabs:%d\n",
+		__func__, ep, num_tabs);
+
+	/* Allocate memory for table array */
+	ep->bd_list.bd_table_array = kzalloc(
+					num_tabs * sizeof(struct bd_table *),
+					GFP_ATOMIC);
+	if (!ep->bd_list.bd_table_array)
+		return -ENOMEM;
+
+	/* Allocate memory for each table */
+	for (index = 0; index < num_tabs; index++) {
+		/* Allocate memory for bd_table structure */
+		bd_table = kzalloc(sizeof(struct bd_table), GFP_ATOMIC);
+		if (!bd_table)
+			goto fail;
+
+		bd_table->start_bd = dma_pool_alloc(bdc->bd_table_pool,
+							GFP_ATOMIC,
+							&dma);
+		if (!bd_table->start_bd)
+			goto fail;
+
+		bd_table->dma = dma;
+
+		dev_dbg(bdc->dev,
+			"index:%d start_bd:%p dma=%08llx prev_table:%p\n",
+			index, bd_table->start_bd,
+			(unsigned long long)bd_table->dma, prev_table);
+
+		ep->bd_list.bd_table_array[index] = bd_table;
+		memset(bd_table->start_bd, 0, bd_p_tab * sizeof(struct bdc_bd));
+		if (prev_table)
+			chain_table(prev_table, bd_table, bd_p_tab);
+
+		prev_table = bd_table;
+	}
+	chain_table(prev_table, ep->bd_list.bd_table_array[0], bd_p_tab);
+	/* Memory allocation is successful, now init the internal fields */
+	ep->bd_list.num_tabs = num_tabs;
+	ep->bd_list.max_bdi  = (num_tabs * bd_p_tab) - 1;
+	ep->bd_list.num_tabs = num_tabs;
+	ep->bd_list.num_bds_table = bd_p_tab;
+	ep->bd_list.eqp_bdi = 0;
+	ep->bd_list.hwd_bdi = 0;
+
+	return 0;
+fail:
+	/* Free the bd_table_array, bd_table struct, bd's */
+	ep_bd_list_free(ep, num_tabs);
+
+	return -ENOMEM;
+}
+
+/* returns how many bd's are need for this transfer */
+static inline int bd_needed_req(struct bdc_req *req)
+{
+	int bd_needed = 0;
+	int remaining;
+
+	/* 1 bd needed for 0 byte transfer */
+	if (req->usb_req.length == 0)
+		return 1;
+
+	/* remaining bytes after tranfering all max BD size BD's */
+	remaining = req->usb_req.length % BD_MAX_BUFF_SIZE;
+	if (remaining)
+		bd_needed++;
+
+	/* How many maximum BUFF size BD's ? */
+	remaining = req->usb_req.length / BD_MAX_BUFF_SIZE;
+	bd_needed += remaining;
+
+	return bd_needed;
+}
+
+/* returns the bd index(bdi) corresponding to bd dma address */
+static int bd_add_to_bdi(struct bdc_ep *ep, dma_addr_t bd_dma_addr)
+{
+	struct bd_list *bd_list = &ep->bd_list;
+	dma_addr_t dma_first_bd, dma_last_bd;
+	struct bdc *bdc = ep->bdc;
+	struct bd_table *bd_table;
+	bool found = false;
+	int tbi, bdi;
+
+	dma_first_bd = dma_last_bd = 0;
+	dev_dbg(bdc->dev, "%s  %llx\n",
+			__func__, (unsigned long long)bd_dma_addr);
+	/*
+	 * Find in which table this bd_dma_addr belongs?, go through the table
+	 * array and compare addresses of first and last address of bd of each
+	 * table
+	 */
+	for (tbi = 0; tbi < bd_list->num_tabs; tbi++) {
+		bd_table = bd_list->bd_table_array[tbi];
+		dma_first_bd = bd_table->dma;
+		dma_last_bd = bd_table->dma +
+					(sizeof(struct bdc_bd) *
+					(bd_list->num_bds_table - 1));
+		dev_dbg(bdc->dev, "dma_first_bd:%llx dma_last_bd:%llx\n",
+					(unsigned long long)dma_first_bd,
+					(unsigned long long)dma_last_bd);
+		if (bd_dma_addr >= dma_first_bd && bd_dma_addr <= dma_last_bd) {
+			found = true;
+			break;
+		}
+	}
+	if (unlikely(!found)) {
+		dev_err(bdc->dev, "%s FATAL err, bd not found\n", __func__);
+		return -EINVAL;
+	}
+	/* Now we know the table, find the bdi */
+	bdi = (bd_dma_addr - dma_first_bd) / sizeof(struct bdc_bd);
+
+	/* return the global bdi, to compare with ep eqp_bdi */
+	return (bdi + (tbi * bd_list->num_bds_table));
+}
+
+/* returns the table index(tbi) of the given bdi */
+static int bdi_to_tbi(struct bdc_ep *ep, int bdi)
+{
+	int tbi;
+
+	tbi = bdi / ep->bd_list.num_bds_table;
+	dev_vdbg(ep->bdc->dev,
+		"bdi:%d num_bds_table:%d tbi:%d\n",
+		bdi, ep->bd_list.num_bds_table, tbi);
+
+	return tbi;
+}
+
+/* Find the bdi last bd in the transfer */
+static inline int find_end_bdi(struct bdc_ep *ep, int next_hwd_bdi)
+{
+	int end_bdi;
+
+	end_bdi = next_hwd_bdi - 1;
+	if (end_bdi < 0)
+		end_bdi = ep->bd_list.max_bdi - 1;
+	 else if ((end_bdi % (ep->bd_list.num_bds_table-1)) == 0)
+		end_bdi--;
+
+	return end_bdi;
+}
+
+/*
+ * How many transfer bd's are available on this ep bdl, chain bds are not
+ * counted in available bds
+ */
+static int bd_available_ep(struct bdc_ep *ep)
+{
+	struct bd_list *bd_list = &ep->bd_list;
+	int available1, available2;
+	struct bdc *bdc = ep->bdc;
+	int chain_bd1, chain_bd2;
+	int available_bd = 0;
+
+	available1 = available2 = chain_bd1 = chain_bd2 = 0;
+	/* if empty then we have all bd's available - number of chain bd's */
+	if (bd_list->eqp_bdi == bd_list->hwd_bdi)
+		return bd_list->max_bdi - bd_list->num_tabs;
+
+	/*
+	 * Depending upon where eqp and dqp pointers are, caculate number
+	 * of avaialble bd's
+	 */
+	if (bd_list->hwd_bdi < bd_list->eqp_bdi) {
+		/* available bd's are from eqp..max_bds + 0..dqp - chain_bds */
+		available1 = bd_list->max_bdi - bd_list->eqp_bdi;
+		available2 = bd_list->hwd_bdi;
+		chain_bd1 = available1 / bd_list->num_bds_table;
+		chain_bd2 = available2 / bd_list->num_bds_table;
+		dev_vdbg(bdc->dev, "chain_bd1:%d chain_bd2:%d\n",
+						chain_bd1, chain_bd2);
+		available_bd = available1 + available2 - chain_bd1 - chain_bd2;
+	} else {
+		/* available bd's are from eqp..dqp - number of chain bd's */
+		available1 = bd_list->hwd_bdi -  bd_list->eqp_bdi;
+		/* if gap between eqp and dqp is less than NUM_BDS_PER_TABLE */
+		if ((bd_list->hwd_bdi - bd_list->eqp_bdi)
+					<= bd_list->num_bds_table) {
+			/* If there any chain bd in between */
+			if (!(bdi_to_tbi(ep, bd_list->hwd_bdi)
+					== bdi_to_tbi(ep, bd_list->eqp_bdi))) {
+				available_bd = available1 - 1;
+			}
+		} else {
+			chain_bd1 = available1 / bd_list->num_bds_table;
+			available_bd = available1 - chain_bd1;
+		}
+	}
+	/*
+	 * we need to keep one extra bd to check if ring is full or empty so
+	 * reduce by 1
+	 */
+	available_bd--;
+	dev_vdbg(bdc->dev, "available_bd:%d\n", available_bd);
+
+	return available_bd;
+}
+
+/* Notify the hardware after queueing the bd to bdl */
+void bdc_notify_xfr(struct bdc *bdc, u32 epnum)
+{
+	struct bdc_ep *ep = bdc->bdc_ep_array[epnum];
+
+	dev_vdbg(bdc->dev, "%s epnum:%d\n", __func__, epnum);
+	/*
+	 * We don't have anyway to check if ep state is running,
+	 * except the software flags.
+	 */
+	if (unlikely(ep->flags & BDC_EP_STOP))
+		ep->flags &= ~BDC_EP_STOP;
+
+	bdc_writel(bdc->regs, BDC_XSFNTF, epnum);
+}
+
+/* returns the bd corresponding to bdi */
+static struct bdc_bd *bdi_to_bd(struct bdc_ep *ep, int bdi)
+{
+	int tbi = bdi_to_tbi(ep, bdi);
+	int local_bdi = 0;
+
+	local_bdi = bdi - (tbi * ep->bd_list.num_bds_table);
+	dev_vdbg(ep->bdc->dev,
+		"%s bdi:%d local_bdi:%d\n",
+		 __func__, bdi, local_bdi);
+
+	return (ep->bd_list.bd_table_array[tbi]->start_bd + local_bdi);
+}
+
+/* Advance the enqueue pointer */
+static void ep_bdlist_eqp_adv(struct bdc_ep *ep)
+{
+	ep->bd_list.eqp_bdi++;
+	/* if it's chain bd, then move to next */
+	if (((ep->bd_list.eqp_bdi + 1) % ep->bd_list.num_bds_table) == 0)
+		ep->bd_list.eqp_bdi++;
+
+	/* if the eqp is pointing to last + 1 then move back to 0 */
+	if (ep->bd_list.eqp_bdi == (ep->bd_list.max_bdi + 1))
+		ep->bd_list.eqp_bdi = 0;
+}
+
+/* Setup the first bd for ep0 transfer */
+static int setup_first_bd_ep0(struct bdc *bdc, struct bdc_req *req, u32 *dword3)
+{
+	u16 wValue;
+	u32 req_len;
+
+	req->ep->dir = 0;
+	req_len = req->usb_req.length;
+	switch (bdc->ep0_state) {
+	case WAIT_FOR_DATA_START:
+		*dword3 |= BD_TYPE_DS;
+		if (bdc->setup_pkt.bRequestType & USB_DIR_IN)
+			*dword3 |= BD_DIR_IN;
+
+		/* check if zlp will be needed */
+		wValue = le16_to_cpu(bdc->setup_pkt.wValue);
+		if ((wValue > req_len) &&
+				(req_len % bdc->gadget.ep0->maxpacket == 0)) {
+			dev_dbg(bdc->dev, "ZLP needed wVal:%d len:%d MaxP:%d\n",
+					wValue, req_len,
+					bdc->gadget.ep0->maxpacket);
+			bdc->zlp_needed = true;
+		}
+		break;
+
+	case WAIT_FOR_STATUS_START:
+		*dword3 |= BD_TYPE_SS;
+		if (!le16_to_cpu(bdc->setup_pkt.wLength) ||
+				!(bdc->setup_pkt.bRequestType & USB_DIR_IN))
+			*dword3 |= BD_DIR_IN;
+		break;
+	default:
+		dev_err(bdc->dev,
+			"Unknown ep0 state for queueing bd ep0_state:%s\n",
+			ep0_state_string[bdc->ep0_state]);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Setup the bd dma descriptor for a given request */
+static int setup_bd_list_xfr(struct bdc *bdc, struct bdc_req *req, int num_bds)
+{
+	dma_addr_t buf_add = req->usb_req.dma;
+	u32 maxp, tfs, dword2, dword3;
+	struct bd_transfer *bd_xfr;
+	struct bd_list *bd_list;
+	struct bdc_ep *ep;
+	struct bdc_bd *bd;
+	int ret, bdnum;
+	u32 req_len;
+
+	ep = req->ep;
+	bd_list = &ep->bd_list;
+	bd_xfr = &req->bd_xfr;
+	bd_xfr->req = req;
+	bd_xfr->start_bdi = bd_list->eqp_bdi;
+	bd = bdi_to_bd(ep, bd_list->eqp_bdi);
+	req_len = req->usb_req.length;
+	maxp = usb_endpoint_maxp(ep->desc) & 0x7ff;
+	tfs = roundup(req->usb_req.length, maxp);
+	tfs = tfs/maxp;
+	dev_vdbg(bdc->dev, "%s ep:%s num_bds:%d tfs:%d r_len:%d bd:%p\n",
+				__func__, ep->name, num_bds, tfs, req_len, bd);
+
+	for (bdnum = 0; bdnum < num_bds; bdnum++) {
+		dword2 = dword3 = 0;
+		/* First bd */
+		if (!bdnum) {
+			dword3 |= BD_SOT|BD_SBF|(tfs<<BD_TFS_SHIFT);
+			dword2 |= BD_LTF;
+			/* format of first bd for ep0 is different than other */
+			if (ep->ep_num == 1) {
+				ret = setup_first_bd_ep0(bdc, req, &dword3);
+				if (ret)
+					return ret;
+			}
+		}
+		if (!req->ep->dir)
+			dword3 |= BD_ISP;
+
+		if (req_len > BD_MAX_BUFF_SIZE) {
+			dword2 |= BD_MAX_BUFF_SIZE;
+			req_len -= BD_MAX_BUFF_SIZE;
+		} else {
+			/* this should be the last bd */
+			dword2 |= req_len;
+			dword3 |= BD_IOC;
+			dword3 |= BD_EOT;
+		}
+		/* Currently only 1 INT target is supported */
+		dword2 |= BD_INTR_TARGET(0);
+		bd = bdi_to_bd(ep, ep->bd_list.eqp_bdi);
+		if (unlikely(!bd)) {
+			dev_err(bdc->dev, "Err bd pointing to wrong addr\n");
+			return -EINVAL;
+		}
+		/* write bd */
+		bd->offset[0] = cpu_to_le32(lower_32_bits(buf_add));
+		bd->offset[1] = cpu_to_le32(upper_32_bits(buf_add));
+		bd->offset[2] = cpu_to_le32(dword2);
+		bd->offset[3] = cpu_to_le32(dword3);
+		/* advance eqp pointer */
+		ep_bdlist_eqp_adv(ep);
+		/* advance the buff pointer */
+		buf_add += BD_MAX_BUFF_SIZE;
+		dev_vdbg(bdc->dev, "buf_add:%08llx req_len:%d bd:%p eqp:%d\n",
+				(unsigned long long)buf_add, req_len, bd,
+							ep->bd_list.eqp_bdi);
+		bd = bdi_to_bd(ep, ep->bd_list.eqp_bdi);
+		bd->offset[3] = cpu_to_le32(BD_SBF);
+	}
+	/* clear the STOP BD fetch bit from the first bd of this xfr */
+	bd = bdi_to_bd(ep, bd_xfr->start_bdi);
+	bd->offset[3] &= cpu_to_le32(~BD_SBF);
+	/* the new eqp will be next hw dqp */
+	bd_xfr->num_bds  = num_bds;
+	bd_xfr->next_hwd_bdi = ep->bd_list.eqp_bdi;
+	/* everything is written correctly before notifying the HW */
+	wmb();
+
+	return 0;
+}
+
+/* Queue the xfr */
+static int bdc_queue_xfr(struct bdc *bdc, struct bdc_req *req)
+{
+	int num_bds, bd_available;
+	struct bdc_ep *ep;
+	int ret;
+
+	ep = req->ep;
+	dev_dbg(bdc->dev, "%s req:%p\n", __func__, req);
+	dev_dbg(bdc->dev, "eqp_bdi:%d hwd_bdi:%d\n",
+			ep->bd_list.eqp_bdi, ep->bd_list.hwd_bdi);
+
+	num_bds =  bd_needed_req(req);
+	bd_available = bd_available_ep(ep);
+
+	/* how many bd's are avaialble on ep */
+	if (num_bds > bd_available)
+		return -ENOMEM;
+
+	ret = setup_bd_list_xfr(bdc, req, num_bds);
+	if (ret)
+		return ret;
+	list_add_tail(&req->queue, &ep->queue);
+	bdc_dbg_bd_list(bdc, ep);
+	bdc_notify_xfr(bdc, ep->ep_num);
+
+	return 0;
+}
+
+/* callback to gadget layer when xfr completes */
+static void bdc_req_complete(struct bdc_ep *ep, struct bdc_req *req,
+						int status)
+{
+	struct bdc *bdc = ep->bdc;
+
+	if (req == NULL  || &req->queue == NULL || &req->usb_req == NULL)
+		return;
+
+	dev_dbg(bdc->dev, "%s ep:%s status:%d\n", __func__, ep->name, status);
+	list_del(&req->queue);
+	req->usb_req.status = status;
+	usb_gadget_unmap_request(&bdc->gadget, &req->usb_req, ep->dir);
+	if (req->usb_req.complete) {
+		spin_unlock(&bdc->lock);
+		usb_gadget_giveback_request(&ep->usb_ep, &req->usb_req);
+		spin_lock(&bdc->lock);
+	}
+}
+
+/* Disable the endpoint */
+int bdc_ep_disable(struct bdc_ep *ep)
+{
+	struct bdc_req *req;
+	struct bdc *bdc;
+	int ret;
+
+	ret = 0;
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s() ep->ep_num=%d\n", __func__, ep->ep_num);
+	/* Stop the endpoint */
+	ret = bdc_stop_ep(bdc, ep->ep_num);
+
+	/*
+	 * Intentionally don't check the ret value of stop, it can fail in
+	 * disconnect scenarios, continue with dconfig
+	 */
+	/* de-queue any pending requests */
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct bdc_req,
+				queue);
+		bdc_req_complete(ep, req, -ESHUTDOWN);
+	}
+	/* deconfigure the endpoint */
+	ret = bdc_dconfig_ep(bdc, ep);
+	if (ret)
+		dev_warn(bdc->dev,
+			"dconfig fail but continue with memory free");
+
+	ep->flags = 0;
+	/* ep0 memory is not freed, but reused on next connect sr */
+	if (ep->ep_num == 1)
+		return 0;
+
+	/* Free the bdl memory */
+	ep_bd_list_free(ep, ep->bd_list.num_tabs);
+	ep->desc = NULL;
+	ep->comp_desc = NULL;
+	ep->usb_ep.desc = NULL;
+	ep->ep_type = 0;
+
+	return ret;
+}
+
+/* Enable the ep */
+int bdc_ep_enable(struct bdc_ep *ep)
+{
+	struct bdc *bdc;
+	int ret = 0;
+
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s NUM_TABLES:%d %d\n",
+					__func__, NUM_TABLES, NUM_TABLES_ISOCH);
+
+	ret = ep_bd_list_alloc(ep);
+	if (ret) {
+		dev_err(bdc->dev, "ep bd list allocation failed:%d\n", ret);
+		return -ENOMEM;
+	}
+	bdc_dbg_bd_list(bdc, ep);
+	/* only for ep0: config ep is called for ep0 from connect event */
+	ep->flags |= BDC_EP_ENABLED;
+	if (ep->ep_num == 1)
+		return ret;
+
+	/* Issue a configure endpoint command */
+	ret = bdc_config_ep(bdc, ep);
+	if (ret)
+		return ret;
+
+	ep->usb_ep.maxpacket = usb_endpoint_maxp(ep->desc);
+	ep->usb_ep.desc = ep->desc;
+	ep->usb_ep.comp_desc = ep->comp_desc;
+	ep->ep_type = usb_endpoint_type(ep->desc);
+	ep->flags |= BDC_EP_ENABLED;
+
+	return 0;
+}
+
+/* EP0 related code */
+
+/* Queue a status stage BD */
+static int ep0_queue_status_stage(struct bdc *bdc)
+{
+	struct bdc_req *status_req;
+	struct bdc_ep *ep;
+
+	status_req = &bdc->status_req;
+	ep = bdc->bdc_ep_array[1];
+	status_req->ep = ep;
+	status_req->usb_req.length = 0;
+	status_req->usb_req.status = -EINPROGRESS;
+	status_req->usb_req.actual = 0;
+	status_req->usb_req.complete = NULL;
+	bdc_queue_xfr(bdc, status_req);
+
+	return 0;
+}
+
+/* Queue xfr on ep0 */
+static int ep0_queue(struct bdc_ep *ep, struct bdc_req *req)
+{
+	struct bdc *bdc;
+	int ret;
+
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	req->usb_req.actual = 0;
+	req->usb_req.status = -EINPROGRESS;
+	req->epnum = ep->ep_num;
+
+	if (bdc->delayed_status) {
+		bdc->delayed_status = false;
+		/* if status stage was delayed? */
+		if (bdc->ep0_state == WAIT_FOR_STATUS_START) {
+			/* Queue a status stage BD */
+			ep0_queue_status_stage(bdc);
+			bdc->ep0_state = WAIT_FOR_STATUS_XMIT;
+			return 0;
+		}
+	} else {
+		/*
+		 * if delayed status is false and 0 length transfer is requested
+		 * i.e. for status stage of some setup request, then just
+		 * return from here the status stage is queued independently
+		 */
+		if (req->usb_req.length == 0)
+			return 0;
+
+	}
+	ret = usb_gadget_map_request(&bdc->gadget, &req->usb_req, ep->dir);
+	if (ret) {
+		dev_err(bdc->dev, "dma mapping failed %s\n", ep->name);
+		return ret;
+	}
+
+	return bdc_queue_xfr(bdc, req);
+}
+
+/* Queue data stage */
+static int ep0_queue_data_stage(struct bdc *bdc)
+{
+	struct usb_request *ep0_usb_req;
+	struct bdc_ep *ep;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	ep0_usb_req = &bdc->ep0_req.usb_req;
+	ep = bdc->bdc_ep_array[1];
+	bdc->ep0_req.ep = ep;
+	bdc->ep0_req.usb_req.complete = NULL;
+
+	return ep0_queue(ep, &bdc->ep0_req);
+}
+
+/* Queue req on ep */
+static int ep_queue(struct bdc_ep *ep, struct bdc_req *req)
+{
+	struct bdc *bdc;
+	int ret = 0;
+
+	if (!req || !ep || !ep->usb_ep.desc)
+		return -EINVAL;
+
+	bdc = ep->bdc;
+
+	req->usb_req.actual = 0;
+	req->usb_req.status = -EINPROGRESS;
+	req->epnum = ep->ep_num;
+
+	ret = usb_gadget_map_request(&bdc->gadget, &req->usb_req, ep->dir);
+	if (ret) {
+		dev_err(bdc->dev, "dma mapping failed\n");
+		return ret;
+	}
+
+	return bdc_queue_xfr(bdc, req);
+}
+
+/* Dequeue a request from ep */
+static int ep_dequeue(struct bdc_ep *ep, struct bdc_req *req)
+{
+	int start_bdi, end_bdi, tbi, eqp_bdi, curr_hw_dqpi;
+	bool start_pending, end_pending;
+	bool first_remove = false;
+	struct bdc_req *first_req;
+	struct bdc_bd *bd_start;
+	struct bd_table *table;
+	dma_addr_t next_bd_dma;
+	u64   deq_ptr_64 = 0;
+	struct bdc  *bdc;
+	u32    tmp_32;
+	int ret;
+
+	bdc = ep->bdc;
+	start_pending = end_pending = false;
+	eqp_bdi = ep->bd_list.eqp_bdi - 1;
+
+	if (eqp_bdi < 0)
+		eqp_bdi = ep->bd_list.max_bdi;
+
+	start_bdi = req->bd_xfr.start_bdi;
+	end_bdi = find_end_bdi(ep, req->bd_xfr.next_hwd_bdi);
+
+	dev_dbg(bdc->dev, "%s ep:%s start:%d end:%d\n",
+					__func__, ep->name, start_bdi, end_bdi);
+	dev_dbg(bdc->dev, "ep_dequeue ep=%p ep->desc=%p\n",
+						ep, (void *)ep->usb_ep.desc);
+	/* Stop the ep to see where the HW is ? */
+	ret = bdc_stop_ep(bdc, ep->ep_num);
+	/* if there is an issue with stopping ep, then no need to go further */
+	if (ret)
+		return 0;
+
+	/*
+	 * After endpoint is stopped, there can be 3 cases, the request
+	 * is processed, pending or in the middle of processing
+	 */
+
+	/* The current hw dequeue pointer */
+	tmp_32 = bdc_readl(bdc->regs, BDC_EPSTS0);
+	deq_ptr_64 = tmp_32;
+	tmp_32 = bdc_readl(bdc->regs, BDC_EPSTS1);
+	deq_ptr_64 |= ((u64)tmp_32 << 32);
+
+	/* we have the dma addr of next bd that will be fetched by hardware */
+	curr_hw_dqpi = bd_add_to_bdi(ep, deq_ptr_64);
+	if (curr_hw_dqpi < 0)
+		return curr_hw_dqpi;
+
+	/*
+	 * curr_hw_dqpi points to actual dqp of HW and HW owns bd's from
+	 * curr_hw_dqbdi..eqp_bdi.
+	 */
+
+	/* Check if start_bdi and end_bdi are in range of HW owned BD's */
+	if (curr_hw_dqpi > eqp_bdi) {
+		/* there is a wrap from last to 0 */
+		if (start_bdi >= curr_hw_dqpi || start_bdi <= eqp_bdi) {
+			start_pending = true;
+			end_pending = true;
+		} else if (end_bdi >= curr_hw_dqpi || end_bdi <= eqp_bdi) {
+				end_pending = true;
+		}
+	} else {
+		if (start_bdi >= curr_hw_dqpi) {
+			start_pending = true;
+			end_pending = true;
+		} else if (end_bdi >= curr_hw_dqpi) {
+			end_pending = true;
+		}
+	}
+	dev_dbg(bdc->dev,
+		"start_pending:%d end_pending:%d speed:%d\n",
+		start_pending, end_pending, bdc->gadget.speed);
+
+	/* If both start till end are processes, we cannot deq req */
+	if (!start_pending && !end_pending)
+		return -EINVAL;
+
+	/*
+	 * if ep_dequeue is called after disconnect then just return
+	 * success from here
+	 */
+	if (bdc->gadget.speed == USB_SPEED_UNKNOWN)
+		return 0;
+	tbi = bdi_to_tbi(ep, req->bd_xfr.next_hwd_bdi);
+	table = ep->bd_list.bd_table_array[tbi];
+	next_bd_dma =  table->dma +
+			sizeof(struct bdc_bd)*(req->bd_xfr.next_hwd_bdi -
+					tbi * ep->bd_list.num_bds_table);
+
+	first_req = list_first_entry(&ep->queue, struct bdc_req,
+			queue);
+
+	if (req == first_req)
+		first_remove = true;
+
+	/*
+	 * Due to HW limitation we need to bypadd chain bd's and issue ep_bla,
+	 * incase if start is pending this is the first request in the list
+	 * then issue ep_bla instead of marking as chain bd
+	 */
+	if (start_pending && !first_remove) {
+		/*
+		 * Mark the start bd as Chain bd, and point the chain
+		 * bd to next_bd_dma
+		 */
+		bd_start = bdi_to_bd(ep, start_bdi);
+		bd_start->offset[0] = cpu_to_le32(lower_32_bits(next_bd_dma));
+		bd_start->offset[1] = cpu_to_le32(upper_32_bits(next_bd_dma));
+		bd_start->offset[2] = 0x0;
+		bd_start->offset[3] = cpu_to_le32(MARK_CHAIN_BD);
+		bdc_dbg_bd_list(bdc, ep);
+	} else if (end_pending) {
+		/*
+		 * The transfer is stopped in the middle, move the
+		 * HW deq pointer to next_bd_dma
+		 */
+		ret = bdc_ep_bla(bdc, ep, next_bd_dma);
+		if (ret) {
+			dev_err(bdc->dev, "error in ep_bla:%d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/* Halt/Clear the ep based on value */
+static int ep_set_halt(struct bdc_ep *ep, u32 value)
+{
+	struct bdc *bdc;
+	int ret;
+
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s ep:%s value=%d\n", __func__, ep->name, value);
+
+	if (value) {
+		dev_dbg(bdc->dev, "Halt\n");
+		if (ep->ep_num == 1)
+			bdc->ep0_state = WAIT_FOR_SETUP;
+
+		ret = bdc_ep_set_stall(bdc, ep->ep_num);
+		if (ret)
+			dev_err(bdc->dev, "failed to %s STALL on %s\n",
+				value ? "set" : "clear", ep->name);
+		else
+			ep->flags |= BDC_EP_STALL;
+	} else {
+		/* Clear */
+		dev_dbg(bdc->dev, "Before Clear\n");
+		ret = bdc_ep_clear_stall(bdc, ep->ep_num);
+		if (ret)
+			dev_err(bdc->dev, "failed to %s STALL on %s\n",
+				value ? "set" : "clear", ep->name);
+		else
+			ep->flags &= ~BDC_EP_STALL;
+		dev_dbg(bdc->dev, "After  Clear\n");
+	}
+
+	return ret;
+}
+
+/* Free all the ep */
+void bdc_free_ep(struct bdc *bdc)
+{
+	struct bdc_ep *ep;
+	u8	epnum;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	for (epnum = 1; epnum < bdc->num_eps; epnum++) {
+		ep = bdc->bdc_ep_array[epnum];
+		if (!ep)
+			continue;
+
+		if (ep->flags & BDC_EP_ENABLED)
+			ep_bd_list_free(ep, ep->bd_list.num_tabs);
+
+		/* ep0 is not in this gadget list */
+		if (epnum != 1)
+			list_del(&ep->usb_ep.ep_list);
+
+		kfree(ep);
+	}
+}
+
+/* USB2 spec, section 7.1.20 */
+static int bdc_set_test_mode(struct bdc *bdc)
+{
+	u32 usb2_pm;
+
+	usb2_pm = bdc_readl(bdc->regs, BDC_USPPM2);
+	usb2_pm &= ~BDC_PTC_MASK;
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	switch (bdc->test_mode) {
+	case TEST_J:
+	case TEST_K:
+	case TEST_SE0_NAK:
+	case TEST_PACKET:
+	case TEST_FORCE_EN:
+		usb2_pm |= bdc->test_mode << 28;
+		break;
+	default:
+		return -EINVAL;
+	}
+	dev_dbg(bdc->dev, "usb2_pm=%08x", usb2_pm);
+	bdc_writel(bdc->regs, BDC_USPPM2, usb2_pm);
+
+	return 0;
+}
+
+/*
+ * Helper function to handle Transfer status report with status as either
+ * success or short
+ */
+static void handle_xsr_succ_status(struct bdc *bdc, struct bdc_ep *ep,
+							struct bdc_sr *sreport)
+{
+	int short_bdi, start_bdi, end_bdi, max_len_bds, chain_bds;
+	struct bd_list *bd_list = &ep->bd_list;
+	int actual_length, length_short;
+	struct bd_transfer *bd_xfr;
+	struct bdc_bd *short_bd;
+	struct bdc_req *req;
+	u64   deq_ptr_64 = 0;
+	int status = 0;
+	int sr_status;
+	u32    tmp_32;
+
+	dev_dbg(bdc->dev, "%s  ep:%p\n", __func__, ep);
+	bdc_dbg_srr(bdc, 0);
+	/* do not process thie sr if ignore flag is set */
+	if (ep->ignore_next_sr) {
+		ep->ignore_next_sr = false;
+		return;
+	}
+
+	if (unlikely(list_empty(&ep->queue))) {
+		dev_warn(bdc->dev, "xfr srr with no BD's queued\n");
+		return;
+	}
+	req = list_entry(ep->queue.next, struct bdc_req,
+			queue);
+
+	bd_xfr = &req->bd_xfr;
+	sr_status = XSF_STS(le32_to_cpu(sreport->offset[3]));
+
+	/*
+	 * sr_status is short and this transfer has more than 1 bd then it needs
+	 * special handling,  this is only applicable for bulk and ctrl
+	 */
+	if (sr_status == XSF_SHORT &&  bd_xfr->num_bds > 1) {
+		/*
+		 * This is multi bd xfr, lets see which bd
+		 * caused short transfer and how many bytes have been
+		 * transferred so far.
+		 */
+		tmp_32 = le32_to_cpu(sreport->offset[0]);
+		deq_ptr_64 = tmp_32;
+		tmp_32 = le32_to_cpu(sreport->offset[1]);
+		deq_ptr_64 |= ((u64)tmp_32 << 32);
+		short_bdi = bd_add_to_bdi(ep, deq_ptr_64);
+		if (unlikely(short_bdi < 0))
+			dev_warn(bdc->dev, "bd doesn't exist?\n");
+
+		start_bdi =  bd_xfr->start_bdi;
+		/*
+		 * We know the start_bdi and short_bdi, how many xfr
+		 * bds in between
+		 */
+		if (start_bdi <= short_bdi) {
+			max_len_bds = short_bdi - start_bdi;
+			if (max_len_bds <= bd_list->num_bds_table) {
+				if (!(bdi_to_tbi(ep, start_bdi) ==
+						bdi_to_tbi(ep, short_bdi)))
+					max_len_bds--;
+			} else {
+				chain_bds = max_len_bds/bd_list->num_bds_table;
+				max_len_bds -= chain_bds;
+			}
+		} else {
+			/* there is a wrap in the ring within a xfr */
+			chain_bds = (bd_list->max_bdi - start_bdi)/
+							bd_list->num_bds_table;
+			chain_bds += short_bdi/bd_list->num_bds_table;
+			max_len_bds = bd_list->max_bdi - start_bdi;
+			max_len_bds += short_bdi;
+			max_len_bds -= chain_bds;
+		}
+		/* max_len_bds is the number of full length bds */
+		end_bdi = find_end_bdi(ep, bd_xfr->next_hwd_bdi);
+		if (!(end_bdi == short_bdi))
+			ep->ignore_next_sr = true;
+
+		actual_length = max_len_bds * BD_MAX_BUFF_SIZE;
+		short_bd = bdi_to_bd(ep, short_bdi);
+		/* length queued */
+		length_short = le32_to_cpu(short_bd->offset[2]) & 0x1FFFFF;
+		/* actual length trensfered */
+		length_short -= SR_BD_LEN(le32_to_cpu(sreport->offset[2]));
+		actual_length += length_short;
+		req->usb_req.actual = actual_length;
+	} else {
+		req->usb_req.actual = req->usb_req.length -
+			SR_BD_LEN(le32_to_cpu(sreport->offset[2]));
+		dev_dbg(bdc->dev,
+			"len=%d actual=%d bd_xfr->next_hwd_bdi:%d\n",
+			req->usb_req.length, req->usb_req.actual,
+			bd_xfr->next_hwd_bdi);
+	}
+
+	/* Update the dequeue pointer */
+	ep->bd_list.hwd_bdi = bd_xfr->next_hwd_bdi;
+	if (req->usb_req.actual < req->usb_req.length) {
+		dev_dbg(bdc->dev, "short xfr on %d\n", ep->ep_num);
+		if (req->usb_req.short_not_ok)
+			status = -EREMOTEIO;
+	}
+	bdc_req_complete(ep, bd_xfr->req, status);
+}
+
+/* EP0 setup related packet handlers */
+
+/*
+ * Setup packet received, just store the packet and process on next DS or SS
+ * started SR
+ */
+void bdc_xsf_ep0_setup_recv(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	struct usb_ctrlrequest *setup_pkt;
+	u32 len;
+
+	dev_dbg(bdc->dev,
+		"%s ep0_state:%s\n",
+		__func__, ep0_state_string[bdc->ep0_state]);
+	/* Store received setup packet */
+	setup_pkt = &bdc->setup_pkt;
+	memcpy(setup_pkt, &sreport->offset[0], sizeof(*setup_pkt));
+	len = le16_to_cpu(setup_pkt->wLength);
+	if (!len)
+		bdc->ep0_state = WAIT_FOR_STATUS_START;
+	else
+		bdc->ep0_state = WAIT_FOR_DATA_START;
+
+
+	dev_dbg(bdc->dev,
+		"%s exit ep0_state:%s\n",
+		__func__, ep0_state_string[bdc->ep0_state]);
+}
+
+/* Stall ep0 */
+static void ep0_stall(struct bdc *bdc)
+{
+	struct bdc_ep	*ep = bdc->bdc_ep_array[1];
+	struct bdc_req *req;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	bdc->delayed_status = false;
+	ep_set_halt(ep, 1);
+
+	/* de-queue any pendig requests */
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct bdc_req,
+				queue);
+		bdc_req_complete(ep, req, -ESHUTDOWN);
+	}
+}
+
+/* SET_ADD handlers */
+static int ep0_set_address(struct bdc *bdc, struct usb_ctrlrequest *ctrl)
+{
+	enum usb_device_state state = bdc->gadget.state;
+	int ret = 0;
+	u32 addr;
+
+	addr = le16_to_cpu(ctrl->wValue);
+	dev_dbg(bdc->dev,
+		"%s addr:%d dev state:%d\n",
+		__func__, addr, state);
+
+	if (addr > 127)
+		return -EINVAL;
+
+	switch (state) {
+	case USB_STATE_DEFAULT:
+	case USB_STATE_ADDRESS:
+		/* Issue Address device command */
+		ret = bdc_address_device(bdc, addr);
+		if (ret)
+			return ret;
+
+		if (addr)
+			usb_gadget_set_state(&bdc->gadget, USB_STATE_ADDRESS);
+		else
+			usb_gadget_set_state(&bdc->gadget, USB_STATE_DEFAULT);
+
+		bdc->dev_addr = addr;
+		break;
+	default:
+		dev_warn(bdc->dev,
+			"SET Address in wrong device state %d\n",
+			state);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/* Handler for SET/CLEAR FEATURE requests for device */
+static int ep0_handle_feature_dev(struct bdc *bdc, u16 wValue,
+							u16 wIndex, bool set)
+{
+	enum usb_device_state state = bdc->gadget.state;
+	u32	usppms = 0;
+
+	dev_dbg(bdc->dev, "%s set:%d dev state:%d\n",
+					__func__, set, state);
+	switch (wValue) {
+	case USB_DEVICE_REMOTE_WAKEUP:
+		dev_dbg(bdc->dev, "USB_DEVICE_REMOTE_WAKEUP\n");
+		if (set)
+			bdc->devstatus |= REMOTE_WAKE_ENABLE;
+		else
+			bdc->devstatus &= ~REMOTE_WAKE_ENABLE;
+		break;
+
+	case USB_DEVICE_TEST_MODE:
+		dev_dbg(bdc->dev, "USB_DEVICE_TEST_MODE\n");
+		if ((wIndex & 0xFF) ||
+				(bdc->gadget.speed != USB_SPEED_HIGH) || !set)
+			return -EINVAL;
+
+		bdc->test_mode = wIndex >> 8;
+		break;
+
+	case USB_DEVICE_U1_ENABLE:
+		dev_dbg(bdc->dev, "USB_DEVICE_U1_ENABLE\n");
+
+		if (bdc->gadget.speed != USB_SPEED_SUPER ||
+						state != USB_STATE_CONFIGURED)
+			return -EINVAL;
+
+		usppms =  bdc_readl(bdc->regs, BDC_USPPMS);
+		if (set) {
+			/* clear previous u1t */
+			usppms &= ~BDC_U1T(BDC_U1T_MASK);
+			usppms |= BDC_U1T(U1_TIMEOUT);
+			usppms |= BDC_U1E | BDC_PORT_W1S;
+			bdc->devstatus |= (1 << USB_DEV_STAT_U1_ENABLED);
+		} else {
+			usppms &= ~BDC_U1E;
+			usppms |= BDC_PORT_W1S;
+			bdc->devstatus &= ~(1 << USB_DEV_STAT_U1_ENABLED);
+		}
+		bdc_writel(bdc->regs, BDC_USPPMS, usppms);
+		break;
+
+	case USB_DEVICE_U2_ENABLE:
+		dev_dbg(bdc->dev, "USB_DEVICE_U2_ENABLE\n");
+
+		if (bdc->gadget.speed != USB_SPEED_SUPER ||
+						state != USB_STATE_CONFIGURED)
+			return -EINVAL;
+
+		usppms = bdc_readl(bdc->regs, BDC_USPPMS);
+		if (set) {
+			usppms |= BDC_U2E;
+			usppms |= BDC_U2A;
+			bdc->devstatus |= (1 << USB_DEV_STAT_U2_ENABLED);
+		} else {
+			usppms &= ~BDC_U2E;
+			usppms &= ~BDC_U2A;
+			bdc->devstatus &= ~(1 << USB_DEV_STAT_U2_ENABLED);
+		}
+		bdc_writel(bdc->regs, BDC_USPPMS, usppms);
+		break;
+
+	case USB_DEVICE_LTM_ENABLE:
+		dev_dbg(bdc->dev, "USB_DEVICE_LTM_ENABLE?\n");
+		if (bdc->gadget.speed != USB_SPEED_SUPER ||
+						state != USB_STATE_CONFIGURED)
+			return -EINVAL;
+		break;
+	default:
+		dev_err(bdc->dev, "Unknown wValue:%d\n", wValue);
+		return -EOPNOTSUPP;
+	} /* USB_RECIP_DEVICE end */
+
+	return 0;
+}
+
+/* SET/CLEAR FEATURE handler */
+static int ep0_handle_feature(struct bdc *bdc,
+			      struct usb_ctrlrequest *setup_pkt, bool set)
+{
+	enum usb_device_state state = bdc->gadget.state;
+	struct bdc_ep *ep;
+	u16 wValue;
+	u16 wIndex;
+	int epnum;
+
+	wValue = le16_to_cpu(setup_pkt->wValue);
+	wIndex = le16_to_cpu(setup_pkt->wIndex);
+
+	dev_dbg(bdc->dev,
+		"%s wValue=%d wIndex=%d	devstate=%08x speed=%d set=%d",
+		__func__, wValue, wIndex, state,
+		bdc->gadget.speed, set);
+
+	switch (setup_pkt->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		return ep0_handle_feature_dev(bdc, wValue, wIndex, set);
+	case USB_RECIP_INTERFACE:
+		dev_dbg(bdc->dev, "USB_RECIP_INTERFACE\n");
+		/* USB3 spec, sec 9.4.9 */
+		if (wValue != USB_INTRF_FUNC_SUSPEND)
+			return -EINVAL;
+		/* USB3 spec, Table 9-8 */
+		if (set) {
+			if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) {
+				dev_dbg(bdc->dev, "SET REMOTE_WAKEUP\n");
+				bdc->devstatus |= REMOTE_WAKE_ENABLE;
+			} else {
+				dev_dbg(bdc->dev, "CLEAR REMOTE_WAKEUP\n");
+				bdc->devstatus &= ~REMOTE_WAKE_ENABLE;
+			}
+		}
+		break;
+
+	case USB_RECIP_ENDPOINT:
+		dev_dbg(bdc->dev, "USB_RECIP_ENDPOINT\n");
+		if (wValue != USB_ENDPOINT_HALT)
+			return -EINVAL;
+
+		epnum = wIndex & USB_ENDPOINT_NUMBER_MASK;
+		if (epnum) {
+			if ((wIndex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
+				epnum = epnum * 2 + 1;
+			else
+				epnum *= 2;
+		} else {
+			epnum = 1; /*EP0*/
+		}
+		/*
+		 * If CLEAR_FEATURE on ep0 then don't do anything as the stall
+		 * condition on ep0 has already been cleared when SETUP packet
+		 * was received.
+		 */
+		if (epnum == 1 && !set) {
+			dev_dbg(bdc->dev, "ep0 stall already cleared\n");
+			return 0;
+		}
+		dev_dbg(bdc->dev, "epnum=%d\n", epnum);
+		ep = bdc->bdc_ep_array[epnum];
+		if (!ep)
+			return -EINVAL;
+
+		return ep_set_halt(ep, set);
+	default:
+		dev_err(bdc->dev, "Unknown recipient\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* GET_STATUS request handler */
+static int ep0_handle_status(struct bdc *bdc,
+			     struct usb_ctrlrequest *setup_pkt)
+{
+	enum usb_device_state state = bdc->gadget.state;
+	struct bdc_ep *ep;
+	u16 usb_status = 0;
+	u32 epnum;
+	u16 wIndex;
+
+	/* USB2.0 spec sec 9.4.5 */
+	if (state == USB_STATE_DEFAULT)
+		return -EINVAL;
+	wIndex = le16_to_cpu(setup_pkt->wIndex);
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	usb_status = bdc->devstatus;
+	switch (setup_pkt->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		dev_dbg(bdc->dev,
+			"USB_RECIP_DEVICE devstatus:%08x\n",
+			bdc->devstatus);
+		/* USB3 spec, sec 9.4.5 */
+		if (bdc->gadget.speed == USB_SPEED_SUPER)
+			usb_status &= ~REMOTE_WAKE_ENABLE;
+		break;
+
+	case USB_RECIP_INTERFACE:
+		dev_dbg(bdc->dev, "USB_RECIP_INTERFACE\n");
+		if (bdc->gadget.speed == USB_SPEED_SUPER) {
+			/*
+			 * This should come from func for Func remote wkup
+			 * usb_status |=1;
+			 */
+			if (bdc->devstatus & REMOTE_WAKE_ENABLE)
+				usb_status |= REMOTE_WAKE_ENABLE;
+		} else {
+			usb_status = 0;
+		}
+
+		break;
+
+	case USB_RECIP_ENDPOINT:
+		dev_dbg(bdc->dev, "USB_RECIP_ENDPOINT\n");
+		epnum = wIndex & USB_ENDPOINT_NUMBER_MASK;
+		if (epnum) {
+			if ((wIndex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
+				epnum = epnum*2 + 1;
+			else
+				epnum *= 2;
+		} else {
+			epnum = 1; /* EP0 */
+		}
+
+		ep = bdc->bdc_ep_array[epnum];
+		if (!ep) {
+			dev_err(bdc->dev, "ISSUE, GET_STATUS for invalid EP ?");
+			return -EINVAL;
+		}
+		if (ep->flags & BDC_EP_STALL)
+			usb_status |= 1 << USB_ENDPOINT_HALT;
+
+		break;
+	default:
+		dev_err(bdc->dev, "Unknown recipient for get_status\n");
+		return -EINVAL;
+	}
+	/* prepare a data stage for GET_STATUS */
+	dev_dbg(bdc->dev, "usb_status=%08x\n", usb_status);
+	*(__le16 *)bdc->ep0_response_buff = cpu_to_le16(usb_status);
+	bdc->ep0_req.usb_req.length = 2;
+	bdc->ep0_req.usb_req.buf = &bdc->ep0_response_buff;
+	ep0_queue_data_stage(bdc);
+
+	return 0;
+}
+
+static void ep0_set_sel_cmpl(struct usb_ep *_ep, struct usb_request *_req)
+{
+	/* ep0_set_sel_cmpl */
+}
+
+/* Queue data stage to handle 6 byte SET_SEL request */
+static int ep0_set_sel(struct bdc *bdc,
+			     struct usb_ctrlrequest *setup_pkt)
+{
+	struct bdc_ep	*ep;
+	u16	wLength;
+	u16	wValue;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	wValue = le16_to_cpu(setup_pkt->wValue);
+	wLength = le16_to_cpu(setup_pkt->wLength);
+	if (unlikely(wLength != 6)) {
+		dev_err(bdc->dev, "%s Wrong wLength:%d\n", __func__, wLength);
+		return -EINVAL;
+	}
+	ep = bdc->bdc_ep_array[1];
+	bdc->ep0_req.ep = ep;
+	bdc->ep0_req.usb_req.length = 6;
+	bdc->ep0_req.usb_req.buf = bdc->ep0_response_buff;
+	bdc->ep0_req.usb_req.complete = ep0_set_sel_cmpl;
+	ep0_queue_data_stage(bdc);
+
+	return 0;
+}
+
+/*
+ * Queue a 0 byte bd only if wLength is more than the length and and length is
+ * a multiple of MaxPacket then queue 0 byte BD
+ */
+static int ep0_queue_zlp(struct bdc *bdc)
+{
+	int ret;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	bdc->ep0_req.ep = bdc->bdc_ep_array[1];
+	bdc->ep0_req.usb_req.length = 0;
+	bdc->ep0_req.usb_req.complete = NULL;
+	bdc->ep0_state = WAIT_FOR_DATA_START;
+	ret = bdc_queue_xfr(bdc, &bdc->ep0_req);
+	if (ret) {
+		dev_err(bdc->dev, "err queueing zlp :%d\n", ret);
+		return ret;
+	}
+	bdc->ep0_state = WAIT_FOR_DATA_XMIT;
+
+	return 0;
+}
+
+/* Control request handler */
+static int handle_control_request(struct bdc *bdc)
+{
+	enum usb_device_state state = bdc->gadget.state;
+	struct usb_ctrlrequest *setup_pkt;
+	int delegate_setup = 0;
+	int ret = 0;
+	int config = 0;
+
+	setup_pkt = &bdc->setup_pkt;
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	if ((setup_pkt->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+		switch (setup_pkt->bRequest) {
+		case USB_REQ_SET_ADDRESS:
+			dev_dbg(bdc->dev, "USB_REQ_SET_ADDRESS\n");
+			ret = ep0_set_address(bdc, setup_pkt);
+			bdc->devstatus &= DEVSTATUS_CLEAR;
+			break;
+
+		case USB_REQ_SET_CONFIGURATION:
+			dev_dbg(bdc->dev, "USB_REQ_SET_CONFIGURATION\n");
+			if (state == USB_STATE_ADDRESS) {
+				usb_gadget_set_state(&bdc->gadget,
+							USB_STATE_CONFIGURED);
+			} else if (state == USB_STATE_CONFIGURED) {
+				/*
+				 * USB2 spec sec 9.4.7, if wValue is 0 then dev
+				 * is moved to addressed state
+				 */
+				config = le16_to_cpu(setup_pkt->wValue);
+				if (!config)
+					usb_gadget_set_state(
+							&bdc->gadget,
+							USB_STATE_ADDRESS);
+			}
+			delegate_setup = 1;
+			break;
+
+		case USB_REQ_SET_FEATURE:
+			dev_dbg(bdc->dev, "USB_REQ_SET_FEATURE\n");
+			ret = ep0_handle_feature(bdc, setup_pkt, 1);
+			break;
+
+		case USB_REQ_CLEAR_FEATURE:
+			dev_dbg(bdc->dev, "USB_REQ_CLEAR_FEATURE\n");
+			ret = ep0_handle_feature(bdc, setup_pkt, 0);
+			break;
+
+		case USB_REQ_GET_STATUS:
+			dev_dbg(bdc->dev, "USB_REQ_GET_STATUS\n");
+			ret = ep0_handle_status(bdc, setup_pkt);
+			break;
+
+		case USB_REQ_SET_SEL:
+			dev_dbg(bdc->dev, "USB_REQ_SET_SEL\n");
+			ret = ep0_set_sel(bdc, setup_pkt);
+			break;
+
+		case USB_REQ_SET_ISOCH_DELAY:
+			dev_warn(bdc->dev,
+			"USB_REQ_SET_ISOCH_DELAY not handled\n");
+			ret = 0;
+			break;
+		default:
+			delegate_setup = 1;
+		}
+	} else {
+		delegate_setup = 1;
+	}
+
+	if (delegate_setup) {
+		spin_unlock(&bdc->lock);
+		ret = bdc->gadget_driver->setup(&bdc->gadget, setup_pkt);
+		spin_lock(&bdc->lock);
+	}
+
+	return ret;
+}
+
+/* EP0: Data stage started */
+void bdc_xsf_ep0_data_start(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	struct bdc_ep *ep;
+	int ret = 0;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	ep = bdc->bdc_ep_array[1];
+	/* If ep0 was stalled, the clear it first */
+	if (ep->flags & BDC_EP_STALL) {
+		ret = ep_set_halt(ep, 0);
+		if (ret)
+			goto err;
+	}
+	if (bdc->ep0_state != WAIT_FOR_DATA_START)
+		dev_warn(bdc->dev,
+			"Data stage not expected ep0_state:%s\n",
+			ep0_state_string[bdc->ep0_state]);
+
+	ret = handle_control_request(bdc);
+	if (ret == USB_GADGET_DELAYED_STATUS) {
+		/*
+		 * The ep0 state will remain WAIT_FOR_DATA_START till
+		 * we received ep_queue on ep0
+		 */
+		bdc->delayed_status = true;
+		return;
+	}
+	if (!ret) {
+		bdc->ep0_state = WAIT_FOR_DATA_XMIT;
+		dev_dbg(bdc->dev,
+			"ep0_state:%s", ep0_state_string[bdc->ep0_state]);
+		return;
+	}
+err:
+	ep0_stall(bdc);
+}
+
+/* EP0: status stage started */
+void bdc_xsf_ep0_status_start(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	struct usb_ctrlrequest *setup_pkt;
+	struct bdc_ep *ep;
+	int ret = 0;
+
+	dev_dbg(bdc->dev,
+		"%s ep0_state:%s",
+		__func__, ep0_state_string[bdc->ep0_state]);
+	ep = bdc->bdc_ep_array[1];
+
+	/* check if ZLP was queued? */
+	if (bdc->zlp_needed)
+		bdc->zlp_needed = false;
+
+	if (ep->flags & BDC_EP_STALL) {
+		ret = ep_set_halt(ep, 0);
+		if (ret)
+			goto err;
+	}
+
+	if ((bdc->ep0_state != WAIT_FOR_STATUS_START) &&
+				(bdc->ep0_state != WAIT_FOR_DATA_XMIT))
+		dev_err(bdc->dev,
+			"Status stage recv but ep0_state:%s\n",
+			ep0_state_string[bdc->ep0_state]);
+
+	/* check if data stage is in progress ? */
+	if (bdc->ep0_state == WAIT_FOR_DATA_XMIT) {
+		bdc->ep0_state = STATUS_PENDING;
+		/* Status stage will be queued upon Data stage transmit event */
+		dev_dbg(bdc->dev,
+			"status started but data  not transmitted yet\n");
+		return;
+	}
+	setup_pkt = &bdc->setup_pkt;
+
+	/*
+	 * 2 stage setup then only process the setup, for 3 stage setup the date
+	 * stage is already handled
+	 */
+	if (!le16_to_cpu(setup_pkt->wLength)) {
+		ret = handle_control_request(bdc);
+		if (ret == USB_GADGET_DELAYED_STATUS) {
+			bdc->delayed_status = true;
+			/* ep0_state will remain WAIT_FOR_STATUS_START */
+			return;
+		}
+	}
+	if (!ret) {
+		/* Queue a status stage BD */
+		ep0_queue_status_stage(bdc);
+		bdc->ep0_state = WAIT_FOR_STATUS_XMIT;
+		dev_dbg(bdc->dev,
+			"ep0_state:%s", ep0_state_string[bdc->ep0_state]);
+		return;
+	}
+err:
+	ep0_stall(bdc);
+}
+
+/* Helper function to update ep0 upon SR with xsf_succ or xsf_short */
+static void ep0_xsf_complete(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	switch (bdc->ep0_state) {
+	case WAIT_FOR_DATA_XMIT:
+		bdc->ep0_state = WAIT_FOR_STATUS_START;
+		break;
+	case WAIT_FOR_STATUS_XMIT:
+		bdc->ep0_state = WAIT_FOR_SETUP;
+		if (bdc->test_mode) {
+			int ret;
+
+			dev_dbg(bdc->dev, "test_mode:%d\n", bdc->test_mode);
+			ret = bdc_set_test_mode(bdc);
+			if (ret < 0) {
+				dev_err(bdc->dev, "Err in setting Test mode\n");
+				return;
+			}
+			bdc->test_mode = 0;
+		}
+		break;
+	case STATUS_PENDING:
+		bdc_xsf_ep0_status_start(bdc, sreport);
+		break;
+
+	default:
+		dev_err(bdc->dev,
+			"Unknown ep0_state:%s\n",
+			ep0_state_string[bdc->ep0_state]);
+
+	}
+}
+
+/* xfr completion status report handler */
+void bdc_sr_xsf(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	struct bdc_ep *ep;
+	u32 sr_status;
+	u8 ep_num;
+
+	ep_num = (le32_to_cpu(sreport->offset[3])>>4) & 0x1f;
+	ep = bdc->bdc_ep_array[ep_num];
+	if (!ep || !(ep->flags & BDC_EP_ENABLED)) {
+		dev_err(bdc->dev, "xsf for ep not enabled\n");
+		return;
+	}
+	/*
+	 * check if this transfer is after link went from U3->U0 due
+	 * to remote wakeup
+	 */
+	if (bdc->devstatus & FUNC_WAKE_ISSUED) {
+		bdc->devstatus &= ~(FUNC_WAKE_ISSUED);
+		dev_dbg(bdc->dev, "%s clearing FUNC_WAKE_ISSUED flag\n",
+								__func__);
+	}
+	sr_status = XSF_STS(le32_to_cpu(sreport->offset[3]));
+	dev_dbg_ratelimited(bdc->dev, "%s sr_status=%d ep:%s\n",
+					__func__, sr_status, ep->name);
+
+	switch (sr_status) {
+	case XSF_SUCC:
+	case XSF_SHORT:
+		handle_xsr_succ_status(bdc, ep, sreport);
+		if (ep_num == 1)
+			ep0_xsf_complete(bdc, sreport);
+		break;
+
+	case XSF_SETUP_RECV:
+	case XSF_DATA_START:
+	case XSF_STATUS_START:
+		if (ep_num != 1) {
+			dev_err(bdc->dev,
+				"ep0 related packets on non ep0 endpoint");
+			return;
+		}
+		bdc->sr_xsf_ep0[sr_status - XSF_SETUP_RECV](bdc, sreport);
+		break;
+
+	case XSF_BABB:
+		if (ep_num == 1) {
+			dev_dbg(bdc->dev, "Babble on ep0 zlp_need:%d\n",
+							bdc->zlp_needed);
+			/*
+			 * If the last completed transfer had wLength >Data Len,
+			 * and Len is multiple of MaxPacket,then queue ZLP
+			 */
+			if (bdc->zlp_needed) {
+				/* queue 0 length bd */
+				ep0_queue_zlp(bdc);
+				return;
+			}
+		}
+		dev_warn(bdc->dev, "Babble on ep not handled\n");
+		break;
+	default:
+		dev_warn(bdc->dev, "sr status not handled:%x\n", sr_status);
+		break;
+	}
+}
+
+static int bdc_gadget_ep_queue(struct usb_ep *_ep,
+				struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct bdc_req *req;
+	unsigned long flags;
+	struct bdc_ep *ep;
+	struct bdc *bdc;
+	int ret;
+
+	if (!_ep || !_ep->desc)
+		return -ESHUTDOWN;
+
+	if (!_req || !_req->complete || !_req->buf)
+		return -EINVAL;
+
+	ep = to_bdc_ep(_ep);
+	req = to_bdc_req(_req);
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s ep:%p req:%p\n", __func__, ep, req);
+	dev_dbg(bdc->dev, "queuing request %p to %s length %d zero:%d\n",
+				_req, ep->name, _req->length, _req->zero);
+
+	if (!ep->usb_ep.desc) {
+		dev_warn(bdc->dev,
+			"trying to queue req %p to disabled %s\n",
+			_req, ep->name);
+		return -ESHUTDOWN;
+	}
+
+	if (_req->length > MAX_XFR_LEN) {
+		dev_warn(bdc->dev,
+			"req length > supported MAX:%d requested:%d\n",
+			MAX_XFR_LEN, _req->length);
+		return -EOPNOTSUPP;
+	}
+	spin_lock_irqsave(&bdc->lock, flags);
+	if (ep == bdc->bdc_ep_array[1])
+		ret = ep0_queue(ep, req);
+	else
+		ret = ep_queue(ep, req);
+
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static int bdc_gadget_ep_dequeue(struct usb_ep *_ep,
+				  struct usb_request *_req)
+{
+	struct bdc_req *req;
+	unsigned long flags;
+	struct bdc_ep *ep;
+	struct bdc *bdc;
+	int ret;
+
+	if (!_ep || !_req)
+		return -EINVAL;
+
+	ep = to_bdc_ep(_ep);
+	req = to_bdc_req(_req);
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s ep:%s req:%p\n", __func__, ep->name, req);
+	bdc_dbg_bd_list(bdc, ep);
+	spin_lock_irqsave(&bdc->lock, flags);
+	/* make sure it's still queued on this endpoint */
+	list_for_each_entry(req, &ep->queue, queue) {
+		if (&req->usb_req == _req)
+			break;
+	}
+	if (&req->usb_req != _req) {
+		spin_unlock_irqrestore(&bdc->lock, flags);
+		dev_err(bdc->dev, "usb_req !=req n");
+		return -EINVAL;
+	}
+	ret = ep_dequeue(ep, req);
+	if (ret) {
+		ret = -EOPNOTSUPP;
+		goto err;
+	}
+	bdc_req_complete(ep, req, -ECONNRESET);
+
+err:
+	bdc_dbg_bd_list(bdc, ep);
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static int bdc_gadget_ep_set_halt(struct usb_ep *_ep, int value)
+{
+	unsigned long flags;
+	struct bdc_ep *ep;
+	struct bdc *bdc;
+	int ret;
+
+	ep = to_bdc_ep(_ep);
+	bdc = ep->bdc;
+	dev_dbg(bdc->dev, "%s ep:%s value=%d\n", __func__, ep->name, value);
+	spin_lock_irqsave(&bdc->lock, flags);
+	if (usb_endpoint_xfer_isoc(ep->usb_ep.desc))
+		ret = -EINVAL;
+	else if (!list_empty(&ep->queue))
+		ret = -EAGAIN;
+	else
+		ret = ep_set_halt(ep, value);
+
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static struct usb_request *bdc_gadget_alloc_request(struct usb_ep *_ep,
+						     gfp_t gfp_flags)
+{
+	struct bdc_req *req;
+	struct bdc_ep *ep;
+
+	req = kzalloc(sizeof(*req), gfp_flags);
+	if (!req)
+		return NULL;
+
+	ep = to_bdc_ep(_ep);
+	req->ep = ep;
+	req->epnum = ep->ep_num;
+	req->usb_req.dma = DMA_ADDR_INVALID;
+	dev_dbg(ep->bdc->dev, "%s ep:%s req:%p\n", __func__, ep->name, req);
+
+	return &req->usb_req;
+}
+
+static void bdc_gadget_free_request(struct usb_ep *_ep,
+				     struct usb_request *_req)
+{
+	struct bdc_req *req;
+
+	req = to_bdc_req(_req);
+	kfree(req);
+}
+
+/* endpoint operations */
+
+/* configure endpoint and also allocate resources */
+static int bdc_gadget_ep_enable(struct usb_ep *_ep,
+				 const struct usb_endpoint_descriptor *desc)
+{
+	unsigned long flags;
+	struct bdc_ep *ep;
+	struct bdc *bdc;
+	int ret;
+
+	if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
+		pr_debug("bdc_gadget_ep_enable invalid parameters\n");
+		return -EINVAL;
+	}
+
+	if (!desc->wMaxPacketSize) {
+		pr_debug("bdc_gadget_ep_enable missing wMaxPacketSize\n");
+		return -EINVAL;
+	}
+
+	ep = to_bdc_ep(_ep);
+	bdc = ep->bdc;
+
+	/* Sanity check, upper layer will not send enable for ep0 */
+	if (ep == bdc->bdc_ep_array[1])
+		return -EINVAL;
+
+	if (!bdc->gadget_driver
+	    || bdc->gadget.speed == USB_SPEED_UNKNOWN) {
+		return -ESHUTDOWN;
+	}
+
+	dev_dbg(bdc->dev, "%s Enabling %s\n", __func__, ep->name);
+	spin_lock_irqsave(&bdc->lock, flags);
+	ep->desc = desc;
+	ep->comp_desc = _ep->comp_desc;
+	ret = bdc_ep_enable(ep);
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static int bdc_gadget_ep_disable(struct usb_ep *_ep)
+{
+	unsigned long flags;
+	struct bdc_ep *ep;
+	struct bdc *bdc;
+	int ret;
+
+	if (!_ep) {
+		pr_debug("bdc: invalid parameters\n");
+		return -EINVAL;
+	}
+	ep = to_bdc_ep(_ep);
+	bdc = ep->bdc;
+
+	/* Upper layer will not call this for ep0, but do a sanity check */
+	if (ep == bdc->bdc_ep_array[1]) {
+		dev_warn(bdc->dev, "%s called for ep0\n", __func__);
+		return -EINVAL;
+	}
+	dev_dbg(bdc->dev,
+		"%s() ep:%s ep->flags:%08x\n",
+		__func__, ep->name, ep->flags);
+
+	if (!(ep->flags & BDC_EP_ENABLED)) {
+		dev_warn(bdc->dev, "%s is already disabled\n", ep->name);
+		return 0;
+	}
+	spin_lock_irqsave(&bdc->lock, flags);
+	ret = bdc_ep_disable(ep);
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static const struct usb_ep_ops bdc_gadget_ep_ops = {
+	.enable = bdc_gadget_ep_enable,
+	.disable = bdc_gadget_ep_disable,
+	.alloc_request = bdc_gadget_alloc_request,
+	.free_request = bdc_gadget_free_request,
+	.queue = bdc_gadget_ep_queue,
+	.dequeue = bdc_gadget_ep_dequeue,
+	.set_halt = bdc_gadget_ep_set_halt
+};
+
+/* dir = 1 is IN */
+static int init_ep(struct bdc *bdc, u32 epnum, u32 dir)
+{
+	struct bdc_ep *ep;
+
+	dev_dbg(bdc->dev, "%s epnum=%d dir=%d\n", __func__, epnum, dir);
+	ep = kzalloc(sizeof(*ep), GFP_KERNEL);
+	if (!ep)
+		return -ENOMEM;
+
+	ep->bdc = bdc;
+	ep->dir = dir;
+
+	/* ep->ep_num is the index inside bdc_ep */
+	if (epnum == 1) {
+		ep->ep_num = 1;
+		bdc->bdc_ep_array[ep->ep_num] = ep;
+		snprintf(ep->name, sizeof(ep->name), "ep%d", epnum - 1);
+		usb_ep_set_maxpacket_limit(&ep->usb_ep, EP0_MAX_PKT_SIZE);
+		ep->comp_desc = NULL;
+		bdc->gadget.ep0 = &ep->usb_ep;
+	} else {
+		if (dir)
+			ep->ep_num = epnum * 2 - 1;
+		else
+			ep->ep_num = epnum * 2 - 2;
+
+		bdc->bdc_ep_array[ep->ep_num] = ep;
+		snprintf(ep->name, sizeof(ep->name), "ep%d%s", epnum - 1,
+			 dir & 1 ? "in" : "out");
+
+		usb_ep_set_maxpacket_limit(&ep->usb_ep, 1024);
+		ep->usb_ep.max_streams = 0;
+		list_add_tail(&ep->usb_ep.ep_list, &bdc->gadget.ep_list);
+	}
+	ep->usb_ep.ops = &bdc_gadget_ep_ops;
+	ep->usb_ep.name = ep->name;
+	ep->flags = 0;
+	ep->ignore_next_sr = false;
+	dev_dbg(bdc->dev, "ep=%p ep->usb_ep.name=%s epnum=%d ep->epnum=%d\n",
+				ep, ep->usb_ep.name, epnum, ep->ep_num);
+
+	INIT_LIST_HEAD(&ep->queue);
+
+	return 0;
+}
+
+/* Init all ep */
+int bdc_init_ep(struct bdc *bdc)
+{
+	u8 epnum;
+	int ret;
+
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	INIT_LIST_HEAD(&bdc->gadget.ep_list);
+	/* init ep0 */
+	ret = init_ep(bdc, 1, 0);
+	if (ret) {
+		dev_err(bdc->dev, "init ep ep0 fail %d\n", ret);
+		return ret;
+	}
+
+	for (epnum = 2; epnum <= bdc->num_eps / 2; epnum++) {
+		/* OUT */
+		ret = init_ep(bdc, epnum, 0);
+		if (ret) {
+			dev_err(bdc->dev,
+				"init ep failed for:%d error: %d\n",
+				epnum, ret);
+			return ret;
+		}
+
+		/* IN */
+		ret = init_ep(bdc, epnum, 1);
+		if (ret) {
+			dev_err(bdc->dev,
+				"init ep failed for:%d error: %d\n",
+				epnum, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/usb/gadget/bdc/bdc_ep.h b/drivers/usb/gadget/bdc/bdc_ep.h
new file mode 100644
index 000000000000..8a6b36cbf2ea
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_ep.h
@@ -0,0 +1,22 @@
+/*
+ * bdc_ep.h - header for the BDC debug functions
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __LINUX_BDC_EP_H__
+#define __LINUX_BDC_EP_H__
+
+int bdc_init_ep(struct bdc *);
+int bdc_ep_disable(struct bdc_ep *);
+int bdc_ep_enable(struct bdc_ep *);
+void bdc_free_ep(struct bdc *);
+
+#endif /* __LINUX_BDC_EP_H__ */
diff --git a/drivers/usb/gadget/bdc/bdc_pci.c b/drivers/usb/gadget/bdc/bdc_pci.c
new file mode 100644
index 000000000000..02968842b359
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_pci.c
@@ -0,0 +1,132 @@
+/*
+ * bdc_pci.c - BRCM BDC USB3.0 device controller PCI interface file.
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * Based on drivers under drivers/usb/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/platform_device.h>
+
+#include "bdc.h"
+
+#define BDC_PCI_PID 0x1570
+
+struct bdc_pci {
+	struct device *dev;
+	struct platform_device *bdc;
+};
+
+static int bdc_setup_msi(struct pci_dev *pci)
+{
+	int ret;
+
+	ret = pci_enable_msi(pci);
+	if (ret) {
+		pr_err("failed to allocate MSI entry\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int bdc_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
+{
+	struct resource res[2];
+	struct platform_device *bdc;
+	struct bdc_pci *glue;
+	int ret = -ENOMEM;
+
+	glue = devm_kzalloc(&pci->dev, sizeof(*glue), GFP_KERNEL);
+	if (!glue)
+		return -ENOMEM;
+
+	glue->dev = &pci->dev;
+	ret = pci_enable_device(pci);
+	if (ret) {
+		dev_err(&pci->dev, "failed to enable pci device\n");
+		return -ENODEV;
+	}
+	pci_set_master(pci);
+
+	bdc = platform_device_alloc(BRCM_BDC_NAME, PLATFORM_DEVID_AUTO);
+	if (!bdc)
+		return -ENOMEM;
+
+	memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
+	bdc_setup_msi(pci);
+
+	res[0].start	= pci_resource_start(pci, 0);
+	res[0].end	= pci_resource_end(pci, 0);
+	res[0].name	= BRCM_BDC_NAME;
+	res[0].flags	= IORESOURCE_MEM;
+
+	res[1].start	= pci->irq;
+	res[1].name	= BRCM_BDC_NAME;
+	res[1].flags	= IORESOURCE_IRQ;
+
+	ret = platform_device_add_resources(bdc, res, ARRAY_SIZE(res));
+	if (ret) {
+		dev_err(&pci->dev,
+			"couldn't add resources to bdc device\n");
+		return ret;
+	}
+
+	pci_set_drvdata(pci, glue);
+
+	dma_set_coherent_mask(&bdc->dev, pci->dev.coherent_dma_mask);
+
+	bdc->dev.dma_mask = pci->dev.dma_mask;
+	bdc->dev.dma_parms = pci->dev.dma_parms;
+	bdc->dev.parent = &pci->dev;
+	glue->bdc = bdc;
+
+	ret = platform_device_add(bdc);
+	if (ret) {
+		dev_err(&pci->dev, "failed to register bdc device\n");
+		platform_device_put(bdc);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void bdc_pci_remove(struct pci_dev *pci)
+{
+	struct bdc_pci *glue = pci_get_drvdata(pci);
+
+	platform_device_unregister(glue->bdc);
+	pci_disable_msi(pci);
+}
+
+static struct pci_device_id bdc_pci_id_table[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BDC_PCI_PID), },
+	{} /* Terminating Entry */
+};
+
+MODULE_DEVICE_TABLE(pci, bdc_pci_id_table);
+
+static struct pci_driver bdc_pci_driver = {
+	.name = "bdc-pci",
+	.id_table = bdc_pci_id_table,
+	.probe = bdc_pci_probe,
+	.remove = bdc_pci_remove,
+};
+
+MODULE_AUTHOR("Ashwini Pahuja <ashwini.linux@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("BRCM BDC USB3 PCI Glue layer");
+module_pci_driver(bdc_pci_driver);
diff --git a/drivers/usb/gadget/bdc/bdc_udc.c b/drivers/usb/gadget/bdc/bdc_udc.c
new file mode 100644
index 000000000000..ad0302fe7487
--- /dev/null
+++ b/drivers/usb/gadget/bdc/bdc_udc.c
@@ -0,0 +1,587 @@
+/*
+ * bdc_udc.c - BRCM BDC USB3.0 device controller gagdet ops
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * Author: Ashwini Pahuja
+ *
+ * Based on drivers under drivers/usb/gadget/udc/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/unaligned.h>
+#include <linux/platform_device.h>
+
+#include "bdc.h"
+#include "bdc_ep.h"
+#include "bdc_cmd.h"
+#include "bdc_dbg.h"
+
+static const struct usb_gadget_ops bdc_gadget_ops;
+
+static const char * const conn_speed_str[] =  {
+	"Not connected",
+	"Full Speed",
+	"Low Speed",
+	"High Speed",
+	"Super Speed",
+};
+
+/* EP0 initial descripror */
+static struct usb_endpoint_descriptor bdc_gadget_ep0_desc = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
+	.bEndpointAddress = 0,
+	.wMaxPacketSize	= cpu_to_le16(EP0_MAX_PKT_SIZE),
+};
+
+/* Advance the srr dqp maintained by SW */
+static void srr_dqp_index_advc(struct bdc *bdc, u32 srr_num)
+{
+	struct srr *srr;
+
+	srr = &bdc->srr;
+	dev_dbg_ratelimited(bdc->dev, "srr->dqp_index:%d\n", srr->dqp_index);
+	srr->dqp_index++;
+	/* rollback to 0 if we are past the last */
+	if (srr->dqp_index == NUM_SR_ENTRIES)
+		srr->dqp_index = 0;
+}
+
+/* connect sr */
+static void bdc_uspc_connected(struct bdc *bdc)
+{
+	u32 speed, temp;
+	u32 usppms;
+	int ret;
+
+	temp = bdc_readl(bdc->regs, BDC_USPC);
+	speed = BDC_PSP(temp);
+	dev_dbg(bdc->dev, "%s speed=%x\n", __func__, speed);
+	switch (speed) {
+	case BDC_SPEED_SS:
+		bdc_gadget_ep0_desc.wMaxPacketSize =
+						cpu_to_le16(EP0_MAX_PKT_SIZE);
+		bdc->gadget.ep0->maxpacket = EP0_MAX_PKT_SIZE;
+		bdc->gadget.speed = USB_SPEED_SUPER;
+		/* Enable U1T in SS mode */
+		usppms =  bdc_readl(bdc->regs, BDC_USPPMS);
+		usppms &= ~BDC_U1T(0xff);
+		usppms |= BDC_U1T(U1_TIMEOUT);
+		usppms |= BDC_PORT_W1S;
+		bdc_writel(bdc->regs, BDC_USPPMS, usppms);
+		break;
+
+	case BDC_SPEED_HS:
+		bdc_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
+		bdc->gadget.ep0->maxpacket = 64;
+		bdc->gadget.speed = USB_SPEED_HIGH;
+		break;
+
+	case BDC_SPEED_FS:
+		bdc_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
+		bdc->gadget.ep0->maxpacket = 64;
+		bdc->gadget.speed = USB_SPEED_FULL;
+		break;
+
+	case BDC_SPEED_LS:
+		bdc_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
+		bdc->gadget.ep0->maxpacket = 8;
+		bdc->gadget.speed = USB_SPEED_LOW;
+		break;
+	default:
+		dev_err(bdc->dev, "UNDEFINED SPEED\n");
+		return;
+	}
+	dev_dbg(bdc->dev, "connected at %s\n", conn_speed_str[speed]);
+	/* Now we know the speed, configure ep0 */
+	bdc->bdc_ep_array[1]->desc = &bdc_gadget_ep0_desc;
+	ret = bdc_config_ep(bdc, bdc->bdc_ep_array[1]);
+	if (ret)
+		dev_err(bdc->dev, "EP0 config failed\n");
+	bdc->bdc_ep_array[1]->usb_ep.desc = &bdc_gadget_ep0_desc;
+	bdc->bdc_ep_array[1]->flags |= BDC_EP_ENABLED;
+	usb_gadget_set_state(&bdc->gadget, USB_STATE_DEFAULT);
+}
+
+/* device got disconnected */
+static void bdc_uspc_disconnected(struct bdc *bdc, bool reinit)
+{
+	struct bdc_ep *ep;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	/*
+	 * Only stop ep0 from here, rest of the endpoints will be disabled
+	 * from gadget_disconnect
+	 */
+	ep = bdc->bdc_ep_array[1];
+	if (ep && (ep->flags & BDC_EP_ENABLED))
+		/* if enabled then stop and remove requests */
+		bdc_ep_disable(ep);
+
+	if (bdc->gadget_driver && bdc->gadget_driver->disconnect) {
+		spin_unlock(&bdc->lock);
+		bdc->gadget_driver->disconnect(&bdc->gadget);
+		spin_lock(&bdc->lock);
+	}
+	/* Set Unknown speed */
+	bdc->gadget.speed = USB_SPEED_UNKNOWN;
+	bdc->devstatus &= DEVSTATUS_CLEAR;
+	bdc->delayed_status = false;
+	bdc->reinit = reinit;
+	bdc->test_mode = false;
+}
+
+/* TNotify wkaeup timer */
+static void bdc_func_wake_timer(struct work_struct *work)
+{
+	struct bdc *bdc = container_of(work, struct bdc, func_wake_notify.work);
+	unsigned long flags;
+
+	dev_dbg(bdc->dev, "%s\n", __func__);
+	spin_lock_irqsave(&bdc->lock, flags);
+	/*
+	 * Check if host has started transferring on endpoints
+	 * FUNC_WAKE_ISSUED is cleared when transfer has started after resume
+	*/
+	if (bdc->devstatus & FUNC_WAKE_ISSUED) {
+		dev_dbg(bdc->dev, "FUNC_WAKE_ISSUED FLAG IS STILL SET\n");
+		/* flag is still set, so again send func wake */
+		bdc_function_wake_fh(bdc, 0);
+		schedule_delayed_work(&bdc->func_wake_notify,
+						msecs_to_jiffies(BDC_TNOTIFY));
+	}
+	spin_unlock_irqrestore(&bdc->lock, flags);
+}
+
+/* handler for Link state change condition */
+static void handle_link_state_change(struct bdc *bdc, u32 uspc)
+{
+	u32 link_state;
+
+	dev_dbg(bdc->dev, "Link state change");
+	link_state = BDC_PST(uspc);
+	switch (link_state) {
+	case BDC_LINK_STATE_U3:
+		if ((bdc->gadget.speed != USB_SPEED_UNKNOWN) &&
+						bdc->gadget_driver->suspend) {
+			dev_dbg(bdc->dev, "Entered Suspend mode\n");
+			spin_unlock(&bdc->lock);
+			bdc->devstatus |= DEVICE_SUSPENDED;
+			bdc->gadget_driver->suspend(&bdc->gadget);
+			spin_lock(&bdc->lock);
+		}
+		break;
+	case BDC_LINK_STATE_U0:
+		if (bdc->devstatus & REMOTE_WAKEUP_ISSUED) {
+					bdc->devstatus &= ~REMOTE_WAKEUP_ISSUED;
+			if (bdc->gadget.speed == USB_SPEED_SUPER) {
+				bdc_function_wake_fh(bdc, 0);
+				bdc->devstatus |= FUNC_WAKE_ISSUED;
+				/*
+				 * Start a Notification timer and check if the
+				 * Host transferred anything on any of the EPs,
+				 * if not then send function wake again every
+				 * TNotification secs until host initiates
+				 * transfer to BDC, USB3 spec Table 8.13
+				*/
+				schedule_delayed_work(
+						&bdc->func_wake_notify,
+						msecs_to_jiffies(BDC_TNOTIFY));
+				dev_dbg(bdc->dev, "sched func_wake_notify\n");
+			}
+		}
+		break;
+
+	case BDC_LINK_STATE_RESUME:
+		dev_dbg(bdc->dev, "Resumed from Suspend\n");
+		if (bdc->devstatus & DEVICE_SUSPENDED) {
+			bdc->gadget_driver->resume(&bdc->gadget);
+			bdc->devstatus &= ~DEVICE_SUSPENDED;
+		}
+		break;
+	default:
+		dev_dbg(bdc->dev, "link state:%d\n", link_state);
+	}
+}
+
+/* something changes on upstream port, handle it here */
+void bdc_sr_uspc(struct bdc *bdc, struct bdc_sr *sreport)
+{
+	u32 clear_flags = 0;
+	u32 uspc;
+	bool connected = false;
+	bool disconn = false;
+
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	dev_dbg(bdc->dev, "%s uspc=0x%08x\n", __func__, uspc);
+
+	/* Port connect changed */
+	if (uspc & BDC_PCC) {
+		/* Vbus not present, and not connected to Downstream port */
+		if ((uspc & BDC_VBC) && !(uspc & BDC_VBS) && !(uspc & BDC_PCS))
+			disconn = true;
+		else if ((uspc & BDC_PCS) && !BDC_PST(uspc))
+			connected = true;
+	}
+
+	/* Change in VBus and VBus is present */
+	if ((uspc & BDC_VBC) && (uspc & BDC_VBS)) {
+		if (bdc->pullup) {
+			dev_dbg(bdc->dev, "Do a softconnect\n");
+			/* Attached state, do a softconnect */
+			bdc_softconn(bdc);
+			usb_gadget_set_state(&bdc->gadget, USB_STATE_POWERED);
+		}
+		clear_flags = BDC_VBC;
+	} else if ((uspc & BDC_PRS) || (uspc & BDC_PRC) || disconn) {
+		/* Hot reset, warm reset, 2.0 bus reset or disconn */
+		dev_dbg(bdc->dev, "Port reset or disconn\n");
+		bdc_uspc_disconnected(bdc, disconn);
+		clear_flags = BDC_PCC|BDC_PCS|BDC_PRS|BDC_PRC;
+	} else if ((uspc & BDC_PSC) && (uspc & BDC_PCS)) {
+		/* Change in Link state */
+		handle_link_state_change(bdc, uspc);
+		clear_flags = BDC_PSC|BDC_PCS;
+	}
+
+	/*
+	 * In SS we might not have PRC bit set before connection, but in 2.0
+	 * the PRC bit is set before connection, so moving this condition out
+	 * of bus reset to handle both SS/2.0 speeds.
+	 */
+	if (connected) {
+		/* This is the connect event for U0/L0 */
+		dev_dbg(bdc->dev, "Connected\n");
+		bdc_uspc_connected(bdc);
+		bdc->devstatus &= ~(DEVICE_SUSPENDED);
+	}
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	uspc &= (~BDC_USPSC_RW);
+	dev_dbg(bdc->dev, "uspc=%x\n", uspc);
+	bdc_writel(bdc->regs, BDC_USPC, clear_flags);
+}
+
+/* Main interrupt handler for bdc */
+static irqreturn_t bdc_udc_interrupt(int irq, void *_bdc)
+{
+	u32 eqp_index, dqp_index, sr_type, srr_int;
+	struct bdc_sr *sreport;
+	struct bdc *bdc = _bdc;
+	u32 status;
+	int ret;
+
+	spin_lock(&bdc->lock);
+	status = bdc_readl(bdc->regs, BDC_BDCSC);
+	if (!(status & BDC_GIP)) {
+		spin_unlock(&bdc->lock);
+		return IRQ_NONE;
+	}
+	srr_int = bdc_readl(bdc->regs, BDC_SRRINT(0));
+	/* Check if the SRR IP bit it set? */
+	if (!(srr_int & BDC_SRR_IP)) {
+		dev_warn(bdc->dev, "Global irq pending but SRR IP is 0\n");
+		spin_unlock(&bdc->lock);
+		return IRQ_NONE;
+	}
+	eqp_index = BDC_SRR_EPI(srr_int);
+	dqp_index = BDC_SRR_DPI(srr_int);
+	dev_dbg(bdc->dev,
+			"%s eqp_index=%d dqp_index=%d  srr.dqp_index=%d\n\n",
+			 __func__, eqp_index, dqp_index, bdc->srr.dqp_index);
+
+	/* check for ring empty condition */
+	if (eqp_index == dqp_index) {
+		dev_dbg(bdc->dev, "SRR empty?\n");
+		spin_unlock(&bdc->lock);
+		return IRQ_HANDLED;
+	}
+
+	while (bdc->srr.dqp_index != eqp_index) {
+		sreport = &bdc->srr.sr_bds[bdc->srr.dqp_index];
+		/* sreport is read before using it */
+		rmb();
+		sr_type = le32_to_cpu(sreport->offset[3]) & BD_TYPE_BITMASK;
+		dev_dbg_ratelimited(bdc->dev, "sr_type=%d\n", sr_type);
+		switch (sr_type) {
+		case SR_XSF:
+			bdc->sr_handler[0](bdc, sreport);
+			break;
+
+		case SR_USPC:
+			bdc->sr_handler[1](bdc, sreport);
+			break;
+		default:
+			dev_warn(bdc->dev, "SR:%d not handled\n", sr_type);
+		}
+		/* Advance the srr dqp index */
+		srr_dqp_index_advc(bdc, 0);
+	}
+	/* update the hw dequeue pointer */
+	srr_int = bdc_readl(bdc->regs, BDC_SRRINT(0));
+	srr_int &= ~BDC_SRR_DPI_MASK;
+	srr_int &= ~(BDC_SRR_RWS|BDC_SRR_RST|BDC_SRR_ISR);
+	srr_int |= ((bdc->srr.dqp_index) << 16);
+	srr_int |= BDC_SRR_IP;
+	bdc_writel(bdc->regs, BDC_SRRINT(0), srr_int);
+	srr_int = bdc_readl(bdc->regs, BDC_SRRINT(0));
+	if (bdc->reinit) {
+		ret = bdc_reinit(bdc);
+		if (ret)
+			dev_err(bdc->dev, "err in bdc reinit\n");
+	}
+
+	spin_unlock(&bdc->lock);
+
+	return IRQ_HANDLED;
+}
+
+/* Gadget ops */
+static int bdc_udc_start(struct usb_gadget *gadget,
+				struct usb_gadget_driver *driver)
+{
+	struct bdc *bdc = gadget_to_bdc(gadget);
+	unsigned long flags;
+	int ret = 0;
+
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	spin_lock_irqsave(&bdc->lock, flags);
+	if (bdc->gadget_driver) {
+		dev_err(bdc->dev, "%s is already bound to %s\n",
+			bdc->gadget.name,
+			bdc->gadget_driver->driver.name);
+		ret = -EBUSY;
+		goto err;
+	}
+	/*
+	 * Run the controller from here and when BDC is connected to
+	 * Host then driver will receive a USPC SR with VBUS present
+	 * and then driver will do a softconnect.
+	*/
+	ret = bdc_run(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "%s bdc run fail\n", __func__);
+		goto err;
+	}
+	bdc->gadget_driver = driver;
+	bdc->gadget.dev.driver = &driver->driver;
+err:
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static int bdc_udc_stop(struct usb_gadget *gadget,
+			struct usb_gadget_driver *d)
+{
+	struct bdc *bdc = gadget_to_bdc(gadget);
+	unsigned long flags;
+
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	spin_lock_irqsave(&bdc->lock, flags);
+	bdc_stop(bdc);
+	bdc->gadget_driver = NULL;
+	bdc->gadget.dev.driver = NULL;
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return 0;
+}
+
+static int bdc_udc_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct bdc *bdc = gadget_to_bdc(gadget);
+	unsigned long flags;
+	u32 uspc;
+
+	dev_dbg(bdc->dev, "%s() is_on:%d\n", __func__, is_on);
+	if (!gadget)
+		return -EINVAL;
+
+	spin_lock_irqsave(&bdc->lock, flags);
+	if (!is_on) {
+		bdc_softdisconn(bdc);
+		bdc->pullup = false;
+	} else {
+		/*
+		 * For a self powered device, we need to wait till we receive
+		 * a VBUS change and Vbus present event, then if pullup flag
+		 * is set, then only we present the Termintation.
+		 */
+		bdc->pullup = true;
+		/*
+		 * Check if BDC is already connected to Host i.e Vbus=1,
+		 * if yes, then present TERM now, this is typical for bus
+		 * powered devices.
+		 */
+		uspc = bdc_readl(bdc->regs, BDC_USPC);
+		if (uspc & BDC_VBS)
+			bdc_softconn(bdc);
+	}
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return 0;
+}
+
+static int bdc_udc_set_selfpowered(struct usb_gadget *gadget,
+		int is_self)
+{
+	struct bdc		*bdc = gadget_to_bdc(gadget);
+	unsigned long           flags;
+
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	spin_lock_irqsave(&bdc->lock, flags);
+	if (!is_self)
+		bdc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
+	else
+		bdc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
+
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return 0;
+}
+
+static int bdc_udc_wakeup(struct usb_gadget *gadget)
+{
+	struct bdc *bdc = gadget_to_bdc(gadget);
+	unsigned long		flags;
+	u8	link_state;
+	u32	uspc;
+	int ret = 0;
+
+	dev_dbg(bdc->dev,
+		"%s() bdc->devstatus=%08x\n",
+		__func__, bdc->devstatus);
+
+	if (!(bdc->devstatus & REMOTE_WAKE_ENABLE))
+		return  -EOPNOTSUPP;
+
+	spin_lock_irqsave(&bdc->lock, flags);
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	link_state = BDC_PST(uspc);
+	dev_dbg(bdc->dev, "link_state =%d portsc=%x", link_state, uspc);
+	if (link_state != BDC_LINK_STATE_U3) {
+		dev_warn(bdc->dev,
+			"can't wakeup from link state %d\n",
+			link_state);
+		ret = -EINVAL;
+		goto out;
+	}
+	if (bdc->gadget.speed == USB_SPEED_SUPER)
+		bdc->devstatus |= REMOTE_WAKEUP_ISSUED;
+
+	uspc &= ~BDC_PST_MASK;
+	uspc &= (~BDC_USPSC_RW);
+	uspc |=  BDC_PST(BDC_LINK_STATE_U0);
+	uspc |=  BDC_SWS;
+	bdc_writel(bdc->regs, BDC_USPC, uspc);
+	uspc = bdc_readl(bdc->regs, BDC_USPC);
+	link_state = BDC_PST(uspc);
+	dev_dbg(bdc->dev, "link_state =%d portsc=%x", link_state, uspc);
+out:
+	spin_unlock_irqrestore(&bdc->lock, flags);
+
+	return ret;
+}
+
+static const struct usb_gadget_ops bdc_gadget_ops = {
+	.wakeup = bdc_udc_wakeup,
+	.set_selfpowered = bdc_udc_set_selfpowered,
+	.pullup = bdc_udc_pullup,
+	.udc_start = bdc_udc_start,
+	.udc_stop = bdc_udc_stop,
+};
+
+/* Init the gadget interface and register the udc */
+int bdc_udc_init(struct bdc *bdc)
+{
+	u32 temp;
+	int ret;
+
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	bdc->gadget.ops = &bdc_gadget_ops;
+	bdc->gadget.max_speed = USB_SPEED_SUPER;
+	bdc->gadget.speed = USB_SPEED_UNKNOWN;
+	bdc->gadget.dev.parent = bdc->dev;
+	bdc->gadget.sg_supported = false;
+	bdc->gadget.name = BRCM_BDC_NAME;
+
+	pr_info("%s: " BRCM_BDC_DESC "\n", bdc->gadget.name);
+	ret = devm_request_irq(bdc->dev, bdc->irq, bdc_udc_interrupt,
+				IRQF_SHARED , BRCM_BDC_NAME, bdc);
+	if (ret) {
+		dev_err(bdc->dev,
+			"failed to request irq #%d %d\n",
+			bdc->irq, ret);
+		return ret;
+	}
+
+	ret = bdc_init_ep(bdc);
+	if (ret) {
+		dev_err(bdc->dev, "bdc init ep fail: %d\n", ret);
+		return ret;
+	}
+
+	ret = usb_add_gadget_udc(bdc->dev, &bdc->gadget);
+	if (ret) {
+		dev_err(bdc->dev, "failed to register udc\n");
+		goto err0;
+	}
+	usb_gadget_set_state(&bdc->gadget, USB_STATE_NOTATTACHED);
+	bdc->bdc_ep_array[1]->desc = &bdc_gadget_ep0_desc;
+	/*
+	 * Allocate bd list for ep0 only, ep0 will be enabled on connect
+	 * status report when the speed is known
+	 */
+	ret = bdc_ep_enable(bdc->bdc_ep_array[1]);
+	if (ret) {
+		dev_err(bdc->dev, "fail to enable %s\n",
+						bdc->bdc_ep_array[1]->name);
+		goto err1;
+	}
+	INIT_DELAYED_WORK(&bdc->func_wake_notify, bdc_func_wake_timer);
+	/* Enable Interrupts */
+	temp = bdc_readl(bdc->regs, BDC_BDCSC);
+	temp |= BDC_GIE;
+	bdc_writel(bdc->regs, BDC_BDCSC, temp);
+	return 0;
+err1:
+	usb_del_gadget_udc(&bdc->gadget);
+err0:
+	bdc_free_ep(bdc);
+
+	return ret;
+}
+
+void bdc_udc_exit(struct bdc *bdc)
+{
+	dev_dbg(bdc->dev, "%s()\n", __func__);
+	bdc_ep_disable(bdc->bdc_ep_array[1]);
+	usb_del_gadget_udc(&bdc->gadget);
+	bdc_free_ep(bdc);
+}
diff --git a/drivers/usb/gadget/udc-core.c b/drivers/usb/gadget/udc-core.c
index 9ce0b135c8c8..436c8a64ae32 100644
--- a/drivers/usb/gadget/udc-core.c
+++ b/drivers/usb/gadget/udc-core.c
@@ -106,6 +106,21 @@ EXPORT_SYMBOL_GPL(usb_gadget_unmap_request);
 
 /* ------------------------------------------------------------------------- */
 
+/**
+ * usb_gadget_giveback_request - give the request back to the gadget layer
+ * Context: in_interrupt()
+ *
+ * This is called by device controller drivers in order to return the
+ * completed request back to the gadget layer.
+ */
+void usb_gadget_giveback_request(struct usb_ep *ep,
+		struct usb_request *req)
+{
+	req->complete(ep, req);
+}
+EXPORT_SYMBOL_GPL(usb_gadget_giveback_request);
+
+
 static void usb_gadget_state_work(struct work_struct *work)
 {
 	struct usb_gadget	*gadget = work_to_gadget(work);
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7530468c9a4f..924f07110ff6 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -21,10 +21,28 @@ ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
 	xhci-hcd-y		+= xhci-plat.o
 endif
 
+ifndef CONFIG_MIPS
+usb-brcm-glue-y := usb-brcm.o usb-brcm-common-init.o
+else
+obj-y				+= ehci-brcm.o
+obj-y				+= ohci-brcm.o
+usb-brcm-glue-y := usb-brcm-mips.o
+endif
+
 obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
 
 obj-$(CONFIG_PCI)		+= pci-quirks.o
 
+obj-$(CONFIG_BRCM_USB)		+= usb-brcm-glue.o
+# The order is important here because it controls the order that
+# the drivers will be initialized and we always need to init
+# the drivers in the order XHCI, EHCI and OHCI.
+ifndef CONFIG_MIPS
+obj-$(CONFIG_BRCM_USB_XHCI)	+= xhci-brcm.o
+obj-$(CONFIG_BRCM_USB_EHCI)	+= ehci-brcm.o
+obj-$(CONFIG_BRCM_USB_OHCI)	+= ohci-brcm.o
+endif
+
 obj-$(CONFIG_USB_EHCI_HCD)	+= ehci-hcd.o
 obj-$(CONFIG_USB_EHCI_PCI)	+= ehci-pci.o
 obj-$(CONFIG_USB_EHCI_HCD_PLATFORM)	+= ehci-platform.o
diff --git a/drivers/usb/host/ehci-brcm.c b/drivers/usb/host/ehci-brcm.c
new file mode 100644
index 000000000000..99547e4f4548
--- /dev/null
+++ b/drivers/usb/host/ehci-brcm.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2009 - 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/clk.h>
+
+#include "ehci.h"
+#include "usb-brcm.h"
+
+#define BRCM_DRIVER_DESC "EHCI BRCM driver"
+
+struct brcm_hcd {
+	struct clk *hcd_clk;
+};
+
+static const char brcm_hcd_name[] = "ehci-brcm";
+
+static int (*org_hub_control)(struct usb_hcd *hcd,
+			u16 typeReq, u16 wValue, u16 wIndex,
+			char *buf, u16 wLength);
+
+/* ehci_brcm_wait_for_sof
+ * Wait for start of next microframe, then wait extra delay microseconds
+ */
+static inline void ehci_brcm_wait_for_sof(struct ehci_hcd *ehci, u32 delay)
+{
+	int frame_idx = ehci_readl(ehci, &ehci->regs->frame_index);
+
+	while (frame_idx == ehci_readl(ehci, &ehci->regs->frame_index))
+		;
+	udelay(delay);
+}
+
+/* ehci_brcm_hub_control
+ * Intercept echi-hcd request to complete RESUME and align it to the start
+ * of the next microframe.
+ * If RESUME is complete too late in the microframe, host controller
+ * detects babble on suspended port and resets the port afterwards.
+ * This s/w workaround allows to avoid this problem.
+ * See http://jira.broadcom.com/browse/SWLINUX-1909 for more details
+ */
+static int ehci_brcm_hub_control(
+	struct usb_hcd	*hcd,
+	u16		typeReq,
+	u16		wValue,
+	u16		wIndex,
+	char		*buf,
+	u16		wLength)
+{
+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
+	int		ports = HCS_N_PORTS(ehci->hcs_params);
+	u32 __iomem	*status_reg = &ehci->regs->port_status[
+				(wIndex & 0xff) - 1];
+	unsigned long flags;
+	int retval, irq_disabled = 0;
+
+	/* RESUME is cleared when GetPortStatus() is called 20ms after start
+	  of RESUME */
+	if ((typeReq == GetPortStatus) &&
+	    (wIndex && wIndex <= ports) &&
+	    ehci->reset_done[wIndex-1] &&
+	    time_after_eq(jiffies, ehci->reset_done[wIndex-1]) &&
+	    (ehci_readl(ehci, status_reg) & PORT_RESUME)) {
+		/* to make sure we are not interrupted until RESUME bit
+		  is cleared, disable interrupts on current CPU */
+		ehci_dbg(ehci, "SOF alignment workaround\n");
+		irq_disabled = 1;
+		local_irq_save(flags);
+		ehci_brcm_wait_for_sof(ehci, 5);
+	}
+	retval = (*org_hub_control)(hcd, typeReq, wValue, wIndex, buf, wLength);
+	if (irq_disabled)
+		local_irq_restore(flags);
+	return retval;
+}
+
+static int ehci_brcm_reset(struct usb_hcd *hcd)
+{
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+	ehci->big_endian_mmio = 1;
+
+	ehci->caps = (struct ehci_caps *) hcd->regs;
+	ehci->regs = (struct ehci_regs *) (hcd->regs +
+		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)));
+
+	/* This fixes the lockup during reboot due to prior interrupts */
+	ehci_writel(ehci, CMD_RESET, &ehci->regs->command);
+	mdelay(10);
+
+	/*
+	 * SWLINUX-1705: Avoid OUT packet underflows during high memory
+	 *   bus usage
+	 * port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x90
+	 */
+	ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);
+	ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);
+
+	return ehci_setup(hcd);
+}
+
+static struct hc_driver __read_mostly ehci_brcm_hc_driver;
+
+static const struct ehci_driver_overrides brcm_overrides __initconst = {
+
+	.reset =	ehci_brcm_reset,
+	.extra_priv_size = sizeof(struct brcm_hcd),
+};
+
+static int ehci_brcm_probe(struct platform_device *dev)
+{
+	int err;
+	struct brcm_hcd *brcm_hcd_ptr;
+	struct clk *usb_clk;
+	struct usb_hcd *hcd;
+
+	err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64));
+	if (err)
+		return err;
+
+	/* Hook the hub control routine to work around a bug */
+	if (org_hub_control == NULL)
+		org_hub_control = ehci_brcm_hc_driver.hub_control;
+	ehci_brcm_hc_driver.hub_control = ehci_brcm_hub_control;
+
+	err = brcm_usb_probe(dev, &ehci_brcm_hc_driver, &hcd, &usb_clk);
+	if (!err) {
+		brcm_hcd_ptr = (struct brcm_hcd *)hcd_to_ehci(hcd)->priv;
+		brcm_hcd_ptr->hcd_clk = usb_clk;
+	}
+	return err;
+}
+
+static int ehci_brcm_remove(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ehci(hcd)->priv;
+
+	return brcm_usb_remove(dev, brcm_hcd_ptr->hcd_clk);
+}
+
+#ifdef CONFIG_PM_SLEEP
+
+static int ehci_brcm_suspend(struct device *dev)
+{
+	int ret;
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ehci(hcd)->priv;
+	bool do_wakeup = device_may_wakeup(dev);
+
+	ret = ehci_suspend(hcd, do_wakeup);
+	clk_disable(brcm_hcd_ptr->hcd_clk);
+
+	return ret;
+}
+
+static int ehci_brcm_resume(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ehci(hcd)->priv;
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+	int err;
+
+	err = clk_enable(brcm_hcd_ptr->hcd_clk);
+	if (err)
+		return err;
+
+	/*
+	 * SWLINUX-1705: Avoid OUT packet underflows during high memory
+	 *   bus usage
+	 * port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00
+	 * @ 0x90
+	 */
+	ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);
+	ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);
+
+	ehci_resume(hcd, false);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(ehci_brcm_pm_ops, ehci_brcm_suspend,
+		ehci_brcm_resume);
+
+#ifdef CONFIG_OF
+static const struct of_device_id brcm_ehci_of_match[] = {
+	{ .compatible = "brcm,ehci-brcm", },
+	{ .compatible = "brcm,ehci-brcm-v2", },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, brcm_ehci_of_match);
+#endif /* CONFIG_OF */
+
+static struct platform_driver ehci_brcm_driver = {
+	.probe		= ehci_brcm_probe,
+	.remove		= ehci_brcm_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ehci-brcm",
+		.pm	= &ehci_brcm_pm_ops,
+		.of_match_table = of_match_ptr(brcm_ehci_of_match),
+	}
+};
+
+static int __init ehci_brcm_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " BRCM_DRIVER_DESC "\n", brcm_hcd_name);
+
+	ehci_init_driver(&ehci_brcm_hc_driver, &brcm_overrides);
+	return platform_driver_register(&ehci_brcm_driver);
+}
+module_init(ehci_brcm_init);
+
+static void __exit ehci_brcm_cleanup(void)
+{
+	platform_driver_unregister(&ehci_brcm_driver);
+}
+module_exit(ehci_brcm_cleanup);
+
+MODULE_DESCRIPTION(BRCM_DRIVER_DESC);
+MODULE_AUTHOR("Al Cooper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/ohci-brcm.c b/drivers/usb/host/ohci-brcm.c
new file mode 100644
index 000000000000..383be1c9dbd7
--- /dev/null
+++ b/drivers/usb/host/ohci-brcm.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2009 - 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+
+#include "ohci.h"
+#include "usb-brcm.h"
+
+#define BRCM_DRIVER_DESC "OHCI BRCM driver"
+
+static const char hcd_name[] = "ohci-brcm";
+
+struct brcm_hcd {
+	struct clk *hcd_clk;
+};
+
+static int ohci_brcm_reset(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+
+	ohci->flags |= OHCI_QUIRK_BE_MMIO;
+	return ohci_setup(hcd);
+}
+
+static struct hc_driver __read_mostly ohci_brcm_hc_driver;
+
+static const struct ohci_driver_overrides brcm_overrides __initconst = {
+	.product_desc =	"BRCM OHCI controller",
+	.reset =	ohci_brcm_reset,
+	.extra_priv_size = sizeof(struct brcm_hcd),
+};
+
+static int ohci_brcm_probe(struct platform_device *dev)
+{
+	int err;
+	struct usb_hcd *hcd;
+	struct brcm_hcd *brcm_hcd_ptr;
+	struct clk *usb_clk;
+
+	err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
+	if (err)
+		return err;
+	err = brcm_usb_probe(dev, &ohci_brcm_hc_driver, &hcd, &usb_clk);
+	if (!err) {
+		brcm_hcd_ptr = (struct brcm_hcd *)hcd_to_ohci(hcd)->priv;
+		brcm_hcd_ptr->hcd_clk = usb_clk;
+	}
+	return err;
+}
+
+static int ohci_brcm_remove(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ohci(hcd)->priv;
+
+	return brcm_usb_remove(dev, brcm_hcd_ptr->hcd_clk);
+}
+
+#ifdef CONFIG_PM_SLEEP
+
+static int ohci_brcm_suspend(struct device *dev)
+{
+	int ret;
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ohci(hcd)->priv;
+	bool do_wakeup = device_may_wakeup(dev);
+
+	ret = ohci_suspend(hcd, do_wakeup);
+	clk_disable(brcm_hcd_ptr->hcd_clk);
+	return ret;
+}
+
+static int ohci_brcm_resume(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct brcm_hcd *brcm_hcd_ptr =
+		(struct brcm_hcd *)hcd_to_ohci(hcd)->priv;
+	int err;
+
+	err = clk_enable(brcm_hcd_ptr->hcd_clk);
+	if (err)
+		return err;
+	ohci_resume(hcd, false);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(ohci_brcm_pm_ops, ohci_brcm_suspend,
+		ohci_brcm_resume);
+
+#ifdef CONFIG_OF
+static const struct of_device_id brcm_ohci_of_match[] = {
+	{ .compatible = "brcm,ohci-brcm", },
+	{ .compatible = "brcm,ohci-brcm-v2", },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, brcm_ohci_of_match);
+#endif /* CONFIG_OF */
+
+static struct platform_driver ohci_brcm_driver = {
+	.probe		= ohci_brcm_probe,
+	.remove		= ohci_brcm_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ohci-brcm",
+		.pm	= &ohci_brcm_pm_ops,
+		.of_match_table = of_match_ptr(brcm_ohci_of_match),
+	}
+};
+
+static int __init ohci_brcm_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " BRCM_DRIVER_DESC "\n", hcd_name);
+
+	ohci_init_driver(&ohci_brcm_hc_driver, &brcm_overrides);
+	return platform_driver_register(&ohci_brcm_driver);
+}
+module_init(ohci_brcm_init);
+
+static void __exit ohci_brcm_cleanup(void)
+{
+	platform_driver_unregister(&ohci_brcm_driver);
+}
+module_exit(ohci_brcm_cleanup);
+
+MODULE_DESCRIPTION(BRCM_DRIVER_DESC);
+MODULE_AUTHOR("Al Cooper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/usb-brcm-common-init.c b/drivers/usb/host/usb-brcm-common-init.c
new file mode 100644
index 000000000000..f2b482a6e018
--- /dev/null
+++ b/drivers/usb/host/usb-brcm-common-init.c
@@ -0,0 +1,524 @@
+/*
+ * Copyright (C) 2014-2016 Broadcom Ltd.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * This module is used by both the bootloader and Linux and
+ * contains USB initialization for power up and S3 resume.
+ */
+
+#if defined(_BOLT_)
+#include "lib_types.h"
+#include "common.h"
+#include "bchp_common.h"
+#include "bchp_usb_ctrl.h"
+#include "bchp_sun_top_ctrl.h"
+#include "timer.h"
+#define msleep bolt_msleep
+#define udelay bolt_usleep
+#else
+#include <linux/delay.h>
+#include <linux/brcmstb/brcmstb.h>
+#endif
+
+#include "usb-brcm-common-init.h"
+
+#define USB_CTRL_REG(base, reg)	(base + BCHP_USB_CTRL_##reg - \
+		BCHP_USB_CTRL_SETUP)
+#define USB_CTRL_MASK(reg, field) (BCHP_USB_CTRL_##reg##_##field##_MASK)
+#define USB_CTRL_SET(base, reg, mask) DEV_SET(USB_CTRL_REG(base, reg),	\
+						USB_CTRL_MASK(reg, mask))
+#define USB_CTRL_UNSET(base, reg, mask) DEV_UNSET(USB_CTRL_REG(base, reg),  \
+						USB_CTRL_MASK(reg, mask))
+#define USB_XHCI_EC_REG(base, reg) (base + BCHP_USB_XHCI_EC_##reg - \
+		BCHP_USB_XHCI_EC_REG_START)
+
+#define MDIO_USB2	0
+#define MDIO_USB3	(1 << 31)
+
+#define USB_CTRL_SETUP_CONDITIONAL_BITS (	\
+		USB_CTRL_MASK(SETUP, BABO) |	\
+		USB_CTRL_MASK(SETUP, FNHW) |	\
+		USB_CTRL_MASK(SETUP, FNBO) |	\
+		USB_CTRL_MASK(SETUP, WABO) |	\
+		USB_CTRL_MASK(SETUP, IOC)  |	\
+		USB_CTRL_MASK(SETUP, IPP))
+
+#ifdef __LITTLE_ENDIAN
+#define ENDIAN_SETTINGS ( \
+		USB_CTRL_MASK(SETUP, BABO) |	\
+		USB_CTRL_MASK(SETUP, FNHW))
+#else
+#define ENDIAN_SETTINGS ( \
+		USB_CTRL_MASK(SETUP, FNHW) |	 \
+		USB_CTRL_MASK(SETUP, FNBO) |	 \
+		USB_CTRL_MASK(SETUP, WABO))
+#endif
+
+static uint32_t usb_mdio_read(uintptr_t ctrl_base, uint32_t reg, int mode)
+{
+	uint32_t data;
+
+	data = (reg << 16) | mode;
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+	data |= (1 << 24);
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+	data &= ~(1 << 24);
+	udelay(10);
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+	udelay(10);
+
+	return DEV_RD(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
+}
+
+static void usb_mdio_write(uintptr_t ctrl_base, uint32_t reg,
+			uint32_t val, int mode)
+{
+	uint32_t data;
+
+	data = (reg << 16) | val | mode;
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+	data |= (1 << 25);
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+	data &= ~(1 << 25);
+	udelay(10);
+	DEV_WR(USB_CTRL_REG(ctrl_base, MDIO), data);
+}
+
+
+static void usb_phy_ldo_fix(uintptr_t ctrl_base)
+{
+	/* first disable FSM but also leave it that way */
+	/* to allow normal suspend/resume */
+	DEV_UNSET(USB_CTRL_REG(ctrl_base, UTMI_CTL_1),
+		USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN_P1) |
+		USB_CTRL_MASK(UTMI_CTL_1, POWER_UP_FSM_EN));
+
+	/* reset USB 2.0 PLL */
+	USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
+	msleep(1);
+	USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
+	msleep(10);
+
+}
+
+
+static void usb2_eye_fix(uintptr_t ctrl_base)
+{
+	/* Increase USB 2.0 TX level to meet spec requirement */
+	usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
+	usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
+}
+
+
+static void usb3_pll_fix(uintptr_t ctrl_base)
+{
+	/* Set correct window for PLL lock detect */
+	usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
+}
+
+
+static void usb3_enable_pipe_reset(uintptr_t ctrl_base)
+{
+	uint32_t val;
+
+	/* Re-enable USB 3.0 pipe reset */
+	usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
+	val = usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
+	usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
+}
+
+
+static void usb3_enable_sigdet(uintptr_t ctrl_base)
+{
+	uint32_t val, ofs;
+	int ii;
+
+	ofs = 0;
+	for (ii = 0; ii < 2; ++ii) {
+		/* Set correct default for sigdet */
+		usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs), MDIO_USB3);
+		val = usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
+		val = (val & ~0x800f) | 0x800d;
+		usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
+		ofs = 0x1000;
+	}
+}
+
+
+static void usb3_enable_skip_align(uintptr_t ctrl_base)
+{
+	uint32_t val, ofs;
+	int ii;
+
+	ofs = 0;
+	for (ii = 0; ii < 2; ++ii) {
+		/* Set correct default for SKIP align */
+		usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs), MDIO_USB3);
+		val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
+		usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
+		ofs = 0x1000;
+	}
+}
+
+
+static void usb3_unfreeze_aeq(uintptr_t ctrl_base)
+{
+	uint32_t val, ofs;
+	int ii;
+
+	ofs = 0;
+	for (ii = 0; ii < 2; ++ii) {
+		/* Let EQ freeze after TSEQ */
+		usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs), MDIO_USB3);
+		val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
+		val &= ~0x0008;
+		usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
+		ofs = 0x1000;
+	}
+}
+
+
+static void usb3_pll_54Mhz(uintptr_t ctrl_base)
+{
+#if defined(CONFIG_BCM7271A0) || defined(CONFIG_BCM7268A0) || \
+	defined(CONFIG_BCM7364)
+	/*
+	 * On the 7271a0 and 7268a0, the reference clock for the
+	 * 3.0 PLL has been changed from 50MHz to 54MHz so the
+	 * PLL needs to be reprogramed. Later chips will have
+	 * the PLL programmed correctly on power-up.
+	 * See SWLINUX-4006.
+	 *
+	 * On the 7364C0, the reference clock for the
+	 * 3.0 PLL has been changed from 50MHz to 54MHz to
+	 * work around a MOCA issue.
+	 * See SWLINUX-4169.
+	 */
+	uint32_t ofs;
+	int ii;
+
+#if defined(CONFIG_BCM7364)
+	/* Only for 7364C0 and later */
+	if ((BDEV_RD(BCHP_SUN_TOP_CTRL_PRODUCT_ID) & 0xff) < 0x20)
+		return;
+#endif
+
+	/* set USB 3.0 PLL to accept 54Mhz reference clock */
+	USB_CTRL_UNSET(ctrl_base, USB30_CTL1, phy3_pll_seq_start);
+
+	usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
+	usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
+
+	/* both ports */
+	ofs = 0;
+	for (ii = 0; ii < 2; ++ii) {
+		usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs), MDIO_USB3);
+		usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
+		usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
+		usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs), MDIO_USB3);
+		usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
+		ofs = 0x1000;
+	}
+
+	/* restart  PLL sequence */
+	USB_CTRL_SET(ctrl_base, USB30_CTL1, phy3_pll_seq_start);
+	msleep(1);
+#endif
+}
+
+
+static void usb3_ssc_enable(uintptr_t ctrl_base)
+{
+	uint32_t val;
+
+	/* Enable USB 3.0 TX spread spectrum */
+	usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
+	val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
+	usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
+
+	/* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
+	 * which should have been adequate. However, due to a bug in the
+	 * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
+	 */
+	usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
+	val = usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
+	usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
+}
+
+
+static void usb3_phy_workarounds(uintptr_t ctrl_base)
+{
+	usb3_pll_fix(ctrl_base);
+	usb3_pll_54Mhz(ctrl_base);
+	usb3_ssc_enable(ctrl_base);
+	usb3_enable_pipe_reset(ctrl_base);
+	usb3_enable_sigdet(ctrl_base);
+	usb3_enable_skip_align(ctrl_base);
+	usb3_unfreeze_aeq(ctrl_base);
+}
+
+
+static void memc_fix(uintptr_t ctrl_base)
+{
+#if defined(CONFIG_BCM7445D0) || defined(CONFIG_BCM7445E0)
+	/*
+	 * This is a workaround for HW7445-1869 where a DMA write ends up
+	 * doing a read pre-fetch after the end of the DMA buffer. This
+	 * causes a problem when the DMA buffer is at the end of physical
+	 * memory, causing the pre-fetch read to access non-existent memory,
+	 * and the chip bondout has MEMC2 disabled. When the pre-fetch read
+	 * tries to use the disabled MEMC2, it hangs the bus. The workaround
+	 * is to disable MEMC2 access in the usb controller which avoids
+	 * the hang.
+	 */
+	uint32_t prid;
+
+	prid = BDEV_RD(BCHP_SUN_TOP_CTRL_PRODUCT_ID) & 0xfffff000;
+	switch (prid) {
+	case 0x72520000:
+	case 0x74480000:
+	case 0x74490000:
+	case 0x07252000:
+	case 0x07448000:
+	case 0x07449000:
+		USB_CTRL_UNSET(ctrl_base, SETUP, scb2_en);
+	}
+#endif
+}
+
+#if defined(CONFIG_BCM74371A0)
+#if defined(_BOLT_)
+#include "bchp_usb_xhci_ec.h"
+#endif
+static void usb3_otp_fix(uintptr_t ctrl_base, uintptr_t xhci_ec_base)
+{
+	uintptr_t val;
+
+	if (xhci_ec_base == 0)
+		return;
+	DEV_WR(USB_XHCI_EC_REG(xhci_ec_base, IRAADR), 0xa20c);
+	val = DEV_RD(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
+
+	/* set cfg_pick_ss_lock */
+	val |= (1 << 27);
+	DEV_WR(USB_XHCI_EC_REG(xhci_ec_base, IRADAT), val);
+
+	/* Reset USB 3.0 PHY for workaround to take effect */
+	USB_CTRL_UNSET(ctrl_base, USB30_CTL1, phy3_resetb);
+	USB_CTRL_SET(ctrl_base, USB30_CTL1, phy3_resetb);
+}
+#else
+static void usb3_otp_fix(uintptr_t ctrl_base, uintptr_t xhci_ec_regs)
+{
+}
+#endif
+
+
+static void xhci_soft_reset(uintptr_t ctrl, int on_off)
+{
+	/* Assert reset */
+	if (on_off) {
+#if defined(BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK)
+		USB_CTRL_UNSET(ctrl, USB_PM, xhc_soft_resetb);
+#else
+		USB_CTRL_UNSET(ctrl, USB30_CTL1, xhc_soft_resetb);
+#endif
+	}
+	/* De-assert reset */
+	else {
+#if defined(BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK)
+		USB_CTRL_SET(ctrl, USB_PM, xhc_soft_resetb);
+#else
+		USB_CTRL_SET(ctrl, USB30_CTL1, xhc_soft_resetb);
+#endif
+	}
+}
+
+
+void brcm_usb_common_init(struct brcm_usb_common_init_params *params)
+{
+	uint32_t reg;
+	uintptr_t ctrl = params->ctrl_regs;
+	int change_ipp = 0;
+
+	xhci_soft_reset(ctrl, 1);
+#if defined(CONFIG_BCM7366)
+	/*
+	 * The PHY3_SOFT_RESETB bits default to the wrong state.
+	 */
+	DEV_SET(USB_CTRL_REG(ctrl, USB30_PCTL),
+		USB_CTRL_MASK(USB30_PCTL, PHY3_SOFT_RESETB_P1) |
+		USB_CTRL_MASK(USB30_PCTL, PHY3_SOFT_RESETB));
+#endif
+#if defined(CONFIG_BCM7366C0)
+	/*
+	 * Don't enable this so the memory controller doesn't read
+	 * into memory holes. NOTE: This bit is low true  on 7366C0.
+	 */
+	DEV_SET(USB_CTRL_REG(ctrl, EBRIDGE),
+		USB_CTRL_MASK(EBRIDGE, ESTOP_SCB_REQ));
+#endif
+
+	/* Take USB out of power down */
+#if defined(BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK)
+	USB_CTRL_UNSET(ctrl, PLL_CTL, PLL_IDDQ_PWRDN);
+	/* 1 millisecond - for USB clocks to settle down */
+	msleep(1);
+#endif
+#if defined(BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK)
+	USB_CTRL_UNSET(ctrl, USB_PM, USB_PWRDN);
+	/* 1 millisecond - for USB clocks to settle down */
+	msleep(1);
+#endif
+#if defined(BCHP_USB_CTRL_USB_PM_soft_reset_MASK)
+	/* 7271a0. */
+	USB_CTRL_UNSET(ctrl, USB_PM, soft_reset);
+	msleep(1);
+#endif
+
+#if defined(BCHP_USB_CTRL_USB30_CTL1_usb3_ipp_MASK)
+	/* Starting with the 7445d0, there are no longer separate 3.0
+	 * versions of IOC and IPP.
+	 */
+	if (params->ioc)
+		USB_CTRL_SET(ctrl, USB30_CTL1, usb3_ioc);
+	if (params->ipp == 1)
+		USB_CTRL_SET(ctrl, USB30_CTL1, usb3_ipp);
+#endif
+
+#if !defined(CONFIG_BCM74371A0) && !defined(CONFIG_BCM7364)
+	/*
+	 * HW7439-637: 7439a0 and its derivatives do not have large enough
+	 * descriptor storage for this.
+	 */
+	USB_CTRL_SET(ctrl, SETUP, ss_ehci64bit_en);
+#endif
+
+#if defined(BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK)
+	/*
+	 * Kick start USB3 PHY
+	 * Make sure it's low to insure a rising edge.
+	 */
+	USB_CTRL_UNSET(ctrl, USB30_CTL1, phy3_pll_seq_start);
+	USB_CTRL_SET(ctrl, USB30_CTL1, phy3_pll_seq_start);
+#endif
+
+	/* Block auto PLL suspend by USB2 PHY */
+	USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
+
+	usb_phy_ldo_fix(ctrl);
+	usb2_eye_fix(ctrl);
+	if (params->has_xhci)
+		usb3_phy_workarounds(ctrl);
+
+	/* Setup the endian bits */
+	reg = DEV_RD(USB_CTRL_REG(ctrl, SETUP));
+	reg &= ~USB_CTRL_SETUP_CONDITIONAL_BITS;
+	reg |= ENDIAN_SETTINGS;
+
+#if defined(CONFIG_BCM7364)
+	if ((BDEV_RD(BCHP_SUN_TOP_CTRL_PRODUCT_ID) == 0x73640000))
+		/* Suppress overcurrent indication from USB30 ports for A0 */
+		reg |= USB_CTRL_MASK(SETUP, OC3_DISABLE);
+#endif
+
+#if defined(BCHP_USB_CTRL_SETUP_strap_ipp_sel_MASK)
+	if (params->ipp != 2)
+		/* override ipp strap pin (if it exists) */
+		reg &= ~(USB_CTRL_MASK(SETUP, strap_ipp_sel));
+#endif
+	/*
+	 * Make sure the the second and third memory controller
+	 * interfaces are enabled, if they exist.
+	 */
+#if defined(BCHP_USB_CTRL_SETUP_scb1_en_MASK)
+	reg |= USB_CTRL_MASK(SETUP, scb1_en);
+#endif
+#if defined(BCHP_USB_CTRL_SETUP_scb2_en_MASK)
+	reg |= USB_CTRL_MASK(SETUP, scb2_en);
+#endif
+
+	/* Override the default OC and PP polarity */
+	if (params->ioc)
+		reg |= USB_CTRL_MASK(SETUP, IOC);
+	if ((params->ipp == 1) && ((reg & USB_CTRL_MASK(SETUP, IPP)) == 0)) {
+		change_ipp = 1;
+		reg |= USB_CTRL_MASK(SETUP, IPP);
+	}
+	DEV_WR(USB_CTRL_REG(ctrl, SETUP), reg);
+
+	/*
+	 * If we're changing IPP, make sure power is off long enough
+	 * to turn off any connected devices.
+	 */
+	if (change_ipp)
+		msleep(50);
+	memc_fix(ctrl);
+	if (params->has_xhci) {
+		xhci_soft_reset(ctrl, 0);
+		usb3_otp_fix(ctrl, params->xhci_ec_regs);
+	}
+#ifdef BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_MASK
+	reg = DEV_RD(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
+	reg &= ~BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_MASK;
+	reg |= params->device_mode;
+	DEV_WR(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1), reg);
+#endif
+#ifdef BCHP_USB_CTRL_USB_PM_bdc_soft_resetb_MASK
+	switch (params->device_mode) {
+	case USB_CTLR_DEVICE_OFF:
+		USB_CTRL_UNSET(ctrl, USB_PM, bdc_soft_resetb);
+		break;
+	default:
+		USB_CTRL_SET(ctrl, USB_PM, bdc_soft_resetb);
+		break;
+	}
+#ifdef BCHP_USB_CTRL_SETUP_strap_cc_drd_mode_enable_sel_MASK
+	/* Never use the strap, it's going away. */
+	USB_CTRL_UNSET(ctrl, SETUP, strap_cc_drd_mode_enable_sel);
+#endif
+#ifdef BCHP_USB_CTRL_SETUP_cc_drd_mode_enable_MASK
+	if (params->device_mode == USB_CTLR_DEVICE_TYPEC_PD)
+		USB_CTRL_SET(ctrl, SETUP, cc_drd_mode_enable);
+	else
+		USB_CTRL_UNSET(ctrl, SETUP, cc_drd_mode_enable);
+
+#endif
+#endif
+}
+
+EXPORT_SYMBOL(brcm_usb_common_init);
diff --git a/drivers/usb/host/usb-brcm-common-init.h b/drivers/usb/host/usb-brcm-common-init.h
new file mode 100644
index 000000000000..c97eda2cb21b
--- /dev/null
+++ b/drivers/usb/host/usb-brcm-common-init.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014-2015 Broadcom Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _USB_BRCM_COMMON_INIT_H
+#define _USB_BRCM_COMMON_INIT_H
+
+#define USB_CTLR_DEVICE_OFF 0
+#define USB_CTLR_DEVICE_ON 1
+#define USB_CTLR_DEVICE_DUAL 2
+#define USB_CTLR_DEVICE_TYPEC_PD 3
+
+struct  brcm_usb_common_init_params {
+	uintptr_t ctrl_regs;
+	int ioc;
+	int ipp;
+	int has_xhci;
+	int device_mode;
+	uintptr_t xhci_ec_regs;
+};
+
+void brcm_usb_common_init(struct  brcm_usb_common_init_params *params);
+
+#endif /* _USB_BRCM_COMMON_INIT_H */
diff --git a/drivers/usb/host/usb-brcm-mips.c b/drivers/usb/host/usb-brcm-mips.c
new file mode 100644
index 000000000000..0f5a1c45934e
--- /dev/null
+++ b/drivers/usb/host/usb-brcm-mips.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+#include <linux/usb/hcd.h>
+#else
+#include "../core/hcd.h"
+#endif
+
+#define MAX_HCD			8
+
+static struct clk *usb_clk;
+
+/***********************************************************************
+ * Library functions
+ ***********************************************************************/
+
+int brcm_usb_probe(struct platform_device *pdev,
+		const struct hc_driver *hc_driver,
+		struct usb_hcd **hcdptr,
+		struct clk **hcd_clk_ptr)
+{
+	struct resource *res_mem;
+	struct usb_hcd *hcd;
+	int irq;
+	struct clk *clk;
+	int err;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	if (!usb_clk) {
+		clk = clk_get(NULL, "usb");
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Error getting Clock\n");
+			return PTR_ERR(clk);
+		}
+		usb_clk = clk;
+	}
+	*hcd_clk_ptr = usb_clk;
+	clk_enable(usb_clk);
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem) {
+		dev_err(&pdev->dev, "platform_get_resource error.\n");
+		return -ENODEV;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "platform_get_irq error.\n");
+		return -ENODEV;
+	}
+
+	/* initialize hcd */
+	hcd = usb_create_hcd(hc_driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		dev_err(&pdev->dev, "Failed to create hcd\n");
+		clk_disable(usb_clk);
+		return -ENOMEM;
+	}
+	*hcdptr = hcd;
+	hcd->rsrc_start = res_mem->start;
+	hcd->rsrc_len = resource_size(res_mem);
+	hcd->regs = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(hcd->regs)) {
+		err = PTR_ERR(hcd->regs);
+		goto err_put_hcd;
+	}
+	err = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+	if (err)
+		goto err_put_hcd;
+
+	usb_disable_autosuspend(hcd->self.root_hub);
+	platform_set_drvdata(pdev, hcd);
+	return err;
+
+err_put_hcd:
+	clk_disable(usb_clk);
+	usb_put_hcd(hcd);
+
+	return err;
+}
+EXPORT_SYMBOL(brcm_usb_probe);
+
+int brcm_usb_remove(struct platform_device *pdev, struct clk *hcd_clk)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	usb_remove_hcd(hcd);
+	usb_put_hcd(hcd);
+	clk_disable(hcd_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_usb_remove);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom USB common functions");
diff --git a/drivers/usb/host/usb-brcm-mips.h b/drivers/usb/host/usb-brcm-mips.h
new file mode 100644
index 000000000000..3650d1559d87
--- /dev/null
+++ b/drivers/usb/host/usb-brcm-mips.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _USB_BRCM_H
+#define _USB_BRCM_H
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/mmdebug.h>
+#include <linux/io.h>
+#include <linux/version.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+#include <linux/usb/hcd.h>
+#else
+#include "../core/hcd.h"
+#endif
+
+/* force non-byteswapping reads/writes on LE and BE alike */
+#define CONFIG_USB_EHCI_BIG_ENDIAN_MMIO		1
+#define CONFIG_USB_OHCI_BIG_ENDIAN_MMIO		1
+#undef readl_be
+#undef writel_be
+#define readl_be(x)				__raw_readl(x)
+#define writel_be(x, y)				__raw_writel(x, y)
+
+/* stock Linux drivers assume USB is always PCI-based on platforms with PCI */
+#undef CONFIG_PCI
+
+extern int brcm_usb_probe(struct platform_device *, const char *,
+	const struct hc_driver *);
+extern int brcm_usb_remove(struct platform_device *pdev);
+extern void brcm_usb_suspend(struct usb_hcd *hcd);
+extern void brcm_usb_resume(struct usb_hcd *hcd);
+extern int brcm_usb_is_inactive(void);
+
+#endif /* _USB_BRCM_H */
diff --git a/drivers/usb/host/usb-brcm.c b/drivers/usb/host/usb-brcm.c
new file mode 100644
index 000000000000..0bea1abe32bc
--- /dev/null
+++ b/drivers/usb/host/usb-brcm.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/usb/hcd.h>
+
+#include "usb-brcm-common-init.h"
+
+struct brcm_usb_instance {
+	void __iomem		*ctrl_regs;
+	void __iomem		*xhci_ec_regs;
+	int			ioc;
+	int			ipp;
+	int			has_xhci;
+	int			device_mode;
+	struct clk		*usb_clk;
+};
+
+static const char msg_clk_not_found[] = "Clock not found in Device Tree\n";
+
+/***********************************************************************
+ * Library functions
+ ***********************************************************************/
+
+int brcm_usb_probe(struct platform_device *pdev,
+		const struct hc_driver *hc_driver,
+		struct usb_hcd **hcdptr,
+		struct clk **hcd_clk_ptr)
+{
+	struct resource *res_mem;
+	int irq;
+	struct usb_hcd *hcd;
+	struct device_node *dn = pdev->dev.of_node;
+	struct clk *usb_clk;
+	int err;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem) {
+		dev_err(&pdev->dev, "platform_get_resource error.\n");
+		return -ENODEV;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "platform_get_irq error.\n");
+		return -ENODEV;
+	}
+
+	usb_clk = of_clk_get_by_name(dn, "sw_usb");
+	if (IS_ERR(usb_clk)) {
+		dev_err(&pdev->dev, msg_clk_not_found);
+		usb_clk = NULL;
+	}
+	err = clk_prepare_enable(usb_clk);
+	if (err)
+		return err;
+	*hcd_clk_ptr = usb_clk;
+
+	/* initialize hcd */
+	hcd = usb_create_hcd(hc_driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		dev_err(&pdev->dev, "Failed to create hcd\n");
+		clk_disable(usb_clk);
+		return -ENOMEM;
+	}
+	*hcdptr = hcd;
+	hcd->rsrc_start = res_mem->start;
+	hcd->rsrc_len = resource_size(res_mem);
+
+	hcd->regs = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(hcd->regs)) {
+		err = PTR_ERR(hcd->regs);
+		goto err_put_hcd;
+	}
+	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
+	if (err)
+		goto err_put_hcd;
+
+	device_wakeup_enable(hcd->self.controller);
+	platform_set_drvdata(pdev, hcd);
+	return err;
+
+err_put_hcd:
+	clk_disable(usb_clk);
+	usb_put_hcd(hcd);
+
+	return err;
+}
+EXPORT_SYMBOL(brcm_usb_probe);
+
+int brcm_usb_remove(struct platform_device *pdev, struct clk *hcd_clk)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	usb_remove_hcd(hcd);
+	usb_put_hcd(hcd);
+	clk_disable(hcd_clk);
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_usb_remove);
+
+
+#ifdef CONFIG_OF
+
+/***********************************************************************
+ * DT support for USB instances
+ ***********************************************************************/
+
+static int brcm_usb_instance_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct resource ctrl_res;
+	struct resource xhci_ec_res;
+	const u32 *prop;
+	struct brcm_usb_instance *priv;
+	struct device_node *node;
+	struct brcm_usb_common_init_params params;
+	int err;
+	const char *device_mode;
+
+	/*
+	 * if there is an alias for "usbphy0", it means we have the new
+	 * style USB device tree without the USB wrapper.
+	 */
+	node = of_find_node_by_path("/aliases");
+	if (node) {
+		const char *usbphy = of_get_property(node, "usbphy0", NULL);
+		if (usbphy)
+			return -ENODEV;
+	}
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	dev_set_drvdata(&pdev->dev, priv);
+
+	if (of_address_to_resource(dn, 0, &ctrl_res)) {
+		dev_err(&pdev->dev, "can't get USB_CTRL base address\n");
+		return -EINVAL;
+	}
+	priv->ctrl_regs = devm_request_and_ioremap(&pdev->dev, &ctrl_res);
+	if (!priv->ctrl_regs) {
+		dev_err(&pdev->dev, "can't map register space\n");
+		return -EINVAL;
+	}
+	if (!of_address_to_resource(dn, 1, &xhci_ec_res))
+		priv->xhci_ec_regs =
+			devm_request_and_ioremap(&pdev->dev, &xhci_ec_res);
+	prop = of_get_property(dn, "ipp", NULL);
+	if (prop)
+		priv->ipp = be32_to_cpup(prop);
+	prop = of_get_property(dn, "ioc", NULL);
+	if (prop)
+		priv->ioc = be32_to_cpup(prop);
+	err = of_property_read_string(dn, "device", &device_mode);
+	priv->device_mode = USB_CTLR_DEVICE_OFF;
+	if (err == 0) {
+		if (strcmp(device_mode, "on") == 0)
+			priv->device_mode = USB_CTLR_DEVICE_ON;
+		if (strcmp(device_mode, "dual") == 0)
+			priv->device_mode = USB_CTLR_DEVICE_DUAL;
+	}
+	node = of_find_compatible_node(dn, NULL, "xhci-platform");
+	of_node_put(node);
+	priv->has_xhci = node != NULL;
+	priv->usb_clk = of_clk_get_by_name(dn, "sw_usb");
+	if (IS_ERR(priv->usb_clk)) {
+		dev_err(&pdev->dev, msg_clk_not_found);
+		priv->usb_clk = NULL;
+	}
+	err = clk_prepare_enable(priv->usb_clk);
+	if (err)
+		return err;
+	params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+	params.ioc = priv->ioc;
+	params.ipp = priv->ipp;
+	params.has_xhci = priv->has_xhci;
+	params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+	params.device_mode = priv->device_mode;
+	brcm_usb_common_init(&params);
+	return of_platform_populate(dn, NULL, NULL, NULL);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int brcm_usb_instance_suspend(struct device *dev)
+{
+	struct brcm_usb_instance *priv = dev_get_drvdata(dev);
+
+	clk_disable(priv->usb_clk);
+	return 0;
+}
+
+static int brcm_usb_instance_resume(struct device *dev)
+{
+	struct brcm_usb_instance *priv = dev_get_drvdata(dev);
+	struct brcm_usb_common_init_params params;
+
+	clk_enable(priv->usb_clk);
+	params.ctrl_regs = (uintptr_t)priv->ctrl_regs;
+	params.ioc = priv->ioc;
+	params.ipp = priv->ipp;
+	params.has_xhci = priv->has_xhci;
+	params.xhci_ec_regs = (uintptr_t)priv->xhci_ec_regs;
+	params.device_mode = priv->device_mode;
+	brcm_usb_common_init(&params);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(brcm_usb_instance_pm_ops, brcm_usb_instance_suspend,
+		brcm_usb_instance_resume);
+
+static const struct of_device_id brcm_usb_instance_match[] = {
+	{ .compatible = "brcm,usb-instance" },
+	{},
+};
+
+static struct platform_driver brcm_usb_instance_driver = {
+	.driver = {
+		.name = "usb-brcm",
+		.bus = &platform_bus_type,
+		.of_match_table = of_match_ptr(brcm_usb_instance_match),
+		.pm = &brcm_usb_instance_pm_ops,
+	}
+};
+
+/*
+ * We really don't want to try to undo of_platform_populate(), so it
+ * is not possible to unbind/deregister this driver.
+ */
+static int __init brcm_usb_instance_init(void)
+{
+	return platform_driver_probe(&brcm_usb_instance_driver,
+				     brcm_usb_instance_probe);
+}
+module_init(brcm_usb_instance_init);
+
+#endif
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom USB common functions");
diff --git a/drivers/usb/host/usb-brcm.h b/drivers/usb/host/usb-brcm.h
new file mode 100644
index 000000000000..638ab71d59a6
--- /dev/null
+++ b/drivers/usb/host/usb-brcm.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _USB_BRCM_H
+#define _USB_BRCM_H
+
+#include <linux/usb.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/usb/hcd.h>
+
+/* force non-byteswapping reads/writes on LE and BE alike */
+#define CONFIG_USB_EHCI_BIG_ENDIAN_MMIO		1
+#define CONFIG_USB_OHCI_BIG_ENDIAN_MMIO		1
+#undef readl_be
+#undef writel_be
+#define readl_be(x)				__raw_readl(x)
+#define writel_be(x, y)				__raw_writel(x, y)
+
+extern int brcm_usb_probe(struct platform_device *pdev,
+			const struct hc_driver *hc_driver,
+			struct usb_hcd **hcdptr,
+			struct clk **hcd_clk_ptr);
+extern int brcm_usb_remove(struct platform_device *pdev, struct clk *hcd_clk);
+
+#endif /* _USB_BRCM_H */
diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c
new file mode 100644
index 000000000000..6a6131bcd060
--- /dev/null
+++ b/drivers/usb/host/xhci-brcm.c
@@ -0,0 +1,205 @@
+/*
+ * xhci-brcm.c - xHCI host controller driver platform Bus Glue.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * A lot of code borrowed from the Linux xHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include "xhci.h"
+#include "usb-brcm.h"
+
+static struct hc_driver __read_mostly xhci_brcm_hc_driver;
+
+
+#define BRCM_DRIVER_DESC "xHCI BRCM driver"
+#define BRCM_DRIVER_NAME "xhci-brcm"
+
+struct brcm_hcd {
+	/*
+	 * xhci_hcd_ptr must always be the first entry
+	 * because the XHCI driver expects this pointer
+	 * to be at the beginning of the hcd_priv area
+	 * in the usb_hcd structure.
+	 */
+	struct xhci_hcd *xhci_hcd_ptr;
+	struct clk *hcd_clk;
+};
+
+static struct brcm_hcd *hcd_to_brcm(struct usb_hcd *hcd)
+{
+	return (struct brcm_hcd *)hcd->hcd_priv;
+}
+
+static void xhci_brcm_quirks(struct device *dev, struct xhci_hcd *xhci)
+{
+	/*
+	 * As of now platform drivers don't provide MSI support so we ensure
+	 * here that the generic code does not try to make a pci_dev from our
+	 * dev struct in order to setup MSI
+	 */
+	xhci->quirks |= XHCI_PLAT;
+
+	/*
+	 * The Broadcom XHCI core does not support save/restore state
+	 * so we need to reset on resume.
+	 */
+	xhci->quirks |= XHCI_RESET_ON_RESUME;
+}
+
+/* called during probe() after chip reset completes */
+static int xhci_brcm_setup(struct usb_hcd *hcd)
+{
+	return xhci_gen_setup(hcd, xhci_brcm_quirks);
+}
+
+static int xhci_brcm_probe(struct platform_device *pdev)
+{
+	struct xhci_hcd		*xhci;
+	struct usb_hcd		*hcd;
+	struct clk		*usb_clk;
+	struct brcm_hcd		*brcm_hcd_ptr;
+	int			ret;
+
+	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+
+	ret = brcm_usb_probe(pdev, &xhci_brcm_hc_driver, &hcd, &usb_clk);
+	if (ret)
+		return ret;
+	brcm_hcd_ptr = hcd_to_brcm(hcd);
+	brcm_hcd_ptr->hcd_clk = usb_clk;
+
+	/* USB 2.0 roothub is stored in the platform_device now. */
+	hcd = platform_get_drvdata(pdev);
+	xhci = hcd_to_xhci(hcd);
+	xhci->shared_hcd = usb_create_shared_hcd(&xhci_brcm_hc_driver,
+			&pdev->dev, dev_name(&pdev->dev), hcd);
+	if (!xhci->shared_hcd) {
+		ret = -ENOMEM;
+		goto dealloc_usb2_hcd;
+	}
+
+	/*
+	 * Set the xHCI pointer before xhci_brcm_setup() (aka hcd_driver.reset)
+	 * is called by usb_add_hcd().
+	 */
+	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
+
+	ret = usb_add_hcd(xhci->shared_hcd, hcd->irq, IRQF_SHARED);
+	if (ret)
+		goto put_usb3_hcd;
+	brcm_hcd_ptr = hcd_to_brcm(hcd);
+	brcm_hcd_ptr->hcd_clk = usb_clk;
+
+	return 0;
+
+put_usb3_hcd:
+	usb_put_hcd(xhci->shared_hcd);
+
+dealloc_usb2_hcd:
+	usb_remove_hcd(hcd);
+	usb_put_hcd(hcd);
+
+	return ret;
+}
+
+static int xhci_brcm_remove(struct platform_device *dev)
+{
+	struct usb_hcd	*hcd = platform_get_drvdata(dev);
+	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+	struct brcm_hcd *brcm_hcd_ptr = hcd_to_brcm(hcd);
+
+	usb_remove_hcd(xhci->shared_hcd);
+	usb_put_hcd(xhci->shared_hcd);
+
+	brcm_usb_remove(dev, brcm_hcd_ptr->hcd_clk);
+	kfree(xhci);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int xhci_brcm_suspend(struct device *dev)
+{
+	int ret;
+	struct usb_hcd	*hcd = dev_get_drvdata(dev);
+	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+	struct brcm_hcd *brcm_hcd_ptr = hcd_to_brcm(hcd);
+
+	ret = xhci_suspend(xhci, device_may_wakeup(dev));
+	clk_disable(brcm_hcd_ptr->hcd_clk);
+	return ret;
+}
+
+static int xhci_brcm_resume(struct device *dev)
+{
+	struct usb_hcd	*hcd = dev_get_drvdata(dev);
+	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+	struct brcm_hcd *brcm_hcd_ptr = hcd_to_brcm(hcd);
+	int err;
+
+	err = clk_enable(brcm_hcd_ptr->hcd_clk);
+	if (err)
+		return err;
+	return xhci_resume(xhci, 0);
+}
+
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(xhci_brcm_pm_ops, xhci_brcm_suspend,
+		xhci_brcm_resume);
+
+#ifdef CONFIG_OF
+static const struct of_device_id brcm_xhci_of_match[] = {
+	{ .compatible = "xhci-platform" },
+	{ .compatible = "brcm,xhci-brcm" },
+	{ .compatible = "brcm,xhci-brcm-v2" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, brcm_xhci_of_match);
+#endif
+
+static struct platform_driver xhci_brcm_driver = {
+	.probe	= xhci_brcm_probe,
+	.remove	= xhci_brcm_remove,
+	.driver	= {
+		.name = BRCM_DRIVER_NAME,
+		.pm = &xhci_brcm_pm_ops,
+		.of_match_table = of_match_ptr(brcm_xhci_of_match),
+	},
+};
+
+static int __init xhci_brcm_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+	pr_info("%s: " BRCM_DRIVER_DESC "\n", BRCM_DRIVER_NAME);
+	xhci_init_driver(&xhci_brcm_hc_driver, xhci_brcm_setup);
+	xhci_brcm_hc_driver.hcd_priv_size = sizeof(struct brcm_hcd);
+	return platform_driver_register(&xhci_brcm_driver);
+}
+module_init(xhci_brcm_init);
+
+static void __exit xhci_brcm_cleanup(void)
+{
+	platform_driver_unregister(&xhci_brcm_driver);
+}
+module_exit(xhci_brcm_cleanup);
+
+MODULE_DESCRIPTION(BRCM_DRIVER_DESC);
+MODULE_AUTHOR("Al Cooper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index eb009a457fb5..bb89175ca6e5 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -594,3 +594,4 @@ void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
 	trace(&vaf);
 	va_end(args);
 }
+EXPORT_SYMBOL_GPL(xhci_dbg_trace);
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 831e28989181..5abc098c6538 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1714,6 +1714,7 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
 
 	if (xhci->lpm_command)
 		xhci_free_command(xhci, xhci->lpm_command);
+	xhci->lpm_command = NULL;
 	xhci->cmd_ring_reserved_trbs = 0;
 	if (xhci->cmd_ring)
 		xhci_ring_free(xhci, xhci->cmd_ring);
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 44af2b02d701..99196018ff4b 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -40,6 +40,8 @@
 
 static const char hcd_name[] = "xhci_hcd";
 
+static struct hc_driver __read_mostly xhci_pci_hc_driver;
+
 /* called after powerup, by probe or system-pm "wakeup" */
 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
 {
@@ -173,7 +175,15 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
 
 	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
-
+#ifdef CONFIG_DREAMBOX_DM7080
+	{
+		unsigned char c;
+		printk("xhci switched power on polarity\n");
+		pci_read_config_byte(pdev, 0xE2, &c);
+		c |= 0x40;
+		pci_write_config_byte(pdev, 0xE2, c);
+	}
+#endif
 	/* Find any debug ports */
 	retval = xhci_pci_reinit(xhci, pdev);
 	if (!retval)
@@ -317,68 +327,6 @@ static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 }
 #endif /* CONFIG_PM */
 
-static const struct hc_driver xhci_pci_hc_driver = {
-	.description =		hcd_name,
-	.product_desc =		"xHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct xhci_hcd *),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			xhci_irq,
-	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,
-
-	/*
-	 * basic lifecycle operations
-	 */
-	.reset =		xhci_pci_setup,
-	.start =		xhci_run,
-#ifdef CONFIG_PM
-	.pci_suspend =          xhci_pci_suspend,
-	.pci_resume =           xhci_pci_resume,
-#endif
-	.stop =			xhci_stop,
-	.shutdown =		xhci_shutdown,
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		xhci_urb_enqueue,
-	.urb_dequeue =		xhci_urb_dequeue,
-	.alloc_dev =		xhci_alloc_dev,
-	.free_dev =		xhci_free_dev,
-	.alloc_streams =	xhci_alloc_streams,
-	.free_streams =		xhci_free_streams,
-	.add_endpoint =		xhci_add_endpoint,
-	.drop_endpoint =	xhci_drop_endpoint,
-	.endpoint_reset =	xhci_endpoint_reset,
-	.check_bandwidth =	xhci_check_bandwidth,
-	.reset_bandwidth =	xhci_reset_bandwidth,
-	.address_device =	xhci_address_device,
-	.enable_device =	xhci_enable_device,
-	.update_hub_device =	xhci_update_hub_device,
-	.reset_device =		xhci_discover_or_reset_device,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	xhci_get_frame,
-
-	/* Root hub support */
-	.hub_control =		xhci_hub_control,
-	.hub_status_data =	xhci_hub_status_data,
-	.bus_suspend =		xhci_bus_suspend,
-	.bus_resume =		xhci_bus_resume,
-	/*
-	 * call back when device connected and addressed
-	 */
-	.update_device =        xhci_update_device,
-	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
-	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
-	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
-	.find_raw_port_number =	xhci_find_raw_port_number,
-};
-
 /*-------------------------------------------------------------------------*/
 
 /* PCI driver selection metadata; PCI hotplugging uses this */
@@ -410,6 +358,11 @@ static struct pci_driver xhci_pci_driver = {
 
 int __init xhci_register_pci(void)
 {
+	xhci_init_driver(&xhci_pci_hc_driver, xhci_pci_setup);
+#ifdef CONFIG_PM
+	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
+	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
+#endif
 	return pci_register_driver(&xhci_pci_driver);
 }
 
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 1d5ba3c299cc..0422bf9fd16b 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -19,6 +19,8 @@
 
 #include "xhci.h"
 
+static struct hc_driver __read_mostly xhci_plat_hc_driver;
+
 static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
 {
 	/*
@@ -35,56 +37,6 @@ static int xhci_plat_setup(struct usb_hcd *hcd)
 	return xhci_gen_setup(hcd, xhci_plat_quirks);
 }
 
-static const struct hc_driver xhci_plat_xhci_driver = {
-	.description =		"xhci-hcd",
-	.product_desc =		"xHCI Host Controller",
-	.hcd_priv_size =	sizeof(struct xhci_hcd *),
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq =			xhci_irq,
-	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,
-
-	/*
-	 * basic lifecycle operations
-	 */
-	.reset =		xhci_plat_setup,
-	.start =		xhci_run,
-	.stop =			xhci_stop,
-	.shutdown =		xhci_shutdown,
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue =		xhci_urb_enqueue,
-	.urb_dequeue =		xhci_urb_dequeue,
-	.alloc_dev =		xhci_alloc_dev,
-	.free_dev =		xhci_free_dev,
-	.alloc_streams =	xhci_alloc_streams,
-	.free_streams =		xhci_free_streams,
-	.add_endpoint =		xhci_add_endpoint,
-	.drop_endpoint =	xhci_drop_endpoint,
-	.endpoint_reset =	xhci_endpoint_reset,
-	.check_bandwidth =	xhci_check_bandwidth,
-	.reset_bandwidth =	xhci_reset_bandwidth,
-	.address_device =	xhci_address_device,
-	.enable_device =	xhci_enable_device,
-	.update_hub_device =	xhci_update_hub_device,
-	.reset_device =		xhci_discover_or_reset_device,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number =	xhci_get_frame,
-
-	/* Root hub support */
-	.hub_control =		xhci_hub_control,
-	.hub_status_data =	xhci_hub_status_data,
-	.bus_suspend =		xhci_bus_suspend,
-	.bus_resume =		xhci_bus_resume,
-};
-
 static int xhci_plat_probe(struct platform_device *pdev)
 {
 	const struct hc_driver	*driver;
@@ -97,7 +49,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
 	if (usb_disabled())
 		return -ENODEV;
 
-	driver = &xhci_plat_xhci_driver;
+	driver = &xhci_plat_hc_driver;
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
@@ -253,6 +205,7 @@ MODULE_ALIAS("platform:xhci-hcd");
 
 int xhci_register_plat(void)
 {
+	xhci_init_driver(&xhci_plat_hc_driver, xhci_plat_setup);
 	return platform_driver_register(&usb_xhci_driver);
 }
 
diff --git a/drivers/usb/host/xhci-trace.c b/drivers/usb/host/xhci-trace.c
index 7cf30c83dcf3..367b630bdb3c 100644
--- a/drivers/usb/host/xhci-trace.c
+++ b/drivers/usb/host/xhci-trace.c
@@ -13,3 +13,5 @@
 
 #define CREATE_TRACE_POINTS
 #include "xhci-trace.h"
+
+EXPORT_TRACEPOINT_SYMBOL_GPL(xhci_dbg_quirks);
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 648f8c4761ed..f0884e7c6b89 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -648,6 +648,7 @@ int xhci_run(struct usb_hcd *hcd)
 			"Finished xhci_run for USB2 roothub");
 	return 0;
 }
+EXPORT_SYMBOL_GPL(xhci_run);
 
 static void xhci_only_stop_hcd(struct usb_hcd *hcd)
 {
@@ -904,6 +905,8 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
 	xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
 	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 	del_timer_sync(&hcd->rh_timer);
+	clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
+	del_timer_sync(&xhci->shared_hcd->rh_timer);
 
 	spin_lock_irq(&xhci->lock);
 	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
@@ -960,6 +963,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
 
 	return rc;
 }
+EXPORT_SYMBOL_GPL(xhci_suspend);
 
 /*
  * start xHC (not bus-specific)
@@ -1108,9 +1112,12 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 	xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
 	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 	usb_hcd_poll_rh_status(hcd);
+	set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
+	usb_hcd_poll_rh_status(xhci->shared_hcd);
 
 	return retval;
 }
+EXPORT_SYMBOL_GPL(xhci_resume);
 #endif	/* CONFIG_PM */
 
 /*-------------------------------------------------------------------------*/
@@ -4862,6 +4869,76 @@ error:
 	kfree(xhci);
 	return retval;
 }
+EXPORT_SYMBOL_GPL(xhci_gen_setup);
+
+static const struct hc_driver xhci_hc_driver = {
+	.description =		"xhci-hcd",
+	.product_desc =		"xHCI Host Controller",
+	.hcd_priv_size =	sizeof(struct xhci_hcd *),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq =			xhci_irq,
+	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.reset =		NULL, /* set in xhci_init_driver() */
+	.start =		xhci_run,
+	.stop =			xhci_stop,
+	.shutdown =		xhci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue =		xhci_urb_enqueue,
+	.urb_dequeue =		xhci_urb_dequeue,
+	.alloc_dev =		xhci_alloc_dev,
+	.free_dev =		xhci_free_dev,
+	.alloc_streams =	xhci_alloc_streams,
+	.free_streams =		xhci_free_streams,
+	.add_endpoint =		xhci_add_endpoint,
+	.drop_endpoint =	xhci_drop_endpoint,
+	.endpoint_reset =	xhci_endpoint_reset,
+	.check_bandwidth =	xhci_check_bandwidth,
+	.reset_bandwidth =	xhci_reset_bandwidth,
+	.address_device =	xhci_address_device,
+	.enable_device =	xhci_enable_device,
+	.update_hub_device =	xhci_update_hub_device,
+	.reset_device =		xhci_discover_or_reset_device,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number =	xhci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_control =		xhci_hub_control,
+	.hub_status_data =	xhci_hub_status_data,
+	.bus_suspend =		xhci_bus_suspend,
+	.bus_resume =		xhci_bus_resume,
+
+	/*
+	 * call back when device connected and addressed
+	 */
+	.update_device =        xhci_update_device,
+	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
+	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
+	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
+	.find_raw_port_number =	xhci_find_raw_port_number,
+};
+
+void xhci_init_driver(struct hc_driver *drv, int (*setup_fn)(struct usb_hcd *))
+{
+	BUG_ON(!setup_fn);
+	*drv = xhci_hc_driver;
+	drv->reset = setup_fn;
+}
+EXPORT_SYMBOL_GPL(xhci_init_driver);
 
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_AUTHOR(DRIVER_AUTHOR);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index c167485e0653..2bfac71b8595 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1763,6 +1763,7 @@ int xhci_run(struct usb_hcd *hcd);
 void xhci_stop(struct usb_hcd *hcd);
 void xhci_shutdown(struct usb_hcd *hcd);
 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
+void xhci_init_driver(struct hc_driver *drv, int (*setup_fn)(struct usb_hcd *));
 
 #ifdef	CONFIG_PM
 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 79d25894343a..7427366117d1 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1180,6 +1180,14 @@ config BCM_KONA_WDT_DEBUG
 
 	  If in doubt, say 'N'.
 
+config BCM7038_WDT
+	tristate "BCM7038 Watchdog"
+	select WATCHDOG_CORE
+	help
+	 Watchdog driver for the built-in hardware in Broadcom 7038 SoCs.
+
+	 Say 'Y or 'M' here to enable the driver.
+
 config LANTIQ_WDT
 	tristate "Lantiq SoC watchdog"
 	depends on LANTIQ
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 985a66cda76f..60da2ea4abcb 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
 obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
 obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
 obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
+obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/bcm7038_wdt.c b/drivers/watchdog/bcm7038_wdt.c
new file mode 100644
index 000000000000..4d5065543823
--- /dev/null
+++ b/drivers/watchdog/bcm7038_wdt.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/watchdog.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/pm.h>
+
+#define WDT_START_1		0xff00
+#define WDT_START_2		0x00ff
+#define WDT_STOP_1		0xee00
+#define WDT_STOP_2		0x00ee
+
+#define WDT_TIMEOUT_REG		0x0
+#define WDT_CMD_REG		0x4
+
+#define WDT_MIN_TIMEOUT		1 /* seconds */
+#define WDT_DEFAULT_TIMEOUT	30 /* seconds */
+#define WDT_DEFAULT_RATE	27000000
+
+struct bcm7038_watchdog {
+	void __iomem		*reg;
+	struct clk		*wdt_clk;
+	struct watchdog_device	wdd;
+	u32			hz;
+};
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+
+static unsigned long bcm7038_wdt_get_rate(struct bcm7038_watchdog *wdt)
+{
+	/* if clock is missing return hz */
+	if (!wdt->wdt_clk)
+		return wdt->hz;
+
+	return clk_get_rate(wdt->wdt_clk);
+
+}
+
+static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog)
+{
+	struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
+	u32 timeout;
+
+	timeout = bcm7038_wdt_get_rate(wdt) * wdog->timeout;
+
+	writel(timeout, wdt->reg + WDT_TIMEOUT_REG);
+}
+
+static int bcm7038_wdt_ping(struct watchdog_device *wdog)
+{
+	struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
+
+	writel(WDT_START_1, wdt->reg + WDT_CMD_REG);
+	writel(WDT_START_2, wdt->reg + WDT_CMD_REG);
+
+	return 0;
+}
+
+static int bcm7038_wdt_start(struct watchdog_device *wdog)
+{
+	bcm7038_wdt_set_timeout_reg(wdog);
+	bcm7038_wdt_ping(wdog);
+
+	return 0;
+}
+
+static int bcm7038_wdt_stop(struct watchdog_device *wdog)
+{
+	struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
+
+	writel(WDT_STOP_1, wdt->reg + WDT_CMD_REG);
+	writel(WDT_STOP_2, wdt->reg + WDT_CMD_REG);
+
+	return 0;
+}
+
+static int bcm7038_wdt_set_timeout(struct watchdog_device *wdog,
+					unsigned int t)
+{
+	if (watchdog_timeout_invalid(wdog, t))
+		return -EINVAL;
+
+	/* Can't modify timeout value if watchdog timer is running */
+	bcm7038_wdt_stop(wdog);
+	wdog->timeout = t;
+	bcm7038_wdt_start(wdog);
+
+	return 0;
+}
+
+static unsigned int bcm7038_wdt_get_timeleft(struct watchdog_device *wdog)
+{
+	struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
+	u32 time_left;
+
+	time_left = readl(wdt->reg + WDT_CMD_REG);
+
+	return time_left / bcm7038_wdt_get_rate(wdt);
+}
+
+static struct watchdog_info bcm7038_wdt_info = {
+	.identity	= "Broadcom Watchdog Timer",
+	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
+				WDIOF_MAGICCLOSE
+};
+
+static struct watchdog_ops bcm7038_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= bcm7038_wdt_start,
+	.stop		= bcm7038_wdt_stop,
+	.set_timeout	= bcm7038_wdt_set_timeout,
+	.get_timeleft	= bcm7038_wdt_get_timeleft,
+};
+
+static int bcm7038_wdt_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct bcm7038_watchdog *wdt;
+	struct resource *res;
+	unsigned long wdt_rate;
+	int err;
+
+	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
+	if (!wdt)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, wdt);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	wdt->reg = devm_ioremap_resource(dev, res);
+	if (IS_ERR(wdt->reg))
+		return PTR_ERR(wdt->reg);
+
+	wdt->wdt_clk = devm_clk_get(dev, NULL);
+	/* If unable to get clock, set clock to NULL */
+	if (IS_ERR(wdt->wdt_clk)) {
+		wdt->wdt_clk = NULL;
+		err = of_property_read_u32(np, "clock-frequency", &wdt->hz);
+		if (err) {
+			wdt->hz = WDT_DEFAULT_RATE;
+			dev_info(dev, "Using default frequency\n");
+		}
+	}
+
+	clk_prepare_enable(wdt->wdt_clk);
+
+	wdt_rate = bcm7038_wdt_get_rate(wdt);
+
+	wdt->wdd.info		= &bcm7038_wdt_info;
+	wdt->wdd.ops		= &bcm7038_wdt_ops;
+	wdt->wdd.min_timeout	= WDT_MIN_TIMEOUT;
+	wdt->wdd.timeout	= WDT_DEFAULT_TIMEOUT;
+	wdt->wdd.max_timeout	= (0xffffffff / wdt_rate);
+	wdt->wdd.parent		= dev;
+	watchdog_set_drvdata(&wdt->wdd, wdt);
+
+	err = watchdog_register_device(&wdt->wdd);
+	if (err) {
+		dev_err(dev, "Failed to register watchdog device\n");
+		return err;
+	}
+
+	dev_info(dev, "Registered Broadcom Watchdog\n");
+
+	return 0;
+}
+
+static int bcm7038_wdt_remove(struct platform_device *pdev)
+{
+	struct bcm7038_watchdog *wdt = platform_get_drvdata(pdev);
+
+	if (!nowayout)
+		bcm7038_wdt_stop(&wdt->wdd);
+
+	watchdog_unregister_device(&wdt->wdd);
+	clk_disable_unprepare(wdt->wdt_clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int bcm7038_wdt_suspend(struct device *dev)
+{
+	struct bcm7038_watchdog *wdt = dev_get_drvdata(dev);
+	if (watchdog_active(&wdt->wdd))
+		return bcm7038_wdt_stop(&wdt->wdd);
+
+	return 0;
+}
+
+static int bcm7038_wdt_resume(struct device *dev)
+{
+	struct bcm7038_watchdog *wdt = dev_get_drvdata(dev);
+	if (watchdog_active(&wdt->wdd))
+		return bcm7038_wdt_start(&wdt->wdd);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_ops, bcm7038_wdt_suspend,
+				bcm7038_wdt_resume);
+
+static void bcm7038_wdt_shutdown(struct platform_device *pdev)
+{
+	struct bcm7038_watchdog *wdt = platform_get_drvdata(pdev);
+	if (watchdog_active(&wdt->wdd))
+		bcm7038_wdt_stop(&wdt->wdd);
+}
+
+static const struct of_device_id bcm7038_wdt_match[] = {
+	{ .compatible = "brcm,bcm7038-wdt" },
+	{},
+};
+
+static struct platform_driver bcm7038_wdt_driver = {
+	.probe		= bcm7038_wdt_probe,
+	.remove		= bcm7038_wdt_remove,
+	.shutdown	= bcm7038_wdt_shutdown,
+	.driver		= {
+		.name		= "bcm7038-wdt",
+		.of_match_table	= bcm7038_wdt_match,
+		.pm		= &bcm7038_wdt_pm_ops,
+	}
+};
+module_platform_driver(bcm7038_wdt_driver);
+
+module_param(nowayout, bool, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
+	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Driver for Broadcom 7038 SoCs Watchdog");
+MODULE_AUTHOR("Justin Chen");
diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
index 6aaefbad303e..52b1f0b2444c 100644
--- a/drivers/watchdog/watchdog_dev.c
+++ b/drivers/watchdog/watchdog_dev.c
@@ -41,6 +41,7 @@
 #include <linux/miscdevice.h>	/* For handling misc devices */
 #include <linux/init.h>		/* For __init/__exit/... */
 #include <linux/uaccess.h>	/* For copy_to_user/put_user/... */
+#include <linux/of.h>
 
 #include "watchdog_core.h"
 
@@ -522,7 +523,13 @@ static struct miscdevice watchdog_miscdev = {
 
 int watchdog_dev_register(struct watchdog_device *watchdog)
 {
-	int err, devno;
+	int err, devno, ret;
+
+	if (watchdog->parent) {
+		ret = of_alias_get_id(watchdog->parent->of_node, "watchdog");
+		if (ret >= 0)
+			watchdog->id = ret;
+	}
 
 	if (watchdog->id == 0) {
 		old_wdd = watchdog;
diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c
index 3f2dd87b899a..4cd1c21acd2f 100644
--- a/fs/cifs/dir.c
+++ b/fs/cifs/dir.c
@@ -515,6 +515,14 @@ cifs_atomic_open(struct inode *inode, struct dentry *direntry,
 		goto out;
 	}
 
+	if (file->f_flags & O_DIRECT &&
+	    CIFS_SB(inode->i_sb)->mnt_cifs_flags & CIFS_MOUNT_STRICT_IO) {
+		if (CIFS_SB(inode->i_sb)->mnt_cifs_flags & CIFS_MOUNT_NO_BRL)
+			file->f_op = &cifs_file_direct_nobrl_ops;
+		else
+			file->f_op = &cifs_file_direct_ops;
+		}
+
 	file_info = cifs_new_fileinfo(&fid, file, tlink, oplock);
 	if (file_info == NULL) {
 		if (server->ops->close)
diff --git a/fs/cifs/file.c b/fs/cifs/file.c
index 40ddb6e93912..f6ba04efcd3e 100644
--- a/fs/cifs/file.c
+++ b/fs/cifs/file.c
@@ -471,6 +471,14 @@ int cifs_open(struct inode *inode, struct file *file)
 	cifs_dbg(FYI, "inode = 0x%p file flags are 0x%x for %s\n",
 		 inode, file->f_flags, full_path);
 
+	if (file->f_flags & O_DIRECT &&
+	    cifs_sb->mnt_cifs_flags & CIFS_MOUNT_STRICT_IO) {
+		if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_BRL)
+			file->f_op = &cifs_file_direct_nobrl_ops;
+		else
+			file->f_op = &cifs_file_direct_ops;
+	}
+
 	if (server->oplocks)
 		oplock = REQ_OPLOCK;
 	else
diff --git a/fs/ioctl.c b/fs/ioctl.c
index 8ac3fad36192..cadc7ee29898 100644
--- a/fs/ioctl.c
+++ b/fs/ioctl.c
@@ -589,7 +589,9 @@ int do_vfs_ioctl(struct file *filp, unsigned int fd, unsigned int cmd,
 		return ioctl_fiemap(filp, arg);
 
 	case FIGETBSZ:
-		return put_user(inode->i_sb->s_blocksize, argp);
+		if (!S_ISCHR(inode->i_mode))
+			return put_user(inode->i_sb->s_blocksize, argp);
+		/* fall through to allow the usage of ioctl's with cmd 0x02 */
 
 	default:
 		if (S_ISREG(inode->i_mode))
diff --git a/fs/proc/meminfo.c b/fs/proc/meminfo.c
index 136e548d9567..181c388ea265 100644
--- a/fs/proc/meminfo.c
+++ b/fs/proc/meminfo.c
@@ -12,6 +12,9 @@
 #include <linux/vmstat.h>
 #include <linux/atomic.h>
 #include <linux/vmalloc.h>
+#ifdef CONFIG_CMA
+#include <linux/cma.h>
+#endif
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include "internal.h"
@@ -138,6 +141,10 @@ static int meminfo_proc_show(struct seq_file *m, void *v)
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 		"AnonHugePages:  %8lu kB\n"
 #endif
+#ifdef CONFIG_CMA
+		"CmaTotal:       %8lu kB\n"
+		"CmaFree:        %8lu kB\n"
+#endif
 		,
 		K(i.totalram),
 		K(i.freeram),
@@ -187,12 +194,16 @@ static int meminfo_proc_show(struct seq_file *m, void *v)
 		vmi.used >> 10,
 		vmi.largest_chunk >> 10
 #ifdef CONFIG_MEMORY_FAILURE
-		,atomic_long_read(&num_poisoned_pages) << (PAGE_SHIFT - 10)
+		, atomic_long_read(&num_poisoned_pages) << (PAGE_SHIFT - 10)
 #endif
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-		,K(global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
+		, K(global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
 		   HPAGE_PMD_NR)
 #endif
+#ifdef CONFIG_CMA
+		, K(totalcma_pages)
+		, K(global_page_state(NR_FREE_CMA_PAGES))
+#endif
 		);
 
 	hugetlb_report_meminfo(m);
diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c
index fe68d8ac4d3d..740a6064755f 100644
--- a/fs/pstore/ram.c
+++ b/fs/pstore/ram.c
@@ -141,25 +141,27 @@ ramoops_get_next_prz(struct persistent_ram_zone *przs[], uint *c, uint max,
 	return prz;
 }
 
-static void ramoops_read_kmsg_hdr(char *buffer, struct timespec *time,
+static int ramoops_read_kmsg_hdr(char *buffer, struct timespec *time,
 				  bool *compressed)
 {
 	char data_type;
+	int header_length = 0;
 
-	if (sscanf(buffer, RAMOOPS_KERNMSG_HDR "%lu.%lu-%c\n",
-			&time->tv_sec, &time->tv_nsec, &data_type) == 3) {
+	if (sscanf(buffer, RAMOOPS_KERNMSG_HDR "%lu.%lu-%c\n%n", &time->tv_sec,
+			&time->tv_nsec, &data_type, &header_length) == 3) {
 		if (data_type == 'C')
 			*compressed = true;
 		else
 			*compressed = false;
-	} else if (sscanf(buffer, RAMOOPS_KERNMSG_HDR "%lu.%lu\n",
-			&time->tv_sec, &time->tv_nsec) == 2) {
+	} else if (sscanf(buffer, RAMOOPS_KERNMSG_HDR "%lu.%lu\n%n",
+			&time->tv_sec, &time->tv_nsec, &header_length) == 2) {
 			*compressed = false;
 	} else {
 		time->tv_sec = 0;
 		time->tv_nsec = 0;
 		*compressed = false;
 	}
+	return header_length;
 }
 
 static ssize_t ramoops_pstore_read(u64 *id, enum pstore_type_id *type,
@@ -171,6 +173,7 @@ static ssize_t ramoops_pstore_read(u64 *id, enum pstore_type_id *type,
 	ssize_t ecc_notice_size;
 	struct ramoops_context *cxt = psi->data;
 	struct persistent_ram_zone *prz;
+	int header_length;
 
 	prz = ramoops_get_next_prz(cxt->przs, &cxt->dump_read_cnt,
 				   cxt->max_dump_cnt, id, type,
@@ -184,7 +187,13 @@ static ssize_t ramoops_pstore_read(u64 *id, enum pstore_type_id *type,
 	if (!prz)
 		return 0;
 
+	if (!persistent_ram_old(prz))
+		return 0;
+
 	size = persistent_ram_old_size(prz);
+	header_length = ramoops_read_kmsg_hdr(persistent_ram_old(prz), time,
+			compressed);
+	size -= header_length;
 
 	/* ECC correction notice */
 	ecc_notice_size = persistent_ram_ecc_string(prz, NULL, 0);
@@ -193,8 +202,7 @@ static ssize_t ramoops_pstore_read(u64 *id, enum pstore_type_id *type,
 	if (*buf == NULL)
 		return -ENOMEM;
 
-	memcpy(*buf, persistent_ram_old(prz), size);
-	ramoops_read_kmsg_hdr(*buf, time, compressed);
+	memcpy(*buf, (char *)persistent_ram_old(prz) + header_length, size);
 	persistent_ram_ecc_string(prz, *buf + size, ecc_notice_size + 1);
 
 	return size + ecc_notice_size;
diff --git a/fs/xfs/xfs_attr.c b/fs/xfs/xfs_attr.c
index 01b6a0102fbd..abda1124a70f 100644
--- a/fs/xfs/xfs_attr.c
+++ b/fs/xfs/xfs_attr.c
@@ -213,7 +213,7 @@ xfs_attr_calc_size(
 		 * Out of line attribute, cannot double split, but
 		 * make room for the attribute value itself.
 		 */
-		uint	dblocks = XFS_B_TO_FSB(mp, valuelen);
+		uint	dblocks = xfs_attr3_rmt_blocks(mp, valuelen);
 		nblks += dblocks;
 		nblks += XFS_NEXTENTADD_SPACE_RES(mp, dblocks, XFS_ATTR_FORK);
 	}
@@ -698,11 +698,22 @@ xfs_attr_leaf_addname(xfs_da_args_t *args)
 
 		trace_xfs_attr_leaf_replace(args);
 
+		/* save the attribute state for later removal*/
 		args->op_flags |= XFS_DA_OP_RENAME;	/* an atomic rename */
 		args->blkno2 = args->blkno;		/* set 2nd entry info*/
 		args->index2 = args->index;
 		args->rmtblkno2 = args->rmtblkno;
 		args->rmtblkcnt2 = args->rmtblkcnt;
+		args->rmtvaluelen2 = args->rmtvaluelen;
+
+		/*
+		 * clear the remote attr state now that it is saved so that the
+		 * values reflect the state of the attribute we are about to
+		 * add, not the attribute we just found and will remove later.
+		 */
+		args->rmtblkno = 0;
+		args->rmtblkcnt = 0;
+		args->rmtvaluelen = 0;
 	}
 
 	/*
@@ -794,6 +805,7 @@ xfs_attr_leaf_addname(xfs_da_args_t *args)
 		args->blkno = args->blkno2;
 		args->rmtblkno = args->rmtblkno2;
 		args->rmtblkcnt = args->rmtblkcnt2;
+		args->rmtvaluelen = args->rmtvaluelen2;
 		if (args->rmtblkno) {
 			error = xfs_attr_rmtval_remove(args);
 			if (error)
@@ -999,13 +1011,22 @@ restart:
 
 		trace_xfs_attr_node_replace(args);
 
+		/* save the attribute state for later removal*/
 		args->op_flags |= XFS_DA_OP_RENAME;	/* atomic rename op */
 		args->blkno2 = args->blkno;		/* set 2nd entry info*/
 		args->index2 = args->index;
 		args->rmtblkno2 = args->rmtblkno;
 		args->rmtblkcnt2 = args->rmtblkcnt;
+		args->rmtvaluelen2 = args->rmtvaluelen;
+
+		/*
+		 * clear the remote attr state now that it is saved so that the
+		 * values reflect the state of the attribute we are about to
+		 * add, not the attribute we just found and will remove later.
+		 */
 		args->rmtblkno = 0;
 		args->rmtblkcnt = 0;
+		args->rmtvaluelen = 0;
 	}
 
 	retval = xfs_attr3_leaf_add(blk->bp, state->args);
@@ -1133,6 +1154,7 @@ restart:
 		args->blkno = args->blkno2;
 		args->rmtblkno = args->rmtblkno2;
 		args->rmtblkcnt = args->rmtblkcnt2;
+		args->rmtvaluelen = args->rmtvaluelen2;
 		if (args->rmtblkno) {
 			error = xfs_attr_rmtval_remove(args);
 			if (error)
diff --git a/fs/xfs/xfs_attr_leaf.c b/fs/xfs/xfs_attr_leaf.c
index 7b126f46a2f9..6bad3ef656aa 100644
--- a/fs/xfs/xfs_attr_leaf.c
+++ b/fs/xfs/xfs_attr_leaf.c
@@ -1228,6 +1228,7 @@ xfs_attr3_leaf_add_work(
 		name_rmt->valueblk = 0;
 		args->rmtblkno = 1;
 		args->rmtblkcnt = xfs_attr3_rmt_blocks(mp, args->valuelen);
+		args->rmtvaluelen = args->valuelen;
 	}
 	xfs_trans_log_buf(args->trans, bp,
 	     XFS_DA_LOGRANGE(leaf, xfs_attr3_leaf_name(leaf, args->index),
@@ -2166,11 +2167,11 @@ xfs_attr3_leaf_lookup_int(
 			if (!xfs_attr_namesp_match(args->flags, entry->flags))
 				continue;
 			args->index = probe;
-			args->valuelen = be32_to_cpu(name_rmt->valuelen);
+			args->rmtvaluelen = be32_to_cpu(name_rmt->valuelen);
 			args->rmtblkno = be32_to_cpu(name_rmt->valueblk);
 			args->rmtblkcnt = xfs_attr3_rmt_blocks(
 							args->dp->i_mount,
-							args->valuelen);
+							args->rmtvaluelen);
 			return XFS_ERROR(EEXIST);
 		}
 	}
@@ -2219,19 +2220,19 @@ xfs_attr3_leaf_getvalue(
 		name_rmt = xfs_attr3_leaf_name_remote(leaf, args->index);
 		ASSERT(name_rmt->namelen == args->namelen);
 		ASSERT(memcmp(args->name, name_rmt->name, args->namelen) == 0);
-		valuelen = be32_to_cpu(name_rmt->valuelen);
+		args->rmtvaluelen = be32_to_cpu(name_rmt->valuelen);
 		args->rmtblkno = be32_to_cpu(name_rmt->valueblk);
 		args->rmtblkcnt = xfs_attr3_rmt_blocks(args->dp->i_mount,
-						       valuelen);
+						       args->rmtvaluelen);
 		if (args->flags & ATTR_KERNOVAL) {
-			args->valuelen = valuelen;
+			args->valuelen = args->rmtvaluelen;
 			return 0;
 		}
-		if (args->valuelen < valuelen) {
-			args->valuelen = valuelen;
+		if (args->valuelen < args->rmtvaluelen) {
+			args->valuelen = args->rmtvaluelen;
 			return XFS_ERROR(ERANGE);
 		}
-		args->valuelen = valuelen;
+		args->valuelen = args->rmtvaluelen;
 	}
 	return 0;
 }
@@ -2518,7 +2519,7 @@ xfs_attr3_leaf_clearflag(
 		ASSERT((entry->flags & XFS_ATTR_LOCAL) == 0);
 		name_rmt = xfs_attr3_leaf_name_remote(leaf, args->index);
 		name_rmt->valueblk = cpu_to_be32(args->rmtblkno);
-		name_rmt->valuelen = cpu_to_be32(args->valuelen);
+		name_rmt->valuelen = cpu_to_be32(args->rmtvaluelen);
 		xfs_trans_log_buf(args->trans, bp,
 			 XFS_DA_LOGRANGE(leaf, name_rmt, sizeof(*name_rmt)));
 	}
@@ -2676,7 +2677,7 @@ xfs_attr3_leaf_flipflags(
 		ASSERT((entry1->flags & XFS_ATTR_LOCAL) == 0);
 		name_rmt = xfs_attr3_leaf_name_remote(leaf1, args->index);
 		name_rmt->valueblk = cpu_to_be32(args->rmtblkno);
-		name_rmt->valuelen = cpu_to_be32(args->valuelen);
+		name_rmt->valuelen = cpu_to_be32(args->rmtvaluelen);
 		xfs_trans_log_buf(args->trans, bp1,
 			 XFS_DA_LOGRANGE(leaf1, name_rmt, sizeof(*name_rmt)));
 	}
diff --git a/fs/xfs/xfs_attr_list.c b/fs/xfs/xfs_attr_list.c
index 70433d8e11b8..b9e7872764eb 100644
--- a/fs/xfs/xfs_attr_list.c
+++ b/fs/xfs/xfs_attr_list.c
@@ -449,6 +449,7 @@ xfs_attr3_leaf_list_int(
 				args.dp = context->dp;
 				args.whichfork = XFS_ATTR_FORK;
 				args.valuelen = valuelen;
+				args.rmtvaluelen = valuelen;
 				args.value = kmem_alloc(valuelen, KM_SLEEP | KM_NOFS);
 				args.rmtblkno = be32_to_cpu(name_rmt->valueblk);
 				args.rmtblkcnt = xfs_attr3_rmt_blocks(
diff --git a/fs/xfs/xfs_attr_remote.c b/fs/xfs/xfs_attr_remote.c
index 5549d69ddb45..1b38936acd3e 100644
--- a/fs/xfs/xfs_attr_remote.c
+++ b/fs/xfs/xfs_attr_remote.c
@@ -340,7 +340,7 @@ xfs_attr_rmtval_get(
 	struct xfs_buf		*bp;
 	xfs_dablk_t		lblkno = args->rmtblkno;
 	__uint8_t		*dst = args->value;
-	int			valuelen = args->valuelen;
+	int			valuelen;
 	int			nmap;
 	int			error;
 	int			blkcnt = args->rmtblkcnt;
@@ -350,7 +350,9 @@ xfs_attr_rmtval_get(
 	trace_xfs_attr_rmtval_get(args);
 
 	ASSERT(!(args->flags & ATTR_KERNOVAL));
+	ASSERT(args->rmtvaluelen == args->valuelen);
 
+	valuelen = args->rmtvaluelen;
 	while (valuelen > 0) {
 		nmap = ATTR_RMTVALUE_MAPSIZE;
 		error = xfs_bmapi_read(args->dp, (xfs_fileoff_t)lblkno,
@@ -418,7 +420,7 @@ xfs_attr_rmtval_set(
 	 * attributes have headers, we can't just do a straight byte to FSB
 	 * conversion and have to take the header space into account.
 	 */
-	blkcnt = xfs_attr3_rmt_blocks(mp, args->valuelen);
+	blkcnt = xfs_attr3_rmt_blocks(mp, args->rmtvaluelen);
 	error = xfs_bmap_first_unused(args->trans, args->dp, blkcnt, &lfileoff,
 						   XFS_ATTR_FORK);
 	if (error)
@@ -483,7 +485,7 @@ xfs_attr_rmtval_set(
 	 */
 	lblkno = args->rmtblkno;
 	blkcnt = args->rmtblkcnt;
-	valuelen = args->valuelen;
+	valuelen = args->rmtvaluelen;
 	while (valuelen > 0) {
 		struct xfs_buf	*bp;
 		xfs_daddr_t	dblkno;
diff --git a/fs/xfs/xfs_da_btree.h b/fs/xfs/xfs_da_btree.h
index 6e95ea79f5d7..201c6091d26a 100644
--- a/fs/xfs/xfs_da_btree.h
+++ b/fs/xfs/xfs_da_btree.h
@@ -60,10 +60,12 @@ typedef struct xfs_da_args {
 	int		index;		/* index of attr of interest in blk */
 	xfs_dablk_t	rmtblkno;	/* remote attr value starting blkno */
 	int		rmtblkcnt;	/* remote attr value block count */
+	int		rmtvaluelen;	/* remote attr value length in bytes */
 	xfs_dablk_t	blkno2;		/* blkno of 2nd attr leaf of interest */
 	int		index2;		/* index of 2nd attr in blk */
 	xfs_dablk_t	rmtblkno2;	/* remote attr value starting blkno */
 	int		rmtblkcnt2;	/* remote attr value block count */
+	int		rmtvaluelen2;	/* remote attr value length in bytes */
 	int		op_flags;	/* operation flags */
 	enum xfs_dacmp	cmpresult;	/* name compare result for lookups */
 } xfs_da_args_t;
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f962aa13..bbd28727fb65 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -112,12 +112,13 @@ extern void warn_slowpath_null(const char *file, const int line);
 #endif
 
 #ifndef HAVE_ARCH_BUG_ON
-#define BUG_ON(condition) do { if (condition) ; } while(0)
+#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while(0)
 #endif
 
 #ifndef HAVE_ARCH_WARN_ON
 #define WARN_ON(condition) ({						\
 	int __ret_warn_on = !!(condition);				\
+	(void)__ret_warn_on;						\
 	unlikely(__ret_warn_on);					\
 })
 #endif
@@ -125,6 +126,8 @@ extern void warn_slowpath_null(const char *file, const int line);
 #ifndef WARN
 #define WARN(condition, format...) ({					\
 	int __ret_warn_on = !!(condition);				\
+	if (0 && (__ret_warn_on))					\
+		printk(format);						\
 	unlikely(__ret_warn_on);					\
 })
 #endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index a5f56a0213a7..23e364538ab5 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -69,7 +69,7 @@ static inline int gpio_direction_input(unsigned gpio)
 }
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
-	return gpiod_direction_output(gpio_to_desc(gpio), value);
+	return gpiod_direction_output_raw(gpio_to_desc(gpio), value);
 }
 
 static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index bc2121fa9132..146e4fffd710 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -167,6 +167,25 @@
 #define CLK_OF_TABLES()
 #endif
 
+#ifdef CONFIG_OF_RESERVED_MEM
+#define RESERVEDMEM_OF_TABLES()				\
+	. = ALIGN(8);					\
+	VMLINUX_SYMBOL(__reservedmem_of_table) = .;	\
+	*(__reservedmem_of_table)			\
+	*(__reservedmem_of_table_end)
+#else
+#define RESERVEDMEM_OF_TABLES()
+#endif
+
+#ifdef CONFIG_SMP
+#define CPU_METHOD_OF_TABLES() . = ALIGN(8);				    \
+			   VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
+			   *(__cpu_method_of_table)			    \
+			   VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
+#else
+#define CPU_METHOD_OF_TABLES()
+#endif
+
 #define KERNEL_DTB()							\
 	STRUCT_ALIGN();							\
 	VMLINUX_SYMBOL(__dtb_start) = .;				\
@@ -490,7 +509,9 @@
 	TRACE_SYSCALLS()						\
 	MEM_DISCARD(init.rodata)					\
 	CLK_OF_TABLES()							\
+	RESERVEDMEM_OF_TABLES()						\
 	CLKSRC_OF_TABLES()						\
+	CPU_METHOD_OF_TABLES()						\
 	KERNEL_DTB()							\
 	IRQCHIP_OF_MATCH_TABLE()
 
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
index 59822a995858..b5e6b0069ac7 100644
--- a/include/dt-bindings/thermal/thermal.h
+++ b/include/dt-bindings/thermal/thermal.h
@@ -11,7 +11,7 @@
 #define _DT_BINDINGS_THERMAL_THERMAL_H
 
 /* On cooling devices upper and lower limits */
-#define THERMAL_NO_LIMIT		(-1UL)
+#define THERMAL_NO_LIMIT		(~0)
 
 #endif
 
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 7ad634501e48..84b1f7346599 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -45,6 +45,7 @@
  * bitmap_set(dst, pos, nbits)			Set specified bit area
  * bitmap_clear(dst, pos, nbits)		Clear specified bit area
  * bitmap_find_next_zero_area(buf, len, pos, n, mask)	Find bit free area
+ * bitmap_find_next_zero_area_off(buf, len, pos, n, mask)	as above
  * bitmap_shift_right(dst, src, n, nbits)	*dst = *src >> n
  * bitmap_shift_left(dst, src, n, nbits)	*dst = *src << n
  * bitmap_remap(dst, src, old, new, nbits)	*dst = map(old, new)(src)
@@ -114,11 +115,36 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
 
 extern void bitmap_set(unsigned long *map, int i, int len);
 extern void bitmap_clear(unsigned long *map, int start, int nr);
-extern unsigned long bitmap_find_next_zero_area(unsigned long *map,
-					 unsigned long size,
-					 unsigned long start,
-					 unsigned int nr,
-					 unsigned long align_mask);
+
+extern unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
+						    unsigned long size,
+						    unsigned long start,
+						    unsigned int nr,
+						    unsigned long align_mask,
+						    unsigned long align_offset);
+
+/**
+ * bitmap_find_next_zero_area - find a contiguous aligned zero area
+ * @map: The address to base the search on
+ * @size: The bitmap size in bits
+ * @start: The bitnumber to start searching at
+ * @nr: The number of zeroed bits we're looking for
+ * @align_mask: Alignment mask for zero area
+ *
+ * The @align_mask should be one less than a power of 2; the effect is that
+ * the bit offset of all zero areas this function finds is multiples of that
+ * power of 2. A @align_mask of 0 means no alignment is required.
+ */
+static inline unsigned long
+bitmap_find_next_zero_area(unsigned long *map,
+			   unsigned long size,
+			   unsigned long start,
+			   unsigned int nr,
+			   unsigned long align_mask)
+{
+	return bitmap_find_next_zero_area_off(map, size, start, nr,
+					      align_mask, 0);
+}
 
 extern int bitmap_scnprintf(char *buf, unsigned int len,
 			const unsigned long *src, int nbits);
diff --git a/include/linux/bmoca.h b/include/linux/bmoca.h
new file mode 100644
index 000000000000..f8439c696152
--- /dev/null
+++ b/include/linux/bmoca.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BMOCA_H_
+#define _BMOCA_H_
+
+#include <linux/if.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+/* NOTE: These need to match what is defined in the API template */
+#define MOCA_IE_DRV_PRINTF	0xff00
+#define MOCA_IE_WDT		0xff01
+
+#define MOCA_BAND_HIGHRF	0
+#define MOCA_BAND_MIDRF		1
+#define MOCA_BAND_WANRF		2
+#define MOCA_BAND_EXT_D		3
+#define MOCA_BAND_D_LOW		4
+#define MOCA_BAND_D_HIGH	5
+#define MOCA_BAND_E		6
+#define MOCA_BAND_F		7
+#define MOCA_BAND_G		8
+#define MOCA_BAND_H		9
+#define MOCA_BAND_MAX		10
+
+#define MOCA_BAND_NAMES { \
+	"highrf", "midrf", "wanrf", \
+	"ext_d", "d_low", "d_high", \
+	"e", "f", "g", "h"\
+}
+
+#define MOCA_BOOT_FLAGS_BONDED	(1 << 0)
+
+#define MOCA_IOC_MAGIC		'M'
+
+#define MOCA_IOCTL_GET_DRV_INFO_V2	_IOR(MOCA_IOC_MAGIC, 0, \
+	struct moca_kdrv_info_v2)
+
+#define MOCA_IOCTL_START	_IOW(MOCA_IOC_MAGIC, 1, struct moca_start)
+#define MOCA_IOCTL_STOP		_IO(MOCA_IOC_MAGIC, 2)
+#define MOCA_IOCTL_READMEM	_IOR(MOCA_IOC_MAGIC, 3, struct moca_xfer)
+#define MOCA_IOCTL_WRITEMEM	_IOR(MOCA_IOC_MAGIC, 4, struct moca_xfer)
+
+#define MOCA_IOCTL_CHECK_FOR_DATA	_IOR(MOCA_IOC_MAGIC, 5, int)
+#define MOCA_IOCTL_WOL		_IOW(MOCA_IOC_MAGIC, 6, int)
+#define MOCA_IOCTL_GET_DRV_INFO	_IOR(MOCA_IOC_MAGIC, 0, struct moca_kdrv_info)
+#define MOCA_IOCTL_SET_CPU_RATE	_IOR(MOCA_IOC_MAGIC, 7, unsigned int)
+#define MOCA_IOCTL_SET_PHY_RATE	_IOR(MOCA_IOC_MAGIC, 8, unsigned int)
+#define MOCA_IOCTL_GET_3450_REG	_IOR(MOCA_IOC_MAGIC, 9, unsigned int)
+#define MOCA_IOCTL_SET_3450_REG	_IOR(MOCA_IOC_MAGIC, 10, unsigned int)
+#define MOCA_IOCTL_PM_SUSPEND   _IO(MOCA_IOC_MAGIC, 11)
+#define MOCA_IOCTL_PM_WOL	_IO(MOCA_IOC_MAGIC, 12)
+
+#define MOCA_DEVICE_ID_UNREGISTERED  (-1)
+
+/* this must match MoCAOS_IFNAMSIZE */
+#define MOCA_IFNAMSIZ		16
+
+/* ID value hinting ioctl caller to use returned IFNAME as is */
+#define MOCA_IFNAME_USE_ID    0xffffffff
+
+/* Legacy version of moca_kdrv_info */
+struct moca_kdrv_info_v2 {
+	__u32			version;
+	__u32			build_number;
+	__u32			builtin_fw;
+
+	__u32			hw_rev;
+	__u32			rf_band;
+
+	__u32			uptime;
+	__s32			refcount;
+	__u32			gp1;
+
+	__s8			enet_name[MOCA_IFNAMSIZ];
+	__u32			enet_id;
+
+	__u32			macaddr_hi;
+	__u32			macaddr_lo;
+
+	__u32			phy_freq;
+	__u32			device_id;
+};
+
+/* this must match MoCAOS_DrvInfo */
+struct moca_kdrv_info {
+	__u32			version;
+	__u32			build_number;
+	__u32			builtin_fw;
+
+	__u32			hw_rev;
+	__u32			rf_band;
+
+	__u32			uptime;
+	__s32			refcount;
+	__u32			gp1;
+
+	__s8			enet_name[MOCA_IFNAMSIZ];
+	__u32			enet_id;
+
+	__u32			macaddr_hi;
+	__u32			macaddr_lo;
+
+	__u32			phy_freq;
+	__u32			device_id;
+
+	__u32			chip_id;
+};
+
+struct moca_xfer {
+	__u64			buf;
+	__u32			len;
+	__u32			moca_addr;
+};
+
+struct moca_start {
+	struct moca_xfer	x;
+	__u32			boot_flags;
+};
+
+/* MoCA PM states */
+enum moca_pm_states {
+	MOCA_ACTIVE,
+	MOCA_SUSPENDING,
+	MOCA_SUSPENDING_WAITING_ACK,
+	MOCA_SUSPENDING_GOT_ACK,
+	MOCA_SUSPENDED,
+	MOCA_RESUMING,
+	MOCA_RESUMING_ASSERT,
+	MOCA_RESUMING_WDOG,
+	MOCA_NONE
+};
+
+#ifdef __KERNEL__
+
+static inline void mac_to_u32(uint32_t *hi, uint32_t *lo, const uint8_t *mac)
+{
+	*hi = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | (mac[3] << 0);
+	*lo = (mac[4] << 24) | (mac[5] << 16);
+}
+
+static inline void u32_to_mac(uint8_t *mac, uint32_t hi, uint32_t lo)
+{
+	mac[0] = (hi >> 24) & 0xff;
+	mac[1] = (hi >> 16) & 0xff;
+	mac[2] = (hi >>  8) & 0xff;
+	mac[3] = (hi >>  0) & 0xff;
+	mac[4] = (lo >> 24) & 0xff;
+	mac[5] = (lo >> 16) & 0xff;
+}
+
+struct moca_platform_data {
+	char			enet_name[IFNAMSIZ];
+	unsigned int		enet_id;
+
+	u32			macaddr_hi;
+	u32			macaddr_lo;
+
+	phys_addr_t		bcm3450_i2c_base;
+	int			bcm3450_i2c_addr;
+
+	u32			hw_rev;  /* this is the chip_id */
+	u32			rf_band;
+
+	int			use_dma;
+	int			use_spi;
+
+	u32			chip_id;
+};
+
+enum {
+	HWREV_MOCA_11		= 0x1100,
+	HWREV_MOCA_11_LITE	= 0x1101,
+	HWREV_MOCA_11_PLUS	= 0x1102,
+	HWREV_MOCA_20_ALT	= 0x2000, /* for backward compatibility */
+	HWREV_MOCA_20_GEN21	= 0x2001,
+	HWREV_MOCA_20_GEN22	= 0x2002,
+	HWREV_MOCA_20_GEN23	= 0x2003,
+	HWREV_MOCA_20_GEN24	= 0x2004,
+};
+
+
+#define MOCA_PROTVER_11		0x1100
+#define MOCA_PROTVER_20		0x2000
+#define MOCA_PROTVER_MASK	0xff00
+
+#endif /* __KERNEL__ */
+
+#endif /* ! _BMOCA_H_ */
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 677b4f01b2d0..85017d11b3f2 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -1,6 +1,11 @@
 #ifndef _LINUX_BRCMPHY_H
 #define _LINUX_BRCMPHY_H
 
+/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
+ * to configure the switch internal registers via MDIO accesses.
+ */
+#define BRCM_PSEUDO_PHY_ADDR		30
+
 #define PHY_ID_BCM50610			0x0143bd60
 #define PHY_ID_BCM50610M		0x0143bd70
 #define PHY_ID_BCM5241			0x0143bc30
@@ -13,10 +18,22 @@
 #define PHY_ID_BCM5461			0x002060c0
 #define PHY_ID_BCM57780			0x03625d90
 
+#define PHY_ID_BCM7250			0xae025280
+#define PHY_ID_BCM7364			0xae025260
+#define PHY_ID_BCM7366			0x600d8490
+#define PHY_ID_BCM74371			0xae0252e0
+#define PHY_ID_BCM7439			0x600d8480
+#define PHY_ID_BCM7439_2		0xae025080
+#define PHY_ID_BCM7445			0x600d8510
+#define PHY_ID_BCM7455			0xae025300
+
 #define PHY_BCM_OUI_MASK		0xfffffc00
 #define PHY_BCM_OUI_1			0x00206000
 #define PHY_BCM_OUI_2			0x0143bc00
 #define PHY_BCM_OUI_3			0x03625c00
+#define PHY_BCM_OUI_4			0x600d8400
+#define PHY_BCM_OUI_5			0x03625e00
+#define PHY_BCM_OUI_6			0xae025000
 
 
 #define PHY_BCM_FLAGS_MODE_COPPER	0x00000001
@@ -31,6 +48,188 @@
 #define PHY_BRCM_EXT_IBND_TX_ENABLE	0x00002000
 #define PHY_BRCM_CLEAR_RGMII_MODE	0x00004000
 #define PHY_BRCM_DIS_TXCRXC_NOENRGY	0x00008000
+/* Broadcom BCM7xxx specific workarounds */
+#define PHY_BRCM_7XXX_REV(x)		(((x) >> 8) & 0xff)
+#define PHY_BRCM_7XXX_PATCH(x)		((x) & 0xff)
 #define PHY_BCM_FLAGS_VALID		0x80000000
 
+/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
+#define MII_BCM54XX_ECR		0x10	/* BCM54xx extended control register */
+#define MII_BCM54XX_ECR_IM	0x1000	/* Interrupt mask */
+#define MII_BCM54XX_ECR_IF	0x0800	/* Interrupt force */
+
+#define MII_BCM54XX_ESR		0x11	/* BCM54xx extended status register */
+#define MII_BCM54XX_ESR_IS	0x1000	/* Interrupt status */
+
+#define MII_BCM54XX_EXP_DATA	0x15	/* Expansion register data */
+#define MII_BCM54XX_EXP_SEL	0x17	/* Expansion register select */
+#define MII_BCM54XX_EXP_SEL_SSD	0x0e00	/* Secondary SerDes select */
+#define MII_BCM54XX_EXP_SEL_ER	0x0f00	/* Expansion register select */
+
+#define MII_BCM54XX_AUX_CTL	0x18	/* Auxiliary control register */
+#define MII_BCM54XX_ISR		0x1a	/* BCM54xx interrupt status register */
+#define MII_BCM54XX_IMR		0x1b	/* BCM54xx interrupt mask register */
+#define MII_BCM54XX_INT_CRCERR	0x0001	/* CRC error */
+#define MII_BCM54XX_INT_LINK	0x0002	/* Link status changed */
+#define MII_BCM54XX_INT_SPEED	0x0004	/* Link speed change */
+#define MII_BCM54XX_INT_DUPLEX	0x0008	/* Duplex mode changed */
+#define MII_BCM54XX_INT_LRS	0x0010	/* Local receiver status changed */
+#define MII_BCM54XX_INT_RRS	0x0020	/* Remote receiver status changed */
+#define MII_BCM54XX_INT_SSERR	0x0040	/* Scrambler synchronization error */
+#define MII_BCM54XX_INT_UHCD	0x0080	/* Unsupported HCD negotiated */
+#define MII_BCM54XX_INT_NHCD	0x0100	/* No HCD */
+#define MII_BCM54XX_INT_NHCDL	0x0200	/* No HCD link */
+#define MII_BCM54XX_INT_ANPR	0x0400	/* Auto-negotiation page received */
+#define MII_BCM54XX_INT_LC	0x0800	/* All counters below 128 */
+#define MII_BCM54XX_INT_HC	0x1000	/* Counter above 32768 */
+#define MII_BCM54XX_INT_MDIX	0x2000	/* MDIX status change */
+#define MII_BCM54XX_INT_PSERR	0x4000	/* Pair swap error */
+
+#define MII_BCM54XX_SHD		0x1c	/* 0x1c shadow registers */
+#define MII_BCM54XX_SHD_WRITE	0x8000
+#define MII_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
+#define MII_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)
+
+/*
+ * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
+ */
+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000
+#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB		0x0400
+#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800
+
+#define MII_BCM54XX_AUXCTL_MISC_WREN	0x8000
+#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX	0x0200
+#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC	0x7000
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC	0x0007
+
+#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x0000
+
+
+/*
+ * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
+ * BCM5482, and possibly some others.
+ */
+#define BCM_LED_SRC_LINKSPD1	0x0
+#define BCM_LED_SRC_LINKSPD2	0x1
+#define BCM_LED_SRC_XMITLED	0x2
+#define BCM_LED_SRC_ACTIVITYLED	0x3
+#define BCM_LED_SRC_FDXLED	0x4
+#define BCM_LED_SRC_SLAVE	0x5
+#define BCM_LED_SRC_INTR	0x6
+#define BCM_LED_SRC_QUALITY	0x7
+#define BCM_LED_SRC_RCVLED	0x8
+#define BCM_LED_SRC_MULTICOLOR1	0xa
+#define BCM_LED_SRC_OPENSHORT	0xb
+#define BCM_LED_SRC_OFF		0xe	/* Tied high */
+#define BCM_LED_SRC_ON		0xf	/* Tied low */
+
+
+/*
+ * BCM5482: Shadow registers
+ * Shadow values go into bits [14:10] of register 0x1c to select a shadow
+ * register to access.
+ */
+/* 00101: Spare Control Register 3 */
+#define BCM54XX_SHD_SCR3		0x05
+#define  BCM54XX_SHD_SCR3_DEF_CLK125	0x0001
+#define  BCM54XX_SHD_SCR3_DLLAPD_DIS	0x0002
+#define  BCM54XX_SHD_SCR3_TRDDAPD	0x0004
+
+/* 01010: Auto Power-Down */
+#define BCM54XX_SHD_APD			0x0a
+#define  BCM54XX_SHD_APD_EN		0x0020
+
+#define BCM5482_SHD_LEDS1	0x0d	/* 01101: LED Selector 1 */
+					/* LED3 / ~LINKSPD[2] selector */
+#define BCM5482_SHD_LEDS1_LED3(src)	((src & 0xf) << 4)
+					/* LED1 / ~LINKSPD[1] selector */
+#define BCM5482_SHD_LEDS1_LED1(src)	((src & 0xf) << 0)
+#define BCM54XX_SHD_RGMII_MODE	0x0b	/* 01011: RGMII Mode Selector */
+#define BCM5482_SHD_SSD		0x14	/* 10100: Secondary SerDes control */
+#define BCM5482_SHD_SSD_LEDM	0x0008	/* SSD LED Mode enable */
+#define BCM5482_SHD_SSD_EN	0x0001	/* SSD enable */
+#define BCM5482_SHD_MODE	0x1f	/* 11111: Mode Control Register */
+#define BCM5482_SHD_MODE_1000BX	0x0001	/* Enable 1000BASE-X registers */
+
+
+/*
+ * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
+ */
+#define MII_BCM54XX_EXP_AADJ1CH0		0x001f
+#define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN	0x0200
+#define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF	0x0100
+#define MII_BCM54XX_EXP_AADJ1CH3		0x601f
+#define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ	0x0002
+#define MII_BCM54XX_EXP_EXP08			0x0F08
+#define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ	0x0001
+#define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE	0x0200
+#define MII_BCM54XX_EXP_EXP75			0x0f75
+#define  MII_BCM54XX_EXP_EXP75_VDACCTRL		0x003c
+#define  MII_BCM54XX_EXP_EXP75_CM_OSC		0x0001
+#define MII_BCM54XX_EXP_EXP96			0x0f96
+#define  MII_BCM54XX_EXP_EXP96_MYST		0x0010
+#define MII_BCM54XX_EXP_EXP97			0x0f97
+#define  MII_BCM54XX_EXP_EXP97_MYST		0x0c0c
+
+/*
+ * BCM5482: Secondary SerDes registers
+ */
+#define BCM5482_SSD_1000BX_CTL		0x00	/* 1000BASE-X Control */
+#define BCM5482_SSD_1000BX_CTL_PWRDOWN	0x0800	/* Power-down SSD */
+#define BCM5482_SSD_SGMII_SLAVE		0x15	/* SGMII Slave Register */
+#define BCM5482_SSD_SGMII_SLAVE_EN	0x0002	/* Slave mode enable */
+#define BCM5482_SSD_SGMII_SLAVE_AD	0x0001	/* Slave auto-detection */
+
+
+/*****************************************************************************/
+/* Fast Ethernet Transceiver definitions. */
+/*****************************************************************************/
+
+#define MII_BRCM_FET_INTREG		0x1a	/* Interrupt register */
+#define MII_BRCM_FET_IR_MASK		0x0100	/* Mask all interrupts */
+#define MII_BRCM_FET_IR_LINK_EN		0x0200	/* Link status change enable */
+#define MII_BRCM_FET_IR_SPEED_EN	0x0400	/* Link speed change enable */
+#define MII_BRCM_FET_IR_DUPLEX_EN	0x0800	/* Duplex mode change enable */
+#define MII_BRCM_FET_IR_ENABLE		0x4000	/* Interrupt enable */
+
+#define MII_BRCM_FET_BRCMTEST		0x1f	/* Brcm test register */
+#define MII_BRCM_FET_BT_SRE		0x0080	/* Shadow register enable */
+
+
+/*** Shadow register definitions ***/
+
+#define MII_BRCM_FET_SHDW_MISCCTRL	0x10	/* Shadow misc ctrl */
+#define MII_BRCM_FET_SHDW_MC_FAME	0x4000	/* Force Auto MDIX enable */
+
+#define MII_BRCM_FET_SHDW_AUXMODE4	0x1a	/* Auxiliary mode 4 */
+#define MII_BRCM_FET_SHDW_AM4_LED_MASK	0x0003
+#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
+
+#define MII_BRCM_FET_SHDW_AUXSTAT2	0x1b	/* Auxiliary status 2 */
+#define MII_BRCM_FET_SHDW_AS2_APDE	0x0020	/* Auto power down enable */
+
+/*
+ * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
+ * 0x1c shadow registers.
+ */
+static inline int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
+{
+	phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
+	return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
+}
+
+static inline int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow,
+				       u16 val)
+{
+	return phy_write(phydev, MII_BCM54XX_SHD,
+			 MII_BCM54XX_SHD_WRITE |
+			 MII_BCM54XX_SHD_VAL(shadow) |
+			 MII_BCM54XX_SHD_DATA(val));
+}
+
+/* Clause 45 vendor specific registers */
+#define CL45VEN_EEE_CONTROL		0x803d
+#define LPI_FEATURE_EN			0x8000
+#define LPI_FEATURE_EN_DIG1000X		0x4000
+
 #endif /* _LINUX_BRCMPHY_H */
diff --git a/include/linux/brcmstb/3390a0/bchp_bspi.h b/include/linux/brcmstb/3390a0/bchp_bspi.h
new file mode 100644
index 000000000000..b77396b4c274
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_bspi.h
@@ -0,0 +1,445 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:12 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x204a3200 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x204a3204 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x204a3208 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x204a320c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x204a3210 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x204a3214 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x204a3218 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x204a321c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x204a3220 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x204a3224 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x204a3228 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x204a322c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x204a3230 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x204a3234 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x204a3238 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x204a323c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x204a3240 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x204a3244 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x204a3248 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x204a324c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000002
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000e00
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000001
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_bspi_raf.h b/include/linux/brcmstb/3390a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..3b2b46a8aaef
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_bspi_raf.h
@@ -0,0 +1,162 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:28 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x204a3300 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x204a3304 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x204a3308 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x204a330c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x204a3310 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x204a3314 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x204a3318 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x204a331c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x204a3320 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_common.h b/include/linux/brcmstb/3390a0/bchp_common.h
new file mode 100644
index 000000000000..d2018d72d225
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_common.h
@@ -0,0 +1,6355 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sun Sep 14 03:14:19 2014
+ *                 Full Compile MD5 Checksum ef22086ebd4065e4fea50dbc64f17e5e
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              39fcae49037a6337517df43bfc24b21f
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM3390_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0xd0000000
+#define BCHP_REGISTER_START                                0x000000e0 /* MC_BPM_CTRL_0 is first */
+#define BCHP_REGISTER_END                                  0x21584d1c /* PHY_ECC_LANE_1 is last */
+#define BCHP_REGISTER_SIZE                                 0x0856130f /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_MC_BPM_CTRL_0_REG_START                       0x000000e0
+#define BCHP_MC_BPM_CTRL_0_REG_END                         0x000000e4
+#define BCHP_MC_BPM_CTRL_1_REG_START                       0x002000e0
+#define BCHP_MC_BPM_CTRL_1_REG_END                         0x002000e4
+#define BCHP_MBDMA_UNI3_REG_START                          0x00400000
+#define BCHP_MBDMA_UNI3_REG_END                            0x00400508
+#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_START              0x00400600
+#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_END                0x00400710
+#define BCHP_UNIMAC_CORE0_UNI3_REG_START                   0x00400800
+#define BCHP_UNIMAC_CORE0_UNI3_REG_END                     0x00400b44
+#define BCHP_MIB0_UNI3_REG_START                           0x00400c00
+#define BCHP_MIB0_UNI3_REG_END                             0x00400cf4
+#define BCHP_HFB0_UNI3_REG_START                           0x00401000
+#define BCHP_HFB0_UNI3_REG_END                             0x00401ffc
+#define BCHP_DAVICMAC_DAV_REG_START                        0x00600000
+#define BCHP_DAVICMAC_DAV_REG_END                          0x0060041c
+#define BCHP_DAVIC_DMA_CTRL_DAV_REG_START                  0x00600800
+#define BCHP_DAVIC_DMA_CTRL_DAV_REG_END                    0x00600844
+#define BCHP_DAVIC_DMA_CH1_DAV_REG_START                   0x00600900
+#define BCHP_DAVIC_DMA_CH1_DAV_REG_END                     0x0060090c
+#define BCHP_DAVIC_DMA_CH2_DAV_REG_START                   0x00600910
+#define BCHP_DAVIC_DMA_CH2_DAV_REG_END                     0x0060091c
+#define BCHP_DAVIC_DMA_CH3_DAV_REG_START                   0x00600920
+#define BCHP_DAVIC_DMA_CH3_DAV_REG_END                     0x0060092c
+#define BCHP_DAVIC_DMA_CH4_DAV_REG_START                   0x00600930
+#define BCHP_DAVIC_DMA_CH4_DAV_REG_END                     0x0060093c
+#define BCHP_DAVIC_DMA_CH5_DAV_REG_START                   0x00600940
+#define BCHP_DAVIC_DMA_CH5_DAV_REG_END                     0x0060094c
+#define BCHP_DAVIC_DMA_CH6_DAV_REG_START                   0x00600950
+#define BCHP_DAVIC_DMA_CH6_DAV_REG_END                     0x0060095c
+#define BCHP_DAVIC_DMA_CH7_DAV_REG_START                   0x00600960
+#define BCHP_DAVIC_DMA_CH7_DAV_REG_END                     0x0060096c
+#define BCHP_DAVIC_DMA_CH8_DAV_REG_START                   0x00600970
+#define BCHP_DAVIC_DMA_CH8_DAV_REG_END                     0x0060097c
+#define BCHP_DAVIC_DMA_CH9_DAV_REG_START                   0x00600980
+#define BCHP_DAVIC_DMA_CH9_DAV_REG_END                     0x0060098c
+#define BCHP_DAVIC_DMA_CH10_DAV_REG_START                  0x00600990
+#define BCHP_DAVIC_DMA_CH10_DAV_REG_END                    0x0060099c
+#define BCHP_DAVIC_DMA_CH1_STATE_DAV_REG_START             0x00600a00
+#define BCHP_DAVIC_DMA_CH1_STATE_DAV_REG_END               0x00600a0c
+#define BCHP_DAVIC_DMA_CH2_STATE_DAV_REG_START             0x00600a10
+#define BCHP_DAVIC_DMA_CH2_STATE_DAV_REG_END               0x00600a1c
+#define BCHP_DAVIC_DMA_CH3_STATE_DAV_REG_START             0x00600a20
+#define BCHP_DAVIC_DMA_CH3_STATE_DAV_REG_END               0x00600a2c
+#define BCHP_DAVIC_DMA_CH4_STATE_DAV_REG_START             0x00600a30
+#define BCHP_DAVIC_DMA_CH4_STATE_DAV_REG_END               0x00600a3c
+#define BCHP_DAVIC_DMA_CH5_STATE_DAV_REG_START             0x00600a40
+#define BCHP_DAVIC_DMA_CH5_STATE_DAV_REG_END               0x00600a4c
+#define BCHP_DAVIC_DMA_CH6_STATE_DAV_REG_START             0x00600a50
+#define BCHP_DAVIC_DMA_CH6_STATE_DAV_REG_END               0x00600a5c
+#define BCHP_DAVIC_DMA_CH7_STATE_DAV_REG_START             0x00600a60
+#define BCHP_DAVIC_DMA_CH7_STATE_DAV_REG_END               0x00600a6c
+#define BCHP_DAVIC_DMA_CH8_STATE_DAV_REG_START             0x00600a70
+#define BCHP_DAVIC_DMA_CH8_STATE_DAV_REG_END               0x00600a7c
+#define BCHP_DAVIC_DMA_CH9_STATE_DAV_REG_START             0x00600a80
+#define BCHP_DAVIC_DMA_CH9_STATE_DAV_REG_END               0x00600a8c
+#define BCHP_DAVIC_DMA_CH10_STATE_DAV_REG_START            0x00600a90
+#define BCHP_DAVIC_DMA_CH10_STATE_DAV_REG_END              0x00600a9c
+#define BCHP_BaseReserved_UTP_REG_START                    0x00a00000
+#define BCHP_BaseReserved_UTP_REG_END                      0x00a00000
+#define BCHP_Control_UTP_REG_START                         0x00a01000
+#define BCHP_Control_UTP_REG_END                           0x00a010fc
+#define BCHP_OutgoingMessageFIFO_UTP_REG_START             0x00a01100
+#define BCHP_OutgoingMessageFIFO_UTP_REG_END               0x00a0117c
+#define BCHP_IncomingMessageFIFO_UTP_REG_START             0x00a01200
+#define BCHP_IncomingMessageFIFO_UTP_REG_END               0x00a0127c
+#define BCHP_DMA0_UTP_REG_START                            0x00a01300
+#define BCHP_DMA0_UTP_REG_END                              0x00a0131c
+#define BCHP_DMA1_UTP_REG_START                            0x00a01320
+#define BCHP_DMA1_UTP_REG_END                              0x00a0133c
+#define BCHP_DMAHI0_UTP_REG_START                          0x00a01340
+#define BCHP_DMAHI0_UTP_REG_END                            0x00a0134c
+#define BCHP_DMAHI1_UTP_REG_START                          0x00a01350
+#define BCHP_DMAHI1_UTP_REG_END                            0x00a0135c
+#define BCHP_Token_UTP_REG_START                           0x00a01400
+#define BCHP_Token_UTP_REG_END                             0x00a01420
+#define BCHP_PerfPower_UTP_REG_START                       0x00a01600
+#define BCHP_PerfPower_UTP_REG_END                         0x00a01640
+#define BCHP_MessageID_UTP_REG_START                       0x00a01700
+#define BCHP_MessageID_UTP_REG_END                         0x00a0177c
+#define BCHP_HWCounters_UTP_REG_START                      0x00a01900
+#define BCHP_HWCounters_UTP_REG_END                        0x00a01944
+#define BCHP_DQM_0_31_UTP_REG_START                        0x00a01c00
+#define BCHP_DQM_0_31_UTP_REG_END                          0x00a01c48
+#define BCHP_DQM_32_63_UTP_REG_START                       0x00a01d00
+#define BCHP_DQM_32_63_UTP_REG_END                         0x00a01d48
+#define BCHP_QUEUE_TIMER_UTP_REG_START                     0x00a02000
+#define BCHP_QUEUE_TIMER_UTP_REG_END                       0x00a021fc
+#define BCHP_QUEUE_STATUS_0_31_UTP_REG_START               0x00a02800
+#define BCHP_QUEUE_STATUS_0_31_UTP_REG_END                 0x00a0287c
+#define BCHP_QUEUE_STATUS_32_63_UTP_REG_START              0x00a02900
+#define BCHP_QUEUE_STATUS_32_63_UTP_REG_END                0x00a0297c
+#define BCHP_QUEUE_MIB_0_31_UTP_REG_START                  0x00a03000
+#define BCHP_QUEUE_MIB_0_31_UTP_REG_END                    0x00a0317c
+#define BCHP_QUEUE_MIB_32_63_UTP_REG_START                 0x00a03200
+#define BCHP_QUEUE_MIB_32_63_UTP_REG_END                   0x00a0337c
+#define BCHP_QUEUE_0_CNTRL_UTP_REG_START                   0x00a04000
+#define BCHP_QUEUE_0_CNTRL_UTP_REG_END                     0x00a0400c
+#define BCHP_QUEUE_1_CNTRL_UTP_REG_START                   0x00a04010
+#define BCHP_QUEUE_1_CNTRL_UTP_REG_END                     0x00a0401c
+#define BCHP_QUEUE_2_CNTRL_UTP_REG_START                   0x00a04020
+#define BCHP_QUEUE_2_CNTRL_UTP_REG_END                     0x00a0402c
+#define BCHP_QUEUE_3_CNTRL_UTP_REG_START                   0x00a04030
+#define BCHP_QUEUE_3_CNTRL_UTP_REG_END                     0x00a0403c
+#define BCHP_QUEUE_4_CNTRL_UTP_REG_START                   0x00a04040
+#define BCHP_QUEUE_4_CNTRL_UTP_REG_END                     0x00a0404c
+#define BCHP_QUEUE_5_CNTRL_UTP_REG_START                   0x00a04050
+#define BCHP_QUEUE_5_CNTRL_UTP_REG_END                     0x00a0405c
+#define BCHP_QUEUE_6_CNTRL_UTP_REG_START                   0x00a04060
+#define BCHP_QUEUE_6_CNTRL_UTP_REG_END                     0x00a0406c
+#define BCHP_QUEUE_7_CNTRL_UTP_REG_START                   0x00a04070
+#define BCHP_QUEUE_7_CNTRL_UTP_REG_END                     0x00a0407c
+#define BCHP_QUEUE_8_CNTRL_UTP_REG_START                   0x00a04080
+#define BCHP_QUEUE_8_CNTRL_UTP_REG_END                     0x00a0408c
+#define BCHP_QUEUE_9_CNTRL_UTP_REG_START                   0x00a04090
+#define BCHP_QUEUE_9_CNTRL_UTP_REG_END                     0x00a0409c
+#define BCHP_QUEUE_10_CNTRL_UTP_REG_START                  0x00a040a0
+#define BCHP_QUEUE_10_CNTRL_UTP_REG_END                    0x00a040ac
+#define BCHP_QUEUE_11_CNTRL_UTP_REG_START                  0x00a040b0
+#define BCHP_QUEUE_11_CNTRL_UTP_REG_END                    0x00a040bc
+#define BCHP_QUEUE_12_CNTRL_UTP_REG_START                  0x00a040c0
+#define BCHP_QUEUE_12_CNTRL_UTP_REG_END                    0x00a040cc
+#define BCHP_QUEUE_13_CNTRL_UTP_REG_START                  0x00a040d0
+#define BCHP_QUEUE_13_CNTRL_UTP_REG_END                    0x00a040dc
+#define BCHP_QUEUE_14_CNTRL_UTP_REG_START                  0x00a040e0
+#define BCHP_QUEUE_14_CNTRL_UTP_REG_END                    0x00a040ec
+#define BCHP_QUEUE_15_CNTRL_UTP_REG_START                  0x00a040f0
+#define BCHP_QUEUE_15_CNTRL_UTP_REG_END                    0x00a040fc
+#define BCHP_QUEUE_16_CNTRL_UTP_REG_START                  0x00a04100
+#define BCHP_QUEUE_16_CNTRL_UTP_REG_END                    0x00a0410c
+#define BCHP_QUEUE_17_CNTRL_UTP_REG_START                  0x00a04110
+#define BCHP_QUEUE_17_CNTRL_UTP_REG_END                    0x00a0411c
+#define BCHP_QUEUE_18_CNTRL_UTP_REG_START                  0x00a04120
+#define BCHP_QUEUE_18_CNTRL_UTP_REG_END                    0x00a0412c
+#define BCHP_QUEUE_19_CNTRL_UTP_REG_START                  0x00a04130
+#define BCHP_QUEUE_19_CNTRL_UTP_REG_END                    0x00a0413c
+#define BCHP_QUEUE_20_CNTRL_UTP_REG_START                  0x00a04140
+#define BCHP_QUEUE_20_CNTRL_UTP_REG_END                    0x00a0414c
+#define BCHP_QUEUE_21_CNTRL_UTP_REG_START                  0x00a04150
+#define BCHP_QUEUE_21_CNTRL_UTP_REG_END                    0x00a0415c
+#define BCHP_QUEUE_22_CNTRL_UTP_REG_START                  0x00a04160
+#define BCHP_QUEUE_22_CNTRL_UTP_REG_END                    0x00a0416c
+#define BCHP_QUEUE_23_CNTRL_UTP_REG_START                  0x00a04170
+#define BCHP_QUEUE_23_CNTRL_UTP_REG_END                    0x00a0417c
+#define BCHP_QUEUE_24_CNTRL_UTP_REG_START                  0x00a04180
+#define BCHP_QUEUE_24_CNTRL_UTP_REG_END                    0x00a0418c
+#define BCHP_QUEUE_25_CNTRL_UTP_REG_START                  0x00a04190
+#define BCHP_QUEUE_25_CNTRL_UTP_REG_END                    0x00a0419c
+#define BCHP_QUEUE_26_CNTRL_UTP_REG_START                  0x00a041a0
+#define BCHP_QUEUE_26_CNTRL_UTP_REG_END                    0x00a041ac
+#define BCHP_QUEUE_27_CNTRL_UTP_REG_START                  0x00a041b0
+#define BCHP_QUEUE_27_CNTRL_UTP_REG_END                    0x00a041bc
+#define BCHP_QUEUE_28_CNTRL_UTP_REG_START                  0x00a041c0
+#define BCHP_QUEUE_28_CNTRL_UTP_REG_END                    0x00a041cc
+#define BCHP_QUEUE_29_CNTRL_UTP_REG_START                  0x00a041d0
+#define BCHP_QUEUE_29_CNTRL_UTP_REG_END                    0x00a041dc
+#define BCHP_QUEUE_30_CNTRL_UTP_REG_START                  0x00a041e0
+#define BCHP_QUEUE_30_CNTRL_UTP_REG_END                    0x00a041ec
+#define BCHP_QUEUE_31_CNTRL_UTP_REG_START                  0x00a041f0
+#define BCHP_QUEUE_31_CNTRL_UTP_REG_END                    0x00a041fc
+#define BCHP_QUEUE_32_CNTRL_UTP_REG_START                  0x00a04200
+#define BCHP_QUEUE_32_CNTRL_UTP_REG_END                    0x00a0420c
+#define BCHP_QUEUE_33_CNTRL_UTP_REG_START                  0x00a04210
+#define BCHP_QUEUE_33_CNTRL_UTP_REG_END                    0x00a0421c
+#define BCHP_QUEUE_34_CNTRL_UTP_REG_START                  0x00a04220
+#define BCHP_QUEUE_34_CNTRL_UTP_REG_END                    0x00a0422c
+#define BCHP_QUEUE_35_CNTRL_UTP_REG_START                  0x00a04230
+#define BCHP_QUEUE_35_CNTRL_UTP_REG_END                    0x00a0423c
+#define BCHP_QUEUE_36_CNTRL_UTP_REG_START                  0x00a04240
+#define BCHP_QUEUE_36_CNTRL_UTP_REG_END                    0x00a0424c
+#define BCHP_QUEUE_37_CNTRL_UTP_REG_START                  0x00a04250
+#define BCHP_QUEUE_37_CNTRL_UTP_REG_END                    0x00a0425c
+#define BCHP_QUEUE_38_CNTRL_UTP_REG_START                  0x00a04260
+#define BCHP_QUEUE_38_CNTRL_UTP_REG_END                    0x00a0426c
+#define BCHP_QUEUE_39_CNTRL_UTP_REG_START                  0x00a04270
+#define BCHP_QUEUE_39_CNTRL_UTP_REG_END                    0x00a0427c
+#define BCHP_QUEUE_40_CNTRL_UTP_REG_START                  0x00a04280
+#define BCHP_QUEUE_40_CNTRL_UTP_REG_END                    0x00a0428c
+#define BCHP_QUEUE_41_CNTRL_UTP_REG_START                  0x00a04290
+#define BCHP_QUEUE_41_CNTRL_UTP_REG_END                    0x00a0429c
+#define BCHP_QUEUE_42_CNTRL_UTP_REG_START                  0x00a042a0
+#define BCHP_QUEUE_42_CNTRL_UTP_REG_END                    0x00a042ac
+#define BCHP_QUEUE_43_CNTRL_UTP_REG_START                  0x00a042b0
+#define BCHP_QUEUE_43_CNTRL_UTP_REG_END                    0x00a042bc
+#define BCHP_QUEUE_44_CNTRL_UTP_REG_START                  0x00a042c0
+#define BCHP_QUEUE_44_CNTRL_UTP_REG_END                    0x00a042cc
+#define BCHP_QUEUE_45_CNTRL_UTP_REG_START                  0x00a042d0
+#define BCHP_QUEUE_45_CNTRL_UTP_REG_END                    0x00a042dc
+#define BCHP_QUEUE_46_CNTRL_UTP_REG_START                  0x00a042e0
+#define BCHP_QUEUE_46_CNTRL_UTP_REG_END                    0x00a042ec
+#define BCHP_QUEUE_47_CNTRL_UTP_REG_START                  0x00a042f0
+#define BCHP_QUEUE_47_CNTRL_UTP_REG_END                    0x00a042fc
+#define BCHP_QUEUE_48_CNTRL_UTP_REG_START                  0x00a04300
+#define BCHP_QUEUE_48_CNTRL_UTP_REG_END                    0x00a0430c
+#define BCHP_QUEUE_49_CNTRL_UTP_REG_START                  0x00a04310
+#define BCHP_QUEUE_49_CNTRL_UTP_REG_END                    0x00a0431c
+#define BCHP_QUEUE_50_CNTRL_UTP_REG_START                  0x00a04320
+#define BCHP_QUEUE_50_CNTRL_UTP_REG_END                    0x00a0432c
+#define BCHP_QUEUE_51_CNTRL_UTP_REG_START                  0x00a04330
+#define BCHP_QUEUE_51_CNTRL_UTP_REG_END                    0x00a0433c
+#define BCHP_QUEUE_52_CNTRL_UTP_REG_START                  0x00a04340
+#define BCHP_QUEUE_52_CNTRL_UTP_REG_END                    0x00a0434c
+#define BCHP_QUEUE_53_CNTRL_UTP_REG_START                  0x00a04350
+#define BCHP_QUEUE_53_CNTRL_UTP_REG_END                    0x00a0435c
+#define BCHP_QUEUE_54_CNTRL_UTP_REG_START                  0x00a04360
+#define BCHP_QUEUE_54_CNTRL_UTP_REG_END                    0x00a0436c
+#define BCHP_QUEUE_55_CNTRL_UTP_REG_START                  0x00a04370
+#define BCHP_QUEUE_55_CNTRL_UTP_REG_END                    0x00a0437c
+#define BCHP_QUEUE_56_CNTRL_UTP_REG_START                  0x00a04380
+#define BCHP_QUEUE_56_CNTRL_UTP_REG_END                    0x00a0438c
+#define BCHP_QUEUE_57_CNTRL_UTP_REG_START                  0x00a04390
+#define BCHP_QUEUE_57_CNTRL_UTP_REG_END                    0x00a0439c
+#define BCHP_QUEUE_58_CNTRL_UTP_REG_START                  0x00a043a0
+#define BCHP_QUEUE_58_CNTRL_UTP_REG_END                    0x00a043ac
+#define BCHP_QUEUE_59_CNTRL_UTP_REG_START                  0x00a043b0
+#define BCHP_QUEUE_59_CNTRL_UTP_REG_END                    0x00a043bc
+#define BCHP_QUEUE_60_CNTRL_UTP_REG_START                  0x00a043c0
+#define BCHP_QUEUE_60_CNTRL_UTP_REG_END                    0x00a043cc
+#define BCHP_QUEUE_61_CNTRL_UTP_REG_START                  0x00a043d0
+#define BCHP_QUEUE_61_CNTRL_UTP_REG_END                    0x00a043dc
+#define BCHP_QUEUE_62_CNTRL_UTP_REG_START                  0x00a043e0
+#define BCHP_QUEUE_62_CNTRL_UTP_REG_END                    0x00a043ec
+#define BCHP_QUEUE_63_CNTRL_UTP_REG_START                  0x00a043f0
+#define BCHP_QUEUE_63_CNTRL_UTP_REG_END                    0x00a043fc
+#define BCHP_QUEUE_0_DATA_UTP_REG_START                    0x00a05000
+#define BCHP_QUEUE_0_DATA_UTP_REG_END                      0x00a0500c
+#define BCHP_QUEUE_1_DATA_UTP_REG_START                    0x00a05010
+#define BCHP_QUEUE_1_DATA_UTP_REG_END                      0x00a0501c
+#define BCHP_QUEUE_2_DATA_UTP_REG_START                    0x00a05020
+#define BCHP_QUEUE_2_DATA_UTP_REG_END                      0x00a0502c
+#define BCHP_QUEUE_3_DATA_UTP_REG_START                    0x00a05030
+#define BCHP_QUEUE_3_DATA_UTP_REG_END                      0x00a0503c
+#define BCHP_QUEUE_4_DATA_UTP_REG_START                    0x00a05040
+#define BCHP_QUEUE_4_DATA_UTP_REG_END                      0x00a0504c
+#define BCHP_QUEUE_5_DATA_UTP_REG_START                    0x00a05050
+#define BCHP_QUEUE_5_DATA_UTP_REG_END                      0x00a0505c
+#define BCHP_QUEUE_6_DATA_UTP_REG_START                    0x00a05060
+#define BCHP_QUEUE_6_DATA_UTP_REG_END                      0x00a0506c
+#define BCHP_QUEUE_7_DATA_UTP_REG_START                    0x00a05070
+#define BCHP_QUEUE_7_DATA_UTP_REG_END                      0x00a0507c
+#define BCHP_QUEUE_8_DATA_UTP_REG_START                    0x00a05080
+#define BCHP_QUEUE_8_DATA_UTP_REG_END                      0x00a0508c
+#define BCHP_QUEUE_9_DATA_UTP_REG_START                    0x00a05090
+#define BCHP_QUEUE_9_DATA_UTP_REG_END                      0x00a0509c
+#define BCHP_QUEUE_10_DATA_UTP_REG_START                   0x00a050a0
+#define BCHP_QUEUE_10_DATA_UTP_REG_END                     0x00a050ac
+#define BCHP_QUEUE_11_DATA_UTP_REG_START                   0x00a050b0
+#define BCHP_QUEUE_11_DATA_UTP_REG_END                     0x00a050bc
+#define BCHP_QUEUE_12_DATA_UTP_REG_START                   0x00a050c0
+#define BCHP_QUEUE_12_DATA_UTP_REG_END                     0x00a050cc
+#define BCHP_QUEUE_13_DATA_UTP_REG_START                   0x00a050d0
+#define BCHP_QUEUE_13_DATA_UTP_REG_END                     0x00a050dc
+#define BCHP_QUEUE_14_DATA_UTP_REG_START                   0x00a050e0
+#define BCHP_QUEUE_14_DATA_UTP_REG_END                     0x00a050ec
+#define BCHP_QUEUE_15_DATA_UTP_REG_START                   0x00a050f0
+#define BCHP_QUEUE_15_DATA_UTP_REG_END                     0x00a050fc
+#define BCHP_QUEUE_16_DATA_UTP_REG_START                   0x00a05100
+#define BCHP_QUEUE_16_DATA_UTP_REG_END                     0x00a0510c
+#define BCHP_QUEUE_17_DATA_UTP_REG_START                   0x00a05110
+#define BCHP_QUEUE_17_DATA_UTP_REG_END                     0x00a0511c
+#define BCHP_QUEUE_18_DATA_UTP_REG_START                   0x00a05120
+#define BCHP_QUEUE_18_DATA_UTP_REG_END                     0x00a0512c
+#define BCHP_QUEUE_19_DATA_UTP_REG_START                   0x00a05130
+#define BCHP_QUEUE_19_DATA_UTP_REG_END                     0x00a0513c
+#define BCHP_QUEUE_20_DATA_UTP_REG_START                   0x00a05140
+#define BCHP_QUEUE_20_DATA_UTP_REG_END                     0x00a0514c
+#define BCHP_QUEUE_21_DATA_UTP_REG_START                   0x00a05150
+#define BCHP_QUEUE_21_DATA_UTP_REG_END                     0x00a0515c
+#define BCHP_QUEUE_22_DATA_UTP_REG_START                   0x00a05160
+#define BCHP_QUEUE_22_DATA_UTP_REG_END                     0x00a0516c
+#define BCHP_QUEUE_23_DATA_UTP_REG_START                   0x00a05170
+#define BCHP_QUEUE_23_DATA_UTP_REG_END                     0x00a0517c
+#define BCHP_QUEUE_24_DATA_UTP_REG_START                   0x00a05180
+#define BCHP_QUEUE_24_DATA_UTP_REG_END                     0x00a0518c
+#define BCHP_QUEUE_25_DATA_UTP_REG_START                   0x00a05190
+#define BCHP_QUEUE_25_DATA_UTP_REG_END                     0x00a0519c
+#define BCHP_QUEUE_26_DATA_UTP_REG_START                   0x00a051a0
+#define BCHP_QUEUE_26_DATA_UTP_REG_END                     0x00a051ac
+#define BCHP_QUEUE_27_DATA_UTP_REG_START                   0x00a051b0
+#define BCHP_QUEUE_27_DATA_UTP_REG_END                     0x00a051bc
+#define BCHP_QUEUE_28_DATA_UTP_REG_START                   0x00a051c0
+#define BCHP_QUEUE_28_DATA_UTP_REG_END                     0x00a051cc
+#define BCHP_QUEUE_29_DATA_UTP_REG_START                   0x00a051d0
+#define BCHP_QUEUE_29_DATA_UTP_REG_END                     0x00a051dc
+#define BCHP_QUEUE_30_DATA_UTP_REG_START                   0x00a051e0
+#define BCHP_QUEUE_30_DATA_UTP_REG_END                     0x00a051ec
+#define BCHP_QUEUE_31_DATA_UTP_REG_START                   0x00a051f0
+#define BCHP_QUEUE_31_DATA_UTP_REG_END                     0x00a051fc
+#define BCHP_QUEUE_32_DATA_UTP_REG_START                   0x00a05200
+#define BCHP_QUEUE_32_DATA_UTP_REG_END                     0x00a0520c
+#define BCHP_QUEUE_33_DATA_UTP_REG_START                   0x00a05210
+#define BCHP_QUEUE_33_DATA_UTP_REG_END                     0x00a0521c
+#define BCHP_QUEUE_34_DATA_UTP_REG_START                   0x00a05220
+#define BCHP_QUEUE_34_DATA_UTP_REG_END                     0x00a0522c
+#define BCHP_QUEUE_35_DATA_UTP_REG_START                   0x00a05230
+#define BCHP_QUEUE_35_DATA_UTP_REG_END                     0x00a0523c
+#define BCHP_QUEUE_36_DATA_UTP_REG_START                   0x00a05240
+#define BCHP_QUEUE_36_DATA_UTP_REG_END                     0x00a0524c
+#define BCHP_QUEUE_37_DATA_UTP_REG_START                   0x00a05250
+#define BCHP_QUEUE_37_DATA_UTP_REG_END                     0x00a0525c
+#define BCHP_QUEUE_38_DATA_UTP_REG_START                   0x00a05260
+#define BCHP_QUEUE_38_DATA_UTP_REG_END                     0x00a0526c
+#define BCHP_QUEUE_39_DATA_UTP_REG_START                   0x00a05270
+#define BCHP_QUEUE_39_DATA_UTP_REG_END                     0x00a0527c
+#define BCHP_QUEUE_40_DATA_UTP_REG_START                   0x00a05280
+#define BCHP_QUEUE_40_DATA_UTP_REG_END                     0x00a0528c
+#define BCHP_QUEUE_41_DATA_UTP_REG_START                   0x00a05290
+#define BCHP_QUEUE_41_DATA_UTP_REG_END                     0x00a0529c
+#define BCHP_QUEUE_42_DATA_UTP_REG_START                   0x00a052a0
+#define BCHP_QUEUE_42_DATA_UTP_REG_END                     0x00a052ac
+#define BCHP_QUEUE_43_DATA_UTP_REG_START                   0x00a052b0
+#define BCHP_QUEUE_43_DATA_UTP_REG_END                     0x00a052bc
+#define BCHP_QUEUE_44_DATA_UTP_REG_START                   0x00a052c0
+#define BCHP_QUEUE_44_DATA_UTP_REG_END                     0x00a052cc
+#define BCHP_QUEUE_45_DATA_UTP_REG_START                   0x00a052d0
+#define BCHP_QUEUE_45_DATA_UTP_REG_END                     0x00a052dc
+#define BCHP_QUEUE_46_DATA_UTP_REG_START                   0x00a052e0
+#define BCHP_QUEUE_46_DATA_UTP_REG_END                     0x00a052ec
+#define BCHP_QUEUE_47_DATA_UTP_REG_START                   0x00a052f0
+#define BCHP_QUEUE_47_DATA_UTP_REG_END                     0x00a052fc
+#define BCHP_QUEUE_48_DATA_UTP_REG_START                   0x00a05300
+#define BCHP_QUEUE_48_DATA_UTP_REG_END                     0x00a0530c
+#define BCHP_QUEUE_49_DATA_UTP_REG_START                   0x00a05310
+#define BCHP_QUEUE_49_DATA_UTP_REG_END                     0x00a0531c
+#define BCHP_QUEUE_50_DATA_UTP_REG_START                   0x00a05320
+#define BCHP_QUEUE_50_DATA_UTP_REG_END                     0x00a0532c
+#define BCHP_QUEUE_51_DATA_UTP_REG_START                   0x00a05330
+#define BCHP_QUEUE_51_DATA_UTP_REG_END                     0x00a0533c
+#define BCHP_QUEUE_52_DATA_UTP_REG_START                   0x00a05340
+#define BCHP_QUEUE_52_DATA_UTP_REG_END                     0x00a0534c
+#define BCHP_QUEUE_53_DATA_UTP_REG_START                   0x00a05350
+#define BCHP_QUEUE_53_DATA_UTP_REG_END                     0x00a0535c
+#define BCHP_QUEUE_54_DATA_UTP_REG_START                   0x00a05360
+#define BCHP_QUEUE_54_DATA_UTP_REG_END                     0x00a0536c
+#define BCHP_QUEUE_55_DATA_UTP_REG_START                   0x00a05370
+#define BCHP_QUEUE_55_DATA_UTP_REG_END                     0x00a0537c
+#define BCHP_QUEUE_56_DATA_UTP_REG_START                   0x00a05380
+#define BCHP_QUEUE_56_DATA_UTP_REG_END                     0x00a0538c
+#define BCHP_QUEUE_57_DATA_UTP_REG_START                   0x00a05390
+#define BCHP_QUEUE_57_DATA_UTP_REG_END                     0x00a0539c
+#define BCHP_QUEUE_58_DATA_UTP_REG_START                   0x00a053a0
+#define BCHP_QUEUE_58_DATA_UTP_REG_END                     0x00a053ac
+#define BCHP_QUEUE_59_DATA_UTP_REG_START                   0x00a053b0
+#define BCHP_QUEUE_59_DATA_UTP_REG_END                     0x00a053bc
+#define BCHP_QUEUE_60_DATA_UTP_REG_START                   0x00a053c0
+#define BCHP_QUEUE_60_DATA_UTP_REG_END                     0x00a053cc
+#define BCHP_QUEUE_61_DATA_UTP_REG_START                   0x00a053d0
+#define BCHP_QUEUE_61_DATA_UTP_REG_END                     0x00a053dc
+#define BCHP_QUEUE_62_DATA_UTP_REG_START                   0x00a053e0
+#define BCHP_QUEUE_62_DATA_UTP_REG_END                     0x00a053ec
+#define BCHP_QUEUE_63_DATA_UTP_REG_START                   0x00a053f0
+#define BCHP_QUEUE_63_DATA_UTP_REG_END                     0x00a053fc
+#define BCHP_OL_DQM_UTP_REG_START                          0x00a06c00
+#define BCHP_OL_DQM_UTP_REG_END                            0x00a06c30
+#define BCHP_OL_QUEUE_STATUS_UTP_REG_START                 0x00a07400
+#define BCHP_OL_QUEUE_STATUS_UTP_REG_END                   0x00a0747c
+#define BCHP_OL_QUEUE_0_CNTRL_UTP_REG_START                0x00a08000
+#define BCHP_OL_QUEUE_0_CNTRL_UTP_REG_END                  0x00a0801c
+#define BCHP_OL_QUEUE_1_CNTRL_UTP_REG_START                0x00a08020
+#define BCHP_OL_QUEUE_1_CNTRL_UTP_REG_END                  0x00a0803c
+#define BCHP_OL_QUEUE_2_CNTRL_UTP_REG_START                0x00a08040
+#define BCHP_OL_QUEUE_2_CNTRL_UTP_REG_END                  0x00a0805c
+#define BCHP_OL_QUEUE_3_CNTRL_UTP_REG_START                0x00a08060
+#define BCHP_OL_QUEUE_3_CNTRL_UTP_REG_END                  0x00a0807c
+#define BCHP_OL_QUEUE_4_CNTRL_UTP_REG_START                0x00a08080
+#define BCHP_OL_QUEUE_4_CNTRL_UTP_REG_END                  0x00a0809c
+#define BCHP_OL_QUEUE_5_CNTRL_UTP_REG_START                0x00a080a0
+#define BCHP_OL_QUEUE_5_CNTRL_UTP_REG_END                  0x00a080bc
+#define BCHP_OL_QUEUE_6_CNTRL_UTP_REG_START                0x00a080c0
+#define BCHP_OL_QUEUE_6_CNTRL_UTP_REG_END                  0x00a080dc
+#define BCHP_OL_QUEUE_7_CNTRL_UTP_REG_START                0x00a080e0
+#define BCHP_OL_QUEUE_7_CNTRL_UTP_REG_END                  0x00a080fc
+#define BCHP_OL_QUEUE_8_CNTRL_UTP_REG_START                0x00a08100
+#define BCHP_OL_QUEUE_8_CNTRL_UTP_REG_END                  0x00a0811c
+#define BCHP_OL_QUEUE_9_CNTRL_UTP_REG_START                0x00a08120
+#define BCHP_OL_QUEUE_9_CNTRL_UTP_REG_END                  0x00a0813c
+#define BCHP_OL_QUEUE_10_CNTRL_UTP_REG_START               0x00a08140
+#define BCHP_OL_QUEUE_10_CNTRL_UTP_REG_END                 0x00a0815c
+#define BCHP_OL_QUEUE_11_CNTRL_UTP_REG_START               0x00a08160
+#define BCHP_OL_QUEUE_11_CNTRL_UTP_REG_END                 0x00a0817c
+#define BCHP_OL_QUEUE_12_CNTRL_UTP_REG_START               0x00a08180
+#define BCHP_OL_QUEUE_12_CNTRL_UTP_REG_END                 0x00a0819c
+#define BCHP_OL_QUEUE_13_CNTRL_UTP_REG_START               0x00a081a0
+#define BCHP_OL_QUEUE_13_CNTRL_UTP_REG_END                 0x00a081bc
+#define BCHP_OL_QUEUE_14_CNTRL_UTP_REG_START               0x00a081c0
+#define BCHP_OL_QUEUE_14_CNTRL_UTP_REG_END                 0x00a081dc
+#define BCHP_OL_QUEUE_15_CNTRL_UTP_REG_START               0x00a081e0
+#define BCHP_OL_QUEUE_15_CNTRL_UTP_REG_END                 0x00a081fc
+#define BCHP_OL_QUEUE_16_CNTRL_UTP_REG_START               0x00a08200
+#define BCHP_OL_QUEUE_16_CNTRL_UTP_REG_END                 0x00a0821c
+#define BCHP_OL_QUEUE_17_CNTRL_UTP_REG_START               0x00a08220
+#define BCHP_OL_QUEUE_17_CNTRL_UTP_REG_END                 0x00a0823c
+#define BCHP_OL_QUEUE_18_CNTRL_UTP_REG_START               0x00a08240
+#define BCHP_OL_QUEUE_18_CNTRL_UTP_REG_END                 0x00a0825c
+#define BCHP_OL_QUEUE_19_CNTRL_UTP_REG_START               0x00a08260
+#define BCHP_OL_QUEUE_19_CNTRL_UTP_REG_END                 0x00a0827c
+#define BCHP_OL_QUEUE_20_CNTRL_UTP_REG_START               0x00a08280
+#define BCHP_OL_QUEUE_20_CNTRL_UTP_REG_END                 0x00a0829c
+#define BCHP_OL_QUEUE_21_CNTRL_UTP_REG_START               0x00a082a0
+#define BCHP_OL_QUEUE_21_CNTRL_UTP_REG_END                 0x00a082bc
+#define BCHP_OL_QUEUE_22_CNTRL_UTP_REG_START               0x00a082c0
+#define BCHP_OL_QUEUE_22_CNTRL_UTP_REG_END                 0x00a082dc
+#define BCHP_OL_QUEUE_23_CNTRL_UTP_REG_START               0x00a082e0
+#define BCHP_OL_QUEUE_23_CNTRL_UTP_REG_END                 0x00a082fc
+#define BCHP_OL_QUEUE_24_CNTRL_UTP_REG_START               0x00a08300
+#define BCHP_OL_QUEUE_24_CNTRL_UTP_REG_END                 0x00a0831c
+#define BCHP_OL_QUEUE_25_CNTRL_UTP_REG_START               0x00a08320
+#define BCHP_OL_QUEUE_25_CNTRL_UTP_REG_END                 0x00a0833c
+#define BCHP_OL_QUEUE_26_CNTRL_UTP_REG_START               0x00a08340
+#define BCHP_OL_QUEUE_26_CNTRL_UTP_REG_END                 0x00a0835c
+#define BCHP_OL_QUEUE_27_CNTRL_UTP_REG_START               0x00a08360
+#define BCHP_OL_QUEUE_27_CNTRL_UTP_REG_END                 0x00a0837c
+#define BCHP_OL_QUEUE_28_CNTRL_UTP_REG_START               0x00a08380
+#define BCHP_OL_QUEUE_28_CNTRL_UTP_REG_END                 0x00a0839c
+#define BCHP_OL_QUEUE_29_CNTRL_UTP_REG_START               0x00a083a0
+#define BCHP_OL_QUEUE_29_CNTRL_UTP_REG_END                 0x00a083bc
+#define BCHP_OL_QUEUE_30_CNTRL_UTP_REG_START               0x00a083c0
+#define BCHP_OL_QUEUE_30_CNTRL_UTP_REG_END                 0x00a083dc
+#define BCHP_OL_QUEUE_31_CNTRL_UTP_REG_START               0x00a083e0
+#define BCHP_OL_QUEUE_31_CNTRL_UTP_REG_END                 0x00a083fc
+#define BCHP_OL_QUEUE_0_DATA_UTP_REG_START                 0x00a09000
+#define BCHP_OL_QUEUE_0_DATA_UTP_REG_END                   0x00a0901c
+#define BCHP_OL_QUEUE_1_DATA_UTP_REG_START                 0x00a09020
+#define BCHP_OL_QUEUE_1_DATA_UTP_REG_END                   0x00a0903c
+#define BCHP_OL_QUEUE_2_DATA_UTP_REG_START                 0x00a09040
+#define BCHP_OL_QUEUE_2_DATA_UTP_REG_END                   0x00a0905c
+#define BCHP_OL_QUEUE_3_DATA_UTP_REG_START                 0x00a09060
+#define BCHP_OL_QUEUE_3_DATA_UTP_REG_END                   0x00a0907c
+#define BCHP_OL_QUEUE_4_DATA_UTP_REG_START                 0x00a09080
+#define BCHP_OL_QUEUE_4_DATA_UTP_REG_END                   0x00a0909c
+#define BCHP_OL_QUEUE_5_DATA_UTP_REG_START                 0x00a090a0
+#define BCHP_OL_QUEUE_5_DATA_UTP_REG_END                   0x00a090bc
+#define BCHP_OL_QUEUE_6_DATA_UTP_REG_START                 0x00a090c0
+#define BCHP_OL_QUEUE_6_DATA_UTP_REG_END                   0x00a090dc
+#define BCHP_OL_QUEUE_7_DATA_UTP_REG_START                 0x00a090e0
+#define BCHP_OL_QUEUE_7_DATA_UTP_REG_END                   0x00a090fc
+#define BCHP_OL_QUEUE_8_DATA_UTP_REG_START                 0x00a09100
+#define BCHP_OL_QUEUE_8_DATA_UTP_REG_END                   0x00a0911c
+#define BCHP_OL_QUEUE_9_DATA_UTP_REG_START                 0x00a09120
+#define BCHP_OL_QUEUE_9_DATA_UTP_REG_END                   0x00a0913c
+#define BCHP_OL_QUEUE_10_DATA_UTP_REG_START                0x00a09140
+#define BCHP_OL_QUEUE_10_DATA_UTP_REG_END                  0x00a0915c
+#define BCHP_OL_QUEUE_11_DATA_UTP_REG_START                0x00a09160
+#define BCHP_OL_QUEUE_11_DATA_UTP_REG_END                  0x00a0917c
+#define BCHP_OL_QUEUE_12_DATA_UTP_REG_START                0x00a09180
+#define BCHP_OL_QUEUE_12_DATA_UTP_REG_END                  0x00a0919c
+#define BCHP_OL_QUEUE_13_DATA_UTP_REG_START                0x00a091a0
+#define BCHP_OL_QUEUE_13_DATA_UTP_REG_END                  0x00a091bc
+#define BCHP_OL_QUEUE_14_DATA_UTP_REG_START                0x00a091c0
+#define BCHP_OL_QUEUE_14_DATA_UTP_REG_END                  0x00a091dc
+#define BCHP_OL_QUEUE_15_DATA_UTP_REG_START                0x00a091e0
+#define BCHP_OL_QUEUE_15_DATA_UTP_REG_END                  0x00a091fc
+#define BCHP_OL_QUEUE_16_DATA_UTP_REG_START                0x00a09200
+#define BCHP_OL_QUEUE_16_DATA_UTP_REG_END                  0x00a0921c
+#define BCHP_OL_QUEUE_17_DATA_UTP_REG_START                0x00a09220
+#define BCHP_OL_QUEUE_17_DATA_UTP_REG_END                  0x00a0923c
+#define BCHP_OL_QUEUE_18_DATA_UTP_REG_START                0x00a09240
+#define BCHP_OL_QUEUE_18_DATA_UTP_REG_END                  0x00a0925c
+#define BCHP_OL_QUEUE_19_DATA_UTP_REG_START                0x00a09260
+#define BCHP_OL_QUEUE_19_DATA_UTP_REG_END                  0x00a0927c
+#define BCHP_OL_QUEUE_20_DATA_UTP_REG_START                0x00a09280
+#define BCHP_OL_QUEUE_20_DATA_UTP_REG_END                  0x00a0929c
+#define BCHP_OL_QUEUE_21_DATA_UTP_REG_START                0x00a092a0
+#define BCHP_OL_QUEUE_21_DATA_UTP_REG_END                  0x00a092bc
+#define BCHP_OL_QUEUE_22_DATA_UTP_REG_START                0x00a092c0
+#define BCHP_OL_QUEUE_22_DATA_UTP_REG_END                  0x00a092dc
+#define BCHP_OL_QUEUE_23_DATA_UTP_REG_START                0x00a092e0
+#define BCHP_OL_QUEUE_23_DATA_UTP_REG_END                  0x00a092fc
+#define BCHP_OL_QUEUE_24_DATA_UTP_REG_START                0x00a09300
+#define BCHP_OL_QUEUE_24_DATA_UTP_REG_END                  0x00a0931c
+#define BCHP_OL_QUEUE_25_DATA_UTP_REG_START                0x00a09320
+#define BCHP_OL_QUEUE_25_DATA_UTP_REG_END                  0x00a0933c
+#define BCHP_OL_QUEUE_26_DATA_UTP_REG_START                0x00a09340
+#define BCHP_OL_QUEUE_26_DATA_UTP_REG_END                  0x00a0935c
+#define BCHP_OL_QUEUE_27_DATA_UTP_REG_START                0x00a09360
+#define BCHP_OL_QUEUE_27_DATA_UTP_REG_END                  0x00a0937c
+#define BCHP_OL_QUEUE_28_DATA_UTP_REG_START                0x00a09380
+#define BCHP_OL_QUEUE_28_DATA_UTP_REG_END                  0x00a0939c
+#define BCHP_OL_QUEUE_29_DATA_UTP_REG_START                0x00a093a0
+#define BCHP_OL_QUEUE_29_DATA_UTP_REG_END                  0x00a093bc
+#define BCHP_OL_QUEUE_30_DATA_UTP_REG_START                0x00a093c0
+#define BCHP_OL_QUEUE_30_DATA_UTP_REG_END                  0x00a093dc
+#define BCHP_OL_QUEUE_31_DATA_UTP_REG_START                0x00a093e0
+#define BCHP_OL_QUEUE_31_DATA_UTP_REG_END                  0x00a093fc
+#define BCHP_OL_QUEUE_MIB_UTP_REG_START                    0x00a0a000
+#define BCHP_OL_QUEUE_MIB_UTP_REG_END                      0x00a0a17c
+#define BCHP_SEGDMA_CONFIG_UTP_REG_START                   0x00a20000
+#define BCHP_SEGDMA_CONFIG_UTP_REG_END                     0x00a2003c
+#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_START                 0x00a20100
+#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_END                   0x00a2013c
+#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_START                  0x00a20200
+#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_END                    0x00a2023c
+#define BCHP_SEGDMA_STAT_UTP_REG_START                     0x00a20300
+#define BCHP_SEGDMA_STAT_UTP_REG_END                       0x00a203a4
+#define BCHP_SEGDMA_TEST_UTP_REG_START                     0x00a20400
+#define BCHP_SEGDMA_TEST_UTP_REG_END                       0x00a2045c
+#define BCHP_SEGDMA_CHAN0_UTP_REG_START                    0x00a21000
+#define BCHP_SEGDMA_CHAN0_UTP_REG_END                      0x00a2103c
+#define BCHP_SEGDMA_CHAN1_UTP_REG_START                    0x00a21100
+#define BCHP_SEGDMA_CHAN1_UTP_REG_END                      0x00a2113c
+#define BCHP_SEGDMA_CHAN2_UTP_REG_START                    0x00a21200
+#define BCHP_SEGDMA_CHAN2_UTP_REG_END                      0x00a2123c
+#define BCHP_SEGDMA_CHAN3_UTP_REG_START                    0x00a21300
+#define BCHP_SEGDMA_CHAN3_UTP_REG_END                      0x00a2133c
+#define BCHP_SEGDMA_CHAN4_UTP_REG_START                    0x00a21400
+#define BCHP_SEGDMA_CHAN4_UTP_REG_END                      0x00a2143c
+#define BCHP_SEGDMA_CHAN5_UTP_REG_START                    0x00a21500
+#define BCHP_SEGDMA_CHAN5_UTP_REG_END                      0x00a2153c
+#define BCHP_SEGDMA_CHAN6_UTP_REG_START                    0x00a21600
+#define BCHP_SEGDMA_CHAN6_UTP_REG_END                      0x00a2163c
+#define BCHP_SEGDMA_CHAN7_UTP_REG_START                    0x00a21700
+#define BCHP_SEGDMA_CHAN7_UTP_REG_END                      0x00a2173c
+#define BCHP_SEGDMA_CHAN8_UTP_REG_START                    0x00a21800
+#define BCHP_SEGDMA_CHAN8_UTP_REG_END                      0x00a2183c
+#define BCHP_SEGDMA_CHAN9_UTP_REG_START                    0x00a21900
+#define BCHP_SEGDMA_CHAN9_UTP_REG_END                      0x00a2193c
+#define BCHP_SEGDMA_FLOW0_UTP_REG_START                    0x00a22000
+#define BCHP_SEGDMA_FLOW0_UTP_REG_END                      0x00a2207c
+#define BCHP_SEGDMA_FLOW1_UTP_REG_START                    0x00a22100
+#define BCHP_SEGDMA_FLOW1_UTP_REG_END                      0x00a2217c
+#define BCHP_SEGDMA_FLOW2_UTP_REG_START                    0x00a22200
+#define BCHP_SEGDMA_FLOW2_UTP_REG_END                      0x00a2227c
+#define BCHP_SEGDMA_FLOW3_UTP_REG_START                    0x00a22300
+#define BCHP_SEGDMA_FLOW3_UTP_REG_END                      0x00a2237c
+#define BCHP_SEGDMA_FLOW4_UTP_REG_START                    0x00a22400
+#define BCHP_SEGDMA_FLOW4_UTP_REG_END                      0x00a2247c
+#define BCHP_SEGDMA_FLOW5_UTP_REG_START                    0x00a22500
+#define BCHP_SEGDMA_FLOW5_UTP_REG_END                      0x00a2257c
+#define BCHP_SEGDMA_FLOW6_UTP_REG_START                    0x00a22600
+#define BCHP_SEGDMA_FLOW6_UTP_REG_END                      0x00a2267c
+#define BCHP_SEGDMA_FLOW7_UTP_REG_START                    0x00a22700
+#define BCHP_SEGDMA_FLOW7_UTP_REG_END                      0x00a2277c
+#define BCHP_SEGDMA_FLOW8_UTP_REG_START                    0x00a22800
+#define BCHP_SEGDMA_FLOW8_UTP_REG_END                      0x00a2287c
+#define BCHP_SEGDMA_FLOW9_UTP_REG_START                    0x00a22900
+#define BCHP_SEGDMA_FLOW9_UTP_REG_END                      0x00a2297c
+#define BCHP_SEGDMA_FLOW10_UTP_REG_START                   0x00a22a00
+#define BCHP_SEGDMA_FLOW10_UTP_REG_END                     0x00a22a7c
+#define BCHP_SEGDMA_FLOW11_UTP_REG_START                   0x00a22b00
+#define BCHP_SEGDMA_FLOW11_UTP_REG_END                     0x00a22b7c
+#define BCHP_SEGDMA_FLOW12_UTP_REG_START                   0x00a22c00
+#define BCHP_SEGDMA_FLOW12_UTP_REG_END                     0x00a22c7c
+#define BCHP_SEGDMA_FLOW13_UTP_REG_START                   0x00a22d00
+#define BCHP_SEGDMA_FLOW13_UTP_REG_END                     0x00a22d7c
+#define BCHP_SEGDMA_FLOW14_UTP_REG_START                   0x00a22e00
+#define BCHP_SEGDMA_FLOW14_UTP_REG_END                     0x00a22e7c
+#define BCHP_SEGDMA_FLOW15_UTP_REG_START                   0x00a22f00
+#define BCHP_SEGDMA_FLOW15_UTP_REG_END                     0x00a22f7c
+#define BCHP_SEGDMA_FLOW16_UTP_REG_START                   0x00a23000
+#define BCHP_SEGDMA_FLOW16_UTP_REG_END                     0x00a2307c
+#define BCHP_SEGDMA_FLOW17_UTP_REG_START                   0x00a23100
+#define BCHP_SEGDMA_FLOW17_UTP_REG_END                     0x00a2317c
+#define BCHP_SEGDMA_FLOW18_UTP_REG_START                   0x00a23200
+#define BCHP_SEGDMA_FLOW18_UTP_REG_END                     0x00a2327c
+#define BCHP_SEGDMA_FLOW19_UTP_REG_START                   0x00a23300
+#define BCHP_SEGDMA_FLOW19_UTP_REG_END                     0x00a2337c
+#define BCHP_SEGDMA_FLOW20_UTP_REG_START                   0x00a23400
+#define BCHP_SEGDMA_FLOW20_UTP_REG_END                     0x00a2347c
+#define BCHP_SEGDMA_FLOW21_UTP_REG_START                   0x00a23500
+#define BCHP_SEGDMA_FLOW21_UTP_REG_END                     0x00a2357c
+#define BCHP_SEGDMA_FLOW22_UTP_REG_START                   0x00a23600
+#define BCHP_SEGDMA_FLOW22_UTP_REG_END                     0x00a2367c
+#define BCHP_SEGDMA_FLOW23_UTP_REG_START                   0x00a23700
+#define BCHP_SEGDMA_FLOW23_UTP_REG_END                     0x00a2377c
+#define BCHP_SEGDMA_FLOW24_UTP_REG_START                   0x00a23800
+#define BCHP_SEGDMA_FLOW24_UTP_REG_END                     0x00a2387c
+#define BCHP_SEGDMA_FLOW25_UTP_REG_START                   0x00a23900
+#define BCHP_SEGDMA_FLOW25_UTP_REG_END                     0x00a2397c
+#define BCHP_SEGDMA_FLOW26_UTP_REG_START                   0x00a23a00
+#define BCHP_SEGDMA_FLOW26_UTP_REG_END                     0x00a23a7c
+#define BCHP_SEGDMA_FLOW27_UTP_REG_START                   0x00a23b00
+#define BCHP_SEGDMA_FLOW27_UTP_REG_END                     0x00a23b7c
+#define BCHP_SEGDMA_FLOW28_UTP_REG_START                   0x00a23c00
+#define BCHP_SEGDMA_FLOW28_UTP_REG_END                     0x00a23c7c
+#define BCHP_SEGDMA_FLOW29_UTP_REG_START                   0x00a23d00
+#define BCHP_SEGDMA_FLOW29_UTP_REG_END                     0x00a23d7c
+#define BCHP_SEGDMA_FLOW30_UTP_REG_START                   0x00a23e00
+#define BCHP_SEGDMA_FLOW30_UTP_REG_END                     0x00a23e7c
+#define BCHP_SEGDMA_FLOW31_UTP_REG_START                   0x00a23f00
+#define BCHP_SEGDMA_FLOW31_UTP_REG_END                     0x00a23f7c
+#define BCHP_SEGDMA_TEST_FLOW_UTP_REG_START                0x00a24000
+#define BCHP_SEGDMA_TEST_FLOW_UTP_REG_END                  0x00a2407c
+#define BCHP_SEGDMA_TEST_FIFO_UTP_REG_START                0x00a24100
+#define BCHP_SEGDMA_TEST_FIFO_UTP_REG_END                  0x00a24108
+#define BCHP_CRYPTO_UTP_REG_START                          0x00a30000
+#define BCHP_CRYPTO_UTP_REG_END                            0x00a3d000
+#define BCHP_QueueSharedMem_UTP_REG_START                  0x00a40000
+#define BCHP_QueueSharedMem_UTP_REG_END                    0x00a4bffc
+#define BCHP_PacketSharedMemory_UTP_REG_START              0x00a80000
+#define BCHP_PacketSharedMemory_UTP_REG_END                0x00a80ffc
+#define BCHP_QListMem_UTP_REG_START                        0x00b00000
+#define BCHP_QListMem_UTP_REG_END                          0x00b03ffc
+#define BCHP_QueueListConfig_UTP_REG_START                 0x00b05000
+#define BCHP_QueueListConfig_UTP_REG_END                   0x00b0521c
+#define BCHP_QiThreshold_UTP_REG_START                     0x00b05400
+#define BCHP_QiThreshold_UTP_REG_END                       0x00b0547c
+#define BCHP_AckCelMaxCnt_UTP_REG_START                    0x00b05500
+#define BCHP_AckCelMaxCnt_UTP_REG_END                      0x00b0553c
+#define BCHP_MIBs_UTP_REG_START                            0x00b05600
+#define BCHP_MIBs_UTP_REG_END                              0x00b05634
+#define BCHP_UTPIncomingMessageFIFO_UTP_REG_START          0x00b05700
+#define BCHP_UTPIncomingMessageFIFO_UTP_REG_END            0x00b05740
+#define BCHP_QueueListHeadTail_UTP_REG_START               0x00b05800
+#define BCHP_QueueListHeadTail_UTP_REG_END                 0x00b058fc
+#define BCHP_TokenInsertion_UTP_REG_START                  0x00b05a00
+#define BCHP_TokenInsertion_UTP_REG_END                    0x00b05a1c
+#define BCHP_TokenDeletion_UTP_REG_START                   0x00b05a20
+#define BCHP_TokenDeletion_UTP_REG_END                     0x00b05a30
+#define BCHP_TamMisc_UTP_REG_START                         0x00b05a40
+#define BCHP_TamMisc_UTP_REG_END                           0x00b05aa0
+#define BCHP_QueueAvailSize_UTP_REG_START                  0x00b05b00
+#define BCHP_QueueAvailSize_UTP_REG_END                    0x00b05bfc
+#define BCHP_UTPMaxRate_FLOW0_UTP_REG_START                0x00b05c00
+#define BCHP_UTPMaxRate_FLOW0_UTP_REG_END                  0x00b05c0c
+#define BCHP_UTPMaxRate_FLOW1_UTP_REG_START                0x00b05c10
+#define BCHP_UTPMaxRate_FLOW1_UTP_REG_END                  0x00b05c1c
+#define BCHP_UTPMaxRate_FLOW2_UTP_REG_START                0x00b05c20
+#define BCHP_UTPMaxRate_FLOW2_UTP_REG_END                  0x00b05c2c
+#define BCHP_UTPMaxRate_FLOW3_UTP_REG_START                0x00b05c30
+#define BCHP_UTPMaxRate_FLOW3_UTP_REG_END                  0x00b05c3c
+#define BCHP_UTPMaxRate_FLOW4_UTP_REG_START                0x00b05c40
+#define BCHP_UTPMaxRate_FLOW4_UTP_REG_END                  0x00b05c4c
+#define BCHP_UTPMaxRate_FLOW5_UTP_REG_START                0x00b05c50
+#define BCHP_UTPMaxRate_FLOW5_UTP_REG_END                  0x00b05c5c
+#define BCHP_UTPMaxRate_FLOW6_UTP_REG_START                0x00b05c60
+#define BCHP_UTPMaxRate_FLOW6_UTP_REG_END                  0x00b05c6c
+#define BCHP_UTPMaxRate_FLOW7_UTP_REG_START                0x00b05c70
+#define BCHP_UTPMaxRate_FLOW7_UTP_REG_END                  0x00b05c7c
+#define BCHP_UTPMaxRate_FLOW8_UTP_REG_START                0x00b05c80
+#define BCHP_UTPMaxRate_FLOW8_UTP_REG_END                  0x00b05c8c
+#define BCHP_UTPMaxRate_FLOW9_UTP_REG_START                0x00b05c90
+#define BCHP_UTPMaxRate_FLOW9_UTP_REG_END                  0x00b05c9c
+#define BCHP_UTPMaxRate_FLOW10_UTP_REG_START               0x00b05ca0
+#define BCHP_UTPMaxRate_FLOW10_UTP_REG_END                 0x00b05cac
+#define BCHP_UTPMaxRate_FLOW11_UTP_REG_START               0x00b05cb0
+#define BCHP_UTPMaxRate_FLOW11_UTP_REG_END                 0x00b05cbc
+#define BCHP_UTPMaxRate_FLOW12_UTP_REG_START               0x00b05cc0
+#define BCHP_UTPMaxRate_FLOW12_UTP_REG_END                 0x00b05ccc
+#define BCHP_UTPMaxRate_FLOW13_UTP_REG_START               0x00b05cd0
+#define BCHP_UTPMaxRate_FLOW13_UTP_REG_END                 0x00b05cdc
+#define BCHP_UTPMaxRate_FLOW14_UTP_REG_START               0x00b05ce0
+#define BCHP_UTPMaxRate_FLOW14_UTP_REG_END                 0x00b05cec
+#define BCHP_UTPMaxRate_FLOW15_UTP_REG_START               0x00b05cf0
+#define BCHP_UTPMaxRate_FLOW15_UTP_REG_END                 0x00b05cfc
+#define BCHP_UTPPeakRate_FLOW0_UTP_REG_START               0x00b05d00
+#define BCHP_UTPPeakRate_FLOW0_UTP_REG_END                 0x00b05d0c
+#define BCHP_UTPPeakRate_FLOW1_UTP_REG_START               0x00b05d10
+#define BCHP_UTPPeakRate_FLOW1_UTP_REG_END                 0x00b05d1c
+#define BCHP_UTPPeakRate_FLOW2_UTP_REG_START               0x00b05d20
+#define BCHP_UTPPeakRate_FLOW2_UTP_REG_END                 0x00b05d2c
+#define BCHP_UTPPeakRate_FLOW3_UTP_REG_START               0x00b05d30
+#define BCHP_UTPPeakRate_FLOW3_UTP_REG_END                 0x00b05d3c
+#define BCHP_UTPPeakRate_FLOW4_UTP_REG_START               0x00b05d40
+#define BCHP_UTPPeakRate_FLOW4_UTP_REG_END                 0x00b05d4c
+#define BCHP_UTPPeakRate_FLOW5_UTP_REG_START               0x00b05d50
+#define BCHP_UTPPeakRate_FLOW5_UTP_REG_END                 0x00b05d5c
+#define BCHP_UTPPeakRate_FLOW6_UTP_REG_START               0x00b05d60
+#define BCHP_UTPPeakRate_FLOW6_UTP_REG_END                 0x00b05d6c
+#define BCHP_UTPPeakRate_FLOW7_UTP_REG_START               0x00b05d70
+#define BCHP_UTPPeakRate_FLOW7_UTP_REG_END                 0x00b05d7c
+#define BCHP_UTPPeakRate_FLOW8_UTP_REG_START               0x00b05d80
+#define BCHP_UTPPeakRate_FLOW8_UTP_REG_END                 0x00b05d8c
+#define BCHP_UTPPeakRate_FLOW9_UTP_REG_START               0x00b05d90
+#define BCHP_UTPPeakRate_FLOW9_UTP_REG_END                 0x00b05d9c
+#define BCHP_UTPPeakRate_FLOW10_UTP_REG_START              0x00b05da0
+#define BCHP_UTPPeakRate_FLOW10_UTP_REG_END                0x00b05dac
+#define BCHP_UTPPeakRate_FLOW11_UTP_REG_START              0x00b05db0
+#define BCHP_UTPPeakRate_FLOW11_UTP_REG_END                0x00b05dbc
+#define BCHP_UTPPeakRate_FLOW12_UTP_REG_START              0x00b05dc0
+#define BCHP_UTPPeakRate_FLOW12_UTP_REG_END                0x00b05dcc
+#define BCHP_UTPPeakRate_FLOW13_UTP_REG_START              0x00b05dd0
+#define BCHP_UTPPeakRate_FLOW13_UTP_REG_END                0x00b05ddc
+#define BCHP_UTPPeakRate_FLOW14_UTP_REG_START              0x00b05de0
+#define BCHP_UTPPeakRate_FLOW14_UTP_REG_END                0x00b05dec
+#define BCHP_UTPPeakRate_FLOW15_UTP_REG_START              0x00b05df0
+#define BCHP_UTPPeakRate_FLOW15_UTP_REG_END                0x00b05dfc
+#define BCHP_UTPTimer_0_UTP_REG_START                      0x00b05e00
+#define BCHP_UTPTimer_0_UTP_REG_END                        0x00b05e04
+#define BCHP_UTPTimer_1_UTP_REG_START                      0x00b05e08
+#define BCHP_UTPTimer_1_UTP_REG_END                        0x00b05e0c
+#define BCHP_UTPTimer_2_UTP_REG_START                      0x00b05e10
+#define BCHP_UTPTimer_2_UTP_REG_END                        0x00b05e14
+#define BCHP_UTPTimer_3_UTP_REG_START                      0x00b05e18
+#define BCHP_UTPTimer_3_UTP_REG_END                        0x00b05e1c
+#define BCHP_UTPTimer_4_UTP_REG_START                      0x00b05e20
+#define BCHP_UTPTimer_4_UTP_REG_END                        0x00b05e24
+#define BCHP_UTPTimer_5_UTP_REG_START                      0x00b05e28
+#define BCHP_UTPTimer_5_UTP_REG_END                        0x00b05e2c
+#define BCHP_UTPTimer_6_UTP_REG_START                      0x00b05e30
+#define BCHP_UTPTimer_6_UTP_REG_END                        0x00b05e34
+#define BCHP_UTPTimer_7_UTP_REG_START                      0x00b05e38
+#define BCHP_UTPTimer_7_UTP_REG_END                        0x00b05e3c
+#define BCHP_UTPTimer_8_UTP_REG_START                      0x00b05e40
+#define BCHP_UTPTimer_8_UTP_REG_END                        0x00b05e44
+#define BCHP_UTPTimer_9_UTP_REG_START                      0x00b05e48
+#define BCHP_UTPTimer_9_UTP_REG_END                        0x00b05e4c
+#define BCHP_UTPTimer_10_UTP_REG_START                     0x00b05e50
+#define BCHP_UTPTimer_10_UTP_REG_END                       0x00b05e54
+#define BCHP_UTPTimer_11_UTP_REG_START                     0x00b05e58
+#define BCHP_UTPTimer_11_UTP_REG_END                       0x00b05e5c
+#define BCHP_UTPTimer_12_UTP_REG_START                     0x00b05e60
+#define BCHP_UTPTimer_12_UTP_REG_END                       0x00b05e64
+#define BCHP_UTPTimer_13_UTP_REG_START                     0x00b05e68
+#define BCHP_UTPTimer_13_UTP_REG_END                       0x00b05e6c
+#define BCHP_UTPTimer_14_UTP_REG_START                     0x00b05e70
+#define BCHP_UTPTimer_14_UTP_REG_END                       0x00b05e74
+#define BCHP_UTPTimer_15_UTP_REG_START                     0x00b05e78
+#define BCHP_UTPTimer_15_UTP_REG_END                       0x00b05e7c
+#define BCHP_UTPTimer_16_UTP_REG_START                     0x00b05e80
+#define BCHP_UTPTimer_16_UTP_REG_END                       0x00b05e84
+#define BCHP_UTPTimer_17_UTP_REG_START                     0x00b05e88
+#define BCHP_UTPTimer_17_UTP_REG_END                       0x00b05e8c
+#define BCHP_UTPBytesSent_FLOW0_UTP_REG_START              0x00b05f00
+#define BCHP_UTPBytesSent_FLOW0_UTP_REG_END                0x00b05f04
+#define BCHP_UTPBytesSent_FLOW1_UTP_REG_START              0x00b05f08
+#define BCHP_UTPBytesSent_FLOW1_UTP_REG_END                0x00b05f0c
+#define BCHP_UTPBytesSent_FLOW2_UTP_REG_START              0x00b05f10
+#define BCHP_UTPBytesSent_FLOW2_UTP_REG_END                0x00b05f14
+#define BCHP_UTPBytesSent_FLOW3_UTP_REG_START              0x00b05f18
+#define BCHP_UTPBytesSent_FLOW3_UTP_REG_END                0x00b05f1c
+#define BCHP_UTPBytesSent_FLOW4_UTP_REG_START              0x00b05f20
+#define BCHP_UTPBytesSent_FLOW4_UTP_REG_END                0x00b05f24
+#define BCHP_UTPBytesSent_FLOW5_UTP_REG_START              0x00b05f28
+#define BCHP_UTPBytesSent_FLOW5_UTP_REG_END                0x00b05f2c
+#define BCHP_UTPBytesSent_FLOW6_UTP_REG_START              0x00b05f30
+#define BCHP_UTPBytesSent_FLOW6_UTP_REG_END                0x00b05f34
+#define BCHP_UTPBytesSent_FLOW7_UTP_REG_START              0x00b05f38
+#define BCHP_UTPBytesSent_FLOW7_UTP_REG_END                0x00b05f3c
+#define BCHP_UTPBytesSent_FLOW8_UTP_REG_START              0x00b05f40
+#define BCHP_UTPBytesSent_FLOW8_UTP_REG_END                0x00b05f44
+#define BCHP_UTPBytesSent_FLOW9_UTP_REG_START              0x00b05f48
+#define BCHP_UTPBytesSent_FLOW9_UTP_REG_END                0x00b05f4c
+#define BCHP_UTPBytesSent_FLOW10_UTP_REG_START             0x00b05f50
+#define BCHP_UTPBytesSent_FLOW10_UTP_REG_END               0x00b05f54
+#define BCHP_UTPBytesSent_FLOW11_UTP_REG_START             0x00b05f58
+#define BCHP_UTPBytesSent_FLOW11_UTP_REG_END               0x00b05f5c
+#define BCHP_UTPBytesSent_FLOW12_UTP_REG_START             0x00b05f60
+#define BCHP_UTPBytesSent_FLOW12_UTP_REG_END               0x00b05f64
+#define BCHP_UTPBytesSent_FLOW13_UTP_REG_START             0x00b05f68
+#define BCHP_UTPBytesSent_FLOW13_UTP_REG_END               0x00b05f6c
+#define BCHP_UTPBytesSent_FLOW14_UTP_REG_START             0x00b05f70
+#define BCHP_UTPBytesSent_FLOW14_UTP_REG_END               0x00b05f74
+#define BCHP_UTPBytesSent_FLOW15_UTP_REG_START             0x00b05f78
+#define BCHP_UTPBytesSent_FLOW15_UTP_REG_END               0x00b05f7c
+#define BCHP_UTPBytesSent_FLOW16_UTP_REG_START             0x00b05f80
+#define BCHP_UTPBytesSent_FLOW16_UTP_REG_END               0x00b05f84
+#define BCHP_UTPBytesSent_FLOW17_UTP_REG_START             0x00b05f88
+#define BCHP_UTPBytesSent_FLOW17_UTP_REG_END               0x00b05f8c
+#define BCHP_UTPBytesSent_FLOW18_UTP_REG_START             0x00b05f90
+#define BCHP_UTPBytesSent_FLOW18_UTP_REG_END               0x00b05f94
+#define BCHP_UTPBytesSent_FLOW19_UTP_REG_START             0x00b05f98
+#define BCHP_UTPBytesSent_FLOW19_UTP_REG_END               0x00b05f9c
+#define BCHP_UTPBytesSent_FLOW20_UTP_REG_START             0x00b05fa0
+#define BCHP_UTPBytesSent_FLOW20_UTP_REG_END               0x00b05fa4
+#define BCHP_UTPBytesSent_FLOW21_UTP_REG_START             0x00b05fa8
+#define BCHP_UTPBytesSent_FLOW21_UTP_REG_END               0x00b05fac
+#define BCHP_UTPBytesSent_FLOW22_UTP_REG_START             0x00b05fb0
+#define BCHP_UTPBytesSent_FLOW22_UTP_REG_END               0x00b05fb4
+#define BCHP_UTPBytesSent_FLOW23_UTP_REG_START             0x00b05fb8
+#define BCHP_UTPBytesSent_FLOW23_UTP_REG_END               0x00b05fbc
+#define BCHP_UTPBytesSent_FLOW24_UTP_REG_START             0x00b05fc0
+#define BCHP_UTPBytesSent_FLOW24_UTP_REG_END               0x00b05fc4
+#define BCHP_UTPBytesSent_FLOW25_UTP_REG_START             0x00b05fc8
+#define BCHP_UTPBytesSent_FLOW25_UTP_REG_END               0x00b05fcc
+#define BCHP_UTPBytesSent_FLOW26_UTP_REG_START             0x00b05fd0
+#define BCHP_UTPBytesSent_FLOW26_UTP_REG_END               0x00b05fd4
+#define BCHP_UTPBytesSent_FLOW27_UTP_REG_START             0x00b05fd8
+#define BCHP_UTPBytesSent_FLOW27_UTP_REG_END               0x00b05fdc
+#define BCHP_UTPBytesSent_FLOW28_UTP_REG_START             0x00b05fe0
+#define BCHP_UTPBytesSent_FLOW28_UTP_REG_END               0x00b05fe4
+#define BCHP_UTPBytesSent_FLOW29_UTP_REG_START             0x00b05fe8
+#define BCHP_UTPBytesSent_FLOW29_UTP_REG_END               0x00b05fec
+#define BCHP_UTPBytesSent_FLOW30_UTP_REG_START             0x00b05ff0
+#define BCHP_UTPBytesSent_FLOW30_UTP_REG_END               0x00b05ff4
+#define BCHP_UTPBytesSent_FLOW31_UTP_REG_START             0x00b05ff8
+#define BCHP_UTPBytesSent_FLOW31_UTP_REG_END               0x00b05ffc
+#define BCHP_UTPTokensInserted0_UTP_REG_START              0x00b06000
+#define BCHP_UTPTokensInserted0_UTP_REG_END                0x00b06004
+#define BCHP_UTPTokensInserted1_UTP_REG_START              0x00b06008
+#define BCHP_UTPTokensInserted1_UTP_REG_END                0x00b0600c
+#define BCHP_UTPTokensInserted2_UTP_REG_START              0x00b06010
+#define BCHP_UTPTokensInserted2_UTP_REG_END                0x00b06014
+#define BCHP_UTPTokensInserted3_UTP_REG_START              0x00b06018
+#define BCHP_UTPTokensInserted3_UTP_REG_END                0x00b0601c
+#define BCHP_UTPTokensInserted4_UTP_REG_START              0x00b06020
+#define BCHP_UTPTokensInserted4_UTP_REG_END                0x00b06024
+#define BCHP_UTPTokensInserted5_UTP_REG_START              0x00b06028
+#define BCHP_UTPTokensInserted5_UTP_REG_END                0x00b0602c
+#define BCHP_UTPTokensInserted6_UTP_REG_START              0x00b06030
+#define BCHP_UTPTokensInserted6_UTP_REG_END                0x00b06034
+#define BCHP_UTPTokensInserted7_UTP_REG_START              0x00b06038
+#define BCHP_UTPTokensInserted7_UTP_REG_END                0x00b0603c
+#define BCHP_UTPTokensInserted8_UTP_REG_START              0x00b06040
+#define BCHP_UTPTokensInserted8_UTP_REG_END                0x00b06044
+#define BCHP_UTPTokensInserted9_UTP_REG_START              0x00b06048
+#define BCHP_UTPTokensInserted9_UTP_REG_END                0x00b0604c
+#define BCHP_UTPTokensInserted10_UTP_REG_START             0x00b06050
+#define BCHP_UTPTokensInserted10_UTP_REG_END               0x00b06054
+#define BCHP_UTPTokensInserted11_UTP_REG_START             0x00b06058
+#define BCHP_UTPTokensInserted11_UTP_REG_END               0x00b0605c
+#define BCHP_UTPTokensInserted12_UTP_REG_START             0x00b06060
+#define BCHP_UTPTokensInserted12_UTP_REG_END               0x00b06064
+#define BCHP_UTPTokensInserted13_UTP_REG_START             0x00b06068
+#define BCHP_UTPTokensInserted13_UTP_REG_END               0x00b0606c
+#define BCHP_UTPTokensInserted14_UTP_REG_START             0x00b06070
+#define BCHP_UTPTokensInserted14_UTP_REG_END               0x00b06074
+#define BCHP_UTPTokensInserted15_UTP_REG_START             0x00b06078
+#define BCHP_UTPTokensInserted15_UTP_REG_END               0x00b0607c
+#define BCHP_UTPTokensInserted16_UTP_REG_START             0x00b06080
+#define BCHP_UTPTokensInserted16_UTP_REG_END               0x00b06084
+#define BCHP_UTPTokensInserted17_UTP_REG_START             0x00b06088
+#define BCHP_UTPTokensInserted17_UTP_REG_END               0x00b0608c
+#define BCHP_UTPTokensInserted18_UTP_REG_START             0x00b06090
+#define BCHP_UTPTokensInserted18_UTP_REG_END               0x00b06094
+#define BCHP_UTPTokensInserted19_UTP_REG_START             0x00b06098
+#define BCHP_UTPTokensInserted19_UTP_REG_END               0x00b0609c
+#define BCHP_UTPTokensInserted20_UTP_REG_START             0x00b060a0
+#define BCHP_UTPTokensInserted20_UTP_REG_END               0x00b060a4
+#define BCHP_UTPTokensInserted21_UTP_REG_START             0x00b060a8
+#define BCHP_UTPTokensInserted21_UTP_REG_END               0x00b060ac
+#define BCHP_UTPTokensInserted22_UTP_REG_START             0x00b060b0
+#define BCHP_UTPTokensInserted22_UTP_REG_END               0x00b060b4
+#define BCHP_UTPTokensInserted23_UTP_REG_START             0x00b060b8
+#define BCHP_UTPTokensInserted23_UTP_REG_END               0x00b060bc
+#define BCHP_UTPTokensInserted24_UTP_REG_START             0x00b060c0
+#define BCHP_UTPTokensInserted24_UTP_REG_END               0x00b060c4
+#define BCHP_UTPTokensInserted25_UTP_REG_START             0x00b060c8
+#define BCHP_UTPTokensInserted25_UTP_REG_END               0x00b060cc
+#define BCHP_UTPTokensInserted26_UTP_REG_START             0x00b060d0
+#define BCHP_UTPTokensInserted26_UTP_REG_END               0x00b060d4
+#define BCHP_UTPTokensInserted27_UTP_REG_START             0x00b060d8
+#define BCHP_UTPTokensInserted27_UTP_REG_END               0x00b060dc
+#define BCHP_UTPTokensInserted28_UTP_REG_START             0x00b060e0
+#define BCHP_UTPTokensInserted28_UTP_REG_END               0x00b060e4
+#define BCHP_UTPTokensInserted29_UTP_REG_START             0x00b060e8
+#define BCHP_UTPTokensInserted29_UTP_REG_END               0x00b060ec
+#define BCHP_UTPTokensInserted30_UTP_REG_START             0x00b060f0
+#define BCHP_UTPTokensInserted30_UTP_REG_END               0x00b060f4
+#define BCHP_UTPTokensInserted31_UTP_REG_START             0x00b060f8
+#define BCHP_UTPTokensInserted31_UTP_REG_END               0x00b060fc
+#define BCHP_UTPTokensDeleted_UTP_REG_START                0x00b06100
+#define BCHP_UTPTokensDeleted_UTP_REG_END                  0x00b0617c
+#define BCHP_UTPTokensReplaced_UTP_REG_START               0x00b06180
+#define BCHP_UTPTokensReplaced_UTP_REG_END                 0x00b061fc
+#define BCHP_IncMsgFifoCntr_UTP_REG_START                  0x00b06200
+#define BCHP_IncMsgFifoCntr_UTP_REG_END                    0x00b0627c
+#define BCHP_UTPAutoDelete_UTP_REG_START                   0x00b06400
+#define BCHP_UTPAutoDelete_UTP_REG_END                     0x00b06418
+#define BCHP_UTPInMsgEngine_UTP_REG_START                  0x00b06500
+#define BCHP_UTPInMsgEngine_UTP_REG_END                    0x00b06594
+#define BCHP_UTPDQMMsgEngine_UTP_REG_START                 0x00b06600
+#define BCHP_UTPDQMMsgEngine_UTP_REG_END                   0x00b06698
+#define BCHP_UTPMIBCounters_UTP_REG_START                  0x00b06700
+#define BCHP_UTPMIBCounters_UTP_REG_END                    0x00b06cbc
+#define BCHP_UTPAQMEngine_UTP_REG_START                    0x00b07000
+#define BCHP_UTPAQMEngine_UTP_REG_END                      0x00b07218
+#define BCHP_TokenMem_UTP_REG_START                        0x00b10000
+#define BCHP_TokenMem_UTP_REG_END                          0x00b1fffc
+#define BCHP_LEGACY_MAC_USM20_REG_START                    0x00e00000
+#define BCHP_LEGACY_MAC_USM20_REG_END                      0x00e00a00
+#define BCHP_TC_0_REG_START                                0x00e08000
+#define BCHP_TC_0_REG_END                                  0x00e080bc
+#define BCHP_TC_BANK0_0_REG_START                          0x00e08100
+#define BCHP_TC_BANK0_0_REG_END                            0x00e0811c
+#define BCHP_TC_BANK1_0_REG_START                          0x00e08120
+#define BCHP_TC_BANK1_0_REG_END                            0x00e0813c
+#define BCHP_TC_BANK2_0_REG_START                          0x00e08140
+#define BCHP_TC_BANK2_0_REG_END                            0x00e0815c
+#define BCHP_TC_BANK3_0_REG_START                          0x00e08160
+#define BCHP_TC_BANK3_0_REG_END                            0x00e0817c
+#define BCHP_TC_BANK4_0_REG_START                          0x00e08180
+#define BCHP_TC_BANK4_0_REG_END                            0x00e0819c
+#define BCHP_TC_BANK5_0_REG_START                          0x00e081a0
+#define BCHP_TC_BANK5_0_REG_END                            0x00e081bc
+#define BCHP_TC_BANK6_0_REG_START                          0x00e081c0
+#define BCHP_TC_BANK6_0_REG_END                            0x00e081dc
+#define BCHP_TC_BANK7_0_REG_START                          0x00e081e0
+#define BCHP_TC_BANK7_0_REG_END                            0x00e081fc
+#define BCHP_TC_BANK8_0_REG_START                          0x00e08200
+#define BCHP_TC_BANK8_0_REG_END                            0x00e0821c
+#define BCHP_TC_AUX_0_REG_START                            0x00e08300
+#define BCHP_TC_AUX_0_REG_END                              0x00e08394
+#define BCHP_TC_PRMBL_0_REG_START                          0x00e08400
+#define BCHP_TC_PRMBL_0_REG_END                            0x00e084bc
+#define BCHP_TC_AUX_EXT_0_REG_START                        0x00e084f0
+#define BCHP_TC_AUX_EXT_0_REG_END                          0x00e084f4
+#define BCHP_TC_1_REG_START                                0x00e09000
+#define BCHP_TC_1_REG_END                                  0x00e090bc
+#define BCHP_TC_BANK0_1_REG_START                          0x00e09100
+#define BCHP_TC_BANK0_1_REG_END                            0x00e0911c
+#define BCHP_TC_BANK1_1_REG_START                          0x00e09120
+#define BCHP_TC_BANK1_1_REG_END                            0x00e0913c
+#define BCHP_TC_BANK2_1_REG_START                          0x00e09140
+#define BCHP_TC_BANK2_1_REG_END                            0x00e0915c
+#define BCHP_TC_BANK3_1_REG_START                          0x00e09160
+#define BCHP_TC_BANK3_1_REG_END                            0x00e0917c
+#define BCHP_TC_BANK4_1_REG_START                          0x00e09180
+#define BCHP_TC_BANK4_1_REG_END                            0x00e0919c
+#define BCHP_TC_BANK5_1_REG_START                          0x00e091a0
+#define BCHP_TC_BANK5_1_REG_END                            0x00e091bc
+#define BCHP_TC_BANK6_1_REG_START                          0x00e091c0
+#define BCHP_TC_BANK6_1_REG_END                            0x00e091dc
+#define BCHP_TC_BANK7_1_REG_START                          0x00e091e0
+#define BCHP_TC_BANK7_1_REG_END                            0x00e091fc
+#define BCHP_TC_BANK8_1_REG_START                          0x00e09200
+#define BCHP_TC_BANK8_1_REG_END                            0x00e0921c
+#define BCHP_TC_AUX_1_REG_START                            0x00e09300
+#define BCHP_TC_AUX_1_REG_END                              0x00e09394
+#define BCHP_TC_PRMBL_1_REG_START                          0x00e09400
+#define BCHP_TC_PRMBL_1_REG_END                            0x00e094bc
+#define BCHP_TC_AUX_EXT_1_REG_START                        0x00e094f0
+#define BCHP_TC_AUX_EXT_1_REG_END                          0x00e094f4
+#define BCHP_TC_2_REG_START                                0x00e0a000
+#define BCHP_TC_2_REG_END                                  0x00e0a0bc
+#define BCHP_TC_BANK0_2_REG_START                          0x00e0a100
+#define BCHP_TC_BANK0_2_REG_END                            0x00e0a11c
+#define BCHP_TC_BANK1_2_REG_START                          0x00e0a120
+#define BCHP_TC_BANK1_2_REG_END                            0x00e0a13c
+#define BCHP_TC_BANK2_2_REG_START                          0x00e0a140
+#define BCHP_TC_BANK2_2_REG_END                            0x00e0a15c
+#define BCHP_TC_BANK3_2_REG_START                          0x00e0a160
+#define BCHP_TC_BANK3_2_REG_END                            0x00e0a17c
+#define BCHP_TC_BANK4_2_REG_START                          0x00e0a180
+#define BCHP_TC_BANK4_2_REG_END                            0x00e0a19c
+#define BCHP_TC_BANK5_2_REG_START                          0x00e0a1a0
+#define BCHP_TC_BANK5_2_REG_END                            0x00e0a1bc
+#define BCHP_TC_BANK6_2_REG_START                          0x00e0a1c0
+#define BCHP_TC_BANK6_2_REG_END                            0x00e0a1dc
+#define BCHP_TC_BANK7_2_REG_START                          0x00e0a1e0
+#define BCHP_TC_BANK7_2_REG_END                            0x00e0a1fc
+#define BCHP_TC_BANK8_2_REG_START                          0x00e0a200
+#define BCHP_TC_BANK8_2_REG_END                            0x00e0a21c
+#define BCHP_TC_AUX_2_REG_START                            0x00e0a300
+#define BCHP_TC_AUX_2_REG_END                              0x00e0a394
+#define BCHP_TC_PRMBL_2_REG_START                          0x00e0a400
+#define BCHP_TC_PRMBL_2_REG_END                            0x00e0a4bc
+#define BCHP_TC_AUX_EXT_2_REG_START                        0x00e0a4f0
+#define BCHP_TC_AUX_EXT_2_REG_END                          0x00e0a4f4
+#define BCHP_TC_3_REG_START                                0x00e0b000
+#define BCHP_TC_3_REG_END                                  0x00e0b0bc
+#define BCHP_TC_BANK0_3_REG_START                          0x00e0b100
+#define BCHP_TC_BANK0_3_REG_END                            0x00e0b11c
+#define BCHP_TC_BANK1_3_REG_START                          0x00e0b120
+#define BCHP_TC_BANK1_3_REG_END                            0x00e0b13c
+#define BCHP_TC_BANK2_3_REG_START                          0x00e0b140
+#define BCHP_TC_BANK2_3_REG_END                            0x00e0b15c
+#define BCHP_TC_BANK3_3_REG_START                          0x00e0b160
+#define BCHP_TC_BANK3_3_REG_END                            0x00e0b17c
+#define BCHP_TC_BANK4_3_REG_START                          0x00e0b180
+#define BCHP_TC_BANK4_3_REG_END                            0x00e0b19c
+#define BCHP_TC_BANK5_3_REG_START                          0x00e0b1a0
+#define BCHP_TC_BANK5_3_REG_END                            0x00e0b1bc
+#define BCHP_TC_BANK6_3_REG_START                          0x00e0b1c0
+#define BCHP_TC_BANK6_3_REG_END                            0x00e0b1dc
+#define BCHP_TC_BANK7_3_REG_START                          0x00e0b1e0
+#define BCHP_TC_BANK7_3_REG_END                            0x00e0b1fc
+#define BCHP_TC_BANK8_3_REG_START                          0x00e0b200
+#define BCHP_TC_BANK8_3_REG_END                            0x00e0b21c
+#define BCHP_TC_AUX_3_REG_START                            0x00e0b300
+#define BCHP_TC_AUX_3_REG_END                              0x00e0b394
+#define BCHP_TC_PRMBL_3_REG_START                          0x00e0b400
+#define BCHP_TC_PRMBL_3_REG_END                            0x00e0b4bc
+#define BCHP_TC_AUX_EXT_3_REG_START                        0x00e0b4f0
+#define BCHP_TC_AUX_EXT_3_REG_END                          0x00e0b4f4
+#define BCHP_TC_4_REG_START                                0x00e0c000
+#define BCHP_TC_4_REG_END                                  0x00e0c0bc
+#define BCHP_TC_BANK0_4_REG_START                          0x00e0c100
+#define BCHP_TC_BANK0_4_REG_END                            0x00e0c11c
+#define BCHP_TC_BANK1_4_REG_START                          0x00e0c120
+#define BCHP_TC_BANK1_4_REG_END                            0x00e0c13c
+#define BCHP_TC_BANK2_4_REG_START                          0x00e0c140
+#define BCHP_TC_BANK2_4_REG_END                            0x00e0c15c
+#define BCHP_TC_BANK3_4_REG_START                          0x00e0c160
+#define BCHP_TC_BANK3_4_REG_END                            0x00e0c17c
+#define BCHP_TC_BANK4_4_REG_START                          0x00e0c180
+#define BCHP_TC_BANK4_4_REG_END                            0x00e0c19c
+#define BCHP_TC_BANK5_4_REG_START                          0x00e0c1a0
+#define BCHP_TC_BANK5_4_REG_END                            0x00e0c1bc
+#define BCHP_TC_BANK6_4_REG_START                          0x00e0c1c0
+#define BCHP_TC_BANK6_4_REG_END                            0x00e0c1dc
+#define BCHP_TC_BANK7_4_REG_START                          0x00e0c1e0
+#define BCHP_TC_BANK7_4_REG_END                            0x00e0c1fc
+#define BCHP_TC_BANK8_4_REG_START                          0x00e0c200
+#define BCHP_TC_BANK8_4_REG_END                            0x00e0c21c
+#define BCHP_TC_AUX_4_REG_START                            0x00e0c300
+#define BCHP_TC_AUX_4_REG_END                              0x00e0c394
+#define BCHP_TC_PRMBL_4_REG_START                          0x00e0c400
+#define BCHP_TC_PRMBL_4_REG_END                            0x00e0c4bc
+#define BCHP_TC_AUX_EXT_4_REG_START                        0x00e0c4f0
+#define BCHP_TC_AUX_EXT_4_REG_END                          0x00e0c4f4
+#define BCHP_TC_5_REG_START                                0x00e0d000
+#define BCHP_TC_5_REG_END                                  0x00e0d0bc
+#define BCHP_TC_BANK0_5_REG_START                          0x00e0d100
+#define BCHP_TC_BANK0_5_REG_END                            0x00e0d11c
+#define BCHP_TC_BANK1_5_REG_START                          0x00e0d120
+#define BCHP_TC_BANK1_5_REG_END                            0x00e0d13c
+#define BCHP_TC_BANK2_5_REG_START                          0x00e0d140
+#define BCHP_TC_BANK2_5_REG_END                            0x00e0d15c
+#define BCHP_TC_BANK3_5_REG_START                          0x00e0d160
+#define BCHP_TC_BANK3_5_REG_END                            0x00e0d17c
+#define BCHP_TC_BANK4_5_REG_START                          0x00e0d180
+#define BCHP_TC_BANK4_5_REG_END                            0x00e0d19c
+#define BCHP_TC_BANK5_5_REG_START                          0x00e0d1a0
+#define BCHP_TC_BANK5_5_REG_END                            0x00e0d1bc
+#define BCHP_TC_BANK6_5_REG_START                          0x00e0d1c0
+#define BCHP_TC_BANK6_5_REG_END                            0x00e0d1dc
+#define BCHP_TC_BANK7_5_REG_START                          0x00e0d1e0
+#define BCHP_TC_BANK7_5_REG_END                            0x00e0d1fc
+#define BCHP_TC_BANK8_5_REG_START                          0x00e0d200
+#define BCHP_TC_BANK8_5_REG_END                            0x00e0d21c
+#define BCHP_TC_AUX_5_REG_START                            0x00e0d300
+#define BCHP_TC_AUX_5_REG_END                              0x00e0d394
+#define BCHP_TC_PRMBL_5_REG_START                          0x00e0d400
+#define BCHP_TC_PRMBL_5_REG_END                            0x00e0d4bc
+#define BCHP_TC_AUX_EXT_5_REG_START                        0x00e0d4f0
+#define BCHP_TC_AUX_EXT_5_REG_END                          0x00e0d4f4
+#define BCHP_TC_6_REG_START                                0x00e0e000
+#define BCHP_TC_6_REG_END                                  0x00e0e0bc
+#define BCHP_TC_BANK0_6_REG_START                          0x00e0e100
+#define BCHP_TC_BANK0_6_REG_END                            0x00e0e11c
+#define BCHP_TC_BANK1_6_REG_START                          0x00e0e120
+#define BCHP_TC_BANK1_6_REG_END                            0x00e0e13c
+#define BCHP_TC_BANK2_6_REG_START                          0x00e0e140
+#define BCHP_TC_BANK2_6_REG_END                            0x00e0e15c
+#define BCHP_TC_BANK3_6_REG_START                          0x00e0e160
+#define BCHP_TC_BANK3_6_REG_END                            0x00e0e17c
+#define BCHP_TC_BANK4_6_REG_START                          0x00e0e180
+#define BCHP_TC_BANK4_6_REG_END                            0x00e0e19c
+#define BCHP_TC_BANK5_6_REG_START                          0x00e0e1a0
+#define BCHP_TC_BANK5_6_REG_END                            0x00e0e1bc
+#define BCHP_TC_BANK6_6_REG_START                          0x00e0e1c0
+#define BCHP_TC_BANK6_6_REG_END                            0x00e0e1dc
+#define BCHP_TC_BANK7_6_REG_START                          0x00e0e1e0
+#define BCHP_TC_BANK7_6_REG_END                            0x00e0e1fc
+#define BCHP_TC_BANK8_6_REG_START                          0x00e0e200
+#define BCHP_TC_BANK8_6_REG_END                            0x00e0e21c
+#define BCHP_TC_AUX_6_REG_START                            0x00e0e300
+#define BCHP_TC_AUX_6_REG_END                              0x00e0e394
+#define BCHP_TC_PRMBL_6_REG_START                          0x00e0e400
+#define BCHP_TC_PRMBL_6_REG_END                            0x00e0e4bc
+#define BCHP_TC_AUX_EXT_6_REG_START                        0x00e0e4f0
+#define BCHP_TC_AUX_EXT_6_REG_END                          0x00e0e4f4
+#define BCHP_TC_7_REG_START                                0x00e0f000
+#define BCHP_TC_7_REG_END                                  0x00e0f0bc
+#define BCHP_TC_BANK0_7_REG_START                          0x00e0f100
+#define BCHP_TC_BANK0_7_REG_END                            0x00e0f11c
+#define BCHP_TC_BANK1_7_REG_START                          0x00e0f120
+#define BCHP_TC_BANK1_7_REG_END                            0x00e0f13c
+#define BCHP_TC_BANK2_7_REG_START                          0x00e0f140
+#define BCHP_TC_BANK2_7_REG_END                            0x00e0f15c
+#define BCHP_TC_BANK3_7_REG_START                          0x00e0f160
+#define BCHP_TC_BANK3_7_REG_END                            0x00e0f17c
+#define BCHP_TC_BANK4_7_REG_START                          0x00e0f180
+#define BCHP_TC_BANK4_7_REG_END                            0x00e0f19c
+#define BCHP_TC_BANK5_7_REG_START                          0x00e0f1a0
+#define BCHP_TC_BANK5_7_REG_END                            0x00e0f1bc
+#define BCHP_TC_BANK6_7_REG_START                          0x00e0f1c0
+#define BCHP_TC_BANK6_7_REG_END                            0x00e0f1dc
+#define BCHP_TC_BANK7_7_REG_START                          0x00e0f1e0
+#define BCHP_TC_BANK7_7_REG_END                            0x00e0f1fc
+#define BCHP_TC_BANK8_7_REG_START                          0x00e0f200
+#define BCHP_TC_BANK8_7_REG_END                            0x00e0f21c
+#define BCHP_TC_AUX_7_REG_START                            0x00e0f300
+#define BCHP_TC_AUX_7_REG_END                              0x00e0f394
+#define BCHP_TC_PRMBL_7_REG_START                          0x00e0f400
+#define BCHP_TC_PRMBL_7_REG_END                            0x00e0f4bc
+#define BCHP_TC_AUX_EXT_7_REG_START                        0x00e0f4f0
+#define BCHP_TC_AUX_EXT_7_REG_END                          0x00e0f4f4
+#define BCHP_US_TOP_REG_START                              0x00e10000
+#define BCHP_US_TOP_REG_END                                0x00e107fc
+#define BCHP_US_MBSC_REG_START                             0x00e10c00
+#define BCHP_US_MBSC_REG_END                               0x00e10c7c
+#define BCHP_US_NOISE_REG_START                            0x00e10d00
+#define BCHP_US_NOISE_REG_END                              0x00e10dfc
+#define BCHP_US_RF_CLIP_REG_START                          0x00e11000
+#define BCHP_US_RF_CLIP_REG_END                            0x00e113fc
+#define BCHP_US_WDAC0_REG_START                            0x00e11c00
+#define BCHP_US_WDAC0_REG_END                              0x00e11cfc
+#define BCHP_US_WDAC1_REG_START                            0x00e11d00
+#define BCHP_US_WDAC1_REG_END                              0x00e11dfc
+#define BCHP_US_OFDM0_REG_START                            0x00e12000
+#define BCHP_US_OFDM0_REG_END                              0x00e12204
+#define BCHP_US_OFDM1_REG_START                            0x00e12400
+#define BCHP_US_OFDM1_REG_END                              0x00e12604
+#define BCHP_US_PDAC0_REG_START                            0x00e13800
+#define BCHP_US_PDAC0_REG_END                              0x00e138fc
+#define BCHP_US_PDAC1_REG_START                            0x00e13900
+#define BCHP_US_PDAC1_REG_END                              0x00e139fc
+#define BCHP_US_PDAC2_REG_START                            0x00e13a00
+#define BCHP_US_PDAC2_REG_END                              0x00e13afc
+#define BCHP_US_PDAC3_REG_START                            0x00e13b00
+#define BCHP_US_PDAC3_REG_END                              0x00e13bfc
+#define BCHP_US_CORE0_REG_START                            0x00e14000
+#define BCHP_US_CORE0_REG_END                              0x00e143fc
+#define BCHP_US_CORE1_REG_START                            0x00e14400
+#define BCHP_US_CORE1_REG_END                              0x00e147fc
+#define BCHP_US_CORE2_REG_START                            0x00e14800
+#define BCHP_US_CORE2_REG_END                              0x00e14bfc
+#define BCHP_US_CORE3_REG_START                            0x00e14c00
+#define BCHP_US_CORE3_REG_END                              0x00e14ffc
+#define BCHP_US_CORE4_REG_START                            0x00e15000
+#define BCHP_US_CORE4_REG_END                              0x00e153fc
+#define BCHP_US_CORE5_REG_START                            0x00e15400
+#define BCHP_US_CORE5_REG_END                              0x00e157fc
+#define BCHP_US_CORE6_REG_START                            0x00e15800
+#define BCHP_US_CORE6_REG_END                              0x00e15bfc
+#define BCHP_US_CORE7_REG_START                            0x00e15c00
+#define BCHP_US_CORE7_REG_END                              0x00e15ffc
+#define BCHP_ChannelRegs_USM30_REG_START                   0x00e18000
+#define BCHP_ChannelRegs_USM30_REG_END                     0x00e183bc
+#define BCHP_ChannelQueRegs_USM30_REG_START                0x00e18600
+#define BCHP_ChannelQueRegs_USM30_REG_END                  0x00e1902b
+#define BCHP_QueueRegs_USM30_REG_START                     0x00e19100
+#define BCHP_QueueRegs_USM30_REG_END                       0x00e194fc
+#define BCHP_SIDRegs_USM30_REG_START                       0x00e1a000
+#define BCHP_SIDRegs_USM30_REG_END                         0x00e1a7f2
+#define BCHP_GroupSIDRegs_USM30_REG_START                  0x00e1a800
+#define BCHP_GroupSIDRegs_USM30_REG_END                    0x00e1a81e
+#define BCHP_CalcPhyRegs_USM30_REG_START                   0x00e1a900
+#define BCHP_CalcPhyRegs_USM30_REG_END                     0x00e1a934
+#define BCHP_SimControlRegs_USM30_REG_START                0x00e1aa00
+#define BCHP_SimControlRegs_USM30_REG_END                  0x00e1aa84
+#define BCHP_InterruptRegs_USM30_REG_START                 0x00e1ab00
+#define BCHP_InterruptRegs_USM30_REG_END                   0x00e1ab99
+#define BCHP_MiscRegs_USM30_REG_START                      0x00e1ac00
+#define BCHP_MiscRegs_USM30_REG_END                        0x00e1accc
+#define BCHP_QueueRegs_ReadOnly_USM30_REG_START            0x00e1b000
+#define BCHP_QueueRegs_ReadOnly_USM30_REG_END              0x00e1b3f0
+#define BCHP_MIBCountersRegs_USM30_REG_START               0x00e1b800
+#define BCHP_MIBCountersRegs_USM30_REG_END                 0x00e1bffc
+#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_START       0x00e1c300
+#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_END         0x00e1c4fc
+#define BCHP_DiagConfigRegs_USM30_REG_START                0x00e1c500
+#define BCHP_DiagConfigRegs_USM30_REG_END                  0x00e1c54c
+#define BCHP_DiagMsgRegs_USM30_REG_START                   0x00e1c600
+#define BCHP_DiagMsgRegs_USM30_REG_END                     0x00e1c710
+#define BCHP_BaseReserved_DTP_REG_START                    0x01000000
+#define BCHP_BaseReserved_DTP_REG_END                      0x01000000
+#define BCHP_Control_DTP_REG_START                         0x01001000
+#define BCHP_Control_DTP_REG_END                           0x010010fc
+#define BCHP_OutgoingMessageFIFO_DTP_REG_START             0x01001100
+#define BCHP_OutgoingMessageFIFO_DTP_REG_END               0x0100117c
+#define BCHP_IncomingMessageFIFO_DTP_REG_START             0x01001200
+#define BCHP_IncomingMessageFIFO_DTP_REG_END               0x0100127c
+#define BCHP_DMA0_DTP_REG_START                            0x01001300
+#define BCHP_DMA0_DTP_REG_END                              0x0100131c
+#define BCHP_DMA1_DTP_REG_START                            0x01001320
+#define BCHP_DMA1_DTP_REG_END                              0x0100133c
+#define BCHP_DMAHI0_DTP_REG_START                          0x01001340
+#define BCHP_DMAHI0_DTP_REG_END                            0x0100134c
+#define BCHP_DMAHI1_DTP_REG_START                          0x01001350
+#define BCHP_DMAHI1_DTP_REG_END                            0x0100135c
+#define BCHP_Token_DTP_REG_START                           0x01001400
+#define BCHP_Token_DTP_REG_END                             0x01001420
+#define BCHP_PerfPower_DTP_REG_START                       0x01001600
+#define BCHP_PerfPower_DTP_REG_END                         0x01001640
+#define BCHP_MessageID_DTP_REG_START                       0x01001700
+#define BCHP_MessageID_DTP_REG_END                         0x0100177c
+#define BCHP_HWCounters_DTP_REG_START                      0x01001900
+#define BCHP_HWCounters_DTP_REG_END                        0x01001944
+#define BCHP_DQM_0_31_DTP_REG_START                        0x01001c00
+#define BCHP_DQM_0_31_DTP_REG_END                          0x01001c48
+#define BCHP_DQM_32_63_DTP_REG_START                       0x01001d00
+#define BCHP_DQM_32_63_DTP_REG_END                         0x01001d48
+#define BCHP_QUEUE_TIMER_DTP_REG_START                     0x01002000
+#define BCHP_QUEUE_TIMER_DTP_REG_END                       0x010021fc
+#define BCHP_QUEUE_STATUS_0_31_DTP_REG_START               0x01002800
+#define BCHP_QUEUE_STATUS_0_31_DTP_REG_END                 0x0100287c
+#define BCHP_QUEUE_STATUS_32_63_DTP_REG_START              0x01002900
+#define BCHP_QUEUE_STATUS_32_63_DTP_REG_END                0x0100297c
+#define BCHP_QUEUE_MIB_0_31_DTP_REG_START                  0x01003000
+#define BCHP_QUEUE_MIB_0_31_DTP_REG_END                    0x0100317c
+#define BCHP_QUEUE_MIB_32_63_DTP_REG_START                 0x01003200
+#define BCHP_QUEUE_MIB_32_63_DTP_REG_END                   0x0100337c
+#define BCHP_QUEUE_0_CNTRL_DTP_REG_START                   0x01004000
+#define BCHP_QUEUE_0_CNTRL_DTP_REG_END                     0x0100400c
+#define BCHP_QUEUE_1_CNTRL_DTP_REG_START                   0x01004010
+#define BCHP_QUEUE_1_CNTRL_DTP_REG_END                     0x0100401c
+#define BCHP_QUEUE_2_CNTRL_DTP_REG_START                   0x01004020
+#define BCHP_QUEUE_2_CNTRL_DTP_REG_END                     0x0100402c
+#define BCHP_QUEUE_3_CNTRL_DTP_REG_START                   0x01004030
+#define BCHP_QUEUE_3_CNTRL_DTP_REG_END                     0x0100403c
+#define BCHP_QUEUE_4_CNTRL_DTP_REG_START                   0x01004040
+#define BCHP_QUEUE_4_CNTRL_DTP_REG_END                     0x0100404c
+#define BCHP_QUEUE_5_CNTRL_DTP_REG_START                   0x01004050
+#define BCHP_QUEUE_5_CNTRL_DTP_REG_END                     0x0100405c
+#define BCHP_QUEUE_6_CNTRL_DTP_REG_START                   0x01004060
+#define BCHP_QUEUE_6_CNTRL_DTP_REG_END                     0x0100406c
+#define BCHP_QUEUE_7_CNTRL_DTP_REG_START                   0x01004070
+#define BCHP_QUEUE_7_CNTRL_DTP_REG_END                     0x0100407c
+#define BCHP_QUEUE_8_CNTRL_DTP_REG_START                   0x01004080
+#define BCHP_QUEUE_8_CNTRL_DTP_REG_END                     0x0100408c
+#define BCHP_QUEUE_9_CNTRL_DTP_REG_START                   0x01004090
+#define BCHP_QUEUE_9_CNTRL_DTP_REG_END                     0x0100409c
+#define BCHP_QUEUE_10_CNTRL_DTP_REG_START                  0x010040a0
+#define BCHP_QUEUE_10_CNTRL_DTP_REG_END                    0x010040ac
+#define BCHP_QUEUE_11_CNTRL_DTP_REG_START                  0x010040b0
+#define BCHP_QUEUE_11_CNTRL_DTP_REG_END                    0x010040bc
+#define BCHP_QUEUE_12_CNTRL_DTP_REG_START                  0x010040c0
+#define BCHP_QUEUE_12_CNTRL_DTP_REG_END                    0x010040cc
+#define BCHP_QUEUE_13_CNTRL_DTP_REG_START                  0x010040d0
+#define BCHP_QUEUE_13_CNTRL_DTP_REG_END                    0x010040dc
+#define BCHP_QUEUE_14_CNTRL_DTP_REG_START                  0x010040e0
+#define BCHP_QUEUE_14_CNTRL_DTP_REG_END                    0x010040ec
+#define BCHP_QUEUE_15_CNTRL_DTP_REG_START                  0x010040f0
+#define BCHP_QUEUE_15_CNTRL_DTP_REG_END                    0x010040fc
+#define BCHP_QUEUE_16_CNTRL_DTP_REG_START                  0x01004100
+#define BCHP_QUEUE_16_CNTRL_DTP_REG_END                    0x0100410c
+#define BCHP_QUEUE_17_CNTRL_DTP_REG_START                  0x01004110
+#define BCHP_QUEUE_17_CNTRL_DTP_REG_END                    0x0100411c
+#define BCHP_QUEUE_18_CNTRL_DTP_REG_START                  0x01004120
+#define BCHP_QUEUE_18_CNTRL_DTP_REG_END                    0x0100412c
+#define BCHP_QUEUE_19_CNTRL_DTP_REG_START                  0x01004130
+#define BCHP_QUEUE_19_CNTRL_DTP_REG_END                    0x0100413c
+#define BCHP_QUEUE_20_CNTRL_DTP_REG_START                  0x01004140
+#define BCHP_QUEUE_20_CNTRL_DTP_REG_END                    0x0100414c
+#define BCHP_QUEUE_21_CNTRL_DTP_REG_START                  0x01004150
+#define BCHP_QUEUE_21_CNTRL_DTP_REG_END                    0x0100415c
+#define BCHP_QUEUE_22_CNTRL_DTP_REG_START                  0x01004160
+#define BCHP_QUEUE_22_CNTRL_DTP_REG_END                    0x0100416c
+#define BCHP_QUEUE_23_CNTRL_DTP_REG_START                  0x01004170
+#define BCHP_QUEUE_23_CNTRL_DTP_REG_END                    0x0100417c
+#define BCHP_QUEUE_24_CNTRL_DTP_REG_START                  0x01004180
+#define BCHP_QUEUE_24_CNTRL_DTP_REG_END                    0x0100418c
+#define BCHP_QUEUE_25_CNTRL_DTP_REG_START                  0x01004190
+#define BCHP_QUEUE_25_CNTRL_DTP_REG_END                    0x0100419c
+#define BCHP_QUEUE_26_CNTRL_DTP_REG_START                  0x010041a0
+#define BCHP_QUEUE_26_CNTRL_DTP_REG_END                    0x010041ac
+#define BCHP_QUEUE_27_CNTRL_DTP_REG_START                  0x010041b0
+#define BCHP_QUEUE_27_CNTRL_DTP_REG_END                    0x010041bc
+#define BCHP_QUEUE_28_CNTRL_DTP_REG_START                  0x010041c0
+#define BCHP_QUEUE_28_CNTRL_DTP_REG_END                    0x010041cc
+#define BCHP_QUEUE_29_CNTRL_DTP_REG_START                  0x010041d0
+#define BCHP_QUEUE_29_CNTRL_DTP_REG_END                    0x010041dc
+#define BCHP_QUEUE_30_CNTRL_DTP_REG_START                  0x010041e0
+#define BCHP_QUEUE_30_CNTRL_DTP_REG_END                    0x010041ec
+#define BCHP_QUEUE_31_CNTRL_DTP_REG_START                  0x010041f0
+#define BCHP_QUEUE_31_CNTRL_DTP_REG_END                    0x010041fc
+#define BCHP_QUEUE_32_CNTRL_DTP_REG_START                  0x01004200
+#define BCHP_QUEUE_32_CNTRL_DTP_REG_END                    0x0100420c
+#define BCHP_QUEUE_33_CNTRL_DTP_REG_START                  0x01004210
+#define BCHP_QUEUE_33_CNTRL_DTP_REG_END                    0x0100421c
+#define BCHP_QUEUE_34_CNTRL_DTP_REG_START                  0x01004220
+#define BCHP_QUEUE_34_CNTRL_DTP_REG_END                    0x0100422c
+#define BCHP_QUEUE_35_CNTRL_DTP_REG_START                  0x01004230
+#define BCHP_QUEUE_35_CNTRL_DTP_REG_END                    0x0100423c
+#define BCHP_QUEUE_36_CNTRL_DTP_REG_START                  0x01004240
+#define BCHP_QUEUE_36_CNTRL_DTP_REG_END                    0x0100424c
+#define BCHP_QUEUE_37_CNTRL_DTP_REG_START                  0x01004250
+#define BCHP_QUEUE_37_CNTRL_DTP_REG_END                    0x0100425c
+#define BCHP_QUEUE_38_CNTRL_DTP_REG_START                  0x01004260
+#define BCHP_QUEUE_38_CNTRL_DTP_REG_END                    0x0100426c
+#define BCHP_QUEUE_39_CNTRL_DTP_REG_START                  0x01004270
+#define BCHP_QUEUE_39_CNTRL_DTP_REG_END                    0x0100427c
+#define BCHP_QUEUE_40_CNTRL_DTP_REG_START                  0x01004280
+#define BCHP_QUEUE_40_CNTRL_DTP_REG_END                    0x0100428c
+#define BCHP_QUEUE_41_CNTRL_DTP_REG_START                  0x01004290
+#define BCHP_QUEUE_41_CNTRL_DTP_REG_END                    0x0100429c
+#define BCHP_QUEUE_42_CNTRL_DTP_REG_START                  0x010042a0
+#define BCHP_QUEUE_42_CNTRL_DTP_REG_END                    0x010042ac
+#define BCHP_QUEUE_43_CNTRL_DTP_REG_START                  0x010042b0
+#define BCHP_QUEUE_43_CNTRL_DTP_REG_END                    0x010042bc
+#define BCHP_QUEUE_44_CNTRL_DTP_REG_START                  0x010042c0
+#define BCHP_QUEUE_44_CNTRL_DTP_REG_END                    0x010042cc
+#define BCHP_QUEUE_45_CNTRL_DTP_REG_START                  0x010042d0
+#define BCHP_QUEUE_45_CNTRL_DTP_REG_END                    0x010042dc
+#define BCHP_QUEUE_46_CNTRL_DTP_REG_START                  0x010042e0
+#define BCHP_QUEUE_46_CNTRL_DTP_REG_END                    0x010042ec
+#define BCHP_QUEUE_47_CNTRL_DTP_REG_START                  0x010042f0
+#define BCHP_QUEUE_47_CNTRL_DTP_REG_END                    0x010042fc
+#define BCHP_QUEUE_48_CNTRL_DTP_REG_START                  0x01004300
+#define BCHP_QUEUE_48_CNTRL_DTP_REG_END                    0x0100430c
+#define BCHP_QUEUE_49_CNTRL_DTP_REG_START                  0x01004310
+#define BCHP_QUEUE_49_CNTRL_DTP_REG_END                    0x0100431c
+#define BCHP_QUEUE_50_CNTRL_DTP_REG_START                  0x01004320
+#define BCHP_QUEUE_50_CNTRL_DTP_REG_END                    0x0100432c
+#define BCHP_QUEUE_51_CNTRL_DTP_REG_START                  0x01004330
+#define BCHP_QUEUE_51_CNTRL_DTP_REG_END                    0x0100433c
+#define BCHP_QUEUE_52_CNTRL_DTP_REG_START                  0x01004340
+#define BCHP_QUEUE_52_CNTRL_DTP_REG_END                    0x0100434c
+#define BCHP_QUEUE_53_CNTRL_DTP_REG_START                  0x01004350
+#define BCHP_QUEUE_53_CNTRL_DTP_REG_END                    0x0100435c
+#define BCHP_QUEUE_54_CNTRL_DTP_REG_START                  0x01004360
+#define BCHP_QUEUE_54_CNTRL_DTP_REG_END                    0x0100436c
+#define BCHP_QUEUE_55_CNTRL_DTP_REG_START                  0x01004370
+#define BCHP_QUEUE_55_CNTRL_DTP_REG_END                    0x0100437c
+#define BCHP_QUEUE_56_CNTRL_DTP_REG_START                  0x01004380
+#define BCHP_QUEUE_56_CNTRL_DTP_REG_END                    0x0100438c
+#define BCHP_QUEUE_57_CNTRL_DTP_REG_START                  0x01004390
+#define BCHP_QUEUE_57_CNTRL_DTP_REG_END                    0x0100439c
+#define BCHP_QUEUE_58_CNTRL_DTP_REG_START                  0x010043a0
+#define BCHP_QUEUE_58_CNTRL_DTP_REG_END                    0x010043ac
+#define BCHP_QUEUE_59_CNTRL_DTP_REG_START                  0x010043b0
+#define BCHP_QUEUE_59_CNTRL_DTP_REG_END                    0x010043bc
+#define BCHP_QUEUE_60_CNTRL_DTP_REG_START                  0x010043c0
+#define BCHP_QUEUE_60_CNTRL_DTP_REG_END                    0x010043cc
+#define BCHP_QUEUE_61_CNTRL_DTP_REG_START                  0x010043d0
+#define BCHP_QUEUE_61_CNTRL_DTP_REG_END                    0x010043dc
+#define BCHP_QUEUE_62_CNTRL_DTP_REG_START                  0x010043e0
+#define BCHP_QUEUE_62_CNTRL_DTP_REG_END                    0x010043ec
+#define BCHP_QUEUE_63_CNTRL_DTP_REG_START                  0x010043f0
+#define BCHP_QUEUE_63_CNTRL_DTP_REG_END                    0x010043fc
+#define BCHP_QUEUE_0_DATA_DTP_REG_START                    0x01005000
+#define BCHP_QUEUE_0_DATA_DTP_REG_END                      0x0100500c
+#define BCHP_QUEUE_1_DATA_DTP_REG_START                    0x01005010
+#define BCHP_QUEUE_1_DATA_DTP_REG_END                      0x0100501c
+#define BCHP_QUEUE_2_DATA_DTP_REG_START                    0x01005020
+#define BCHP_QUEUE_2_DATA_DTP_REG_END                      0x0100502c
+#define BCHP_QUEUE_3_DATA_DTP_REG_START                    0x01005030
+#define BCHP_QUEUE_3_DATA_DTP_REG_END                      0x0100503c
+#define BCHP_QUEUE_4_DATA_DTP_REG_START                    0x01005040
+#define BCHP_QUEUE_4_DATA_DTP_REG_END                      0x0100504c
+#define BCHP_QUEUE_5_DATA_DTP_REG_START                    0x01005050
+#define BCHP_QUEUE_5_DATA_DTP_REG_END                      0x0100505c
+#define BCHP_QUEUE_6_DATA_DTP_REG_START                    0x01005060
+#define BCHP_QUEUE_6_DATA_DTP_REG_END                      0x0100506c
+#define BCHP_QUEUE_7_DATA_DTP_REG_START                    0x01005070
+#define BCHP_QUEUE_7_DATA_DTP_REG_END                      0x0100507c
+#define BCHP_QUEUE_8_DATA_DTP_REG_START                    0x01005080
+#define BCHP_QUEUE_8_DATA_DTP_REG_END                      0x0100508c
+#define BCHP_QUEUE_9_DATA_DTP_REG_START                    0x01005090
+#define BCHP_QUEUE_9_DATA_DTP_REG_END                      0x0100509c
+#define BCHP_QUEUE_10_DATA_DTP_REG_START                   0x010050a0
+#define BCHP_QUEUE_10_DATA_DTP_REG_END                     0x010050ac
+#define BCHP_QUEUE_11_DATA_DTP_REG_START                   0x010050b0
+#define BCHP_QUEUE_11_DATA_DTP_REG_END                     0x010050bc
+#define BCHP_QUEUE_12_DATA_DTP_REG_START                   0x010050c0
+#define BCHP_QUEUE_12_DATA_DTP_REG_END                     0x010050cc
+#define BCHP_QUEUE_13_DATA_DTP_REG_START                   0x010050d0
+#define BCHP_QUEUE_13_DATA_DTP_REG_END                     0x010050dc
+#define BCHP_QUEUE_14_DATA_DTP_REG_START                   0x010050e0
+#define BCHP_QUEUE_14_DATA_DTP_REG_END                     0x010050ec
+#define BCHP_QUEUE_15_DATA_DTP_REG_START                   0x010050f0
+#define BCHP_QUEUE_15_DATA_DTP_REG_END                     0x010050fc
+#define BCHP_QUEUE_16_DATA_DTP_REG_START                   0x01005100
+#define BCHP_QUEUE_16_DATA_DTP_REG_END                     0x0100510c
+#define BCHP_QUEUE_17_DATA_DTP_REG_START                   0x01005110
+#define BCHP_QUEUE_17_DATA_DTP_REG_END                     0x0100511c
+#define BCHP_QUEUE_18_DATA_DTP_REG_START                   0x01005120
+#define BCHP_QUEUE_18_DATA_DTP_REG_END                     0x0100512c
+#define BCHP_QUEUE_19_DATA_DTP_REG_START                   0x01005130
+#define BCHP_QUEUE_19_DATA_DTP_REG_END                     0x0100513c
+#define BCHP_QUEUE_20_DATA_DTP_REG_START                   0x01005140
+#define BCHP_QUEUE_20_DATA_DTP_REG_END                     0x0100514c
+#define BCHP_QUEUE_21_DATA_DTP_REG_START                   0x01005150
+#define BCHP_QUEUE_21_DATA_DTP_REG_END                     0x0100515c
+#define BCHP_QUEUE_22_DATA_DTP_REG_START                   0x01005160
+#define BCHP_QUEUE_22_DATA_DTP_REG_END                     0x0100516c
+#define BCHP_QUEUE_23_DATA_DTP_REG_START                   0x01005170
+#define BCHP_QUEUE_23_DATA_DTP_REG_END                     0x0100517c
+#define BCHP_QUEUE_24_DATA_DTP_REG_START                   0x01005180
+#define BCHP_QUEUE_24_DATA_DTP_REG_END                     0x0100518c
+#define BCHP_QUEUE_25_DATA_DTP_REG_START                   0x01005190
+#define BCHP_QUEUE_25_DATA_DTP_REG_END                     0x0100519c
+#define BCHP_QUEUE_26_DATA_DTP_REG_START                   0x010051a0
+#define BCHP_QUEUE_26_DATA_DTP_REG_END                     0x010051ac
+#define BCHP_QUEUE_27_DATA_DTP_REG_START                   0x010051b0
+#define BCHP_QUEUE_27_DATA_DTP_REG_END                     0x010051bc
+#define BCHP_QUEUE_28_DATA_DTP_REG_START                   0x010051c0
+#define BCHP_QUEUE_28_DATA_DTP_REG_END                     0x010051cc
+#define BCHP_QUEUE_29_DATA_DTP_REG_START                   0x010051d0
+#define BCHP_QUEUE_29_DATA_DTP_REG_END                     0x010051dc
+#define BCHP_QUEUE_30_DATA_DTP_REG_START                   0x010051e0
+#define BCHP_QUEUE_30_DATA_DTP_REG_END                     0x010051ec
+#define BCHP_QUEUE_31_DATA_DTP_REG_START                   0x010051f0
+#define BCHP_QUEUE_31_DATA_DTP_REG_END                     0x010051fc
+#define BCHP_QUEUE_32_DATA_DTP_REG_START                   0x01005200
+#define BCHP_QUEUE_32_DATA_DTP_REG_END                     0x0100520c
+#define BCHP_QUEUE_33_DATA_DTP_REG_START                   0x01005210
+#define BCHP_QUEUE_33_DATA_DTP_REG_END                     0x0100521c
+#define BCHP_QUEUE_34_DATA_DTP_REG_START                   0x01005220
+#define BCHP_QUEUE_34_DATA_DTP_REG_END                     0x0100522c
+#define BCHP_QUEUE_35_DATA_DTP_REG_START                   0x01005230
+#define BCHP_QUEUE_35_DATA_DTP_REG_END                     0x0100523c
+#define BCHP_QUEUE_36_DATA_DTP_REG_START                   0x01005240
+#define BCHP_QUEUE_36_DATA_DTP_REG_END                     0x0100524c
+#define BCHP_QUEUE_37_DATA_DTP_REG_START                   0x01005250
+#define BCHP_QUEUE_37_DATA_DTP_REG_END                     0x0100525c
+#define BCHP_QUEUE_38_DATA_DTP_REG_START                   0x01005260
+#define BCHP_QUEUE_38_DATA_DTP_REG_END                     0x0100526c
+#define BCHP_QUEUE_39_DATA_DTP_REG_START                   0x01005270
+#define BCHP_QUEUE_39_DATA_DTP_REG_END                     0x0100527c
+#define BCHP_QUEUE_40_DATA_DTP_REG_START                   0x01005280
+#define BCHP_QUEUE_40_DATA_DTP_REG_END                     0x0100528c
+#define BCHP_QUEUE_41_DATA_DTP_REG_START                   0x01005290
+#define BCHP_QUEUE_41_DATA_DTP_REG_END                     0x0100529c
+#define BCHP_QUEUE_42_DATA_DTP_REG_START                   0x010052a0
+#define BCHP_QUEUE_42_DATA_DTP_REG_END                     0x010052ac
+#define BCHP_QUEUE_43_DATA_DTP_REG_START                   0x010052b0
+#define BCHP_QUEUE_43_DATA_DTP_REG_END                     0x010052bc
+#define BCHP_QUEUE_44_DATA_DTP_REG_START                   0x010052c0
+#define BCHP_QUEUE_44_DATA_DTP_REG_END                     0x010052cc
+#define BCHP_QUEUE_45_DATA_DTP_REG_START                   0x010052d0
+#define BCHP_QUEUE_45_DATA_DTP_REG_END                     0x010052dc
+#define BCHP_QUEUE_46_DATA_DTP_REG_START                   0x010052e0
+#define BCHP_QUEUE_46_DATA_DTP_REG_END                     0x010052ec
+#define BCHP_QUEUE_47_DATA_DTP_REG_START                   0x010052f0
+#define BCHP_QUEUE_47_DATA_DTP_REG_END                     0x010052fc
+#define BCHP_QUEUE_48_DATA_DTP_REG_START                   0x01005300
+#define BCHP_QUEUE_48_DATA_DTP_REG_END                     0x0100530c
+#define BCHP_QUEUE_49_DATA_DTP_REG_START                   0x01005310
+#define BCHP_QUEUE_49_DATA_DTP_REG_END                     0x0100531c
+#define BCHP_QUEUE_50_DATA_DTP_REG_START                   0x01005320
+#define BCHP_QUEUE_50_DATA_DTP_REG_END                     0x0100532c
+#define BCHP_QUEUE_51_DATA_DTP_REG_START                   0x01005330
+#define BCHP_QUEUE_51_DATA_DTP_REG_END                     0x0100533c
+#define BCHP_QUEUE_52_DATA_DTP_REG_START                   0x01005340
+#define BCHP_QUEUE_52_DATA_DTP_REG_END                     0x0100534c
+#define BCHP_QUEUE_53_DATA_DTP_REG_START                   0x01005350
+#define BCHP_QUEUE_53_DATA_DTP_REG_END                     0x0100535c
+#define BCHP_QUEUE_54_DATA_DTP_REG_START                   0x01005360
+#define BCHP_QUEUE_54_DATA_DTP_REG_END                     0x0100536c
+#define BCHP_QUEUE_55_DATA_DTP_REG_START                   0x01005370
+#define BCHP_QUEUE_55_DATA_DTP_REG_END                     0x0100537c
+#define BCHP_QUEUE_56_DATA_DTP_REG_START                   0x01005380
+#define BCHP_QUEUE_56_DATA_DTP_REG_END                     0x0100538c
+#define BCHP_QUEUE_57_DATA_DTP_REG_START                   0x01005390
+#define BCHP_QUEUE_57_DATA_DTP_REG_END                     0x0100539c
+#define BCHP_QUEUE_58_DATA_DTP_REG_START                   0x010053a0
+#define BCHP_QUEUE_58_DATA_DTP_REG_END                     0x010053ac
+#define BCHP_QUEUE_59_DATA_DTP_REG_START                   0x010053b0
+#define BCHP_QUEUE_59_DATA_DTP_REG_END                     0x010053bc
+#define BCHP_QUEUE_60_DATA_DTP_REG_START                   0x010053c0
+#define BCHP_QUEUE_60_DATA_DTP_REG_END                     0x010053cc
+#define BCHP_QUEUE_61_DATA_DTP_REG_START                   0x010053d0
+#define BCHP_QUEUE_61_DATA_DTP_REG_END                     0x010053dc
+#define BCHP_QUEUE_62_DATA_DTP_REG_START                   0x010053e0
+#define BCHP_QUEUE_62_DATA_DTP_REG_END                     0x010053ec
+#define BCHP_QUEUE_63_DATA_DTP_REG_START                   0x010053f0
+#define BCHP_QUEUE_63_DATA_DTP_REG_END                     0x010053fc
+#define BCHP_OL_DQM_DTP_REG_START                          0x01006c00
+#define BCHP_OL_DQM_DTP_REG_END                            0x01006c30
+#define BCHP_OL_QUEUE_STATUS_DTP_REG_START                 0x01007400
+#define BCHP_OL_QUEUE_STATUS_DTP_REG_END                   0x0100747c
+#define BCHP_OL_QUEUE_0_CNTRL_DTP_REG_START                0x01008000
+#define BCHP_OL_QUEUE_0_CNTRL_DTP_REG_END                  0x0100801c
+#define BCHP_OL_QUEUE_1_CNTRL_DTP_REG_START                0x01008020
+#define BCHP_OL_QUEUE_1_CNTRL_DTP_REG_END                  0x0100803c
+#define BCHP_OL_QUEUE_2_CNTRL_DTP_REG_START                0x01008040
+#define BCHP_OL_QUEUE_2_CNTRL_DTP_REG_END                  0x0100805c
+#define BCHP_OL_QUEUE_3_CNTRL_DTP_REG_START                0x01008060
+#define BCHP_OL_QUEUE_3_CNTRL_DTP_REG_END                  0x0100807c
+#define BCHP_OL_QUEUE_4_CNTRL_DTP_REG_START                0x01008080
+#define BCHP_OL_QUEUE_4_CNTRL_DTP_REG_END                  0x0100809c
+#define BCHP_OL_QUEUE_5_CNTRL_DTP_REG_START                0x010080a0
+#define BCHP_OL_QUEUE_5_CNTRL_DTP_REG_END                  0x010080bc
+#define BCHP_OL_QUEUE_6_CNTRL_DTP_REG_START                0x010080c0
+#define BCHP_OL_QUEUE_6_CNTRL_DTP_REG_END                  0x010080dc
+#define BCHP_OL_QUEUE_7_CNTRL_DTP_REG_START                0x010080e0
+#define BCHP_OL_QUEUE_7_CNTRL_DTP_REG_END                  0x010080fc
+#define BCHP_OL_QUEUE_8_CNTRL_DTP_REG_START                0x01008100
+#define BCHP_OL_QUEUE_8_CNTRL_DTP_REG_END                  0x0100811c
+#define BCHP_OL_QUEUE_9_CNTRL_DTP_REG_START                0x01008120
+#define BCHP_OL_QUEUE_9_CNTRL_DTP_REG_END                  0x0100813c
+#define BCHP_OL_QUEUE_10_CNTRL_DTP_REG_START               0x01008140
+#define BCHP_OL_QUEUE_10_CNTRL_DTP_REG_END                 0x0100815c
+#define BCHP_OL_QUEUE_11_CNTRL_DTP_REG_START               0x01008160
+#define BCHP_OL_QUEUE_11_CNTRL_DTP_REG_END                 0x0100817c
+#define BCHP_OL_QUEUE_12_CNTRL_DTP_REG_START               0x01008180
+#define BCHP_OL_QUEUE_12_CNTRL_DTP_REG_END                 0x0100819c
+#define BCHP_OL_QUEUE_13_CNTRL_DTP_REG_START               0x010081a0
+#define BCHP_OL_QUEUE_13_CNTRL_DTP_REG_END                 0x010081bc
+#define BCHP_OL_QUEUE_14_CNTRL_DTP_REG_START               0x010081c0
+#define BCHP_OL_QUEUE_14_CNTRL_DTP_REG_END                 0x010081dc
+#define BCHP_OL_QUEUE_15_CNTRL_DTP_REG_START               0x010081e0
+#define BCHP_OL_QUEUE_15_CNTRL_DTP_REG_END                 0x010081fc
+#define BCHP_OL_QUEUE_16_CNTRL_DTP_REG_START               0x01008200
+#define BCHP_OL_QUEUE_16_CNTRL_DTP_REG_END                 0x0100821c
+#define BCHP_OL_QUEUE_17_CNTRL_DTP_REG_START               0x01008220
+#define BCHP_OL_QUEUE_17_CNTRL_DTP_REG_END                 0x0100823c
+#define BCHP_OL_QUEUE_18_CNTRL_DTP_REG_START               0x01008240
+#define BCHP_OL_QUEUE_18_CNTRL_DTP_REG_END                 0x0100825c
+#define BCHP_OL_QUEUE_19_CNTRL_DTP_REG_START               0x01008260
+#define BCHP_OL_QUEUE_19_CNTRL_DTP_REG_END                 0x0100827c
+#define BCHP_OL_QUEUE_20_CNTRL_DTP_REG_START               0x01008280
+#define BCHP_OL_QUEUE_20_CNTRL_DTP_REG_END                 0x0100829c
+#define BCHP_OL_QUEUE_21_CNTRL_DTP_REG_START               0x010082a0
+#define BCHP_OL_QUEUE_21_CNTRL_DTP_REG_END                 0x010082bc
+#define BCHP_OL_QUEUE_22_CNTRL_DTP_REG_START               0x010082c0
+#define BCHP_OL_QUEUE_22_CNTRL_DTP_REG_END                 0x010082dc
+#define BCHP_OL_QUEUE_23_CNTRL_DTP_REG_START               0x010082e0
+#define BCHP_OL_QUEUE_23_CNTRL_DTP_REG_END                 0x010082fc
+#define BCHP_OL_QUEUE_24_CNTRL_DTP_REG_START               0x01008300
+#define BCHP_OL_QUEUE_24_CNTRL_DTP_REG_END                 0x0100831c
+#define BCHP_OL_QUEUE_25_CNTRL_DTP_REG_START               0x01008320
+#define BCHP_OL_QUEUE_25_CNTRL_DTP_REG_END                 0x0100833c
+#define BCHP_OL_QUEUE_26_CNTRL_DTP_REG_START               0x01008340
+#define BCHP_OL_QUEUE_26_CNTRL_DTP_REG_END                 0x0100835c
+#define BCHP_OL_QUEUE_27_CNTRL_DTP_REG_START               0x01008360
+#define BCHP_OL_QUEUE_27_CNTRL_DTP_REG_END                 0x0100837c
+#define BCHP_OL_QUEUE_28_CNTRL_DTP_REG_START               0x01008380
+#define BCHP_OL_QUEUE_28_CNTRL_DTP_REG_END                 0x0100839c
+#define BCHP_OL_QUEUE_29_CNTRL_DTP_REG_START               0x010083a0
+#define BCHP_OL_QUEUE_29_CNTRL_DTP_REG_END                 0x010083bc
+#define BCHP_OL_QUEUE_30_CNTRL_DTP_REG_START               0x010083c0
+#define BCHP_OL_QUEUE_30_CNTRL_DTP_REG_END                 0x010083dc
+#define BCHP_OL_QUEUE_31_CNTRL_DTP_REG_START               0x010083e0
+#define BCHP_OL_QUEUE_31_CNTRL_DTP_REG_END                 0x010083fc
+#define BCHP_OL_QUEUE_0_DATA_DTP_REG_START                 0x01009000
+#define BCHP_OL_QUEUE_0_DATA_DTP_REG_END                   0x0100901c
+#define BCHP_OL_QUEUE_1_DATA_DTP_REG_START                 0x01009020
+#define BCHP_OL_QUEUE_1_DATA_DTP_REG_END                   0x0100903c
+#define BCHP_OL_QUEUE_2_DATA_DTP_REG_START                 0x01009040
+#define BCHP_OL_QUEUE_2_DATA_DTP_REG_END                   0x0100905c
+#define BCHP_OL_QUEUE_3_DATA_DTP_REG_START                 0x01009060
+#define BCHP_OL_QUEUE_3_DATA_DTP_REG_END                   0x0100907c
+#define BCHP_OL_QUEUE_4_DATA_DTP_REG_START                 0x01009080
+#define BCHP_OL_QUEUE_4_DATA_DTP_REG_END                   0x0100909c
+#define BCHP_OL_QUEUE_5_DATA_DTP_REG_START                 0x010090a0
+#define BCHP_OL_QUEUE_5_DATA_DTP_REG_END                   0x010090bc
+#define BCHP_OL_QUEUE_6_DATA_DTP_REG_START                 0x010090c0
+#define BCHP_OL_QUEUE_6_DATA_DTP_REG_END                   0x010090dc
+#define BCHP_OL_QUEUE_7_DATA_DTP_REG_START                 0x010090e0
+#define BCHP_OL_QUEUE_7_DATA_DTP_REG_END                   0x010090fc
+#define BCHP_OL_QUEUE_8_DATA_DTP_REG_START                 0x01009100
+#define BCHP_OL_QUEUE_8_DATA_DTP_REG_END                   0x0100911c
+#define BCHP_OL_QUEUE_9_DATA_DTP_REG_START                 0x01009120
+#define BCHP_OL_QUEUE_9_DATA_DTP_REG_END                   0x0100913c
+#define BCHP_OL_QUEUE_10_DATA_DTP_REG_START                0x01009140
+#define BCHP_OL_QUEUE_10_DATA_DTP_REG_END                  0x0100915c
+#define BCHP_OL_QUEUE_11_DATA_DTP_REG_START                0x01009160
+#define BCHP_OL_QUEUE_11_DATA_DTP_REG_END                  0x0100917c
+#define BCHP_OL_QUEUE_12_DATA_DTP_REG_START                0x01009180
+#define BCHP_OL_QUEUE_12_DATA_DTP_REG_END                  0x0100919c
+#define BCHP_OL_QUEUE_13_DATA_DTP_REG_START                0x010091a0
+#define BCHP_OL_QUEUE_13_DATA_DTP_REG_END                  0x010091bc
+#define BCHP_OL_QUEUE_14_DATA_DTP_REG_START                0x010091c0
+#define BCHP_OL_QUEUE_14_DATA_DTP_REG_END                  0x010091dc
+#define BCHP_OL_QUEUE_15_DATA_DTP_REG_START                0x010091e0
+#define BCHP_OL_QUEUE_15_DATA_DTP_REG_END                  0x010091fc
+#define BCHP_OL_QUEUE_16_DATA_DTP_REG_START                0x01009200
+#define BCHP_OL_QUEUE_16_DATA_DTP_REG_END                  0x0100921c
+#define BCHP_OL_QUEUE_17_DATA_DTP_REG_START                0x01009220
+#define BCHP_OL_QUEUE_17_DATA_DTP_REG_END                  0x0100923c
+#define BCHP_OL_QUEUE_18_DATA_DTP_REG_START                0x01009240
+#define BCHP_OL_QUEUE_18_DATA_DTP_REG_END                  0x0100925c
+#define BCHP_OL_QUEUE_19_DATA_DTP_REG_START                0x01009260
+#define BCHP_OL_QUEUE_19_DATA_DTP_REG_END                  0x0100927c
+#define BCHP_OL_QUEUE_20_DATA_DTP_REG_START                0x01009280
+#define BCHP_OL_QUEUE_20_DATA_DTP_REG_END                  0x0100929c
+#define BCHP_OL_QUEUE_21_DATA_DTP_REG_START                0x010092a0
+#define BCHP_OL_QUEUE_21_DATA_DTP_REG_END                  0x010092bc
+#define BCHP_OL_QUEUE_22_DATA_DTP_REG_START                0x010092c0
+#define BCHP_OL_QUEUE_22_DATA_DTP_REG_END                  0x010092dc
+#define BCHP_OL_QUEUE_23_DATA_DTP_REG_START                0x010092e0
+#define BCHP_OL_QUEUE_23_DATA_DTP_REG_END                  0x010092fc
+#define BCHP_OL_QUEUE_24_DATA_DTP_REG_START                0x01009300
+#define BCHP_OL_QUEUE_24_DATA_DTP_REG_END                  0x0100931c
+#define BCHP_OL_QUEUE_25_DATA_DTP_REG_START                0x01009320
+#define BCHP_OL_QUEUE_25_DATA_DTP_REG_END                  0x0100933c
+#define BCHP_OL_QUEUE_26_DATA_DTP_REG_START                0x01009340
+#define BCHP_OL_QUEUE_26_DATA_DTP_REG_END                  0x0100935c
+#define BCHP_OL_QUEUE_27_DATA_DTP_REG_START                0x01009360
+#define BCHP_OL_QUEUE_27_DATA_DTP_REG_END                  0x0100937c
+#define BCHP_OL_QUEUE_28_DATA_DTP_REG_START                0x01009380
+#define BCHP_OL_QUEUE_28_DATA_DTP_REG_END                  0x0100939c
+#define BCHP_OL_QUEUE_29_DATA_DTP_REG_START                0x010093a0
+#define BCHP_OL_QUEUE_29_DATA_DTP_REG_END                  0x010093bc
+#define BCHP_OL_QUEUE_30_DATA_DTP_REG_START                0x010093c0
+#define BCHP_OL_QUEUE_30_DATA_DTP_REG_END                  0x010093dc
+#define BCHP_OL_QUEUE_31_DATA_DTP_REG_START                0x010093e0
+#define BCHP_OL_QUEUE_31_DATA_DTP_REG_END                  0x010093fc
+#define BCHP_OL_QUEUE_MIB_DTP_REG_START                    0x0100a000
+#define BCHP_OL_QUEUE_MIB_DTP_REG_END                      0x0100a17c
+#define BCHP_QueueSharedMem_DTP_REG_START                  0x01040000
+#define BCHP_QueueSharedMem_DTP_REG_END                    0x0104bffc
+#define BCHP_PacketSharedMemory_DTP_REG_START              0x01080000
+#define BCHP_PacketSharedMemory_DTP_REG_END                0x01080ffc
+#define BCHP_DSRM_DTP_REG_START                            0x01100000
+#define BCHP_DSRM_DTP_REG_END                              0x011006ec
+#define BCHP_DSRM_MAX_RATE_DTP_REG_START                   0x01100700
+#define BCHP_DSRM_MAX_RATE_DTP_REG_END                     0x0110070c
+#define BCHP_DSRM_PEAK_RATE_DTP_REG_START                  0x01100710
+#define BCHP_DSRM_PEAK_RATE_DTP_REG_END                    0x0110071c
+#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_START              0x01100800
+#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_END                0x011008fc
+#define BCHP_DSRM_STATE_MEM_DTP_REG_START                  0x01101000
+#define BCHP_DSRM_STATE_MEM_DTP_REG_END                    0x011017fc
+#define BCHP_DSRM_STATS_MEM_DTP_REG_START                  0x01102000
+#define BCHP_DSRM_STATS_MEM_DTP_REG_END                    0x01102ffc
+#define BCHP_DSRM_TMOUT_MEM_DTP_REG_START                  0x01103000
+#define BCHP_DSRM_TMOUT_MEM_DTP_REG_END                    0x01103ffc
+#define BCHP_DSRM_TAG_MEM_DTP_REG_START                    0x01104000
+#define BCHP_DSRM_TAG_MEM_DTP_REG_END                      0x011057fc
+#define BCHP_DSRM_RLD_MEM_DTP_REG_START                    0x01106000
+#define BCHP_DSRM_RLD_MEM_DTP_REG_END                      0x01107fc4
+#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_START             0x01108000
+#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_END               0x011082fc
+#define BCHP_DSRM_CLSTR_MEM_DTP_REG_START                  0x01110000
+#define BCHP_DSRM_CLSTR_MEM_DTP_REG_END                    0x01117ffc
+#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_START             0x01180000
+#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_END               0x011afffc
+#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_START         0x011c0000
+#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_END           0x011efffc
+#define BCHP_BaseReserved_DFAP_REG_START                   0x01200000
+#define BCHP_BaseReserved_DFAP_REG_END                     0x01200000
+#define BCHP_Control_DFAP_REG_START                        0x01201000
+#define BCHP_Control_DFAP_REG_END                          0x012010fc
+#define BCHP_OutgoingMessageFIFO_DFAP_REG_START            0x01201100
+#define BCHP_OutgoingMessageFIFO_DFAP_REG_END              0x0120117c
+#define BCHP_IncomingMessageFIFO_DFAP_REG_START            0x01201200
+#define BCHP_IncomingMessageFIFO_DFAP_REG_END              0x0120127c
+#define BCHP_DMA0_DFAP_REG_START                           0x01201300
+#define BCHP_DMA0_DFAP_REG_END                             0x0120131c
+#define BCHP_DMA1_DFAP_REG_START                           0x01201320
+#define BCHP_DMA1_DFAP_REG_END                             0x0120133c
+#define BCHP_DMAHI0_DFAP_REG_START                         0x01201340
+#define BCHP_DMAHI0_DFAP_REG_END                           0x0120134c
+#define BCHP_DMAHI1_DFAP_REG_START                         0x01201350
+#define BCHP_DMAHI1_DFAP_REG_END                           0x0120135c
+#define BCHP_Token_DFAP_REG_START                          0x01201400
+#define BCHP_Token_DFAP_REG_END                            0x01201420
+#define BCHP_PerfPower_DFAP_REG_START                      0x01201600
+#define BCHP_PerfPower_DFAP_REG_END                        0x01201640
+#define BCHP_MessageID_DFAP_REG_START                      0x01201700
+#define BCHP_MessageID_DFAP_REG_END                        0x0120177c
+#define BCHP_HWCounters_DFAP_REG_START                     0x01201900
+#define BCHP_HWCounters_DFAP_REG_END                       0x01201944
+#define BCHP_DQM_0_31_DFAP_REG_START                       0x01201c00
+#define BCHP_DQM_0_31_DFAP_REG_END                         0x01201c48
+#define BCHP_DQM_32_63_DFAP_REG_START                      0x01201d00
+#define BCHP_DQM_32_63_DFAP_REG_END                        0x01201d48
+#define BCHP_QUEUE_TIMER_DFAP_REG_START                    0x01202000
+#define BCHP_QUEUE_TIMER_DFAP_REG_END                      0x012021fc
+#define BCHP_QUEUE_STATUS_0_31_DFAP_REG_START              0x01202800
+#define BCHP_QUEUE_STATUS_0_31_DFAP_REG_END                0x0120287c
+#define BCHP_QUEUE_STATUS_32_63_DFAP_REG_START             0x01202900
+#define BCHP_QUEUE_STATUS_32_63_DFAP_REG_END               0x0120297c
+#define BCHP_QUEUE_MIB_0_31_DFAP_REG_START                 0x01203000
+#define BCHP_QUEUE_MIB_0_31_DFAP_REG_END                   0x0120317c
+#define BCHP_QUEUE_MIB_32_63_DFAP_REG_START                0x01203200
+#define BCHP_QUEUE_MIB_32_63_DFAP_REG_END                  0x0120337c
+#define BCHP_QUEUE_0_CNTRL_DFAP_REG_START                  0x01204000
+#define BCHP_QUEUE_0_CNTRL_DFAP_REG_END                    0x0120400c
+#define BCHP_QUEUE_1_CNTRL_DFAP_REG_START                  0x01204010
+#define BCHP_QUEUE_1_CNTRL_DFAP_REG_END                    0x0120401c
+#define BCHP_QUEUE_2_CNTRL_DFAP_REG_START                  0x01204020
+#define BCHP_QUEUE_2_CNTRL_DFAP_REG_END                    0x0120402c
+#define BCHP_QUEUE_3_CNTRL_DFAP_REG_START                  0x01204030
+#define BCHP_QUEUE_3_CNTRL_DFAP_REG_END                    0x0120403c
+#define BCHP_QUEUE_4_CNTRL_DFAP_REG_START                  0x01204040
+#define BCHP_QUEUE_4_CNTRL_DFAP_REG_END                    0x0120404c
+#define BCHP_QUEUE_5_CNTRL_DFAP_REG_START                  0x01204050
+#define BCHP_QUEUE_5_CNTRL_DFAP_REG_END                    0x0120405c
+#define BCHP_QUEUE_6_CNTRL_DFAP_REG_START                  0x01204060
+#define BCHP_QUEUE_6_CNTRL_DFAP_REG_END                    0x0120406c
+#define BCHP_QUEUE_7_CNTRL_DFAP_REG_START                  0x01204070
+#define BCHP_QUEUE_7_CNTRL_DFAP_REG_END                    0x0120407c
+#define BCHP_QUEUE_8_CNTRL_DFAP_REG_START                  0x01204080
+#define BCHP_QUEUE_8_CNTRL_DFAP_REG_END                    0x0120408c
+#define BCHP_QUEUE_9_CNTRL_DFAP_REG_START                  0x01204090
+#define BCHP_QUEUE_9_CNTRL_DFAP_REG_END                    0x0120409c
+#define BCHP_QUEUE_10_CNTRL_DFAP_REG_START                 0x012040a0
+#define BCHP_QUEUE_10_CNTRL_DFAP_REG_END                   0x012040ac
+#define BCHP_QUEUE_11_CNTRL_DFAP_REG_START                 0x012040b0
+#define BCHP_QUEUE_11_CNTRL_DFAP_REG_END                   0x012040bc
+#define BCHP_QUEUE_12_CNTRL_DFAP_REG_START                 0x012040c0
+#define BCHP_QUEUE_12_CNTRL_DFAP_REG_END                   0x012040cc
+#define BCHP_QUEUE_13_CNTRL_DFAP_REG_START                 0x012040d0
+#define BCHP_QUEUE_13_CNTRL_DFAP_REG_END                   0x012040dc
+#define BCHP_QUEUE_14_CNTRL_DFAP_REG_START                 0x012040e0
+#define BCHP_QUEUE_14_CNTRL_DFAP_REG_END                   0x012040ec
+#define BCHP_QUEUE_15_CNTRL_DFAP_REG_START                 0x012040f0
+#define BCHP_QUEUE_15_CNTRL_DFAP_REG_END                   0x012040fc
+#define BCHP_QUEUE_16_CNTRL_DFAP_REG_START                 0x01204100
+#define BCHP_QUEUE_16_CNTRL_DFAP_REG_END                   0x0120410c
+#define BCHP_QUEUE_17_CNTRL_DFAP_REG_START                 0x01204110
+#define BCHP_QUEUE_17_CNTRL_DFAP_REG_END                   0x0120411c
+#define BCHP_QUEUE_18_CNTRL_DFAP_REG_START                 0x01204120
+#define BCHP_QUEUE_18_CNTRL_DFAP_REG_END                   0x0120412c
+#define BCHP_QUEUE_19_CNTRL_DFAP_REG_START                 0x01204130
+#define BCHP_QUEUE_19_CNTRL_DFAP_REG_END                   0x0120413c
+#define BCHP_QUEUE_20_CNTRL_DFAP_REG_START                 0x01204140
+#define BCHP_QUEUE_20_CNTRL_DFAP_REG_END                   0x0120414c
+#define BCHP_QUEUE_21_CNTRL_DFAP_REG_START                 0x01204150
+#define BCHP_QUEUE_21_CNTRL_DFAP_REG_END                   0x0120415c
+#define BCHP_QUEUE_22_CNTRL_DFAP_REG_START                 0x01204160
+#define BCHP_QUEUE_22_CNTRL_DFAP_REG_END                   0x0120416c
+#define BCHP_QUEUE_23_CNTRL_DFAP_REG_START                 0x01204170
+#define BCHP_QUEUE_23_CNTRL_DFAP_REG_END                   0x0120417c
+#define BCHP_QUEUE_24_CNTRL_DFAP_REG_START                 0x01204180
+#define BCHP_QUEUE_24_CNTRL_DFAP_REG_END                   0x0120418c
+#define BCHP_QUEUE_25_CNTRL_DFAP_REG_START                 0x01204190
+#define BCHP_QUEUE_25_CNTRL_DFAP_REG_END                   0x0120419c
+#define BCHP_QUEUE_26_CNTRL_DFAP_REG_START                 0x012041a0
+#define BCHP_QUEUE_26_CNTRL_DFAP_REG_END                   0x012041ac
+#define BCHP_QUEUE_27_CNTRL_DFAP_REG_START                 0x012041b0
+#define BCHP_QUEUE_27_CNTRL_DFAP_REG_END                   0x012041bc
+#define BCHP_QUEUE_28_CNTRL_DFAP_REG_START                 0x012041c0
+#define BCHP_QUEUE_28_CNTRL_DFAP_REG_END                   0x012041cc
+#define BCHP_QUEUE_29_CNTRL_DFAP_REG_START                 0x012041d0
+#define BCHP_QUEUE_29_CNTRL_DFAP_REG_END                   0x012041dc
+#define BCHP_QUEUE_30_CNTRL_DFAP_REG_START                 0x012041e0
+#define BCHP_QUEUE_30_CNTRL_DFAP_REG_END                   0x012041ec
+#define BCHP_QUEUE_31_CNTRL_DFAP_REG_START                 0x012041f0
+#define BCHP_QUEUE_31_CNTRL_DFAP_REG_END                   0x012041fc
+#define BCHP_QUEUE_32_CNTRL_DFAP_REG_START                 0x01204200
+#define BCHP_QUEUE_32_CNTRL_DFAP_REG_END                   0x0120420c
+#define BCHP_QUEUE_33_CNTRL_DFAP_REG_START                 0x01204210
+#define BCHP_QUEUE_33_CNTRL_DFAP_REG_END                   0x0120421c
+#define BCHP_QUEUE_34_CNTRL_DFAP_REG_START                 0x01204220
+#define BCHP_QUEUE_34_CNTRL_DFAP_REG_END                   0x0120422c
+#define BCHP_QUEUE_35_CNTRL_DFAP_REG_START                 0x01204230
+#define BCHP_QUEUE_35_CNTRL_DFAP_REG_END                   0x0120423c
+#define BCHP_QUEUE_36_CNTRL_DFAP_REG_START                 0x01204240
+#define BCHP_QUEUE_36_CNTRL_DFAP_REG_END                   0x0120424c
+#define BCHP_QUEUE_37_CNTRL_DFAP_REG_START                 0x01204250
+#define BCHP_QUEUE_37_CNTRL_DFAP_REG_END                   0x0120425c
+#define BCHP_QUEUE_38_CNTRL_DFAP_REG_START                 0x01204260
+#define BCHP_QUEUE_38_CNTRL_DFAP_REG_END                   0x0120426c
+#define BCHP_QUEUE_39_CNTRL_DFAP_REG_START                 0x01204270
+#define BCHP_QUEUE_39_CNTRL_DFAP_REG_END                   0x0120427c
+#define BCHP_QUEUE_40_CNTRL_DFAP_REG_START                 0x01204280
+#define BCHP_QUEUE_40_CNTRL_DFAP_REG_END                   0x0120428c
+#define BCHP_QUEUE_41_CNTRL_DFAP_REG_START                 0x01204290
+#define BCHP_QUEUE_41_CNTRL_DFAP_REG_END                   0x0120429c
+#define BCHP_QUEUE_42_CNTRL_DFAP_REG_START                 0x012042a0
+#define BCHP_QUEUE_42_CNTRL_DFAP_REG_END                   0x012042ac
+#define BCHP_QUEUE_43_CNTRL_DFAP_REG_START                 0x012042b0
+#define BCHP_QUEUE_43_CNTRL_DFAP_REG_END                   0x012042bc
+#define BCHP_QUEUE_44_CNTRL_DFAP_REG_START                 0x012042c0
+#define BCHP_QUEUE_44_CNTRL_DFAP_REG_END                   0x012042cc
+#define BCHP_QUEUE_45_CNTRL_DFAP_REG_START                 0x012042d0
+#define BCHP_QUEUE_45_CNTRL_DFAP_REG_END                   0x012042dc
+#define BCHP_QUEUE_46_CNTRL_DFAP_REG_START                 0x012042e0
+#define BCHP_QUEUE_46_CNTRL_DFAP_REG_END                   0x012042ec
+#define BCHP_QUEUE_47_CNTRL_DFAP_REG_START                 0x012042f0
+#define BCHP_QUEUE_47_CNTRL_DFAP_REG_END                   0x012042fc
+#define BCHP_QUEUE_48_CNTRL_DFAP_REG_START                 0x01204300
+#define BCHP_QUEUE_48_CNTRL_DFAP_REG_END                   0x0120430c
+#define BCHP_QUEUE_49_CNTRL_DFAP_REG_START                 0x01204310
+#define BCHP_QUEUE_49_CNTRL_DFAP_REG_END                   0x0120431c
+#define BCHP_QUEUE_50_CNTRL_DFAP_REG_START                 0x01204320
+#define BCHP_QUEUE_50_CNTRL_DFAP_REG_END                   0x0120432c
+#define BCHP_QUEUE_51_CNTRL_DFAP_REG_START                 0x01204330
+#define BCHP_QUEUE_51_CNTRL_DFAP_REG_END                   0x0120433c
+#define BCHP_QUEUE_52_CNTRL_DFAP_REG_START                 0x01204340
+#define BCHP_QUEUE_52_CNTRL_DFAP_REG_END                   0x0120434c
+#define BCHP_QUEUE_53_CNTRL_DFAP_REG_START                 0x01204350
+#define BCHP_QUEUE_53_CNTRL_DFAP_REG_END                   0x0120435c
+#define BCHP_QUEUE_54_CNTRL_DFAP_REG_START                 0x01204360
+#define BCHP_QUEUE_54_CNTRL_DFAP_REG_END                   0x0120436c
+#define BCHP_QUEUE_55_CNTRL_DFAP_REG_START                 0x01204370
+#define BCHP_QUEUE_55_CNTRL_DFAP_REG_END                   0x0120437c
+#define BCHP_QUEUE_56_CNTRL_DFAP_REG_START                 0x01204380
+#define BCHP_QUEUE_56_CNTRL_DFAP_REG_END                   0x0120438c
+#define BCHP_QUEUE_57_CNTRL_DFAP_REG_START                 0x01204390
+#define BCHP_QUEUE_57_CNTRL_DFAP_REG_END                   0x0120439c
+#define BCHP_QUEUE_58_CNTRL_DFAP_REG_START                 0x012043a0
+#define BCHP_QUEUE_58_CNTRL_DFAP_REG_END                   0x012043ac
+#define BCHP_QUEUE_59_CNTRL_DFAP_REG_START                 0x012043b0
+#define BCHP_QUEUE_59_CNTRL_DFAP_REG_END                   0x012043bc
+#define BCHP_QUEUE_60_CNTRL_DFAP_REG_START                 0x012043c0
+#define BCHP_QUEUE_60_CNTRL_DFAP_REG_END                   0x012043cc
+#define BCHP_QUEUE_61_CNTRL_DFAP_REG_START                 0x012043d0
+#define BCHP_QUEUE_61_CNTRL_DFAP_REG_END                   0x012043dc
+#define BCHP_QUEUE_62_CNTRL_DFAP_REG_START                 0x012043e0
+#define BCHP_QUEUE_62_CNTRL_DFAP_REG_END                   0x012043ec
+#define BCHP_QUEUE_63_CNTRL_DFAP_REG_START                 0x012043f0
+#define BCHP_QUEUE_63_CNTRL_DFAP_REG_END                   0x012043fc
+#define BCHP_QUEUE_0_DATA_DFAP_REG_START                   0x01205000
+#define BCHP_QUEUE_0_DATA_DFAP_REG_END                     0x0120500c
+#define BCHP_QUEUE_1_DATA_DFAP_REG_START                   0x01205010
+#define BCHP_QUEUE_1_DATA_DFAP_REG_END                     0x0120501c
+#define BCHP_QUEUE_2_DATA_DFAP_REG_START                   0x01205020
+#define BCHP_QUEUE_2_DATA_DFAP_REG_END                     0x0120502c
+#define BCHP_QUEUE_3_DATA_DFAP_REG_START                   0x01205030
+#define BCHP_QUEUE_3_DATA_DFAP_REG_END                     0x0120503c
+#define BCHP_QUEUE_4_DATA_DFAP_REG_START                   0x01205040
+#define BCHP_QUEUE_4_DATA_DFAP_REG_END                     0x0120504c
+#define BCHP_QUEUE_5_DATA_DFAP_REG_START                   0x01205050
+#define BCHP_QUEUE_5_DATA_DFAP_REG_END                     0x0120505c
+#define BCHP_QUEUE_6_DATA_DFAP_REG_START                   0x01205060
+#define BCHP_QUEUE_6_DATA_DFAP_REG_END                     0x0120506c
+#define BCHP_QUEUE_7_DATA_DFAP_REG_START                   0x01205070
+#define BCHP_QUEUE_7_DATA_DFAP_REG_END                     0x0120507c
+#define BCHP_QUEUE_8_DATA_DFAP_REG_START                   0x01205080
+#define BCHP_QUEUE_8_DATA_DFAP_REG_END                     0x0120508c
+#define BCHP_QUEUE_9_DATA_DFAP_REG_START                   0x01205090
+#define BCHP_QUEUE_9_DATA_DFAP_REG_END                     0x0120509c
+#define BCHP_QUEUE_10_DATA_DFAP_REG_START                  0x012050a0
+#define BCHP_QUEUE_10_DATA_DFAP_REG_END                    0x012050ac
+#define BCHP_QUEUE_11_DATA_DFAP_REG_START                  0x012050b0
+#define BCHP_QUEUE_11_DATA_DFAP_REG_END                    0x012050bc
+#define BCHP_QUEUE_12_DATA_DFAP_REG_START                  0x012050c0
+#define BCHP_QUEUE_12_DATA_DFAP_REG_END                    0x012050cc
+#define BCHP_QUEUE_13_DATA_DFAP_REG_START                  0x012050d0
+#define BCHP_QUEUE_13_DATA_DFAP_REG_END                    0x012050dc
+#define BCHP_QUEUE_14_DATA_DFAP_REG_START                  0x012050e0
+#define BCHP_QUEUE_14_DATA_DFAP_REG_END                    0x012050ec
+#define BCHP_QUEUE_15_DATA_DFAP_REG_START                  0x012050f0
+#define BCHP_QUEUE_15_DATA_DFAP_REG_END                    0x012050fc
+#define BCHP_QUEUE_16_DATA_DFAP_REG_START                  0x01205100
+#define BCHP_QUEUE_16_DATA_DFAP_REG_END                    0x0120510c
+#define BCHP_QUEUE_17_DATA_DFAP_REG_START                  0x01205110
+#define BCHP_QUEUE_17_DATA_DFAP_REG_END                    0x0120511c
+#define BCHP_QUEUE_18_DATA_DFAP_REG_START                  0x01205120
+#define BCHP_QUEUE_18_DATA_DFAP_REG_END                    0x0120512c
+#define BCHP_QUEUE_19_DATA_DFAP_REG_START                  0x01205130
+#define BCHP_QUEUE_19_DATA_DFAP_REG_END                    0x0120513c
+#define BCHP_QUEUE_20_DATA_DFAP_REG_START                  0x01205140
+#define BCHP_QUEUE_20_DATA_DFAP_REG_END                    0x0120514c
+#define BCHP_QUEUE_21_DATA_DFAP_REG_START                  0x01205150
+#define BCHP_QUEUE_21_DATA_DFAP_REG_END                    0x0120515c
+#define BCHP_QUEUE_22_DATA_DFAP_REG_START                  0x01205160
+#define BCHP_QUEUE_22_DATA_DFAP_REG_END                    0x0120516c
+#define BCHP_QUEUE_23_DATA_DFAP_REG_START                  0x01205170
+#define BCHP_QUEUE_23_DATA_DFAP_REG_END                    0x0120517c
+#define BCHP_QUEUE_24_DATA_DFAP_REG_START                  0x01205180
+#define BCHP_QUEUE_24_DATA_DFAP_REG_END                    0x0120518c
+#define BCHP_QUEUE_25_DATA_DFAP_REG_START                  0x01205190
+#define BCHP_QUEUE_25_DATA_DFAP_REG_END                    0x0120519c
+#define BCHP_QUEUE_26_DATA_DFAP_REG_START                  0x012051a0
+#define BCHP_QUEUE_26_DATA_DFAP_REG_END                    0x012051ac
+#define BCHP_QUEUE_27_DATA_DFAP_REG_START                  0x012051b0
+#define BCHP_QUEUE_27_DATA_DFAP_REG_END                    0x012051bc
+#define BCHP_QUEUE_28_DATA_DFAP_REG_START                  0x012051c0
+#define BCHP_QUEUE_28_DATA_DFAP_REG_END                    0x012051cc
+#define BCHP_QUEUE_29_DATA_DFAP_REG_START                  0x012051d0
+#define BCHP_QUEUE_29_DATA_DFAP_REG_END                    0x012051dc
+#define BCHP_QUEUE_30_DATA_DFAP_REG_START                  0x012051e0
+#define BCHP_QUEUE_30_DATA_DFAP_REG_END                    0x012051ec
+#define BCHP_QUEUE_31_DATA_DFAP_REG_START                  0x012051f0
+#define BCHP_QUEUE_31_DATA_DFAP_REG_END                    0x012051fc
+#define BCHP_QUEUE_32_DATA_DFAP_REG_START                  0x01205200
+#define BCHP_QUEUE_32_DATA_DFAP_REG_END                    0x0120520c
+#define BCHP_QUEUE_33_DATA_DFAP_REG_START                  0x01205210
+#define BCHP_QUEUE_33_DATA_DFAP_REG_END                    0x0120521c
+#define BCHP_QUEUE_34_DATA_DFAP_REG_START                  0x01205220
+#define BCHP_QUEUE_34_DATA_DFAP_REG_END                    0x0120522c
+#define BCHP_QUEUE_35_DATA_DFAP_REG_START                  0x01205230
+#define BCHP_QUEUE_35_DATA_DFAP_REG_END                    0x0120523c
+#define BCHP_QUEUE_36_DATA_DFAP_REG_START                  0x01205240
+#define BCHP_QUEUE_36_DATA_DFAP_REG_END                    0x0120524c
+#define BCHP_QUEUE_37_DATA_DFAP_REG_START                  0x01205250
+#define BCHP_QUEUE_37_DATA_DFAP_REG_END                    0x0120525c
+#define BCHP_QUEUE_38_DATA_DFAP_REG_START                  0x01205260
+#define BCHP_QUEUE_38_DATA_DFAP_REG_END                    0x0120526c
+#define BCHP_QUEUE_39_DATA_DFAP_REG_START                  0x01205270
+#define BCHP_QUEUE_39_DATA_DFAP_REG_END                    0x0120527c
+#define BCHP_QUEUE_40_DATA_DFAP_REG_START                  0x01205280
+#define BCHP_QUEUE_40_DATA_DFAP_REG_END                    0x0120528c
+#define BCHP_QUEUE_41_DATA_DFAP_REG_START                  0x01205290
+#define BCHP_QUEUE_41_DATA_DFAP_REG_END                    0x0120529c
+#define BCHP_QUEUE_42_DATA_DFAP_REG_START                  0x012052a0
+#define BCHP_QUEUE_42_DATA_DFAP_REG_END                    0x012052ac
+#define BCHP_QUEUE_43_DATA_DFAP_REG_START                  0x012052b0
+#define BCHP_QUEUE_43_DATA_DFAP_REG_END                    0x012052bc
+#define BCHP_QUEUE_44_DATA_DFAP_REG_START                  0x012052c0
+#define BCHP_QUEUE_44_DATA_DFAP_REG_END                    0x012052cc
+#define BCHP_QUEUE_45_DATA_DFAP_REG_START                  0x012052d0
+#define BCHP_QUEUE_45_DATA_DFAP_REG_END                    0x012052dc
+#define BCHP_QUEUE_46_DATA_DFAP_REG_START                  0x012052e0
+#define BCHP_QUEUE_46_DATA_DFAP_REG_END                    0x012052ec
+#define BCHP_QUEUE_47_DATA_DFAP_REG_START                  0x012052f0
+#define BCHP_QUEUE_47_DATA_DFAP_REG_END                    0x012052fc
+#define BCHP_QUEUE_48_DATA_DFAP_REG_START                  0x01205300
+#define BCHP_QUEUE_48_DATA_DFAP_REG_END                    0x0120530c
+#define BCHP_QUEUE_49_DATA_DFAP_REG_START                  0x01205310
+#define BCHP_QUEUE_49_DATA_DFAP_REG_END                    0x0120531c
+#define BCHP_QUEUE_50_DATA_DFAP_REG_START                  0x01205320
+#define BCHP_QUEUE_50_DATA_DFAP_REG_END                    0x0120532c
+#define BCHP_QUEUE_51_DATA_DFAP_REG_START                  0x01205330
+#define BCHP_QUEUE_51_DATA_DFAP_REG_END                    0x0120533c
+#define BCHP_QUEUE_52_DATA_DFAP_REG_START                  0x01205340
+#define BCHP_QUEUE_52_DATA_DFAP_REG_END                    0x0120534c
+#define BCHP_QUEUE_53_DATA_DFAP_REG_START                  0x01205350
+#define BCHP_QUEUE_53_DATA_DFAP_REG_END                    0x0120535c
+#define BCHP_QUEUE_54_DATA_DFAP_REG_START                  0x01205360
+#define BCHP_QUEUE_54_DATA_DFAP_REG_END                    0x0120536c
+#define BCHP_QUEUE_55_DATA_DFAP_REG_START                  0x01205370
+#define BCHP_QUEUE_55_DATA_DFAP_REG_END                    0x0120537c
+#define BCHP_QUEUE_56_DATA_DFAP_REG_START                  0x01205380
+#define BCHP_QUEUE_56_DATA_DFAP_REG_END                    0x0120538c
+#define BCHP_QUEUE_57_DATA_DFAP_REG_START                  0x01205390
+#define BCHP_QUEUE_57_DATA_DFAP_REG_END                    0x0120539c
+#define BCHP_QUEUE_58_DATA_DFAP_REG_START                  0x012053a0
+#define BCHP_QUEUE_58_DATA_DFAP_REG_END                    0x012053ac
+#define BCHP_QUEUE_59_DATA_DFAP_REG_START                  0x012053b0
+#define BCHP_QUEUE_59_DATA_DFAP_REG_END                    0x012053bc
+#define BCHP_QUEUE_60_DATA_DFAP_REG_START                  0x012053c0
+#define BCHP_QUEUE_60_DATA_DFAP_REG_END                    0x012053cc
+#define BCHP_QUEUE_61_DATA_DFAP_REG_START                  0x012053d0
+#define BCHP_QUEUE_61_DATA_DFAP_REG_END                    0x012053dc
+#define BCHP_QUEUE_62_DATA_DFAP_REG_START                  0x012053e0
+#define BCHP_QUEUE_62_DATA_DFAP_REG_END                    0x012053ec
+#define BCHP_QUEUE_63_DATA_DFAP_REG_START                  0x012053f0
+#define BCHP_QUEUE_63_DATA_DFAP_REG_END                    0x012053fc
+#define BCHP_OL_DQM_DFAP_REG_START                         0x01206c00
+#define BCHP_OL_DQM_DFAP_REG_END                           0x01206c30
+#define BCHP_OL_QUEUE_STATUS_DFAP_REG_START                0x01207400
+#define BCHP_OL_QUEUE_STATUS_DFAP_REG_END                  0x0120747c
+#define BCHP_OL_QUEUE_0_CNTRL_DFAP_REG_START               0x01208000
+#define BCHP_OL_QUEUE_0_CNTRL_DFAP_REG_END                 0x0120801c
+#define BCHP_OL_QUEUE_1_CNTRL_DFAP_REG_START               0x01208020
+#define BCHP_OL_QUEUE_1_CNTRL_DFAP_REG_END                 0x0120803c
+#define BCHP_OL_QUEUE_2_CNTRL_DFAP_REG_START               0x01208040
+#define BCHP_OL_QUEUE_2_CNTRL_DFAP_REG_END                 0x0120805c
+#define BCHP_OL_QUEUE_3_CNTRL_DFAP_REG_START               0x01208060
+#define BCHP_OL_QUEUE_3_CNTRL_DFAP_REG_END                 0x0120807c
+#define BCHP_OL_QUEUE_4_CNTRL_DFAP_REG_START               0x01208080
+#define BCHP_OL_QUEUE_4_CNTRL_DFAP_REG_END                 0x0120809c
+#define BCHP_OL_QUEUE_5_CNTRL_DFAP_REG_START               0x012080a0
+#define BCHP_OL_QUEUE_5_CNTRL_DFAP_REG_END                 0x012080bc
+#define BCHP_OL_QUEUE_6_CNTRL_DFAP_REG_START               0x012080c0
+#define BCHP_OL_QUEUE_6_CNTRL_DFAP_REG_END                 0x012080dc
+#define BCHP_OL_QUEUE_7_CNTRL_DFAP_REG_START               0x012080e0
+#define BCHP_OL_QUEUE_7_CNTRL_DFAP_REG_END                 0x012080fc
+#define BCHP_OL_QUEUE_8_CNTRL_DFAP_REG_START               0x01208100
+#define BCHP_OL_QUEUE_8_CNTRL_DFAP_REG_END                 0x0120811c
+#define BCHP_OL_QUEUE_9_CNTRL_DFAP_REG_START               0x01208120
+#define BCHP_OL_QUEUE_9_CNTRL_DFAP_REG_END                 0x0120813c
+#define BCHP_OL_QUEUE_10_CNTRL_DFAP_REG_START              0x01208140
+#define BCHP_OL_QUEUE_10_CNTRL_DFAP_REG_END                0x0120815c
+#define BCHP_OL_QUEUE_11_CNTRL_DFAP_REG_START              0x01208160
+#define BCHP_OL_QUEUE_11_CNTRL_DFAP_REG_END                0x0120817c
+#define BCHP_OL_QUEUE_12_CNTRL_DFAP_REG_START              0x01208180
+#define BCHP_OL_QUEUE_12_CNTRL_DFAP_REG_END                0x0120819c
+#define BCHP_OL_QUEUE_13_CNTRL_DFAP_REG_START              0x012081a0
+#define BCHP_OL_QUEUE_13_CNTRL_DFAP_REG_END                0x012081bc
+#define BCHP_OL_QUEUE_14_CNTRL_DFAP_REG_START              0x012081c0
+#define BCHP_OL_QUEUE_14_CNTRL_DFAP_REG_END                0x012081dc
+#define BCHP_OL_QUEUE_15_CNTRL_DFAP_REG_START              0x012081e0
+#define BCHP_OL_QUEUE_15_CNTRL_DFAP_REG_END                0x012081fc
+#define BCHP_OL_QUEUE_16_CNTRL_DFAP_REG_START              0x01208200
+#define BCHP_OL_QUEUE_16_CNTRL_DFAP_REG_END                0x0120821c
+#define BCHP_OL_QUEUE_17_CNTRL_DFAP_REG_START              0x01208220
+#define BCHP_OL_QUEUE_17_CNTRL_DFAP_REG_END                0x0120823c
+#define BCHP_OL_QUEUE_18_CNTRL_DFAP_REG_START              0x01208240
+#define BCHP_OL_QUEUE_18_CNTRL_DFAP_REG_END                0x0120825c
+#define BCHP_OL_QUEUE_19_CNTRL_DFAP_REG_START              0x01208260
+#define BCHP_OL_QUEUE_19_CNTRL_DFAP_REG_END                0x0120827c
+#define BCHP_OL_QUEUE_20_CNTRL_DFAP_REG_START              0x01208280
+#define BCHP_OL_QUEUE_20_CNTRL_DFAP_REG_END                0x0120829c
+#define BCHP_OL_QUEUE_21_CNTRL_DFAP_REG_START              0x012082a0
+#define BCHP_OL_QUEUE_21_CNTRL_DFAP_REG_END                0x012082bc
+#define BCHP_OL_QUEUE_22_CNTRL_DFAP_REG_START              0x012082c0
+#define BCHP_OL_QUEUE_22_CNTRL_DFAP_REG_END                0x012082dc
+#define BCHP_OL_QUEUE_23_CNTRL_DFAP_REG_START              0x012082e0
+#define BCHP_OL_QUEUE_23_CNTRL_DFAP_REG_END                0x012082fc
+#define BCHP_OL_QUEUE_24_CNTRL_DFAP_REG_START              0x01208300
+#define BCHP_OL_QUEUE_24_CNTRL_DFAP_REG_END                0x0120831c
+#define BCHP_OL_QUEUE_25_CNTRL_DFAP_REG_START              0x01208320
+#define BCHP_OL_QUEUE_25_CNTRL_DFAP_REG_END                0x0120833c
+#define BCHP_OL_QUEUE_26_CNTRL_DFAP_REG_START              0x01208340
+#define BCHP_OL_QUEUE_26_CNTRL_DFAP_REG_END                0x0120835c
+#define BCHP_OL_QUEUE_27_CNTRL_DFAP_REG_START              0x01208360
+#define BCHP_OL_QUEUE_27_CNTRL_DFAP_REG_END                0x0120837c
+#define BCHP_OL_QUEUE_28_CNTRL_DFAP_REG_START              0x01208380
+#define BCHP_OL_QUEUE_28_CNTRL_DFAP_REG_END                0x0120839c
+#define BCHP_OL_QUEUE_29_CNTRL_DFAP_REG_START              0x012083a0
+#define BCHP_OL_QUEUE_29_CNTRL_DFAP_REG_END                0x012083bc
+#define BCHP_OL_QUEUE_30_CNTRL_DFAP_REG_START              0x012083c0
+#define BCHP_OL_QUEUE_30_CNTRL_DFAP_REG_END                0x012083dc
+#define BCHP_OL_QUEUE_31_CNTRL_DFAP_REG_START              0x012083e0
+#define BCHP_OL_QUEUE_31_CNTRL_DFAP_REG_END                0x012083fc
+#define BCHP_OL_QUEUE_0_DATA_DFAP_REG_START                0x01209000
+#define BCHP_OL_QUEUE_0_DATA_DFAP_REG_END                  0x0120901c
+#define BCHP_OL_QUEUE_1_DATA_DFAP_REG_START                0x01209020
+#define BCHP_OL_QUEUE_1_DATA_DFAP_REG_END                  0x0120903c
+#define BCHP_OL_QUEUE_2_DATA_DFAP_REG_START                0x01209040
+#define BCHP_OL_QUEUE_2_DATA_DFAP_REG_END                  0x0120905c
+#define BCHP_OL_QUEUE_3_DATA_DFAP_REG_START                0x01209060
+#define BCHP_OL_QUEUE_3_DATA_DFAP_REG_END                  0x0120907c
+#define BCHP_OL_QUEUE_4_DATA_DFAP_REG_START                0x01209080
+#define BCHP_OL_QUEUE_4_DATA_DFAP_REG_END                  0x0120909c
+#define BCHP_OL_QUEUE_5_DATA_DFAP_REG_START                0x012090a0
+#define BCHP_OL_QUEUE_5_DATA_DFAP_REG_END                  0x012090bc
+#define BCHP_OL_QUEUE_6_DATA_DFAP_REG_START                0x012090c0
+#define BCHP_OL_QUEUE_6_DATA_DFAP_REG_END                  0x012090dc
+#define BCHP_OL_QUEUE_7_DATA_DFAP_REG_START                0x012090e0
+#define BCHP_OL_QUEUE_7_DATA_DFAP_REG_END                  0x012090fc
+#define BCHP_OL_QUEUE_8_DATA_DFAP_REG_START                0x01209100
+#define BCHP_OL_QUEUE_8_DATA_DFAP_REG_END                  0x0120911c
+#define BCHP_OL_QUEUE_9_DATA_DFAP_REG_START                0x01209120
+#define BCHP_OL_QUEUE_9_DATA_DFAP_REG_END                  0x0120913c
+#define BCHP_OL_QUEUE_10_DATA_DFAP_REG_START               0x01209140
+#define BCHP_OL_QUEUE_10_DATA_DFAP_REG_END                 0x0120915c
+#define BCHP_OL_QUEUE_11_DATA_DFAP_REG_START               0x01209160
+#define BCHP_OL_QUEUE_11_DATA_DFAP_REG_END                 0x0120917c
+#define BCHP_OL_QUEUE_12_DATA_DFAP_REG_START               0x01209180
+#define BCHP_OL_QUEUE_12_DATA_DFAP_REG_END                 0x0120919c
+#define BCHP_OL_QUEUE_13_DATA_DFAP_REG_START               0x012091a0
+#define BCHP_OL_QUEUE_13_DATA_DFAP_REG_END                 0x012091bc
+#define BCHP_OL_QUEUE_14_DATA_DFAP_REG_START               0x012091c0
+#define BCHP_OL_QUEUE_14_DATA_DFAP_REG_END                 0x012091dc
+#define BCHP_OL_QUEUE_15_DATA_DFAP_REG_START               0x012091e0
+#define BCHP_OL_QUEUE_15_DATA_DFAP_REG_END                 0x012091fc
+#define BCHP_OL_QUEUE_16_DATA_DFAP_REG_START               0x01209200
+#define BCHP_OL_QUEUE_16_DATA_DFAP_REG_END                 0x0120921c
+#define BCHP_OL_QUEUE_17_DATA_DFAP_REG_START               0x01209220
+#define BCHP_OL_QUEUE_17_DATA_DFAP_REG_END                 0x0120923c
+#define BCHP_OL_QUEUE_18_DATA_DFAP_REG_START               0x01209240
+#define BCHP_OL_QUEUE_18_DATA_DFAP_REG_END                 0x0120925c
+#define BCHP_OL_QUEUE_19_DATA_DFAP_REG_START               0x01209260
+#define BCHP_OL_QUEUE_19_DATA_DFAP_REG_END                 0x0120927c
+#define BCHP_OL_QUEUE_20_DATA_DFAP_REG_START               0x01209280
+#define BCHP_OL_QUEUE_20_DATA_DFAP_REG_END                 0x0120929c
+#define BCHP_OL_QUEUE_21_DATA_DFAP_REG_START               0x012092a0
+#define BCHP_OL_QUEUE_21_DATA_DFAP_REG_END                 0x012092bc
+#define BCHP_OL_QUEUE_22_DATA_DFAP_REG_START               0x012092c0
+#define BCHP_OL_QUEUE_22_DATA_DFAP_REG_END                 0x012092dc
+#define BCHP_OL_QUEUE_23_DATA_DFAP_REG_START               0x012092e0
+#define BCHP_OL_QUEUE_23_DATA_DFAP_REG_END                 0x012092fc
+#define BCHP_OL_QUEUE_24_DATA_DFAP_REG_START               0x01209300
+#define BCHP_OL_QUEUE_24_DATA_DFAP_REG_END                 0x0120931c
+#define BCHP_OL_QUEUE_25_DATA_DFAP_REG_START               0x01209320
+#define BCHP_OL_QUEUE_25_DATA_DFAP_REG_END                 0x0120933c
+#define BCHP_OL_QUEUE_26_DATA_DFAP_REG_START               0x01209340
+#define BCHP_OL_QUEUE_26_DATA_DFAP_REG_END                 0x0120935c
+#define BCHP_OL_QUEUE_27_DATA_DFAP_REG_START               0x01209360
+#define BCHP_OL_QUEUE_27_DATA_DFAP_REG_END                 0x0120937c
+#define BCHP_OL_QUEUE_28_DATA_DFAP_REG_START               0x01209380
+#define BCHP_OL_QUEUE_28_DATA_DFAP_REG_END                 0x0120939c
+#define BCHP_OL_QUEUE_29_DATA_DFAP_REG_START               0x012093a0
+#define BCHP_OL_QUEUE_29_DATA_DFAP_REG_END                 0x012093bc
+#define BCHP_OL_QUEUE_30_DATA_DFAP_REG_START               0x012093c0
+#define BCHP_OL_QUEUE_30_DATA_DFAP_REG_END                 0x012093dc
+#define BCHP_OL_QUEUE_31_DATA_DFAP_REG_START               0x012093e0
+#define BCHP_OL_QUEUE_31_DATA_DFAP_REG_END                 0x012093fc
+#define BCHP_OL_QUEUE_MIB_DFAP_REG_START                   0x0120a000
+#define BCHP_OL_QUEUE_MIB_DFAP_REG_END                     0x0120a17c
+#define BCHP_QueueSharedMem_DFAP_REG_START                 0x01240000
+#define BCHP_QueueSharedMem_DFAP_REG_END                   0x0124bffc
+#define BCHP_Memory_DFAP_REG_START                         0x01280000
+#define BCHP_Memory_DFAP_REG_END                           0x01287ffc
+#define BCHP_DPE_BASIC_DFAP_REG_START                      0x01300000
+#define BCHP_DPE_BASIC_DFAP_REG_END                        0x01300094
+#define BCHP_DPE_MPEG_DFAP_REG_START                       0x01300200
+#define BCHP_DPE_MPEG_DFAP_REG_END                         0x0130034c
+#define BCHP_DPE_HW_DFAP_REG_START                         0x01300400
+#define BCHP_DPE_HW_DFAP_REG_END                           0x0130169c
+#define BCHP_DPE_EXT_DROP_DFAP_REG_START                   0x01305000
+#define BCHP_DPE_EXT_DROP_DFAP_REG_END                     0x01305200
+#define BCHP_NATC_REG_DFAP_REG_START                       0x01306000
+#define BCHP_NATC_REG_DFAP_REG_END                         0x01306164
+#define BCHP_NATC_SMEM_DFAP_REG_START                      0x01307000
+#define BCHP_NATC_SMEM_DFAP_REG_END                        0x01307ffc
+#define BCHP_NATC_MEM_DFAP_REG_START                       0x01308000
+#define BCHP_NATC_MEM_DFAP_REG_END                         0x0130fffc
+#define BCHP_FAP_PT_MEM_DFAP_REG_START                     0x01310000
+#define BCHP_FAP_PT_MEM_DFAP_REG_END                       0x01317ffc
+#define BCHP_FPM_PT_CTRL_DFAP_REG_START                    0x01320000
+#define BCHP_FPM_PT_CTRL_DFAP_REG_END                      0x0132014c
+#define BCHP_FPM_PT_POOL_DFAP_REG_START                    0x01320200
+#define BCHP_FPM_PT_POOL_DFAP_REG_END                      0x01320224
+#define BCHP_FPM_PT_SEARCH_DFAP_REG_START                  0x01324000
+#define BCHP_FPM_PT_SEARCH_DFAP_REG_END                    0x013248b8
+#define BCHP_FPM_PT_MULTI_DFAP_REG_START                   0x01330000
+#define BCHP_FPM_PT_MULTI_DFAP_REG_END                     0x01333ff8
+#define BCHP_FFE_N_0_DFAP_REG_START                        0x01380000
+#define BCHP_FFE_N_0_DFAP_REG_END                          0x013803fc
+#define BCHP_FFE_P_0_DFAP_REG_START                        0x01381000
+#define BCHP_FFE_P_0_DFAP_REG_END                          0x013817fc
+#define BCHP_FFE_I_0_DFAP_REG_START                        0x01384000
+#define BCHP_FFE_I_0_DFAP_REG_END                          0x01387ffc
+#define BCHP_FFE_N_1_DFAP_REG_START                        0x01390000
+#define BCHP_FFE_N_1_DFAP_REG_END                          0x013903fc
+#define BCHP_FFE_P_1_DFAP_REG_START                        0x01391000
+#define BCHP_FFE_P_1_DFAP_REG_END                          0x013917fc
+#define BCHP_FFE_I_1_DFAP_REG_START                        0x01394000
+#define BCHP_FFE_I_1_DFAP_REG_END                          0x01397ffc
+#define BCHP_FFE_N_2_DFAP_REG_START                        0x013a0000
+#define BCHP_FFE_N_2_DFAP_REG_END                          0x013a03fc
+#define BCHP_FFE_P_2_DFAP_REG_START                        0x013a1000
+#define BCHP_FFE_P_2_DFAP_REG_END                          0x013a17fc
+#define BCHP_FFE_I_2_DFAP_REG_START                        0x013a4000
+#define BCHP_FFE_I_2_DFAP_REG_END                          0x013a7ffc
+#define BCHP_FFE_N_3_DFAP_REG_START                        0x013b0000
+#define BCHP_FFE_N_3_DFAP_REG_END                          0x013b03fc
+#define BCHP_FFE_P_3_DFAP_REG_START                        0x013b1000
+#define BCHP_FFE_P_3_DFAP_REG_END                          0x013b17fc
+#define BCHP_FFE_I_3_DFAP_REG_START                        0x013b4000
+#define BCHP_FFE_I_3_DFAP_REG_END                          0x013b7ffc
+#define BCHP_FFE_N_4_DFAP_REG_START                        0x013c0000
+#define BCHP_FFE_N_4_DFAP_REG_END                          0x013c03fc
+#define BCHP_FFE_P_4_DFAP_REG_START                        0x013c1000
+#define BCHP_FFE_P_4_DFAP_REG_END                          0x013c17fc
+#define BCHP_FFE_I_4_DFAP_REG_START                        0x013c4000
+#define BCHP_FFE_I_4_DFAP_REG_END                          0x013c7ffc
+#define BCHP_FFE_N_5_DFAP_REG_START                        0x013d0000
+#define BCHP_FFE_N_5_DFAP_REG_END                          0x013d03fc
+#define BCHP_FFE_P_5_DFAP_REG_START                        0x013d1000
+#define BCHP_FFE_P_5_DFAP_REG_END                          0x013d17fc
+#define BCHP_FFE_I_5_DFAP_REG_START                        0x013d4000
+#define BCHP_FFE_I_5_DFAP_REG_END                          0x013d7ffc
+#define BCHP_FFE_N_6_DFAP_REG_START                        0x013e0000
+#define BCHP_FFE_N_6_DFAP_REG_END                          0x013e03fc
+#define BCHP_FFE_P_6_DFAP_REG_START                        0x013e1000
+#define BCHP_FFE_P_6_DFAP_REG_END                          0x013e17fc
+#define BCHP_FFE_I_6_DFAP_REG_START                        0x013e4000
+#define BCHP_FFE_I_6_DFAP_REG_END                          0x013e7ffc
+#define BCHP_FFE_N_7_DFAP_REG_START                        0x013f0000
+#define BCHP_FFE_N_7_DFAP_REG_END                          0x013f03fc
+#define BCHP_FFE_P_7_DFAP_REG_START                        0x013f1000
+#define BCHP_FFE_P_7_DFAP_REG_END                          0x013f17fc
+#define BCHP_FFE_I_7_DFAP_REG_START                        0x013f4000
+#define BCHP_FFE_I_7_DFAP_REG_END                          0x013f7ffc
+#define BCHP_DOWNSTREAM_REG_START                          0x01400000
+#define BCHP_DOWNSTREAM_REG_END                            0x014073e0
+#define BCHP_D31DSMAC_A_REG_START                          0x01600000
+#define BCHP_D31DSMAC_A_REG_END                            0x016073e0
+#define BCHP_D31DSMAC_B_REG_START                          0x01800000
+#define BCHP_D31DSMAC_B_REG_END                            0x018073e0
+#define BCHP_TCOFDM_0_REG_START                            0x01a00000
+#define BCHP_TCOFDM_0_REG_END                              0x01a0086c
+#define BCHP_TCOFDM_1_REG_START                            0x01a10000
+#define BCHP_TCOFDM_1_REG_END                              0x01a1086c
+#define BCHP_TCDTR_0_REG_START                             0x01a20000
+#define BCHP_TCDTR_0_REG_END                               0x01a200fc
+#define BCHP_APM_COMMON_APM_REG_START                      0x01c00000
+#define BCHP_APM_COMMON_APM_REG_END                        0x01c0005c
+#define BCHP_APM_ADC_BIST_APM_REG_START                    0x01c00100
+#define BCHP_APM_ADC_BIST_APM_REG_END                      0x01c001a0
+#define BCHP_APM_ACP_CMN_APM_REG_START                     0x01c00400
+#define BCHP_APM_ACP_CMN_APM_REG_END                       0x01c00424
+#define BCHP_APM_ACP_ChA_APM_REG_START                     0x01c00500
+#define BCHP_APM_ACP_ChA_APM_REG_END                       0x01c0056c
+#define BCHP_APM_ACP_ChB_APM_REG_START                     0x01c00600
+#define BCHP_APM_ACP_ChB_APM_REG_END                       0x01c0066c
+#define BCHP_APM_HVG_CMN_APM_REG_START                     0x01c00800
+#define BCHP_APM_HVG_CMN_APM_REG_END                       0x01c00850
+#define BCHP_APM_HVG_ChA_APM_REG_START                     0x01c00900
+#define BCHP_APM_HVG_ChA_APM_REG_END                       0x01c00950
+#define BCHP_APM_HVG_ChB_APM_REG_START                     0x01c00a00
+#define BCHP_APM_HVG_ChB_APM_REG_END                       0x01c00a50
+#define BCHP_APM_PCM_APM_REG_START                         0x01c00c00
+#define BCHP_APM_PCM_APM_REG_END                           0x01c00c7c
+#define BCHP_APM_DMA_CTRL_APM_REG_START                    0x01c01800
+#define BCHP_APM_DMA_CTRL_APM_REG_END                      0x01c01844
+#define BCHP_APM_DMA_CH0_APM_REG_START                     0x01c01a00
+#define BCHP_APM_DMA_CH0_APM_REG_END                       0x01c01a0c
+#define BCHP_APM_DMA_CH1_APM_REG_START                     0x01c01a10
+#define BCHP_APM_DMA_CH1_APM_REG_END                       0x01c01a1c
+#define BCHP_APM_DMA_CH2_APM_REG_START                     0x01c01a20
+#define BCHP_APM_DMA_CH2_APM_REG_END                       0x01c01a2c
+#define BCHP_APM_DMA_CH3_APM_REG_START                     0x01c01a30
+#define BCHP_APM_DMA_CH3_APM_REG_END                       0x01c01a3c
+#define BCHP_APM_DMA_CH4_APM_REG_START                     0x01c01a40
+#define BCHP_APM_DMA_CH4_APM_REG_END                       0x01c01a4c
+#define BCHP_APM_DMA_CH5_APM_REG_START                     0x01c01a50
+#define BCHP_APM_DMA_CH5_APM_REG_END                       0x01c01a5c
+#define BCHP_APM_DMA_CH0_STATE_APM_REG_START               0x01c01c00
+#define BCHP_APM_DMA_CH0_STATE_APM_REG_END                 0x01c01c0c
+#define BCHP_APM_DMA_CH1_STATE_APM_REG_START               0x01c01c10
+#define BCHP_APM_DMA_CH1_STATE_APM_REG_END                 0x01c01c1c
+#define BCHP_APM_DMA_CH2_STATE_APM_REG_START               0x01c01c20
+#define BCHP_APM_DMA_CH2_STATE_APM_REG_END                 0x01c01c2c
+#define BCHP_APM_DMA_CH3_STATE_APM_REG_START               0x01c01c30
+#define BCHP_APM_DMA_CH3_STATE_APM_REG_END                 0x01c01c3c
+#define BCHP_APM_DMA_CH4_STATE_APM_REG_START               0x01c01c40
+#define BCHP_APM_DMA_CH4_STATE_APM_REG_END                 0x01c01c4c
+#define BCHP_APM_DMA_CH5_STATE_APM_REG_START               0x01c01c50
+#define BCHP_APM_DMA_CH5_STATE_APM_REG_END                 0x01c01c5c
+#define BCHP_APM_BMU_BMU_DMEM_APM_REG_START                0x01c02000
+#define BCHP_APM_BMU_BMU_DMEM_APM_REG_END                  0x01c023fc
+#define BCHP_APM_BMU_BMU_SMEM_APM_REG_START                0x01c02400
+#define BCHP_APM_BMU_BMU_SMEM_APM_REG_END                  0x01c025fc
+#define BCHP_APM_BMU_BMU_LS_APM_REG_START                  0x01c02800
+#define BCHP_APM_BMU_BMU_LS_APM_REG_END                    0x01c0291c
+#define BCHP_APM_BMU_BMU_CP_APM_REG_START                  0x01c02c00
+#define BCHP_APM_BMU_BMU_CP_APM_REG_END                    0x01c02d0c
+#define BCHP_APM_PICO_IMEM_APM_REG_START                   0x01c10000
+#define BCHP_APM_PICO_IMEM_APM_REG_END                     0x01c127fc
+#define BCHP_DECT_AHB_DCT_REG_START                        0x01e00000
+#define BCHP_DECT_AHB_DCT_REG_END                          0x01e07f80
+#define BCHP_DECT_SHM_DCT_REG_START                        0x01e10000
+#define BCHP_DECT_SHM_DCT_REG_END                          0x01e100ac
+#define BCHP_DECT_APB_DCT_REG_START                        0x01e10800
+#define BCHP_DECT_APB_DCT_REG_END                          0x01e10802
+#define BCHP_LEAP_ROM_REG_START                            0x02000000
+#define BCHP_LEAP_ROM_REG_END                              0x02007ffc
+#define BCHP_LEAP_PROG0_MEM_REG_START                      0x02040000
+#define BCHP_LEAP_PROG0_MEM_REG_END                        0x0204bffc
+#define BCHP_LEAP_CPU_CORE_REGS_REG_START                  0x020a0000
+#define BCHP_LEAP_CPU_CORE_REGS_REG_END                    0x020a00fc
+#define BCHP_LEAP_CPU_AUX_REGS_REG_START                   0x020c0000
+#define BCHP_LEAP_CPU_AUX_REGS_REG_END                     0x020c1058
+#define BCHP_LEAP_HAB_MEM_REG_START                        0x020c8000
+#define BCHP_LEAP_HAB_MEM_REG_END                          0x020c83fc
+#define BCHP_LEAP_UART_REG_START                           0x020c9000
+#define BCHP_LEAP_UART_REG_END                             0x020c9ffc
+#define BCHP_LEAP_WDG_REG_START                            0x020ca000
+#define BCHP_LEAP_WDG_REG_END                              0x020caffc
+#define BCHP_LEAP_CTRL_REG_START                           0x02100000
+#define BCHP_LEAP_CTRL_REG_END                             0x02100310
+#define BCHP_LEAP_L1_REG_START                             0x02100400
+#define BCHP_LEAP_L1_REG_END                               0x0210041c
+#define BCHP_LEAP_L2_REG_START                             0x02100500
+#define BCHP_LEAP_L2_REG_END                               0x02100514
+#define BCHP_LEAP_HOST_L1_REG_START                        0x02100600
+#define BCHP_LEAP_HOST_L1_REG_END                          0x0210061c
+#define BCHP_LEAP_HOST_L2_REG_START                        0x02100700
+#define BCHP_LEAP_HOST_L2_REG_END                          0x0210072c
+#define BCHP_LEAP_CTRL_MISC_REG_START                      0x02100800
+#define BCHP_LEAP_CTRL_MISC_REG_END                        0x0210084c
+#define BCHP_LEAP_HOST2_L1_REG_START                       0x02100900
+#define BCHP_LEAP_HOST2_L1_REG_END                         0x0210091c
+#define BCHP_LEAP_ROM_PATCH_REG_START                      0x02100a00
+#define BCHP_LEAP_ROM_PATCH_REG_END                        0x02100a3c
+#define BCHP_DS_A_MICRO_REG_START                          0x02200000
+#define BCHP_DS_A_MICRO_REG_END                            0x0220001c
+#define BCHP_DS_A_TOPS_REG_START                           0x02200100
+#define BCHP_DS_A_TOPS_REG_END                             0x02200148
+#define BCHP_DS_A_TP_REG_START                             0x02200400
+#define BCHP_DS_A_TP_REG_END                               0x02200418
+#define BCHP_OOB_REG_START                                 0x02201000
+#define BCHP_OOB_REG_END                                   0x022011f8
+#define BCHP_DS_A_CHAN_FE_REG_START                        0x02210000
+#define BCHP_DS_A_CHAN_FE_REG_END                          0x0221000c
+#define BCHP_DS_A_CHAN_ACI_ANXA_REG_START                  0x02210100
+#define BCHP_DS_A_CHAN_ACI_ANXA_REG_END                    0x02210144
+#define BCHP_DS_A_CHAN_ACI_ANXB_REG_START                  0x02210200
+#define BCHP_DS_A_CHAN_ACI_ANXB_REG_END                    0x02210244
+#define BCHP_DS_A_CHAN_OOB_ISW_MXR_REG_START               0x02210300
+#define BCHP_DS_A_CHAN_OOB_ISW_MXR_REG_END                 0x02210308
+#define BCHP_DS_A_CHAN_OOB_ACI_AGF_REG_START               0x02210400
+#define BCHP_DS_A_CHAN_OOB_ACI_AGF_REG_END                 0x0221040c
+#define BCHP_DS_A_CHAN_SPECA_ISW_MXR_REG_START             0x02210500
+#define BCHP_DS_A_CHAN_SPECA_ISW_MXR_REG_END               0x02210508
+#define BCHP_DS_A_CHAN_SPECA_ACI_AGF_REG_START             0x02210600
+#define BCHP_DS_A_CHAN_SPECA_ACI_AGF_REG_END               0x0221060c
+#define BCHP_DS_A_CHAN_SPARE_ISW_MXR_REG_START             0x02210700
+#define BCHP_DS_A_CHAN_SPARE_ISW_MXR_REG_END               0x02210708
+#define BCHP_DS_A_CHAN_SPARE_ACI_AGF_REG_START             0x02210800
+#define BCHP_DS_A_CHAN_SPARE_ACI_AGF_REG_END               0x0221080c
+#define BCHP_DS_A_00_ISW_MXR_REG_START                     0x02220000
+#define BCHP_DS_A_00_ISW_MXR_REG_END                       0x02220008
+#define BCHP_DS_A_00_ACI_AGF_REG_START                     0x02220200
+#define BCHP_DS_A_00_ACI_AGF_REG_END                       0x0222037c
+#define BCHP_DS_A_00_TRL_REG_START                         0x02220400
+#define BCHP_DS_A_00_TRL_REG_END                           0x022206fc
+#define BCHP_DS_A_00_EQ_REG_START                          0x02220800
+#define BCHP_DS_A_00_EQ_REG_END                            0x02220bbc
+#define BCHP_DS_A_00_FECF_REG_START                        0x02220c00
+#define BCHP_DS_A_00_FECF_REG_END                          0x02220d7c
+#define BCHP_DS_A_00_FECB_REG_START                        0x02220e00
+#define BCHP_DS_A_00_FECB_REG_END                          0x02220ebc
+#define BCHP_DS_A_00_FFT_REG_START                         0x02221000
+#define BCHP_DS_A_00_FFT_REG_END                           0x0222117c
+#define BCHP_DS_A_00_OI_REG_START                          0x02221200
+#define BCHP_DS_A_00_OI_REG_END                            0x0222123c
+#define BCHP_DS_A_00_IRQ_REG_START                         0x02221300
+#define BCHP_DS_A_00_IRQ_REG_END                           0x02221314
+#define BCHP_DS_A_01_ISW_MXR_REG_START                     0x02222000
+#define BCHP_DS_A_01_ISW_MXR_REG_END                       0x02222008
+#define BCHP_DS_A_01_ACI_AGF_REG_START                     0x02222200
+#define BCHP_DS_A_01_ACI_AGF_REG_END                       0x0222237c
+#define BCHP_DS_A_01_TRL_REG_START                         0x02222400
+#define BCHP_DS_A_01_TRL_REG_END                           0x022226fc
+#define BCHP_DS_A_01_EQ_REG_START                          0x02222800
+#define BCHP_DS_A_01_EQ_REG_END                            0x02222bbc
+#define BCHP_DS_A_01_FECF_REG_START                        0x02222c00
+#define BCHP_DS_A_01_FECF_REG_END                          0x02222d7c
+#define BCHP_DS_A_01_FECB_REG_START                        0x02222e00
+#define BCHP_DS_A_01_FECB_REG_END                          0x02222ebc
+#define BCHP_DS_A_01_FFT_REG_START                         0x02223000
+#define BCHP_DS_A_01_FFT_REG_END                           0x0222317c
+#define BCHP_DS_A_01_OI_REG_START                          0x02223200
+#define BCHP_DS_A_01_OI_REG_END                            0x0222323c
+#define BCHP_DS_A_01_IRQ_REG_START                         0x02223300
+#define BCHP_DS_A_01_IRQ_REG_END                           0x02223314
+#define BCHP_DS_A_02_ISW_MXR_REG_START                     0x02224000
+#define BCHP_DS_A_02_ISW_MXR_REG_END                       0x02224008
+#define BCHP_DS_A_02_ACI_AGF_REG_START                     0x02224200
+#define BCHP_DS_A_02_ACI_AGF_REG_END                       0x0222437c
+#define BCHP_DS_A_02_TRL_REG_START                         0x02224400
+#define BCHP_DS_A_02_TRL_REG_END                           0x022246fc
+#define BCHP_DS_A_02_EQ_REG_START                          0x02224800
+#define BCHP_DS_A_02_EQ_REG_END                            0x02224bbc
+#define BCHP_DS_A_02_FECF_REG_START                        0x02224c00
+#define BCHP_DS_A_02_FECF_REG_END                          0x02224d7c
+#define BCHP_DS_A_02_FECB_REG_START                        0x02224e00
+#define BCHP_DS_A_02_FECB_REG_END                          0x02224ebc
+#define BCHP_DS_A_02_FFT_REG_START                         0x02225000
+#define BCHP_DS_A_02_FFT_REG_END                           0x0222517c
+#define BCHP_DS_A_02_OI_REG_START                          0x02225200
+#define BCHP_DS_A_02_OI_REG_END                            0x0222523c
+#define BCHP_DS_A_02_IRQ_REG_START                         0x02225300
+#define BCHP_DS_A_02_IRQ_REG_END                           0x02225314
+#define BCHP_DS_A_03_ISW_MXR_REG_START                     0x02226000
+#define BCHP_DS_A_03_ISW_MXR_REG_END                       0x02226008
+#define BCHP_DS_A_03_ACI_AGF_REG_START                     0x02226200
+#define BCHP_DS_A_03_ACI_AGF_REG_END                       0x0222637c
+#define BCHP_DS_A_03_TRL_REG_START                         0x02226400
+#define BCHP_DS_A_03_TRL_REG_END                           0x022266fc
+#define BCHP_DS_A_03_EQ_REG_START                          0x02226800
+#define BCHP_DS_A_03_EQ_REG_END                            0x02226bbc
+#define BCHP_DS_A_03_FECF_REG_START                        0x02226c00
+#define BCHP_DS_A_03_FECF_REG_END                          0x02226d7c
+#define BCHP_DS_A_03_FECB_REG_START                        0x02226e00
+#define BCHP_DS_A_03_FECB_REG_END                          0x02226ebc
+#define BCHP_DS_A_03_FFT_REG_START                         0x02227000
+#define BCHP_DS_A_03_FFT_REG_END                           0x0222717c
+#define BCHP_DS_A_03_OI_REG_START                          0x02227200
+#define BCHP_DS_A_03_OI_REG_END                            0x0222723c
+#define BCHP_DS_A_03_IRQ_REG_START                         0x02227300
+#define BCHP_DS_A_03_IRQ_REG_END                           0x02227314
+#define BCHP_DS_A_04_ISW_MXR_REG_START                     0x02228000
+#define BCHP_DS_A_04_ISW_MXR_REG_END                       0x02228008
+#define BCHP_DS_A_04_ACI_AGF_REG_START                     0x02228200
+#define BCHP_DS_A_04_ACI_AGF_REG_END                       0x0222837c
+#define BCHP_DS_A_04_TRL_REG_START                         0x02228400
+#define BCHP_DS_A_04_TRL_REG_END                           0x022286fc
+#define BCHP_DS_A_04_EQ_REG_START                          0x02228800
+#define BCHP_DS_A_04_EQ_REG_END                            0x02228bbc
+#define BCHP_DS_A_04_FECF_REG_START                        0x02228c00
+#define BCHP_DS_A_04_FECF_REG_END                          0x02228d7c
+#define BCHP_DS_A_04_FECB_REG_START                        0x02228e00
+#define BCHP_DS_A_04_FECB_REG_END                          0x02228ebc
+#define BCHP_DS_A_04_FFT_REG_START                         0x02229000
+#define BCHP_DS_A_04_FFT_REG_END                           0x0222917c
+#define BCHP_DS_A_04_OI_REG_START                          0x02229200
+#define BCHP_DS_A_04_OI_REG_END                            0x0222923c
+#define BCHP_DS_A_04_IRQ_REG_START                         0x02229300
+#define BCHP_DS_A_04_IRQ_REG_END                           0x02229314
+#define BCHP_DS_A_05_ISW_MXR_REG_START                     0x0222a000
+#define BCHP_DS_A_05_ISW_MXR_REG_END                       0x0222a008
+#define BCHP_DS_A_05_ACI_AGF_REG_START                     0x0222a200
+#define BCHP_DS_A_05_ACI_AGF_REG_END                       0x0222a37c
+#define BCHP_DS_A_05_TRL_REG_START                         0x0222a400
+#define BCHP_DS_A_05_TRL_REG_END                           0x0222a6fc
+#define BCHP_DS_A_05_EQ_REG_START                          0x0222a800
+#define BCHP_DS_A_05_EQ_REG_END                            0x0222abbc
+#define BCHP_DS_A_05_FECF_REG_START                        0x0222ac00
+#define BCHP_DS_A_05_FECF_REG_END                          0x0222ad7c
+#define BCHP_DS_A_05_FECB_REG_START                        0x0222ae00
+#define BCHP_DS_A_05_FECB_REG_END                          0x0222aebc
+#define BCHP_DS_A_05_FFT_REG_START                         0x0222b000
+#define BCHP_DS_A_05_FFT_REG_END                           0x0222b17c
+#define BCHP_DS_A_05_OI_REG_START                          0x0222b200
+#define BCHP_DS_A_05_OI_REG_END                            0x0222b23c
+#define BCHP_DS_A_05_IRQ_REG_START                         0x0222b300
+#define BCHP_DS_A_05_IRQ_REG_END                           0x0222b314
+#define BCHP_DS_A_06_ISW_MXR_REG_START                     0x0222c000
+#define BCHP_DS_A_06_ISW_MXR_REG_END                       0x0222c008
+#define BCHP_DS_A_06_ACI_AGF_REG_START                     0x0222c200
+#define BCHP_DS_A_06_ACI_AGF_REG_END                       0x0222c37c
+#define BCHP_DS_A_06_TRL_REG_START                         0x0222c400
+#define BCHP_DS_A_06_TRL_REG_END                           0x0222c6fc
+#define BCHP_DS_A_06_EQ_REG_START                          0x0222c800
+#define BCHP_DS_A_06_EQ_REG_END                            0x0222cbbc
+#define BCHP_DS_A_06_FECF_REG_START                        0x0222cc00
+#define BCHP_DS_A_06_FECF_REG_END                          0x0222cd7c
+#define BCHP_DS_A_06_FECB_REG_START                        0x0222ce00
+#define BCHP_DS_A_06_FECB_REG_END                          0x0222cebc
+#define BCHP_DS_A_06_FFT_REG_START                         0x0222d000
+#define BCHP_DS_A_06_FFT_REG_END                           0x0222d17c
+#define BCHP_DS_A_06_OI_REG_START                          0x0222d200
+#define BCHP_DS_A_06_OI_REG_END                            0x0222d23c
+#define BCHP_DS_A_06_IRQ_REG_START                         0x0222d300
+#define BCHP_DS_A_06_IRQ_REG_END                           0x0222d314
+#define BCHP_DS_A_07_ISW_MXR_REG_START                     0x0222e000
+#define BCHP_DS_A_07_ISW_MXR_REG_END                       0x0222e008
+#define BCHP_DS_A_07_ACI_AGF_REG_START                     0x0222e200
+#define BCHP_DS_A_07_ACI_AGF_REG_END                       0x0222e37c
+#define BCHP_DS_A_07_TRL_REG_START                         0x0222e400
+#define BCHP_DS_A_07_TRL_REG_END                           0x0222e6fc
+#define BCHP_DS_A_07_EQ_REG_START                          0x0222e800
+#define BCHP_DS_A_07_EQ_REG_END                            0x0222ebbc
+#define BCHP_DS_A_07_FECF_REG_START                        0x0222ec00
+#define BCHP_DS_A_07_FECF_REG_END                          0x0222ed7c
+#define BCHP_DS_A_07_FECB_REG_START                        0x0222ee00
+#define BCHP_DS_A_07_FECB_REG_END                          0x0222eebc
+#define BCHP_DS_A_07_FFT_REG_START                         0x0222f000
+#define BCHP_DS_A_07_FFT_REG_END                           0x0222f17c
+#define BCHP_DS_A_07_OI_REG_START                          0x0222f200
+#define BCHP_DS_A_07_OI_REG_END                            0x0222f23c
+#define BCHP_DS_A_07_IRQ_REG_START                         0x0222f300
+#define BCHP_DS_A_07_IRQ_REG_END                           0x0222f314
+#define BCHP_DS_A_08_ISW_MXR_REG_START                     0x02230000
+#define BCHP_DS_A_08_ISW_MXR_REG_END                       0x02230008
+#define BCHP_DS_A_08_ACI_AGF_REG_START                     0x02230200
+#define BCHP_DS_A_08_ACI_AGF_REG_END                       0x0223037c
+#define BCHP_DS_A_08_TRL_REG_START                         0x02230400
+#define BCHP_DS_A_08_TRL_REG_END                           0x022306fc
+#define BCHP_DS_A_08_EQ_REG_START                          0x02230800
+#define BCHP_DS_A_08_EQ_REG_END                            0x02230bbc
+#define BCHP_DS_A_08_FECF_REG_START                        0x02230c00
+#define BCHP_DS_A_08_FECF_REG_END                          0x02230d7c
+#define BCHP_DS_A_08_FECB_REG_START                        0x02230e00
+#define BCHP_DS_A_08_FECB_REG_END                          0x02230ebc
+#define BCHP_DS_A_08_FFT_REG_START                         0x02231000
+#define BCHP_DS_A_08_FFT_REG_END                           0x0223117c
+#define BCHP_DS_A_08_OI_REG_START                          0x02231200
+#define BCHP_DS_A_08_OI_REG_END                            0x0223123c
+#define BCHP_DS_A_08_IRQ_REG_START                         0x02231300
+#define BCHP_DS_A_08_IRQ_REG_END                           0x02231314
+#define BCHP_DS_A_09_ISW_MXR_REG_START                     0x02232000
+#define BCHP_DS_A_09_ISW_MXR_REG_END                       0x02232008
+#define BCHP_DS_A_09_ACI_AGF_REG_START                     0x02232200
+#define BCHP_DS_A_09_ACI_AGF_REG_END                       0x0223237c
+#define BCHP_DS_A_09_TRL_REG_START                         0x02232400
+#define BCHP_DS_A_09_TRL_REG_END                           0x022326fc
+#define BCHP_DS_A_09_EQ_REG_START                          0x02232800
+#define BCHP_DS_A_09_EQ_REG_END                            0x02232bbc
+#define BCHP_DS_A_09_FECF_REG_START                        0x02232c00
+#define BCHP_DS_A_09_FECF_REG_END                          0x02232d7c
+#define BCHP_DS_A_09_FECB_REG_START                        0x02232e00
+#define BCHP_DS_A_09_FECB_REG_END                          0x02232ebc
+#define BCHP_DS_A_09_FFT_REG_START                         0x02233000
+#define BCHP_DS_A_09_FFT_REG_END                           0x0223317c
+#define BCHP_DS_A_09_OI_REG_START                          0x02233200
+#define BCHP_DS_A_09_OI_REG_END                            0x0223323c
+#define BCHP_DS_A_09_IRQ_REG_START                         0x02233300
+#define BCHP_DS_A_09_IRQ_REG_END                           0x02233314
+#define BCHP_DS_A_10_ISW_MXR_REG_START                     0x02234000
+#define BCHP_DS_A_10_ISW_MXR_REG_END                       0x02234008
+#define BCHP_DS_A_10_ACI_AGF_REG_START                     0x02234200
+#define BCHP_DS_A_10_ACI_AGF_REG_END                       0x0223437c
+#define BCHP_DS_A_10_TRL_REG_START                         0x02234400
+#define BCHP_DS_A_10_TRL_REG_END                           0x022346fc
+#define BCHP_DS_A_10_EQ_REG_START                          0x02234800
+#define BCHP_DS_A_10_EQ_REG_END                            0x02234bbc
+#define BCHP_DS_A_10_FECF_REG_START                        0x02234c00
+#define BCHP_DS_A_10_FECF_REG_END                          0x02234d7c
+#define BCHP_DS_A_10_FECB_REG_START                        0x02234e00
+#define BCHP_DS_A_10_FECB_REG_END                          0x02234ebc
+#define BCHP_DS_A_10_FFT_REG_START                         0x02235000
+#define BCHP_DS_A_10_FFT_REG_END                           0x0223517c
+#define BCHP_DS_A_10_OI_REG_START                          0x02235200
+#define BCHP_DS_A_10_OI_REG_END                            0x0223523c
+#define BCHP_DS_A_10_IRQ_REG_START                         0x02235300
+#define BCHP_DS_A_10_IRQ_REG_END                           0x02235314
+#define BCHP_DS_A_11_ISW_MXR_REG_START                     0x02236000
+#define BCHP_DS_A_11_ISW_MXR_REG_END                       0x02236008
+#define BCHP_DS_A_11_ACI_AGF_REG_START                     0x02236200
+#define BCHP_DS_A_11_ACI_AGF_REG_END                       0x0223637c
+#define BCHP_DS_A_11_TRL_REG_START                         0x02236400
+#define BCHP_DS_A_11_TRL_REG_END                           0x022366fc
+#define BCHP_DS_A_11_EQ_REG_START                          0x02236800
+#define BCHP_DS_A_11_EQ_REG_END                            0x02236bbc
+#define BCHP_DS_A_11_FECF_REG_START                        0x02236c00
+#define BCHP_DS_A_11_FECF_REG_END                          0x02236d7c
+#define BCHP_DS_A_11_FECB_REG_START                        0x02236e00
+#define BCHP_DS_A_11_FECB_REG_END                          0x02236ebc
+#define BCHP_DS_A_11_FFT_REG_START                         0x02237000
+#define BCHP_DS_A_11_FFT_REG_END                           0x0223717c
+#define BCHP_DS_A_11_OI_REG_START                          0x02237200
+#define BCHP_DS_A_11_OI_REG_END                            0x0223723c
+#define BCHP_DS_A_11_IRQ_REG_START                         0x02237300
+#define BCHP_DS_A_11_IRQ_REG_END                           0x02237314
+#define BCHP_DS_A_12_ISW_MXR_REG_START                     0x02238000
+#define BCHP_DS_A_12_ISW_MXR_REG_END                       0x02238008
+#define BCHP_DS_A_12_ACI_AGF_REG_START                     0x02238200
+#define BCHP_DS_A_12_ACI_AGF_REG_END                       0x0223837c
+#define BCHP_DS_A_12_TRL_REG_START                         0x02238400
+#define BCHP_DS_A_12_TRL_REG_END                           0x022386fc
+#define BCHP_DS_A_12_EQ_REG_START                          0x02238800
+#define BCHP_DS_A_12_EQ_REG_END                            0x02238bbc
+#define BCHP_DS_A_12_FECF_REG_START                        0x02238c00
+#define BCHP_DS_A_12_FECF_REG_END                          0x02238d7c
+#define BCHP_DS_A_12_FECB_REG_START                        0x02238e00
+#define BCHP_DS_A_12_FECB_REG_END                          0x02238ebc
+#define BCHP_DS_A_12_FFT_REG_START                         0x02239000
+#define BCHP_DS_A_12_FFT_REG_END                           0x0223917c
+#define BCHP_DS_A_12_OI_REG_START                          0x02239200
+#define BCHP_DS_A_12_OI_REG_END                            0x0223923c
+#define BCHP_DS_A_12_IRQ_REG_START                         0x02239300
+#define BCHP_DS_A_12_IRQ_REG_END                           0x02239314
+#define BCHP_DS_A_13_ISW_MXR_REG_START                     0x0223a000
+#define BCHP_DS_A_13_ISW_MXR_REG_END                       0x0223a008
+#define BCHP_DS_A_13_ACI_AGF_REG_START                     0x0223a200
+#define BCHP_DS_A_13_ACI_AGF_REG_END                       0x0223a37c
+#define BCHP_DS_A_13_TRL_REG_START                         0x0223a400
+#define BCHP_DS_A_13_TRL_REG_END                           0x0223a6fc
+#define BCHP_DS_A_13_EQ_REG_START                          0x0223a800
+#define BCHP_DS_A_13_EQ_REG_END                            0x0223abbc
+#define BCHP_DS_A_13_FECF_REG_START                        0x0223ac00
+#define BCHP_DS_A_13_FECF_REG_END                          0x0223ad7c
+#define BCHP_DS_A_13_FECB_REG_START                        0x0223ae00
+#define BCHP_DS_A_13_FECB_REG_END                          0x0223aebc
+#define BCHP_DS_A_13_FFT_REG_START                         0x0223b000
+#define BCHP_DS_A_13_FFT_REG_END                           0x0223b17c
+#define BCHP_DS_A_13_OI_REG_START                          0x0223b200
+#define BCHP_DS_A_13_OI_REG_END                            0x0223b23c
+#define BCHP_DS_A_13_IRQ_REG_START                         0x0223b300
+#define BCHP_DS_A_13_IRQ_REG_END                           0x0223b314
+#define BCHP_DS_A_14_ISW_MXR_REG_START                     0x0223c000
+#define BCHP_DS_A_14_ISW_MXR_REG_END                       0x0223c008
+#define BCHP_DS_A_14_ACI_AGF_REG_START                     0x0223c200
+#define BCHP_DS_A_14_ACI_AGF_REG_END                       0x0223c37c
+#define BCHP_DS_A_14_TRL_REG_START                         0x0223c400
+#define BCHP_DS_A_14_TRL_REG_END                           0x0223c6fc
+#define BCHP_DS_A_14_EQ_REG_START                          0x0223c800
+#define BCHP_DS_A_14_EQ_REG_END                            0x0223cbbc
+#define BCHP_DS_A_14_FECF_REG_START                        0x0223cc00
+#define BCHP_DS_A_14_FECF_REG_END                          0x0223cd7c
+#define BCHP_DS_A_14_FECB_REG_START                        0x0223ce00
+#define BCHP_DS_A_14_FECB_REG_END                          0x0223cebc
+#define BCHP_DS_A_14_FFT_REG_START                         0x0223d000
+#define BCHP_DS_A_14_FFT_REG_END                           0x0223d17c
+#define BCHP_DS_A_14_OI_REG_START                          0x0223d200
+#define BCHP_DS_A_14_OI_REG_END                            0x0223d23c
+#define BCHP_DS_A_14_IRQ_REG_START                         0x0223d300
+#define BCHP_DS_A_14_IRQ_REG_END                           0x0223d314
+#define BCHP_DS_A_15_ISW_MXR_REG_START                     0x0223e000
+#define BCHP_DS_A_15_ISW_MXR_REG_END                       0x0223e008
+#define BCHP_DS_A_15_ACI_AGF_REG_START                     0x0223e200
+#define BCHP_DS_A_15_ACI_AGF_REG_END                       0x0223e37c
+#define BCHP_DS_A_15_TRL_REG_START                         0x0223e400
+#define BCHP_DS_A_15_TRL_REG_END                           0x0223e6fc
+#define BCHP_DS_A_15_EQ_REG_START                          0x0223e800
+#define BCHP_DS_A_15_EQ_REG_END                            0x0223ebbc
+#define BCHP_DS_A_15_FECF_REG_START                        0x0223ec00
+#define BCHP_DS_A_15_FECF_REG_END                          0x0223ed7c
+#define BCHP_DS_A_15_FECB_REG_START                        0x0223ee00
+#define BCHP_DS_A_15_FECB_REG_END                          0x0223eebc
+#define BCHP_DS_A_15_FFT_REG_START                         0x0223f000
+#define BCHP_DS_A_15_FFT_REG_END                           0x0223f17c
+#define BCHP_DS_A_15_OI_REG_START                          0x0223f200
+#define BCHP_DS_A_15_OI_REG_END                            0x0223f23c
+#define BCHP_DS_A_15_IRQ_REG_START                         0x0223f300
+#define BCHP_DS_A_15_IRQ_REG_END                           0x0223f314
+#define BCHP_DS_A_16_ISW_MXR_REG_START                     0x02240000
+#define BCHP_DS_A_16_ISW_MXR_REG_END                       0x02240008
+#define BCHP_DS_A_16_ACI_AGF_REG_START                     0x02240200
+#define BCHP_DS_A_16_ACI_AGF_REG_END                       0x0224037c
+#define BCHP_DS_A_16_TRL_REG_START                         0x02240400
+#define BCHP_DS_A_16_TRL_REG_END                           0x022406fc
+#define BCHP_DS_A_16_EQ_REG_START                          0x02240800
+#define BCHP_DS_A_16_EQ_REG_END                            0x02240bbc
+#define BCHP_DS_A_16_FECF_REG_START                        0x02240c00
+#define BCHP_DS_A_16_FECF_REG_END                          0x02240d7c
+#define BCHP_DS_A_16_FECB_REG_START                        0x02240e00
+#define BCHP_DS_A_16_FECB_REG_END                          0x02240ebc
+#define BCHP_DS_A_16_FFT_REG_START                         0x02241000
+#define BCHP_DS_A_16_FFT_REG_END                           0x0224117c
+#define BCHP_DS_A_16_OI_REG_START                          0x02241200
+#define BCHP_DS_A_16_OI_REG_END                            0x0224123c
+#define BCHP_DS_A_16_IRQ_REG_START                         0x02241300
+#define BCHP_DS_A_16_IRQ_REG_END                           0x02241314
+#define BCHP_DS_A_17_ISW_MXR_REG_START                     0x02242000
+#define BCHP_DS_A_17_ISW_MXR_REG_END                       0x02242008
+#define BCHP_DS_A_17_ACI_AGF_REG_START                     0x02242200
+#define BCHP_DS_A_17_ACI_AGF_REG_END                       0x0224237c
+#define BCHP_DS_A_17_TRL_REG_START                         0x02242400
+#define BCHP_DS_A_17_TRL_REG_END                           0x022426fc
+#define BCHP_DS_A_17_EQ_REG_START                          0x02242800
+#define BCHP_DS_A_17_EQ_REG_END                            0x02242bbc
+#define BCHP_DS_A_17_FECF_REG_START                        0x02242c00
+#define BCHP_DS_A_17_FECF_REG_END                          0x02242d7c
+#define BCHP_DS_A_17_FECB_REG_START                        0x02242e00
+#define BCHP_DS_A_17_FECB_REG_END                          0x02242ebc
+#define BCHP_DS_A_17_FFT_REG_START                         0x02243000
+#define BCHP_DS_A_17_FFT_REG_END                           0x0224317c
+#define BCHP_DS_A_17_OI_REG_START                          0x02243200
+#define BCHP_DS_A_17_OI_REG_END                            0x0224323c
+#define BCHP_DS_A_17_IRQ_REG_START                         0x02243300
+#define BCHP_DS_A_17_IRQ_REG_END                           0x02243314
+#define BCHP_DS_A_18_ISW_MXR_REG_START                     0x02244000
+#define BCHP_DS_A_18_ISW_MXR_REG_END                       0x02244008
+#define BCHP_DS_A_18_ACI_AGF_REG_START                     0x02244200
+#define BCHP_DS_A_18_ACI_AGF_REG_END                       0x0224437c
+#define BCHP_DS_A_18_TRL_REG_START                         0x02244400
+#define BCHP_DS_A_18_TRL_REG_END                           0x022446fc
+#define BCHP_DS_A_18_EQ_REG_START                          0x02244800
+#define BCHP_DS_A_18_EQ_REG_END                            0x02244bbc
+#define BCHP_DS_A_18_FECF_REG_START                        0x02244c00
+#define BCHP_DS_A_18_FECF_REG_END                          0x02244d7c
+#define BCHP_DS_A_18_FECB_REG_START                        0x02244e00
+#define BCHP_DS_A_18_FECB_REG_END                          0x02244ebc
+#define BCHP_DS_A_18_FFT_REG_START                         0x02245000
+#define BCHP_DS_A_18_FFT_REG_END                           0x0224517c
+#define BCHP_DS_A_18_OI_REG_START                          0x02245200
+#define BCHP_DS_A_18_OI_REG_END                            0x0224523c
+#define BCHP_DS_A_18_IRQ_REG_START                         0x02245300
+#define BCHP_DS_A_18_IRQ_REG_END                           0x02245314
+#define BCHP_DS_A_19_ISW_MXR_REG_START                     0x02246000
+#define BCHP_DS_A_19_ISW_MXR_REG_END                       0x02246008
+#define BCHP_DS_A_19_ACI_AGF_REG_START                     0x02246200
+#define BCHP_DS_A_19_ACI_AGF_REG_END                       0x0224637c
+#define BCHP_DS_A_19_TRL_REG_START                         0x02246400
+#define BCHP_DS_A_19_TRL_REG_END                           0x022466fc
+#define BCHP_DS_A_19_EQ_REG_START                          0x02246800
+#define BCHP_DS_A_19_EQ_REG_END                            0x02246bbc
+#define BCHP_DS_A_19_FECF_REG_START                        0x02246c00
+#define BCHP_DS_A_19_FECF_REG_END                          0x02246d7c
+#define BCHP_DS_A_19_FECB_REG_START                        0x02246e00
+#define BCHP_DS_A_19_FECB_REG_END                          0x02246ebc
+#define BCHP_DS_A_19_FFT_REG_START                         0x02247000
+#define BCHP_DS_A_19_FFT_REG_END                           0x0224717c
+#define BCHP_DS_A_19_OI_REG_START                          0x02247200
+#define BCHP_DS_A_19_OI_REG_END                            0x0224723c
+#define BCHP_DS_A_19_IRQ_REG_START                         0x02247300
+#define BCHP_DS_A_19_IRQ_REG_END                           0x02247314
+#define BCHP_DS_A_20_ISW_MXR_REG_START                     0x02248000
+#define BCHP_DS_A_20_ISW_MXR_REG_END                       0x02248008
+#define BCHP_DS_A_20_ACI_AGF_REG_START                     0x02248200
+#define BCHP_DS_A_20_ACI_AGF_REG_END                       0x0224837c
+#define BCHP_DS_A_20_TRL_REG_START                         0x02248400
+#define BCHP_DS_A_20_TRL_REG_END                           0x022486fc
+#define BCHP_DS_A_20_EQ_REG_START                          0x02248800
+#define BCHP_DS_A_20_EQ_REG_END                            0x02248bbc
+#define BCHP_DS_A_20_FECF_REG_START                        0x02248c00
+#define BCHP_DS_A_20_FECF_REG_END                          0x02248d7c
+#define BCHP_DS_A_20_FECB_REG_START                        0x02248e00
+#define BCHP_DS_A_20_FECB_REG_END                          0x02248ebc
+#define BCHP_DS_A_20_FFT_REG_START                         0x02249000
+#define BCHP_DS_A_20_FFT_REG_END                           0x0224917c
+#define BCHP_DS_A_20_OI_REG_START                          0x02249200
+#define BCHP_DS_A_20_OI_REG_END                            0x0224923c
+#define BCHP_DS_A_20_IRQ_REG_START                         0x02249300
+#define BCHP_DS_A_20_IRQ_REG_END                           0x02249314
+#define BCHP_DS_A_21_ISW_MXR_REG_START                     0x0224a000
+#define BCHP_DS_A_21_ISW_MXR_REG_END                       0x0224a008
+#define BCHP_DS_A_21_ACI_AGF_REG_START                     0x0224a200
+#define BCHP_DS_A_21_ACI_AGF_REG_END                       0x0224a37c
+#define BCHP_DS_A_21_TRL_REG_START                         0x0224a400
+#define BCHP_DS_A_21_TRL_REG_END                           0x0224a6fc
+#define BCHP_DS_A_21_EQ_REG_START                          0x0224a800
+#define BCHP_DS_A_21_EQ_REG_END                            0x0224abbc
+#define BCHP_DS_A_21_FECF_REG_START                        0x0224ac00
+#define BCHP_DS_A_21_FECF_REG_END                          0x0224ad7c
+#define BCHP_DS_A_21_FECB_REG_START                        0x0224ae00
+#define BCHP_DS_A_21_FECB_REG_END                          0x0224aebc
+#define BCHP_DS_A_21_FFT_REG_START                         0x0224b000
+#define BCHP_DS_A_21_FFT_REG_END                           0x0224b17c
+#define BCHP_DS_A_21_OI_REG_START                          0x0224b200
+#define BCHP_DS_A_21_OI_REG_END                            0x0224b23c
+#define BCHP_DS_A_21_IRQ_REG_START                         0x0224b300
+#define BCHP_DS_A_21_IRQ_REG_END                           0x0224b314
+#define BCHP_DS_A_22_ISW_MXR_REG_START                     0x0224c000
+#define BCHP_DS_A_22_ISW_MXR_REG_END                       0x0224c008
+#define BCHP_DS_A_22_ACI_AGF_REG_START                     0x0224c200
+#define BCHP_DS_A_22_ACI_AGF_REG_END                       0x0224c37c
+#define BCHP_DS_A_22_TRL_REG_START                         0x0224c400
+#define BCHP_DS_A_22_TRL_REG_END                           0x0224c6fc
+#define BCHP_DS_A_22_EQ_REG_START                          0x0224c800
+#define BCHP_DS_A_22_EQ_REG_END                            0x0224cbbc
+#define BCHP_DS_A_22_FECF_REG_START                        0x0224cc00
+#define BCHP_DS_A_22_FECF_REG_END                          0x0224cd7c
+#define BCHP_DS_A_22_FECB_REG_START                        0x0224ce00
+#define BCHP_DS_A_22_FECB_REG_END                          0x0224cebc
+#define BCHP_DS_A_22_FFT_REG_START                         0x0224d000
+#define BCHP_DS_A_22_FFT_REG_END                           0x0224d17c
+#define BCHP_DS_A_22_OI_REG_START                          0x0224d200
+#define BCHP_DS_A_22_OI_REG_END                            0x0224d23c
+#define BCHP_DS_A_22_IRQ_REG_START                         0x0224d300
+#define BCHP_DS_A_22_IRQ_REG_END                           0x0224d314
+#define BCHP_DS_A_23_ISW_MXR_REG_START                     0x0224e000
+#define BCHP_DS_A_23_ISW_MXR_REG_END                       0x0224e008
+#define BCHP_DS_A_23_ACI_AGF_REG_START                     0x0224e200
+#define BCHP_DS_A_23_ACI_AGF_REG_END                       0x0224e37c
+#define BCHP_DS_A_23_TRL_REG_START                         0x0224e400
+#define BCHP_DS_A_23_TRL_REG_END                           0x0224e6fc
+#define BCHP_DS_A_23_EQ_REG_START                          0x0224e800
+#define BCHP_DS_A_23_EQ_REG_END                            0x0224ebbc
+#define BCHP_DS_A_23_FECF_REG_START                        0x0224ec00
+#define BCHP_DS_A_23_FECF_REG_END                          0x0224ed7c
+#define BCHP_DS_A_23_FECB_REG_START                        0x0224ee00
+#define BCHP_DS_A_23_FECB_REG_END                          0x0224eebc
+#define BCHP_DS_A_23_FFT_REG_START                         0x0224f000
+#define BCHP_DS_A_23_FFT_REG_END                           0x0224f17c
+#define BCHP_DS_A_23_OI_REG_START                          0x0224f200
+#define BCHP_DS_A_23_OI_REG_END                            0x0224f23c
+#define BCHP_DS_A_23_IRQ_REG_START                         0x0224f300
+#define BCHP_DS_A_23_IRQ_REG_END                           0x0224f314
+#define BCHP_DS_A_24_ISW_MXR_REG_START                     0x02250000
+#define BCHP_DS_A_24_ISW_MXR_REG_END                       0x02250008
+#define BCHP_DS_A_24_ACI_AGF_REG_START                     0x02250200
+#define BCHP_DS_A_24_ACI_AGF_REG_END                       0x0225037c
+#define BCHP_DS_A_24_TRL_REG_START                         0x02250400
+#define BCHP_DS_A_24_TRL_REG_END                           0x022506fc
+#define BCHP_DS_A_24_EQ_REG_START                          0x02250800
+#define BCHP_DS_A_24_EQ_REG_END                            0x02250bbc
+#define BCHP_DS_A_24_FECF_REG_START                        0x02250c00
+#define BCHP_DS_A_24_FECF_REG_END                          0x02250d7c
+#define BCHP_DS_A_24_FECB_REG_START                        0x02250e00
+#define BCHP_DS_A_24_FECB_REG_END                          0x02250ebc
+#define BCHP_DS_A_24_FFT_REG_START                         0x02251000
+#define BCHP_DS_A_24_FFT_REG_END                           0x0225117c
+#define BCHP_DS_A_24_OI_REG_START                          0x02251200
+#define BCHP_DS_A_24_OI_REG_END                            0x0225123c
+#define BCHP_DS_A_24_IRQ_REG_START                         0x02251300
+#define BCHP_DS_A_24_IRQ_REG_END                           0x02251314
+#define BCHP_DS_A_25_ISW_MXR_REG_START                     0x02252000
+#define BCHP_DS_A_25_ISW_MXR_REG_END                       0x02252008
+#define BCHP_DS_A_25_ACI_AGF_REG_START                     0x02252200
+#define BCHP_DS_A_25_ACI_AGF_REG_END                       0x0225237c
+#define BCHP_DS_A_25_TRL_REG_START                         0x02252400
+#define BCHP_DS_A_25_TRL_REG_END                           0x022526fc
+#define BCHP_DS_A_25_EQ_REG_START                          0x02252800
+#define BCHP_DS_A_25_EQ_REG_END                            0x02252bbc
+#define BCHP_DS_A_25_FECF_REG_START                        0x02252c00
+#define BCHP_DS_A_25_FECF_REG_END                          0x02252d7c
+#define BCHP_DS_A_25_FECB_REG_START                        0x02252e00
+#define BCHP_DS_A_25_FECB_REG_END                          0x02252ebc
+#define BCHP_DS_A_25_FFT_REG_START                         0x02253000
+#define BCHP_DS_A_25_FFT_REG_END                           0x0225317c
+#define BCHP_DS_A_25_OI_REG_START                          0x02253200
+#define BCHP_DS_A_25_OI_REG_END                            0x0225323c
+#define BCHP_DS_A_25_IRQ_REG_START                         0x02253300
+#define BCHP_DS_A_25_IRQ_REG_END                           0x02253314
+#define BCHP_DS_A_26_ISW_MXR_REG_START                     0x02254000
+#define BCHP_DS_A_26_ISW_MXR_REG_END                       0x02254008
+#define BCHP_DS_A_26_ACI_AGF_REG_START                     0x02254200
+#define BCHP_DS_A_26_ACI_AGF_REG_END                       0x0225437c
+#define BCHP_DS_A_26_TRL_REG_START                         0x02254400
+#define BCHP_DS_A_26_TRL_REG_END                           0x022546fc
+#define BCHP_DS_A_26_EQ_REG_START                          0x02254800
+#define BCHP_DS_A_26_EQ_REG_END                            0x02254bbc
+#define BCHP_DS_A_26_FECF_REG_START                        0x02254c00
+#define BCHP_DS_A_26_FECF_REG_END                          0x02254d7c
+#define BCHP_DS_A_26_FECB_REG_START                        0x02254e00
+#define BCHP_DS_A_26_FECB_REG_END                          0x02254ebc
+#define BCHP_DS_A_26_FFT_REG_START                         0x02255000
+#define BCHP_DS_A_26_FFT_REG_END                           0x0225517c
+#define BCHP_DS_A_26_OI_REG_START                          0x02255200
+#define BCHP_DS_A_26_OI_REG_END                            0x0225523c
+#define BCHP_DS_A_26_IRQ_REG_START                         0x02255300
+#define BCHP_DS_A_26_IRQ_REG_END                           0x02255314
+#define BCHP_DS_A_27_ISW_MXR_REG_START                     0x02256000
+#define BCHP_DS_A_27_ISW_MXR_REG_END                       0x02256008
+#define BCHP_DS_A_27_ACI_AGF_REG_START                     0x02256200
+#define BCHP_DS_A_27_ACI_AGF_REG_END                       0x0225637c
+#define BCHP_DS_A_27_TRL_REG_START                         0x02256400
+#define BCHP_DS_A_27_TRL_REG_END                           0x022566fc
+#define BCHP_DS_A_27_EQ_REG_START                          0x02256800
+#define BCHP_DS_A_27_EQ_REG_END                            0x02256bbc
+#define BCHP_DS_A_27_FECF_REG_START                        0x02256c00
+#define BCHP_DS_A_27_FECF_REG_END                          0x02256d7c
+#define BCHP_DS_A_27_FECB_REG_START                        0x02256e00
+#define BCHP_DS_A_27_FECB_REG_END                          0x02256ebc
+#define BCHP_DS_A_27_FFT_REG_START                         0x02257000
+#define BCHP_DS_A_27_FFT_REG_END                           0x0225717c
+#define BCHP_DS_A_27_OI_REG_START                          0x02257200
+#define BCHP_DS_A_27_OI_REG_END                            0x0225723c
+#define BCHP_DS_A_27_IRQ_REG_START                         0x02257300
+#define BCHP_DS_A_27_IRQ_REG_END                           0x02257314
+#define BCHP_DS_A_28_ISW_MXR_REG_START                     0x02258000
+#define BCHP_DS_A_28_ISW_MXR_REG_END                       0x02258008
+#define BCHP_DS_A_28_ACI_AGF_REG_START                     0x02258200
+#define BCHP_DS_A_28_ACI_AGF_REG_END                       0x0225837c
+#define BCHP_DS_A_28_TRL_REG_START                         0x02258400
+#define BCHP_DS_A_28_TRL_REG_END                           0x022586fc
+#define BCHP_DS_A_28_EQ_REG_START                          0x02258800
+#define BCHP_DS_A_28_EQ_REG_END                            0x02258bbc
+#define BCHP_DS_A_28_FECF_REG_START                        0x02258c00
+#define BCHP_DS_A_28_FECF_REG_END                          0x02258d7c
+#define BCHP_DS_A_28_FECB_REG_START                        0x02258e00
+#define BCHP_DS_A_28_FECB_REG_END                          0x02258ebc
+#define BCHP_DS_A_28_FFT_REG_START                         0x02259000
+#define BCHP_DS_A_28_FFT_REG_END                           0x0225917c
+#define BCHP_DS_A_28_OI_REG_START                          0x02259200
+#define BCHP_DS_A_28_OI_REG_END                            0x0225923c
+#define BCHP_DS_A_28_IRQ_REG_START                         0x02259300
+#define BCHP_DS_A_28_IRQ_REG_END                           0x02259314
+#define BCHP_DS_A_29_ISW_MXR_REG_START                     0x0225a000
+#define BCHP_DS_A_29_ISW_MXR_REG_END                       0x0225a008
+#define BCHP_DS_A_29_ACI_AGF_REG_START                     0x0225a200
+#define BCHP_DS_A_29_ACI_AGF_REG_END                       0x0225a37c
+#define BCHP_DS_A_29_TRL_REG_START                         0x0225a400
+#define BCHP_DS_A_29_TRL_REG_END                           0x0225a6fc
+#define BCHP_DS_A_29_EQ_REG_START                          0x0225a800
+#define BCHP_DS_A_29_EQ_REG_END                            0x0225abbc
+#define BCHP_DS_A_29_FECF_REG_START                        0x0225ac00
+#define BCHP_DS_A_29_FECF_REG_END                          0x0225ad7c
+#define BCHP_DS_A_29_FECB_REG_START                        0x0225ae00
+#define BCHP_DS_A_29_FECB_REG_END                          0x0225aebc
+#define BCHP_DS_A_29_FFT_REG_START                         0x0225b000
+#define BCHP_DS_A_29_FFT_REG_END                           0x0225b17c
+#define BCHP_DS_A_29_OI_REG_START                          0x0225b200
+#define BCHP_DS_A_29_OI_REG_END                            0x0225b23c
+#define BCHP_DS_A_29_IRQ_REG_START                         0x0225b300
+#define BCHP_DS_A_29_IRQ_REG_END                           0x0225b314
+#define BCHP_DS_A_30_ISW_MXR_REG_START                     0x0225c000
+#define BCHP_DS_A_30_ISW_MXR_REG_END                       0x0225c008
+#define BCHP_DS_A_30_ACI_AGF_REG_START                     0x0225c200
+#define BCHP_DS_A_30_ACI_AGF_REG_END                       0x0225c37c
+#define BCHP_DS_A_30_TRL_REG_START                         0x0225c400
+#define BCHP_DS_A_30_TRL_REG_END                           0x0225c6fc
+#define BCHP_DS_A_30_EQ_REG_START                          0x0225c800
+#define BCHP_DS_A_30_EQ_REG_END                            0x0225cbbc
+#define BCHP_DS_A_30_FECF_REG_START                        0x0225cc00
+#define BCHP_DS_A_30_FECF_REG_END                          0x0225cd7c
+#define BCHP_DS_A_30_FECB_REG_START                        0x0225ce00
+#define BCHP_DS_A_30_FECB_REG_END                          0x0225cebc
+#define BCHP_DS_A_30_FFT_REG_START                         0x0225d000
+#define BCHP_DS_A_30_FFT_REG_END                           0x0225d17c
+#define BCHP_DS_A_30_OI_REG_START                          0x0225d200
+#define BCHP_DS_A_30_OI_REG_END                            0x0225d23c
+#define BCHP_DS_A_30_IRQ_REG_START                         0x0225d300
+#define BCHP_DS_A_30_IRQ_REG_END                           0x0225d314
+#define BCHP_DS_A_31_ISW_MXR_REG_START                     0x0225e000
+#define BCHP_DS_A_31_ISW_MXR_REG_END                       0x0225e008
+#define BCHP_DS_A_31_ACI_AGF_REG_START                     0x0225e200
+#define BCHP_DS_A_31_ACI_AGF_REG_END                       0x0225e37c
+#define BCHP_DS_A_31_TRL_REG_START                         0x0225e400
+#define BCHP_DS_A_31_TRL_REG_END                           0x0225e6fc
+#define BCHP_DS_A_31_EQ_REG_START                          0x0225e800
+#define BCHP_DS_A_31_EQ_REG_END                            0x0225ebbc
+#define BCHP_DS_A_31_FECF_REG_START                        0x0225ec00
+#define BCHP_DS_A_31_FECF_REG_END                          0x0225ed7c
+#define BCHP_DS_A_31_FECB_REG_START                        0x0225ee00
+#define BCHP_DS_A_31_FECB_REG_END                          0x0225eebc
+#define BCHP_DS_A_31_FFT_REG_START                         0x0225f000
+#define BCHP_DS_A_31_FFT_REG_END                           0x0225f17c
+#define BCHP_DS_A_31_OI_REG_START                          0x0225f200
+#define BCHP_DS_A_31_OI_REG_END                            0x0225f23c
+#define BCHP_DS_A_31_IRQ_REG_START                         0x0225f300
+#define BCHP_DS_A_31_IRQ_REG_END                           0x0225f314
+#define BCHP_DS_A_32_ISW_MXR_REG_START                     0x02260000
+#define BCHP_DS_A_32_ISW_MXR_REG_END                       0x02260008
+#define BCHP_DS_A_32_ACI_AGF_REG_START                     0x02260200
+#define BCHP_DS_A_32_ACI_AGF_REG_END                       0x0226037c
+#define BCHP_DS_A_32_TRL_REG_START                         0x02260400
+#define BCHP_DS_A_32_TRL_REG_END                           0x022606fc
+#define BCHP_DS_A_32_EQ_REG_START                          0x02260800
+#define BCHP_DS_A_32_EQ_REG_END                            0x02260bbc
+#define BCHP_DS_A_32_FECF_REG_START                        0x02260c00
+#define BCHP_DS_A_32_FECF_REG_END                          0x02260d7c
+#define BCHP_DS_A_32_FECB_REG_START                        0x02260e00
+#define BCHP_DS_A_32_FECB_REG_END                          0x02260ebc
+#define BCHP_DS_A_32_FFT_REG_START                         0x02261000
+#define BCHP_DS_A_32_FFT_REG_END                           0x0226117c
+#define BCHP_DS_A_32_OI_REG_START                          0x02261200
+#define BCHP_DS_A_32_OI_REG_END                            0x0226123c
+#define BCHP_DS_A_32_IRQ_REG_START                         0x02261300
+#define BCHP_DS_A_32_IRQ_REG_END                           0x02261314
+#define BCHP_CMD_AFEC_GLOBAL_A_REG_START                   0x022c0000
+#define BCHP_CMD_AFEC_GLOBAL_A_REG_END                     0x022c0010
+#define BCHP_CMD_AFEC_A_REG_START                          0x022c0100
+#define BCHP_CMD_AFEC_A_REG_END                            0x022c0158
+#define BCHP_CMD_AFEC_STATS_A_REG_START                    0x022c2000
+#define BCHP_CMD_AFEC_STATS_A_REG_END                      0x022c3048
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_A_REG_START             0x022c4000
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_A_REG_END               0x022c402c
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_A_REG_START             0x022c4400
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_A_REG_END               0x022c442c
+#define BCHP_CMD_AFEC_GLOBAL_B_REG_START                   0x022d0000
+#define BCHP_CMD_AFEC_GLOBAL_B_REG_END                     0x022d0010
+#define BCHP_CMD_AFEC_B_REG_START                          0x022d0100
+#define BCHP_CMD_AFEC_B_REG_END                            0x022d0158
+#define BCHP_CMD_AFEC_STATS_B_REG_START                    0x022d2000
+#define BCHP_CMD_AFEC_STATS_B_REG_END                      0x022d3048
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_B_REG_START             0x022d4000
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_B_REG_END               0x022d402c
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_B_REG_START             0x022d4400
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_B_REG_END               0x022d442c
+#define BCHP_AIF_WB_CAB_CORE_REG_START                     0x022e0000
+#define BCHP_AIF_WB_CAB_CORE_REG_END                       0x022e04e4
+#define BCHP_AIF_WB_CAB_CORE_INTR2_REG_START               0x022e0800
+#define BCHP_AIF_WB_CAB_CORE_INTR2_REG_END                 0x022e082c
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_REG_START               0x022e1000
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_REG_END                 0x022e1138
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_INTR2_REG_START         0x022e1800
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_INTR2_REG_END           0x022e182c
+#define BCHP_AIF_WB_CAB_ANA_REG_START                      0x022e2000
+#define BCHP_AIF_WB_CAB_ANA_REG_END                        0x022e20a4
+#define BCHP_AIF_WB_CAB_DECFILT_REG_START                  0x022e3000
+#define BCHP_AIF_WB_CAB_DECFILT_REG_END                    0x022e302c
+#define BCHP_WOD_CPU0_PROG_MEM_A_REG_START                 0x02300000
+#define BCHP_WOD_CPU0_PROG_MEM_A_REG_END                   0x02307ffc
+#define BCHP_WOD_CPU0_DATA_MEM_A_REG_START                 0x02320000
+#define BCHP_WOD_CPU0_DATA_MEM_A_REG_END                   0x0232affc
+#define BCHP_WOD_CPU0_CORE_REGS_A_REG_START                0x02340000
+#define BCHP_WOD_CPU0_CORE_REGS_A_REG_END                  0x023400fc
+#define BCHP_WOD_CPU0_AUX_REGS_A_REG_START                 0x02342000
+#define BCHP_WOD_CPU0_AUX_REGS_A_REG_END                   0x02342a08
+#define BCHP_WOD_CPU0_CTRL_A_REG_START                     0x02344000
+#define BCHP_WOD_CPU0_CTRL_A_REG_END                       0x02344010
+#define BCHP_WOD_CPU0_L1_A_REG_START                       0x02344100
+#define BCHP_WOD_CPU0_L1_A_REG_END                         0x02344118
+#define BCHP_WOD_INTR_A_REG_START                          0x02346000
+#define BCHP_WOD_INTR_A_REG_END                            0x0234602c
+#define BCHP_WOD_INTR2_A_REG_START                         0x02346040
+#define BCHP_WOD_INTR2_A_REG_END                           0x0234606c
+#define BCHP_WOD_MEM_CTRL_A_REG_START                      0x02350000
+#define BCHP_WOD_MEM_CTRL_A_REG_END                        0x02350040
+#define BCHP_WOD_MEM_PROC0_A_REG_START                     0x02350100
+#define BCHP_WOD_MEM_PROC0_A_REG_END                       0x02350124
+#define BCHP_WOD_MEM_PROC1_A_REG_START                     0x02350140
+#define BCHP_WOD_MEM_PROC1_A_REG_END                       0x02350164
+#define BCHP_WOD_MEM_PROC2_A_REG_START                     0x02350180
+#define BCHP_WOD_MEM_PROC2_A_REG_END                       0x023501a4
+#define BCHP_WOD_MEM_PROC3_A_REG_START                     0x023501c0
+#define BCHP_WOD_MEM_PROC3_A_REG_END                       0x023501e4
+#define BCHP_WOD_MEM_PROC4_A_REG_START                     0x02350200
+#define BCHP_WOD_MEM_PROC4_A_REG_END                       0x02350224
+#define BCHP_WOD_MEM_PROC5_A_REG_START                     0x02350240
+#define BCHP_WOD_MEM_PROC5_A_REG_END                       0x02350264
+#define BCHP_WOD_MEM_PROC6_A_REG_START                     0x02350280
+#define BCHP_WOD_MEM_PROC6_A_REG_END                       0x023502a4
+#define BCHP_WOD_MEM_PROC7_A_REG_START                     0x023502c0
+#define BCHP_WOD_MEM_PROC7_A_REG_END                       0x023502e4
+#define BCHP_WOD_MEM_PROC8_A_REG_START                     0x02350300
+#define BCHP_WOD_MEM_PROC8_A_REG_END                       0x02350324
+#define BCHP_WOD_MEM_PROC9_A_REG_START                     0x02350340
+#define BCHP_WOD_MEM_PROC9_A_REG_END                       0x02350364
+#define BCHP_WOD_MEM_PROC10_A_REG_START                    0x02350380
+#define BCHP_WOD_MEM_PROC10_A_REG_END                      0x023503a4
+#define BCHP_WOD_MEM_PROC11_A_REG_START                    0x023503c0
+#define BCHP_WOD_MEM_PROC11_A_REG_END                      0x023503e4
+#define BCHP_WOD_MEM_PROC12_A_REG_START                    0x02350400
+#define BCHP_WOD_MEM_PROC12_A_REG_END                      0x02350424
+#define BCHP_WOD_MEM_PROC13_A_REG_START                    0x02350440
+#define BCHP_WOD_MEM_PROC13_A_REG_END                      0x02350464
+#define BCHP_WOD_MEM_PROC14_A_REG_START                    0x02350480
+#define BCHP_WOD_MEM_PROC14_A_REG_END                      0x023504a4
+#define BCHP_WOD_MEM_PROC15_A_REG_START                    0x023504c0
+#define BCHP_WOD_MEM_PROC15_A_REG_END                      0x023504e4
+#define BCHP_WOD_GLB_A_REG_START                           0x02350800
+#define BCHP_WOD_GLB_A_REG_END                             0x023508ac
+#define BCHP_WOD_CHAN_FE_A_REG_START                       0x02351000
+#define BCHP_WOD_CHAN_FE_A_REG_END                         0x02351114
+#define BCHP_WOD_OFDM_A_REG_START                          0x02352000
+#define BCHP_WOD_OFDM_A_REG_END                            0x02352438
+#define BCHP_WOD_LOCAL_A_REG_START                         0x02353000
+#define BCHP_WOD_LOCAL_A_REG_END                           0x023530dc
+#define BCHP_WOD_INTR_LOC_A_A_REG_START                    0x02354000
+#define BCHP_WOD_INTR_LOC_A_A_REG_END                      0x0235402c
+#define BCHP_WOD_INTR_LOC_B_A_REG_START                    0x02354040
+#define BCHP_WOD_INTR_LOC_B_A_REG_END                      0x0235406c
+#define BCHP_WOD_INTR_LOC_A2_A_REG_START                   0x02354080
+#define BCHP_WOD_INTR_LOC_A2_A_REG_END                     0x023540ac
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_A_REG_START             0x02358000
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_A_REG_END               0x02358ffc
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_A_REG_START              0x02359000
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_A_REG_END                0x02359ffc
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_A_REG_START       0x0235a000
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_A_REG_END         0x0235a3fc
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_A_REG_START          0x0235a400
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_A_REG_END            0x0235a4fc
+#define BCHP_WOD_TABLE_PP_CP_INDEX_A_REG_START             0x0235a500
+#define BCHP_WOD_TABLE_PP_CP_INDEX_A_REG_END               0x0235a5fc
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_A_REG_START            0x0235a600
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_A_REG_END              0x0235a69c
+#define BCHP_WOD_TABLE_FAVG_COEF_A_REG_START               0x0235a6c0
+#define BCHP_WOD_TABLE_FAVG_COEF_A_REG_END                 0x0235a6dc
+#define BCHP_WOD_DMEM0_A_REG_START                         0x02360000
+#define BCHP_WOD_DMEM0_A_REG_END                           0x02367ffc
+#define BCHP_WOD_DMEM1_A_REG_START                         0x02368000
+#define BCHP_WOD_DMEM1_A_REG_END                           0x0236fffc
+#define BCHP_WOD_DMEM2_A_REG_START                         0x02370000
+#define BCHP_WOD_DMEM2_A_REG_END                           0x02377ffc
+#define BCHP_WOD_DMEM3_A_REG_START                         0x02378000
+#define BCHP_WOD_DMEM3_A_REG_END                           0x0237fffc
+#define BCHP_WOD_CPU0_PROG_MEM_B_REG_START                 0x02380000
+#define BCHP_WOD_CPU0_PROG_MEM_B_REG_END                   0x02387ffc
+#define BCHP_WOD_CPU0_DATA_MEM_B_REG_START                 0x023a0000
+#define BCHP_WOD_CPU0_DATA_MEM_B_REG_END                   0x023aaffc
+#define BCHP_WOD_CPU0_CORE_REGS_B_REG_START                0x023c0000
+#define BCHP_WOD_CPU0_CORE_REGS_B_REG_END                  0x023c00fc
+#define BCHP_WOD_CPU0_AUX_REGS_B_REG_START                 0x023c2000
+#define BCHP_WOD_CPU0_AUX_REGS_B_REG_END                   0x023c2a08
+#define BCHP_WOD_CPU0_CTRL_B_REG_START                     0x023c4000
+#define BCHP_WOD_CPU0_CTRL_B_REG_END                       0x023c4010
+#define BCHP_WOD_CPU0_L1_B_REG_START                       0x023c4100
+#define BCHP_WOD_CPU0_L1_B_REG_END                         0x023c4118
+#define BCHP_WOD_INTR_B_REG_START                          0x023c6000
+#define BCHP_WOD_INTR_B_REG_END                            0x023c602c
+#define BCHP_WOD_INTR2_B_REG_START                         0x023c6040
+#define BCHP_WOD_INTR2_B_REG_END                           0x023c606c
+#define BCHP_WOD_MEM_CTRL_B_REG_START                      0x023d0000
+#define BCHP_WOD_MEM_CTRL_B_REG_END                        0x023d0040
+#define BCHP_WOD_MEM_PROC0_B_REG_START                     0x023d0100
+#define BCHP_WOD_MEM_PROC0_B_REG_END                       0x023d0124
+#define BCHP_WOD_MEM_PROC1_B_REG_START                     0x023d0140
+#define BCHP_WOD_MEM_PROC1_B_REG_END                       0x023d0164
+#define BCHP_WOD_MEM_PROC2_B_REG_START                     0x023d0180
+#define BCHP_WOD_MEM_PROC2_B_REG_END                       0x023d01a4
+#define BCHP_WOD_MEM_PROC3_B_REG_START                     0x023d01c0
+#define BCHP_WOD_MEM_PROC3_B_REG_END                       0x023d01e4
+#define BCHP_WOD_MEM_PROC4_B_REG_START                     0x023d0200
+#define BCHP_WOD_MEM_PROC4_B_REG_END                       0x023d0224
+#define BCHP_WOD_MEM_PROC5_B_REG_START                     0x023d0240
+#define BCHP_WOD_MEM_PROC5_B_REG_END                       0x023d0264
+#define BCHP_WOD_MEM_PROC6_B_REG_START                     0x023d0280
+#define BCHP_WOD_MEM_PROC6_B_REG_END                       0x023d02a4
+#define BCHP_WOD_MEM_PROC7_B_REG_START                     0x023d02c0
+#define BCHP_WOD_MEM_PROC7_B_REG_END                       0x023d02e4
+#define BCHP_WOD_MEM_PROC8_B_REG_START                     0x023d0300
+#define BCHP_WOD_MEM_PROC8_B_REG_END                       0x023d0324
+#define BCHP_WOD_MEM_PROC9_B_REG_START                     0x023d0340
+#define BCHP_WOD_MEM_PROC9_B_REG_END                       0x023d0364
+#define BCHP_WOD_MEM_PROC10_B_REG_START                    0x023d0380
+#define BCHP_WOD_MEM_PROC10_B_REG_END                      0x023d03a4
+#define BCHP_WOD_MEM_PROC11_B_REG_START                    0x023d03c0
+#define BCHP_WOD_MEM_PROC11_B_REG_END                      0x023d03e4
+#define BCHP_WOD_MEM_PROC12_B_REG_START                    0x023d0400
+#define BCHP_WOD_MEM_PROC12_B_REG_END                      0x023d0424
+#define BCHP_WOD_MEM_PROC13_B_REG_START                    0x023d0440
+#define BCHP_WOD_MEM_PROC13_B_REG_END                      0x023d0464
+#define BCHP_WOD_MEM_PROC14_B_REG_START                    0x023d0480
+#define BCHP_WOD_MEM_PROC14_B_REG_END                      0x023d04a4
+#define BCHP_WOD_MEM_PROC15_B_REG_START                    0x023d04c0
+#define BCHP_WOD_MEM_PROC15_B_REG_END                      0x023d04e4
+#define BCHP_WOD_GLB_B_REG_START                           0x023d0800
+#define BCHP_WOD_GLB_B_REG_END                             0x023d08ac
+#define BCHP_WOD_CHAN_FE_B_REG_START                       0x023d1000
+#define BCHP_WOD_CHAN_FE_B_REG_END                         0x023d1114
+#define BCHP_WOD_OFDM_B_REG_START                          0x023d2000
+#define BCHP_WOD_OFDM_B_REG_END                            0x023d2438
+#define BCHP_WOD_LOCAL_B_REG_START                         0x023d3000
+#define BCHP_WOD_LOCAL_B_REG_END                           0x023d30dc
+#define BCHP_WOD_INTR_LOC_A_B_REG_START                    0x023d4000
+#define BCHP_WOD_INTR_LOC_A_B_REG_END                      0x023d402c
+#define BCHP_WOD_INTR_LOC_B_B_REG_START                    0x023d4040
+#define BCHP_WOD_INTR_LOC_B_B_REG_END                      0x023d406c
+#define BCHP_WOD_INTR_LOC_A2_B_REG_START                   0x023d4080
+#define BCHP_WOD_INTR_LOC_A2_B_REG_END                     0x023d40ac
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_B_REG_START             0x023d8000
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_B_REG_END               0x023d8ffc
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_B_REG_START              0x023d9000
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_B_REG_END                0x023d9ffc
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_B_REG_START       0x023da000
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_B_REG_END         0x023da3fc
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_B_REG_START          0x023da400
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_B_REG_END            0x023da4fc
+#define BCHP_WOD_TABLE_PP_CP_INDEX_B_REG_START             0x023da500
+#define BCHP_WOD_TABLE_PP_CP_INDEX_B_REG_END               0x023da5fc
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_B_REG_START            0x023da600
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_B_REG_END              0x023da69c
+#define BCHP_WOD_TABLE_FAVG_COEF_B_REG_START               0x023da6c0
+#define BCHP_WOD_TABLE_FAVG_COEF_B_REG_END                 0x023da6dc
+#define BCHP_WOD_DMEM0_B_REG_START                         0x023e0000
+#define BCHP_WOD_DMEM0_B_REG_END                           0x023e7ffc
+#define BCHP_WOD_DMEM1_B_REG_START                         0x023e8000
+#define BCHP_WOD_DMEM1_B_REG_END                           0x023efffc
+#define BCHP_WOD_DMEM2_B_REG_START                         0x023f0000
+#define BCHP_WOD_DMEM2_B_REG_END                           0x023f7ffc
+#define BCHP_WOD_DMEM3_B_REG_START                         0x023f8000
+#define BCHP_WOD_DMEM3_B_REG_END                           0x023ffffc
+#define BCHP_BaseReserved_EMC_REG_START                    0x03600000
+#define BCHP_BaseReserved_EMC_REG_END                      0x03600000
+#define BCHP_Control_EMC_REG_START                         0x03601000
+#define BCHP_Control_EMC_REG_END                           0x036010fc
+#define BCHP_OutgoingMessageFIFO_EMC_REG_START             0x03601100
+#define BCHP_OutgoingMessageFIFO_EMC_REG_END               0x0360117c
+#define BCHP_IncomingMessageFIFO_EMC_REG_START             0x03601200
+#define BCHP_IncomingMessageFIFO_EMC_REG_END               0x0360127c
+#define BCHP_DMA0_EMC_REG_START                            0x03601300
+#define BCHP_DMA0_EMC_REG_END                              0x0360131c
+#define BCHP_DMA1_EMC_REG_START                            0x03601320
+#define BCHP_DMA1_EMC_REG_END                              0x0360133c
+#define BCHP_DMAHI0_EMC_REG_START                          0x03601340
+#define BCHP_DMAHI0_EMC_REG_END                            0x0360134c
+#define BCHP_DMAHI1_EMC_REG_START                          0x03601350
+#define BCHP_DMAHI1_EMC_REG_END                            0x0360135c
+#define BCHP_Token_EMC_REG_START                           0x03601400
+#define BCHP_Token_EMC_REG_END                             0x03601420
+#define BCHP_PerfPower_EMC_REG_START                       0x03601600
+#define BCHP_PerfPower_EMC_REG_END                         0x03601640
+#define BCHP_MessageID_EMC_REG_START                       0x03601700
+#define BCHP_MessageID_EMC_REG_END                         0x0360177c
+#define BCHP_HWCounters_EMC_REG_START                      0x03601900
+#define BCHP_HWCounters_EMC_REG_END                        0x03601944
+#define BCHP_DQM_0_31_EMC_REG_START                        0x03601c00
+#define BCHP_DQM_0_31_EMC_REG_END                          0x03601c48
+#define BCHP_DQM_32_63_EMC_REG_START                       0x03601d00
+#define BCHP_DQM_32_63_EMC_REG_END                         0x03601d48
+#define BCHP_QUEUE_TIMER_EMC_REG_START                     0x03602000
+#define BCHP_QUEUE_TIMER_EMC_REG_END                       0x036021fc
+#define BCHP_QUEUE_STATUS_0_31_EMC_REG_START               0x03602800
+#define BCHP_QUEUE_STATUS_0_31_EMC_REG_END                 0x0360287c
+#define BCHP_QUEUE_STATUS_32_63_EMC_REG_START              0x03602900
+#define BCHP_QUEUE_STATUS_32_63_EMC_REG_END                0x0360297c
+#define BCHP_QUEUE_MIB_0_31_EMC_REG_START                  0x03603000
+#define BCHP_QUEUE_MIB_0_31_EMC_REG_END                    0x0360317c
+#define BCHP_QUEUE_MIB_32_63_EMC_REG_START                 0x03603200
+#define BCHP_QUEUE_MIB_32_63_EMC_REG_END                   0x0360337c
+#define BCHP_QUEUE_0_CNTRL_EMC_REG_START                   0x03604000
+#define BCHP_QUEUE_0_CNTRL_EMC_REG_END                     0x0360400c
+#define BCHP_QUEUE_1_CNTRL_EMC_REG_START                   0x03604010
+#define BCHP_QUEUE_1_CNTRL_EMC_REG_END                     0x0360401c
+#define BCHP_QUEUE_2_CNTRL_EMC_REG_START                   0x03604020
+#define BCHP_QUEUE_2_CNTRL_EMC_REG_END                     0x0360402c
+#define BCHP_QUEUE_3_CNTRL_EMC_REG_START                   0x03604030
+#define BCHP_QUEUE_3_CNTRL_EMC_REG_END                     0x0360403c
+#define BCHP_QUEUE_4_CNTRL_EMC_REG_START                   0x03604040
+#define BCHP_QUEUE_4_CNTRL_EMC_REG_END                     0x0360404c
+#define BCHP_QUEUE_5_CNTRL_EMC_REG_START                   0x03604050
+#define BCHP_QUEUE_5_CNTRL_EMC_REG_END                     0x0360405c
+#define BCHP_QUEUE_6_CNTRL_EMC_REG_START                   0x03604060
+#define BCHP_QUEUE_6_CNTRL_EMC_REG_END                     0x0360406c
+#define BCHP_QUEUE_7_CNTRL_EMC_REG_START                   0x03604070
+#define BCHP_QUEUE_7_CNTRL_EMC_REG_END                     0x0360407c
+#define BCHP_QUEUE_8_CNTRL_EMC_REG_START                   0x03604080
+#define BCHP_QUEUE_8_CNTRL_EMC_REG_END                     0x0360408c
+#define BCHP_QUEUE_9_CNTRL_EMC_REG_START                   0x03604090
+#define BCHP_QUEUE_9_CNTRL_EMC_REG_END                     0x0360409c
+#define BCHP_QUEUE_10_CNTRL_EMC_REG_START                  0x036040a0
+#define BCHP_QUEUE_10_CNTRL_EMC_REG_END                    0x036040ac
+#define BCHP_QUEUE_11_CNTRL_EMC_REG_START                  0x036040b0
+#define BCHP_QUEUE_11_CNTRL_EMC_REG_END                    0x036040bc
+#define BCHP_QUEUE_12_CNTRL_EMC_REG_START                  0x036040c0
+#define BCHP_QUEUE_12_CNTRL_EMC_REG_END                    0x036040cc
+#define BCHP_QUEUE_13_CNTRL_EMC_REG_START                  0x036040d0
+#define BCHP_QUEUE_13_CNTRL_EMC_REG_END                    0x036040dc
+#define BCHP_QUEUE_14_CNTRL_EMC_REG_START                  0x036040e0
+#define BCHP_QUEUE_14_CNTRL_EMC_REG_END                    0x036040ec
+#define BCHP_QUEUE_15_CNTRL_EMC_REG_START                  0x036040f0
+#define BCHP_QUEUE_15_CNTRL_EMC_REG_END                    0x036040fc
+#define BCHP_QUEUE_16_CNTRL_EMC_REG_START                  0x03604100
+#define BCHP_QUEUE_16_CNTRL_EMC_REG_END                    0x0360410c
+#define BCHP_QUEUE_17_CNTRL_EMC_REG_START                  0x03604110
+#define BCHP_QUEUE_17_CNTRL_EMC_REG_END                    0x0360411c
+#define BCHP_QUEUE_18_CNTRL_EMC_REG_START                  0x03604120
+#define BCHP_QUEUE_18_CNTRL_EMC_REG_END                    0x0360412c
+#define BCHP_QUEUE_19_CNTRL_EMC_REG_START                  0x03604130
+#define BCHP_QUEUE_19_CNTRL_EMC_REG_END                    0x0360413c
+#define BCHP_QUEUE_20_CNTRL_EMC_REG_START                  0x03604140
+#define BCHP_QUEUE_20_CNTRL_EMC_REG_END                    0x0360414c
+#define BCHP_QUEUE_21_CNTRL_EMC_REG_START                  0x03604150
+#define BCHP_QUEUE_21_CNTRL_EMC_REG_END                    0x0360415c
+#define BCHP_QUEUE_22_CNTRL_EMC_REG_START                  0x03604160
+#define BCHP_QUEUE_22_CNTRL_EMC_REG_END                    0x0360416c
+#define BCHP_QUEUE_23_CNTRL_EMC_REG_START                  0x03604170
+#define BCHP_QUEUE_23_CNTRL_EMC_REG_END                    0x0360417c
+#define BCHP_QUEUE_24_CNTRL_EMC_REG_START                  0x03604180
+#define BCHP_QUEUE_24_CNTRL_EMC_REG_END                    0x0360418c
+#define BCHP_QUEUE_25_CNTRL_EMC_REG_START                  0x03604190
+#define BCHP_QUEUE_25_CNTRL_EMC_REG_END                    0x0360419c
+#define BCHP_QUEUE_26_CNTRL_EMC_REG_START                  0x036041a0
+#define BCHP_QUEUE_26_CNTRL_EMC_REG_END                    0x036041ac
+#define BCHP_QUEUE_27_CNTRL_EMC_REG_START                  0x036041b0
+#define BCHP_QUEUE_27_CNTRL_EMC_REG_END                    0x036041bc
+#define BCHP_QUEUE_28_CNTRL_EMC_REG_START                  0x036041c0
+#define BCHP_QUEUE_28_CNTRL_EMC_REG_END                    0x036041cc
+#define BCHP_QUEUE_29_CNTRL_EMC_REG_START                  0x036041d0
+#define BCHP_QUEUE_29_CNTRL_EMC_REG_END                    0x036041dc
+#define BCHP_QUEUE_30_CNTRL_EMC_REG_START                  0x036041e0
+#define BCHP_QUEUE_30_CNTRL_EMC_REG_END                    0x036041ec
+#define BCHP_QUEUE_31_CNTRL_EMC_REG_START                  0x036041f0
+#define BCHP_QUEUE_31_CNTRL_EMC_REG_END                    0x036041fc
+#define BCHP_QUEUE_32_CNTRL_EMC_REG_START                  0x03604200
+#define BCHP_QUEUE_32_CNTRL_EMC_REG_END                    0x0360420c
+#define BCHP_QUEUE_33_CNTRL_EMC_REG_START                  0x03604210
+#define BCHP_QUEUE_33_CNTRL_EMC_REG_END                    0x0360421c
+#define BCHP_QUEUE_34_CNTRL_EMC_REG_START                  0x03604220
+#define BCHP_QUEUE_34_CNTRL_EMC_REG_END                    0x0360422c
+#define BCHP_QUEUE_35_CNTRL_EMC_REG_START                  0x03604230
+#define BCHP_QUEUE_35_CNTRL_EMC_REG_END                    0x0360423c
+#define BCHP_QUEUE_36_CNTRL_EMC_REG_START                  0x03604240
+#define BCHP_QUEUE_36_CNTRL_EMC_REG_END                    0x0360424c
+#define BCHP_QUEUE_37_CNTRL_EMC_REG_START                  0x03604250
+#define BCHP_QUEUE_37_CNTRL_EMC_REG_END                    0x0360425c
+#define BCHP_QUEUE_38_CNTRL_EMC_REG_START                  0x03604260
+#define BCHP_QUEUE_38_CNTRL_EMC_REG_END                    0x0360426c
+#define BCHP_QUEUE_39_CNTRL_EMC_REG_START                  0x03604270
+#define BCHP_QUEUE_39_CNTRL_EMC_REG_END                    0x0360427c
+#define BCHP_QUEUE_40_CNTRL_EMC_REG_START                  0x03604280
+#define BCHP_QUEUE_40_CNTRL_EMC_REG_END                    0x0360428c
+#define BCHP_QUEUE_41_CNTRL_EMC_REG_START                  0x03604290
+#define BCHP_QUEUE_41_CNTRL_EMC_REG_END                    0x0360429c
+#define BCHP_QUEUE_42_CNTRL_EMC_REG_START                  0x036042a0
+#define BCHP_QUEUE_42_CNTRL_EMC_REG_END                    0x036042ac
+#define BCHP_QUEUE_43_CNTRL_EMC_REG_START                  0x036042b0
+#define BCHP_QUEUE_43_CNTRL_EMC_REG_END                    0x036042bc
+#define BCHP_QUEUE_44_CNTRL_EMC_REG_START                  0x036042c0
+#define BCHP_QUEUE_44_CNTRL_EMC_REG_END                    0x036042cc
+#define BCHP_QUEUE_45_CNTRL_EMC_REG_START                  0x036042d0
+#define BCHP_QUEUE_45_CNTRL_EMC_REG_END                    0x036042dc
+#define BCHP_QUEUE_46_CNTRL_EMC_REG_START                  0x036042e0
+#define BCHP_QUEUE_46_CNTRL_EMC_REG_END                    0x036042ec
+#define BCHP_QUEUE_47_CNTRL_EMC_REG_START                  0x036042f0
+#define BCHP_QUEUE_47_CNTRL_EMC_REG_END                    0x036042fc
+#define BCHP_QUEUE_48_CNTRL_EMC_REG_START                  0x03604300
+#define BCHP_QUEUE_48_CNTRL_EMC_REG_END                    0x0360430c
+#define BCHP_QUEUE_49_CNTRL_EMC_REG_START                  0x03604310
+#define BCHP_QUEUE_49_CNTRL_EMC_REG_END                    0x0360431c
+#define BCHP_QUEUE_50_CNTRL_EMC_REG_START                  0x03604320
+#define BCHP_QUEUE_50_CNTRL_EMC_REG_END                    0x0360432c
+#define BCHP_QUEUE_51_CNTRL_EMC_REG_START                  0x03604330
+#define BCHP_QUEUE_51_CNTRL_EMC_REG_END                    0x0360433c
+#define BCHP_QUEUE_52_CNTRL_EMC_REG_START                  0x03604340
+#define BCHP_QUEUE_52_CNTRL_EMC_REG_END                    0x0360434c
+#define BCHP_QUEUE_53_CNTRL_EMC_REG_START                  0x03604350
+#define BCHP_QUEUE_53_CNTRL_EMC_REG_END                    0x0360435c
+#define BCHP_QUEUE_54_CNTRL_EMC_REG_START                  0x03604360
+#define BCHP_QUEUE_54_CNTRL_EMC_REG_END                    0x0360436c
+#define BCHP_QUEUE_55_CNTRL_EMC_REG_START                  0x03604370
+#define BCHP_QUEUE_55_CNTRL_EMC_REG_END                    0x0360437c
+#define BCHP_QUEUE_56_CNTRL_EMC_REG_START                  0x03604380
+#define BCHP_QUEUE_56_CNTRL_EMC_REG_END                    0x0360438c
+#define BCHP_QUEUE_57_CNTRL_EMC_REG_START                  0x03604390
+#define BCHP_QUEUE_57_CNTRL_EMC_REG_END                    0x0360439c
+#define BCHP_QUEUE_58_CNTRL_EMC_REG_START                  0x036043a0
+#define BCHP_QUEUE_58_CNTRL_EMC_REG_END                    0x036043ac
+#define BCHP_QUEUE_59_CNTRL_EMC_REG_START                  0x036043b0
+#define BCHP_QUEUE_59_CNTRL_EMC_REG_END                    0x036043bc
+#define BCHP_QUEUE_60_CNTRL_EMC_REG_START                  0x036043c0
+#define BCHP_QUEUE_60_CNTRL_EMC_REG_END                    0x036043cc
+#define BCHP_QUEUE_61_CNTRL_EMC_REG_START                  0x036043d0
+#define BCHP_QUEUE_61_CNTRL_EMC_REG_END                    0x036043dc
+#define BCHP_QUEUE_62_CNTRL_EMC_REG_START                  0x036043e0
+#define BCHP_QUEUE_62_CNTRL_EMC_REG_END                    0x036043ec
+#define BCHP_QUEUE_63_CNTRL_EMC_REG_START                  0x036043f0
+#define BCHP_QUEUE_63_CNTRL_EMC_REG_END                    0x036043fc
+#define BCHP_QUEUE_0_DATA_EMC_REG_START                    0x03605000
+#define BCHP_QUEUE_0_DATA_EMC_REG_END                      0x0360500c
+#define BCHP_QUEUE_1_DATA_EMC_REG_START                    0x03605010
+#define BCHP_QUEUE_1_DATA_EMC_REG_END                      0x0360501c
+#define BCHP_QUEUE_2_DATA_EMC_REG_START                    0x03605020
+#define BCHP_QUEUE_2_DATA_EMC_REG_END                      0x0360502c
+#define BCHP_QUEUE_3_DATA_EMC_REG_START                    0x03605030
+#define BCHP_QUEUE_3_DATA_EMC_REG_END                      0x0360503c
+#define BCHP_QUEUE_4_DATA_EMC_REG_START                    0x03605040
+#define BCHP_QUEUE_4_DATA_EMC_REG_END                      0x0360504c
+#define BCHP_QUEUE_5_DATA_EMC_REG_START                    0x03605050
+#define BCHP_QUEUE_5_DATA_EMC_REG_END                      0x0360505c
+#define BCHP_QUEUE_6_DATA_EMC_REG_START                    0x03605060
+#define BCHP_QUEUE_6_DATA_EMC_REG_END                      0x0360506c
+#define BCHP_QUEUE_7_DATA_EMC_REG_START                    0x03605070
+#define BCHP_QUEUE_7_DATA_EMC_REG_END                      0x0360507c
+#define BCHP_QUEUE_8_DATA_EMC_REG_START                    0x03605080
+#define BCHP_QUEUE_8_DATA_EMC_REG_END                      0x0360508c
+#define BCHP_QUEUE_9_DATA_EMC_REG_START                    0x03605090
+#define BCHP_QUEUE_9_DATA_EMC_REG_END                      0x0360509c
+#define BCHP_QUEUE_10_DATA_EMC_REG_START                   0x036050a0
+#define BCHP_QUEUE_10_DATA_EMC_REG_END                     0x036050ac
+#define BCHP_QUEUE_11_DATA_EMC_REG_START                   0x036050b0
+#define BCHP_QUEUE_11_DATA_EMC_REG_END                     0x036050bc
+#define BCHP_QUEUE_12_DATA_EMC_REG_START                   0x036050c0
+#define BCHP_QUEUE_12_DATA_EMC_REG_END                     0x036050cc
+#define BCHP_QUEUE_13_DATA_EMC_REG_START                   0x036050d0
+#define BCHP_QUEUE_13_DATA_EMC_REG_END                     0x036050dc
+#define BCHP_QUEUE_14_DATA_EMC_REG_START                   0x036050e0
+#define BCHP_QUEUE_14_DATA_EMC_REG_END                     0x036050ec
+#define BCHP_QUEUE_15_DATA_EMC_REG_START                   0x036050f0
+#define BCHP_QUEUE_15_DATA_EMC_REG_END                     0x036050fc
+#define BCHP_QUEUE_16_DATA_EMC_REG_START                   0x03605100
+#define BCHP_QUEUE_16_DATA_EMC_REG_END                     0x0360510c
+#define BCHP_QUEUE_17_DATA_EMC_REG_START                   0x03605110
+#define BCHP_QUEUE_17_DATA_EMC_REG_END                     0x0360511c
+#define BCHP_QUEUE_18_DATA_EMC_REG_START                   0x03605120
+#define BCHP_QUEUE_18_DATA_EMC_REG_END                     0x0360512c
+#define BCHP_QUEUE_19_DATA_EMC_REG_START                   0x03605130
+#define BCHP_QUEUE_19_DATA_EMC_REG_END                     0x0360513c
+#define BCHP_QUEUE_20_DATA_EMC_REG_START                   0x03605140
+#define BCHP_QUEUE_20_DATA_EMC_REG_END                     0x0360514c
+#define BCHP_QUEUE_21_DATA_EMC_REG_START                   0x03605150
+#define BCHP_QUEUE_21_DATA_EMC_REG_END                     0x0360515c
+#define BCHP_QUEUE_22_DATA_EMC_REG_START                   0x03605160
+#define BCHP_QUEUE_22_DATA_EMC_REG_END                     0x0360516c
+#define BCHP_QUEUE_23_DATA_EMC_REG_START                   0x03605170
+#define BCHP_QUEUE_23_DATA_EMC_REG_END                     0x0360517c
+#define BCHP_QUEUE_24_DATA_EMC_REG_START                   0x03605180
+#define BCHP_QUEUE_24_DATA_EMC_REG_END                     0x0360518c
+#define BCHP_QUEUE_25_DATA_EMC_REG_START                   0x03605190
+#define BCHP_QUEUE_25_DATA_EMC_REG_END                     0x0360519c
+#define BCHP_QUEUE_26_DATA_EMC_REG_START                   0x036051a0
+#define BCHP_QUEUE_26_DATA_EMC_REG_END                     0x036051ac
+#define BCHP_QUEUE_27_DATA_EMC_REG_START                   0x036051b0
+#define BCHP_QUEUE_27_DATA_EMC_REG_END                     0x036051bc
+#define BCHP_QUEUE_28_DATA_EMC_REG_START                   0x036051c0
+#define BCHP_QUEUE_28_DATA_EMC_REG_END                     0x036051cc
+#define BCHP_QUEUE_29_DATA_EMC_REG_START                   0x036051d0
+#define BCHP_QUEUE_29_DATA_EMC_REG_END                     0x036051dc
+#define BCHP_QUEUE_30_DATA_EMC_REG_START                   0x036051e0
+#define BCHP_QUEUE_30_DATA_EMC_REG_END                     0x036051ec
+#define BCHP_QUEUE_31_DATA_EMC_REG_START                   0x036051f0
+#define BCHP_QUEUE_31_DATA_EMC_REG_END                     0x036051fc
+#define BCHP_QUEUE_32_DATA_EMC_REG_START                   0x03605200
+#define BCHP_QUEUE_32_DATA_EMC_REG_END                     0x0360520c
+#define BCHP_QUEUE_33_DATA_EMC_REG_START                   0x03605210
+#define BCHP_QUEUE_33_DATA_EMC_REG_END                     0x0360521c
+#define BCHP_QUEUE_34_DATA_EMC_REG_START                   0x03605220
+#define BCHP_QUEUE_34_DATA_EMC_REG_END                     0x0360522c
+#define BCHP_QUEUE_35_DATA_EMC_REG_START                   0x03605230
+#define BCHP_QUEUE_35_DATA_EMC_REG_END                     0x0360523c
+#define BCHP_QUEUE_36_DATA_EMC_REG_START                   0x03605240
+#define BCHP_QUEUE_36_DATA_EMC_REG_END                     0x0360524c
+#define BCHP_QUEUE_37_DATA_EMC_REG_START                   0x03605250
+#define BCHP_QUEUE_37_DATA_EMC_REG_END                     0x0360525c
+#define BCHP_QUEUE_38_DATA_EMC_REG_START                   0x03605260
+#define BCHP_QUEUE_38_DATA_EMC_REG_END                     0x0360526c
+#define BCHP_QUEUE_39_DATA_EMC_REG_START                   0x03605270
+#define BCHP_QUEUE_39_DATA_EMC_REG_END                     0x0360527c
+#define BCHP_QUEUE_40_DATA_EMC_REG_START                   0x03605280
+#define BCHP_QUEUE_40_DATA_EMC_REG_END                     0x0360528c
+#define BCHP_QUEUE_41_DATA_EMC_REG_START                   0x03605290
+#define BCHP_QUEUE_41_DATA_EMC_REG_END                     0x0360529c
+#define BCHP_QUEUE_42_DATA_EMC_REG_START                   0x036052a0
+#define BCHP_QUEUE_42_DATA_EMC_REG_END                     0x036052ac
+#define BCHP_QUEUE_43_DATA_EMC_REG_START                   0x036052b0
+#define BCHP_QUEUE_43_DATA_EMC_REG_END                     0x036052bc
+#define BCHP_QUEUE_44_DATA_EMC_REG_START                   0x036052c0
+#define BCHP_QUEUE_44_DATA_EMC_REG_END                     0x036052cc
+#define BCHP_QUEUE_45_DATA_EMC_REG_START                   0x036052d0
+#define BCHP_QUEUE_45_DATA_EMC_REG_END                     0x036052dc
+#define BCHP_QUEUE_46_DATA_EMC_REG_START                   0x036052e0
+#define BCHP_QUEUE_46_DATA_EMC_REG_END                     0x036052ec
+#define BCHP_QUEUE_47_DATA_EMC_REG_START                   0x036052f0
+#define BCHP_QUEUE_47_DATA_EMC_REG_END                     0x036052fc
+#define BCHP_QUEUE_48_DATA_EMC_REG_START                   0x03605300
+#define BCHP_QUEUE_48_DATA_EMC_REG_END                     0x0360530c
+#define BCHP_QUEUE_49_DATA_EMC_REG_START                   0x03605310
+#define BCHP_QUEUE_49_DATA_EMC_REG_END                     0x0360531c
+#define BCHP_QUEUE_50_DATA_EMC_REG_START                   0x03605320
+#define BCHP_QUEUE_50_DATA_EMC_REG_END                     0x0360532c
+#define BCHP_QUEUE_51_DATA_EMC_REG_START                   0x03605330
+#define BCHP_QUEUE_51_DATA_EMC_REG_END                     0x0360533c
+#define BCHP_QUEUE_52_DATA_EMC_REG_START                   0x03605340
+#define BCHP_QUEUE_52_DATA_EMC_REG_END                     0x0360534c
+#define BCHP_QUEUE_53_DATA_EMC_REG_START                   0x03605350
+#define BCHP_QUEUE_53_DATA_EMC_REG_END                     0x0360535c
+#define BCHP_QUEUE_54_DATA_EMC_REG_START                   0x03605360
+#define BCHP_QUEUE_54_DATA_EMC_REG_END                     0x0360536c
+#define BCHP_QUEUE_55_DATA_EMC_REG_START                   0x03605370
+#define BCHP_QUEUE_55_DATA_EMC_REG_END                     0x0360537c
+#define BCHP_QUEUE_56_DATA_EMC_REG_START                   0x03605380
+#define BCHP_QUEUE_56_DATA_EMC_REG_END                     0x0360538c
+#define BCHP_QUEUE_57_DATA_EMC_REG_START                   0x03605390
+#define BCHP_QUEUE_57_DATA_EMC_REG_END                     0x0360539c
+#define BCHP_QUEUE_58_DATA_EMC_REG_START                   0x036053a0
+#define BCHP_QUEUE_58_DATA_EMC_REG_END                     0x036053ac
+#define BCHP_QUEUE_59_DATA_EMC_REG_START                   0x036053b0
+#define BCHP_QUEUE_59_DATA_EMC_REG_END                     0x036053bc
+#define BCHP_QUEUE_60_DATA_EMC_REG_START                   0x036053c0
+#define BCHP_QUEUE_60_DATA_EMC_REG_END                     0x036053cc
+#define BCHP_QUEUE_61_DATA_EMC_REG_START                   0x036053d0
+#define BCHP_QUEUE_61_DATA_EMC_REG_END                     0x036053dc
+#define BCHP_QUEUE_62_DATA_EMC_REG_START                   0x036053e0
+#define BCHP_QUEUE_62_DATA_EMC_REG_END                     0x036053ec
+#define BCHP_QUEUE_63_DATA_EMC_REG_START                   0x036053f0
+#define BCHP_QUEUE_63_DATA_EMC_REG_END                     0x036053fc
+#define BCHP_OL_DQM_EMC_REG_START                          0x03606c00
+#define BCHP_OL_DQM_EMC_REG_END                            0x03606c30
+#define BCHP_OL_QUEUE_STATUS_EMC_REG_START                 0x03607400
+#define BCHP_OL_QUEUE_STATUS_EMC_REG_END                   0x0360747c
+#define BCHP_OL_QUEUE_0_CNTRL_EMC_REG_START                0x03608000
+#define BCHP_OL_QUEUE_0_CNTRL_EMC_REG_END                  0x0360801c
+#define BCHP_OL_QUEUE_1_CNTRL_EMC_REG_START                0x03608020
+#define BCHP_OL_QUEUE_1_CNTRL_EMC_REG_END                  0x0360803c
+#define BCHP_OL_QUEUE_2_CNTRL_EMC_REG_START                0x03608040
+#define BCHP_OL_QUEUE_2_CNTRL_EMC_REG_END                  0x0360805c
+#define BCHP_OL_QUEUE_3_CNTRL_EMC_REG_START                0x03608060
+#define BCHP_OL_QUEUE_3_CNTRL_EMC_REG_END                  0x0360807c
+#define BCHP_OL_QUEUE_4_CNTRL_EMC_REG_START                0x03608080
+#define BCHP_OL_QUEUE_4_CNTRL_EMC_REG_END                  0x0360809c
+#define BCHP_OL_QUEUE_5_CNTRL_EMC_REG_START                0x036080a0
+#define BCHP_OL_QUEUE_5_CNTRL_EMC_REG_END                  0x036080bc
+#define BCHP_OL_QUEUE_6_CNTRL_EMC_REG_START                0x036080c0
+#define BCHP_OL_QUEUE_6_CNTRL_EMC_REG_END                  0x036080dc
+#define BCHP_OL_QUEUE_7_CNTRL_EMC_REG_START                0x036080e0
+#define BCHP_OL_QUEUE_7_CNTRL_EMC_REG_END                  0x036080fc
+#define BCHP_OL_QUEUE_8_CNTRL_EMC_REG_START                0x03608100
+#define BCHP_OL_QUEUE_8_CNTRL_EMC_REG_END                  0x0360811c
+#define BCHP_OL_QUEUE_9_CNTRL_EMC_REG_START                0x03608120
+#define BCHP_OL_QUEUE_9_CNTRL_EMC_REG_END                  0x0360813c
+#define BCHP_OL_QUEUE_10_CNTRL_EMC_REG_START               0x03608140
+#define BCHP_OL_QUEUE_10_CNTRL_EMC_REG_END                 0x0360815c
+#define BCHP_OL_QUEUE_11_CNTRL_EMC_REG_START               0x03608160
+#define BCHP_OL_QUEUE_11_CNTRL_EMC_REG_END                 0x0360817c
+#define BCHP_OL_QUEUE_12_CNTRL_EMC_REG_START               0x03608180
+#define BCHP_OL_QUEUE_12_CNTRL_EMC_REG_END                 0x0360819c
+#define BCHP_OL_QUEUE_13_CNTRL_EMC_REG_START               0x036081a0
+#define BCHP_OL_QUEUE_13_CNTRL_EMC_REG_END                 0x036081bc
+#define BCHP_OL_QUEUE_14_CNTRL_EMC_REG_START               0x036081c0
+#define BCHP_OL_QUEUE_14_CNTRL_EMC_REG_END                 0x036081dc
+#define BCHP_OL_QUEUE_15_CNTRL_EMC_REG_START               0x036081e0
+#define BCHP_OL_QUEUE_15_CNTRL_EMC_REG_END                 0x036081fc
+#define BCHP_OL_QUEUE_16_CNTRL_EMC_REG_START               0x03608200
+#define BCHP_OL_QUEUE_16_CNTRL_EMC_REG_END                 0x0360821c
+#define BCHP_OL_QUEUE_17_CNTRL_EMC_REG_START               0x03608220
+#define BCHP_OL_QUEUE_17_CNTRL_EMC_REG_END                 0x0360823c
+#define BCHP_OL_QUEUE_18_CNTRL_EMC_REG_START               0x03608240
+#define BCHP_OL_QUEUE_18_CNTRL_EMC_REG_END                 0x0360825c
+#define BCHP_OL_QUEUE_19_CNTRL_EMC_REG_START               0x03608260
+#define BCHP_OL_QUEUE_19_CNTRL_EMC_REG_END                 0x0360827c
+#define BCHP_OL_QUEUE_20_CNTRL_EMC_REG_START               0x03608280
+#define BCHP_OL_QUEUE_20_CNTRL_EMC_REG_END                 0x0360829c
+#define BCHP_OL_QUEUE_21_CNTRL_EMC_REG_START               0x036082a0
+#define BCHP_OL_QUEUE_21_CNTRL_EMC_REG_END                 0x036082bc
+#define BCHP_OL_QUEUE_22_CNTRL_EMC_REG_START               0x036082c0
+#define BCHP_OL_QUEUE_22_CNTRL_EMC_REG_END                 0x036082dc
+#define BCHP_OL_QUEUE_23_CNTRL_EMC_REG_START               0x036082e0
+#define BCHP_OL_QUEUE_23_CNTRL_EMC_REG_END                 0x036082fc
+#define BCHP_OL_QUEUE_24_CNTRL_EMC_REG_START               0x03608300
+#define BCHP_OL_QUEUE_24_CNTRL_EMC_REG_END                 0x0360831c
+#define BCHP_OL_QUEUE_25_CNTRL_EMC_REG_START               0x03608320
+#define BCHP_OL_QUEUE_25_CNTRL_EMC_REG_END                 0x0360833c
+#define BCHP_OL_QUEUE_26_CNTRL_EMC_REG_START               0x03608340
+#define BCHP_OL_QUEUE_26_CNTRL_EMC_REG_END                 0x0360835c
+#define BCHP_OL_QUEUE_27_CNTRL_EMC_REG_START               0x03608360
+#define BCHP_OL_QUEUE_27_CNTRL_EMC_REG_END                 0x0360837c
+#define BCHP_OL_QUEUE_28_CNTRL_EMC_REG_START               0x03608380
+#define BCHP_OL_QUEUE_28_CNTRL_EMC_REG_END                 0x0360839c
+#define BCHP_OL_QUEUE_29_CNTRL_EMC_REG_START               0x036083a0
+#define BCHP_OL_QUEUE_29_CNTRL_EMC_REG_END                 0x036083bc
+#define BCHP_OL_QUEUE_30_CNTRL_EMC_REG_START               0x036083c0
+#define BCHP_OL_QUEUE_30_CNTRL_EMC_REG_END                 0x036083dc
+#define BCHP_OL_QUEUE_31_CNTRL_EMC_REG_START               0x036083e0
+#define BCHP_OL_QUEUE_31_CNTRL_EMC_REG_END                 0x036083fc
+#define BCHP_OL_QUEUE_0_DATA_EMC_REG_START                 0x03609000
+#define BCHP_OL_QUEUE_0_DATA_EMC_REG_END                   0x0360901c
+#define BCHP_OL_QUEUE_1_DATA_EMC_REG_START                 0x03609020
+#define BCHP_OL_QUEUE_1_DATA_EMC_REG_END                   0x0360903c
+#define BCHP_OL_QUEUE_2_DATA_EMC_REG_START                 0x03609040
+#define BCHP_OL_QUEUE_2_DATA_EMC_REG_END                   0x0360905c
+#define BCHP_OL_QUEUE_3_DATA_EMC_REG_START                 0x03609060
+#define BCHP_OL_QUEUE_3_DATA_EMC_REG_END                   0x0360907c
+#define BCHP_OL_QUEUE_4_DATA_EMC_REG_START                 0x03609080
+#define BCHP_OL_QUEUE_4_DATA_EMC_REG_END                   0x0360909c
+#define BCHP_OL_QUEUE_5_DATA_EMC_REG_START                 0x036090a0
+#define BCHP_OL_QUEUE_5_DATA_EMC_REG_END                   0x036090bc
+#define BCHP_OL_QUEUE_6_DATA_EMC_REG_START                 0x036090c0
+#define BCHP_OL_QUEUE_6_DATA_EMC_REG_END                   0x036090dc
+#define BCHP_OL_QUEUE_7_DATA_EMC_REG_START                 0x036090e0
+#define BCHP_OL_QUEUE_7_DATA_EMC_REG_END                   0x036090fc
+#define BCHP_OL_QUEUE_8_DATA_EMC_REG_START                 0x03609100
+#define BCHP_OL_QUEUE_8_DATA_EMC_REG_END                   0x0360911c
+#define BCHP_OL_QUEUE_9_DATA_EMC_REG_START                 0x03609120
+#define BCHP_OL_QUEUE_9_DATA_EMC_REG_END                   0x0360913c
+#define BCHP_OL_QUEUE_10_DATA_EMC_REG_START                0x03609140
+#define BCHP_OL_QUEUE_10_DATA_EMC_REG_END                  0x0360915c
+#define BCHP_OL_QUEUE_11_DATA_EMC_REG_START                0x03609160
+#define BCHP_OL_QUEUE_11_DATA_EMC_REG_END                  0x0360917c
+#define BCHP_OL_QUEUE_12_DATA_EMC_REG_START                0x03609180
+#define BCHP_OL_QUEUE_12_DATA_EMC_REG_END                  0x0360919c
+#define BCHP_OL_QUEUE_13_DATA_EMC_REG_START                0x036091a0
+#define BCHP_OL_QUEUE_13_DATA_EMC_REG_END                  0x036091bc
+#define BCHP_OL_QUEUE_14_DATA_EMC_REG_START                0x036091c0
+#define BCHP_OL_QUEUE_14_DATA_EMC_REG_END                  0x036091dc
+#define BCHP_OL_QUEUE_15_DATA_EMC_REG_START                0x036091e0
+#define BCHP_OL_QUEUE_15_DATA_EMC_REG_END                  0x036091fc
+#define BCHP_OL_QUEUE_16_DATA_EMC_REG_START                0x03609200
+#define BCHP_OL_QUEUE_16_DATA_EMC_REG_END                  0x0360921c
+#define BCHP_OL_QUEUE_17_DATA_EMC_REG_START                0x03609220
+#define BCHP_OL_QUEUE_17_DATA_EMC_REG_END                  0x0360923c
+#define BCHP_OL_QUEUE_18_DATA_EMC_REG_START                0x03609240
+#define BCHP_OL_QUEUE_18_DATA_EMC_REG_END                  0x0360925c
+#define BCHP_OL_QUEUE_19_DATA_EMC_REG_START                0x03609260
+#define BCHP_OL_QUEUE_19_DATA_EMC_REG_END                  0x0360927c
+#define BCHP_OL_QUEUE_20_DATA_EMC_REG_START                0x03609280
+#define BCHP_OL_QUEUE_20_DATA_EMC_REG_END                  0x0360929c
+#define BCHP_OL_QUEUE_21_DATA_EMC_REG_START                0x036092a0
+#define BCHP_OL_QUEUE_21_DATA_EMC_REG_END                  0x036092bc
+#define BCHP_OL_QUEUE_22_DATA_EMC_REG_START                0x036092c0
+#define BCHP_OL_QUEUE_22_DATA_EMC_REG_END                  0x036092dc
+#define BCHP_OL_QUEUE_23_DATA_EMC_REG_START                0x036092e0
+#define BCHP_OL_QUEUE_23_DATA_EMC_REG_END                  0x036092fc
+#define BCHP_OL_QUEUE_24_DATA_EMC_REG_START                0x03609300
+#define BCHP_OL_QUEUE_24_DATA_EMC_REG_END                  0x0360931c
+#define BCHP_OL_QUEUE_25_DATA_EMC_REG_START                0x03609320
+#define BCHP_OL_QUEUE_25_DATA_EMC_REG_END                  0x0360933c
+#define BCHP_OL_QUEUE_26_DATA_EMC_REG_START                0x03609340
+#define BCHP_OL_QUEUE_26_DATA_EMC_REG_END                  0x0360935c
+#define BCHP_OL_QUEUE_27_DATA_EMC_REG_START                0x03609360
+#define BCHP_OL_QUEUE_27_DATA_EMC_REG_END                  0x0360937c
+#define BCHP_OL_QUEUE_28_DATA_EMC_REG_START                0x03609380
+#define BCHP_OL_QUEUE_28_DATA_EMC_REG_END                  0x0360939c
+#define BCHP_OL_QUEUE_29_DATA_EMC_REG_START                0x036093a0
+#define BCHP_OL_QUEUE_29_DATA_EMC_REG_END                  0x036093bc
+#define BCHP_OL_QUEUE_30_DATA_EMC_REG_START                0x036093c0
+#define BCHP_OL_QUEUE_30_DATA_EMC_REG_END                  0x036093dc
+#define BCHP_OL_QUEUE_31_DATA_EMC_REG_START                0x036093e0
+#define BCHP_OL_QUEUE_31_DATA_EMC_REG_END                  0x036093fc
+#define BCHP_OL_QUEUE_MIB_EMC_REG_START                    0x0360a000
+#define BCHP_OL_QUEUE_MIB_EMC_REG_END                      0x0360a17c
+#define BCHP_QueueSharedMem_EMC_REG_START                  0x03640000
+#define BCHP_QueueSharedMem_EMC_REG_END                    0x0364bffc
+#define BCHP_PacketSharedMemory_EMC_REG_START              0x03680000
+#define BCHP_PacketSharedMemory_EMC_REG_END                0x03680ffc
+#define BCHP_CPU_COMM_REGS_CPUC_REG_START                  0x03800000
+#define BCHP_CPU_COMM_REGS_CPUC_REG_END                    0x0380007c
+#define BCHP_MBOX_CPUC_REG_START                           0x03800080
+#define BCHP_MBOX_CPUC_REG_END                             0x038000fc
+#define BCHP_HW_COUNTER_CPUC_REG_START                     0x03800100
+#define BCHP_HW_COUNTER_CPUC_REG_END                       0x03800184
+#define BCHP_BTM_CPUC_REG_START                            0x03800400
+#define BCHP_BTM_CPUC_REG_END                              0x03800440
+#define BCHP_DQM_MDMA_CPUC_REG_START                       0x03800480
+#define BCHP_DQM_MDMA_CPUC_REG_END                         0x0380057c
+#define BCHP_TRACEBUFF_CPUC_REG_START                      0x03801000
+#define BCHP_TRACEBUFF_CPUC_REG_END                        0x03801028
+#define BCHP_Token_CPUC_REG_START                          0x03801400
+#define BCHP_Token_CPUC_REG_END                            0x03801420
+#define BCHP_RNR_WKUP_CPUC_REG_START                       0x03801800
+#define BCHP_RNR_WKUP_CPUC_REG_END                         0x03801984
+#define BCHP_DQM_CPUC_REG_START                            0x03801c00
+#define BCHP_DQM_CPUC_REG_END                              0x03801dfc
+#define BCHP_QUEUE_TIMER_CPUC_REG_START                    0x03802000
+#define BCHP_QUEUE_TIMER_CPUC_REG_END                      0x038021fc
+#define BCHP_QUEUE_TIMER_96_CPUC_REG_START                 0x03802200
+#define BCHP_QUEUE_TIMER_96_CPUC_REG_END                   0x038022fc
+#define BCHP_OL_QUEUE_STATUS_CPUC_REG_START                0x03807400
+#define BCHP_OL_QUEUE_STATUS_CPUC_REG_END                  0x0380747c
+#define BCHP_OL_QUEUE_STATUS_64_CPUC_REG_START             0x03807480
+#define BCHP_OL_QUEUE_STATUS_64_CPUC_REG_END               0x038074fc
+#define BCHP_OL_QUEUE_STATUS_96_CPUC_REG_START             0x03807500
+#define BCHP_OL_QUEUE_STATUS_96_CPUC_REG_END               0x0380757c
+#define BCHP_OL_QUEUE_0_CNTRL_CPUC_REG_START               0x03808000
+#define BCHP_OL_QUEUE_0_CNTRL_CPUC_REG_END                 0x0380801c
+#define BCHP_OL_QUEUE_1_CNTRL_CPUC_REG_START               0x03808020
+#define BCHP_OL_QUEUE_1_CNTRL_CPUC_REG_END                 0x0380803c
+#define BCHP_OL_QUEUE_2_CNTRL_CPUC_REG_START               0x03808040
+#define BCHP_OL_QUEUE_2_CNTRL_CPUC_REG_END                 0x0380805c
+#define BCHP_OL_QUEUE_3_CNTRL_CPUC_REG_START               0x03808060
+#define BCHP_OL_QUEUE_3_CNTRL_CPUC_REG_END                 0x0380807c
+#define BCHP_OL_QUEUE_4_CNTRL_CPUC_REG_START               0x03808080
+#define BCHP_OL_QUEUE_4_CNTRL_CPUC_REG_END                 0x0380809c
+#define BCHP_OL_QUEUE_5_CNTRL_CPUC_REG_START               0x038080a0
+#define BCHP_OL_QUEUE_5_CNTRL_CPUC_REG_END                 0x038080bc
+#define BCHP_OL_QUEUE_6_CNTRL_CPUC_REG_START               0x038080c0
+#define BCHP_OL_QUEUE_6_CNTRL_CPUC_REG_END                 0x038080dc
+#define BCHP_OL_QUEUE_7_CNTRL_CPUC_REG_START               0x038080e0
+#define BCHP_OL_QUEUE_7_CNTRL_CPUC_REG_END                 0x038080fc
+#define BCHP_OL_QUEUE_8_CNTRL_CPUC_REG_START               0x03808100
+#define BCHP_OL_QUEUE_8_CNTRL_CPUC_REG_END                 0x0380811c
+#define BCHP_OL_QUEUE_9_CNTRL_CPUC_REG_START               0x03808120
+#define BCHP_OL_QUEUE_9_CNTRL_CPUC_REG_END                 0x0380813c
+#define BCHP_OL_QUEUE_10_CNTRL_CPUC_REG_START              0x03808140
+#define BCHP_OL_QUEUE_10_CNTRL_CPUC_REG_END                0x0380815c
+#define BCHP_OL_QUEUE_11_CNTRL_CPUC_REG_START              0x03808160
+#define BCHP_OL_QUEUE_11_CNTRL_CPUC_REG_END                0x0380817c
+#define BCHP_OL_QUEUE_12_CNTRL_CPUC_REG_START              0x03808180
+#define BCHP_OL_QUEUE_12_CNTRL_CPUC_REG_END                0x0380819c
+#define BCHP_OL_QUEUE_13_CNTRL_CPUC_REG_START              0x038081a0
+#define BCHP_OL_QUEUE_13_CNTRL_CPUC_REG_END                0x038081bc
+#define BCHP_OL_QUEUE_14_CNTRL_CPUC_REG_START              0x038081c0
+#define BCHP_OL_QUEUE_14_CNTRL_CPUC_REG_END                0x038081dc
+#define BCHP_OL_QUEUE_15_CNTRL_CPUC_REG_START              0x038081e0
+#define BCHP_OL_QUEUE_15_CNTRL_CPUC_REG_END                0x038081fc
+#define BCHP_OL_QUEUE_16_CNTRL_CPUC_REG_START              0x03808200
+#define BCHP_OL_QUEUE_16_CNTRL_CPUC_REG_END                0x0380821c
+#define BCHP_OL_QUEUE_17_CNTRL_CPUC_REG_START              0x03808220
+#define BCHP_OL_QUEUE_17_CNTRL_CPUC_REG_END                0x0380823c
+#define BCHP_OL_QUEUE_18_CNTRL_CPUC_REG_START              0x03808240
+#define BCHP_OL_QUEUE_18_CNTRL_CPUC_REG_END                0x0380825c
+#define BCHP_OL_QUEUE_19_CNTRL_CPUC_REG_START              0x03808260
+#define BCHP_OL_QUEUE_19_CNTRL_CPUC_REG_END                0x0380827c
+#define BCHP_OL_QUEUE_20_CNTRL_CPUC_REG_START              0x03808280
+#define BCHP_OL_QUEUE_20_CNTRL_CPUC_REG_END                0x0380829c
+#define BCHP_OL_QUEUE_21_CNTRL_CPUC_REG_START              0x038082a0
+#define BCHP_OL_QUEUE_21_CNTRL_CPUC_REG_END                0x038082bc
+#define BCHP_OL_QUEUE_22_CNTRL_CPUC_REG_START              0x038082c0
+#define BCHP_OL_QUEUE_22_CNTRL_CPUC_REG_END                0x038082dc
+#define BCHP_OL_QUEUE_23_CNTRL_CPUC_REG_START              0x038082e0
+#define BCHP_OL_QUEUE_23_CNTRL_CPUC_REG_END                0x038082fc
+#define BCHP_OL_QUEUE_24_CNTRL_CPUC_REG_START              0x03808300
+#define BCHP_OL_QUEUE_24_CNTRL_CPUC_REG_END                0x0380831c
+#define BCHP_OL_QUEUE_25_CNTRL_CPUC_REG_START              0x03808320
+#define BCHP_OL_QUEUE_25_CNTRL_CPUC_REG_END                0x0380833c
+#define BCHP_OL_QUEUE_26_CNTRL_CPUC_REG_START              0x03808340
+#define BCHP_OL_QUEUE_26_CNTRL_CPUC_REG_END                0x0380835c
+#define BCHP_OL_QUEUE_27_CNTRL_CPUC_REG_START              0x03808360
+#define BCHP_OL_QUEUE_27_CNTRL_CPUC_REG_END                0x0380837c
+#define BCHP_OL_QUEUE_28_CNTRL_CPUC_REG_START              0x03808380
+#define BCHP_OL_QUEUE_28_CNTRL_CPUC_REG_END                0x0380839c
+#define BCHP_OL_QUEUE_29_CNTRL_CPUC_REG_START              0x038083a0
+#define BCHP_OL_QUEUE_29_CNTRL_CPUC_REG_END                0x038083bc
+#define BCHP_OL_QUEUE_30_CNTRL_CPUC_REG_START              0x038083c0
+#define BCHP_OL_QUEUE_30_CNTRL_CPUC_REG_END                0x038083dc
+#define BCHP_OL_QUEUE_31_CNTRL_CPUC_REG_START              0x038083e0
+#define BCHP_OL_QUEUE_31_CNTRL_CPUC_REG_END                0x038083fc
+#define BCHP_OL_QUEUE_32_CNTRL_CPUC_REG_START              0x03808400
+#define BCHP_OL_QUEUE_32_CNTRL_CPUC_REG_END                0x0380841c
+#define BCHP_OL_QUEUE_33_CNTRL_CPUC_REG_START              0x03808420
+#define BCHP_OL_QUEUE_33_CNTRL_CPUC_REG_END                0x0380843c
+#define BCHP_OL_QUEUE_34_CNTRL_CPUC_REG_START              0x03808440
+#define BCHP_OL_QUEUE_34_CNTRL_CPUC_REG_END                0x0380845c
+#define BCHP_OL_QUEUE_35_CNTRL_CPUC_REG_START              0x03808460
+#define BCHP_OL_QUEUE_35_CNTRL_CPUC_REG_END                0x0380847c
+#define BCHP_OL_QUEUE_36_CNTRL_CPUC_REG_START              0x03808480
+#define BCHP_OL_QUEUE_36_CNTRL_CPUC_REG_END                0x0380849c
+#define BCHP_OL_QUEUE_37_CNTRL_CPUC_REG_START              0x038084a0
+#define BCHP_OL_QUEUE_37_CNTRL_CPUC_REG_END                0x038084bc
+#define BCHP_OL_QUEUE_38_CNTRL_CPUC_REG_START              0x038084c0
+#define BCHP_OL_QUEUE_38_CNTRL_CPUC_REG_END                0x038084dc
+#define BCHP_OL_QUEUE_39_CNTRL_CPUC_REG_START              0x038084e0
+#define BCHP_OL_QUEUE_39_CNTRL_CPUC_REG_END                0x038084fc
+#define BCHP_OL_QUEUE_40_CNTRL_CPUC_REG_START              0x03808500
+#define BCHP_OL_QUEUE_40_CNTRL_CPUC_REG_END                0x0380851c
+#define BCHP_OL_QUEUE_41_CNTRL_CPUC_REG_START              0x03808520
+#define BCHP_OL_QUEUE_41_CNTRL_CPUC_REG_END                0x0380853c
+#define BCHP_OL_QUEUE_42_CNTRL_CPUC_REG_START              0x03808540
+#define BCHP_OL_QUEUE_42_CNTRL_CPUC_REG_END                0x0380855c
+#define BCHP_OL_QUEUE_43_CNTRL_CPUC_REG_START              0x03808560
+#define BCHP_OL_QUEUE_43_CNTRL_CPUC_REG_END                0x0380857c
+#define BCHP_OL_QUEUE_44_CNTRL_CPUC_REG_START              0x03808580
+#define BCHP_OL_QUEUE_44_CNTRL_CPUC_REG_END                0x0380859c
+#define BCHP_OL_QUEUE_45_CNTRL_CPUC_REG_START              0x038085a0
+#define BCHP_OL_QUEUE_45_CNTRL_CPUC_REG_END                0x038085bc
+#define BCHP_OL_QUEUE_46_CNTRL_CPUC_REG_START              0x038085c0
+#define BCHP_OL_QUEUE_46_CNTRL_CPUC_REG_END                0x038085dc
+#define BCHP_OL_QUEUE_47_CNTRL_CPUC_REG_START              0x038085e0
+#define BCHP_OL_QUEUE_47_CNTRL_CPUC_REG_END                0x038085fc
+#define BCHP_OL_QUEUE_48_CNTRL_CPUC_REG_START              0x03808600
+#define BCHP_OL_QUEUE_48_CNTRL_CPUC_REG_END                0x0380861c
+#define BCHP_OL_QUEUE_49_CNTRL_CPUC_REG_START              0x03808620
+#define BCHP_OL_QUEUE_49_CNTRL_CPUC_REG_END                0x0380863c
+#define BCHP_OL_QUEUE_50_CNTRL_CPUC_REG_START              0x03808640
+#define BCHP_OL_QUEUE_50_CNTRL_CPUC_REG_END                0x0380865c
+#define BCHP_OL_QUEUE_51_CNTRL_CPUC_REG_START              0x03808660
+#define BCHP_OL_QUEUE_51_CNTRL_CPUC_REG_END                0x0380867c
+#define BCHP_OL_QUEUE_52_CNTRL_CPUC_REG_START              0x03808680
+#define BCHP_OL_QUEUE_52_CNTRL_CPUC_REG_END                0x0380869c
+#define BCHP_OL_QUEUE_53_CNTRL_CPUC_REG_START              0x038086a0
+#define BCHP_OL_QUEUE_53_CNTRL_CPUC_REG_END                0x038086bc
+#define BCHP_OL_QUEUE_54_CNTRL_CPUC_REG_START              0x038086c0
+#define BCHP_OL_QUEUE_54_CNTRL_CPUC_REG_END                0x038086dc
+#define BCHP_OL_QUEUE_55_CNTRL_CPUC_REG_START              0x038086e0
+#define BCHP_OL_QUEUE_55_CNTRL_CPUC_REG_END                0x038086fc
+#define BCHP_OL_QUEUE_56_CNTRL_CPUC_REG_START              0x03808700
+#define BCHP_OL_QUEUE_56_CNTRL_CPUC_REG_END                0x0380871c
+#define BCHP_OL_QUEUE_57_CNTRL_CPUC_REG_START              0x03808720
+#define BCHP_OL_QUEUE_57_CNTRL_CPUC_REG_END                0x0380873c
+#define BCHP_OL_QUEUE_58_CNTRL_CPUC_REG_START              0x03808740
+#define BCHP_OL_QUEUE_58_CNTRL_CPUC_REG_END                0x0380875c
+#define BCHP_OL_QUEUE_59_CNTRL_CPUC_REG_START              0x03808760
+#define BCHP_OL_QUEUE_59_CNTRL_CPUC_REG_END                0x0380877c
+#define BCHP_OL_QUEUE_60_CNTRL_CPUC_REG_START              0x03808780
+#define BCHP_OL_QUEUE_60_CNTRL_CPUC_REG_END                0x0380879c
+#define BCHP_OL_QUEUE_61_CNTRL_CPUC_REG_START              0x038087a0
+#define BCHP_OL_QUEUE_61_CNTRL_CPUC_REG_END                0x038087bc
+#define BCHP_OL_QUEUE_62_CNTRL_CPUC_REG_START              0x038087c0
+#define BCHP_OL_QUEUE_62_CNTRL_CPUC_REG_END                0x038087dc
+#define BCHP_OL_QUEUE_63_CNTRL_CPUC_REG_START              0x038087e0
+#define BCHP_OL_QUEUE_63_CNTRL_CPUC_REG_END                0x038087fc
+#define BCHP_OL_QUEUE_64_CNTRL_CPUC_REG_START              0x03808800
+#define BCHP_OL_QUEUE_64_CNTRL_CPUC_REG_END                0x0380881c
+#define BCHP_OL_QUEUE_65_CNTRL_CPUC_REG_START              0x03808820
+#define BCHP_OL_QUEUE_65_CNTRL_CPUC_REG_END                0x0380883c
+#define BCHP_OL_QUEUE_66_CNTRL_CPUC_REG_START              0x03808840
+#define BCHP_OL_QUEUE_66_CNTRL_CPUC_REG_END                0x0380885c
+#define BCHP_OL_QUEUE_67_CNTRL_CPUC_REG_START              0x03808860
+#define BCHP_OL_QUEUE_67_CNTRL_CPUC_REG_END                0x0380887c
+#define BCHP_OL_QUEUE_68_CNTRL_CPUC_REG_START              0x03808880
+#define BCHP_OL_QUEUE_68_CNTRL_CPUC_REG_END                0x0380889c
+#define BCHP_OL_QUEUE_69_CNTRL_CPUC_REG_START              0x038088a0
+#define BCHP_OL_QUEUE_69_CNTRL_CPUC_REG_END                0x038088bc
+#define BCHP_OL_QUEUE_70_CNTRL_CPUC_REG_START              0x038088c0
+#define BCHP_OL_QUEUE_70_CNTRL_CPUC_REG_END                0x038088dc
+#define BCHP_OL_QUEUE_71_CNTRL_CPUC_REG_START              0x038088e0
+#define BCHP_OL_QUEUE_71_CNTRL_CPUC_REG_END                0x038088fc
+#define BCHP_OL_QUEUE_72_CNTRL_CPUC_REG_START              0x03808900
+#define BCHP_OL_QUEUE_72_CNTRL_CPUC_REG_END                0x0380891c
+#define BCHP_OL_QUEUE_73_CNTRL_CPUC_REG_START              0x03808920
+#define BCHP_OL_QUEUE_73_CNTRL_CPUC_REG_END                0x0380893c
+#define BCHP_OL_QUEUE_74_CNTRL_CPUC_REG_START              0x03808940
+#define BCHP_OL_QUEUE_74_CNTRL_CPUC_REG_END                0x0380895c
+#define BCHP_OL_QUEUE_75_CNTRL_CPUC_REG_START              0x03808960
+#define BCHP_OL_QUEUE_75_CNTRL_CPUC_REG_END                0x0380897c
+#define BCHP_OL_QUEUE_76_CNTRL_CPUC_REG_START              0x03808980
+#define BCHP_OL_QUEUE_76_CNTRL_CPUC_REG_END                0x0380899c
+#define BCHP_OL_QUEUE_77_CNTRL_CPUC_REG_START              0x038089a0
+#define BCHP_OL_QUEUE_77_CNTRL_CPUC_REG_END                0x038089bc
+#define BCHP_OL_QUEUE_78_CNTRL_CPUC_REG_START              0x038089c0
+#define BCHP_OL_QUEUE_78_CNTRL_CPUC_REG_END                0x038089dc
+#define BCHP_OL_QUEUE_79_CNTRL_CPUC_REG_START              0x038089e0
+#define BCHP_OL_QUEUE_79_CNTRL_CPUC_REG_END                0x038089fc
+#define BCHP_OL_QUEUE_80_CNTRL_CPUC_REG_START              0x03808a00
+#define BCHP_OL_QUEUE_80_CNTRL_CPUC_REG_END                0x03808a1c
+#define BCHP_OL_QUEUE_81_CNTRL_CPUC_REG_START              0x03808a20
+#define BCHP_OL_QUEUE_81_CNTRL_CPUC_REG_END                0x03808a3c
+#define BCHP_OL_QUEUE_82_CNTRL_CPUC_REG_START              0x03808a40
+#define BCHP_OL_QUEUE_82_CNTRL_CPUC_REG_END                0x03808a5c
+#define BCHP_OL_QUEUE_83_CNTRL_CPUC_REG_START              0x03808a60
+#define BCHP_OL_QUEUE_83_CNTRL_CPUC_REG_END                0x03808a7c
+#define BCHP_OL_QUEUE_84_CNTRL_CPUC_REG_START              0x03808a80
+#define BCHP_OL_QUEUE_84_CNTRL_CPUC_REG_END                0x03808a9c
+#define BCHP_OL_QUEUE_85_CNTRL_CPUC_REG_START              0x03808aa0
+#define BCHP_OL_QUEUE_85_CNTRL_CPUC_REG_END                0x03808abc
+#define BCHP_OL_QUEUE_86_CNTRL_CPUC_REG_START              0x03808ac0
+#define BCHP_OL_QUEUE_86_CNTRL_CPUC_REG_END                0x03808adc
+#define BCHP_OL_QUEUE_87_CNTRL_CPUC_REG_START              0x03808ae0
+#define BCHP_OL_QUEUE_87_CNTRL_CPUC_REG_END                0x03808afc
+#define BCHP_OL_QUEUE_88_CNTRL_CPUC_REG_START              0x03808b00
+#define BCHP_OL_QUEUE_88_CNTRL_CPUC_REG_END                0x03808b1c
+#define BCHP_OL_QUEUE_89_CNTRL_CPUC_REG_START              0x03808b20
+#define BCHP_OL_QUEUE_89_CNTRL_CPUC_REG_END                0x03808b3c
+#define BCHP_OL_QUEUE_90_CNTRL_CPUC_REG_START              0x03808b40
+#define BCHP_OL_QUEUE_90_CNTRL_CPUC_REG_END                0x03808b5c
+#define BCHP_OL_QUEUE_91_CNTRL_CPUC_REG_START              0x03808b60
+#define BCHP_OL_QUEUE_91_CNTRL_CPUC_REG_END                0x03808b7c
+#define BCHP_OL_QUEUE_92_CNTRL_CPUC_REG_START              0x03808b80
+#define BCHP_OL_QUEUE_92_CNTRL_CPUC_REG_END                0x03808b9c
+#define BCHP_OL_QUEUE_93_CNTRL_CPUC_REG_START              0x03808ba0
+#define BCHP_OL_QUEUE_93_CNTRL_CPUC_REG_END                0x03808bbc
+#define BCHP_OL_QUEUE_94_CNTRL_CPUC_REG_START              0x03808bc0
+#define BCHP_OL_QUEUE_94_CNTRL_CPUC_REG_END                0x03808bdc
+#define BCHP_OL_QUEUE_95_CNTRL_CPUC_REG_START              0x03808be0
+#define BCHP_OL_QUEUE_95_CNTRL_CPUC_REG_END                0x03808bfc
+#define BCHP_OL_QUEUE_0_DATA_CPUC_REG_START                0x03809000
+#define BCHP_OL_QUEUE_0_DATA_CPUC_REG_END                  0x0380901c
+#define BCHP_OL_QUEUE_1_DATA_CPUC_REG_START                0x03809020
+#define BCHP_OL_QUEUE_1_DATA_CPUC_REG_END                  0x0380903c
+#define BCHP_OL_QUEUE_2_DATA_CPUC_REG_START                0x03809040
+#define BCHP_OL_QUEUE_2_DATA_CPUC_REG_END                  0x0380905c
+#define BCHP_OL_QUEUE_3_DATA_CPUC_REG_START                0x03809060
+#define BCHP_OL_QUEUE_3_DATA_CPUC_REG_END                  0x0380907c
+#define BCHP_OL_QUEUE_4_DATA_CPUC_REG_START                0x03809080
+#define BCHP_OL_QUEUE_4_DATA_CPUC_REG_END                  0x0380909c
+#define BCHP_OL_QUEUE_5_DATA_CPUC_REG_START                0x038090a0
+#define BCHP_OL_QUEUE_5_DATA_CPUC_REG_END                  0x038090bc
+#define BCHP_OL_QUEUE_6_DATA_CPUC_REG_START                0x038090c0
+#define BCHP_OL_QUEUE_6_DATA_CPUC_REG_END                  0x038090dc
+#define BCHP_OL_QUEUE_7_DATA_CPUC_REG_START                0x038090e0
+#define BCHP_OL_QUEUE_7_DATA_CPUC_REG_END                  0x038090fc
+#define BCHP_OL_QUEUE_8_DATA_CPUC_REG_START                0x03809100
+#define BCHP_OL_QUEUE_8_DATA_CPUC_REG_END                  0x0380911c
+#define BCHP_OL_QUEUE_9_DATA_CPUC_REG_START                0x03809120
+#define BCHP_OL_QUEUE_9_DATA_CPUC_REG_END                  0x0380913c
+#define BCHP_OL_QUEUE_10_DATA_CPUC_REG_START               0x03809140
+#define BCHP_OL_QUEUE_10_DATA_CPUC_REG_END                 0x0380915c
+#define BCHP_OL_QUEUE_11_DATA_CPUC_REG_START               0x03809160
+#define BCHP_OL_QUEUE_11_DATA_CPUC_REG_END                 0x0380917c
+#define BCHP_OL_QUEUE_12_DATA_CPUC_REG_START               0x03809180
+#define BCHP_OL_QUEUE_12_DATA_CPUC_REG_END                 0x0380919c
+#define BCHP_OL_QUEUE_13_DATA_CPUC_REG_START               0x038091a0
+#define BCHP_OL_QUEUE_13_DATA_CPUC_REG_END                 0x038091bc
+#define BCHP_OL_QUEUE_14_DATA_CPUC_REG_START               0x038091c0
+#define BCHP_OL_QUEUE_14_DATA_CPUC_REG_END                 0x038091dc
+#define BCHP_OL_QUEUE_15_DATA_CPUC_REG_START               0x038091e0
+#define BCHP_OL_QUEUE_15_DATA_CPUC_REG_END                 0x038091fc
+#define BCHP_OL_QUEUE_16_DATA_CPUC_REG_START               0x03809200
+#define BCHP_OL_QUEUE_16_DATA_CPUC_REG_END                 0x0380921c
+#define BCHP_OL_QUEUE_17_DATA_CPUC_REG_START               0x03809220
+#define BCHP_OL_QUEUE_17_DATA_CPUC_REG_END                 0x0380923c
+#define BCHP_OL_QUEUE_18_DATA_CPUC_REG_START               0x03809240
+#define BCHP_OL_QUEUE_18_DATA_CPUC_REG_END                 0x0380925c
+#define BCHP_OL_QUEUE_19_DATA_CPUC_REG_START               0x03809260
+#define BCHP_OL_QUEUE_19_DATA_CPUC_REG_END                 0x0380927c
+#define BCHP_OL_QUEUE_20_DATA_CPUC_REG_START               0x03809280
+#define BCHP_OL_QUEUE_20_DATA_CPUC_REG_END                 0x0380929c
+#define BCHP_OL_QUEUE_21_DATA_CPUC_REG_START               0x038092a0
+#define BCHP_OL_QUEUE_21_DATA_CPUC_REG_END                 0x038092bc
+#define BCHP_OL_QUEUE_22_DATA_CPUC_REG_START               0x038092c0
+#define BCHP_OL_QUEUE_22_DATA_CPUC_REG_END                 0x038092dc
+#define BCHP_OL_QUEUE_23_DATA_CPUC_REG_START               0x038092e0
+#define BCHP_OL_QUEUE_23_DATA_CPUC_REG_END                 0x038092fc
+#define BCHP_OL_QUEUE_24_DATA_CPUC_REG_START               0x03809300
+#define BCHP_OL_QUEUE_24_DATA_CPUC_REG_END                 0x0380931c
+#define BCHP_OL_QUEUE_25_DATA_CPUC_REG_START               0x03809320
+#define BCHP_OL_QUEUE_25_DATA_CPUC_REG_END                 0x0380933c
+#define BCHP_OL_QUEUE_26_DATA_CPUC_REG_START               0x03809340
+#define BCHP_OL_QUEUE_26_DATA_CPUC_REG_END                 0x0380935c
+#define BCHP_OL_QUEUE_27_DATA_CPUC_REG_START               0x03809360
+#define BCHP_OL_QUEUE_27_DATA_CPUC_REG_END                 0x0380937c
+#define BCHP_OL_QUEUE_28_DATA_CPUC_REG_START               0x03809380
+#define BCHP_OL_QUEUE_28_DATA_CPUC_REG_END                 0x0380939c
+#define BCHP_OL_QUEUE_29_DATA_CPUC_REG_START               0x038093a0
+#define BCHP_OL_QUEUE_29_DATA_CPUC_REG_END                 0x038093bc
+#define BCHP_OL_QUEUE_30_DATA_CPUC_REG_START               0x038093c0
+#define BCHP_OL_QUEUE_30_DATA_CPUC_REG_END                 0x038093dc
+#define BCHP_OL_QUEUE_31_DATA_CPUC_REG_START               0x038093e0
+#define BCHP_OL_QUEUE_31_DATA_CPUC_REG_END                 0x038093fc
+#define BCHP_OL_QUEUE_32_DATA_CPUC_REG_START               0x03809400
+#define BCHP_OL_QUEUE_32_DATA_CPUC_REG_END                 0x0380941c
+#define BCHP_OL_QUEUE_33_DATA_CPUC_REG_START               0x03809420
+#define BCHP_OL_QUEUE_33_DATA_CPUC_REG_END                 0x0380943c
+#define BCHP_OL_QUEUE_34_DATA_CPUC_REG_START               0x03809440
+#define BCHP_OL_QUEUE_34_DATA_CPUC_REG_END                 0x0380945c
+#define BCHP_OL_QUEUE_35_DATA_CPUC_REG_START               0x03809460
+#define BCHP_OL_QUEUE_35_DATA_CPUC_REG_END                 0x0380947c
+#define BCHP_OL_QUEUE_36_DATA_CPUC_REG_START               0x03809480
+#define BCHP_OL_QUEUE_36_DATA_CPUC_REG_END                 0x0380949c
+#define BCHP_OL_QUEUE_37_DATA_CPUC_REG_START               0x038094a0
+#define BCHP_OL_QUEUE_37_DATA_CPUC_REG_END                 0x038094bc
+#define BCHP_OL_QUEUE_38_DATA_CPUC_REG_START               0x038094c0
+#define BCHP_OL_QUEUE_38_DATA_CPUC_REG_END                 0x038094dc
+#define BCHP_OL_QUEUE_39_DATA_CPUC_REG_START               0x038094e0
+#define BCHP_OL_QUEUE_39_DATA_CPUC_REG_END                 0x038094fc
+#define BCHP_OL_QUEUE_40_DATA_CPUC_REG_START               0x03809500
+#define BCHP_OL_QUEUE_40_DATA_CPUC_REG_END                 0x0380951c
+#define BCHP_OL_QUEUE_41_DATA_CPUC_REG_START               0x03809520
+#define BCHP_OL_QUEUE_41_DATA_CPUC_REG_END                 0x0380953c
+#define BCHP_OL_QUEUE_42_DATA_CPUC_REG_START               0x03809540
+#define BCHP_OL_QUEUE_42_DATA_CPUC_REG_END                 0x0380955c
+#define BCHP_OL_QUEUE_43_DATA_CPUC_REG_START               0x03809560
+#define BCHP_OL_QUEUE_43_DATA_CPUC_REG_END                 0x0380957c
+#define BCHP_OL_QUEUE_44_DATA_CPUC_REG_START               0x03809580
+#define BCHP_OL_QUEUE_44_DATA_CPUC_REG_END                 0x0380959c
+#define BCHP_OL_QUEUE_45_DATA_CPUC_REG_START               0x038095a0
+#define BCHP_OL_QUEUE_45_DATA_CPUC_REG_END                 0x038095bc
+#define BCHP_OL_QUEUE_46_DATA_CPUC_REG_START               0x038095c0
+#define BCHP_OL_QUEUE_46_DATA_CPUC_REG_END                 0x038095dc
+#define BCHP_OL_QUEUE_47_DATA_CPUC_REG_START               0x038095e0
+#define BCHP_OL_QUEUE_47_DATA_CPUC_REG_END                 0x038095fc
+#define BCHP_OL_QUEUE_48_DATA_CPUC_REG_START               0x03809600
+#define BCHP_OL_QUEUE_48_DATA_CPUC_REG_END                 0x0380961c
+#define BCHP_OL_QUEUE_49_DATA_CPUC_REG_START               0x03809620
+#define BCHP_OL_QUEUE_49_DATA_CPUC_REG_END                 0x0380963c
+#define BCHP_OL_QUEUE_50_DATA_CPUC_REG_START               0x03809640
+#define BCHP_OL_QUEUE_50_DATA_CPUC_REG_END                 0x0380965c
+#define BCHP_OL_QUEUE_51_DATA_CPUC_REG_START               0x03809660
+#define BCHP_OL_QUEUE_51_DATA_CPUC_REG_END                 0x0380967c
+#define BCHP_OL_QUEUE_52_DATA_CPUC_REG_START               0x03809680
+#define BCHP_OL_QUEUE_52_DATA_CPUC_REG_END                 0x0380969c
+#define BCHP_OL_QUEUE_53_DATA_CPUC_REG_START               0x038096a0
+#define BCHP_OL_QUEUE_53_DATA_CPUC_REG_END                 0x038096bc
+#define BCHP_OL_QUEUE_54_DATA_CPUC_REG_START               0x038096c0
+#define BCHP_OL_QUEUE_54_DATA_CPUC_REG_END                 0x038096dc
+#define BCHP_OL_QUEUE_55_DATA_CPUC_REG_START               0x038096e0
+#define BCHP_OL_QUEUE_55_DATA_CPUC_REG_END                 0x038096fc
+#define BCHP_OL_QUEUE_56_DATA_CPUC_REG_START               0x03809700
+#define BCHP_OL_QUEUE_56_DATA_CPUC_REG_END                 0x0380971c
+#define BCHP_OL_QUEUE_57_DATA_CPUC_REG_START               0x03809720
+#define BCHP_OL_QUEUE_57_DATA_CPUC_REG_END                 0x0380973c
+#define BCHP_OL_QUEUE_58_DATA_CPUC_REG_START               0x03809740
+#define BCHP_OL_QUEUE_58_DATA_CPUC_REG_END                 0x0380975c
+#define BCHP_OL_QUEUE_59_DATA_CPUC_REG_START               0x03809760
+#define BCHP_OL_QUEUE_59_DATA_CPUC_REG_END                 0x0380977c
+#define BCHP_OL_QUEUE_60_DATA_CPUC_REG_START               0x03809780
+#define BCHP_OL_QUEUE_60_DATA_CPUC_REG_END                 0x0380979c
+#define BCHP_OL_QUEUE_61_DATA_CPUC_REG_START               0x038097a0
+#define BCHP_OL_QUEUE_61_DATA_CPUC_REG_END                 0x038097bc
+#define BCHP_OL_QUEUE_62_DATA_CPUC_REG_START               0x038097c0
+#define BCHP_OL_QUEUE_62_DATA_CPUC_REG_END                 0x038097dc
+#define BCHP_OL_QUEUE_63_DATA_CPUC_REG_START               0x038097e0
+#define BCHP_OL_QUEUE_63_DATA_CPUC_REG_END                 0x038097fc
+#define BCHP_OL_QUEUE_64_DATA_CPUC_REG_START               0x03809800
+#define BCHP_OL_QUEUE_64_DATA_CPUC_REG_END                 0x0380981c
+#define BCHP_OL_QUEUE_65_DATA_CPUC_REG_START               0x03809820
+#define BCHP_OL_QUEUE_65_DATA_CPUC_REG_END                 0x0380983c
+#define BCHP_OL_QUEUE_66_DATA_CPUC_REG_START               0x03809840
+#define BCHP_OL_QUEUE_66_DATA_CPUC_REG_END                 0x0380985c
+#define BCHP_OL_QUEUE_67_DATA_CPUC_REG_START               0x03809860
+#define BCHP_OL_QUEUE_67_DATA_CPUC_REG_END                 0x0380987c
+#define BCHP_OL_QUEUE_68_DATA_CPUC_REG_START               0x03809880
+#define BCHP_OL_QUEUE_68_DATA_CPUC_REG_END                 0x0380989c
+#define BCHP_OL_QUEUE_69_DATA_CPUC_REG_START               0x038098a0
+#define BCHP_OL_QUEUE_69_DATA_CPUC_REG_END                 0x038098bc
+#define BCHP_OL_QUEUE_70_DATA_CPUC_REG_START               0x038098c0
+#define BCHP_OL_QUEUE_70_DATA_CPUC_REG_END                 0x038098dc
+#define BCHP_OL_QUEUE_71_DATA_CPUC_REG_START               0x038098e0
+#define BCHP_OL_QUEUE_71_DATA_CPUC_REG_END                 0x038098fc
+#define BCHP_OL_QUEUE_72_DATA_CPUC_REG_START               0x03809900
+#define BCHP_OL_QUEUE_72_DATA_CPUC_REG_END                 0x0380991c
+#define BCHP_OL_QUEUE_73_DATA_CPUC_REG_START               0x03809920
+#define BCHP_OL_QUEUE_73_DATA_CPUC_REG_END                 0x0380993c
+#define BCHP_OL_QUEUE_74_DATA_CPUC_REG_START               0x03809940
+#define BCHP_OL_QUEUE_74_DATA_CPUC_REG_END                 0x0380995c
+#define BCHP_OL_QUEUE_75_DATA_CPUC_REG_START               0x03809960
+#define BCHP_OL_QUEUE_75_DATA_CPUC_REG_END                 0x0380997c
+#define BCHP_OL_QUEUE_76_DATA_CPUC_REG_START               0x03809980
+#define BCHP_OL_QUEUE_76_DATA_CPUC_REG_END                 0x0380999c
+#define BCHP_OL_QUEUE_77_DATA_CPUC_REG_START               0x038099a0
+#define BCHP_OL_QUEUE_77_DATA_CPUC_REG_END                 0x038099bc
+#define BCHP_OL_QUEUE_78_DATA_CPUC_REG_START               0x038099c0
+#define BCHP_OL_QUEUE_78_DATA_CPUC_REG_END                 0x038099dc
+#define BCHP_OL_QUEUE_79_DATA_CPUC_REG_START               0x038099e0
+#define BCHP_OL_QUEUE_79_DATA_CPUC_REG_END                 0x038099fc
+#define BCHP_OL_QUEUE_80_DATA_CPUC_REG_START               0x03809a00
+#define BCHP_OL_QUEUE_80_DATA_CPUC_REG_END                 0x03809a1c
+#define BCHP_OL_QUEUE_81_DATA_CPUC_REG_START               0x03809a20
+#define BCHP_OL_QUEUE_81_DATA_CPUC_REG_END                 0x03809a3c
+#define BCHP_OL_QUEUE_82_DATA_CPUC_REG_START               0x03809a40
+#define BCHP_OL_QUEUE_82_DATA_CPUC_REG_END                 0x03809a5c
+#define BCHP_OL_QUEUE_83_DATA_CPUC_REG_START               0x03809a60
+#define BCHP_OL_QUEUE_83_DATA_CPUC_REG_END                 0x03809a7c
+#define BCHP_OL_QUEUE_84_DATA_CPUC_REG_START               0x03809a80
+#define BCHP_OL_QUEUE_84_DATA_CPUC_REG_END                 0x03809a9c
+#define BCHP_OL_QUEUE_85_DATA_CPUC_REG_START               0x03809aa0
+#define BCHP_OL_QUEUE_85_DATA_CPUC_REG_END                 0x03809abc
+#define BCHP_OL_QUEUE_86_DATA_CPUC_REG_START               0x03809ac0
+#define BCHP_OL_QUEUE_86_DATA_CPUC_REG_END                 0x03809adc
+#define BCHP_OL_QUEUE_87_DATA_CPUC_REG_START               0x03809ae0
+#define BCHP_OL_QUEUE_87_DATA_CPUC_REG_END                 0x03809afc
+#define BCHP_OL_QUEUE_88_DATA_CPUC_REG_START               0x03809b00
+#define BCHP_OL_QUEUE_88_DATA_CPUC_REG_END                 0x03809b1c
+#define BCHP_OL_QUEUE_89_DATA_CPUC_REG_START               0x03809b20
+#define BCHP_OL_QUEUE_89_DATA_CPUC_REG_END                 0x03809b3c
+#define BCHP_OL_QUEUE_90_DATA_CPUC_REG_START               0x03809b40
+#define BCHP_OL_QUEUE_90_DATA_CPUC_REG_END                 0x03809b5c
+#define BCHP_OL_QUEUE_91_DATA_CPUC_REG_START               0x03809b60
+#define BCHP_OL_QUEUE_91_DATA_CPUC_REG_END                 0x03809b7c
+#define BCHP_OL_QUEUE_92_DATA_CPUC_REG_START               0x03809b80
+#define BCHP_OL_QUEUE_92_DATA_CPUC_REG_END                 0x03809b9c
+#define BCHP_OL_QUEUE_93_DATA_CPUC_REG_START               0x03809ba0
+#define BCHP_OL_QUEUE_93_DATA_CPUC_REG_END                 0x03809bbc
+#define BCHP_OL_QUEUE_94_DATA_CPUC_REG_START               0x03809bc0
+#define BCHP_OL_QUEUE_94_DATA_CPUC_REG_END                 0x03809bdc
+#define BCHP_OL_QUEUE_95_DATA_CPUC_REG_START               0x03809be0
+#define BCHP_OL_QUEUE_95_DATA_CPUC_REG_END                 0x03809bfc
+#define BCHP_OL_QUEUE_MIB_CPUC_REG_START                   0x0380a000
+#define BCHP_OL_QUEUE_MIB_CPUC_REG_END                     0x0380a17c
+#define BCHP_OL_QUEUE_MIB_64_CPUC_REG_START                0x0380a200
+#define BCHP_OL_QUEUE_MIB_64_CPUC_REG_END                  0x0380a37c
+#define BCHP_OL_QUEUE_MIB_96_CPUC_REG_START                0x0380a400
+#define BCHP_OL_QUEUE_MIB_96_CPUC_REG_END                  0x0380a57c
+#define BCHP_QueueSharedMem_CPUC_REG_START                 0x03840000
+#define BCHP_QueueSharedMem_CPUC_REG_END                   0x0384bffc
+#define BCHP_CM_TOP_CTRL_REG_START                         0x03880000
+#define BCHP_CM_TOP_CTRL_REG_END                           0x03880370
+#define BCHP_RG_TOP_CTRL_REG_START                         0x03881000
+#define BCHP_RG_TOP_CTRL_REG_END                           0x0388104c
+#define BCHP_UART_REG_START                                0x03881800
+#define BCHP_UART_REG_END                                  0x0388181c
+#define BCHP_CM_AON_CTRL_REG_START                         0x03882000
+#define BCHP_CM_AON_CTRL_REG_END                           0x03882008
+#define BCHP_PROD_OTP_GRB_UB_REG_START                     0x03890000
+#define BCHP_PROD_OTP_GRB_UB_REG_END                       0x0389000c
+#define BCHP_JTAG_OTP_UB_REG_START                         0x03890100
+#define BCHP_JTAG_OTP_UB_REG_END                           0x0389015c
+#define BCHP_RF4CE_CPU_PROG0_MEM_UB_REG_START              0x03900000
+#define BCHP_RF4CE_CPU_PROG0_MEM_UB_REG_END                0x0391fffc
+#define BCHP_RF4CE_CPU_PROG1_MEM_UB_REG_START              0x03920000
+#define BCHP_RF4CE_CPU_PROG1_MEM_UB_REG_END                0x0393fffc
+#define BCHP_RF4CE_CPU_DATA_MEM_UB_REG_START               0x03940000
+#define BCHP_RF4CE_CPU_DATA_MEM_UB_REG_END                 0x03947ffc
+#define BCHP_RF4CE_CPU_CORE_REGS_UB_REG_START              0x03950000
+#define BCHP_RF4CE_CPU_CORE_REGS_UB_REG_END                0x039500fc
+#define BCHP_RF4CE_CPU_AUX_REGS_UB_REG_START               0x03951000
+#define BCHP_RF4CE_CPU_AUX_REGS_UB_REG_END                 0x03951a08
+#define BCHP_RF4CE_CPU_UART_UB_REG_START                   0x03952000
+#define BCHP_RF4CE_CPU_UART_UB_REG_END                     0x03952ffc
+#define BCHP_RF4CE_CPU_WDG_UB_REG_START                    0x03953000
+#define BCHP_RF4CE_CPU_WDG_UB_REG_END                      0x03953ffc
+#define BCHP_RF4CE_CPU_CTRL_UB_REG_START                   0x03980000
+#define BCHP_RF4CE_CPU_CTRL_UB_REG_END                     0x0398008c
+#define BCHP_RF4CE_CPU_L2_UB_REG_START                     0x03980300
+#define BCHP_RF4CE_CPU_L2_UB_REG_END                       0x03980314
+#define BCHP_RF4CE_CPU_HOST_STB_L2_UB_REG_START            0x03980500
+#define BCHP_RF4CE_CPU_HOST_STB_L2_UB_REG_END              0x0398052c
+#define BCHP_RF4CE_CPU_HOST_CM_L2_UB_REG_START             0x03980800
+#define BCHP_RF4CE_CPU_HOST_CM_L2_UB_REG_END               0x0398082c
+#define BCHP_RF4CE_CPU_HOST_RG_L2_UB_REG_START             0x03980a00
+#define BCHP_RF4CE_CPU_HOST_RG_L2_UB_REG_END               0x03980a2c
+#define BCHP_TX_UB_REG_START                               0x039c0000
+#define BCHP_TX_UB_REG_END                                 0x039c0020
+#define BCHP_RX_UB_REG_START                               0x039d0000
+#define BCHP_RX_UB_REG_END                                 0x039d0254
+#define BCHP_RF_UB_REG_START                               0x039e0000
+#define BCHP_RF_UB_REG_END                                 0x039e00a4
+#define BCHP_VCOCAL_UB_REG_START                           0x039e0100
+#define BCHP_VCOCAL_UB_REG_END                             0x039e0174
+#define BCHP_KVCO_UB_REG_START                             0x039e0200
+#define BCHP_KVCO_UB_REG_END                               0x039e0224
+#define BCHP_PA_UB_REG_START                               0x039e0300
+#define BCHP_PA_UB_REG_END                                 0x039e0314
+#define BCHP_MAC_UB_REG_START                              0x039e0400
+#define BCHP_MAC_UB_REG_END                                0x039e0564
+#define BCHP_PWR_MGT_L2_UB_REG_START                       0x039e0600
+#define BCHP_PWR_MGT_L2_UB_REG_END                         0x039e0614
+#define BCHP_MISC_L2_UB_REG_START                          0x039e0700
+#define BCHP_MISC_L2_UB_REG_END                            0x039e0714
+#define BCHP_IQCAL_CCA_CCM_L2_UB_REG_START                 0x039e0800
+#define BCHP_IQCAL_CCA_CCM_L2_UB_REG_END                   0x039e0814
+#define BCHP_SYMCNT6_L2_UB_REG_START                       0x039e0900
+#define BCHP_SYMCNT6_L2_UB_REG_END                         0x039e0914
+#define BCHP_TX_DONE_L2_UB_REG_START                       0x039e0a00
+#define BCHP_TX_DONE_L2_UB_REG_END                         0x039e0a14
+#define BCHP_RX_DONE_L2_UB_REG_START                       0x039e0b00
+#define BCHP_RX_DONE_L2_UB_REG_END                         0x039e0b14
+#define BCHP_RX_START_L2_UB_REG_START                      0x039e0c00
+#define BCHP_RX_START_L2_UB_REG_END                        0x039e0c14
+#define BCHP_SYMCNT7_L2_UB_REG_START                       0x039e0d00
+#define BCHP_SYMCNT7_L2_UB_REG_END                         0x039e0d14
+#define BCHP_GCI_0_UB_REG_START                            0x039e1000
+#define BCHP_GCI_0_UB_REG_END                              0x039e120c
+#define BCHP_GCI_1_UB_REG_START                            0x039e1400
+#define BCHP_GCI_1_UB_REG_END                              0x039e1604
+#define BCHP_GCI_2_UB_REG_START                            0x039e1800
+#define BCHP_GCI_2_UB_REG_END                              0x039e1a04
+#define BCHP_FPM_CTRL_FPM_REG_START                        0x03a00000
+#define BCHP_FPM_CTRL_FPM_REG_END                          0x03a0014c
+#define BCHP_FPM_POOL_FPM_REG_START                        0x03a00200
+#define BCHP_FPM_POOL_FPM_REG_END                          0x03a00224
+#define BCHP_FPM_POOL_0_FPM_REG_START                      0x03a00400
+#define BCHP_FPM_POOL_0_FPM_REG_END                        0x03a00424
+#define BCHP_FPM_POOL_1_FPM_REG_START                      0x03a00600
+#define BCHP_FPM_POOL_1_FPM_REG_END                        0x03a00624
+#define BCHP_FPM_SEARCH_0_FPM_REG_START                    0x03a04000
+#define BCHP_FPM_SEARCH_0_FPM_REG_END                      0x03a048b8
+#define BCHP_FPM_SEARCH_1_FPM_REG_START                    0x03a05000
+#define BCHP_FPM_SEARCH_1_FPM_REG_END                      0x03a058b8
+#define BCHP_FPM_MULTI_0_FPM_REG_START                     0x03a10000
+#define BCHP_FPM_MULTI_0_FPM_REG_END                       0x03a13ff8
+#define BCHP_FPM_MULTI_1_FPM_REG_START                     0x03a20000
+#define BCHP_FPM_MULTI_1_FPM_REG_END                       0x03a23ff8
+#define BCHP_REGS_FPM_REG_START                            0x03a30000
+#define BCHP_REGS_FPM_REG_END                              0x03a30130
+#define BCHP_GenInt_PER_REG_START                          0x03c00000
+#define BCHP_GenInt_PER_REG_END                            0x03c00048
+#define BCHP_IntSet0_PER_REG_START                         0x03c00100
+#define BCHP_IntSet0_PER_REG_END                           0x03c0018c
+#define BCHP_IntSet1_PER_REG_START                         0x03c00200
+#define BCHP_IntSet1_PER_REG_END                           0x03c0028c
+#define BCHP_IntSet2_PER_REG_START                         0x03c00300
+#define BCHP_IntSet2_PER_REG_END                           0x03c0038c
+#define BCHP_PERIPH_TIMER_PER_REG_START                    0x03c00400
+#define BCHP_PERIPH_TIMER_PER_REG_END                      0x03c00438
+#define BCHP_GPIO_PER_REG_START                            0x03c00500
+#define BCHP_GPIO_PER_REG_END                              0x03c00578
+#define BCHP_BROM_GEN_PER_REG_START                        0x03c00600
+#define BCHP_BROM_GEN_PER_REG_END                          0x03c00608
+#define BCHP_BROM_SEC1_PER_REG_START                       0x03c00620
+#define BCHP_BROM_SEC1_PER_REG_END                         0x03c00630
+#define BCHP_UART0_PER_REG_START                           0x03c00640
+#define BCHP_UART0_PER_REG_END                             0x03c00654
+#define BCHP_UART1_PER_REG_START                           0x03c00660
+#define BCHP_UART1_PER_REG_END                             0x03c00674
+#define BCHP_I2C_DUAL_CORE1_PER_REG_START                  0x03c00700
+#define BCHP_I2C_DUAL_CORE1_PER_REG_END                    0x03c00754
+#define BCHP_I2C_DUAL_CORE2_PER_REG_START                  0x03c00780
+#define BCHP_I2C_DUAL_CORE2_PER_REG_END                    0x03c007d4
+#define BCHP_LED_PER_REG_START                             0x03c009c0
+#define BCHP_LED_PER_REG_END                               0x03c009ec
+#define BCHP_DIAG_MEM_TOP_PER_REG_START                    0x03c00a00
+#define BCHP_DIAG_MEM_TOP_PER_REG_END                      0x03c00b00
+#define BCHP_GLOBALCNTRL_PER_REG_START                     0x03c01000
+#define BCHP_GLOBALCNTRL_PER_REG_END                       0x03c01018
+#define BCHP_PINGPONG_0_PER_REG_START                      0x03c01080
+#define BCHP_PINGPONG_0_PER_REG_END                        0x03c010bc
+#define BCHP_PINGPONG_1_PER_REG_START                      0x03c010c0
+#define BCHP_PINGPONG_1_PER_REG_END                        0x03c010fc
+#define BCHP_PROFILE_0_PER_REG_START                       0x03c01100
+#define BCHP_PROFILE_0_PER_REG_END                         0x03c0111c
+#define BCHP_PROFILE_1_PER_REG_START                       0x03c01120
+#define BCHP_PROFILE_1_PER_REG_END                         0x03c0113c
+#define BCHP_PROFILE_2_PER_REG_START                       0x03c01140
+#define BCHP_PROFILE_2_PER_REG_END                         0x03c0115c
+#define BCHP_PROFILE_3_PER_REG_START                       0x03c01160
+#define BCHP_PROFILE_3_PER_REG_END                         0x03c0117c
+#define BCHP_PROFILE_4_PER_REG_START                       0x03c01180
+#define BCHP_PROFILE_4_PER_REG_END                         0x03c0119c
+#define BCHP_PROFILE_5_PER_REG_START                       0x03c011a0
+#define BCHP_PROFILE_5_PER_REG_END                         0x03c011bc
+#define BCHP_PROFILE_6_PER_REG_START                       0x03c011c0
+#define BCHP_PROFILE_6_PER_REG_END                         0x03c011dc
+#define BCHP_PROFILE_7_PER_REG_START                       0x03c011e0
+#define BCHP_PROFILE_7_PER_REG_END                         0x03c011fc
+#define BCHP_FIFO_0_PER_REG_START                          0x03c01200
+#define BCHP_FIFO_0_PER_REG_END                            0x03c013ff
+#define BCHP_FIFO_1_PER_REG_START                          0x03c01400
+#define BCHP_FIFO_1_PER_REG_END                            0x03c015ff
+#define BCHP_PERIPH_MISC_PER_REG_START                     0x03c02600
+#define BCHP_PERIPH_MISC_PER_REG_END                       0x03c026d0
+#define BCHP_PMB_MASTER_PER_REG_START                      0x03c03000
+#define BCHP_PMB_MASTER_PER_REG_END                        0x03c0300c
+#define BCHP_DTP_CFGCTL_PER_REG_START                      0x03c03100
+#define BCHP_DTP_CFGCTL_PER_REG_END                        0x03c0310c
+#define BCHP_DTP_RESERVED_PER_REG_START                    0x03c03110
+#define BCHP_DTP_RESERVED_PER_REG_END                      0x03c0311c
+#define BCHP_DTP_SOFTRESET_PER_REG_START                   0x03c03120
+#define BCHP_DTP_SOFTRESET_PER_REG_END                     0x03c03120
+#define BCHP_DTP_ZONE0_PER_REG_START                       0x03c03140
+#define BCHP_DTP_ZONE0_PER_REG_END                         0x03c0314c
+#define BCHP_DTP_ZONE1_PER_REG_START                       0x03c03150
+#define BCHP_DTP_ZONE1_PER_REG_END                         0x03c0315c
+#define BCHP_DTP_ZONE2_PER_REG_START                       0x03c03160
+#define BCHP_DTP_ZONE2_PER_REG_END                         0x03c0316c
+#define BCHP_DFAP_CFGCTL_PER_REG_START                     0x03c07100
+#define BCHP_DFAP_CFGCTL_PER_REG_END                       0x03c0710c
+#define BCHP_DFAP_RESERVED_PER_REG_START                   0x03c07110
+#define BCHP_DFAP_RESERVED_PER_REG_END                     0x03c0711c
+#define BCHP_DFAP_SOFTRESET_PER_REG_START                  0x03c07120
+#define BCHP_DFAP_SOFTRESET_PER_REG_END                    0x03c07120
+#define BCHP_DFAP_ZONE0_PER_REG_START                      0x03c07140
+#define BCHP_DFAP_ZONE0_PER_REG_END                        0x03c0714c
+#define BCHP_DFAP_ZONE1_PER_REG_START                      0x03c07150
+#define BCHP_DFAP_ZONE1_PER_REG_END                        0x03c0715c
+#define BCHP_DFAP_ZONE2_PER_REG_START                      0x03c07160
+#define BCHP_DFAP_ZONE2_PER_REG_END                        0x03c0716c
+#define BCHP_D3DSMAC32_CFGCTL_PER_REG_START                0x03c0b100
+#define BCHP_D3DSMAC32_CFGCTL_PER_REG_END                  0x03c0b10c
+#define BCHP_D3DSMAC32_RESERVED_PER_REG_START              0x03c0b110
+#define BCHP_D3DSMAC32_RESERVED_PER_REG_END                0x03c0b11c
+#define BCHP_D3DSMAC32_SOFTRESET_PER_REG_START             0x03c0b120
+#define BCHP_D3DSMAC32_SOFTRESET_PER_REG_END               0x03c0b120
+#define BCHP_D3DSMAC32_ZONE0_PER_REG_START                 0x03c0b140
+#define BCHP_D3DSMAC32_ZONE0_PER_REG_END                   0x03c0b14c
+#define BCHP_D3DSMAC32_ZONE1_PER_REG_START                 0x03c0b150
+#define BCHP_D3DSMAC32_ZONE1_PER_REG_END                   0x03c0b15c
+#define BCHP_D3DSMAC32_ZONE2_PER_REG_START                 0x03c0b160
+#define BCHP_D3DSMAC32_ZONE2_PER_REG_END                   0x03c0b16c
+#define BCHP_D3DSMAC32_ZONE3_PER_REG_START                 0x03c0b170
+#define BCHP_D3DSMAC32_ZONE3_PER_REG_END                   0x03c0b17c
+#define BCHP_D3DSMAC32_ZONE4_PER_REG_START                 0x03c0b180
+#define BCHP_D3DSMAC32_ZONE4_PER_REG_END                   0x03c0b18c
+#define BCHP_D3DSMAC32_ZONE5_PER_REG_START                 0x03c0b190
+#define BCHP_D3DSMAC32_ZONE5_PER_REG_END                   0x03c0b19c
+#define BCHP_DSMACOFDA_CFGCTL_PER_REG_START                0x03c0f100
+#define BCHP_DSMACOFDA_CFGCTL_PER_REG_END                  0x03c0f10c
+#define BCHP_DSMACOFDA_RESERVED_PER_REG_START              0x03c0f110
+#define BCHP_DSMACOFDA_RESERVED_PER_REG_END                0x03c0f11c
+#define BCHP_DSMACOFDA_SOFTRESET_PER_REG_START             0x03c0f120
+#define BCHP_DSMACOFDA_SOFTRESET_PER_REG_END               0x03c0f120
+#define BCHP_DSMACOFDA_ZONE0_PER_REG_START                 0x03c0f140
+#define BCHP_DSMACOFDA_ZONE0_PER_REG_END                   0x03c0f14c
+#define BCHP_DSMACSFDB_CFGCTL_PER_REG_START                0x03c13100
+#define BCHP_DSMACSFDB_CFGCTL_PER_REG_END                  0x03c1310c
+#define BCHP_DSMACSFDB_RESERVED_PER_REG_START              0x03c13110
+#define BCHP_DSMACSFDB_RESERVED_PER_REG_END                0x03c1311c
+#define BCHP_DSMACSFDB_SOFTRESET_PER_REG_START             0x03c13120
+#define BCHP_DSMACSFDB_SOFTRESET_PER_REG_END               0x03c13120
+#define BCHP_DSMACSFDB_ZONE0_PER_REG_START                 0x03c13140
+#define BCHP_DSMACSFDB_ZONE0_PER_REG_END                   0x03c1314c
+#define BCHP_UTP_CFGCTL_PER_REG_START                      0x03c17100
+#define BCHP_UTP_CFGCTL_PER_REG_END                        0x03c1710c
+#define BCHP_UTP_RESERVED_PER_REG_START                    0x03c17110
+#define BCHP_UTP_RESERVED_PER_REG_END                      0x03c1711c
+#define BCHP_UTP_SOFTRESET_PER_REG_START                   0x03c17120
+#define BCHP_UTP_SOFTRESET_PER_REG_END                     0x03c17120
+#define BCHP_UTP_ZONE0_PER_REG_START                       0x03c17140
+#define BCHP_UTP_ZONE0_PER_REG_END                         0x03c1714c
+#define BCHP_UTP_ZONE1_PER_REG_START                       0x03c17150
+#define BCHP_UTP_ZONE1_PER_REG_END                         0x03c1715c
+#define BCHP_UTP_ZONE2_PER_REG_START                       0x03c17160
+#define BCHP_UTP_ZONE2_PER_REG_END                         0x03c1716c
+#define BCHP_UTP_ZONE3_PER_REG_START                       0x03c17170
+#define BCHP_UTP_ZONE3_PER_REG_END                         0x03c1717c
+#define BCHP_UTP_ZONE4_PER_REG_START                       0x03c17180
+#define BCHP_UTP_ZONE4_PER_REG_END                         0x03c1718c
+#define BCHP_PERIPH_CFGCTL_PER_REG_START                   0x03c1b100
+#define BCHP_PERIPH_CFGCTL_PER_REG_END                     0x03c1b10c
+#define BCHP_PERIPH_RESERVED_PER_REG_START                 0x03c1b110
+#define BCHP_PERIPH_RESERVED_PER_REG_END                   0x03c1b11c
+#define BCHP_PERIPH_SOFTRESET_PER_REG_START                0x03c1b120
+#define BCHP_PERIPH_SOFTRESET_PER_REG_END                  0x03c1b120
+#define BCHP_PERIPH_ZONE0_PER_REG_START                    0x03c1b140
+#define BCHP_PERIPH_ZONE0_PER_REG_END                      0x03c1b14c
+#define BCHP_PERIPH_ZONE1_PER_REG_START                    0x03c1b150
+#define BCHP_PERIPH_ZONE1_PER_REG_END                      0x03c1b15c
+#define BCHP_PERIPH_ZONE2_PER_REG_START                    0x03c1b160
+#define BCHP_PERIPH_ZONE2_PER_REG_END                      0x03c1b16c
+#define BCHP_FPM_CFGCTL_PER_REG_START                      0x03c1f100
+#define BCHP_FPM_CFGCTL_PER_REG_END                        0x03c1f10c
+#define BCHP_FPM_RESERVED_PER_REG_START                    0x03c1f110
+#define BCHP_FPM_RESERVED_PER_REG_END                      0x03c1f11c
+#define BCHP_FPM_SOFTRESET_PER_REG_START                   0x03c1f120
+#define BCHP_FPM_SOFTRESET_PER_REG_END                     0x03c1f120
+#define BCHP_FPM_ZONE0_PER_REG_START                       0x03c1f140
+#define BCHP_FPM_ZONE0_PER_REG_END                         0x03c1f14c
+#define BCHP_CPUC_CFGCTL_PER_REG_START                     0x03c23100
+#define BCHP_CPUC_CFGCTL_PER_REG_END                       0x03c2310c
+#define BCHP_CPUC_RESERVED_PER_REG_START                   0x03c23110
+#define BCHP_CPUC_RESERVED_PER_REG_END                     0x03c2311c
+#define BCHP_CPUC_SOFTRESET_PER_REG_START                  0x03c23120
+#define BCHP_CPUC_SOFTRESET_PER_REG_END                    0x03c23120
+#define BCHP_CPUC_ZONE0_PER_REG_START                      0x03c23140
+#define BCHP_CPUC_ZONE0_PER_REG_END                        0x03c2314c
+#define BCHP_DECT_CFGCTL_PER_REG_START                     0x03c27100
+#define BCHP_DECT_CFGCTL_PER_REG_END                       0x03c2710c
+#define BCHP_DECT_RESERVED_PER_REG_START                   0x03c27110
+#define BCHP_DECT_RESERVED_PER_REG_END                     0x03c2711c
+#define BCHP_DECT_SOFTRESET_PER_REG_START                  0x03c27120
+#define BCHP_DECT_SOFTRESET_PER_REG_END                    0x03c27120
+#define BCHP_DECT_ZONE0_PER_REG_START                      0x03c27140
+#define BCHP_DECT_ZONE0_PER_REG_END                        0x03c2714c
+#define BCHP_APM_CFGCTL_PER_REG_START                      0x03c2b100
+#define BCHP_APM_CFGCTL_PER_REG_END                        0x03c2b10c
+#define BCHP_APM_RESERVED_PER_REG_START                    0x03c2b110
+#define BCHP_APM_RESERVED_PER_REG_END                      0x03c2b11c
+#define BCHP_APM_SOFTRESET_PER_REG_START                   0x03c2b120
+#define BCHP_APM_SOFTRESET_PER_REG_END                     0x03c2b120
+#define BCHP_APM_ZONE0_PER_REG_START                       0x03c2b140
+#define BCHP_APM_ZONE0_PER_REG_END                         0x03c2b14c
+#define BCHP_APM_ZONE1_PER_REG_START                       0x03c2b150
+#define BCHP_APM_ZONE1_PER_REG_END                         0x03c2b15c
+#define BCHP_APM_ZONE2_PER_REG_START                       0x03c2b160
+#define BCHP_APM_ZONE2_PER_REG_END                         0x03c2b16c
+#define BCHP_APM_ZONE3_PER_REG_START                       0x03c2b170
+#define BCHP_APM_ZONE3_PER_REG_END                         0x03c2b17c
+#define BCHP_APM_ZONE4_PER_REG_START                       0x03c2b180
+#define BCHP_APM_ZONE4_PER_REG_END                         0x03c2b18c
+#define BCHP_UNIMAC_CFGCTL_PER_REG_START                   0x03c2f100
+#define BCHP_UNIMAC_CFGCTL_PER_REG_END                     0x03c2f10c
+#define BCHP_UNIMAC_RESERVED_PER_REG_START                 0x03c2f110
+#define BCHP_UNIMAC_RESERVED_PER_REG_END                   0x03c2f11c
+#define BCHP_UNIMAC_SOFTRESET_PER_REG_START                0x03c2f120
+#define BCHP_UNIMAC_SOFTRESET_PER_REG_END                  0x03c2f120
+#define BCHP_UNIMAC_ZONE0_PER_REG_START                    0x03c2f140
+#define BCHP_UNIMAC_ZONE0_PER_REG_END                      0x03c2f14c
+#define BCHP_USMAC_CFGCTL_PER_REG_START                    0x03c33100
+#define BCHP_USMAC_CFGCTL_PER_REG_END                      0x03c3310c
+#define BCHP_USMAC_RESERVED_PER_REG_START                  0x03c33110
+#define BCHP_USMAC_RESERVED_PER_REG_END                    0x03c3311c
+#define BCHP_USMAC_SOFTRESET_PER_REG_START                 0x03c33120
+#define BCHP_USMAC_SOFTRESET_PER_REG_END                   0x03c33120
+#define BCHP_USMAC_ZONE0_PER_REG_START                     0x03c33140
+#define BCHP_USMAC_ZONE0_PER_REG_END                       0x03c3314c
+#define BCHP_USMAC_ZONE1_PER_REG_START                     0x03c33150
+#define BCHP_USMAC_ZONE1_PER_REG_END                       0x03c3315c
+#define BCHP_USMAC_ZONE2_PER_REG_START                     0x03c33160
+#define BCHP_USMAC_ZONE2_PER_REG_END                       0x03c3316c
+#define BCHP_USMAC_ZONE3_PER_REG_START                     0x03c33170
+#define BCHP_USMAC_ZONE3_PER_REG_END                       0x03c3317c
+#define BCHP_USMAC_ZONE4_PER_REG_START                     0x03c33180
+#define BCHP_USMAC_ZONE4_PER_REG_END                       0x03c3318c
+#define BCHP_USMAC_ZONE5_PER_REG_START                     0x03c33190
+#define BCHP_USMAC_ZONE5_PER_REG_END                       0x03c3319c
+#define BCHP_USMAC_ZONE6_PER_REG_START                     0x03c331a0
+#define BCHP_USMAC_ZONE6_PER_REG_END                       0x03c331ac
+#define BCHP_USMAC_ZONE7_PER_REG_START                     0x03c331b0
+#define BCHP_USMAC_ZONE7_PER_REG_END                       0x03c331bc
+#define BCHP_USMAC_ZONE8_PER_REG_START                     0x03c331c0
+#define BCHP_USMAC_ZONE8_PER_REG_END                       0x03c331cc
+#define BCHP_USMAC_ZONE9_PER_REG_START                     0x03c331d0
+#define BCHP_USMAC_ZONE9_PER_REG_END                       0x03c331dc
+#define BCHP_USMAC_ZONE10_PER_REG_START                    0x03c331e0
+#define BCHP_USMAC_ZONE10_PER_REG_END                      0x03c331ec
+#define BCHP_USMAC_ZONE11_PER_REG_START                    0x03c331f0
+#define BCHP_USMAC_ZONE11_PER_REG_END                      0x03c331fc
+#define BCHP_USMAC_ZONE12_PER_REG_START                    0x03c33200
+#define BCHP_USMAC_ZONE12_PER_REG_END                      0x03c3320c
+#define BCHP_TC8X_CFGCTL_PER_REG_START                     0x03c37100
+#define BCHP_TC8X_CFGCTL_PER_REG_END                       0x03c3710c
+#define BCHP_TC8X_RESERVED_PER_REG_START                   0x03c37110
+#define BCHP_TC8X_RESERVED_PER_REG_END                     0x03c3711c
+#define BCHP_TC8X_SOFTRESET_PER_REG_START                  0x03c37120
+#define BCHP_TC8X_SOFTRESET_PER_REG_END                    0x03c37120
+#define BCHP_TC8X_ZONE0_PER_REG_START                      0x03c37140
+#define BCHP_TC8X_ZONE0_PER_REG_END                        0x03c3714c
+#define BCHP_TC8X_ZONE1_PER_REG_START                      0x03c37150
+#define BCHP_TC8X_ZONE1_PER_REG_END                        0x03c3715c
+#define BCHP_TC8X_ZONE2_PER_REG_START                      0x03c37160
+#define BCHP_TC8X_ZONE2_PER_REG_END                        0x03c3716c
+#define BCHP_TC8X_ZONE3_PER_REG_START                      0x03c37170
+#define BCHP_TC8X_ZONE3_PER_REG_END                        0x03c3717c
+#define BCHP_TC8X_ZONE4_PER_REG_START                      0x03c37180
+#define BCHP_TC8X_ZONE4_PER_REG_END                        0x03c3718c
+#define BCHP_TC8X_ZONE5_PER_REG_START                      0x03c37190
+#define BCHP_TC8X_ZONE5_PER_REG_END                        0x03c3719c
+#define BCHP_TC8X_ZONE6_PER_REG_START                      0x03c371a0
+#define BCHP_TC8X_ZONE6_PER_REG_END                        0x03c371ac
+#define BCHP_TC8X_ZONE7_PER_REG_START                      0x03c371b0
+#define BCHP_TC8X_ZONE7_PER_REG_END                        0x03c371bc
+#define BCHP_TC8X_ZONE8_PER_REG_START                      0x03c371c0
+#define BCHP_TC8X_ZONE8_PER_REG_END                        0x03c371cc
+#define BCHP_TCOFDM_CFGCTL_PER_REG_START                   0x03c3b100
+#define BCHP_TCOFDM_CFGCTL_PER_REG_END                     0x03c3b10c
+#define BCHP_TCOFDM_RESERVED_PER_REG_START                 0x03c3b110
+#define BCHP_TCOFDM_RESERVED_PER_REG_END                   0x03c3b11c
+#define BCHP_TCOFDM_SOFTRESET_PER_REG_START                0x03c3b120
+#define BCHP_TCOFDM_SOFTRESET_PER_REG_END                  0x03c3b120
+#define BCHP_TCOFDM_ZONE0_PER_REG_START                    0x03c3b140
+#define BCHP_TCOFDM_ZONE0_PER_REG_END                      0x03c3b14c
+#define BCHP_TCOFDM_ZONE1_PER_REG_START                    0x03c3b150
+#define BCHP_TCOFDM_ZONE1_PER_REG_END                      0x03c3b15c
+#define BCHP_TCOFDM_ZONE2_PER_REG_START                    0x03c3b160
+#define BCHP_TCOFDM_ZONE2_PER_REG_END                      0x03c3b16c
+#define BCHP_TCOFDM_ZONE3_PER_REG_START                    0x03c3b170
+#define BCHP_TCOFDM_ZONE3_PER_REG_END                      0x03c3b17c
+#define BCHP_TCOFDM_ZONE4_PER_REG_START                    0x03c3b180
+#define BCHP_TCOFDM_ZONE4_PER_REG_END                      0x03c3b18c
+#define BCHP_DAVIC_CFGCTL_PER_REG_START                    0x03c3f100
+#define BCHP_DAVIC_CFGCTL_PER_REG_END                      0x03c3f10c
+#define BCHP_DAVIC_RESERVED_PER_REG_START                  0x03c3f110
+#define BCHP_DAVIC_RESERVED_PER_REG_END                    0x03c3f11c
+#define BCHP_DAVIC_SOFTRESET_PER_REG_START                 0x03c3f120
+#define BCHP_DAVIC_SOFTRESET_PER_REG_END                   0x03c3f120
+#define BCHP_DAVIC_ZONE0_PER_REG_START                     0x03c3f140
+#define BCHP_DAVIC_ZONE0_PER_REG_END                       0x03c3f14c
+#define BCHP_MIPS_CFGCTL_PER_REG_START                     0x03c43100
+#define BCHP_MIPS_CFGCTL_PER_REG_END                       0x03c4310c
+#define BCHP_MIPS_RESERVED_PER_REG_START                   0x03c43110
+#define BCHP_MIPS_RESERVED_PER_REG_END                     0x03c4311c
+#define BCHP_MIPS_SOFTRESET_PER_REG_START                  0x03c43120
+#define BCHP_MIPS_SOFTRESET_PER_REG_END                    0x03c43120
+#define BCHP_MIPS_ZONE0_PER_REG_START                      0x03c43140
+#define BCHP_MIPS_ZONE0_PER_REG_END                        0x03c4314c
+#define BCHP_USTOP_CFGCTL_PER_REG_START                    0x03c47100
+#define BCHP_USTOP_CFGCTL_PER_REG_END                      0x03c4710c
+#define BCHP_USTOP_RESERVED_PER_REG_START                  0x03c47110
+#define BCHP_USTOP_RESERVED_PER_REG_END                    0x03c4711c
+#define BCHP_USTOP_SOFTRESET_PER_REG_START                 0x03c47120
+#define BCHP_USTOP_SOFTRESET_PER_REG_END                   0x03c47120
+#define BCHP_USTOP_ZONE0_PER_REG_START                     0x03c47140
+#define BCHP_USTOP_ZONE0_PER_REG_END                       0x03c4714c
+#define BCHP_LEAP_CFGCTL_PER_REG_START                     0x03c4b100
+#define BCHP_LEAP_CFGCTL_PER_REG_END                       0x03c4b10c
+#define BCHP_LEAP_RESERVED_PER_REG_START                   0x03c4b110
+#define BCHP_LEAP_RESERVED_PER_REG_END                     0x03c4b11c
+#define BCHP_LEAP_SOFTRESET_PER_REG_START                  0x03c4b120
+#define BCHP_LEAP_SOFTRESET_PER_REG_END                    0x03c4b120
+#define BCHP_LEAP_ZONE0_PER_REG_START                      0x03c4b140
+#define BCHP_LEAP_ZONE0_PER_REG_END                        0x03c4b14c
+#define BCHP_EMC_CFGCTL_PER_REG_START                      0x03c4f100
+#define BCHP_EMC_CFGCTL_PER_REG_END                        0x03c4f10c
+#define BCHP_EMC_RESERVED_PER_REG_START                    0x03c4f110
+#define BCHP_EMC_RESERVED_PER_REG_END                      0x03c4f11c
+#define BCHP_EMC_SOFTRESET_PER_REG_START                   0x03c4f120
+#define BCHP_EMC_SOFTRESET_PER_REG_END                     0x03c4f120
+#define BCHP_EMC_ZONE0_PER_REG_START                       0x03c4f140
+#define BCHP_EMC_ZONE0_PER_REG_END                         0x03c4f14c
+#define BCHP_CNTLERRPORT_PERIPH_REG_START                  0x03e00000
+#define BCHP_CNTLERRPORT_PERIPH_REG_END                    0x03e000e4
+#define BCHP_REQA0_PERIPH_REG_START                        0x03e00400
+#define BCHP_REQA0_PERIPH_REG_END                          0x03e0048c
+#define BCHP_REPA0_PERIPH_REG_START                        0x03e00500
+#define BCHP_REPA0_PERIPH_REG_END                          0x03e0058c
+#define BCHP_REQA1_PERIPH_REG_START                        0x03e00600
+#define BCHP_REQA1_PERIPH_REG_END                          0x03e0068c
+#define BCHP_REPA1_PERIPH_REG_START                        0x03e00700
+#define BCHP_REPA1_PERIPH_REG_END                          0x03e0078c
+#define BCHP_REQB0_PERIPH_REG_START                        0x03e00800
+#define BCHP_REQB0_PERIPH_REG_END                          0x03e0088c
+#define BCHP_REPB0_PERIPH_REG_START                        0x03e00900
+#define BCHP_REPB0_PERIPH_REG_END                          0x03e0098c
+#define BCHP_REQB1_PERIPH_REG_START                        0x03e00a00
+#define BCHP_REQB1_PERIPH_REG_END                          0x03e00a8c
+#define BCHP_REPB1_PERIPH_REG_START                        0x03e00b00
+#define BCHP_REPB1_PERIPH_REG_END                          0x03e00b8c
+#define BCHP_REQC0_PERIPH_REG_START                        0x03e00c00
+#define BCHP_REQC0_PERIPH_REG_END                          0x03e00c8c
+#define BCHP_REPC0_PERIPH_REG_START                        0x03e00d00
+#define BCHP_REPC0_PERIPH_REG_END                          0x03e00d8c
+#define BCHP_REQC1_PERIPH_REG_START                        0x03e00e00
+#define BCHP_REQC1_PERIPH_REG_END                          0x03e00e8c
+#define BCHP_REPC1_PERIPH_REG_START                        0x03e00f00
+#define BCHP_REPC1_PERIPH_REG_END                          0x03e00f8c
+#define BCHP_SWITCH_CORE_REG_START                         0x04e00000
+#define BCHP_SWITCH_CORE_REG_END                           0x04e3fffc
+#define BCHP_SWITCH_REG_REG_START                          0x04e40000
+#define BCHP_SWITCH_REG_REG_END                            0x04e401b0
+#define BCHP_SWITCH_INDIR_RW_REG_START                     0x04e40300
+#define BCHP_SWITCH_INDIR_RW_REG_END                       0x04e40314
+#define BCHP_SWITCH_INTRL2_0_REG_START                     0x04e40340
+#define BCHP_SWITCH_INTRL2_0_REG_END                       0x04e4036c
+#define BCHP_SWITCH_INTRL2_1_REG_START                     0x04e40380
+#define BCHP_SWITCH_INTRL2_1_REG_END                       0x04e403ac
+#define BCHP_SWITCH_MDIO_REG_START                         0x04e403c0
+#define BCHP_SWITCH_MDIO_REG_END                           0x04e403c4
+#define BCHP_SWITCH_FCB_REG_START                          0x04e40400
+#define BCHP_SWITCH_FCB_REG_END                            0x04e40430
+#define BCHP_SWITCH_ACB_REG_START                          0x04e40600
+#define BCHP_SWITCH_ACB_REG_END                            0x04e40804
+#define BCHP_MEM_COMMON_1_REG_START                        0x05000000
+#define BCHP_MEM_COMMON_1_REG_END                          0x05000004
+#define BCHP_MEM_PRIVATE_1_REG_START                       0x05010000
+#define BCHP_MEM_PRIVATE_1_REG_END                         0x05010004
+#define BCHP_MEM_INST_MAIN_1_REG_START                     0x05020000
+#define BCHP_MEM_INST_MAIN_1_REG_END                       0x05020000
+#define BCHP_MEM_CNTXT_MAIN_1_REG_START                    0x05028000
+#define BCHP_MEM_CNTXT_MAIN_1_REG_END                      0x05028000
+#define BCHP_MEM_PRED_MAIN_1_REG_START                     0x0502c000
+#define BCHP_MEM_PRED_MAIN_1_REG_END                       0x0502c37e
+#define BCHP_MEM_INST_PICO_1_REG_START                     0x05030000
+#define BCHP_MEM_INST_PICO_1_REG_END                       0x05030000
+#define BCHP_MEM_CNTXT_PICO_1_REG_START                    0x05038000
+#define BCHP_MEM_CNTXT_PICO_1_REG_END                      0x05038000
+#define BCHP_MEM_PRED_PICO_1_REG_START                     0x0503c000
+#define BCHP_MEM_PRED_PICO_1_REG_END                       0x0503c1fe
+#define BCHP_MEM_COMMON_2_REG_START                        0x05040000
+#define BCHP_MEM_COMMON_2_REG_END                          0x05040004
+#define BCHP_MEM_PRIVATE_2_REG_START                       0x05050000
+#define BCHP_MEM_PRIVATE_2_REG_END                         0x05050004
+#define BCHP_MEM_INST_MAIN_2_REG_START                     0x05060000
+#define BCHP_MEM_INST_MAIN_2_REG_END                       0x05060000
+#define BCHP_MEM_CNTXT_MAIN_2_REG_START                    0x05068000
+#define BCHP_MEM_CNTXT_MAIN_2_REG_END                      0x05068000
+#define BCHP_MEM_PRED_MAIN_2_REG_START                     0x0506c000
+#define BCHP_MEM_PRED_MAIN_2_REG_END                       0x0506c37e
+#define BCHP_MEM_INST_PICO_2_REG_START                     0x05070000
+#define BCHP_MEM_INST_PICO_2_REG_END                       0x05070000
+#define BCHP_MEM_CNTXT_PICO_2_REG_START                    0x05078000
+#define BCHP_MEM_CNTXT_PICO_2_REG_END                      0x05078000
+#define BCHP_MEM_PRED_PICO_2_REG_START                     0x0507c000
+#define BCHP_MEM_PRED_PICO_2_REG_END                       0x0507c1fe
+#define BCHP_CFG_REGS_1_REG_START                          0x05099000
+#define BCHP_CFG_REGS_1_REG_END                            0x050991c8
+#define BCHP_DBG_REGS_1_REG_START                          0x050991d0
+#define BCHP_DBG_REGS_1_REG_END                            0x050992b8
+#define BCHP_CFG_REGS_2_REG_START                          0x0509a000
+#define BCHP_CFG_REGS_2_REG_END                            0x0509a1c8
+#define BCHP_DBG_REGS_2_REG_START                          0x0509a1d0
+#define BCHP_DBG_REGS_2_REG_END                            0x0509a2b8
+#define BCHP_MEM_ENTRY_REG_START                           0x050a0000
+#define BCHP_MEM_ENTRY_REG_END                             0x050a0000
+#define BCHP_CONFIGURATIONS_REG_START                      0x050c0000
+#define BCHP_CONFIGURATIONS_REG_END                        0x050c001c
+#define BCHP_PM_COUNTERS_REG_START                         0x050c0100
+#define BCHP_PM_COUNTERS_REG_END                           0x050c01fc
+#define BCHP_DEBUG_REG_START                               0x050c0200
+#define BCHP_DEBUG_REG_END                                 0x050c0208
+#define A0_BCHP_REGS_REG_START                             0x050c4000
+#define A0_BCHP_REGS_REG_END                               0x050c4130
+#define BCHP_REGS_REG_START                                0x050c8000
+#define BCHP_REGS_REG_END                                  0x050c81a8
+#define BCHP_LOOKUP_CONFIGURATION_REG_START                0x050d0000
+#define BCHP_LOOKUP_CONFIGURATION_REG_END                  0x050d0250
+#define BCHP_PARSER_CORE_CONFIGURATION_REG_START           0x050d0400
+#define BCHP_PARSER_CORE_CONFIGURATION_REG_END             0x050d0560
+#define BCHP_GENERAL_CONFIGURATION_REG_START               0x050d0800
+#define BCHP_GENERAL_CONFIGURATION_REG_END                 0x050d0ad0
+#define BCHP_CONFIG_DMA_REGS_1_REG_START                   0x050d1000
+#define BCHP_CONFIG_DMA_REGS_1_REG_END                     0x050d10a8
+#define BCHP_DEBUG_DMA_REGS_1_REG_START                    0x050d1100
+#define BCHP_DEBUG_DMA_REGS_1_REG_END                      0x050d1218
+#define BCHP_CONFIG_DMA_REGS_2_REG_START                   0x050d1800
+#define BCHP_CONFIG_DMA_REGS_2_REG_END                     0x050d18a8
+#define BCHP_DEBUG_DMA_REGS_2_REG_START                    0x050d1900
+#define BCHP_DEBUG_DMA_REGS_2_REG_END                      0x050d1a18
+#define BCHP_BRDG_REG_UBUS_MASTER_1_REG_START              0x050d2000
+#define BCHP_BRDG_REG_UBUS_MASTER_1_REG_END                0x050d2014
+#define BCHP_BRDG_REG_UBUS_MASTER_2_REG_START              0x050d2400
+#define BCHP_BRDG_REG_UBUS_MASTER_2_REG_END                0x050d2414
+#define BCHP_BRDG_REG_UBUS_MASTER_3_REG_START              0x050d2800
+#define BCHP_BRDG_REG_UBUS_MASTER_3_REG_END                0x050d2814
+#define A0_BCHP_BRDG_REG_REG_START                         0x050d2c00
+#define A0_BCHP_BRDG_REG_REG_END                           0x050d2c08
+#define BCHP_EGPHY_REG_START                               0x050d3000
+#define BCHP_EGPHY_REG_END                                 0x050d3014
+#define BCHP_BRDG_REG_REG_START                            0x050d3c00
+#define BCHP_BRDG_REG_REG_END                              0x050d3c14
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_0_REG_START         0x050d4000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_0_REG_END           0x050d464c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_1_REG_START         0x050d5000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_1_REG_END           0x050d564c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_2_REG_START         0x050d6000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_2_REG_END           0x050d664c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_0Module_REG_START 0x050da000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_0Module_REG_END 0x050da180
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_1Module_REG_START 0x050da400
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_1Module_REG_END 0x050da580
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_2Module_REG_START 0x050da800
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_2Module_REG_END 0x050da980
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_1_REG_START            0x050db800
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_1_REG_END              0x050db820
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_2_REG_START            0x050dbc00
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_2_REG_END              0x050dbc20
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_3_REG_START            0x050dc000
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_3_REG_END              0x050dc020
+#define BCHP_GENERAL_CONFIGURATION_RX_1_REG_START          0x050de000
+#define BCHP_GENERAL_CONFIGURATION_RX_1_REG_END            0x050de094
+#define BCHP_PM_COUNTERS_RX_1_REG_START                    0x050de100
+#define BCHP_PM_COUNTERS_RX_1_REG_END                      0x050de144
+#define BCHP_DEBUG_RX_1_REG_START                          0x050de200
+#define BCHP_DEBUG_RX_1_REG_END                            0x050de2cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_1_REG_START           0x050de400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_1_REG_END             0x050de7fc
+#define BCHP_GENERAL_CONFIGURATION_RX_2_REG_START          0x050de800
+#define BCHP_GENERAL_CONFIGURATION_RX_2_REG_END            0x050de894
+#define BCHP_PM_COUNTERS_RX_2_REG_START                    0x050de900
+#define BCHP_PM_COUNTERS_RX_2_REG_END                      0x050de944
+#define BCHP_DEBUG_RX_2_REG_START                          0x050dea00
+#define BCHP_DEBUG_RX_2_REG_END                            0x050deacc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_2_REG_START           0x050dec00
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_2_REG_END             0x050deffc
+#define BCHP_GENERAL_CONFIGURATION_RX_3_REG_START          0x050df000
+#define BCHP_GENERAL_CONFIGURATION_RX_3_REG_END            0x050df094
+#define BCHP_PM_COUNTERS_RX_3_REG_START                    0x050df100
+#define BCHP_PM_COUNTERS_RX_3_REG_END                      0x050df144
+#define BCHP_DEBUG_RX_3_REG_START                          0x050df200
+#define BCHP_DEBUG_RX_3_REG_END                            0x050df2cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_3_REG_START           0x050df400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_3_REG_END             0x050df7fc
+#define BCHP_GENERAL_CONFIGURATION_RX_4_REG_START          0x050e1000
+#define BCHP_GENERAL_CONFIGURATION_RX_4_REG_END            0x050e1094
+#define BCHP_PM_COUNTERS_RX_4_REG_START                    0x050e1100
+#define BCHP_PM_COUNTERS_RX_4_REG_END                      0x050e1144
+#define BCHP_DEBUG_RX_4_REG_START                          0x050e1200
+#define BCHP_DEBUG_RX_4_REG_END                            0x050e12cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_4_REG_START           0x050e1400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_4_REG_END             0x050e17fc
+#define BCHP_GENERAL_CONFIGURATION_RX_5_REG_START          0x050e2000
+#define BCHP_GENERAL_CONFIGURATION_RX_5_REG_END            0x050e2094
+#define BCHP_PM_COUNTERS_RX_5_REG_START                    0x050e2100
+#define BCHP_PM_COUNTERS_RX_5_REG_END                      0x050e2144
+#define BCHP_DEBUG_RX_5_REG_START                          0x050e2200
+#define BCHP_DEBUG_RX_5_REG_END                            0x050e22cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_5_REG_START           0x050e2400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_5_REG_END             0x050e27fc
+#define BCHP_CONFIGURATIONS_TX_1_REG_START                 0x050e8000
+#define BCHP_CONFIGURATIONS_TX_1_REG_END                   0x050e8098
+#define BCHP_DEBUG_TX_1_REG_START                          0x050e8100
+#define BCHP_DEBUG_TX_1_REG_END                            0x050e81ec
+#define BCHP_PD_FIFO_TX_1_REG_START                        0x050e8200
+#define BCHP_PD_FIFO_TX_1_REG_END                          0x050e85fc
+#define BCHP_CONTEXT_TX_1_REG_START                        0x050e8600
+#define BCHP_CONTEXT_TX_1_REG_END                          0x050e869c
+#define BCHP_EPON_PD_FIFO_TX_1_REG_START                   0x050e8700
+#define BCHP_EPON_PD_FIFO_TX_1_REG_END                     0x050e8efc
+#define BCHP_EPON_CFG_TX_1_REG_START                       0x050e9000
+#define BCHP_EPON_CFG_TX_1_REG_END                         0x050e9054
+#define BCHP_EPON_DBG_TX_1_REG_START                       0x050e9100
+#define BCHP_EPON_DBG_TX_1_REG_END                         0x050e9204
+#define BCHP_EPON_STS_FIFO_TX_1_REG_START                  0x050e9700
+#define BCHP_EPON_STS_FIFO_TX_1_REG_END                    0x050e9efc
+#define BCHP_CONFIGURATIONS_TX_2_REG_START                 0x050ea000
+#define BCHP_CONFIGURATIONS_TX_2_REG_END                   0x050ea098
+#define BCHP_DEBUG_TX_2_REG_START                          0x050ea100
+#define BCHP_DEBUG_TX_2_REG_END                            0x050ea1ec
+#define BCHP_PD_FIFO_TX_2_REG_START                        0x050ea200
+#define BCHP_PD_FIFO_TX_2_REG_END                          0x050ea5fc
+#define BCHP_CONTEXT_TX_2_REG_START                        0x050ea600
+#define BCHP_CONTEXT_TX_2_REG_END                          0x050ea69c
+#define BCHP_EPON_PD_FIFO_TX_2_REG_START                   0x050ea700
+#define BCHP_EPON_PD_FIFO_TX_2_REG_END                     0x050eaefc
+#define BCHP_EPON_CFG_TX_2_REG_START                       0x050eb000
+#define BCHP_EPON_CFG_TX_2_REG_END                         0x050eb054
+#define BCHP_EPON_DBG_TX_2_REG_START                       0x050eb100
+#define BCHP_EPON_DBG_TX_2_REG_END                         0x050eb204
+#define BCHP_EPON_STS_FIFO_TX_2_REG_START                  0x050eb700
+#define BCHP_EPON_STS_FIFO_TX_2_REG_END                    0x050ebefc
+#define BCHP_CONFIGURATIONS_TX_3_REG_START                 0x050ec000
+#define BCHP_CONFIGURATIONS_TX_3_REG_END                   0x050ec098
+#define BCHP_DEBUG_TX_3_REG_START                          0x050ec100
+#define BCHP_DEBUG_TX_3_REG_END                            0x050ec1ec
+#define BCHP_PD_FIFO_TX_3_REG_START                        0x050ec200
+#define BCHP_PD_FIFO_TX_3_REG_END                          0x050ec5fc
+#define BCHP_CONTEXT_TX_3_REG_START                        0x050ec600
+#define BCHP_CONTEXT_TX_3_REG_END                          0x050ec69c
+#define BCHP_EPON_PD_FIFO_TX_3_REG_START                   0x050ec700
+#define BCHP_EPON_PD_FIFO_TX_3_REG_END                     0x050ecefc
+#define BCHP_EPON_CFG_TX_3_REG_START                       0x050ed000
+#define BCHP_EPON_CFG_TX_3_REG_END                         0x050ed054
+#define BCHP_EPON_DBG_TX_3_REG_START                       0x050ed100
+#define BCHP_EPON_DBG_TX_3_REG_END                         0x050ed204
+#define BCHP_EPON_STS_FIFO_TX_3_REG_START                  0x050ed700
+#define BCHP_EPON_STS_FIFO_TX_3_REG_END                    0x050edefc
+#define BCHP_CONFIGURATIONS_TX_4_REG_START                 0x050f4000
+#define BCHP_CONFIGURATIONS_TX_4_REG_END                   0x050f4098
+#define BCHP_DEBUG_TX_4_REG_START                          0x050f4100
+#define BCHP_DEBUG_TX_4_REG_END                            0x050f41ec
+#define BCHP_PD_FIFO_TX_4_REG_START                        0x050f4200
+#define BCHP_PD_FIFO_TX_4_REG_END                          0x050f45fc
+#define BCHP_CONTEXT_TX_4_REG_START                        0x050f4600
+#define BCHP_CONTEXT_TX_4_REG_END                          0x050f469c
+#define BCHP_EPON_PD_FIFO_TX_4_REG_START                   0x050f4700
+#define BCHP_EPON_PD_FIFO_TX_4_REG_END                     0x050f4efc
+#define BCHP_EPON_CFG_TX_4_REG_START                       0x050f5000
+#define BCHP_EPON_CFG_TX_4_REG_END                         0x050f5054
+#define BCHP_EPON_DBG_TX_4_REG_START                       0x050f5100
+#define BCHP_EPON_DBG_TX_4_REG_END                         0x050f5204
+#define BCHP_EPON_STS_FIFO_TX_4_REG_START                  0x050f5700
+#define BCHP_EPON_STS_FIFO_TX_4_REG_END                    0x050f5efc
+#define BCHP_CONFIGURATIONS_TX_5_REG_START                 0x050f6000
+#define BCHP_CONFIGURATIONS_TX_5_REG_END                   0x050f6098
+#define BCHP_DEBUG_TX_5_REG_START                          0x050f6100
+#define BCHP_DEBUG_TX_5_REG_END                            0x050f61ec
+#define BCHP_PD_FIFO_TX_5_REG_START                        0x050f6200
+#define BCHP_PD_FIFO_TX_5_REG_END                          0x050f65fc
+#define BCHP_CONTEXT_TX_5_REG_START                        0x050f6600
+#define BCHP_CONTEXT_TX_5_REG_END                          0x050f669c
+#define BCHP_EPON_PD_FIFO_TX_5_REG_START                   0x050f6700
+#define BCHP_EPON_PD_FIFO_TX_5_REG_END                     0x050f6efc
+#define BCHP_EPON_CFG_TX_5_REG_START                       0x050f7000
+#define BCHP_EPON_CFG_TX_5_REG_END                         0x050f7054
+#define BCHP_EPON_DBG_TX_5_REG_START                       0x050f7100
+#define BCHP_EPON_DBG_TX_5_REG_END                         0x050f7204
+#define BCHP_EPON_STS_FIFO_TX_5_REG_START                  0x050f7700
+#define BCHP_EPON_STS_FIFO_TX_5_REG_END                    0x050f7efc
+#define BCHP_NATCACHE_REG_START                            0x050fc000
+#define BCHP_NATCACHE_REG_END                              0x050fc2b0
+#define BCHP_NATCACHE_INDIR_RW_REG_START                   0x050fc400
+#define BCHP_NATCACHE_INDIR_RW_REG_END                     0x050fc45c
+#define BCHP_CNTLERRPORT_G2U_REG_START                     0x07e00000
+#define BCHP_CNTLERRPORT_G2U_REG_END                       0x07e000e4
+#define BCHP_REQA0_G2U_REG_START                           0x07e00400
+#define BCHP_REQA0_G2U_REG_END                             0x07e0048c
+#define BCHP_REPA0_G2U_REG_START                           0x07e00500
+#define BCHP_REPA0_G2U_REG_END                             0x07e0058c
+#define BCHP_REQA1_G2U_REG_START                           0x07e00600
+#define BCHP_REQA1_G2U_REG_END                             0x07e0068c
+#define BCHP_REPA1_G2U_REG_START                           0x07e00700
+#define BCHP_REPA1_G2U_REG_END                             0x07e0078c
+#define BCHP_REQB0_G2U_REG_START                           0x07e00800
+#define BCHP_REQB0_G2U_REG_END                             0x07e0088c
+#define BCHP_REPB0_G2U_REG_START                           0x07e00900
+#define BCHP_REPB0_G2U_REG_END                             0x07e0098c
+#define BCHP_REQB1_G2U_REG_START                           0x07e00a00
+#define BCHP_REQB1_G2U_REG_END                             0x07e00a8c
+#define BCHP_REPB1_G2U_REG_START                           0x07e00b00
+#define BCHP_REPB1_G2U_REG_END                             0x07e00b8c
+#define BCHP_REQC0_G2U_REG_START                           0x07e00c00
+#define BCHP_REQC0_G2U_REG_END                             0x07e00c8c
+#define BCHP_REPC0_G2U_REG_START                           0x07e00d00
+#define BCHP_REPC0_G2U_REG_END                             0x07e00d8c
+#define BCHP_REQC1_G2U_REG_START                           0x07e00e00
+#define BCHP_REQC1_G2U_REG_END                             0x07e00e8c
+#define BCHP_REPC1_G2U_REG_START                           0x07e00f00
+#define BCHP_REPC1_G2U_REG_END                             0x07e00f8c
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x20300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x2030fffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x20310000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x203103fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x20310400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x20310450
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x20310460
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x20310470
+#define BCHP_SCPU_INTR1_REG_START                          0x20310480
+#define BCHP_SCPU_INTR1_REG_END                            0x20310498
+#define BCHP_INTERNAL_INTR2_REG_START                      0x203104c0
+#define BCHP_INTERNAL_INTR2_REG_END                        0x203104ec
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x20310500
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x2031052c
+#define BCHP_SCPU_HW_INTR2_REG_START                       0x20310540
+#define BCHP_SCPU_HW_INTR2_REG_END                         0x2031056c
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x20311000
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x2031102c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x20311040
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x2031106c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x20312000
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x20312008
+#define BCHP_SCPU_HDMI_CTRL_REG_START                      0x20312080
+#define BCHP_SCPU_HDMI_CTRL_REG_END                        0x20312084
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x20312100
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x20312114
+#define BCHP_SAGE_UART_REG_START                           0x20312200
+#define BCHP_SAGE_UART_REG_END                             0x2031221c
+#define BCHP_SCPU_PM_REG_START                             0x20312980
+#define BCHP_SCPU_PM_REG_END                               0x20312988
+#define BCHP_SCPU_TIMER_REG_START                          0x20312e80
+#define BCHP_SCPU_TIMER_REG_END                            0x20312ebc
+#define BCHP_BSP_CMDBUF_REG_START                          0x2032c800
+#define BCHP_BSP_CMDBUF_REG_END                            0x2032cffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x2032d000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x2032d0b0
+#define BCHP_BSP_PKL_REG_START                             0x2032d300
+#define BCHP_BSP_PKL_REG_END                               0x2032d37c
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x2032d800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x2032d82c
+#define BCHP_BSP_VISTA_GENACC_REG_START                    0x2032d900
+#define BCHP_BSP_VISTA_GENACC_REG_END                      0x2032d9fc
+#define BCHP_BSP_OTP_SCRATCH_REG_START                     0x2032e000
+#define BCHP_BSP_OTP_SCRATCH_REG_END                       0x2032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x20360000
+#define BCHP_XPT_SECURITY_REG_END                          0x2037fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x20380000
+#define BCHP_SECTOP_GRB_REG_END                            0x2038000c
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START             0x20380080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END               0x203800ac
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START             0x20380100
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END               0x2038012c
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START             0x20380180
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END               0x203801ac
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x20380200
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x203802c8
+#define BCHP_S_MEMC_0_REG_START                            0x203bc000
+#define BCHP_S_MEMC_0_REG_END                              0x203bc780
+#define BCHP_MEMC_SECURE_UBUS_0_REG_START                  0x203bd000
+#define BCHP_MEMC_SECURE_UBUS_0_REG_END                    0x203bd494
+#define BCHP_S_MEMC_1_REG_START                            0x203cc000
+#define BCHP_S_MEMC_1_REG_END                              0x203cc780
+#define BCHP_MEMC_SECURE_UBUS_1_REG_START                  0x203cd000
+#define BCHP_MEMC_SECURE_UBUS_1_REG_END                    0x203cd494
+#define BCHP_SUN_GISB_ARB_REG_START                        0x20400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x204007fc
+#define BCHP_SUN_GR_REG_START                              0x20401000
+#define BCHP_SUN_GR_REG_END                                0x2040100c
+#define BCHP_SSP_RG_REG_START                              0x20401200
+#define BCHP_SSP_RG_REG_END                                0x2040120c
+#define BCHP_SUN_RG_REG_START                              0x20401400
+#define BCHP_SUN_RG_REG_END                                0x2040140c
+#define BCHP_RF4CE_GR_REG_START                            0x20401600
+#define BCHP_RF4CE_GR_REG_END                              0x2040160c
+#define BCHP_TPCAP_REG_START                               0x20401800
+#define BCHP_TPCAP_REG_END                                 0x2040189c
+#define BCHP_SUN_L2_REG_START                              0x20403000
+#define BCHP_SUN_L2_REG_END                                0x20403044
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x20404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x2040452c
+#define BCHP_BBSI_RG_REG_START                             0x20405c00
+#define BCHP_BBSI_RG_REG_END                               0x20405c0c
+#define BCHP_PWM_REG_START                                 0x20408000
+#define BCHP_PWM_REG_END                                   0x20408024
+#define BCHP_PWMB_REG_START                                0x20409000
+#define BCHP_PWMB_REG_END                                  0x20409024
+#define BCHP_GIO_REG_START                                 0x2040a000
+#define BCHP_GIO_REG_END                                   0x2040a09c
+#define BCHP_TIMER_REG_START                               0x2040a100
+#define BCHP_TIMER_REG_END                                 0x2040a13c
+#define BCHP_WATCHDOG_REG_START                            0x2040a200
+#define BCHP_WATCHDOG_REG_END                              0x2040a210
+#define BCHP_BSCA_REG_START                                0x2040a300
+#define BCHP_BSCA_REG_END                                  0x2040a354
+#define BCHP_BSCD_REG_START                                0x2040a400
+#define BCHP_BSCD_REG_END                                  0x2040a454
+#define BCHP_BSCE_REG_START                                0x2040a500
+#define BCHP_BSCE_REG_END                                  0x2040a554
+#define BCHP_IRQ0_REG_START                                0x2040a600
+#define BCHP_IRQ0_REG_END                                  0x2040a604
+#define BCHP_IRQ1_REG_START                                0x2040a640
+#define BCHP_IRQ1_REG_END                                  0x2040a644
+#define BCHP_PM_REG_START                                  0x2040a680
+#define BCHP_PM_REG_END                                    0x2040a688
+#define BCHP_UARTA_REG_START                               0x2040a900
+#define BCHP_UARTA_REG_END                                 0x2040a91c
+#define BCHP_UARTB_REG_START                               0x2040a940
+#define BCHP_UARTB_REG_END                                 0x2040a95c
+#define BCHP_UARTC_REG_START                               0x2040a980
+#define BCHP_UARTC_REG_END                                 0x2040a99c
+#define BCHP_SCA_REG_START                                 0x2040ac00
+#define BCHP_SCA_REG_END                                   0x2040acbc
+#define BCHP_SCB_REG_START                                 0x2040ad00
+#define BCHP_SCB_REG_END                                   0x2040adbc
+#define BCHP_SCIRQ0_REG_START                              0x2040ae00
+#define BCHP_SCIRQ0_REG_END                                0x2040ae04
+#define BCHP_SCIRQ1_REG_START                              0x2040ae40
+#define BCHP_SCIRQ1_REG_END                                0x2040ae44
+#define BCHP_SCIRQ_SCPU_REG_START                          0x2040ae80
+#define BCHP_SCIRQ_SCPU_REG_END                            0x2040ae84
+#define BCHP_MCIF_INTR2_REG_START                          0x2040b000
+#define BCHP_MCIF_INTR2_REG_END                            0x2040b044
+#define BCHP_MCIF_REG_START                                0x2040b080
+#define BCHP_MCIF_REG_END                                  0x2040b0a8
+#define BCHP_MCIF1_REG_START                               0x2040b0c0
+#define BCHP_MCIF1_REG_END                                 0x2040b0e8
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x2040b100
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x2040b12c
+#define BCHP_UPG_UART_DMA_REG_START                        0x2040b400
+#define BCHP_UPG_UART_DMA_REG_END                          0x2040b430
+#define BCHP_AON_CTRL_REG_START                            0x20410000
+#define BCHP_AON_CTRL_REG_END                              0x204105fc
+#define BCHP_AON_L2_REG_START                              0x20410600
+#define BCHP_AON_L2_REG_END                                0x2041062c
+#define BCHP_AON_PM_L2_REG_START                           0x20410640
+#define BCHP_AON_PM_L2_REG_END                             0x2041066c
+#define BCHP_AON_PM_BBM_L2_REG_START                       0x20410680
+#define BCHP_AON_PM_BBM_L2_REG_END                         0x204106ac
+#define BCHP_AON_PIN_CTRL_REG_START                        0x20410700
+#define BCHP_AON_PIN_CTRL_REG_END                          0x20410714
+#define BCHP_CNTControlBase_REG_START                      0x20412000
+#define BCHP_CNTControlBase_REG_END                        0x20412ffc
+#define BCHP_CNTReadBase_REG_START                         0x20414000
+#define BCHP_CNTReadBase_REG_END                           0x20414ffc
+#define BCHP_MSPI_REG_START                                0x20416000
+#define BCHP_MSPI_REG_END                                  0x2041617c
+#define BCHP_GIO_AON_REG_START                             0x20417000
+#define BCHP_GIO_AON_REG_END                               0x2041703c
+#define BCHP_LDK_REG_START                                 0x20417100
+#define BCHP_LDK_REG_END                                   0x20417144
+#define BCHP_BSCB_REG_START                                0x20417180
+#define BCHP_BSCB_REG_END                                  0x204171d4
+#define BCHP_IRQ0_AON_REG_START                            0x20417200
+#define BCHP_IRQ0_AON_REG_END                              0x20417204
+#define BCHP_IRQ1_AON_REG_START                            0x20417240
+#define BCHP_IRQ1_AON_REG_END                              0x20417244
+#define BCHP_PM_AON_REG_START                              0x20417280
+#define BCHP_PM_AON_REG_END                                0x20417288
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x20417400
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x2041742c
+#define BCHP_WKTMR_REG_START                               0x20417480
+#define BCHP_WKTMR_REG_END                                 0x20417490
+#define BCHP_AVS_CPU_PROG_MEM_REG_START                    0x20420000
+#define BCHP_AVS_CPU_PROG_MEM_REG_END                      0x20422ffc
+#define BCHP_AVS_CPU_DATA_MEM_REG_START                    0x20424000
+#define BCHP_AVS_CPU_DATA_MEM_REG_END                      0x20424bfc
+#define BCHP_AVS_CPU_CORE_REGS_REG_START                   0x20428000
+#define BCHP_AVS_CPU_CORE_REGS_REG_END                     0x204280fc
+#define BCHP_AVS_CPU_AUX_REGS_REG_START                    0x2042a000
+#define BCHP_AVS_CPU_AUX_REGS_REG_END                      0x2042b058
+#define BCHP_AVS_UART_REG_START                            0x20430000
+#define BCHP_AVS_UART_REG_END                              0x20430ffc
+#define BCHP_AVS_CPU_L2_REG_START                          0x20431100
+#define BCHP_AVS_CPU_L2_REG_END                            0x2043112c
+#define BCHP_AVS_HOST_L2_REG_START                         0x20431200
+#define BCHP_AVS_HOST_L2_REG_END                           0x20431244
+#define BCHP_AVS_CPU_CTRL_REG_START                        0x20431300
+#define BCHP_AVS_CPU_CTRL_REG_END                          0x2043135c
+#define BCHP_AVS_BSTI_REG_START                            0x20431400
+#define BCHP_AVS_BSTI_REG_END                              0x20431404
+#define BCHP_AVS_TMON_REG_START                            0x20431500
+#define BCHP_AVS_TMON_REG_END                              0x20431524
+#define BCHP_AVS_TOP_CTRL_REG_START                        0x20431800
+#define BCHP_AVS_TOP_CTRL_REG_END                          0x204318a8
+#define BCHP_AVS_HW_MNTR_1_REG_START                       0x20432000
+#define BCHP_AVS_HW_MNTR_1_REG_END                         0x204320c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_START               0x20432100
+#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_END                 0x20432124
+#define BCHP_AVS_RO_REGISTERS_0_1_REG_START                0x20432200
+#define BCHP_AVS_RO_REGISTERS_0_1_REG_END                  0x204322e0
+#define BCHP_AVS_RO_REGISTERS_1_1_REG_START                0x20432800
+#define BCHP_AVS_RO_REGISTERS_1_1_REG_END                  0x20432808
+#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_START              0x20432d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_END                0x20432dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_START              0x20432e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_END                0x20432efc
+#define BCHP_AVS_HW_MNTR_2_REG_START                       0x20434000
+#define BCHP_AVS_HW_MNTR_2_REG_END                         0x204340c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_START               0x20434100
+#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_END                 0x20434124
+#define BCHP_AVS_RO_REGISTERS_0_2_REG_START                0x20434200
+#define BCHP_AVS_RO_REGISTERS_0_2_REG_END                  0x204342e0
+#define BCHP_AVS_RO_REGISTERS_1_2_REG_START                0x20434800
+#define BCHP_AVS_RO_REGISTERS_1_2_REG_END                  0x20434808
+#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_START              0x20434d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_END                0x20434dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_START              0x20434e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_END                0x20434efc
+#define BCHP_AVS_WDOG_REG_START                            0x20436000
+#define BCHP_AVS_WDOG_REG_END                              0x20436ffc
+#define BCHP_AVS_PMB_S_000_REG_START                       0x20438000
+#define BCHP_AVS_PMB_S_000_REG_END                         0x20438024
+#define BCHP_AVS_PMB_S_001_REG_START                       0x20438040
+#define BCHP_AVS_PMB_S_001_REG_END                         0x20438064
+#define BCHP_AVS_PMB_S_002_REG_START                       0x20438080
+#define BCHP_AVS_PMB_S_002_REG_END                         0x204380a4
+#define BCHP_AVS_PMB_S_003_REG_START                       0x204380c0
+#define BCHP_AVS_PMB_S_003_REG_END                         0x204380e4
+#define BCHP_AVS_PMB_S_004_REG_START                       0x20438100
+#define BCHP_AVS_PMB_S_004_REG_END                         0x20438124
+#define BCHP_AVS_PMB_S_005_REG_START                       0x20438140
+#define BCHP_AVS_PMB_S_005_REG_END                         0x20438164
+#define BCHP_AVS_PMB_S_006_REG_START                       0x20438180
+#define BCHP_AVS_PMB_S_006_REG_END                         0x204381a4
+#define BCHP_AVS_PMB_S_007_REG_START                       0x204381c0
+#define BCHP_AVS_PMB_S_007_REG_END                         0x204381e4
+#define BCHP_AVS_PMB_S_008_REG_START                       0x20438200
+#define BCHP_AVS_PMB_S_008_REG_END                         0x20438224
+#define BCHP_AVS_PMB_S_009_REG_START                       0x20438240
+#define BCHP_AVS_PMB_S_009_REG_END                         0x20438264
+#define BCHP_AVS_PMB_S_010_REG_START                       0x20438280
+#define BCHP_AVS_PMB_S_010_REG_END                         0x204382a4
+#define BCHP_AVS_PMB_S_011_REG_START                       0x204382c0
+#define BCHP_AVS_PMB_S_011_REG_END                         0x204382e4
+#define BCHP_AVS_PMB_S_012_REG_START                       0x20438300
+#define BCHP_AVS_PMB_S_012_REG_END                         0x20438324
+#define BCHP_AVS_PMB_S_013_REG_START                       0x20438340
+#define BCHP_AVS_PMB_S_013_REG_END                         0x20438364
+#define BCHP_AVS_PMB_S_014_REG_START                       0x20438380
+#define BCHP_AVS_PMB_S_014_REG_END                         0x204383a4
+#define BCHP_AVS_PMB_S_015_REG_START                       0x204383c0
+#define BCHP_AVS_PMB_S_015_REG_END                         0x204383e4
+#define BCHP_AVS_PMB_S_016_REG_START                       0x20438400
+#define BCHP_AVS_PMB_S_016_REG_END                         0x20438424
+#define BCHP_AVS_PMB_S_017_REG_START                       0x20438440
+#define BCHP_AVS_PMB_S_017_REG_END                         0x20438464
+#define BCHP_AVS_PMB_S_018_REG_START                       0x20438480
+#define BCHP_AVS_PMB_S_018_REG_END                         0x204384a4
+#define BCHP_AVS_PMB_S_019_REG_START                       0x204384c0
+#define BCHP_AVS_PMB_S_019_REG_END                         0x204384e4
+#define BCHP_AVS_PMB_S_020_REG_START                       0x20438500
+#define BCHP_AVS_PMB_S_020_REG_END                         0x20438524
+#define BCHP_AVS_PMB_S_021_REG_START                       0x20438540
+#define BCHP_AVS_PMB_S_021_REG_END                         0x20438564
+#define BCHP_AVS_PMB_S_022_REG_START                       0x20438580
+#define BCHP_AVS_PMB_S_022_REG_END                         0x204385a4
+#define BCHP_AVS_PMB_S_023_REG_START                       0x204385c0
+#define BCHP_AVS_PMB_S_023_REG_END                         0x204385e4
+#define BCHP_AVS_PMB_S_024_REG_START                       0x20438600
+#define BCHP_AVS_PMB_S_024_REG_END                         0x20438624
+#define BCHP_AVS_PMB_S_025_REG_START                       0x20438640
+#define BCHP_AVS_PMB_S_025_REG_END                         0x20438664
+#define BCHP_AVS_PMB_S_026_REG_START                       0x20438680
+#define BCHP_AVS_PMB_S_026_REG_END                         0x204386a4
+#define BCHP_AVS_PMB_S_027_REG_START                       0x204386c0
+#define BCHP_AVS_PMB_S_027_REG_END                         0x204386e4
+#define BCHP_AVS_PMB_S_028_REG_START                       0x20438700
+#define BCHP_AVS_PMB_S_028_REG_END                         0x20438724
+#define BCHP_AVS_PMB_S_029_REG_START                       0x20438740
+#define BCHP_AVS_PMB_S_029_REG_END                         0x20438764
+#define BCHP_AVS_PMB_S_030_REG_START                       0x20438780
+#define BCHP_AVS_PMB_S_030_REG_END                         0x204387a4
+#define BCHP_AVS_PMB_S_031_REG_START                       0x204387c0
+#define BCHP_AVS_PMB_S_031_REG_END                         0x204387e4
+#define BCHP_AVS_PMB_S_032_REG_START                       0x20438800
+#define BCHP_AVS_PMB_S_032_REG_END                         0x20438824
+#define BCHP_AVS_PMB_S_033_REG_START                       0x20438840
+#define BCHP_AVS_PMB_S_033_REG_END                         0x20438864
+#define BCHP_AVS_PMB_S_034_REG_START                       0x20438880
+#define BCHP_AVS_PMB_S_034_REG_END                         0x204388a4
+#define BCHP_AVS_PMB_REGISTERS_REG_START                   0x2043a000
+#define BCHP_AVS_PMB_REGISTERS_REG_END                     0x2043a008
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x20440000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x204407fc
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x20440800
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x20440804
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x20440900
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x2044097c
+#define BCHP_AVS_RANGE_BLOCKER_REG_START                   0x20440a00
+#define BCHP_AVS_RANGE_BLOCKER_REG_END                     0x20440a58
+#define BCHP_HIF_CONTINUATION_REG_START                    0x20450000
+#define BCHP_HIF_CONTINUATION_REG_END                      0x204500fc
+#define BCHP_WEBHIF_CONTINUATION_REG_START                 0x20450800
+#define BCHP_WEBHIF_CONTINUATION_REG_END                   0x20450814
+#define BCHP_CLKGEN_REG_START                              0x20480000
+#define BCHP_CLKGEN_REG_END                                0x2048058c
+#define BCHP_CLKGEN_GR_REG_START                           0x20483000
+#define BCHP_CLKGEN_GR_REG_END                             0x2048300c
+#define BCHP_SDIO_0_HOST_REG_START                         0x204a0000
+#define BCHP_SDIO_0_HOST_REG_END                           0x204a00fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x204a0100
+#define BCHP_SDIO_0_CFG_REG_END                            0x204a01fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x204a0200
+#define BCHP_SDIO_1_HOST_REG_END                           0x204a02fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x204a0300
+#define BCHP_SDIO_1_CFG_REG_END                            0x204a03fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x204a0400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x204a043c
+#define BCHP_EBI_REG_START                                 0x204a0800
+#define BCHP_EBI_REG_END                                   0x204a0bfc
+#define BCHP_HIF_INTR2_REG_START                           0x204a1000
+#define BCHP_HIF_INTR2_REG_END                             0x204a102c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x204a1500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x204a154c
+#define BCHP_HIF_RGR2_REG_START                            0x204a1700
+#define BCHP_HIF_RGR2_REG_END                              0x204a1710
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x204a1a00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x204a1a2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x204a2000
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x204a203c
+#define BCHP_WEBHIF_L1_MASK_REG_START                      0x204a2100
+#define BCHP_WEBHIF_L1_MASK_REG_END                        0x204a2110
+#define BCHP_HIF_CPUBIUARCH_REG_START                      0x204a2200
+#define BCHP_HIF_CPUBIUARCH_REG_END                        0x204a23fc
+#define BCHP_HIF_CPUBIUCTRL_REG_START                      0x204a2400
+#define BCHP_HIF_CPUBIUCTRL_REG_END                        0x204a27fc
+#define BCHP_NAND_REG_START                                0x204a2800
+#define BCHP_NAND_REG_END                                  0x204a2dfc
+#define BCHP_FLASH_DMA_REG_START                           0x204a3000
+#define BCHP_FLASH_DMA_REG_END                             0x204a3028
+#define BCHP_BSPI_REG_START                                0x204a3200
+#define BCHP_BSPI_REG_END                                  0x204a324c
+#define BCHP_BSPI_RAF_REG_START                            0x204a3300
+#define BCHP_BSPI_RAF_REG_END                              0x204a3320
+#define BCHP_HIF_MSPI_REG_START                            0x204a3400
+#define BCHP_HIF_MSPI_REG_END                              0x204a3584
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START          0x204a3600
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END            0x204a3604
+#define BCHP_IPI0_INTR2_REG_START                          0x204a4000
+#define BCHP_IPI0_INTR2_REG_END                            0x204a402c
+#define BCHP_IPI1_INTR2_REG_START                          0x204a4100
+#define BCHP_IPI1_INTR2_REG_END                            0x204a412c
+#define BCHP_BOOTSRAM_TM_REG_START                         0x204b0000
+#define BCHP_BOOTSRAM_TM_REG_END                           0x204bfffc
+#define BCHP_BOOTSRAM_SECURE_REG_START                     0x204c0000
+#define BCHP_BOOTSRAM_SECURE_REG_END                       0x204cfffc
+#define BCHP_ITCH0_REG_START                               0x204d0000
+#define BCHP_ITCH0_REG_END                                 0x204d0000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x204d0400
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x204d0400
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x204d0500
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x204d0500
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x204d0600
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x204d0600
+#define BCHP_NAND_SECURE_REG_START                         0x204d0800
+#define BCHP_NAND_SECURE_REG_END                           0x204d0800
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START       0x204d0c00
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END         0x204d0c00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START               0x204d0e00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END                 0x204d0ffc
+#define BCHP_HIF_CONTINUATION_SECURE_REG_START             0x204d1000
+#define BCHP_HIF_CONTINUATION_SECURE_REG_END               0x204d1004
+#define BCHP_ITCH1_REG_START                               0x204d1200
+#define BCHP_ITCH1_REG_END                                 0x204d1200
+#define BCHP_PROD_OTP_GRB_REG_START                        0x204e6000
+#define BCHP_PROD_OTP_GRB_REG_END                          0x204e600c
+#define BCHP_JTAG_OTP_REG_START                            0x204e6100
+#define BCHP_JTAG_OTP_REG_END                              0x204e615c
+#define BCHP_BOOTROM_REG_START                             0x20500000
+#define BCHP_BOOTROM_REG_END                               0x20503ffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x20a00000
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x20a0002c
+#define BCHP_XPT_BUS_IF_REG_START                          0x20a00080
+#define BCHP_XPT_BUS_IF_REG_END                            0x20a000fc
+#define BCHP_XPT_XMEMIF_REG_START                          0x20a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x20a001fc
+#define BCHP_XPT_PMU_REG_START                             0x20a00200
+#define BCHP_XPT_PMU_REG_END                               0x20a00218
+#define BCHP_XPT_GR_REG_START                              0x20a00300
+#define BCHP_XPT_GR_REG_END                                0x20a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x20a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x20a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x20a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x20a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x20a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x20a01fbc
+#define BCHP_XPT_DPCR0_REG_START                           0x20a02000
+#define BCHP_XPT_DPCR0_REG_END                             0x20a02078
+#define BCHP_XPT_DPCR1_REG_START                           0x20a02080
+#define BCHP_XPT_DPCR1_REG_END                             0x20a020f8
+#define BCHP_XPT_DPCR2_REG_START                           0x20a02100
+#define BCHP_XPT_DPCR2_REG_END                             0x20a02178
+#define BCHP_XPT_DPCR3_REG_START                           0x20a02180
+#define BCHP_XPT_DPCR3_REG_END                             0x20a021f8
+#define BCHP_XPT_DPCR4_REG_START                           0x20a02200
+#define BCHP_XPT_DPCR4_REG_END                             0x20a02278
+#define BCHP_XPT_DPCR5_REG_START                           0x20a02280
+#define BCHP_XPT_DPCR5_REG_END                             0x20a022f8
+#define BCHP_XPT_DPCR6_REG_START                           0x20a02300
+#define BCHP_XPT_DPCR6_REG_END                             0x20a02378
+#define BCHP_XPT_DPCR7_REG_START                           0x20a02380
+#define BCHP_XPT_DPCR7_REG_END                             0x20a023f8
+#define BCHP_XPT_DPCR8_REG_START                           0x20a02400
+#define BCHP_XPT_DPCR8_REG_END                             0x20a02478
+#define BCHP_XPT_DPCR9_REG_START                           0x20a02480
+#define BCHP_XPT_DPCR9_REG_END                             0x20a024f8
+#define BCHP_XPT_DPCR10_REG_START                          0x20a02500
+#define BCHP_XPT_DPCR10_REG_END                            0x20a02578
+#define BCHP_XPT_DPCR11_REG_START                          0x20a02580
+#define BCHP_XPT_DPCR11_REG_END                            0x20a025f8
+#define BCHP_XPT_DPCR12_REG_START                          0x20a02600
+#define BCHP_XPT_DPCR12_REG_END                            0x20a02678
+#define BCHP_XPT_DPCR13_REG_START                          0x20a02680
+#define BCHP_XPT_DPCR13_REG_END                            0x20a026f8
+#define BCHP_XPT_DPCR_PP_REG_START                         0x20a02800
+#define BCHP_XPT_DPCR_PP_REG_END                           0x20a02804
+#define BCHP_XPT_PSUB_REG_START                            0x20a02a00
+#define BCHP_XPT_PSUB_REG_END                              0x20a02b88
+#define BCHP_XPT_MPOD_REG_START                            0x20a02c00
+#define BCHP_XPT_MPOD_REG_END                              0x20a02c20
+#define BCHP_XPT_RMX0_REG_START                            0x20a02d00
+#define BCHP_XPT_RMX0_REG_END                              0x20a02d10
+#define BCHP_XPT_RMX1_REG_START                            0x20a02e00
+#define BCHP_XPT_RMX1_REG_END                              0x20a02e10
+#define BCHP_XPT_RSBUFF_REG_START                          0x20a04000
+#define BCHP_XPT_RSBUFF_REG_END                            0x20a054fc
+#define BCHP_XPT_XCBUFF_REG_START                          0x20a06000
+#define BCHP_XPT_XCBUFF_REG_END                            0x20a07e9c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x20a08000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x20a0aafc
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START           0x20a0c000
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END             0x20a0ea04
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START            0x20a0f000
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END              0x20a0f9fc
+#define BCHP_XPT_TSIO_INTR_L2_REG_START                    0x20a0fc00
+#define BCHP_XPT_TSIO_INTR_L2_REG_END                      0x20a0fc2c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x20a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x20a14050
+#define BCHP_XPT_FE_REG_START                              0x20a20000
+#define BCHP_XPT_FE_REG_END                                0x20a25ffc
+#define BCHP_XPT_MSG_REG_START                             0x20a30000
+#define BCHP_XPT_MSG_REG_END                               0x20a3ca14
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x20a3fb00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x20a3fb1c
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x20a3fb20
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END  0x20a3fb3c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x20a3fb40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x20a3fb5c
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x20a3fb60
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END  0x20a3fb7c
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START             0x20a3fb80
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END               0x20a3fbac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START   0x20a3fc00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END     0x20a3fc2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START   0x20a3fc40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END     0x20a3fc6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START   0x20a3fc80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END     0x20a3fcac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START  0x20a3fcc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END    0x20a3fcec
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x20a3fd00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END   0x20a3fd2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x20a3fd40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END   0x20a3fd6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x20a3fd80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END   0x20a3fdac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x20a3fdc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END   0x20a3fdec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START      0x20a3fe00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END        0x20a3fe2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START      0x20a3fe40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END        0x20a3fe6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START      0x20a3fe80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END        0x20a3feac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START     0x20a3fec0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END       0x20a3feec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START    0x20a3ff00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END      0x20a3ff2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START    0x20a3ff40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END      0x20a3ff6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START    0x20a3ff80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END      0x20a3ffac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START    0x20a3ffc0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END      0x20a3ffec
+#define BCHP_XPT_RAVE_REG_START                            0x20a40000
+#define BCHP_XPT_RAVE_REG_END                              0x20a4e178
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START        0x20a4f000
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END          0x20a4f01c
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START        0x20a4f020
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END          0x20a4f03c
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START               0x20a4f040
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END                 0x20a4f06c
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START  0x20a4f080
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END    0x20a4f0ac
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START  0x20a4f0c0
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END    0x20a4f0ec
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x20a4f100
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END   0x20a4f12c
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x20a4f140
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END   0x20a4f16c
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START  0x20a4f180
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END    0x20a4f1ac
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START  0x20a4f1c0
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END    0x20a4f1ec
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START   0x20a4f200
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END     0x20a4f22c
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START   0x20a4f240
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END     0x20a4f26c
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x20a4f280
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x20a4f2ac
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x20a4f2c0
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x20a4f2ec
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x20a4f300
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x20a4f32c
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x20a4f340
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x20a4f36c
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START     0x20a4f380
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END       0x20a4f3ac
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START     0x20a4f3c0
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END       0x20a4f3ec
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START   0x20a4f400
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END     0x20a4f42c
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START   0x20a4f440
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END     0x20a4f46c
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f480
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f4ac
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f4c0
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f4ec
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f500
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f52c
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f540
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f56c
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f580
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f5ac
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f5c0
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f5ec
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f600
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f62c
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f640
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f66c
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f680
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f6ac
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f6c0
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f6ec
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f700
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f72c
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x20a4f740
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x20a4f76c
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x20a4f780
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x20a4f7ac
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x20a4f7c0
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x20a4f7ec
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x20a4f800
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x20a4f82c
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x20a4f840
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x20a4f86c
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START       0x20a4ff80
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END         0x20a4ffac
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START      0x20a4ffc0
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END        0x20a4ffec
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x20a60000
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END   0x20a6001c
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x20a60020
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END   0x20a6003c
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START   0x20a60040
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END     0x20a6006c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x20a60080
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x20a600ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START    0x20a600c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END      0x20a600ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x20a60100
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x20a6012c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START    0x20a60140
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END      0x20a6016c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x20a60180
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x20a601ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x20a601c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x20a601ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x20a60200
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x20a6022c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x20a60240
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x20a6026c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x20a60280
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x20a602ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x20a602c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x20a602ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x20a60300
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x20a6032c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x20a60340
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x20a6036c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x20a60380
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x20a603ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x20a603c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x20a603ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x20a60400
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x20a6042c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x20a60440
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x20a6046c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x20a60480
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x20a604ac
+#define BCHP_XPT_MEMDMA_MCPB_REG_START                     0x20a60800
+#define BCHP_XPT_MEMDMA_MCPB_REG_END                       0x20a60b98
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START                 0x20a60c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END                   0x20a60d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START                 0x20a60e00
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END                   0x20a60f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START                 0x20a61000
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END                   0x20a6115c
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START                 0x20a61200
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END                   0x20a6135c
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START                 0x20a61400
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END                   0x20a6155c
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START                 0x20a61600
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END                   0x20a6175c
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START                 0x20a61800
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END                   0x20a6195c
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START                 0x20a61a00
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END                   0x20a61b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START                 0x20a61c00
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END                   0x20a61d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START                 0x20a61e00
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END                   0x20a61f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START                0x20a62000
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END                  0x20a6215c
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START                0x20a62200
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END                  0x20a6235c
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START                0x20a62400
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END                  0x20a6255c
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START                0x20a62600
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END                  0x20a6275c
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START                0x20a62800
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END                  0x20a6295c
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START                0x20a62a00
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END                  0x20a62b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START                0x20a62c00
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END                  0x20a62d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START                0x20a62e00
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END                  0x20a62f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START                0x20a63000
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END                  0x20a6315c
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START                0x20a63200
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END                  0x20a6335c
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START                0x20a63400
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END                  0x20a6355c
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START                0x20a63600
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END                  0x20a6375c
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START                0x20a63800
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END                  0x20a6395c
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START                0x20a63a00
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END                  0x20a63b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START                0x20a63c00
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END                  0x20a63d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START                0x20a63e00
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END                  0x20a63f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START                0x20a64000
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END                  0x20a6415c
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START                0x20a64200
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END                  0x20a6435c
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START                0x20a64400
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END                  0x20a6455c
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START                0x20a64600
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END                  0x20a6475c
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START                0x20a64800
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END                  0x20a6495c
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START                0x20a64a00
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END                  0x20a64b5c
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START        0x20a68000
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END          0x20a6801c
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START        0x20a68020
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END          0x20a6803c
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START       0x20a68040
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END         0x20a6805c
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START                0x20a68100
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END                  0x20a68144
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START           0x20a68200
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END             0x20a68244
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START          0x20a68300
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END            0x20a68344
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START                 0x20a68400
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END                   0x20a68444
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_START                 0x20a68500
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_END                   0x20a68510
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_START                 0x20a68600
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_END                   0x20a68658
+#define BCHP_XPT_WDMA_REGS_REG_START                       0x20a69000
+#define BCHP_XPT_WDMA_REGS_REG_END                         0x20a69068
+#define BCHP_XPT_WDMA_CH0_REG_START                        0x20a6a000
+#define BCHP_XPT_WDMA_CH0_REG_END                          0x20a6a0fc
+#define BCHP_XPT_WDMA_CH1_REG_START                        0x20a6a100
+#define BCHP_XPT_WDMA_CH1_REG_END                          0x20a6a1fc
+#define BCHP_XPT_WDMA_CH2_REG_START                        0x20a6a200
+#define BCHP_XPT_WDMA_CH2_REG_END                          0x20a6a2fc
+#define BCHP_XPT_WDMA_CH3_REG_START                        0x20a6a300
+#define BCHP_XPT_WDMA_CH3_REG_END                          0x20a6a3fc
+#define BCHP_XPT_WDMA_CH4_REG_START                        0x20a6a400
+#define BCHP_XPT_WDMA_CH4_REG_END                          0x20a6a4fc
+#define BCHP_XPT_WDMA_CH5_REG_START                        0x20a6a500
+#define BCHP_XPT_WDMA_CH5_REG_END                          0x20a6a5fc
+#define BCHP_XPT_WDMA_CH6_REG_START                        0x20a6a600
+#define BCHP_XPT_WDMA_CH6_REG_END                          0x20a6a6fc
+#define BCHP_XPT_WDMA_CH7_REG_START                        0x20a6a700
+#define BCHP_XPT_WDMA_CH7_REG_END                          0x20a6a7fc
+#define BCHP_XPT_WDMA_CH8_REG_START                        0x20a6a800
+#define BCHP_XPT_WDMA_CH8_REG_END                          0x20a6a8fc
+#define BCHP_XPT_WDMA_CH9_REG_START                        0x20a6a900
+#define BCHP_XPT_WDMA_CH9_REG_END                          0x20a6a9fc
+#define BCHP_XPT_WDMA_CH10_REG_START                       0x20a6aa00
+#define BCHP_XPT_WDMA_CH10_REG_END                         0x20a6aafc
+#define BCHP_XPT_WDMA_CH11_REG_START                       0x20a6ab00
+#define BCHP_XPT_WDMA_CH11_REG_END                         0x20a6abfc
+#define BCHP_XPT_WDMA_CH12_REG_START                       0x20a6ac00
+#define BCHP_XPT_WDMA_CH12_REG_END                         0x20a6acfc
+#define BCHP_XPT_WDMA_CH13_REG_START                       0x20a6ad00
+#define BCHP_XPT_WDMA_CH13_REG_END                         0x20a6adfc
+#define BCHP_XPT_WDMA_CH14_REG_START                       0x20a6ae00
+#define BCHP_XPT_WDMA_CH14_REG_END                         0x20a6aefc
+#define BCHP_XPT_WDMA_CH15_REG_START                       0x20a6af00
+#define BCHP_XPT_WDMA_CH15_REG_END                         0x20a6affc
+#define BCHP_XPT_WDMA_CH16_REG_START                       0x20a6b000
+#define BCHP_XPT_WDMA_CH16_REG_END                         0x20a6b0fc
+#define BCHP_XPT_WDMA_CH17_REG_START                       0x20a6b100
+#define BCHP_XPT_WDMA_CH17_REG_END                         0x20a6b1fc
+#define BCHP_XPT_WDMA_CH18_REG_START                       0x20a6b200
+#define BCHP_XPT_WDMA_CH18_REG_END                         0x20a6b2fc
+#define BCHP_XPT_WDMA_CH19_REG_START                       0x20a6b300
+#define BCHP_XPT_WDMA_CH19_REG_END                         0x20a6b3fc
+#define BCHP_XPT_WDMA_CH20_REG_START                       0x20a6b400
+#define BCHP_XPT_WDMA_CH20_REG_END                         0x20a6b4fc
+#define BCHP_XPT_WDMA_CH21_REG_START                       0x20a6b500
+#define BCHP_XPT_WDMA_CH21_REG_END                         0x20a6b5fc
+#define BCHP_XPT_WDMA_CH22_REG_START                       0x20a6b600
+#define BCHP_XPT_WDMA_CH22_REG_END                         0x20a6b6fc
+#define BCHP_XPT_WDMA_CH23_REG_START                       0x20a6b700
+#define BCHP_XPT_WDMA_CH23_REG_END                         0x20a6b7fc
+#define BCHP_XPT_WDMA_CH24_REG_START                       0x20a6b800
+#define BCHP_XPT_WDMA_CH24_REG_END                         0x20a6b8fc
+#define BCHP_XPT_WDMA_CH25_REG_START                       0x20a6b900
+#define BCHP_XPT_WDMA_CH25_REG_END                         0x20a6b9fc
+#define BCHP_XPT_WDMA_CH26_REG_START                       0x20a6ba00
+#define BCHP_XPT_WDMA_CH26_REG_END                         0x20a6bafc
+#define BCHP_XPT_WDMA_CH27_REG_START                       0x20a6bb00
+#define BCHP_XPT_WDMA_CH27_REG_END                         0x20a6bbfc
+#define BCHP_XPT_WDMA_CH28_REG_START                       0x20a6bc00
+#define BCHP_XPT_WDMA_CH28_REG_END                         0x20a6bcfc
+#define BCHP_XPT_WDMA_CH29_REG_START                       0x20a6bd00
+#define BCHP_XPT_WDMA_CH29_REG_END                         0x20a6bdfc
+#define BCHP_XPT_WDMA_CH30_REG_START                       0x20a6be00
+#define BCHP_XPT_WDMA_CH30_REG_END                         0x20a6befc
+#define BCHP_XPT_WDMA_CH31_REG_START                       0x20a6bf00
+#define BCHP_XPT_WDMA_CH31_REG_END                         0x20a6bffc
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_START                   0x20a6ff00
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_END                     0x20a6fffc
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START        0x20a70000
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END          0x20a7001c
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START        0x20a70020
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END          0x20a7003c
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START          0x20a70040
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END            0x20a7006c
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START    0x20a70080
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END      0x20a700ac
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START           0x20a700c0
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END             0x20a700ec
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x20a70100
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END   0x20a7012c
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START           0x20a70140
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END             0x20a7016c
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START   0x20a70180
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END     0x20a701ac
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x20a701c0
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x20a701ec
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x20a70200
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x20a7022c
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x20a70240
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x20a7026c
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x20a70280
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x20a702ac
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START  0x20a702c0
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END    0x20a702ec
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x20a70300
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x20a7032c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x20a70340
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x20a7036c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x20a70380
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x20a703ac
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x20a703c0
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x20a703ec
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70400
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7042c
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70440
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7046c
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x20a70480
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x20a704ac
+#define BCHP_XPT_MCPB_REG_START                            0x20a70800
+#define BCHP_XPT_MCPB_REG_END                              0x20a70b98
+#define BCHP_XPT_MCPB_CH0_REG_START                        0x20a70c00
+#define BCHP_XPT_MCPB_CH0_REG_END                          0x20a70d5c
+#define BCHP_XPT_MCPB_CH1_REG_START                        0x20a70e00
+#define BCHP_XPT_MCPB_CH1_REG_END                          0x20a70f5c
+#define BCHP_XPT_MCPB_CH2_REG_START                        0x20a71000
+#define BCHP_XPT_MCPB_CH2_REG_END                          0x20a7115c
+#define BCHP_XPT_MCPB_CH3_REG_START                        0x20a71200
+#define BCHP_XPT_MCPB_CH3_REG_END                          0x20a7135c
+#define BCHP_XPT_MCPB_CH4_REG_START                        0x20a71400
+#define BCHP_XPT_MCPB_CH4_REG_END                          0x20a7155c
+#define BCHP_XPT_MCPB_CH5_REG_START                        0x20a71600
+#define BCHP_XPT_MCPB_CH5_REG_END                          0x20a7175c
+#define BCHP_XPT_MCPB_CH6_REG_START                        0x20a71800
+#define BCHP_XPT_MCPB_CH6_REG_END                          0x20a7195c
+#define BCHP_XPT_MCPB_CH7_REG_START                        0x20a71a00
+#define BCHP_XPT_MCPB_CH7_REG_END                          0x20a71b5c
+#define BCHP_XPT_MCPB_CH8_REG_START                        0x20a71c00
+#define BCHP_XPT_MCPB_CH8_REG_END                          0x20a71d5c
+#define BCHP_XPT_MCPB_CH9_REG_START                        0x20a71e00
+#define BCHP_XPT_MCPB_CH9_REG_END                          0x20a71f5c
+#define BCHP_XPT_MCPB_CH10_REG_START                       0x20a72000
+#define BCHP_XPT_MCPB_CH10_REG_END                         0x20a7215c
+#define BCHP_XPT_MCPB_CH11_REG_START                       0x20a72200
+#define BCHP_XPT_MCPB_CH11_REG_END                         0x20a7235c
+#define BCHP_XPT_MCPB_CH12_REG_START                       0x20a72400
+#define BCHP_XPT_MCPB_CH12_REG_END                         0x20a7255c
+#define BCHP_XPT_MCPB_CH13_REG_START                       0x20a72600
+#define BCHP_XPT_MCPB_CH13_REG_END                         0x20a7275c
+#define BCHP_XPT_MCPB_CH14_REG_START                       0x20a72800
+#define BCHP_XPT_MCPB_CH14_REG_END                         0x20a7295c
+#define BCHP_XPT_MCPB_CH15_REG_START                       0x20a72a00
+#define BCHP_XPT_MCPB_CH15_REG_END                         0x20a72b5c
+#define BCHP_XPT_MCPB_CH16_REG_START                       0x20a72c00
+#define BCHP_XPT_MCPB_CH16_REG_END                         0x20a72d5c
+#define BCHP_XPT_MCPB_CH17_REG_START                       0x20a72e00
+#define BCHP_XPT_MCPB_CH17_REG_END                         0x20a72f5c
+#define BCHP_XPT_MCPB_CH18_REG_START                       0x20a73000
+#define BCHP_XPT_MCPB_CH18_REG_END                         0x20a7315c
+#define BCHP_XPT_MCPB_CH19_REG_START                       0x20a73200
+#define BCHP_XPT_MCPB_CH19_REG_END                         0x20a7335c
+#define BCHP_XPT_MCPB_CH20_REG_START                       0x20a73400
+#define BCHP_XPT_MCPB_CH20_REG_END                         0x20a7355c
+#define BCHP_XPT_MCPB_CH21_REG_START                       0x20a73600
+#define BCHP_XPT_MCPB_CH21_REG_END                         0x20a7375c
+#define BCHP_XPT_MCPB_CH22_REG_START                       0x20a73800
+#define BCHP_XPT_MCPB_CH22_REG_END                         0x20a7395c
+#define BCHP_XPT_MCPB_CH23_REG_START                       0x20a73a00
+#define BCHP_XPT_MCPB_CH23_REG_END                         0x20a73b5c
+#define BCHP_XPT_MCPB_CH24_REG_START                       0x20a73c00
+#define BCHP_XPT_MCPB_CH24_REG_END                         0x20a73d5c
+#define BCHP_XPT_MCPB_CH25_REG_START                       0x20a73e00
+#define BCHP_XPT_MCPB_CH25_REG_END                         0x20a73f5c
+#define BCHP_XPT_MCPB_CH26_REG_START                       0x20a74000
+#define BCHP_XPT_MCPB_CH26_REG_END                         0x20a7415c
+#define BCHP_XPT_MCPB_CH27_REG_START                       0x20a74200
+#define BCHP_XPT_MCPB_CH27_REG_END                         0x20a7435c
+#define BCHP_XPT_MCPB_CH28_REG_START                       0x20a74400
+#define BCHP_XPT_MCPB_CH28_REG_END                         0x20a7455c
+#define BCHP_XPT_MCPB_CH29_REG_START                       0x20a74600
+#define BCHP_XPT_MCPB_CH29_REG_END                         0x20a7475c
+#define BCHP_XPT_MCPB_CH30_REG_START                       0x20a74800
+#define BCHP_XPT_MCPB_CH30_REG_END                         0x20a7495c
+#define BCHP_XPT_MCPB_CH31_REG_START                       0x20a74a00
+#define BCHP_XPT_MCPB_CH31_REG_END                         0x20a74b5c
+#define BCHP_XPT_XPU_REG_START                             0x20a78000
+#define BCHP_XPT_XPU_REG_END                               0x20a7c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x20a7f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x20a7f000
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_START              0x20a80200
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_END                0x20a80204
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_START              0x20a80300
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_END                0x20a80304
+#define BCHP_DEMOD_XPT_WAKEUP_REG_START                    0x20a81000
+#define BCHP_DEMOD_XPT_WAKEUP_REG_END                      0x20a81fbc
+#define BCHP_DEMOD_XPT_FE_REG_START                        0x20a82000
+#define BCHP_DEMOD_XPT_FE_REG_END                          0x20a837fc
+#define BCHP_SID_REG_START                                 0x20bc0100
+#define BCHP_SID_REG_END                                   0x20bc019c
+#define BCHP_SID_RLE_REG_START                             0x20bc0300
+#define BCHP_SID_RLE_REG_END                               0x20bc039c
+#define BCHP_SID_DQ_REG_START                              0x20bc0400
+#define BCHP_SID_DQ_REG_END                                0x20bc04bc
+#define BCHP_SID_STRM_REG_START                            0x20bc0800
+#define BCHP_SID_STRM_REG_END                              0x20bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x20bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x20bc0c40
+#define BCHP_SID_ARC_REG_START                             0x20bc0f00
+#define BCHP_SID_ARC_REG_END                               0x20bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x20bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x20bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x20bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x20bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x20bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x20bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x20bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x20bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x20bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x20bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x20bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x20bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x20bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x20bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x20bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x20bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x20bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x20bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x20bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x20bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x20bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x20bd5014
+#define BCHP_SID_GR_REG_START                              0x20be0000
+#define BCHP_SID_GR_REG_END                                0x20be000c
+#define BCHP_SID_L2_REG_START                              0x20be0100
+#define BCHP_SID_L2_REG_END                                0x20be012c
+#define BCHP_SICH_REG_START                                0x20be2000
+#define BCHP_SICH_REG_END                                  0x20be203c
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_START                 0x20e00000
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_END                   0x20e1fffc
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_START                 0x20e20000
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_END                   0x20e3fffc
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_START                  0x20e40000
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_END                    0x20e47ffc
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_START                 0x20e50000
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_END                   0x20e500fc
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_START                  0x20e51000
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_END                    0x20e51a08
+#define BCHP_RF4CE_CPU_UART_REG_START                      0x20e52000
+#define BCHP_RF4CE_CPU_UART_REG_END                        0x20e52ffc
+#define BCHP_RF4CE_CPU_WDG_REG_START                       0x20e53000
+#define BCHP_RF4CE_CPU_WDG_REG_END                         0x20e53ffc
+#define BCHP_RF4CE_CPU_CTRL_REG_START                      0x20e80000
+#define BCHP_RF4CE_CPU_CTRL_REG_END                        0x20e8008c
+#define BCHP_RF4CE_CPU_L2_REG_START                        0x20e80300
+#define BCHP_RF4CE_CPU_L2_REG_END                          0x20e80314
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_START               0x20e80500
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_END                 0x20e8052c
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_START                0x20e80800
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_END                  0x20e8082c
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_START                0x20e80a00
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_END                  0x20e80a2c
+#define BCHP_TX_REG_START                                  0x20ec0000
+#define BCHP_TX_REG_END                                    0x20ec0020
+#define BCHP_RX_REG_START                                  0x20ed0000
+#define BCHP_RX_REG_END                                    0x20ed0254
+#define BCHP_RF_REG_START                                  0x20ee0000
+#define BCHP_RF_REG_END                                    0x20ee00a4
+#define BCHP_VCOCAL_REG_START                              0x20ee0100
+#define BCHP_VCOCAL_REG_END                                0x20ee0174
+#define BCHP_KVCO_REG_START                                0x20ee0200
+#define BCHP_KVCO_REG_END                                  0x20ee0224
+#define BCHP_PA_REG_START                                  0x20ee0300
+#define BCHP_PA_REG_END                                    0x20ee0314
+#define BCHP_MAC_REG_START                                 0x20ee0400
+#define BCHP_MAC_REG_END                                   0x20ee0564
+#define BCHP_PWR_MGT_L2_REG_START                          0x20ee0600
+#define BCHP_PWR_MGT_L2_REG_END                            0x20ee0614
+#define BCHP_MISC_L2_REG_START                             0x20ee0700
+#define BCHP_MISC_L2_REG_END                               0x20ee0714
+#define BCHP_IQCAL_CCA_CCM_L2_REG_START                    0x20ee0800
+#define BCHP_IQCAL_CCA_CCM_L2_REG_END                      0x20ee0814
+#define BCHP_SYMCNT6_L2_REG_START                          0x20ee0900
+#define BCHP_SYMCNT6_L2_REG_END                            0x20ee0914
+#define BCHP_TX_DONE_L2_REG_START                          0x20ee0a00
+#define BCHP_TX_DONE_L2_REG_END                            0x20ee0a14
+#define BCHP_RX_DONE_L2_REG_START                          0x20ee0b00
+#define BCHP_RX_DONE_L2_REG_END                            0x20ee0b14
+#define BCHP_RX_START_L2_REG_START                         0x20ee0c00
+#define BCHP_RX_START_L2_REG_END                           0x20ee0c14
+#define BCHP_SYMCNT7_L2_REG_START                          0x20ee0d00
+#define BCHP_SYMCNT7_L2_REG_END                            0x20ee0d14
+#define BCHP_GCI_0_REG_START                               0x20ee1000
+#define BCHP_GCI_0_REG_END                                 0x20ee120c
+#define BCHP_GCI_1_REG_START                               0x20ee1400
+#define BCHP_GCI_1_REG_END                                 0x20ee1604
+#define BCHP_GCI_2_REG_START                               0x20ee1800
+#define BCHP_GCI_2_REG_END                                 0x20ee1a04
+#define BCHP_USB_CAPS_REG_START                            0x21000000
+#define BCHP_USB_CAPS_REG_END                              0x2100002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x21000100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x2100010c
+#define BCHP_USB_INTR2_REG_START                           0x21000180
+#define BCHP_USB_INTR2_REG_END                             0x210001ac
+#define BCHP_USB_CTRL_REG_START                            0x21000200
+#define BCHP_USB_CTRL_REG_END                              0x210002fc
+#define BCHP_USB_EHCI_REG_START                            0x21000300
+#define BCHP_USB_EHCI_REG_END                              0x210003a4
+#define BCHP_USB_OHCI_REG_START                            0x21000400
+#define BCHP_USB_OHCI_REG_END                              0x21000454
+#define BCHP_USB_XHCI_REG_START                            0x21001000
+#define BCHP_USB_XHCI_REG_END                              0x21001ffc
+#define BCHP_USB1_CAPS_REG_START                           0x21010000
+#define BCHP_USB1_CAPS_REG_END                             0x2101002c
+#define BCHP_USB1_INTR2_REG_START                          0x21010180
+#define BCHP_USB1_INTR2_REG_END                            0x210101ac
+#define BCHP_USB1_CTRL_REG_START                           0x21010200
+#define BCHP_USB1_CTRL_REG_END                             0x210102fc
+#define BCHP_USB1_EHCI_REG_START                           0x21010300
+#define BCHP_USB1_EHCI_REG_END                             0x210103a4
+#define BCHP_USB1_OHCI_REG_START                           0x21010400
+#define BCHP_USB1_OHCI_REG_END                             0x21010454
+#define BCHP_USB1_XHCI_REG_START                           0x21011000
+#define BCHP_USB1_XHCI_REG_END                             0x21011ffc
+#define BCHP_USB1_BDC_REG_START                            0x21012000
+#define BCHP_USB1_BDC_REG_END                              0x21012fc0
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START                 0x21080000
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END                   0x2108003c
+#define BCHP_PCIE_0_RC_CFG_PM_REG_START                    0x21080048
+#define BCHP_PCIE_0_RC_CFG_PM_REG_END                      0x2108004c
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START                  0x210800ac
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END                    0x210800e4
+#define BCHP_PCIE_0_RC_CFG_AER_REG_START                   0x21080100
+#define BCHP_PCIE_0_RC_CFG_AER_REG_END                     0x21080134
+#define BCHP_PCIE_0_RC_CFG_VC_REG_START                    0x21080160
+#define BCHP_PCIE_0_RC_CFG_VC_REG_END                      0x21080178
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START                0x21080180
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END                  0x210801a4
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START                 0x21080404
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END                   0x21080418
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START                 0x21080428
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END                   0x21080630
+#define BCHP_PCIE_0_RC_TL_REG_START                        0x21080800
+#define BCHP_PCIE_0_RC_TL_REG_END                          0x21080998
+#define BCHP_PCIE_0_RC_DL_REG_START                        0x21081000
+#define BCHP_PCIE_0_RC_DL_REG_END                          0x21081424
+#define BCHP_PCIE_0_RC_PL_REG_START                        0x21081800
+#define BCHP_PCIE_0_RC_PL_REG_END                          0x21081e1c
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START                 0x21082000
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END                   0x2108203c
+#define BCHP_PCIE_0_EP_CFG_PM_REG_START                    0x21082048
+#define BCHP_PCIE_0_EP_CFG_PM_REG_END                      0x2108204c
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_START                   0x21082050
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_END                     0x21082054
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_START                   0x21082058
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_END                     0x21082064
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START                  0x210820a0
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END                    0x210820a8
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START                  0x210820ac
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END                    0x210820e4
+#define BCHP_PCIE_0_EP_CFG_AER_REG_START                   0x21082100
+#define BCHP_PCIE_0_EP_CFG_AER_REG_END                     0x21082134
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_START                   0x2108213c
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_END                     0x21082144
+#define BCHP_PCIE_0_EP_CFG_PB_REG_START                    0x21082150
+#define BCHP_PCIE_0_EP_CFG_PB_REG_END                      0x2108215c
+#define BCHP_PCIE_0_EP_CFG_VC_REG_START                    0x21082160
+#define BCHP_PCIE_0_EP_CFG_VC_REG_END                      0x21082178
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START                0x21082180
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END                  0x210821a4
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START                 0x21082404
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END                   0x21082418
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START                 0x21082428
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END                   0x21082630
+#define BCHP_PCIE_0_EP_TL_REG_START                        0x21082800
+#define BCHP_PCIE_0_EP_TL_REG_END                          0x21082998
+#define BCHP_PCIE_0_EP_DL_REG_START                        0x21083000
+#define BCHP_PCIE_0_EP_DL_REG_END                          0x21083424
+#define BCHP_PCIE_0_EP_PL_REG_START                        0x21083800
+#define BCHP_PCIE_0_EP_PL_REG_END                          0x21083e1c
+#define BCHP_PCIE_0_MISC_REG_START                         0x21084000
+#define BCHP_PCIE_0_MISC_REG_END                           0x210840cc
+#define BCHP_PCIE_0_MISC_PERST_REG_START                   0x21084100
+#define BCHP_PCIE_0_MISC_PERST_REG_END                     0x21084104
+#define BCHP_PCIE_0_MISC_HARD_REG_START                    0x21084200
+#define BCHP_PCIE_0_MISC_HARD_REG_END                      0x21084204
+#define BCHP_PCIE_0_INTR2_REG_START                        0x21084300
+#define BCHP_PCIE_0_INTR2_REG_END                          0x2108432c
+#define BCHP_PCIE_0_DMA_REG_START                          0x21084400
+#define BCHP_PCIE_0_DMA_REG_END                            0x2108446c
+#define BCHP_PCIE_0_EXT_CFG_REG_START                      0x21088000
+#define BCHP_PCIE_0_EXT_CFG_REG_END                        0x21089008
+#define BCHP_PCIE_0_RGR1_REG_START                         0x21089200
+#define BCHP_PCIE_0_RGR1_REG_END                           0x21089210
+#define BCHP_PCIE_0_RG_REG_START                           0x21089300
+#define BCHP_PCIE_0_RG_REG_END                             0x2108930c
+#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_START                 0x21090000
+#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_END                   0x2109003c
+#define BCHP_PCIE_1_RC_CFG_PM_REG_START                    0x21090048
+#define BCHP_PCIE_1_RC_CFG_PM_REG_END                      0x2109004c
+#define BCHP_PCIE_1_RC_CFG_PCIE_REG_START                  0x210900ac
+#define BCHP_PCIE_1_RC_CFG_PCIE_REG_END                    0x210900e4
+#define BCHP_PCIE_1_RC_CFG_AER_REG_START                   0x21090100
+#define BCHP_PCIE_1_RC_CFG_AER_REG_END                     0x21090134
+#define BCHP_PCIE_1_RC_CFG_VC_REG_START                    0x21090160
+#define BCHP_PCIE_1_RC_CFG_VC_REG_END                      0x21090178
+#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_START                0x21090180
+#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_END                  0x210901a4
+#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_START                 0x21090404
+#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_END                   0x21090418
+#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_START                 0x21090428
+#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_END                   0x21090630
+#define BCHP_PCIE_1_RC_TL_REG_START                        0x21090800
+#define BCHP_PCIE_1_RC_TL_REG_END                          0x21090998
+#define BCHP_PCIE_1_RC_DL_REG_START                        0x21091000
+#define BCHP_PCIE_1_RC_DL_REG_END                          0x21091424
+#define BCHP_PCIE_1_RC_PL_REG_START                        0x21091800
+#define BCHP_PCIE_1_RC_PL_REG_END                          0x21091e1c
+#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_START                 0x21092000
+#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_END                   0x2109203c
+#define BCHP_PCIE_1_EP_CFG_PM_REG_START                    0x21092048
+#define BCHP_PCIE_1_EP_CFG_PM_REG_END                      0x2109204c
+#define BCHP_PCIE_1_EP_CFG_VPD_REG_START                   0x21092050
+#define BCHP_PCIE_1_EP_CFG_VPD_REG_END                     0x21092054
+#define BCHP_PCIE_1_EP_CFG_MSI_REG_START                   0x21092058
+#define BCHP_PCIE_1_EP_CFG_MSI_REG_END                     0x21092064
+#define BCHP_PCIE_1_EP_CFG_MSIX_REG_START                  0x210920a0
+#define BCHP_PCIE_1_EP_CFG_MSIX_REG_END                    0x210920a8
+#define BCHP_PCIE_1_EP_CFG_PCIE_REG_START                  0x210920ac
+#define BCHP_PCIE_1_EP_CFG_PCIE_REG_END                    0x210920e4
+#define BCHP_PCIE_1_EP_CFG_AER_REG_START                   0x21092100
+#define BCHP_PCIE_1_EP_CFG_AER_REG_END                     0x21092134
+#define BCHP_PCIE_1_EP_CFG_DEV_REG_START                   0x2109213c
+#define BCHP_PCIE_1_EP_CFG_DEV_REG_END                     0x21092144
+#define BCHP_PCIE_1_EP_CFG_PB_REG_START                    0x21092150
+#define BCHP_PCIE_1_EP_CFG_PB_REG_END                      0x2109215c
+#define BCHP_PCIE_1_EP_CFG_VC_REG_START                    0x21092160
+#define BCHP_PCIE_1_EP_CFG_VC_REG_END                      0x21092178
+#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_START                0x21092180
+#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_END                  0x210921a4
+#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_START                 0x21092404
+#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_END                   0x21092418
+#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_START                 0x21092428
+#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_END                   0x21092630
+#define BCHP_PCIE_1_EP_TL_REG_START                        0x21092800
+#define BCHP_PCIE_1_EP_TL_REG_END                          0x21092998
+#define BCHP_PCIE_1_EP_DL_REG_START                        0x21093000
+#define BCHP_PCIE_1_EP_DL_REG_END                          0x21093424
+#define BCHP_PCIE_1_EP_PL_REG_START                        0x21093800
+#define BCHP_PCIE_1_EP_PL_REG_END                          0x21093e1c
+#define BCHP_PCIE_1_MISC_REG_START                         0x21094000
+#define BCHP_PCIE_1_MISC_REG_END                           0x210940cc
+#define BCHP_PCIE_1_MISC_PERST_REG_START                   0x21094100
+#define BCHP_PCIE_1_MISC_PERST_REG_END                     0x21094104
+#define BCHP_PCIE_1_MISC_HARD_REG_START                    0x21094200
+#define BCHP_PCIE_1_MISC_HARD_REG_END                      0x21094204
+#define BCHP_PCIE_1_INTR2_REG_START                        0x21094300
+#define BCHP_PCIE_1_INTR2_REG_END                          0x2109432c
+#define BCHP_PCIE_1_DMA_REG_START                          0x21094400
+#define BCHP_PCIE_1_DMA_REG_END                            0x2109446c
+#define BCHP_PCIE_1_EXT_CFG_REG_START                      0x21098000
+#define BCHP_PCIE_1_EXT_CFG_REG_END                        0x21099008
+#define BCHP_PCIE_1_RGR1_REG_START                         0x21099200
+#define BCHP_PCIE_1_RGR1_REG_END                           0x21099210
+#define BCHP_PCIE_1_RG_REG_START                           0x21099300
+#define BCHP_PCIE_1_RG_REG_END                             0x2109930c
+#define BCHP_G2U_REGS_REG_START                            0x210a0000
+#define BCHP_G2U_REGS_REG_END                              0x210a0030
+#define BCHP_WEBHIF_RGR_REG_START                          0x210b0000
+#define BCHP_WEBHIF_RGR_REG_END                            0x210b0010
+#define BCHP_WEBHIF_INTR2_REG_START                        0x210b0100
+#define BCHP_WEBHIF_INTR2_REG_END                          0x210b012c
+#define BCHP_WEBHIF_CPU_INTR1_REG_START                    0x210b0600
+#define BCHP_WEBHIF_CPU_INTR1_REG_END                      0x210b064c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x210b0700
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x210b074c
+#define BCHP_WEBHIF_SCRATCH_REG_START                      0x210b0800
+#define BCHP_WEBHIF_SCRATCH_REG_END                        0x210b081c
+#define BCHP_WEBHIF_TIMER_REG_START                        0x210b0900
+#define BCHP_WEBHIF_TIMER_REG_END                          0x210b093c
+#define BCHP_WEBHIF_TOP_CTRL_REG_START                     0x210b0a00
+#define BCHP_WEBHIF_TOP_CTRL_REG_END                       0x210b0a00
+#define BCHP_RG_PM_REG_START                               0x210b0e00
+#define BCHP_RG_PM_REG_END                                 0x210b0e1c
+#define BCHP_PMBM_REG_START                                0x210b0f00
+#define BCHP_PMBM_REG_END                                  0x210b0f0c
+#define BCHP_WEBHIF_IPI0_INTR2_REG_START                   0x210b1000
+#define BCHP_WEBHIF_IPI0_INTR2_REG_END                     0x210b102c
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START               0x210b2000
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END                 0x210b202c
+#define BCHP_DATA_MEM_REG_START                            0x21200000
+#define BCHP_DATA_MEM_REG_END                              0x21247ffc
+#define BCHP_CNTL_MEM_REG_START                            0x21320000
+#define BCHP_CNTL_MEM_REG_END                              0x21367ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x213c0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x213c0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x213c0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x213c0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x213c0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x213c0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x213c0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x213c0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x213c0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x213c0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x213c0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x213c0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x213c0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x213c0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x213c0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x213c0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x213c0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x213c0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x213c0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x213c0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x213c00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x213c00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x213c00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x213c00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x213c00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x213c00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x213c00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x213c00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x213c00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x213c00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x213c00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x213c00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x213c0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x213c0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x213c0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x213c0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x213c0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x213c0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x213c0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x213c0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x213c0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x213c0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x213c4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x213c4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x213c4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x213c4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x213c4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x213c4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x213c4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x213c4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x213c4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x213c4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x213c4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x213c4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x213c4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x213c4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x213c4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x213c4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x213c4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x213c4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x213c4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x213c4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x213c40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x213c40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x213c40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x213c40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x213c40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x213c40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x213c40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x213c40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x213c40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x213c40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x213c40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x213c40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x213c4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x213c4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x213c4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x213c4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x213c4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x213c4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x213c4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x213c4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x213c4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x213c4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x213c4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x213c4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x213c4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x213c4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x213c4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x213c4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x213c4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x213c4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x213c4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x213c4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x213c4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x213c4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x213c4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x213c4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x213c4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x213c4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x213c4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x213c4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x213c4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x213c4c00
+#define BCHP_MAC_AHB_REG_START                             0x213c5000
+#define BCHP_MAC_AHB_REG_END                               0x213c500c
+#define BCHP_LLM_AHB_REG_START                             0x213c8000
+#define BCHP_LLM_AHB_REG_END                               0x213c805c
+#define BCHP_PHY_REG_START                                 0x213e0000
+#define BCHP_PHY_REG_END                                   0x213e47fc
+#define BCHP_ECL_REG_START                                 0x213e8000
+#define BCHP_ECL_REG_END                                   0x213ecb20
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x213ed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x213ed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x213ed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x213ed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x213ed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x213ed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x213ed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x213ed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x213ed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x213ed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x213ed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x213ed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x213ed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x213ed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x213ed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x213ed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x213ed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x213ed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x213ed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x213ed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x213ed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x213ed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x213ed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x213ed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x213ed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x213ed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x213ed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x213ed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x213ed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x213ed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x213ed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x213ed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x213ed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x213ed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x213ed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x213ed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x213ed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x213ed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x213ed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x213ed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x213ed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x213ed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x213ed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x213ed828
+#define BCHP_GMII_REG_START                                0x213edc00
+#define BCHP_GMII_REG_END                                  0x213edc58
+#define BCHP_MAC_APB_REG_START                             0x213f0000
+#define BCHP_MAC_APB_REG_END                               0x213f14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x213f4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x213f4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x213f4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x213f406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x213f4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x213f40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x213f40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x213f40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x213f4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x213f412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x213f4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x213f416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x213f4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x213f41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x213f41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x213f41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x213f4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x213f422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x213f4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x213f426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x213f4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x213f42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x213f42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x213f42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x213f4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x213f432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x213f4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x213f436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x213f4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x213f43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x213f43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x213f43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x213f4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x213f442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x213f4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x213f446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x213f4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x213f44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x213f44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x213f44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x213f4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x213f452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x213f4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x213f4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x213f4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x213f486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x213f4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x213f48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x213f48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x213f48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x213f4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x213f492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x213f4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x213f496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x213f4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x213f49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x213f49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x213f49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x213f4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x213f4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x213f6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x213f6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x213f6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x213f6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x213f6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x213f6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x213f8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x213f8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x213f8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x213f8d84
+#define BCHP_LLM_APB_REG_START                             0x213fc000
+#define BCHP_LLM_APB_REG_END                               0x213fd00c
+#define BCHP_TRX_REG_START                                 0x213fe000
+#define BCHP_TRX_REG_END                                   0x213fe1fc
+#define BCHP_MOCA_TIMER_REG_START                          0x213fe400
+#define BCHP_MOCA_TIMER_REG_END                            0x213fe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x213fe800
+#define BCHP_MOCA_GPIO_REG_END                             0x213fe818
+#define BCHP_EXTRAS_REG_START                              0x213fec00
+#define BCHP_EXTRAS_REG_END                                0x213fed18
+#define BCHP_MOCA_BSC_REG_START                            0x213ff000
+#define BCHP_MOCA_BSC_REG_END                              0x213ff058
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x213ffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x213ffc14
+#define BCHP_AHB_M2M_DMA_REG_START                         0x213ffc20
+#define BCHP_AHB_M2M_DMA_REG_END                           0x213ffc2c
+#define BCHP_MOCA_L2_REG_START                             0x213ffc40
+#define BCHP_MOCA_L2_REG_END                               0x213ffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x213ffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x213ffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x213ffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x213ffd9c
+#define BCHP_MC_GLB_0_REG_START                            0x21500000
+#define BCHP_MC_GLB_0_REG_END                              0x21500010
+#define BCHP_MC_SRAM_REMAP_0_REG_START                     0x21500020
+#define BCHP_MC_SRAM_REMAP_0_REG_END                       0x2150002c
+#define BCHP_MC_RBF_REORDER_0_0_REG_START                  0x21500040
+#define BCHP_MC_RBF_REORDER_0_0_REG_END                    0x2150007c
+#define BCHP_MC_INTR2_0_REG_START                          0x21500080
+#define BCHP_MC_INTR2_0_REG_END                            0x215000c4
+#define BCHP_MC_BPM_0_REG_START                            0x215000e0
+#define BCHP_MC_BPM_0_REG_END                              0x215000e4
+#define BCHP_MC_CHN_CFG_0_REG_START                        0x21500100
+#define BCHP_MC_CHN_CFG_0_REG_END                          0x21500198
+#define BCHP_MC_CHN_TIM_0_REG_START                        0x21500200
+#define BCHP_MC_CHN_TIM_0_REG_END                          0x2150023c
+#define BCHP_MC_ARB_0_REG_START                            0x21500300
+#define BCHP_MC_ARB_0_REG_END                              0x21500394
+#define BCHP_MC_UBUSIF_0_0_REG_START                       0x21500400
+#define BCHP_MC_UBUSIF_0_0_REG_END                         0x2150041c
+#define BCHP_MC_UBUSIF_1_0_REG_START                       0x21500440
+#define BCHP_MC_UBUSIF_1_0_REG_END                         0x2150045c
+#define BCHP_MC_MCPIF_0_0_REG_START                        0x21500500
+#define BCHP_MC_MCPIF_0_0_REG_END                          0x21500520
+#define BCHP_MC_EXACC_0_REG_START                          0x21500580
+#define BCHP_MC_EXACC_0_REG_END                            0x215005dc
+#define BCHP_MC_LMBIF_0_0_REG_START                        0x21500600
+#define BCHP_MC_LMBIF_0_0_REG_END                          0x2150060c
+#define BCHP_MC_EDIS_0_0_REG_START                         0x21500800
+#define BCHP_MC_EDIS_0_0_REG_END                           0x215008fc
+#define BCHP_MC_EDIS_1_0_REG_START                         0x21500900
+#define BCHP_MC_EDIS_1_0_REG_END                           0x215009fc
+#define BCHP_MC_STATS_0_REG_START                          0x21500a00
+#define BCHP_MC_STATS_0_REG_END                            0x21500a30
+#define BCHP_MC_CAP_0_REG_START                            0x21500a80
+#define BCHP_MC_CAP_0_REG_END                              0x21500aec
+#define BCHP_MC_SEC_SRAM_REMAP_0_REG_START                 0x21500b00
+#define BCHP_MC_SEC_SRAM_REMAP_0_REG_END                   0x21500b0c
+#define BCHP_MC_CORE_ATW_0_REG_START                       0x21500c00
+#define BCHP_MC_CORE_ATW_0_REG_END                         0x21500db8
+#define BCHP_MC_SEC_INTR2_0_REG_START                      0x21500e00
+#define BCHP_MC_SEC_INTR2_0_REG_END                        0x21500e14
+#define BCHP_MC_RGR_BRIDGE_0_REG_START                     0x21500e80
+#define BCHP_MC_RGR_BRIDGE_0_REG_END                       0x21500e90
+#define BCHP_MC_SCBARB_0_REG_START                         0x21501000
+#define BCHP_MC_SCBARB_0_REG_END                           0x215014f0
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_0_REG_START           0x21501800
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_0_REG_END             0x21501b5c
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_0_REG_START            0x21501c00
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_0_REG_END              0x21501f5c
+#define BCHP_MC_MSA_0_REG_START                            0x21502000
+#define BCHP_MC_MSA_0_REG_END                              0x2150223c
+#define BCHP_PHY_CONTROL_REGS_0_REG_START                  0x21504000
+#define BCHP_PHY_CONTROL_REGS_0_REG_END                    0x21504218
+#define BCHP_PHY_BYTE_LANE_0_0_REG_START                   0x21504400
+#define BCHP_PHY_BYTE_LANE_0_0_REG_END                     0x21504518
+#define BCHP_PHY_BYTE_LANE_1_0_REG_START                   0x21504600
+#define BCHP_PHY_BYTE_LANE_1_0_REG_END                     0x21504718
+#define BCHP_PHY_BYTE_LANE_2_0_REG_START                   0x21504800
+#define BCHP_PHY_BYTE_LANE_2_0_REG_END                     0x21504918
+#define BCHP_PHY_BYTE_LANE_3_0_REG_START                   0x21504a00
+#define BCHP_PHY_BYTE_LANE_3_0_REG_END                     0x21504b18
+#define BCHP_PHY_ECC_LANE_0_REG_START                      0x21504c00
+#define BCHP_PHY_ECC_LANE_0_REG_END                        0x21504d18
+#define BCHP_MC_GLB_1_REG_START                            0x21580000
+#define BCHP_MC_GLB_1_REG_END                              0x21580010
+#define BCHP_MC_SRAM_REMAP_1_REG_START                     0x21580020
+#define BCHP_MC_SRAM_REMAP_1_REG_END                       0x2158002c
+#define BCHP_MC_RBF_REORDER_0_1_REG_START                  0x21580040
+#define BCHP_MC_RBF_REORDER_0_1_REG_END                    0x2158007c
+#define BCHP_MC_INTR2_1_REG_START                          0x21580080
+#define BCHP_MC_INTR2_1_REG_END                            0x215800c4
+#define BCHP_MC_BPM_1_REG_START                            0x215800e0
+#define BCHP_MC_BPM_1_REG_END                              0x215800e4
+#define BCHP_MC_CHN_CFG_1_REG_START                        0x21580100
+#define BCHP_MC_CHN_CFG_1_REG_END                          0x21580198
+#define BCHP_MC_CHN_TIM_1_REG_START                        0x21580200
+#define BCHP_MC_CHN_TIM_1_REG_END                          0x2158023c
+#define BCHP_MC_ARB_1_REG_START                            0x21580300
+#define BCHP_MC_ARB_1_REG_END                              0x21580394
+#define BCHP_MC_UBUSIF_0_1_REG_START                       0x21580400
+#define BCHP_MC_UBUSIF_0_1_REG_END                         0x2158041c
+#define BCHP_MC_UBUSIF_1_1_REG_START                       0x21580440
+#define BCHP_MC_UBUSIF_1_1_REG_END                         0x2158045c
+#define BCHP_MC_MCPIF_0_1_REG_START                        0x21580500
+#define BCHP_MC_MCPIF_0_1_REG_END                          0x21580520
+#define BCHP_MC_EXACC_1_REG_START                          0x21580580
+#define BCHP_MC_EXACC_1_REG_END                            0x215805dc
+#define BCHP_MC_LMBIF_0_1_REG_START                        0x21580600
+#define BCHP_MC_LMBIF_0_1_REG_END                          0x2158060c
+#define BCHP_MC_EDIS_0_1_REG_START                         0x21580800
+#define BCHP_MC_EDIS_0_1_REG_END                           0x215808fc
+#define BCHP_MC_EDIS_1_1_REG_START                         0x21580900
+#define BCHP_MC_EDIS_1_1_REG_END                           0x215809fc
+#define BCHP_MC_STATS_1_REG_START                          0x21580a00
+#define BCHP_MC_STATS_1_REG_END                            0x21580a30
+#define BCHP_MC_CAP_1_REG_START                            0x21580a80
+#define BCHP_MC_CAP_1_REG_END                              0x21580aec
+#define BCHP_MC_SEC_SRAM_REMAP_1_REG_START                 0x21580b00
+#define BCHP_MC_SEC_SRAM_REMAP_1_REG_END                   0x21580b0c
+#define BCHP_MC_CORE_ATW_1_REG_START                       0x21580c00
+#define BCHP_MC_CORE_ATW_1_REG_END                         0x21580db8
+#define BCHP_MC_SEC_INTR2_1_REG_START                      0x21580e00
+#define BCHP_MC_SEC_INTR2_1_REG_END                        0x21580e14
+#define BCHP_MC_RGR_BRIDGE_1_REG_START                     0x21580e80
+#define BCHP_MC_RGR_BRIDGE_1_REG_END                       0x21580e90
+#define BCHP_MC_SCBARB_1_REG_START                         0x21581000
+#define BCHP_MC_SCBARB_1_REG_END                           0x215814f0
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_1_REG_START           0x21581800
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_1_REG_END             0x21581b5c
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_1_REG_START            0x21581c00
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_1_REG_END              0x21581f5c
+#define BCHP_MC_MSA_1_REG_START                            0x21582000
+#define BCHP_MC_MSA_1_REG_END                              0x2158223c
+#define BCHP_PHY_CONTROL_REGS_1_REG_START                  0x21584000
+#define BCHP_PHY_CONTROL_REGS_1_REG_END                    0x21584218
+#define BCHP_PHY_BYTE_LANE_0_1_REG_START                   0x21584400
+#define BCHP_PHY_BYTE_LANE_0_1_REG_END                     0x21584518
+#define BCHP_PHY_BYTE_LANE_1_1_REG_START                   0x21584600
+#define BCHP_PHY_BYTE_LANE_1_1_REG_END                     0x21584718
+#define BCHP_PHY_BYTE_LANE_2_1_REG_START                   0x21584800
+#define BCHP_PHY_BYTE_LANE_2_1_REG_END                     0x21584918
+#define BCHP_PHY_BYTE_LANE_3_1_REG_START                   0x21584a00
+#define BCHP_PHY_BYTE_LANE_3_1_REG_END                     0x21584b18
+#define BCHP_PHY_ECC_LANE_1_REG_START                      0x21584c00
+#define BCHP_PHY_ECC_LANE_1_REG_END                        0x21584d18
+
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01ffffff
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffff00
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   8
+
+/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK            0x000000ff
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT           0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_ebi.h b/include/linux/brcmstb/3390a0/bchp_ebi.h
new file mode 100644
index 000000000000..c786b82d06b8
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_ebi.h
@@ -0,0 +1,2007 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:19 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_HI_0                    0x204a0800 /* Upper 8-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_BASE_0                       0x204a0804 /* Lower 32-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x204a0808 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_HI_1                    0x204a080c /* Upper 8-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_BASE_1                       0x204a0810 /* Lower 32-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x204a0814 /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_HI_2                    0x204a0818 /* Upper 8-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_BASE_2                       0x204a081c /* Lower 32-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x204a0820 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_HI_3                    0x204a0824 /* Upper 8-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_BASE_3                       0x204a0828 /* Lower 32-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x204a082c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_HI_4                    0x204a0830 /* Upper 8-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_BASE_4                       0x204a0834 /* Lower 32-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x204a0838 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_HI_5                    0x204a083c /* Upper 8-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_BASE_5                       0x204a0840 /* Lower 32-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x204a0844 /* EBI CS Config 5 Register */
+#define BCHP_EBI_CS_BASE_HI_6                    0x204a0848 /* Upper 8-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_BASE_6                       0x204a084c /* Lower 32-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_CONFIG_6                     0x204a0850 /* EBI CS Config 6 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x204a0860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x204a0864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x204a0868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x204a086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x204a0870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x204a0874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_6                     0x204a0878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x204a0900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x204a0918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x204a0920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x204a09f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_6 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_6_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_6_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_6 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_6_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_6_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_6_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_6 - EBI CS Config 6 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_6_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_6_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_6_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_6_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_6_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_6_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_6_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_6_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_6_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_6 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_6_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_6_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_6_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_6_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_6_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffff80
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   7
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK             0x00000040
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT            6
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff8000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     15
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK                      0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT                     7
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x204a0a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_hif_intr2.h b/include/linux/brcmstb/3390a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..b2069ff8f808
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_hif_intr2.h
@@ -0,0 +1,1250 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:25 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x204a1000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x204a1004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x204a1008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x204a100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x204a1010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x204a1014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x204a1018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x204a101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x204a1020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x204a1024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x204a1028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x204a102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x000c0000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  18
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK                   0x00007fc0
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT                  6
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK                   0x00000004
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT                  2
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK               0x00000002
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT              1
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x000c0000
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     18
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK                      0x00007fc0
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT                     6
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK                      0x00000004
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT                     2
+
+/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK                  0x00000002
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT                 1
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x000c0000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   18
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK                    0x00007fc0
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT                   6
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK                    0x00000004
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT                   2
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT               1
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             18
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK              0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT             6
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK              0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT             2
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                18
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK                 0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT                6
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK                 0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT                2
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT            1
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              18
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK               0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT              6
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK               0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT              2
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x000c0000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  18
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK                   0x00007fc0
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT                  6
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK                   0x00000004
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT                  2
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK               0x00000002
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT              1
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x000c0000
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     18
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK                      0x00007fc0
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT                     6
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK                      0x00000004
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT                     2
+
+/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK                  0x00000002
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT                 1
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x000c0000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   18
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK                    0x00007fc0
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT                   6
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK                    0x00000004
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT                   2
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT               1
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             18
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK              0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT             6
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK              0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT             2
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                18
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK                 0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT                6
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK                 0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT                2
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT            1
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              18
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK               0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT              6
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK               0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT              2
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_hif_mspi.h b/include/linux/brcmstb/3390a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..b81657a1c303
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_hif_mspi.h
@@ -0,0 +1,1291 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:20 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x204a3400 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x204a3404 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x204a3408 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x204a340c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x204a3410 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x204a3414 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x204a3418 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x204a3420 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x204a3424 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR3                      0x204a3428 /* SPCR3 REGISTER */
+#define BCHP_HIF_MSPI_REVISION                   0x204a342c /* REVISION ID REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x204a3440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x204a3444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x204a3448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x204a344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x204a3450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x204a3454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x204a3458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x204a345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x204a3460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x204a3464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x204a3468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x204a346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x204a3470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x204a3474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x204a3478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x204a347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x204a3480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x204a3484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x204a3488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x204a348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x204a3490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x204a3494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x204a3498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x204a349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x204a34a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x204a34a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x204a34a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x204a34ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x204a34b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x204a34b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x204a34b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x204a34bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x204a34c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x204a34c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x204a34c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x204a34cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x204a34d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x204a34d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x204a34d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x204a34dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x204a34e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x204a34e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x204a34e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x204a34ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x204a34f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x204a34f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x204a34f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x204a34fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x204a3500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x204a3504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x204a3508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x204a350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x204a3510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x204a3514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x204a3518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x204a351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x204a3520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x204a3524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x204a3528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x204a352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x204a3530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x204a3534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x204a3538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x204a353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x204a3540 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x204a3544 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x204a3548 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x204a354c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x204a3550 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x204a3554 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x204a3558 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x204a355c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x204a3560 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x204a3564 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x204a3568 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x204a356c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x204a3570 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x204a3574 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x204a3578 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x204a357c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x204a3580 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x204a3584 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xfffffe00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    9
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000100
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              8
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* union - case data_reg_8 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK          0x000000c0
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT         6
+
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK               0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT              2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT            0x00000000
+
+/* union - case data_reg_32 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK              0x000000fc
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT             2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT           0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR3 - SPCR3 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
+#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK                         0xfffffc00
+#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT                        10
+
+/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
+#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK                            0x00000200
+#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT                           9
+#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK                     0x00000100
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT                    8
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT                  0x00000000
+
+/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK                         0x00000080
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT                        7
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT                      0x00000000
+
+/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK                        0x00000040
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT                       6
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT                     0x00000000
+
+/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
+#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK                          0x00000030
+#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT                         4
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK                          0x0000000c
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
+#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK                            0x00000002
+#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT                           1
+#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
+#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK                            0x00000001
+#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT                           0
+#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *REVISION - REVISION ID REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_REVISION_reserved0_MASK                      0xffffff00
+#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT                     8
+
+/* HIF_MSPI :: REVISION :: major [07:04] */
+#define BCHP_HIF_MSPI_REVISION_major_MASK                          0x000000f0
+#define BCHP_HIF_MSPI_REVISION_major_SHIFT                         4
+#define BCHP_HIF_MSPI_REVISION_major_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: REVISION :: minor [03:00] */
+#define BCHP_HIF_MSPI_REVISION_minor_MASK                          0x0000000f
+#define BCHP_HIF_MSPI_REVISION_minor_SHIFT                         0
+#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT                       0x00000005
+
+/***************************************************************************
+ *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/3390a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..acfc29949a9b
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,566 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:09 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x204a1a00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x204a1a04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x204a1a08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x204a1a0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x204a1a10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x204a1a14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x204a1a18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x204a1a1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x204a1a20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x204a1a24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x204a1a28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x204a1a2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_irq0.h b/include/linux/brcmstb/3390a0/bchp_irq0.h
new file mode 100644
index 000000000000..7fd9189f3458
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_irq0.h
@@ -0,0 +1,166 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Jun 21 03:10:25 2014
+ *                 Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              ad87f49099acb161d3ffa5d223fcb978
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x2040a600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x2040a604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xfffffc00
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: gio_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000200
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            9
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: iice_irqen [08:08] */
+#define BCHP_IRQ0_IRQEN_iice_irqen_MASK                            0x00000100
+#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT                           8
+#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [07:07] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x00000080
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           7
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x00000040
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           6
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000020
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             5
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00000004
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          2
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00000002
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          1
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00000001
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          0
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xfffffc00
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: gioirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000200
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             9
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: iiceirq [08:08] */
+#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK                             0x00000100
+#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT                            8
+#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [07:07] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x00000080
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            7
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x00000040
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            6
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000020
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              5
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uairq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00000004
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          2
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00000002
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          1
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00000001
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          0
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_nand.h b/include/linux/brcmstb/3390a0/bchp_nand.h
new file mode 100644
index 000000000000..220089d3c4f5
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_nand.h
@@ -0,0 +1,3757 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:22 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x204a2800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x204a2804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x204a2808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x204a280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x204a2810 /* Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x204a2814 /* Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x204a2818 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x204a281c /* Nand Flash EBI CS XOR masking on CPU address Control */
+#define BCHP_NAND_LL_OP                          0x204a2820 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x204a2824 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x204a2828 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x204a2850 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS0                 0x204a2854 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS0                     0x204a2858 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x204a285c /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x204a2860 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x204a2864 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS1                 0x204a2868 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS1                     0x204a286c /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x204a2870 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x204a2874 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x204a2878 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS2                 0x204a287c /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS2                     0x204a2880 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x204a2884 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x204a2888 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x204a288c /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS3                 0x204a2890 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS3                     0x204a2894 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x204a2898 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x204a289c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x204a28a0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS4                 0x204a28a4 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS4                     0x204a28a8 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x204a28ac /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x204a28b0 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x204a28b4 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS5                 0x204a28b8 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS5                     0x204a28bc /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x204a28c0 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x204a28c4 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS6                0x204a28c8 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS6                 0x204a28cc /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS6                     0x204a28d0 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS6                   0x204a28d4 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS6                   0x204a28d8 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x204a28dc /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x204a28e0 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x204a28e4 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x204a28e8 /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x204a28ec /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x204a28f0 /* Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x204a28fc /* Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x204a2900 /* Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x204a2904 /* Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x204a2908 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x204a290c /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x204a2910 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x204a2914 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x204a2918 /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x204a291c /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x204a2920 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x204a2924 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x204a2928 /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x204a292c /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x204a2930 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x204a2934 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x204a2938 /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x204a293c /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x204a2940 /* Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x204a2944 /* Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x204a2948 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x204a294c /* ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x204a2950 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x204a2994 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x204a2998 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x204a299c /* Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x204a2a00 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x204a2a04 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x204a2a08 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x204a2a0c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x204a2a10 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x204a2a14 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x204a2a18 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x204a2a1c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x204a2a20 /* Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x204a2a24 /* Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x204a2a28 /* Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x204a2a2c /* Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x204a2a30 /* Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x204a2a34 /* Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x204a2a38 /* Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x204a2a3c /* Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x204a2a80 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x204a2a84 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x204a2a88 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x204a2a8c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x204a2a90 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x204a2a94 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x204a2a98 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x204a2a9c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x204a2aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x204a2aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x204a2aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x204a2aac /* Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x204a2ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x204a2ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x204a2ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x204a2abc /* Nand Flash Spare Area Write Bytes 60-63 */
+#define BCHP_NAND_DDR_TIMING                     0x204a2ac0 /* Nand Flash DDR TIMING */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL             0x204a2ac4 /* Nand Flash Calibration Control for Master DLL */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD          0x204a2ac8 /* Nand Flash Calibration Period */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT            0x204a2acc /* Nand Flash Calibration Status for Master DLL */
+#define BCHP_NAND_DDR_NCDL_MODE                  0x204a2ad0 /* Nand Flash NCDL mode for Slave DLLs */
+#define BCHP_NAND_DDR_NCDL_OFFSET                0x204a2ad4 /* Nand Flash NCDL offset for Slave DLLs */
+#define BCHP_NAND_DDR_PHY_CTL                    0x204a2ad8 /* Nand Flash DDR PHY CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_CTL               0x204a2adc /* Nand Flash DDR PHY BIST CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_STAT              0x204a2ae0 /* Nand Flash DDR PHY BIST STATUS */
+#define BCHP_NAND_DDR_DIAG_STAT0                 0x204a2ae4 /* Nand Flash DDR DIAG STATUS0 */
+#define BCHP_NAND_DDR_DIAG_STAT1                 0x204a2ae8 /* Nand Flash DDR DIAG STATUS1 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: reserved0 [31:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0xffff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000007
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000001
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:05] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5
+
+/* NAND :: CMD_START :: OPCODE [04:00] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK                      0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT                     29
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT                   0x00000001
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK                0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT               31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT             0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK               0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT              7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK               0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT              6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK               0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT              5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK               0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT              4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK               0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT              3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK               0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT              2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK               0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT              1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK               0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT              0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS0 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS0 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS0 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS0 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS0 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS0_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS0_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS0_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS0_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS1 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS1 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS1 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS1 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS1 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS1_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS1_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS1_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS1_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS2 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS2 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS2 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS2 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS2 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS2_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS2_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS2_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS2_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS3 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS3 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS3 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS3 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS3 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS3_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS3_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS3_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS3_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS4 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS4 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS4 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS4 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS4 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS4_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS4_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS4_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS4_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS5 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS5 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS5 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS5 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS5 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS5_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS5_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS5_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS5_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS6 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS6 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS6 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS6 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS6 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS6 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS6 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS6_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS6 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS6_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS6_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS6_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS6_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS6 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS6_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS6_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS6_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS6_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS6_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS6_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS6_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS6 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS6 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS6 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS6_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS6_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS6_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS6_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS6_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS6_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xfffff000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          12
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *DDR_TIMING - Nand Flash DDR TIMING
+ ***************************************************************************/
+/* NAND :: DDR_TIMING :: reserved0 [31:28] */
+#define BCHP_NAND_DDR_TIMING_reserved0_MASK                        0xf0000000
+#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT                       28
+
+/* NAND :: DDR_TIMING :: tCCS [27:24] */
+#define BCHP_NAND_DDR_TIMING_tCCS_MASK                             0x0f000000
+#define BCHP_NAND_DDR_TIMING_tCCS_SHIFT                            24
+#define BCHP_NAND_DDR_TIMING_tCCS_DEFAULT                          0x00000008
+
+/* NAND :: DDR_TIMING :: tCAD [23:20] */
+#define BCHP_NAND_DDR_TIMING_tCAD_MASK                             0x00f00000
+#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT                            20
+#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT                          0x00000004
+
+/* NAND :: DDR_TIMING :: reserved1 [19:17] */
+#define BCHP_NAND_DDR_TIMING_reserved1_MASK                        0x000e0000
+#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT                       17
+
+/* NAND :: DDR_TIMING :: tWHR [16:12] */
+#define BCHP_NAND_DDR_TIMING_tWHR_MASK                             0x0001f000
+#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT                            12
+#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT                          0x00000014
+
+/* NAND :: DDR_TIMING :: tCS [11:08] */
+#define BCHP_NAND_DDR_TIMING_tCS_MASK                              0x00000f00
+#define BCHP_NAND_DDR_TIMING_tCS_SHIFT                             8
+#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT                           0x00000002
+
+/* NAND :: DDR_TIMING :: tWB [07:04] */
+#define BCHP_NAND_DDR_TIMING_tWB_MASK                              0x000000f0
+#define BCHP_NAND_DDR_TIMING_tWB_SHIFT                             4
+#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT                           0x0000000f
+
+/* NAND :: DDR_TIMING :: tADL [03:00] */
+#define BCHP_NAND_DDR_TIMING_tADL_MASK                             0x0000000f
+#define BCHP_NAND_DDR_TIMING_tADL_SHIFT                            0
+#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT                          0x00000007
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK                0xfffffff0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT               4
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK           0x00000008
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT          3
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT        0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK             0x00000004
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT            2
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT          0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK               0x00000002
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT              1
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT            0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK                 0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT                0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK             0xfff00000
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT            20
+
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK          0x000fffff
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT         0
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK               0xffff0000
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT              16
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK              0x0000ff00
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT             8
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT           0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK               0x000000fe
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT              1
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK              0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT             0
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT           0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK                     0xffffffe0
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT                    5
+
+/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK                        0x00000010
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT                       4
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT                     0x00000000
+
+/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK                     0x0000000e
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT                    1
+
+/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK                        0x00000001
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT                       0
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK                   0xfe000000
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT                  25
+
+/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK                  0x01ff0000
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT                 16
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT               0x00000000
+
+/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK                   0x0000fe00
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT                  9
+
+/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK                  0x000001ff
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT                 0
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT               0x00000000
+
+/***************************************************************************
+ *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK                       0xfffffffc
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT                      2
+
+/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK                        0x00000002
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT                       1
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT                     0x00000000
+
+/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK                       0x00000001
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT                      0
+
+/***************************************************************************
+ *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK                  0xffffffe0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT                 5
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK                   0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT                  4
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT                0x00000000
+
+/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK                  0x0000000e
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT                 1
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT                0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK                 0xffffff80
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT                7
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK          0x00000040
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT         6
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK          0x00000020
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT         5
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK          0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT         4
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK          0x00000008
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT         3
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK               0x00000004
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT              2
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK               0x00000002
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT              1
+
+/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT                0
+
+/***************************************************************************
+ *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x204a2c00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/3390a0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..4d050def40e5
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,823 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sun Sep 14 03:14:53 2014
+ *                 Full Compile MD5 Checksum ef22086ebd4065e4fea50dbc64f17e5e
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              39fcae49037a6337517df43bfc24b21f
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD0/EMMC0) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x204a0100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x204a0104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x204a0108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE         0x204a010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x204a0110 /* SDIO CAPABILITIES override Register[31:0] */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x204a0114 /* SDIO CAPABILITIES override Register[63:32] */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x204a0118 /* SDIO PRESET_INIT/PRESET_DS override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x204a011c /* SDIO PRESET_HS/PRESET_SDR12 override Register */
+#define BCHP_SDIO_0_CFG_PRESET3                  0x204a0120 /* SDIO PRESET_SDR25/PRESET_SDR50 override Register */
+#define BCHP_SDIO_0_CFG_PRESET4                  0x204a0124 /* SDIO PRESET_SDR104/PRESET_DDR50 override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x204a0128 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x204a012c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x204a0130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x204a0134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x204a0138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x204a013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY            0x204a0140 /* Debug TAP delay setting register */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS  0x204a0144 /* Debug A2S Bridge Status */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x204a0148 /* Debug register to read AHB req start address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR   0x204a014c /* Debug register to read AHB req end address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x204a0150 /* Disable Client Init */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL               0x204a0154 /* SD Pin Select */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT              0x204a0158 /* Max Current Override */
+#define BCHP_SDIO_0_CFG_VERSION                  0x204a01f0 /* SDIO VERSION Register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x204a01fc /* SDIO Scratch Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK             0x0ffc0000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT            18
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK        0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT       17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK             0x000003fc
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT            2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK          0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT         0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT       0x00000003
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000003
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK            0xfffffffe
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT           1
+
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK     0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT    0
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0xc0000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK                     0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT                    29
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK                0x10000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT               28
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK                    0x08000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT                   27
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK                 0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT                26
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK                 0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT                25
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK               0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT              23
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK                         0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT                        22
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT                      0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK                   0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT                  21
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK                    0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT                   20
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK                        0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT                       19
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK               0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT              18
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK                0x00030000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT               16
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK                0x0000ff00
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT               8
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK                 0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT                7
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK                    0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT                   6
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK             0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0xfc000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   26
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK               0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT              25
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    24
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x00ff0000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    16
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK                0x0000c000
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT               14
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK                   0x00002000
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT                  13
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK                    0x00001000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT                   12
+
+/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK                  0x00000f00
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT                 8
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK                    0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT                   7
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK                     0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT                    6
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK                     0x00000020
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT                    5
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK                     0x00000010
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT                    4
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT                   3
+
+/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK                        0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT                       2
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK                       0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT                      1
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT                    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK                        0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT                       0
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK                   0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT                  16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT                  0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK                  0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT                 0
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT               0x00000003
+
+/***************************************************************************
+ *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK                 0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT                0
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT              0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:05] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffe0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     5
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000001f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xffffffc0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     6
+
+/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT                  0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT                0x00000020
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *DEBUG_TAP_DLY - Debug TAP delay setting register
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK               0xfffff000
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT              12
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK      0x00000f00
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT     8
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK               0x00000080
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT              7
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK      0x0000007f
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT     0
+
+/***************************************************************************
+ *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK     0x60000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT    29
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK  0x10000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK     0x0e000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT    25
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK     0x0000ff80
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT    7
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK     0x00000070
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT    4
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK     0x00000008
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT    3
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK     0x00000007
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT    0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK   0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT  0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK       0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT      0
+
+/***************************************************************************
+ *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK   0xfffffffe
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT  1
+
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SD_PIN_SEL - SD Pin Select
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK                    0x00000003
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT                   0
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MAX_CURRENT - Max Current Override
+ ***************************************************************************/
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK                  0x80000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT                 31
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK                 0x7f000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT                24
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK             0x00ff0000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT            16
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK             0x0000ff00
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT            8
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK             0x000000ff
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT            0
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK                     0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT                    24
+
+/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK                      0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT                     16
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT                   0x00000003
+
+/* SDIO_0_CFG :: VERSION :: IP_VERSION [15:00] */
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_MASK                    0x0000ffff
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_SHIFT                   0
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_DEFAULT                 0x00001170
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/3390a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..16d6ebd08c18
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7243 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Jun 21 03:10:26 2014
+ *                 Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              ad87f49099acb161d3ffa5d223fcb978
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x20404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x20404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x20404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x2040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x20404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x20404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x20404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x2040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x20404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x20404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x20404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x2040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x20404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x20404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x20404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x2040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x20404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x20404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x20404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x2040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x20404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x20404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x20404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x2040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x20404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x20404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x20404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x2040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x20404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x20404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x20404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x2040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x20404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x20404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x20404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x2040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x204040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x204040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x204040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x204040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x204040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x204040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x204040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3       0x204040bc /* General status register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4       0x204040c0 /* General status register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x20404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x20404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x20404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x2040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x20404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x20404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x20404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x2040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x20404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x20404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x20404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x2040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x20404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x20404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x20404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x2040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x20404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x20404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x20404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x2040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x20404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x20404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x20404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x2040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x20404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x20404164 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x20404168 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x20404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x20404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x20404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x2040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x20404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x20404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x20404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x2040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x20404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x20404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x20404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x2040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x20404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x20404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x20404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x2040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x20404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x20404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x20404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x2040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x20404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x20404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x20404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x2040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x20404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE    0x20404364 /* Router software init 0 mask */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE    0x20404368 /* Router software init 0 mask */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x2040436c /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x20404370 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x20404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x20404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x20404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x2040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x20404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x20404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x20404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x204043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x204043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0      0x204043a8 /* UART Router select 0 */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1      0x204043ac /* UART Router select 1 */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x20404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x20404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x20404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x20404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x20404518 /* Test configuration */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL 0x20404520 /* Power Cycle Control */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY  0x20404524 /* Power Cycle Delay */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6         0x20404528 /* General control register 6 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7         0x2040452c /* General control register 7 */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x33900000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x33900000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffc000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            14
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [13:13] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [12:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x00001f00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_1 [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_MASK          0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_SHIFT         3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_3 [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_DEFAULT       0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie0_rc_ep [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie1_rc_ep [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_DEFAULT  0x00000001
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_rsvd_0 [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_MASK          0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT   0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_capsense_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_capsense_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_memc1_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memc1_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memc1_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memc1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p0_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rdp_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p1_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0x001ffe00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_d31ofdmb_dis [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gphy_trim_dac [15:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_MASK 0x0000f000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rgmii_1_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_d31ofdma_dis [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_mtsif_enc_ctrl_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_memc0_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_eaglet_disable [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie0_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gisb_to_ubus_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_20_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_capsense_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_capsense_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_memc1_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memc1_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memc1_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p0_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rdp_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rdp_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rdp_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p1_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0x001ffe00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_d31ofdmb_dis [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdmb_dis_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdmb_dis_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gphy_trim_dac [15:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_MASK 0x0000f000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rgmii_1_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_d31ofdma_dis [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdma_dis_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdma_dis_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_mtsif_enc_ctrl_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mtsif_enc_ctrl_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mtsif_enc_ctrl_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_memc0_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_memc0_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_memc0_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_eaglet_disable [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_eaglet_disable_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_eaglet_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie0_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gisb_to_ubus_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_20_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_pin_sel [04:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_MASK        0x00000018
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio1_pin_sel [02:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_MASK        0x00000006
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: core0_sw_init_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: disable_rg_wd_reset [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: disable_host_wd_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT    1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT   1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffffc0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   6
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_amp_en [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_gmii [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_modehv [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xe0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   29
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_060 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_059 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_058 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [20:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x001f0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xffffffe0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   5
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_018 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_017 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_016 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_015 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_014 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_STATUS_3 - General status register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_4 - General status register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_000 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_RGMII1_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_EXT_IRQB_6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_TP_IN_00         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_PM_GPIO_000      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_clk [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_EMMC1_CLK       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_PM_EMMC1_CLK    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_cmd [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_EMMC1_CMD       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_PM_EMMC1_CMD    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_nand_dqs [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_MASK         0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_EBI_NAND_DQS 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_PM_EBI_NAND_DQS 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_waitb [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_PM_EBI_WAITB    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs2b [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_EBI_CS2B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_ALT_TP_IN_10     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs1b [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_EBI_CS1B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_ALT_TP_IN_09     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs0b [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_EBI_CS0B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_ALT_TP_IN_08     1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_008 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_RGMII1_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_UART_RXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_SC0_PRES         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_TP_IN_08         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_PM_GPIO_008      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_007 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MII_RXEN_RGMII1_RXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_SC0_RST          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_EXT_IRQB_4       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_TP_IN_07         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_PM_GPIO_007      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_006 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_RGMII1_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_SC0_CLK          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_TP_IN_06         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_PM_GPIO_006      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_005 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_RGMII1_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_RMX_SYNC0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_SC0_IO           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_TP_IN_05         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_PM_GPIO_005      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_004 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_RGMII1_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_RMX_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_SC0_VPP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_TP_IN_04         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_PM_GPIO_004      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_003 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_RGMII1_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_RMX_CLK0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SC0_AUX2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_TP_IN_03         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_PM_GPIO_003      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_002 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_RGMII1_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PWM_2            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SC0_AUX1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_TP_IN_02         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PM_GPIO_002      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_001 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MII_TXEN_RGMII1_TXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_TP_IN_01         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_PM_GPIO_001      3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_016 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_CHIP2POD_CTX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_EBI_ADDR_04      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_TP_IN_12         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_PM_GPIO_016      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_015 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_CHIP2POD_CRX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_EBI_ADDR_08      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_ALT_TP_OUT_11    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_014 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_CHIP2POD_DRX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_EBI_ADDR_09      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_ALT_TP_OUT_10    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_013 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_RGMII1_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_UART_TXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_ALT_TP_OUT_09    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_012 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_RGMII1_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_UART_RXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_EXT_IRQB_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_TP_IN_09         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_PM_GPIO_012      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_011 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_RGMII1_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_UART_RTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_ALT_TP_IN_31     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_010 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_RGMII1_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_UART_CTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_EXT_IRQB_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_TP_IN_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_PM_GPIO_010      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_009 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_RGMII1_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_UART_TXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SC0_VCC          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_TP_OUT_00        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_PM_GPIO_009      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_024 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_GPIO_024         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_PKT_CLK1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SDIO1_DAT1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_LED_LD_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_HCPU_TRACE_RXD   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_MTSIF_TX1_DATA5  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_TP_IN_19         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_PM_GPIO_024      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_023 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_GPIO_023         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_PKT_VALID0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SDIO1_DAT0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_LED_LD_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_HCPU_TRACE_DATA3 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MTSIF_TX1_DATA4  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_TP_IN_18         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_PM_GPIO_023      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_022 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_GPIO_022         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_PKT_ERROR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SDIO1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_LED_LD_11        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_HCPU_TRACE_DATA2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MTSIF_TX1_DATA3  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_PM_GPIO_022      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_021 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_GPIO_021         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_PKT_SYNC0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SDIO1_PWR0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_LED_LD_10        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_HCPU_TRACE_DATA1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MTSIF_TX1_DATA2  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_TP_IN_17         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_PM_GPIO_021      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_020 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_PKT_DATA0        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SDIO1_WPROT      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_LED_LD_9         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_HCPU_TRACE_DATA0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_CHIP2POD_SCLK_1  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MTSIF_TX1_DATA1  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_TP_IN_16         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_PM_GPIO_020      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_019 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_PKT_CLK0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SDIO1_CMD        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_LED_LD_8         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_HCPU_TRACE_CLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MTSIF_TX1_DATA0  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_TP_IN_15         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_PM_GPIO_019      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_018 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_POD2CHIP_ITX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_EBI_ADDR_05      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_TP_IN_14         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_PM_GPIO_018      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_017 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_POD2CHIP_QTX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_EBI_ADDR_07      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_TP_IN_13         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_PM_GPIO_017      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_032 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_GPIO_032         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_POD2CHIP_MCLKI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_EBI_ADDR_14      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SPI_S_SS0B       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_PPKT_CLK         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SW_SPI_S_SS0B    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_TP_IN_25         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_PM_GPIO_032      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_031 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_GPIO_031         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_TXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_TP_OUT_07        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_PM_GPIO_031      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_030 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_GPIO_030         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_RXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_TP_IN_23         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_PM_GPIO_030      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_029 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_GPIO_029         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_EXT_IRQB_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_TSIO_VCTRL       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_TP_IN_22         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_PM_GPIO_029      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_028 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_GPIO_028         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_PKT_VALID1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SDIO1_LED        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_EXT_IRQB_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_POD2CHIP_SDI_1   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MTSIF_TX1_CLK    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_TP_IN_21         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_PM_GPIO_028      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_027 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_GPIO_027         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_PKT_ERROR1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SDIO1_PRES       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MTSIF_TX1_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_PM_GPIO_027      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_026 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_GPIO_026         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PKT_SYNC1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SDIO1_DAT3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_LED_LD_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MTSIF_TX1_DATA7  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_ALT_TP_IN_12     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PM_GPIO_026      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_025 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_GPIO_025         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PKT_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SDIO1_DAT2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_LED_LD_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MTSIF_TX1_DATA6  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_TP_IN_20         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PM_GPIO_025      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_040 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_GPIO_040         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_POD2CHIP_MDI0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_PPKT_DATA0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_UART_TXD_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_TP_OUT_27        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_PM_GPIO_040      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_039 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_GPIO_039         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_POD2CHIP_MIVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_PPKT_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_UART_RXD_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_TP_IN_28         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_PM_GPIO_039      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_038 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_GPIO_038         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_POD2CHIP_MISTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_PPKT_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_TP_IN_27         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_PM_GPIO_038      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_037 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_GPIO_037         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_CHIP2POD_SCTL_0  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_EBI_ADDR_02      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_ALT_TP_OUT_14    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_036 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_GPIO_036         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_CHIP2POD_SDO_0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_EBI_ADDR_00      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_ALT_TP_OUT_13    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_035 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_GPIO_035         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_POD2CHIP_SDI_0   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SW_SPI_S_MOSI    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_PM_GPIO_035      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_034 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_GPIO_034         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_CHIP2POD_SCLK_0  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_EBI_ADDR_01      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SW_SPI_S_SCK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_TP_IN_26         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_PM_GPIO_034      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_033 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_GPIO_033         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_CHIP2POD_MCLKO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_EBI_ADDR_15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SPI_S_MISO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_RMXP_CLK         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SW_SPI_S_MISO    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_ALT_TP_OUT_12    6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_048 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_GPIO_048         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_POD2CHIP_MICLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_PPKT_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_EBI_ADDR_13      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_TP_OUT_11        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_PM_GPIO_048      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_047 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_GPIO_047         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_POD2CHIP_MDI7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_PPKT_DATA7       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_EBI_ADDR_15      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_TP_OUT_10        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_PM_GPIO_047      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_046 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_GPIO_046         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_POD2CHIP_MDI6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_PPKT_DATA6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_EBI_ADDR_14      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_TP_IN_24         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_PM_GPIO_046      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_045 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_GPIO_045         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_POD2CHIP_MDI5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_PPKT_DATA5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_PM_GPIO_045      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_044 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_GPIO_044         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_POD2CHIP_MDI4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_PPKT_DATA4       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_UART_TXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_TP_OUT_08        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_PM_GPIO_044      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_043 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_GPIO_043         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_POD2CHIP_MDI3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_PPKT_DATA3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_UART_RXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_TP_IN_30         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_PM_GPIO_043      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_042 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_GPIO_042         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_POD2CHIP_MDI2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PPKT_DATA2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_UART_TXD_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_TP_OUT_09        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PM_GPIO_042      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_041 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_GPIO_041         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_POD2CHIP_MDI1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PPKT_DATA1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_UART_RXD_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_TP_IN_29         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PM_GPIO_041      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_056 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_GPIO_056         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_CHIP2POD_MDO5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_RMXP_DATA5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SC1_VPP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_EBI_ADDR_23      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_TP_OUT_19        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_PM_GPIO_056      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_055 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_GPIO_055         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_CHIP2POD_MDO4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_RMXP_DATA4       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SC1_AUX2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_EBI_ADDR_22      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_TP_OUT_18        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_PM_GPIO_055      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_054 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_GPIO_054         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_CHIP2POD_MDO3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_RMXP_DATA3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SC1_AUX1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_EBI_ADDR_21      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_TP_OUT_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_PM_GPIO_054      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_053 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_GPIO_053         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_CHIP2POD_MDO2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_RMXP_DATA2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_SC1_VCC          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_EBI_ADDR_20      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_TP_OUT_16        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_PM_GPIO_053      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_052 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_GPIO_052         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_CHIP2POD_MDO1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_RMXP_DATA1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_SC1_PRES         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_EBI_ADDR_19      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_TP_OUT_15        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_PM_GPIO_052      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_051 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_GPIO_051         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_CHIP2POD_MDO0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_RMXP_DATA0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_SC1_RST          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_EBI_ADDR_18      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_TP_OUT_14        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_PM_GPIO_051      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_050 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_GPIO_050         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_CHIP2POD_MOSTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_RMXP_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SC1_CLK          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_EBI_ADDR_17      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_ALT_TP_OUT_15    5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_049 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_GPIO_049         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_CHIP2POD_MOVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_RMXP_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SC1_IO           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_EBI_ADDR_16      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_TP_OUT_12        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_PM_GPIO_049      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_064 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_GPIO_064         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SDIO0_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_RMX_PAUSE0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PWM_2            3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_ALT_TP_IN_11     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PM_GPIO_064      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_063 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_GPIO_063         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SDIO0_PWR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SC1_VPP          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_PM_GPIO_063      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_062 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_GPIO_062         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SDIO0_WPROT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SC1_AUX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_TP_OUT_25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_PM_GPIO_062      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_061 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_GPIO_061         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SDIO0_CMD        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SC1_AUX1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_TP_OUT_24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_PM_GPIO_061      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_060 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_GPIO_060         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_POD2CHIP_ETX     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_EBI_ADDR_06      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_UART_CTS_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_TP_OUT_23        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_PM_GPIO_060      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_059 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_GPIO_059         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_CHIP2POD_MOCLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_RMXP_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_EBI_ADDR_12      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_CHIP2POD_MCLKO   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_TP_OUT_22        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_PM_GPIO_059      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_058 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_GPIO_058         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_CHIP2POD_MDO7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_RMXP_DATA7       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_EBI_ADDR_25      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_TP_OUT_21        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_PM_GPIO_058      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_057 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_GPIO_057         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_CHIP2POD_MDO6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_RMXP_DATA6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_EBI_ADDR_24      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_TP_OUT_20        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_PM_GPIO_057      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_072 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_GPIO_072        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SC0_AUX2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SPI_M_MOSI      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_PM_GPIO_072     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_071 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SC0_AUX1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SPI_M_SCK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_PM_GPIO_071     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_070 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SDIO0_LED       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_EXT_IRQB_4      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PM_GPIO_070     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_069 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SDIO0_PRES      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_CTS_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_EXT_IRQB_3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_TXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_TP_OUT_30       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_PM_GPIO_069     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_068 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SDIO0_DAT3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RTS_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_EXT_IRQB_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_TP_OUT_29       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_PM_GPIO_068     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_067 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SDIO0_DAT2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_UART_TXD_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_EXT_IRQB_1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_PM_GPIO_067     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_066 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SDIO0_DAT1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_UART_RXD_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_EXT_IRQB_0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_TP_IN_31        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_PM_GPIO_066     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_065 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SDIO0_DAT0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_RMX_PAUSE1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_TP_OUT_26       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_PM_GPIO_065     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_080 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_GPIO_080        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MII_IRQ         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_ALT_TP_IN_19    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_PM_GPIO_080     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_079 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_GPIO_079        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_TEST_THP        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PWM_1           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_UART_CTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_ALT_TP_IN_18    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PM_GPIO_079     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_078 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_GPIO_078        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_SC0_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_ALT_TP_IN_17    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PM_GPIO_078     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_077 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_GPIO_077        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_SC0_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_ALT_TP_IN_16    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_PM_GPIO_077     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_076 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_GPIO_076        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SC0_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SPI_M_SS2B      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_ALT_TP_IN_15    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_PM_GPIO_076     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_075 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_GPIO_075        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SC0_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SPI_M_SS1B      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_ALT_TP_IN_14    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_PM_GPIO_075     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_074 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_GPIO_074        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SC0_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SPI_M_SS0B      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_ALT_TP_IN_13    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_PM_GPIO_074     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_073 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_GPIO_073        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SC0_VPP         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SPI_M_MISO      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_PM_GPIO_073     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_088 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_GPIO_088        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_EBI_ADDR_10     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PWM_1           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_MODEHV_D        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_ALT_TP_IN_26    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PM_GPIO_088     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_087 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_GPIO_087        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_EBI_ADDR_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PWM_0           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_MODEHV_A        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_ALT_TP_IN_25    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PM_GPIO_087     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_086 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_GPIO_086        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_EXT_IRQB_5      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SDIO1_VOLT      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SC_EXT_CLK      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_RGMII1_RX_OK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_CHIP2POD_SDO_1  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_ALT_TP_IN_24    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_PM_GPIO_086     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_085 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_GPIO_085        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_CHIP2POD_SDO_1  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SDIO0_VOLT      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PWM_3           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_RGMII1_START_STOP 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_ALT_TP_IN_23    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PM_GPIO_085     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_084 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_GPIO_084        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MII_TX_ERR      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_083 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_GPIO_083        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MII_RX_ERR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_RMX_SYNC1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_UART_RTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_ALT_TP_IN_22    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_PM_GPIO_083     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_082 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_GPIO_082        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_RMX_DATA1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_UART_RXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_ALT_TP_IN_21    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_PM_GPIO_082     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_081 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_GPIO_081        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_RMX_CLK1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_UART_TXD_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PWM_3           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_ALT_TP_IN_20    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PM_GPIO_081     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_096 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_GPIO_096        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SPI_M_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_ZIG_SECI_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_PM_GPIO_096     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_095 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_GPIO_095        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SPI_M_MOSI      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_094 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_GPIO_094        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SPI_M_SCK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_ZIG_SECI_0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_PM_GPIO_094     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_093 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_GPIO_093        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SW_LED_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_TP_IN_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_PM_GPIO_093     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_092 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_GPIO_092        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SW_LED_DATA     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_ALT_TP_IN_30    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_PM_GPIO_092     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_091 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_GPIO_091        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_EBI_RWB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_ALT_TP_IN_29    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_PM_GPIO_091     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_090 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_GPIO_090        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_EBI_CS3B        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_ALT_TP_IN_28    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PM_GPIO_090     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_089 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_GPIO_089        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_EBI_ADDR_11     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MODEHV_F        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_ALT_TP_IN_27    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PM_GPIO_089     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_01 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_BSC_M4_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MOCA_BSC_SDA    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_00 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_BSC_M4_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MOCA_BSC_SCL    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_102 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SDIO1_CLK_IN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_CHIP2POD_SCTL_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_PM_GPIO_102     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_101 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SDIO0_CLK_IN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_PM_GPIO_101     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_100 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PWM_0           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PM_GPIO_100     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_099 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_GPIO_099        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SPI_M_SS2B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PM_GPIO_099     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_098 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_GPIO_098        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SPI_M_SS1B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_ZIG_SECI_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_PM_GPIO_098     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_097 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_GPIO_097        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SPI_M_SS0B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_ZIG_SECO        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: byp_hs_stb_clk [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_BYP_HS_STB_CLK 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_CLK_OUT0  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M3_SCL      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_tsb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_rdb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_we1b_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_we0b_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs2b_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs1b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs0b_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_rstb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie0_clkreqb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie0_rstb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_clk_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_cmd_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_wpb_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_MASK  0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_holdb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK  0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_dqs_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_waitb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_wpb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_rbb_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_dsb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_009_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_008_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_008_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_007_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_006_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_005_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_004_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_003_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_002_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_001_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_000_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [09:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x000003fc
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie1_clkreqb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_024_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_023_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_022_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_021_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_020_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_019_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_018_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_017_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_016_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [11:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x00000fc0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_012_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK        0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_010_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_039_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_038_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [25:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x03c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_035_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_034_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_032_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_031_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_030_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_029_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_028_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_027_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_026_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_025_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_054_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_053_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_052_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_051_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_049_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_048_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_047_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_046_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_045_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_044_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_043_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_042_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_041_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_040_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_069_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_068_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_067_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_066_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_065_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_064_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_063_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_062_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_061_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_060_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_059_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_058_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_057_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_056_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_055_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: reserved0 [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_MASK        0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_083_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_083_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_082_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_081_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_080_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_079_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_078_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_077_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_076_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_075_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_074_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_073_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_072_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_071_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_070_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_099_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_099_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_098_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_098_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_096_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_094_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_093_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_092_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved2 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved2_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved2_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_089_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_088_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_087_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_086_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_085_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0xff000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved1 [21:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_MASK        0x003fffc0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_SHIFT       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_102_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_101_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_100_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffff8000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       15
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_500_514p28_clk [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_hs_stb_clk [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_073 [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_072 [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_071 [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_063 [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_039 [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_035 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_027 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_wpb [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_holdb [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_dqs [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_waitb [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_dsb [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_tsb [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffff000
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      12
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          2
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: local_master_reset [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [29:29] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 29
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [28:28] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 28
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 27
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 26
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [25:25] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK      0x02000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT     25
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_cpu_ejtag_reset [24:24] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_MASK    0x01000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_SHIFT   24
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_cpu_ejtag_reset [23:23] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_MASK    0x00800000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_SHIFT   23
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: host_cpu_ejtag_reset [22:22] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_MASK  0x00400000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_SHIFT 22
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: powerloss_reset [21:21] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_SHIFT      21
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overvoltage_1_reset [20:20] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_SHIFT 20
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_1_reset [19:19] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_SHIFT 19
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_0_reset [18:18] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_SHIFT 18
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [17:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT  17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK  0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK  0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overtemp_reset [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_SHIFT    14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_software_master_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_SHIFT 11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: local_software_master_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_SHIFT 10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_watchdog_timer_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_watchdog_timer_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: host_watchdog_timer_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_SHIFT 4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_SHIFT  31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_MASK   0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_SHIFT  29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_MASK       0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_SHIFT      26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK          0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT         22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK         0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT        20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_MASK   0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_SHIFT  15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_SHIFT  14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_MASK   0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_SHIFT  10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_MASK    0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_SHIFT   9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK        0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT       22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK       0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_MASK    0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_SHIFT   26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT      22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK      0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK  0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_MASK   0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_SHIFT  10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK         0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT        7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT  9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK       0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK       0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT      7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_11_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffc000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffc000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RG_SW_INIT_0_ENABLE - Router software init 0 mask
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_MASK    0x10000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_SHIFT   28
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: gphy_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_MASK    0x08000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_SHIFT   27
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_MASK    0x02000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_MASK    0x01000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_SHIFT   24
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: switch_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_MASK  0x00800000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: pcie1_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_SHIFT  7
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_MASK   0x00000020
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_SHIFT  5
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: rg_sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RG_SW_INIT_1_ENABLE - Router software init 0 mask
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_reserved0_MASK       0xffffc000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_reserved0_SHIFT      14
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_US_TOP  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_CAB_TOP 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_LEAP    19
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1   36
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE    44
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_WOD_RCVRA 48
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_WOD_RCVRB 49
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CMD_AFECA 60
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CMD_AFECB 61
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:06] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffffc0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           6
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [05:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000003f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_HOST_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 32
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         4
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_HOST_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 5
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xff800000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               23
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xffffffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             5
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UART_ROUTER_SEL_0 - UART Router select 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK    0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK    0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU    3
+
+/***************************************************************************
+ *UART_ROUTER_SEL_1 - UART Router select 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK   0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU   3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK   0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU   3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU    3
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x20404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x20404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xfffc0000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        18
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STB_POWER_CYCLE_CONTROL - Power Cycle Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_CONTROL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_reserved0_MASK   0xfffffffe
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_reserved0_SHIFT  1
+
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_CONTROL :: power_cycle_stb [00:00] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STB_POWER_CYCLE_DELAY - Power Cycle Delay
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_DELAY :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_reserved0_MASK     0xff000000
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_reserved0_SHIFT    24
+
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_DELAY :: prog_delay [23:00] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_MASK    0x00ffffff
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_DEFAULT 0x00001518
+
+/***************************************************************************
+ *GENERAL_CTRL_6 - General control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK            0xfffffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT           1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_7 - General control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_acb.h b/include/linux/brcmstb/3390a0/bchp_switch_acb.h
new file mode 100644
index 000000000000..f217347318cb
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_acb.h
@@ -0,0 +1,4448 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Jun 21 03:10:18 2014
+ *                 Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              ad87f49099acb161d3ffa5d223fcb978
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_ACB_H__
+#define BCHP_SWITCH_ACB_H__
+
+/***************************************************************************
+ *SWITCH_ACB
+ ***************************************************************************/
+#define BCHP_SWITCH_ACB_ACB_CONTROL              0x04e40600 /* ACB Control Register */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION 0x04e40604 /* ACB XON Threshold Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION 0x04e40608 /* ACB Queue 0 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION 0x04e4060c /* ACB Queue 1 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION 0x04e40610 /* ACB Queue 2 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION 0x04e40614 /* ACB Queue 3 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION 0x04e40618 /* ACB Queue 4 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION 0x04e4061c /* ACB Queue 5 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION 0x04e40620 /* ACB Queue 6 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION 0x04e40624 /* ACB Queue 7 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION 0x04e40628 /* ACB Queue 8 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION 0x04e4062c /* ACB Queue 9 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION 0x04e40630 /* ACB Queue 10 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION 0x04e40634 /* ACB Queue 11 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION 0x04e40638 /* ACB Queue 12 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION 0x04e4063c /* ACB Queue 13 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION 0x04e40640 /* ACB Queue 14 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION 0x04e40644 /* ACB Queue 15 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION 0x04e40648 /* ACB Queue 16 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION 0x04e4064c /* ACB Queue 17 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION 0x04e40650 /* ACB Queue 18 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION 0x04e40654 /* ACB Queue 19 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION 0x04e40658 /* ACB Queue 20 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION 0x04e4065c /* ACB Queue 21 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION 0x04e40660 /* ACB Queue 22 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION 0x04e40664 /* ACB Queue 23 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION 0x04e40668 /* ACB Queue 24 Configuration Register6 */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION 0x04e4066c /* ACB Queue 25 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION 0x04e40670 /* ACB Queue 26 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION 0x04e40674 /* ACB Queue 27 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION 0x04e40678 /* ACB Queue 28 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION 0x04e4067c /* ACB Queue 29 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION 0x04e40680 /* ACB Queue 30 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION 0x04e40684 /* ACB Queue 31 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION 0x04e40688 /* ACB Queue 32 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION 0x04e4068c /* ACB Queue 33 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION 0x04e40690 /* ACB Queue 34 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION 0x04e40694 /* ACB Queue 35 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION 0x04e40698 /* ACB Queue 36 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION 0x04e4069c /* ACB Queue 37 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION 0x04e406a0 /* ACB Queue 38 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION 0x04e406a4 /* ACB Queue 39 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION 0x04e406a8 /* ACB Queue 40 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION 0x04e406ac /* ACB Queue 41 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION 0x04e406b0 /* ACB Queue 42 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION 0x04e406b4 /* ACB Queue 43 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION 0x04e406b8 /* ACB Queue 44 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION 0x04e406bc /* ACB Queue 45 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION 0x04e406c0 /* ACB Queue 46 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION 0x04e406c4 /* ACB Queue 47 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION 0x04e406c8 /* ACB Queue 48 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION 0x04e406cc /* ACB Queue 49 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION 0x04e406d0 /* ACB Queue 50 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION 0x04e406d4 /* ACB Queue 51 Configuration Register6 */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION 0x04e406d8 /* ACB Queue 52 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION 0x04e406dc /* ACB Queue 53 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION 0x04e406e0 /* ACB Queue 54 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION 0x04e406e4 /* ACB Queue 55 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION 0x04e406e8 /* ACB Queue 56 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION 0x04e406ec /* ACB Queue 57 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION 0x04e406f0 /* ACB Queue 58 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION 0x04e406f4 /* ACB Queue 59 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION 0x04e406f8 /* ACB Queue 60 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION 0x04e406fc /* ACB Queue 61 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION 0x04e40700 /* ACB Queue 62 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION 0x04e40704 /* ACB Queue 63 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT 0x04e40708 /* ACB Queue 0 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT 0x04e4070c /* ACB Queue 1 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT 0x04e40710 /* ACB Queue 2 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT 0x04e40714 /* ACB Queue 3 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT 0x04e40718 /* ACB Queue 4 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT 0x04e4071c /* ACB Queue 5 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT 0x04e40720 /* ACB Queue 6 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT 0x04e40724 /* ACB Queue 7 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT 0x04e40728 /* ACB Queue 8 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT 0x04e4072c /* ACB Queue 9 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT 0x04e40730 /* ACB Queue 10 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT 0x04e40734 /* ACB Queue 11 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT 0x04e40738 /* ACB Queue 12 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT 0x04e4073c /* ACB Queue 13 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT 0x04e40740 /* ACB Queue 14 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT 0x04e40744 /* ACB Queue 15 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT 0x04e40748 /* ACB Queue 16 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT 0x04e4074c /* ACB Queue 17 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT 0x04e40750 /* ACB Queue 18 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT 0x04e40754 /* ACB Queue 19 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT 0x04e40758 /* ACB Queue 20 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT 0x04e4075c /* ACB Queue 21 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT 0x04e40760 /* ACB Queue 22 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT 0x04e40764 /* ACB Queue 23 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT 0x04e40768 /* ACB Queue 24 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT 0x04e4076c /* ACB Queue 25 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT 0x04e40770 /* ACB Queue 26 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT 0x04e40774 /* ACB Queue 27 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT 0x04e40778 /* ACB Queue 28 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT 0x04e4077c /* ACB Queue 29 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT 0x04e40780 /* ACB Queue 30 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT 0x04e40784 /* ACB Queue 31 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT 0x04e40788 /* ACB Queue 32 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT 0x04e4078c /* ACB Queue 33 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT 0x04e40790 /* ACB Queue 34 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT 0x04e40794 /* ACB Queue 35 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT 0x04e40798 /* ACB Queue 36 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT 0x04e4079c /* ACB Queue 37 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT 0x04e407a0 /* ACB Queue 38 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT 0x04e407a4 /* ACB Queue 39 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT 0x04e407a8 /* ACB Queue 40 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT 0x04e407ac /* ACB Queue 41 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT 0x04e407b0 /* ACB Queue 42 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT 0x04e407b4 /* ACB Queue 43 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT 0x04e407b8 /* ACB Queue 44 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT 0x04e407bc /* ACB Queue 45 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT 0x04e407c0 /* ACB Queue 46 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT 0x04e407c4 /* ACB Queue 47 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT 0x04e407c8 /* ACB Queue 48 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT 0x04e407cc /* ACB Queue 49 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT 0x04e407d0 /* ACB Queue 50 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT 0x04e407d4 /* ACB Queue 51 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT 0x04e407d8 /* ACB Queue 52 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT 0x04e407dc /* ACB Queue 53 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT 0x04e407e0 /* ACB Queue 54 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT 0x04e407e4 /* ACB Queue 55 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT 0x04e407e8 /* ACB Queue 56 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT 0x04e407ec /* ACB Queue 57 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT 0x04e407f0 /* ACB Queue 58 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT 0x04e407f4 /* ACB Queue 59 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT 0x04e407f8 /* ACB Queue 60 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT 0x04e407fc /* ACB Queue 61 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT 0x04e40800 /* ACB Queue 62 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT 0x04e40804 /* ACB Queue 63 Packets In Flight Register */
+
+/***************************************************************************
+ *ACB_CONTROL - ACB Control Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_CONTROL :: reserved0 [31:13] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_MASK                 0xffffe000
+#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_SHIFT                13
+
+/* SWITCH_ACB :: ACB_CONTROL :: eop_delay [12:05] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_MASK                 0x00001fe0
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_SHIFT                5
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_DEFAULT              0x00000032
+
+/* SWITCH_ACB :: ACB_CONTROL :: flush [04:02] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_MASK                     0x0000001c
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_SHIFT                    2
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_DEFAULT                  0x00000000
+
+/* SWITCH_ACB :: ACB_CONTROL :: acb_algorithm [01:01] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_MASK             0x00000002
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_SHIFT            1
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_DEFAULT          0x00000000
+
+/* SWITCH_ACB :: ACB_CONTROL :: acb_en [00:00] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_MASK                    0x00000001
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_SHIFT                   0
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ACB_XON_THRESHOLD_CONFIGURATION - ACB XON Threshold Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: reserved0 [31:22] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_MASK 0xffc00000
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_SHIFT 22
+
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: total_xon_hyst [21:11] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_MASK 0x003ff800
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_SHIFT 11
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: queue_xon_hyst [10:00] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_0_CONFIGURATION - ACB Queue 0 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_0_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_acb_queue_0_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_1_CONFIGURATION - ACB Queue 1 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_1_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_acb_queue_1_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_2_CONFIGURATION - ACB Queue 2 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_2_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_acb_queue_2_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_3_CONFIGURATION - ACB Queue 3 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_3_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_acb_queue_3_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_4_CONFIGURATION - ACB Queue 4 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_4_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_acb_queue_4_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_5_CONFIGURATION - ACB Queue 5 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_5_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_acb_queue_5_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_6_CONFIGURATION - ACB Queue 6 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_6_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_acb_queue_6_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_7_CONFIGURATION - ACB Queue 7 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_7_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_acb_queue_7_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_8_CONFIGURATION - ACB Queue 8 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_8_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_acb_queue_8_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_9_CONFIGURATION - ACB Queue 9 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_9_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_acb_queue_9_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_10_CONFIGURATION - ACB Queue 10 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_10_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_acb_queue_10_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_11_CONFIGURATION - ACB Queue 11 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_11_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_acb_queue_11_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_12_CONFIGURATION - ACB Queue 12 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_12_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_acb_queue_12_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_13_CONFIGURATION - ACB Queue 13 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_13_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_acb_queue_13_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_14_CONFIGURATION - ACB Queue 14 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_14_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_acb_queue_14_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_15_CONFIGURATION - ACB Queue 15 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_15_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_acb_queue_15_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_16_CONFIGURATION - ACB Queue 16 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_16_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_acb_queue_16_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_17_CONFIGURATION - ACB Queue 17 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_17_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_acb_queue_17_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_18_CONFIGURATION - ACB Queue 18 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_18_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_acb_queue_18_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_19_CONFIGURATION - ACB Queue 19 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_19_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_acb_queue_19_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_20_CONFIGURATION - ACB Queue 20 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_20_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_acb_queue_20_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_21_CONFIGURATION - ACB Queue 21 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_21_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_acb_queue_21_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_22_CONFIGURATION - ACB Queue 22 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_22_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_acb_queue_22_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_23_CONFIGURATION - ACB Queue 23 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_23_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_acb_queue_23_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_24_CONFIGURATION - ACB Queue 24 Configuration Register6
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_24_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_acb_queue_24_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_25_CONFIGURATION - ACB Queue 25 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_25_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_acb_queue_25_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_26_CONFIGURATION - ACB Queue 26 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_26_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_acb_queue_26_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_27_CONFIGURATION - ACB Queue 27 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_27_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_acb_queue_27_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_28_CONFIGURATION - ACB Queue 28 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_28_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_acb_queue_28_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_29_CONFIGURATION - ACB Queue 29 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_29_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_acb_queue_29_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_30_CONFIGURATION - ACB Queue 30 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_30_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_acb_queue_30_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_31_CONFIGURATION - ACB Queue 31 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_31_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_acb_queue_31_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_32_CONFIGURATION - ACB Queue 32 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_32_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_acb_queue_32_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_33_CONFIGURATION - ACB Queue 33 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_33_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_acb_queue_33_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_34_CONFIGURATION - ACB Queue 34 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_34_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_acb_queue_34_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_35_CONFIGURATION - ACB Queue 35 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_35_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_acb_queue_35_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_36_CONFIGURATION - ACB Queue 36 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_36_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_acb_queue_36_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_37_CONFIGURATION - ACB Queue 37 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_37_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_acb_queue_37_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_38_CONFIGURATION - ACB Queue 38 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_38_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_acb_queue_38_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_39_CONFIGURATION - ACB Queue 39 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_39_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_acb_queue_39_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_40_CONFIGURATION - ACB Queue 40 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_40_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_acb_queue_40_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_41_CONFIGURATION - ACB Queue 41 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_41_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_acb_queue_41_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_42_CONFIGURATION - ACB Queue 42 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_42_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_acb_queue_42_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_43_CONFIGURATION - ACB Queue 43 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_43_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_acb_queue_43_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_44_CONFIGURATION - ACB Queue 44 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_44_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_acb_queue_44_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_45_CONFIGURATION - ACB Queue 45 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_45_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_acb_queue_45_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_46_CONFIGURATION - ACB Queue 46 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_46_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_acb_queue_46_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_47_CONFIGURATION - ACB Queue 47 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_47_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_acb_queue_47_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_48_CONFIGURATION - ACB Queue 48 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_48_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_acb_queue_48_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_49_CONFIGURATION - ACB Queue 49 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_49_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_acb_queue_49_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_50_CONFIGURATION - ACB Queue 50 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_50_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_acb_queue_50_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_51_CONFIGURATION - ACB Queue 51 Configuration Register6
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_51_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_acb_queue_51_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_52_CONFIGURATION - ACB Queue 52 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_52_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_acb_queue_52_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_53_CONFIGURATION - ACB Queue 53 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_53_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_acb_queue_53_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_54_CONFIGURATION - ACB Queue 54 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_54_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_acb_queue_54_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_55_CONFIGURATION - ACB Queue 55 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_55_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_acb_queue_55_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_56_CONFIGURATION - ACB Queue 56 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_56_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_acb_queue_56_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_57_CONFIGURATION - ACB Queue 57 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_57_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_acb_queue_57_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_58_CONFIGURATION - ACB Queue 58 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_58_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_acb_queue_58_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_59_CONFIGURATION - ACB Queue 59 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_59_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_acb_queue_59_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_60_CONFIGURATION - ACB Queue 60 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_60_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_acb_queue_60_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_61_CONFIGURATION - ACB Queue 61 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_61_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_acb_queue_61_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_62_CONFIGURATION - ACB Queue 62 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_62_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_acb_queue_62_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_63_CONFIGURATION - ACB Queue 63 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_63_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_acb_queue_63_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_0_PACKETS_IN_FLIGHT - ACB Queue 0 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_0_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: input_is_acb_queue_0_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_1_PACKETS_IN_FLIGHT - ACB Queue 1 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_1_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: input_is_acb_queue_1_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_2_PACKETS_IN_FLIGHT - ACB Queue 2 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_2_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: input_is_acb_queue_2_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_3_PACKETS_IN_FLIGHT - ACB Queue 3 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_3_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: input_is_acb_queue_3_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_4_PACKETS_IN_FLIGHT - ACB Queue 4 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_4_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: input_is_acb_queue_4_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_5_PACKETS_IN_FLIGHT - ACB Queue 5 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_5_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: input_is_acb_queue_5_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_6_PACKETS_IN_FLIGHT - ACB Queue 6 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_6_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: input_is_acb_queue_6_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_7_PACKETS_IN_FLIGHT - ACB Queue 7 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_7_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: input_is_acb_queue_7_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_8_PACKETS_IN_FLIGHT - ACB Queue 8 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_8_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: input_is_acb_queue_8_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_9_PACKETS_IN_FLIGHT - ACB Queue 9 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_9_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: input_is_acb_queue_9_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_10_PACKETS_IN_FLIGHT - ACB Queue 10 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_10_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: input_is_acb_queue_10_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_11_PACKETS_IN_FLIGHT - ACB Queue 11 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_11_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: input_is_acb_queue_11_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_12_PACKETS_IN_FLIGHT - ACB Queue 12 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_13_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: input_is_acb_queue_13_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_13_PACKETS_IN_FLIGHT - ACB Queue 13 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_13_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: input_is_acb_queue_13_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_14_PACKETS_IN_FLIGHT - ACB Queue 14 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_14_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: input_is_acb_queue_14_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_15_PACKETS_IN_FLIGHT - ACB Queue 15 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_15_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: input_is_acb_queue_15_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_16_PACKETS_IN_FLIGHT - ACB Queue 16 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_16_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: input_is_acb_queue_16_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_17_PACKETS_IN_FLIGHT - ACB Queue 17 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_17_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: input_is_acb_queue_17_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_18_PACKETS_IN_FLIGHT - ACB Queue 18 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_18_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: input_is_acb_queue_18_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_19_PACKETS_IN_FLIGHT - ACB Queue 19 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_19_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: input_is_acb_queue_19_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_20_PACKETS_IN_FLIGHT - ACB Queue 20 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_20_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: input_is_acb_queue_20_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_21_PACKETS_IN_FLIGHT - ACB Queue 21 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_21_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: input_is_acb_queue_21_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_22_PACKETS_IN_FLIGHT - ACB Queue 22 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_22_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: input_is_acb_queue_22_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_23_PACKETS_IN_FLIGHT - ACB Queue 23 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_23_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: input_is_acb_queue_23_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_24_PACKETS_IN_FLIGHT - ACB Queue 24 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_24_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: input_is_acb_queue_24_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_25_PACKETS_IN_FLIGHT - ACB Queue 25 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_25_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: input_is_acb_queue_25_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_26_PACKETS_IN_FLIGHT - ACB Queue 26 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_26_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: input_is_acb_queue_26_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_27_PACKETS_IN_FLIGHT - ACB Queue 27 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_27_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: input_is_acb_queue_27_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_28_PACKETS_IN_FLIGHT - ACB Queue 28 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_28_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: input_is_acb_queue_28_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_29_PACKETS_IN_FLIGHT - ACB Queue 29 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_29_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: input_is_acb_queue_29_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_30_PACKETS_IN_FLIGHT - ACB Queue 30 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_30_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: input_is_acb_queue_30_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_31_PACKETS_IN_FLIGHT - ACB Queue 31 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_31_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: input_is_acb_queue_31_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_32_PACKETS_IN_FLIGHT - ACB Queue 32 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_32_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: input_is_acb_queue_32_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_33_PACKETS_IN_FLIGHT - ACB Queue 33 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_33_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: input_is_acb_queue_33_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_34_PACKETS_IN_FLIGHT - ACB Queue 34 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_34_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: input_is_acb_queue_34_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_35_PACKETS_IN_FLIGHT - ACB Queue 35 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_35_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: input_is_acb_queue_35_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_36_PACKETS_IN_FLIGHT - ACB Queue 36 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_36_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: input_is_acb_queue_36_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_37_PACKETS_IN_FLIGHT - ACB Queue 37 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_37_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: input_is_acb_queue_37_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_38_PACKETS_IN_FLIGHT - ACB Queue 38 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_38_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: input_is_acb_queue_38_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_39_PACKETS_IN_FLIGHT - ACB Queue 39 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_39_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: input_is_acb_queue_39_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_40_PACKETS_IN_FLIGHT - ACB Queue 40 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_40_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: input_is_acb_queue_40_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_41_PACKETS_IN_FLIGHT - ACB Queue 41 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_41_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: input_is_acb_queue_41_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_42_PACKETS_IN_FLIGHT - ACB Queue 42 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_42_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: input_is_acb_queue_42_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_43_PACKETS_IN_FLIGHT - ACB Queue 43 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_43_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: input_is_acb_queue_43_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_44_PACKETS_IN_FLIGHT - ACB Queue 44 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_44_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: input_is_acb_queue_44_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_45_PACKETS_IN_FLIGHT - ACB Queue 45 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_45_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: input_is_acb_queue_45_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_46_PACKETS_IN_FLIGHT - ACB Queue 46 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_46_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: input_is_acb_queue_46_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_47_PACKETS_IN_FLIGHT - ACB Queue 47 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_47_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: input_is_acb_queue_47_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_48_PACKETS_IN_FLIGHT - ACB Queue 48 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_48_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: input_is_acb_queue_48_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_49_PACKETS_IN_FLIGHT - ACB Queue 49 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_49_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: input_is_acb_queue_49_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_50_PACKETS_IN_FLIGHT - ACB Queue 50 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_50_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: input_is_acb_queue_50_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_51_PACKETS_IN_FLIGHT - ACB Queue 51 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_51_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: input_is_acb_queue_51_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_52_PACKETS_IN_FLIGHT - ACB Queue 52 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_52_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: input_is_acb_queue_52_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_53_PACKETS_IN_FLIGHT - ACB Queue 53 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_53_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: input_is_acb_queue_53_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_54_PACKETS_IN_FLIGHT - ACB Queue 54 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_54_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: input_is_acb_queue_54_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_55_PACKETS_IN_FLIGHT - ACB Queue 55 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_55_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: input_is_acb_queue_55_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_56_PACKETS_IN_FLIGHT - ACB Queue 56 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_56_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: input_is_acb_queue_56_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_57_PACKETS_IN_FLIGHT - ACB Queue 57 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_57_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: input_is_acb_queue_57_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_58_PACKETS_IN_FLIGHT - ACB Queue 58 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_58_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: input_is_acb_queue_58_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_59_PACKETS_IN_FLIGHT - ACB Queue 59 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_59_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: input_is_acb_queue_59_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_60_PACKETS_IN_FLIGHT - ACB Queue 60 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_60_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: input_is_acb_queue_60_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_61_PACKETS_IN_FLIGHT - ACB Queue 61 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_61_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: input_is_acb_queue_61_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_62_PACKETS_IN_FLIGHT - ACB Queue 62 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_62_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: input_is_acb_queue_62_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_63_PACKETS_IN_FLIGHT - ACB Queue 63 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_63_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: input_is_acb_queue_63_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_ACB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_core.h b/include/linux/brcmstb/3390a0/bchp_switch_core.h
new file mode 100644
index 000000000000..9e902c2e1181
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_core.h
@@ -0,0 +1,32026 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Jun 21 03:10:22 2014
+ *                 Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              ad87f49099acb161d3ffa5d223fcb978
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_CORE_H__
+#define BCHP_SWITCH_CORE_H__
+
+/***************************************************************************
+ *SWITCH_CORE
+ ***************************************************************************/
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0           0x04e00000 /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1           0x04e00004 /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2           0x04e00008 /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3           0x04e0000c /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4           0x04e00010 /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5           0x04e00014 /* Port N 10/100/1000 Control Register */
+#define BCHP_SWITCH_CORE_P7_CTL                  0x04e0001c /* Port 7 Control Register */
+#define BCHP_SWITCH_CORE_IMP_CTL                 0x04e00020 /* IMP Port Control Register */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL           0x04e00028 /* RX Global Control register(Not2Release) */
+#define BCHP_SWITCH_CORE_SWMODE                  0x04e0002c /* Switch Mode Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP        0x04e00038 /* IMP Port States Override Register */
+#define BCHP_SWITCH_CORE_DEBUG_REG               0x04e00078 /* Debug Control Register(Not2Release) */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG           0x04e0007c /* Removed Pins Debug Register(Not2Release) */
+#define BCHP_SWITCH_CORE_NEW_CTRL                0x04e00084 /* New Control Register */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL             0x04e00088 /* Switch Control Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL           0x04e00090 /* Protected Port Select Register */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL            0x04e00098 /* WAN Port select Register */
+#define BCHP_SWITCH_CORE_PAUSE_CAP               0x04e000a0 /* PAUSE Capability Register */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL          0x04e000bc /* Reserved Multicast Register */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE          0x04e000c4 /* TxQ Flush Mode Control Register(Not2Release) */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP            0x04e000c8 /* Unicast Lookup Failed Forward Map Register */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP            0x04e000d0 /* Multicast Lookup Failed Forward Map Register */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP        0x04e000d8 /* IPMC Forward Map Register */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS           0x04e000e0 /* Pause pass Through for RX Register */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS           0x04e000e8 /* Pause pass Through for TX Register */
+#define BCHP_SWITCH_CORE_DIS_LEARN               0x04e000f0 /* Disable Learning Register */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL             0x04e000f8 /* Software Learning Control */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1          0x04e00100 /* Low Power Expansion I Register */
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE        0x04e00150 /* Spare Register (Not2Release) */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0 0x04e00160 /* Port N GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1 0x04e00164 /* Port N GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2 0x04e00168 /* Port N GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3 0x04e0016c /* Port N GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4 0x04e00170 /* Port N GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5         0x04e00174 /* Port 5 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7         0x04e0017c /* Port 7 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL          0x04e001e4 /* Watch Dog Control Register */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1          0x04e001e8 /* Watch Dog Report 1 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2          0x04e001f0 /* Watch Dog Report 2 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3          0x04e001f8 /* Watch Dog Report 3 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL          0x04e00200 /* Pause Frame Detection Control Register */
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR           0x04e00204 /* PAUSE Frame DA Address */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL           0x04e00220 /* Fast Ageing Control Register */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT           0x04e00224 /* Fast Ageing Port Control Register */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID            0x04e00228 /* Fast Ageing VID Control Register */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL          0x04e00378 /* LOW Power Control Register */
+#define BCHP_SWITCH_CORE_TCAM_CTRL               0x04e003a0 /* TCAM Control Register */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS         0x04e003a8 /* TCAM Checksum Status Register */
+#define BCHP_SWITCH_CORE_LNKSTS                  0x04e00400 /* Link Status Summary Register */
+#define BCHP_SWITCH_CORE_LNKSTSCHG               0x04e00408 /* Link Status Change Register */
+#define BCHP_SWITCH_CORE_SPDSTS                  0x04e00410 /* Port Speed Summary Register */
+#define BCHP_SWITCH_CORE_DUPSTS                  0x04e00420 /* Duplex status Summary Register */
+#define BCHP_SWITCH_CORE_PAUSESTS                0x04e00428 /* Pause Status Summary Register */
+#define BCHP_SWITCH_CORE_SRCADRCHG               0x04e00438 /* Source Address Change Register */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_0         0x04e00440 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_1         0x04e00458 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_2         0x04e00470 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_3         0x04e00488 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_4         0x04e004a0 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_5         0x04e004b8 /* Port N Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT7               0x04e004e8 /* Port 7 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_MII_PORT            0x04e00500 /* Port 8 Last Source Address */
+#define BCHP_SWITCH_CORE_BIST_STS0               0x04e00518 /* BIST Status Register 0 */
+#define BCHP_SWITCH_CORE_BIST_STS1               0x04e00530 /* BIST Status Register 1 */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0             0x04e00540 /* PBPTRFIFO Status Register 0(Not2Release) */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1             0x04e00558 /* PBPTRFIFO Status Register 1(Not2Release) */
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS        0x04e005c0 /* Strap Pin Status Register */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE 0x04e00600 /* Direct Input Control Value Register */
+#define BCHP_SWITCH_CORE_RESET_STATUS            0x04e00640 /* Reset Status Register */
+#define BCHP_SWITCH_CORE_ENG_DET_STS             0x04e00648 /* PHY Energy Detect Status Register */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG         0x04e0064c /* PHY Energy Detect Status Change Register */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0        0x04e00680 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1        0x04e00690 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_GMNGCFG                 0x04e00800 /* Global Management Configuration Register */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID             0x04e00804 /* IMP/IMP0 Port ID Register */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID             0x04e00808 /* IMP1 Port ID Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL           0x04e0080c /* BRCM Header Control Register */
+#define BCHP_SWITCH_CORE_SPTAGT                  0x04e00818 /* Aging Time Control Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2          0x04e00828 /* BRCM Header Control 2 Register */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL          0x04e00830 /* IPG Shrink Control Register */
+#define BCHP_SWITCH_CORE_MIRCAPCTL               0x04e00840 /* Mirror Capture Control Register */
+#define BCHP_SWITCH_CORE_IGMIRCTL                0x04e00848 /* Ingress Mirror Control Register */
+#define BCHP_SWITCH_CORE_IGMIRDIV                0x04e00850 /* Ingress Mirror Divider Register */
+#define BCHP_SWITCH_CORE_IGMIRMAC                0x04e00858 /* Ingress Mirror Mac Address Register */
+#define BCHP_SWITCH_CORE_EGMIRCTL                0x04e00870 /* Egress Mirror Control Register */
+#define BCHP_SWITCH_CORE_EGMIRDIV                0x04e00878 /* Egress Mirror Divider Register */
+#define BCHP_SWITCH_CORE_EGMIRMAC                0x04e00880 /* Egress Mirror MAC Address Register */
+#define BCHP_SWITCH_CORE_MODEL_ID                0x04e008c0 /* Model ID Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CHIP_REVID              0x04e00900 /* Chip Version ID Register */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL            0x04e00940 /* High Level Protocol Control Register */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN          0x04e00950 /* Reset MIB Counter Enable Register */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA        0x04e00960 /* IPG Shrink 2G Workaround Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS         0x04e00980 /* Broadcom Header RX Disable Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS         0x04e00988 /* Broadcom Header TX Disable Register */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0      0x04e009c0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1      0x04e009d0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_INT_STS                 0x04e00c00 /* External Host Raw Interrupt Status Register */
+#define BCHP_SWITCH_CORE_INT_EN                  0x04e00c20 /* External Host Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER         0x04e00c40 /* IMP Port(port 8) Sleep Timer Register */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER       0x04e00c48 /* Port 7 Sleep Timer Register */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER         0x04e00c50 /* WAN Port Sleep Timer Register */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS          0x04e00c60 /* Port Sleep Status Register */
+#define BCHP_SWITCH_CORE_INT_TRIGGER             0x04e00c80 /* Interrupt Trigger Register */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN         0x04e00c90 /* Link Status Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN          0x04e00ca0 /* Energy Detection Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN      0x04e00ca8 /* LPI Status Change Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER    0x04e00d00 /* CPU Resource Arbitor Register */
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE          0x04e00d40 /* CPU Data Share Register */
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1        0x04e00d60 /* CPU Data Share 1 Register */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS     0x04e00d80 /* Memory ECC Double-Error-Detection Interrupt Status (Not2Release) */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN      0x04e00d88 /* Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS    0x04e00d90 /* Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS    0x04e00d98 /* Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS    0x04e00da0 /* Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL           0x04e00dc0 /* Probe Bus Control Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL         0x04e00dd0 /* MDC Extend Clock Control Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN  0x04e00e00 /* PPPoE Session Packet Parsing Enable Register */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0     0x04e00e40 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1     0x04e00e50 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_GARLCFG                 0x04e01000 /* Global ARL Configuration Register */
+#define BCHP_SWITCH_CORE_BPDU_MCADDR             0x04e01010 /* BPDU Multicast Address Register */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL          0x04e01038 /* Multiport Control Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0         0x04e01040 /* Multiport Address 0 Register (Default for TS) */
+#define BCHP_SWITCH_CORE_MPORTVEC0               0x04e01060 /* Multiport Vector 0 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1         0x04e01080 /* Multiport Address 1 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC1               0x04e010a0 /* Multiport Vector 1 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2         0x04e010c0 /* Multiport Address 2 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC2               0x04e010e0 /* Multiport Vector 2 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3         0x04e01100 /* Multiport Address 3 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC3               0x04e01120 /* Multiport Vector 3 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4         0x04e01140 /* Multiport Address 4 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC4               0x04e01160 /* Multiport Vector 4 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5         0x04e01180 /* Multiport Address 5 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC5               0x04e011a0 /* Multiport Vector 5 Register */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR       0x04e011c0 /* ARL Bin Full Counter Register */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD        0x04e011d0 /* ARL Biin Full Forward Enable Register */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0       0x04e01200 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1       0x04e01210 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL              0x04e01400 /* ARL Read/Write Control Register */
+#define BCHP_SWITCH_CORE_ARLA_MAC                0x04e01408 /* MAC Address Index Register */
+#define BCHP_SWITCH_CORE_ARLA_VID                0x04e01420 /* VID Index Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0      0x04e01440 /* ARL MAC/VID Entry 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0         0x04e01460 /* ARL FWD Entry 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1      0x04e01480 /* ARL MAC/VID Entry 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1         0x04e014a0 /* ARL FWD Entry 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2      0x04e014c0 /* ARL MAC/VID Entry 2 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2         0x04e014e0 /* ARL FWD Entry 2 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3      0x04e01500 /* ARL MAC/VID Entry 3 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3         0x04e01520 /* ARL FWD Entry 3 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL           0x04e01540 /* ARL Search Control Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR           0x04e01544 /* ARL Search Address Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID 0x04e01580 /* ARL Search MAC/VID Result 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0        0x04e015a0 /* ARL Search Result 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID 0x04e015c0 /* ARL Search MAC/VID Result 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1        0x04e015e0 /* ARL Search Result 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL        0x04e01600 /* VTBL Read/Write/Clear Control Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR          0x04e01604 /* VTBL Address Index Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY         0x04e0160c /* VTBL Entry Register */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0      0x04e01640 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1      0x04e01650 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MEM_CTRL                0x04e02000 /* Memory Debug Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_ADDR                0x04e02004 /* Memory Debug Address RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0      0x04e02020 /* Memory Debug Data 0_0 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1      0x04e02040 /* Memory Debug Data 0_1 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0      0x04e02048 /* Memory Debug Data 1_0 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1      0x04e02068 /* Memory Debug Data 1_1 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR            0x04e02080 /* Frame Memory Address RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0           0x04e020c0 /* Frame Memory Data 1st RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1           0x04e020e0 /* Frame Memory Data 2st RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2           0x04e02100 /* Frame Memory Data 3st RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3           0x04e02120 /* Frame Memory Data 4th RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0           0x04e02140 /* Buffer Tag Memory Register 0Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1           0x04e02160 /* Buffer Tag Memory Register 1Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR            0x04e02180 /* Buffer Control Memory Address RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA            0x04e02188 /* Buffer Control Memory Data RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL     0x04e021c0 /* PRS_FIFO Debug Control Register(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA     0x04e021c4 /* PRS_FIFO Debug Data Register(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0          0x04e022a0 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1          0x04e022b0 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL           0x04e022c0 /* Memory Misc Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0          0x04e022d0 /* Memory Test Control 0 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1          0x04e022e0 /* Memory Test Control 1 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2          0x04e022f0 /* Memory Test Control 2 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3          0x04e02300 /* Memory Test Control 3 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4          0x04e02310 /* Memory Test Control 4 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5          0x04e02320 /* Memory Test Control 5 RegisterNot2Release */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL        0x04e02380 /* Memory PSM_VDD Pin Control registerNot2Release */
+#define BCHP_SWITCH_CORE_PORT0_DEBUG             0x04e02400 /* PORT0 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT1_DEBUG             0x04e02440 /* PORT1 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT2_DEBUG             0x04e02480 /* PORT2 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT3_DEBUG             0x04e024c0 /* PORT3 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT4_DEBUG             0x04e02500 /* PORT4 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT5_DEBUG             0x04e02540 /* PORT5 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT6_DEBUG             0x04e02580 /* PORT6 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT7_DEBUG             0x04e025c0 /* PORT7 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT8_DEBUG             0x04e02600 /* PORT8 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL            0x04e02800 /* Flowcon Diagnosis Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE            0x04e02808 /* Flow Control Mode Selection RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT            0x04e0280c /* Flow Control Port Selection RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN         0x04e02810 /* OOB Pause Signal Enable Register (Release2Customer)Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX          0x04e02840 /* MAX Quantum Pause Time RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN          0x04e02848 /* MIN Quantum Pause Time RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD    0x04e02850 /* Quantum Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD 0x04e02858 /* Quantum Pause Update Period RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT      0x04e02860 /* Default Quantum Pause Time RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL      0x04e02868 /* Multicast Drop Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL      0x04e02870 /* Pause/Drop Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF    0x04e02878 /* TXQ Pause Off Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF            0x04e02880 /* RX-Based Run-Off RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD           0x04e02888 /* RX-Based Reserved RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD          0x04e02890 /* RX-Based Hysteresis RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR           0x04e02898 /* RX-Based Maximum Buffer Remap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG       0x04e028a0 /* Flow Control Spare Zero RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG        0x04e028a8 /* Flow Control Spare One RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0       0x04e028c0 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1       0x04e028c8 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2       0x04e028d0 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3       0x04e028d8 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4       0x04e028e0 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5       0x04e028e8 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6       0x04e028f0 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7       0x04e028f8 /* Monitored TXQ N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0      0x04e02900 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1      0x04e02908 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2      0x04e02910 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3      0x04e02918 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4      0x04e02920 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5      0x04e02928 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6      0x04e02930 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7      0x04e02938 /* Peak TXQ N Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED      0x04e02940 /* Peak Total Used Count RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED           0x04e02948 /* Total Used Count RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT          0x04e02950 /* Peak RX Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP         0x04e02958 /* PHY Link Information RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP         0x04e02960 /* Giga Speed Information RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0 0x04e02980 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1 0x04e02988 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2 0x04e02990 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3 0x04e02998 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4 0x04e029a0 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5 0x04e029a8 /* Port N Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7      0x04e029b8 /* Port 7 Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8      0x04e029c0 /* Port 8 Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS            0x04e029e0 /* Pause History RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS 0x04e029e8 /* TX Quantum Pause History RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS         0x04e029f0 /* RX Based Pause History RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS        0x04e029f8 /* RX Buffer Error History RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0 0x04e02a00 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1 0x04e02a08 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2 0x04e02a10 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3 0x04e02a18 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4 0x04e02a20 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5 0x04e02a28 /* Port N TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7  0x04e02a38 /* Port 7 TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8  0x04e02a40 /* Port 8 TXQ Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0 0x04e02a68 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1 0x04e02a70 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2 0x04e02a78 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3 0x04e02a80 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4 0x04e02a88 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5 0x04e02a90 /* Port N Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7 0x04e02aa0 /* Port 7 Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8 0x04e02aa8 /* Port 8 Total Congested PortMap RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0 0x04e02c00 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1 0x04e02c08 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2 0x04e02c10 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3 0x04e02c18 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4 0x04e02c20 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5 0x04e02c28 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6 0x04e02c30 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7 0x04e02c38 /* LAN Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0 0x04e02c40 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1 0x04e02c48 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2 0x04e02c50 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3 0x04e02c58 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4 0x04e02c60 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5 0x04e02c68 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6 0x04e02c70 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7 0x04e02c78 /* LAN Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0 0x04e02c80 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1 0x04e02c88 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2 0x04e02c90 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3 0x04e02c98 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4 0x04e02ca0 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5 0x04e02ca8 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6 0x04e02cb0 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7 0x04e02cb8 /* LAN Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0 0x04e02cc0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1 0x04e02cc8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2 0x04e02cd0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3 0x04e02cd8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4 0x04e02ce0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5 0x04e02ce8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6 0x04e02cf0 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7 0x04e02cf8 /* LAN Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0 0x04e02d00 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1 0x04e02d08 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2 0x04e02d10 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3 0x04e02d18 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4 0x04e02d20 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5 0x04e02d28 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6 0x04e02d30 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7 0x04e02d38 /* LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 0x04e02d40 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 0x04e02d48 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 0x04e02d50 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 0x04e02d58 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 0x04e02d60 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 0x04e02d68 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 0x04e02d70 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 0x04e02d78 /* LAN Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0 0x04e02d80 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1 0x04e02d88 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2 0x04e02d90 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3 0x04e02d98 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4 0x04e02da0 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5 0x04e02da8 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6 0x04e02db0 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7 0x04e02db8 /* LAN Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX            0x04e03000 /* P0 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX            0x04e03010 /* P1 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX            0x04e03020 /* P2 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX            0x04e03030 /* P3 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX            0x04e03040 /* P4 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX            0x04e03050 /* P5 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX            0x04e03060 /* P6 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P7_DEBUG_MUX            0x04e03070 /* P7 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX           0x04e03080 /* IMP DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0         0x04e03090 /* CFP DEBUG BUS 0Not2Release */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1         0x04e030a0 /* CFP DEBUG BUS 1Not2Release */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0            0x04e030b0 /* WRED DEBUG 0Not2Release */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1            0x04e030c0 /* WRED DEBUG 1Not2Release */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0        0x04e030d0 /* TOP MISC DEBUG 0Not2Release */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1        0x04e030e0 /* TOP MISC DEBUG 1Not2Release */
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON          0x04e030f0 /* DIAGREG BUFCONNot2Release */
+#define BCHP_SWITCH_CORE_TESTBUS_P1588           0x04e03100 /* TESTBUS P1588Not2Release */
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS       0x04e03110 /* FLOWCON DEBUG BUSNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0 0x04e03400 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1 0x04e03408 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2 0x04e03410 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3 0x04e03418 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4 0x04e03420 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5 0x04e03428 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6 0x04e03430 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7 0x04e03438 /* IMP0 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0 0x04e03440 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1 0x04e03448 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2 0x04e03450 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3 0x04e03458 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4 0x04e03460 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5 0x04e03468 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6 0x04e03470 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7 0x04e03478 /* IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 0x04e03480 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 0x04e03488 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 0x04e03490 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 0x04e03498 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 0x04e034a0 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 0x04e034a8 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 0x04e034b0 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 0x04e034b8 /* IMP0 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0 0x04e034c0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1 0x04e034c8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2 0x04e034d0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3 0x04e034d8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4 0x04e034e0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5 0x04e034e8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6 0x04e034f0 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7 0x04e034f8 /* IMP0 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0 0x04e03500 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1 0x04e03508 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2 0x04e03510 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3 0x04e03518 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4 0x04e03520 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5 0x04e03528 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6 0x04e03530 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7 0x04e03538 /* IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 0x04e03540 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 0x04e03548 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 0x04e03550 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 0x04e03558 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 0x04e03560 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 0x04e03568 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 0x04e03570 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 0x04e03578 /* IMP0 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0 0x04e03580 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1 0x04e03588 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2 0x04e03590 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3 0x04e03598 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4 0x04e035a0 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5 0x04e035a8 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6 0x04e035b0 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7 0x04e035b8 /* IMP0 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0      0x04e035c0 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1      0x04e035c8 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 0x04e03800 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 0x04e03808 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 0x04e03810 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 0x04e03818 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 0x04e03820 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 0x04e03828 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 0x04e03830 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 0x04e03838 /* WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 0x04e03840 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 0x04e03848 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 0x04e03850 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 0x04e03858 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 0x04e03860 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 0x04e03868 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 0x04e03870 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 0x04e03878 /* WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 0x04e03880 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 0x04e03888 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 0x04e03890 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 0x04e03898 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 0x04e038a0 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 0x04e038a8 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 0x04e038b0 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 0x04e038b8 /* WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 0x04e038c0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 0x04e038c8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 0x04e038d0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 0x04e038d8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 0x04e038e0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 0x04e038e8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 0x04e038f0 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 0x04e038f8 /* WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 0x04e03900 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 0x04e03908 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 0x04e03910 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 0x04e03918 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 0x04e03920 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 0x04e03928 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 0x04e03930 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 0x04e03938 /* WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 0x04e03940 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 0x04e03948 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 0x04e03950 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 0x04e03958 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 0x04e03960 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 0x04e03968 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 0x04e03970 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 0x04e03978 /* WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 0x04e03980 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 0x04e03988 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 0x04e03990 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 0x04e03998 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 0x04e039a0 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 0x04e039a8 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 0x04e039b0 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 0x04e039b8 /* WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0  0x04e039c0 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1  0x04e039c8 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL            0x04e03c00 /* Temperature Monitor Control Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU           0x04e03c08 /* Temperature Monitor Result Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU      0x04e03c10 /* Peak Temperature Monitor Result Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL            0x04e03c18 /* Temperature Monitor Calibration Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL       0x04e03c20 /* Temperature Monitor Special Control Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TxOctets_P0             0x04e08000 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P0           0x04e08020 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0             0x04e08030 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0      0x04e08040 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0      0x04e08050 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0        0x04e08060 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P0         0x04e08070 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0    0x04e08080 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0  0x04e08090 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0   0x04e080a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P0      0x04e080b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0 0x04e080c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0        0x04e080d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P0          0x04e080e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0             0x04e080f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0             0x04e08100 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0             0x04e08110 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0             0x04e08120 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0             0x04e08130 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P0             0x04e08140 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0      0x04e08160 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P0          0x04e08170 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0       0x04e08180 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0  0x04e08190 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0 0x04e081a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0 0x04e081b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0 0x04e081c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0 0x04e081d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0       0x04e081e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P0            0x04e081f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0    0x04e08200 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0          0x04e08210 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0         0x04e08220 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P0           0x04e08240 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0        0x04e08250 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0      0x04e08260 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0      0x04e08270 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P0          0x04e08280 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P0          0x04e08290 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0           0x04e082a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P0           0x04e082b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0      0x04e082c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0     0x04e082d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0        0x04e082e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0     0x04e082f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P0            0x04e08300 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0             0x04e08320 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0             0x04e08330 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0       0x04e08340 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0  0x04e08350 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0 0x04e08360 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0 0x04e08370 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0 0x04e08380 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0 0x04e08390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P1             0x04e08400 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P1           0x04e08420 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1             0x04e08430 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1      0x04e08440 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1      0x04e08450 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1        0x04e08460 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P1         0x04e08470 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1    0x04e08480 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1  0x04e08490 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1   0x04e084a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P1      0x04e084b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1 0x04e084c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1        0x04e084d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P1          0x04e084e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1             0x04e084f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1             0x04e08500 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1             0x04e08510 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1             0x04e08520 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1             0x04e08530 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P1             0x04e08540 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1      0x04e08560 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P1          0x04e08570 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1       0x04e08580 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1  0x04e08590 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1 0x04e085a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1 0x04e085b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1 0x04e085c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1 0x04e085d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1       0x04e085e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P1            0x04e085f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1    0x04e08600 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1          0x04e08610 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1         0x04e08620 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P1           0x04e08640 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1        0x04e08650 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1      0x04e08660 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1      0x04e08670 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P1          0x04e08680 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P1          0x04e08690 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1           0x04e086a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P1           0x04e086b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1      0x04e086c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1     0x04e086d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1        0x04e086e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1     0x04e086f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P1            0x04e08700 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1             0x04e08720 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1             0x04e08730 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1       0x04e08740 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1  0x04e08750 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1 0x04e08760 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1 0x04e08770 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1 0x04e08780 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1 0x04e08790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P2             0x04e08800 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P2           0x04e08820 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2             0x04e08830 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2      0x04e08840 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2      0x04e08850 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2        0x04e08860 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P2         0x04e08870 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2    0x04e08880 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2  0x04e08890 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2   0x04e088a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P2      0x04e088b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2 0x04e088c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2        0x04e088d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P2          0x04e088e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2             0x04e088f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2             0x04e08900 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2             0x04e08910 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2             0x04e08920 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2             0x04e08930 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P2             0x04e08940 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2      0x04e08960 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P2          0x04e08970 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2       0x04e08980 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2  0x04e08990 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2 0x04e089a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2 0x04e089b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2 0x04e089c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2 0x04e089d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2       0x04e089e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P2            0x04e089f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2    0x04e08a00 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2          0x04e08a10 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2         0x04e08a20 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P2           0x04e08a40 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2        0x04e08a50 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2      0x04e08a60 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2      0x04e08a70 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P2          0x04e08a80 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P2          0x04e08a90 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2           0x04e08aa0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P2           0x04e08ab0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2      0x04e08ac0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2     0x04e08ad0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2        0x04e08ae0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2     0x04e08af0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P2            0x04e08b00 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2             0x04e08b20 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2             0x04e08b30 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2       0x04e08b40 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2  0x04e08b50 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2 0x04e08b60 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2 0x04e08b70 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2 0x04e08b80 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2 0x04e08b90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P3             0x04e08c00 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P3           0x04e08c20 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3             0x04e08c30 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3      0x04e08c40 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3      0x04e08c50 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3        0x04e08c60 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P3         0x04e08c70 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3    0x04e08c80 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3  0x04e08c90 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3   0x04e08ca0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P3      0x04e08cb0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3 0x04e08cc0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3        0x04e08cd0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P3          0x04e08ce0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3             0x04e08cf0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3             0x04e08d00 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3             0x04e08d10 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3             0x04e08d20 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3             0x04e08d30 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P3             0x04e08d40 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3      0x04e08d60 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P3          0x04e08d70 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3       0x04e08d80 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3  0x04e08d90 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3 0x04e08da0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3 0x04e08db0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3 0x04e08dc0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3 0x04e08dd0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3       0x04e08de0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P3            0x04e08df0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3    0x04e08e00 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3          0x04e08e10 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3         0x04e08e20 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P3           0x04e08e40 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3        0x04e08e50 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3      0x04e08e60 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3      0x04e08e70 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P3          0x04e08e80 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P3          0x04e08e90 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3           0x04e08ea0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P3           0x04e08eb0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3      0x04e08ec0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3     0x04e08ed0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3        0x04e08ee0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3     0x04e08ef0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P3            0x04e08f00 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3             0x04e08f20 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3             0x04e08f30 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3       0x04e08f40 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3  0x04e08f50 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3 0x04e08f60 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3 0x04e08f70 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3 0x04e08f80 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3 0x04e08f90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P4             0x04e09000 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P4           0x04e09020 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4             0x04e09030 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4      0x04e09040 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4      0x04e09050 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4        0x04e09060 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P4         0x04e09070 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4    0x04e09080 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4  0x04e09090 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4   0x04e090a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P4      0x04e090b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4 0x04e090c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4        0x04e090d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P4          0x04e090e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4             0x04e090f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4             0x04e09100 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4             0x04e09110 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4             0x04e09120 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4             0x04e09130 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P4             0x04e09140 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4      0x04e09160 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P4          0x04e09170 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4       0x04e09180 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4  0x04e09190 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4 0x04e091a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4 0x04e091b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4 0x04e091c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4 0x04e091d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4       0x04e091e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P4            0x04e091f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4    0x04e09200 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4          0x04e09210 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4         0x04e09220 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P4           0x04e09240 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4        0x04e09250 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4      0x04e09260 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4      0x04e09270 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P4          0x04e09280 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P4          0x04e09290 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4           0x04e092a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P4           0x04e092b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4      0x04e092c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4     0x04e092d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4        0x04e092e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4     0x04e092f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P4            0x04e09300 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4             0x04e09320 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4             0x04e09330 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4       0x04e09340 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4  0x04e09350 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4 0x04e09360 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4 0x04e09370 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4 0x04e09380 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4 0x04e09390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P5             0x04e09400 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P5           0x04e09420 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5             0x04e09430 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5      0x04e09440 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5      0x04e09450 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5        0x04e09460 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P5         0x04e09470 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5    0x04e09480 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5  0x04e09490 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5   0x04e094a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P5      0x04e094b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5 0x04e094c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5        0x04e094d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P5          0x04e094e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5             0x04e094f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5             0x04e09500 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5             0x04e09510 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5             0x04e09520 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5             0x04e09530 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P5             0x04e09540 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5      0x04e09560 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P5          0x04e09570 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5       0x04e09580 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5  0x04e09590 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5 0x04e095a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5 0x04e095b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5 0x04e095c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5 0x04e095d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5       0x04e095e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P5            0x04e095f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5    0x04e09600 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5          0x04e09610 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5         0x04e09620 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P5           0x04e09640 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5        0x04e09650 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5      0x04e09660 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5      0x04e09670 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P5          0x04e09680 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P5          0x04e09690 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5           0x04e096a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P5           0x04e096b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5      0x04e096c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5     0x04e096d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5        0x04e096e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5     0x04e096f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P5            0x04e09700 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5             0x04e09720 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5             0x04e09730 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5       0x04e09740 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5  0x04e09750 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5 0x04e09760 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5 0x04e09770 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5 0x04e09780 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5 0x04e09790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P7             0x04e09c00 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P7           0x04e09c20 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7             0x04e09c30 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7      0x04e09c40 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7      0x04e09c50 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7        0x04e09c60 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P7         0x04e09c70 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7    0x04e09c80 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7  0x04e09c90 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7   0x04e09ca0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P7      0x04e09cb0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7 0x04e09cc0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7        0x04e09cd0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P7          0x04e09ce0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7             0x04e09cf0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7             0x04e09d00 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7             0x04e09d10 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7             0x04e09d20 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7             0x04e09d30 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P7             0x04e09d40 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7      0x04e09d60 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P7          0x04e09d70 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7       0x04e09d80 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7  0x04e09d90 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7 0x04e09da0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7 0x04e09db0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7 0x04e09dc0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7 0x04e09dd0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7       0x04e09de0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P7            0x04e09df0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7    0x04e09e00 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7          0x04e09e10 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7         0x04e09e20 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P7           0x04e09e40 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7        0x04e09e50 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7      0x04e09e60 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7      0x04e09e70 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P7          0x04e09e80 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P7          0x04e09e90 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7           0x04e09ea0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P7           0x04e09eb0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7      0x04e09ec0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7     0x04e09ed0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7        0x04e09ee0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7     0x04e09ef0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P7            0x04e09f00 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7             0x04e09f20 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7             0x04e09f30 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7       0x04e09f40 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7  0x04e09f50 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7 0x04e09f60 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7 0x04e09f70 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7 0x04e09f80 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7 0x04e09f90 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_IMP            0x04e0a000 /* Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP          0x04e0a020 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP            0x04e0a030 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP     0x04e0a040 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP     0x04e0a050 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP       0x04e0a060 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_IMP        0x04e0a070 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP   0x04e0a080 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP 0x04e0a090 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP  0x04e0a0a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP     0x04e0a0b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP 0x04e0a0c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP       0x04e0a0d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP         0x04e0a0e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP            0x04e0a0f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP            0x04e0a100 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP            0x04e0a110 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP            0x04e0a120 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP            0x04e0a130 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_IMP            0x04e0a140 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP     0x04e0a160 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP         0x04e0a170 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP      0x04e0a180 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP 0x04e0a190 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP 0x04e0a1a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP 0x04e0a1b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP 0x04e0a1c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP 0x04e0a1d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP      0x04e0a1e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_IMP           0x04e0a1f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP   0x04e0a200 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP         0x04e0a210 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP        0x04e0a220 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP          0x04e0a240 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP       0x04e0a250 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP     0x04e0a260 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP     0x04e0a270 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP         0x04e0a280 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_IMP         0x04e0a290 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP          0x04e0a2a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP          0x04e0a2b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP     0x04e0a2c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP    0x04e0a2d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP       0x04e0a2e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP    0x04e0a2f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_IMP           0x04e0a300 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP            0x04e0a320 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP            0x04e0a330 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP      0x04e0a340 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP 0x04e0a350 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP 0x04e0a360 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP 0x04e0a370 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP 0x04e0a380 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP 0x04e0a390 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL         0x04e0c000 /* QOS Global Control Register */
+#define BCHP_SWITCH_CORE_QOS_1P_EN               0x04e0c010 /* QoS 802.1P Enable Register */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV         0x04e0c018 /* QOS DiffServ Enable Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0   0x04e0c040 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1   0x04e0c050 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2   0x04e0c060 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3   0x04e0c070 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4   0x04e0c080 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5   0x04e0c090 /* Port N PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0          0x04e0c0a0 /* Port 7 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0         0x04e0c0b0 /* Port 8 (IMP) PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0          0x04e0c0c0 /* DiffServ Priority Map 0 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1          0x04e0c0d8 /* DiffServ Priority Map 1 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2          0x04e0c0f0 /* DiffServ Priority Map 2 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3          0x04e0c108 /* DiffServ Priority Map 3 Register */
+#define BCHP_SWITCH_CORE_PID2TC                  0x04e0c120 /* Port ID to TC Map Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0     0x04e0c140 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1     0x04e0c148 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2     0x04e0c150 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3     0x04e0c158 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4     0x04e0c160 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5     0x04e0c168 /* Port N TC Select Table Register */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE         0x04e0c178 /* Port 7 TC Select Table Register */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE        0x04e0c180 /* Port 8 TC Select Table Register */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP             0x04e0c190 /* CPU to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0    0x04e0c1c0 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1    0x04e0c1d0 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2    0x04e0c1e0 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3    0x04e0c1f0 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4    0x04e0c200 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5    0x04e0c210 /* Port N TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP           0x04e0c230 /* Port 7 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP          0x04e0c240 /* Port 8 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0          0x04e0c2a0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1          0x04e0c2b0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0   0x04e0c2c0 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1   0x04e0c2d0 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2   0x04e0c2e0 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3   0x04e0c2f0 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4   0x04e0c300 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5   0x04e0c310 /* Port N PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1          0x04e0c320 /* Port 7 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1         0x04e0c330 /* Port 8 (IMP) PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0    0x04e0c400 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1    0x04e0c408 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2    0x04e0c410 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3    0x04e0c418 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4    0x04e0c420 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5    0x04e0c428 /* PORT N VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7        0x04e0c438 /* PORT 7 VLAN Control Register */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP       0x04e0c440 /* PORT 8 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0         0x04e0c480 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1         0x04e0c490 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL           0x04e0c800 /* MAC Trunk Control Register */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL            0x04e0c808 /* IMP0 Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0    0x04e0c840 /* Trunk N Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1    0x04e0c848 /* Trunk N Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0        0x04e0c880 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1        0x04e0c890 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0              0x04e0d000 /* 802.1Q VLAN Control 0 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1              0x04e0d004 /* 802.1Q VLAN Control 1 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2              0x04e0d008 /* 802.1Q VLAN Control 2 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3              0x04e0d00c /* 802.1Q VLAN Control 3 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4              0x04e0d014 /* 802.1Q VLAN Control 4 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5              0x04e0d018 /* 802.1Q VLAN Control 5 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6              0x04e0d01c /* 802.1Q VLAN Control 6 Registers */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL 0x04e0d028 /* VLAN Multiport Address Control Register */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0   0x04e0d040 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1   0x04e0d048 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2   0x04e0d050 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3   0x04e0d058 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4   0x04e0d060 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5   0x04e0d068 /* Port N 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7       0x04e0d078 /* Port 7 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP      0x04e0d080 /* Port 8 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DTAG_TPID               0x04e0d0c0 /* Double Tagging TPID Registers */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP         0x04e0d0c8 /* ISP Port Selection Portmap Registers */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS  0x04e0d100 /* Egress VID Remarking Table Access Register */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA 0x04e0d110 /* Egress VID Remarking Table Data Register */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN        0x04e0d140 /* Join All VLAN Enable Register */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL       0x04e0d148 /* Port IVL or SVL Control Register */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0     0x04e0d180 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1     0x04e0d190 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_DOS_CTRL                0x04e0d800 /* DoS Control RegisterRegister */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ      0x04e0d810 /* Minimum TCP Header Size Register */
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG     0x04e0d820 /* Maximum ICMPv4 Size Register */
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG     0x04e0d830 /* Maximum ICMPv6 Size Register */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG         0x04e0d840 /* DoS Disable Learn Register */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0          0x04e0d880 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1          0x04e0d890 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK         0x04e10004 /* Jumbo Frame Port Mask Registers */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE      0x04e10014 /* Jumbo MIB Good Frame Max Size Registers */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0   0x04e10040 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1   0x04e10050 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON            0x04e10400 /* Common Ingress rate Control Configuration Registers */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD    0x04e10410 /* Ingress Rate Control Virtual Zero Threshold Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD           0x04e10418 /* Ingress Rate Control Alarm Threshold Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0 0x04e10440 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1 0x04e10450 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2 0x04e10460 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3 0x04e10470 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4 0x04e10480 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5 0x04e10490 /* Port N Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7      0x04e104b0 /* Port 7 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP     0x04e104c0 /* Port 8 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0 0x04e104d0 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1 0x04e104d8 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2 0x04e104e0 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3 0x04e104e8 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4 0x04e104f0 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5 0x04e104f8 /* Port N Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7    0x04e10508 /* Port 7 Receive Rate Control 1 Register */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP   0x04e1050c /* Port 8 Receive Rate Control 1 Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0 0x04e10540 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1 0x04e10550 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2 0x04e10560 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3 0x04e10570 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4 0x04e10580 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5 0x04e10590 /* Port N Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7   0x04e105b0 /* Port 7 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP  0x04e105c0 /* Port 8 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0  0x04e10740 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1  0x04e10750 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON             0x04e10800 /* EAP Global Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL     0x04e10804 /* EAP Multiport Address Control Register */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0          0x04e10808 /* EAP Destination IP Registers */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1          0x04e10828 /* EAP Destination IP Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0     0x04e10880 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1     0x04e108a0 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2     0x04e108c0 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3     0x04e108e0 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4     0x04e10900 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5     0x04e10920 /* Port N EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7         0x04e10960 /* Port 7 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP        0x04e10980 /* IMP EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0    0x04e109c0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1    0x04e109d0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MST_CON                 0x04e10c00 /* MST Control Registers */
+#define BCHP_SWITCH_CORE_MST_AGE                 0x04e10c08 /* MST Ageing Control Register */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0          0x04e10c40 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1          0x04e10c50 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2          0x04e10c60 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3          0x04e10c70 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4          0x04e10c80 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5          0x04e10c90 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6          0x04e10ca0 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7          0x04e10cb0 /* MST Table N Enable Registers */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL 0x04e10d40 /* STP Multiport Address Bypass Control Register */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0    0x04e10d80 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1    0x04e10d90 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE         0x04e11400 /* SA Limit Enable Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST         0x04e11408 /* SA Learned Counters Reset Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST   0x04e11410 /* SA Over Limit Counters Reset Register */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL      0x04e11440 /* Total SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0 0x04e11448 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1 0x04e11450 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2 0x04e11458 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3 0x04e11460 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4 0x04e11468 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5 0x04e11470 /* Port N SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL     0x04e11480 /* Port 7 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL     0x04e11488 /* Port 8 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR       0x04e114c0 /* Total SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0 0x04e114c8 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1 0x04e114d0 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2 0x04e114d8 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3 0x04e114e0 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4 0x04e114e8 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5 0x04e114f0 /* Port N SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR      0x04e11500 /* Port 7 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR      0x04e11508 /* Port 8 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0 0x04e11540 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1 0x04e11550 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2 0x04e11560 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3 0x04e11570 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4 0x04e11580 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5 0x04e11590 /* Port N SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR 0x04e115b0 /* Port 7 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR 0x04e115c0 /* Port 8 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT 0x04e115d0 /* SA Over Limit Actions Config Register */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0    0x04e11600 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1    0x04e11610 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0   0x04e11800 /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1   0x04e11804 /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2   0x04e11808 /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3   0x04e1180c /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4   0x04e11810 /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5   0x04e11814 /* Port N, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL          0x04e1181c /* Port 7, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL         0x04e11820 /* Port 8, QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0    0x04e11840 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1    0x04e11860 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2    0x04e11880 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3    0x04e118a0 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4    0x04e118c0 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5    0x04e118e0 /* Port N, QOS Weight Register */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT           0x04e11920 /* Port 7, QOS Weight Register */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT          0x04e11940 /* Port 8, QOS Weight Register */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0  0x04e11980 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1  0x04e11988 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2  0x04e11990 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3  0x04e11998 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4  0x04e119a0 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5  0x04e119a8 /* Port N, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY         0x04e119c0 /* Port 7, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY         0x04e119c8 /* Port 8, WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0    0x04e11a00 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1    0x04e11a10 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 0x04e11c00 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 0x04e11c10 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 0x04e11c20 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 0x04e11c30 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 0x04e11c40 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 0x04e11c50 /* Port N, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x04e11c70 /* Port 7, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x04e11c80 /* Port 8, Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 0x04e11cc0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 0x04e11cd0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 0x04e11ce0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 0x04e11cf0 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 0x04e11d00 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 0x04e11d10 /* Port N, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x04e11d30 /* Port 7, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x04e11d40 /* Port 8, Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0 0x04e11d80 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1 0x04e11d90 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2 0x04e11da0 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3 0x04e11db0 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4 0x04e11dc0 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5 0x04e11dd0 /* Port N, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS      0x04e11df0 /* Port 7, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS     0x04e11e00 /* Port 8, PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 0x04e11e40 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 0x04e11e50 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 0x04e11e60 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 0x04e11e70 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 0x04e11e80 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 0x04e11e90 /* Port N, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x04e11eb0 /* Port 7, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x04e11ec0 /* Port 8, Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0 0x04e11ee0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1 0x04e11ef0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 0x04e11f00 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 0x04e11f10 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 0x04e11f20 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 0x04e11f30 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 0x04e11f40 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 0x04e11f50 /* Port N, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x04e11f70 /* Port 7, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x04e11f80 /* Port 8, Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE 0x04e11f90 /* Port Shaper AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE      0x04e11f98 /* Port Shaper Enable Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT 0x04e11fa0 /* Port Shaper Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING    0x04e11fa8 /* Port Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_IFG_BYTES               0x04e11fb8 /* IFG Correction Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0 0x04e12000 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1 0x04e12010 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2 0x04e12020 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3 0x04e12030 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4 0x04e12040 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5 0x04e12050 /* Port N, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH   0x04e12070 /* Port 7, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH  0x04e12080 /* Port 8, Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0 0x04e120c0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1 0x04e120d0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2 0x04e120e0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3 0x04e120f0 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4 0x04e12100 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5 0x04e12110 /* Port N, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL   0x04e12130 /* Port 7, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL  0x04e12140 /* Port 8, Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0 0x04e12180 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1 0x04e12190 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2 0x04e121a0 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3 0x04e121b0 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4 0x04e121c0 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5 0x04e121d0 /* Port N, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS    0x04e121f0 /* Port 7, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS   0x04e12200 /* Port 8, Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 0x04e12240 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 0x04e12250 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 0x04e12260 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 0x04e12270 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 0x04e12280 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 0x04e12290 /* Port N, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH 0x04e122b0 /* Port 7, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH 0x04e122c0 /* Port 8, Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 0x04e122e0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 0x04e122f0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 0x04e12300 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 0x04e12310 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 0x04e12320 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 0x04e12330 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 0x04e12340 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 0x04e12350 /* Port N, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL 0x04e12370 /* Port 7, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL 0x04e12380 /* Port 8, Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE 0x04e12390 /* Queue 0 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE    0x04e12398 /* Queue 0 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT 0x04e123a0 /* Queue 0 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING  0x04e123a8 /* Queue 0 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0 0x04e12400 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1 0x04e12410 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2 0x04e12420 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3 0x04e12430 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4 0x04e12440 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5 0x04e12450 /* Port N, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH   0x04e12470 /* Port 7, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH  0x04e12480 /* Port 8, Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0 0x04e124c0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1 0x04e124d0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2 0x04e124e0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3 0x04e124f0 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4 0x04e12500 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5 0x04e12510 /* Port N, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL   0x04e12530 /* Port 7, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL  0x04e12540 /* Port 8, Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0 0x04e12580 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1 0x04e12590 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2 0x04e125a0 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3 0x04e125b0 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4 0x04e125c0 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5 0x04e125d0 /* Port N, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS    0x04e125f0 /* Port 7, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS   0x04e12600 /* Port 8, Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 0x04e12640 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 0x04e12650 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 0x04e12660 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 0x04e12670 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 0x04e12680 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 0x04e12690 /* Port N, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH 0x04e126b0 /* Port 7, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH 0x04e126c0 /* Port 8, Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 0x04e126e0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 0x04e126f0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 0x04e12700 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 0x04e12710 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 0x04e12720 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 0x04e12730 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 0x04e12740 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 0x04e12750 /* Port N, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL 0x04e12770 /* Port 7, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL 0x04e12780 /* Port 8, Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE 0x04e12790 /* Queue 1 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE    0x04e12798 /* Queue 1 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT 0x04e127a0 /* Queue 1 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING  0x04e127a8 /* Queue 1 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0 0x04e12800 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1 0x04e12810 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2 0x04e12820 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3 0x04e12830 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4 0x04e12840 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5 0x04e12850 /* Port N, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH   0x04e12870 /* Port 7, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH  0x04e12880 /* Port 8, Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0 0x04e128c0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1 0x04e128d0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2 0x04e128e0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3 0x04e128f0 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4 0x04e12900 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5 0x04e12910 /* Port N, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL   0x04e12930 /* Port 7, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL  0x04e12940 /* Port 8, Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0 0x04e12980 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1 0x04e12990 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2 0x04e129a0 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3 0x04e129b0 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4 0x04e129c0 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5 0x04e129d0 /* Port N, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS    0x04e129f0 /* Port 7, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS   0x04e12a00 /* Port 8, Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 0x04e12a40 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 0x04e12a50 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 0x04e12a60 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 0x04e12a70 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 0x04e12a80 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 0x04e12a90 /* Port N, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH 0x04e12ab0 /* Port 7, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH 0x04e12ac0 /* Port 8, Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 0x04e12ae0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 0x04e12af0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 0x04e12b00 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 0x04e12b10 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 0x04e12b20 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 0x04e12b30 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 0x04e12b40 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 0x04e12b50 /* Port N, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL 0x04e12b70 /* Port 7, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL 0x04e12b80 /* Port 8, Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE 0x04e12b90 /* Queue 2 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE    0x04e12b98 /* Queue 2 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT 0x04e12ba0 /* Queue 2 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING  0x04e12ba8 /* Queue 2 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0 0x04e12c00 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1 0x04e12c10 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2 0x04e12c20 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3 0x04e12c30 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4 0x04e12c40 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5 0x04e12c50 /* Port N, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH   0x04e12c70 /* Port 7, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH  0x04e12c80 /* Port 8, Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0 0x04e12cc0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1 0x04e12cd0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2 0x04e12ce0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3 0x04e12cf0 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4 0x04e12d00 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5 0x04e12d10 /* Port N, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL   0x04e12d30 /* Port 7, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL  0x04e12d40 /* Port 8, Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0 0x04e12d80 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1 0x04e12d90 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2 0x04e12da0 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3 0x04e12db0 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4 0x04e12dc0 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5 0x04e12dd0 /* Port N, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS    0x04e12df0 /* Port 7, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS   0x04e12e00 /* Port 8, Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 0x04e12e40 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 0x04e12e50 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 0x04e12e60 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 0x04e12e70 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 0x04e12e80 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 0x04e12e90 /* Port N, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH 0x04e12eb0 /* Port 7, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH 0x04e12ec0 /* Port 8, Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 0x04e12ee0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 0x04e12ef0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 0x04e12f00 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 0x04e12f10 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 0x04e12f20 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 0x04e12f30 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 0x04e12f40 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 0x04e12f50 /* Port N, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL 0x04e12f70 /* Port 7, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL 0x04e12f80 /* Port 8, Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE 0x04e12f90 /* Queue 3 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE    0x04e12f98 /* Queue 3 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT 0x04e12fa0 /* Queue 3 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING  0x04e12fa8 /* Queue 3 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0 0x04e13000 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1 0x04e13010 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2 0x04e13020 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3 0x04e13030 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4 0x04e13040 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5 0x04e13050 /* Port N, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH   0x04e13070 /* Port 7, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH  0x04e13080 /* Port 8, Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0 0x04e130c0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1 0x04e130d0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2 0x04e130e0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3 0x04e130f0 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4 0x04e13100 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5 0x04e13110 /* Port N, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL   0x04e13130 /* Port 7, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL  0x04e13140 /* Port 8, Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0 0x04e13180 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1 0x04e13190 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2 0x04e131a0 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3 0x04e131b0 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4 0x04e131c0 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5 0x04e131d0 /* Port N, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS    0x04e131f0 /* Port 7, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS   0x04e13200 /* Port 8, Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 0x04e13240 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 0x04e13250 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 0x04e13260 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 0x04e13270 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 0x04e13280 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 0x04e13290 /* Port N, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH 0x04e132b0 /* Port 7, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH 0x04e132c0 /* Port 8, Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 0x04e132e0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 0x04e132f0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 0x04e13300 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 0x04e13310 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 0x04e13320 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 0x04e13330 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 0x04e13340 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 0x04e13350 /* Port N, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL 0x04e13370 /* Port 7, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL 0x04e13380 /* Port 8, Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE 0x04e13390 /* Queue 4 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE    0x04e13398 /* Queue 4 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT 0x04e133a0 /* Queue 4 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING  0x04e133a8 /* Queue 4 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0 0x04e13400 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1 0x04e13410 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2 0x04e13420 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3 0x04e13430 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4 0x04e13440 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5 0x04e13450 /* Port N, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH   0x04e13470 /* Port 7, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH  0x04e13480 /* Port 8, Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0 0x04e134c0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1 0x04e134d0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2 0x04e134e0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3 0x04e134f0 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4 0x04e13500 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5 0x04e13510 /* Port N, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL   0x04e13530 /* Port 7, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL  0x04e13540 /* Port 8, Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0 0x04e13580 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1 0x04e13590 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2 0x04e135a0 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3 0x04e135b0 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4 0x04e135c0 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5 0x04e135d0 /* Port N, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS    0x04e135f0 /* Port 7, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS   0x04e13600 /* Port 8, Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 0x04e13640 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 0x04e13650 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 0x04e13660 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 0x04e13670 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 0x04e13680 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 0x04e13690 /* Port N, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH 0x04e136b0 /* Port 7, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH 0x04e136c0 /* Port 8, Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 0x04e136e0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 0x04e136f0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 0x04e13700 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 0x04e13710 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 0x04e13720 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 0x04e13730 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 0x04e13740 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 0x04e13750 /* Port N, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL 0x04e13770 /* Port 7, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL 0x04e13780 /* Port 8, Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE 0x04e13790 /* Queue 5 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE    0x04e13798 /* Queue 5 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT 0x04e137a0 /* Queue 5 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING  0x04e137a8 /* Queue 5 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0 0x04e13800 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1 0x04e13810 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2 0x04e13820 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3 0x04e13830 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4 0x04e13840 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5 0x04e13850 /* Port N, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH   0x04e13870 /* Port 7, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH  0x04e13880 /* Port 8, Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0 0x04e138c0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1 0x04e138d0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2 0x04e138e0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3 0x04e138f0 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4 0x04e13900 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5 0x04e13910 /* Port N, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL   0x04e13930 /* Port 7, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL  0x04e13940 /* Port 8, Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0 0x04e13980 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1 0x04e13990 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2 0x04e139a0 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3 0x04e139b0 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4 0x04e139c0 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5 0x04e139d0 /* Port N, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS    0x04e139f0 /* Port 7, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS   0x04e13a00 /* Port 8, Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 0x04e13a40 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 0x04e13a50 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 0x04e13a60 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 0x04e13a70 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 0x04e13a80 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 0x04e13a90 /* Port N, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH 0x04e13ab0 /* Port 7, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH 0x04e13ac0 /* Port 8, Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 0x04e13ae0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 0x04e13af0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 0x04e13b00 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 0x04e13b10 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 0x04e13b20 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 0x04e13b30 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 0x04e13b40 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 0x04e13b50 /* Port N, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL 0x04e13b70 /* Port 7, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL 0x04e13b80 /* Port 8, Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE 0x04e13b90 /* Queue 6 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE    0x04e13b98 /* Queue 6 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT 0x04e13ba0 /* Queue 6 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING  0x04e13ba8 /* Queue 6 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0 0x04e13c00 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1 0x04e13c10 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2 0x04e13c20 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3 0x04e13c30 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4 0x04e13c40 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5 0x04e13c50 /* Port N, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH   0x04e13c70 /* Port 7, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH  0x04e13c80 /* Port 8, Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0 0x04e13cc0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1 0x04e13cd0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2 0x04e13ce0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3 0x04e13cf0 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4 0x04e13d00 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5 0x04e13d10 /* Port N, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL   0x04e13d30 /* Port 7, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL  0x04e13d40 /* Port 8, Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0 0x04e13d80 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1 0x04e13d90 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2 0x04e13da0 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3 0x04e13db0 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4 0x04e13dc0 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5 0x04e13dd0 /* Port N, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS    0x04e13df0 /* Port 7, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS   0x04e13e00 /* Port 8, Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 0x04e13e40 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 0x04e13e50 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 0x04e13e60 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 0x04e13e70 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 0x04e13e80 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 0x04e13e90 /* Port N, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH 0x04e13eb0 /* Port 7, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH 0x04e13ec0 /* Port 8, Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 0x04e13ee0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 0x04e13ef0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 0x04e13f00 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 0x04e13f10 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 0x04e13f20 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 0x04e13f30 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 0x04e13f40 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 0x04e13f50 /* Port N, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL 0x04e13f70 /* Port 7, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL 0x04e13f80 /* Port 8, Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE 0x04e13f90 /* Queue 7 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE    0x04e13f98 /* Queue 7 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT 0x04e13fa0 /* Queue 7 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING  0x04e13fa8 /* Queue 7 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL        0x04e1c000 /* MIB Snapshot Control Register */
+#define BCHP_SWITCH_CORE_S_TxOctets              0x04e1c400 /* Tx Octets */
+#define BCHP_SWITCH_CORE_S_TxDropPkts            0x04e1c420 /* Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0              0x04e1c430 /* Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts       0x04e1c440 /* Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts       0x04e1c450 /* Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts         0x04e1c460 /* Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxCollisions          0x04e1c470 /* Tx Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxSingleCollision     0x04e1c480 /* Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision   0x04e1c490 /* Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit    0x04e1c4a0 /* Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_S_TxLateCollision       0x04e1c4b0 /* Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision  0x04e1c4c0 /* Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc         0x04e1c4d0 /* Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_S_TxPausePkts           0x04e1c4e0 /* Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1              0x04e1c4f0 /* Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2              0x04e1c500 /* Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3              0x04e1c510 /* Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4              0x04e1c520 /* Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5              0x04e1c530 /* Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxOctets              0x04e1c540 /* Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts       0x04e1c560 /* Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPausePkts           0x04e1c570 /* Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets        0x04e1c580 /* Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets   0x04e1c590 /* Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets  0x04e1c5a0 /* Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets  0x04e1c5b0 /* Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets 0x04e1c5c0 /* Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets 0x04e1c5d0 /* Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxOversizePkts        0x04e1c5e0 /* Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxJabbers             0x04e1c5f0 /* Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors     0x04e1c600 /* Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_S_RxFCSErrors           0x04e1c610 /* Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_S_RxGoodOctets          0x04e1c620 /* Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_S_RxDropPkts            0x04e1c640 /* Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts         0x04e1c650 /* Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts       0x04e1c660 /* Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts       0x04e1c670 /* Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxSAChanges           0x04e1c680 /* Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_S_RxFragments           0x04e1c690 /* Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_S_RxJumboPkt            0x04e1c6a0 /* Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxSymblErr            0x04e1c6b0 /* Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_S_InRangeErrCount       0x04e1c6c0 /* InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount      0x04e1c6d0 /* OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT         0x04e1c6e0 /* EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION      0x04e1c6f0 /* EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_S_RxDiscard             0x04e1c700 /* Rx Discard Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6              0x04e1c720 /* Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7              0x04e1c730 /* Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets        0x04e1c740 /* Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets   0x04e1c750 /* Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets  0x04e1c760 /* Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets  0x04e1c770 /* Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets 0x04e1c780 /* Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets 0x04e1c790 /* Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_LPDET_CFG               0x04e1c800 /* Loop Detection Configuration RegistersNot2Release */
+#define BCHP_SWITCH_CORE_DF_TIMER                0x04e1c808 /* Discovery Frame Timer RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LED_PORTMAP             0x04e1c80c /* LED Waming Portmap RegistersNot2Release */
+#define BCHP_SWITCH_CORE_MODULE_ID0              0x04e1c814 /* Module ID 0 RegistersNot2Release */
+#define BCHP_SWITCH_CORE_MODULE_ID1              0x04e1c82c /* Module ID 1 RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LPDET_SA                0x04e1c844 /* Loop Detect Frame SA RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0        0x04e1c880 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1        0x04e1c890 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_BPM_CTRL                0x04e1cc00 /* BPM Power Switching Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL        0x04e1cc04 /* BPM Power Switching SW Override RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG        0x04e1cc08 /* PSM_VDD Timing Parameter Configuration RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG         0x04e1cc10 /* PSM_VDD Switching Threshold Configuration RegisterNot2Release */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL      0x04e1cc20 /* BUFCON Row Status Valid Mask SW Override Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_STS                 0x04e1cc30 /* BPM Status RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL        0x04e1cc40 /* BPM PDA Switching SW Override Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG         0x04e1cc48 /* BPM PDA Switching Timeout Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG      0x04e1cc50 /* BPM PDA Switching Setup Time RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG       0x04e1cc58 /* BPM PDA Switching Hold Time RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0    0x04e1cc60 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1    0x04e1cc68 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2    0x04e1cc70 /* Packet Buffer Block N Valid Buffer Count RegisterNot2Release */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG            0x04e1cc78 /* Recycling Check Pulse Period Counter RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL     0x04e1cc80 /* PBB Powerdown Monitor Control RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0 0x04e1cca0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1 0x04e1ccc0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2 0x04e1cce0 /* PBB Powerdown Time Monitor N RegisterNot2Release */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0          0x04e1cd80 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1          0x04e1cd90 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0             0x04e24400 /* Traffic Remarking Control 0 Register */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1             0x04e24410 /* Traffic Remarking Control 1 Register */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2             0x04e24420 /* Traffic Remarking Control 2 Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0 0x04e24440 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1 0x04e24460 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2 0x04e24480 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3 0x04e244a0 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4 0x04e244c0 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5 0x04e244e0 /* Port N, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP 0x04e24520 /* Port 7, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP 0x04e24540 /* Port 8, Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 0x04e24580 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 0x04e245a0 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 0x04e245c0 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 0x04e245e0 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 0x04e24600 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 0x04e24620 /* Port N, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP 0x04e24660 /* Port 7, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP 0x04e24680 /* Port 8, Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0        0x04e246c0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1        0x04e246d0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL             0x04e24800 /* EEE Enable Control Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT          0x04e24808 /* EEE Low Power Assert Status Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE        0x04e24810 /* EEE Low Power Indicate Status Registers */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL      0x04e24818 /* EEE Receiving Idle Symbols Status Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE 0x04e24820 /* EEE LPI Symbol Transmit Disable Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER      0x04e24830 /* EEE Pipeline Delay Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0 0x04e24840 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1 0x04e24850 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2 0x04e24860 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3 0x04e24870 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4 0x04e24880 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5 0x04e24890 /* EEE Port N Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7    0x04e248b0 /* EEE Port 7 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP   0x04e248c0 /* EEE Port 8(IMP) Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0 0x04e248d0 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1 0x04e248e0 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2 0x04e248f0 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3 0x04e24900 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4 0x04e24910 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5 0x04e24920 /* EEE Port N Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7    0x04e24940 /* EEE Port 7 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP   0x04e24950 /* EEE Port 8(IMP) Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0 0x04e24960 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1 0x04e24970 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2 0x04e24980 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3 0x04e24990 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4 0x04e249a0 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5 0x04e249b0 /* EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7   0x04e249d0 /* EEE Port 7 Minimum Low-Power Duration Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP  0x04e249e0 /* EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0 0x04e249f0 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1 0x04e24a00 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2 0x04e24a10 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3 0x04e24a20 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4 0x04e24a30 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5 0x04e24a40 /* EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7   0x04e24a60 /* EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP  0x04e24a70 /* EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0 0x04e24a80 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1 0x04e24a88 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2 0x04e24a90 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3 0x04e24a98 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4 0x04e24aa0 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5 0x04e24aa8 /* EEE Port N Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7     0x04e24ab8 /* EEE Port 7 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP    0x04e24ac0 /* EEE Port 8(IMP) Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0 0x04e24ac8 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1 0x04e24ad0 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2 0x04e24ad8 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3 0x04e24ae0 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4 0x04e24ae8 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5 0x04e24af0 /* EEE Port N Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7     0x04e24b00 /* EEE Port 7 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP    0x04e24b08 /* EEE Port 8(IMP) Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH         0x04e24b10 /* EEE Global Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0  0x04e24b18 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1  0x04e24b20 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2  0x04e24b28 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3  0x04e24b30 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4  0x04e24b38 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5  0x04e24b40 /* EEE TXQ N Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL            0x04e24b48 /* EEE PHY Control Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6        0x04e24b4c /* EEE TXQ 6 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7        0x04e24b54 /* EEE TXQ 7 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0      0x04e24b6c /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1      0x04e24b80 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_DEBUG               0x04e24b9c /* EEE Debug Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER      0x04e24ba0 /* EEE Link Delay Timer Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_STATE               0x04e24bb0 /* EEE Control Policy State Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_RED_CONTROL             0x04e25400 /* RED Control Register */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE    0x04e25408 /* RED Table Configuration Register */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS       0x04e25410 /* RED Egress Bypass Register */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL         0x04e25418 /* RED AQD Control Register */
+#define BCHP_SWITCH_CORE_RED_EXPONENT            0x04e25420 /* RED AQD Weighted Factor Register */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB     0x04e25428 /* RED Drop Add to MIB Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT     0x04e25440 /* Default RED profile Register */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0         0x04e25450 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1         0x04e25460 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0    0x04e25480 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1    0x04e25490 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2    0x04e254a0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3    0x04e254b0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4    0x04e254c0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5    0x04e254d0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6    0x04e254e0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7    0x04e254f0 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8    0x04e25500 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9    0x04e25510 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10   0x04e25520 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11   0x04e25530 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12   0x04e25540 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13   0x04e25550 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14   0x04e25560 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15   0x04e25570 /* RED profile N Register */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST       0x04e255b0 /* RED Drop Counter Reset Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0 0x04e255c0 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1 0x04e255d0 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2 0x04e255e0 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3 0x04e255f0 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4 0x04e25600 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5 0x04e25610 /* PORT N RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR 0x04e25630 /* PORT 7 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR 0x04e25640 /* PORT 8 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0 0x04e25680 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1 0x04e256a0 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2 0x04e256c0 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3 0x04e256e0 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4 0x04e25700 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5 0x04e25720 /* PORT N RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR 0x04e25760 /* PORT 7 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR 0x04e25780 /* PORT 8 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_CFP_ACC                 0x04e28000 /* CFP Access Registers */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL   0x04e28010 /* CFP RATE METER Global Control Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_0         0x04e28040 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_1         0x04e28050 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_2         0x04e28060 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_3         0x04e28070 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_4         0x04e28080 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_5         0x04e28090 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_6         0x04e280a0 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_7         0x04e280b0 /* CFP TCAM Data X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_0         0x04e280c0 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_1         0x04e280d0 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_2         0x04e280e0 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_3         0x04e280f0 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_4         0x04e28100 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_5         0x04e28110 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_6         0x04e28120 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_7         0x04e28130 /* CFP TCAM Mask X Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0           0x04e28140 /* CFP Action/Policy Data 0 Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1           0x04e28150 /* CFP Action/Policy Data 1 Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2           0x04e28160 /* CFP Action/Policy Data 2 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER0             0x04e28180 /* CFP RATE METER DATA 0 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER1             0x04e28190 /* CFP RATE METER DATA 1 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER2             0x04e281a0 /* CFP RATE METER DATA 2 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER3             0x04e281b0 /* CFP RATE METER DATA 3 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER4             0x04e281c0 /* CFP RATE METER DATA 4 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER5             0x04e281d0 /* CFP RATE METER DATA 5 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER6             0x04e281e0 /* CFP RATE METER DATA 6 Registers */
+#define BCHP_SWITCH_CORE_TC2COLOR                0x04e281f0 /* TC to COLOR Mapping Registers */
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR         0x04e28200 /* Policer Green color statistic counter */
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR        0x04e28210 /* Policer Yellow color statistic counter */
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR           0x04e28220 /* Policer RED color statistic counter */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL       0x04e28280 /* TCAM BIST Control Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS        0x04e28290 /* TCAM BIST Status Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS 0x04e282a0 /* TCAM Test Compare Status Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0          0x04e282c0 /* Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1          0x04e282d0 /* Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG             0x04e28400 /* CFP Control Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0      0x04e28440 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1      0x04e28444 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2      0x04e28448 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3      0x04e2844c /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4      0x04e28450 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5      0x04e28454 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6      0x04e28458 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7      0x04e2845c /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8      0x04e28460 /* UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0      0x04e28480 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1      0x04e28484 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2      0x04e28488 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3      0x04e2848c /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4      0x04e28490 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5      0x04e28494 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6      0x04e28498 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7      0x04e2849c /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8      0x04e284a0 /* UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0      0x04e284c0 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1      0x04e284c4 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2      0x04e284c8 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3      0x04e284cc /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4      0x04e284d0 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5      0x04e284d4 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6      0x04e284d8 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7      0x04e284dc /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8      0x04e284e0 /* UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0      0x04e28500 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1      0x04e28504 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2      0x04e28508 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3      0x04e2850c /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4      0x04e28510 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5      0x04e28514 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6      0x04e28518 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7      0x04e2851c /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8      0x04e28520 /* UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0      0x04e28540 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1      0x04e28544 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2      0x04e28548 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3      0x04e2854c /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4      0x04e28550 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5      0x04e28554 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6      0x04e28558 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7      0x04e2855c /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8      0x04e28560 /* UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0      0x04e28580 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1      0x04e28584 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2      0x04e28588 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3      0x04e2858c /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4      0x04e28590 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5      0x04e28594 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6      0x04e28598 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7      0x04e2859c /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8      0x04e285a0 /* UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0      0x04e285c0 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1      0x04e285c4 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2      0x04e285c8 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3      0x04e285cc /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4      0x04e285d0 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5      0x04e285d4 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6      0x04e285d8 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7      0x04e285dc /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8      0x04e285e0 /* UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0      0x04e28600 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1      0x04e28604 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2      0x04e28608 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3      0x04e2860c /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4      0x04e28610 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5      0x04e28614 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6      0x04e28618 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7      0x04e2861c /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8      0x04e28620 /* UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0      0x04e28640 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1      0x04e28644 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2      0x04e28648 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3      0x04e2864c /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4      0x04e28650 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5      0x04e28654 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6      0x04e28658 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7      0x04e2865c /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8      0x04e28660 /* UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0     0x04e28680 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1     0x04e28684 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2     0x04e28688 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3     0x04e2868c /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4     0x04e28690 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5     0x04e28694 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6     0x04e28698 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7     0x04e2869c /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8     0x04e286a0 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9     0x04e286a4 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10    0x04e286a8 /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11    0x04e286ac /* UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG             0x04e38000 /* CPU OTP Control RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG            0x04e38010 /* CPU OTP Address RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_STS_REG             0x04e38018 /* CPU OTP Status RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_WR_DATA             0x04e38020 /* CPU OTP Write Data RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_RD_DATA             0x04e38030 /* CPU OTP Read Data RegistersNot2Release */
+#define BCHP_SWITCH_CORE_IO_SR_CTL               0x04e38080 /* I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0              0x04e38090 /* I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2              0x04e380b0 /* I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL          0x04e380c0 /* GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0         0x04e380d0 /* GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1         0x04e380e0 /* GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0      0x04e38100 /* Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1      0x04e38110 /* Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_SPIDIO0                 0x04e3ffc0 /* SPI Data I/O Registers 0 */
+#define BCHP_SWITCH_CORE_SPIDIO1                 0x04e3ffc4 /* SPI Data I/O Registers 1 */
+#define BCHP_SWITCH_CORE_SPIDIO2                 0x04e3ffc8 /* SPI Data I/O Registers 2 */
+#define BCHP_SWITCH_CORE_SPIDIO3                 0x04e3ffcc /* SPI Data I/O Registers 3 */
+#define BCHP_SWITCH_CORE_SPIDIO4                 0x04e3ffd0 /* SPI Data I/O Registers 4 */
+#define BCHP_SWITCH_CORE_SPIDIO5                 0x04e3ffd4 /* SPI Data I/O Registers 5 */
+#define BCHP_SWITCH_CORE_SPIDIO6                 0x04e3ffd8 /* SPI Data I/O Registers 6 */
+#define BCHP_SWITCH_CORE_SPIDIO7                 0x04e3ffdc /* SPI Data I/O Registers 7 */
+#define BCHP_SWITCH_CORE_CLKSET                  0x04e3ffe8 /* Clock Period Setting Registers */
+#define BCHP_SWITCH_CORE_SPISTS                  0x04e3fff8 /* SPI Status Registers */
+#define BCHP_SWITCH_CORE_PAGEREG                 0x04e3fffc /* PAGE Control Registers */
+
+/***************************************************************************
+ *G_PCTL_Port_0 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_0 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_0 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_0 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_0 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_0_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *G_PCTL_Port_1 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_1 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_1 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_1 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_1 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_1_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *G_PCTL_Port_2 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_2 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_2 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_2 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_2 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_2_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *G_PCTL_Port_3 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_3 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_3 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_3 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_3 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_3_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *G_PCTL_Port_4 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_4 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_4 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_4 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_4 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_4_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *G_PCTL_Port_5 - Port N 10/100/1000 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: G_PCTL_Port_5 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_MASK          0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_SHIFT         5
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_G_MISTP_STATE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: G_PCTL_Port_5 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_MASK            0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_SHIFT           2
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_5 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_SHIFT                1
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_TX_DIS_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: G_PCTL_Port_5 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_SHIFT                0
+#define BCHP_SWITCH_CORE_G_PCTL_Port_5_RX_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *P7_CTL - Port 7 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_P7_CTL_reserved_for_padding0_MASK         0xffffff00
+#define BCHP_SWITCH_CORE_P7_CTL_reserved_for_padding0_SHIFT        8
+
+/* SWITCH_CORE :: P7_CTL :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_MASK                 0x000000e0
+#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_SHIFT                5
+#define BCHP_SWITCH_CORE_P7_CTL_G_MISTP_STATE_DEFAULT              0x00000001
+
+/* SWITCH_CORE :: P7_CTL :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_MASK                   0x0000001c
+#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_SHIFT                  2
+#define BCHP_SWITCH_CORE_P7_CTL_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: P7_CTL :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_MASK                        0x00000002
+#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_SHIFT                       1
+#define BCHP_SWITCH_CORE_P7_CTL_TX_DIS_DEFAULT                     0x00000000
+
+/* SWITCH_CORE :: P7_CTL :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_MASK                        0x00000001
+#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_SHIFT                       0
+#define BCHP_SWITCH_CORE_P7_CTL_RX_DIS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *IMP_CTL - IMP Port Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP_CTL_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_IMP_CTL_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: IMP_CTL :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_MASK                  0x000000e0
+#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_SHIFT                 5
+#define BCHP_SWITCH_CORE_IMP_CTL_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: IMP_CTL :: RX_UCST_EN [04:04] */
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_MASK                   0x00000010
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_SHIFT                  4
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_UCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: IMP_CTL :: RX_MCST_EN [03:03] */
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_MASK                   0x00000008
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_SHIFT                  3
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_MCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: IMP_CTL :: RX_BCST_EN [02:02] */
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_MASK                   0x00000004
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_SHIFT                  2
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_BCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: IMP_CTL :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_MASK                       0x00000002
+#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_SHIFT                      1
+#define BCHP_SWITCH_CORE_IMP_CTL_TX_DIS_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: IMP_CTL :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_SHIFT                      0
+#define BCHP_SWITCH_CORE_IMP_CTL_RX_DIS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RX_GLOBAL_CTL - RX Global Control register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: SWITCH_RESV [07:07] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_MASK            0x00000080
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_SHIFT           7
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_RX_MASK [06:06] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_MASK            0x00000040
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_SHIFT           6
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_ECC_CHK [05:05] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_MASK            0x00000020
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_SHIFT           5
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_CRC_CHK [04:04] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_MASK            0x00000010
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_SHIFT           4
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: FMOK_LATENCY_CNT [03:00] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *SWMODE - Switch Mode Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SWMODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_MASK         0xffffff00
+#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_SHIFT        8
+
+/* SWITCH_CORE :: SWMODE :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_MASK                   0x000000e0
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_SHIFT                  5
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SWMODE :: NOBLKCD [04:04] */
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_MASK                       0x00000010
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_SHIFT                      4
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: SWMODE :: FAST_TXDESC_RERURN [03:03] */
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_SHIFT           3
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWMODE :: RTRY_LMT_DIS [02:02] */
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_MASK                  0x00000004
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_SHIFT                 2
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_DEFAULT               0x00000001
+
+/* SWITCH_CORE :: SWMODE :: SW_FWDG_EN [01:01] */
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_MASK                    0x00000002
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_SHIFT                   1
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: SWMODE :: SW_FWDG_MODE [00:00] */
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_SHIFT                 0
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_DEFAULT               0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_IMP - IMP Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: MII_SW_OR [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_MASK           0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_SHIFT          7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: GMII_SPEED_UP_2G [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_MASK    0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_SHIFT   6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_MASK         0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_SHIFT        5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_MASK         0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_SHIFT        4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_MASK               0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_SHIFT              2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_DEFAULT            0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_MASK          0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_SHIFT         1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_MASK            0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_SHIFT           0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DEBUG_REG - Debug Control Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DEBUG_REG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: DEBUG_REG :: PROBE_SOC_DMU_CLK [07:07] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_MASK          0x00000080
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_SHIFT         7
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: DEBUG_REG :: DEBUG_SEL [06:01] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_MASK                  0x0000007e
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_SHIFT                 1
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: DEBUG_REG :: EN_DEBUG [00:00] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_MASK                   0x00000001
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_SHIFT                  0
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RM_PINS_DEBUG - Removed Pins Debug Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: RM_PINS_DEBUG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_MASK            0x000000f8
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_SHIFT           3
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: DIS_IMP_PIN [02:02] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_MASK            0x00000004
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_SHIFT           2
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: ENFDXFLOW_PIN [01:01] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_MASK          0x00000002
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_SHIFT         1
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: ENHDXFLOW_PIN [00:00] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_MASK          0x00000001
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_SHIFT         0
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_DEFAULT       0x00000001
+
+/***************************************************************************
+ *NEW_CTRL - New Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: NEW_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: NEW_CTRL :: MC_FWD_EN [07:07] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_MASK                   0x00000080
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_SHIFT                  7
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: UC_FWD_EN [06:06] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_MASK                   0x00000040
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_SHIFT                  6
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: EN_AUTO_PD_WAR [05:05] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_MASK              0x00000020
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_SHIFT             5
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: OVERRIDE_AUTO_PD_WAR [04:04] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_MASK        0x00000010
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_SHIFT       4
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: CABLE_DIAG_LEN [03:03] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_MASK              0x00000008
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_SHIFT             3
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: INRANGEERR_DISCARD [02:02] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_MASK          0x00000004
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_SHIFT         2
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: OUTRANGEERR_DISCARD [01:01] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_MASK         0x00000002
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_SHIFT        1
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: IP_MC [00:00] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_SHIFT                      0
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_DEFAULT                    0x00000001
+
+/***************************************************************************
+ *SWITCH_CTRL - Switch Control Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SWITCH_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_1 [15:07] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_MASK            0x0000ff80
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_SHIFT           7
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII_DUMB_FWDG_EN [06:06] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_MASK         0x00000040
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_SHIFT        6
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_0 [05:04] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_MASK            0x00000030
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_SHIFT           4
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: GPHY_PLLBYPASS [03:03] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_MASK           0x00000008
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_SHIFT          3
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII3_VOL_SEL [02:02] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_MASK             0x00000004
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_SHIFT            2
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII2_VOL_SEL [01:01] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_MASK             0x00000002
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_SHIFT            1
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_DEFAULT          0x00000001
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII1_VOL_SEL [00:00] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_MASK             0x00000001
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_SHIFT            0
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PROTECTED_SEL - Protected Port Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PROTECTED_SEL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PROTECTED_SEL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: PROTECTED_SEL :: PORT_SEL [08:00] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_SHIFT              0
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *WAN_PORT_SEL - WAN Port select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WAN_PORT_SEL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_1 [15:10] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_MASK           0x0000fc00
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_SHIFT          10
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: EN_MAN2WAN [09:09] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_MASK              0x00000200
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_SHIFT             9
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_0 [08:08] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_MASK           0x00000100
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_SHIFT          8
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: WAN_SELECT [07:00] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_MASK              0x000000ff
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_SHIFT             0
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PAUSE_CAP - PAUSE Capability Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV_1 [31:24] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_MASK              0xff000000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_SHIFT             24
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: EN_OVERRIDE [23:23] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_MASK                0x00800000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_SHIFT               23
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV [22:18] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_MASK                0x007c0000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_SHIFT               18
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: RX_PAUSE_CAP [17:09] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_MASK               0x0003fe00
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_SHIFT              9
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: TX_PAUSE_CAP [08:00] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_SHIFT              0
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RSV_MCAST_CTRL - Reserved Multicast Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_RES_MUL_LEARN [07:07] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_MASK      0x00000080
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_SHIFT     7
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: SWITCH_RESV [06:05] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_MASK           0x00000060
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_SHIFT          5
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_4 [04:04] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_MASK              0x00000010
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_SHIFT             4
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_3 [03:03] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_MASK              0x00000008
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_SHIFT             3
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_2 [02:02] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_MASK              0x00000004
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_SHIFT             2
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_1 [01:01] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_MASK              0x00000002
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_SHIFT             1
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_0 [00:00] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_MASK              0x00000001
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_SHIFT             0
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TXQ_FLUSH_MODE - TxQ Flush Mode Control Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_NEW_BOFF_SEED [07:07] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_MASK      0x00000080
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_SHIFT     7
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LATECOl65_DROP [06:06] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_MASK     0x00000040
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_SHIFT    6
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_ECOL_TXFM_MASK [05:05] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_MASK     0x00000020
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_SHIFT    5
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_TXFM_MASK [04:04] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_MASK     0x00000010
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_SHIFT    4
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_RELOAD_ERR_PATH [03:03] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_MASK    0x00000008
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_SHIFT   3
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_FLUSH [02:02] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_MASK         0x00000004
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_SHIFT        2
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: DIS_NEW_TXDIS [01:01] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_MASK         0x00000002
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_SHIFT        1
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: BYPASS_FASTTXDSC_PATH [00:00] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_MASK 0x00000001
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_SHIFT 0
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ULF_DROP_MAP - Unicast Lookup Failed Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ULF_DROP_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: ULF_DROP_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ULF_DROP_MAP :: UNI_LOOKUP_FAIL_FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MLF_DROP_MAP - Multicast Lookup Failed Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MLF_DROP_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MLF_DROP_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: MLF_DROP_MAP :: MUL_LOOKUP_FAIL_FRW_MAP [08:00] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MLF_IPMC_FWD_MAP - IPMC Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: MLF_IPMC_FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_SHIFT   0
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_PAUSE_PASS - Pause pass Through for RX Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_SHIFT         9
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_0 [08:08] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_MASK          0x00000100
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_SHIFT         8
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: RX_PAUSE_PASS [07:00] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_MASK          0x000000ff
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_SHIFT         0
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TX_PAUSE_PASS - Pause pass Through for TX Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TX_PAUSE_PASS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TX_PAUSE_PASS :: TX_PAUSE_PASS [08:00] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_SHIFT         0
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DIS_LEARN - Disable Learning Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DIS_LEARN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: DIS_LEARN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DIS_LEARN :: DIS_LEARN [08:00] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_SHIFT                 0
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SFT_LRN_CTL - Software Learning Control
+ ***************************************************************************/
+/* SWITCH_CORE :: SFT_LRN_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: SFT_LRN_CTL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: SFT_LRN_CTL :: SW_LEARN_CNTL [08:00] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_SHIFT           0
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *LOW_POWER_EXP1 - Low Power Expansion I Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_MASK         0xfe000000
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_SHIFT        25
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_MACCLK_PORT [24:16] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_MASK     0x01ff0000
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_SHIFT    16
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_SHIFT        9
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_SYSCLK_PORT [08:00] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_MASK     0x000001ff
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_SHIFT    0
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CTLREG_REG_SPARE - Spare Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_REG_SPARE :: CTLREG_REG_SPARE [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_SHIFT   0
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STS_OVERRIDE_GMIIP_Port_0 - Port N GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_MASK 0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_SHIFT 6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SW_OVERRIDE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_MASK 0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_SHIFT 5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_TXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_MASK 0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_SHIFT 4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_RXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_SHIFT     2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_SPEED_DEFAULT   0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_MASK 0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_SHIFT 1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_DUPLX_MODE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_0 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_MASK   0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_SHIFT  0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_0_LINK_STS_DEFAULT 0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMIIP_Port_1 - Port N GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_MASK 0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_SHIFT 6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SW_OVERRIDE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_MASK 0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_SHIFT 5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_TXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_MASK 0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_SHIFT 4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_RXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_SHIFT     2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_SPEED_DEFAULT   0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_MASK 0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_SHIFT 1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_DUPLX_MODE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_1 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_MASK   0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_SHIFT  0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_1_LINK_STS_DEFAULT 0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMIIP_Port_2 - Port N GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_MASK 0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_SHIFT 6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SW_OVERRIDE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_MASK 0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_SHIFT 5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_TXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_MASK 0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_SHIFT 4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_RXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_SHIFT     2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_SPEED_DEFAULT   0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_MASK 0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_SHIFT 1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_DUPLX_MODE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_2 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_MASK   0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_SHIFT  0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_2_LINK_STS_DEFAULT 0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMIIP_Port_3 - Port N GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_MASK 0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_SHIFT 6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SW_OVERRIDE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_MASK 0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_SHIFT 5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_TXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_MASK 0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_SHIFT 4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_RXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_SHIFT     2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_SPEED_DEFAULT   0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_MASK 0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_SHIFT 1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_DUPLX_MODE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_3 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_MASK   0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_SHIFT  0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_3_LINK_STS_DEFAULT 0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMIIP_Port_4 - Port N GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_MASK 0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_SHIFT 6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SW_OVERRIDE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_MASK 0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_SHIFT 5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_TXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_MASK 0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_SHIFT 4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_RXFLOW_CNTL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_SHIFT     2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_SPEED_DEFAULT   0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_MASK 0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_SHIFT 1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_DUPLX_MODE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMIIP_Port_4 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_MASK   0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_SHIFT  0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMIIP_Port_4_LINK_STS_DEFAULT 0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_P5 - Port 5 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: GMII_SPEED_UP_2G [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_MASK     0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_SHIFT    7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_GMII_SPEED_UP_2G_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_MASK          0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_SHIFT         6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SW_OVERRIDE_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_MASK          0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_SHIFT         5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_TXFLOW_CNTL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_MASK          0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_SHIFT         4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_RXFLOW_CNTL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_MASK                0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_SHIFT               2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_SPEED_DEFAULT             0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_MASK           0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_SHIFT          1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_DUPLX_MODE_DEFAULT        0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_P5 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_MASK             0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_SHIFT            0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P5_LINK_STS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STS_OVERRIDE_P7 - Port 7 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: GMII_SPEED_UP_2G [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_MASK     0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_SHIFT    7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_GMII_SPEED_UP_2G_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_MASK          0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_SHIFT         6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SW_OVERRIDE_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_MASK          0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_SHIFT         5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_TXFLOW_CNTL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_MASK          0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_SHIFT         4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_RXFLOW_CNTL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_MASK                0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_SHIFT               2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_SPEED_DEFAULT             0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_MASK           0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_SHIFT          1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_DUPLX_MODE_DEFAULT        0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_P7 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_MASK             0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_SHIFT            0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_P7_LINK_STS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_CTRL - Watch Dog Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: SOFTWARE_RESET [07:07] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_MASK        0x00000080
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_SHIFT       7
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_CHIP_RST [06:06] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_MASK           0x00000040
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_SHIFT          6
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: SWITCH_RESV [05:05] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_MASK           0x00000020
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_SHIFT          5
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_SW_RESET [04:04] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_MASK           0x00000010
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_SHIFT          4
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_AUTO_RST [03:03] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_MASK           0x00000008
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_SHIFT          3
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RELOAD_EEPROM [02:02] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_MASK      0x00000004
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_SHIFT     2
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_REGFILE [01:01] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_MASK        0x00000002
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_SHIFT       1
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_SWITCH [00:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_MASK         0x00000001
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_SHIFT        0
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_DEFAULT      0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT1 - Watch Dog Report 1 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: TX_PORT_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_SHIFT 0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT2 - Watch Dog Report 2 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: RX_PORT_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_SHIFT 0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT3 - Watch Dog Report 3 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: ARL_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_SHIFT   0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_FRM_CTRL - Pause Frame Detection Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_2 [07:03] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_MASK         0x000000f8
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_SHIFT        3
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_1 [02:01] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_MASK         0x00000006
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_SHIFT        1
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: PAUSE_IGNORE_DA [00:00] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_MASK       0x00000001
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PAUSE_ST_ADDR - PAUSE Frame DA Address
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_ST_ADDR :: PAUSE_ST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_MASK          0x000000000000
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_SHIFT         0
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_DEFAULT       0x0180c2000001
+
+/***************************************************************************
+ *FAST_AGE_CTRL - Fast Ageing Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: FAST_AGE_STR_DONE [07:07] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_MASK      0x00000080
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_SHIFT     7
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_MASK            0x00000040
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_SHIFT           6
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_MCAST [05:05] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_MASK           0x00000020
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_SHIFT          5
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_SPT [04:04] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_MASK             0x00000010
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_SHIFT            4
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_VLAN [03:03] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_SHIFT           3
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_PORT [02:02] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_MASK            0x00000004
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_SHIFT           2
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_DYNAMIC [01:01] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_MASK         0x00000002
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_SHIFT        1
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_DEFAULT      0x00000001
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_FAST_AGE_STATIC [00:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_MASK     0x00000001
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_SHIFT    0
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_DEFAULT  0x00000000
+
+/***************************************************************************
+ *FAST_AGE_PORT - Fast Ageing Port Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_PORT :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: FAST_AGE_PORT :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_MASK            0x000000f0
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_SHIFT           4
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_PORT :: AGE_PORT [03:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_MASK               0x0000000f
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_SHIFT              0
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *FAST_AGE_VID - Fast Ageing VID Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_VID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FAST_AGE_VID :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_MASK             0x0000f000
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_SHIFT            12
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_VID :: AGE_VID [11:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_MASK                 0x00000fff
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_SHIFT                0
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_DEFAULT              0x00000000
+
+/***************************************************************************
+ *LOW_POWER_CTRL - LOW Power Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LOW_POWER_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P8 [15:15] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_MASK              0x00008000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_SHIFT             15
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_1 [14:13] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_MASK         0x00006000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_SHIFT        13
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P5 [12:12] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_MASK              0x00001000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_SHIFT             12
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P4 [11:11] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_MASK              0x00000800
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_SHIFT             11
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_0 [10:07] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_MASK         0x00000780
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_SHIFT        7
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_SYS [06:06] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_MASK             0x00000040
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_SHIFT            6
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: TIMER_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_MASK         0x00000020
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_SHIFT        5
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: EN_LOW_POWER [04:04] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_MASK          0x00000010
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_SHIFT         4
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: LOW_POWER_DIVIDER [03:00] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_MASK     0x0000000f
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_SHIFT    0
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_DEFAULT  0x00000000
+
+/***************************************************************************
+ *TCAM_CTRL - TCAM Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: TCAM_CTRL :: EN_TCAM_CHKSUM [07:07] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_MASK             0x00000080
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_SHIFT            7
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TCAM_CTRL :: SWITCH_RESV [06:00] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_MASK                0x0000007f
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_SHIFT               0
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TCAM_CHKSUM_STS - TCAM Checksum Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ERR [15:15] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_MASK  0x00008000
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_SHIFT 15
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: SWITCH_RESV [14:08] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_MASK          0x00007f00
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_SHIFT         8
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ADDR [07:00] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_SHIFT 0
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LNKSTS - Link Status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LNKSTS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_SHIFT        16
+
+/* SWITCH_CORE :: LNKSTS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_MASK                   0x0000fe00
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_SHIFT                  9
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LNKSTS :: LNK_STS [08:00] */
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_MASK                       0x000001ff
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_SHIFT                      0
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *LNKSTSCHG - Link Status Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LNKSTSCHG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: LNKSTSCHG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: LNKSTSCHG :: LNK_STS_CHG [08:00] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_MASK                0x000001ff
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_SHIFT               0
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_DEFAULT             0x000001ff
+
+/***************************************************************************
+ *SPDSTS - Port Speed Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPDSTS :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_MASK                   0xfffc0000
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_SHIFT                  18
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SPDSTS :: PORT_SPD [17:00] */
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_MASK                      0x0003ffff
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_SHIFT                     0
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_DEFAULT                   0x0002aaaa
+
+/***************************************************************************
+ *DUPSTS - Duplex status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DUPSTS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_SHIFT        16
+
+/* SWITCH_CORE :: DUPSTS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_MASK                   0x0000fe00
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_SHIFT                  9
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: DUPSTS :: DUP_STS [08:00] */
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_MASK                       0x000001ff
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_SHIFT                      0
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_DEFAULT                    0x000001ff
+
+/***************************************************************************
+ *PAUSESTS - Pause Status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSESTS :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_MASK                 0xfffc0000
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_SHIFT                18
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: PAUSESTS :: PAUSE_STS [17:00] */
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_MASK                   0x0003ffff
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_SHIFT                  0
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_DEFAULT                0x00024120
+
+/***************************************************************************
+ *SRCADRCHG - Source Address Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SRCADRCHG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: SRCADRCHG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: SRCADRCHG :: SRC_ADDR_CHANGE [08:00] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_SHIFT           0
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *LSA_PORT_Port_0 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_0 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_0_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_Port_1 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_1 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_1_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_Port_2 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_2 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_2_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_Port_3 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_3 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_3_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_Port_4 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_4 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_4_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_Port_5 - Port N Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_Port_5 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_LSA_PORT_Port_5_LST_ADDR_DEFAULT          0x000000000000
+
+/***************************************************************************
+ *LSA_PORT7 - Port 7 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT7 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_MASK                   0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_SHIFT                  0
+#define BCHP_SWITCH_CORE_LSA_PORT7_LST_ADDR_DEFAULT                0x000000000000
+
+/***************************************************************************
+ *LSA_MII_PORT - Port 8 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_MII_PORT :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_MASK                0x000000000000
+#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_SHIFT               0
+#define BCHP_SWITCH_CORE_LSA_MII_PORT_LST_ADDR_DEFAULT             0x000000000000
+
+/***************************************************************************
+ *BIST_STS0 - BIST Status Register 0
+ ***************************************************************************/
+/* SWITCH_CORE :: BIST_STS0 :: BIST_STS0 [47:00] */
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_MASK                  0x000000000000
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_SHIFT                 0
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_DEFAULT               0x000000000000
+
+/***************************************************************************
+ *BIST_STS1 - BIST Status Register 1
+ ***************************************************************************/
+/* SWITCH_CORE :: BIST_STS1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: BIST_STS1 :: BIST_STS1 [15:00] */
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_MASK                  0x0000ffff
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_SHIFT                 0
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PBPTRFIFO_0 - PBPTRFIFO Status Register 0(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P5 [47:40] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_MASK             0xff0000000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_SHIFT            40
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P4 [39:32] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_MASK             0x00ff00000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_SHIFT            32
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P3 [31:24] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_MASK             0x0000ff000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_SHIFT            24
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P2 [23:16] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_MASK             0x000000ff0000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_SHIFT            16
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P1 [15:08] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_MASK             0x00000000ff00
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_SHIFT            8
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P0 [07:00] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_MASK             0x0000000000ff
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_SHIFT            0
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_DEFAULT          0x000000000002
+
+/***************************************************************************
+ *PBPTRFIFO_1 - PBPTRFIFO Status Register 1(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_1 [31:24] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_MASK            0xff000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_SHIFT           24
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P8 [23:16] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_MASK             0x00ff0000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_SHIFT            16
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P7 [15:08] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_MASK             0x0000ff00
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_SHIFT            8
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_0 [07:00] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_SHIFT           0
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_PIN_STATUS - Strap Pin Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STRAP_PIN_STATUS :: STRAP_VALUE_VECTOR [31:00] */
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_SHIFT 0
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_DEFAULT 0x000003f8
+
+/***************************************************************************
+ *DIRECT_INPUT_CTRL_VALUE - Direct Input Control Value Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: SWITCH_RESV [31:02] */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_MASK  0xfffffffc
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_SHIFT 2
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: DIRECT_INPUT_CTRL_VALUE [01:00] */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_MASK 0x00000003
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_SHIFT 0
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_STATUS - Reset Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RESET_STATUS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_1 [15:11] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_SHIFT          11
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SOC_BOOT_DN [10:10] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_MASK             0x00000400
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_SHIFT            10
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SW_CORE_RST_STS [09:09] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_MASK         0x00000200
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_SHIFT        9
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SW_REG_RST_STS [08:08] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_MASK          0x00000100
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_SHIFT         8
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_0 [07:06] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_SHIFT          6
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SD_RST_STS [05:05] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_MASK              0x00000020
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_SHIFT             5
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SPHY_RST_STS [04:04] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_MASK            0x00000010
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_SHIFT           4
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: QPHY_RST_STS [03:00] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_MASK            0x0000000f
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_SHIFT           0
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ENG_DET_STS - PHY Energy Detect Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_STS :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: ENG_DET_STS :: ENG_DET_STS [07:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_MASK              0x000000ff
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_SHIFT             0
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *ENG_DET_STS_CHG - PHY Energy Detect Status Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_STS_CHG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ENG_DET_STS_CHG :: ENG_DET_STS_CHG [07:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_SHIFT     0
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_DEFAULT   0x00000000
+
+/***************************************************************************
+ *STREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: STREG_REG_SPARE0 :: STREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: STREG_REG_SPARE1 :: STREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GMNGCFG - Global Management Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: GMNGCFG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: GMNGCFG :: FRM_MNGP [07:06] */
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_MASK                     0x000000c0
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_SHIFT                    6
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: SWITCH_RESV [05:02] */
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_MASK                  0x0000003c
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_SHIFT                 2
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: RXBPDU_EN [01:01] */
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_MASK                    0x00000002
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_SHIFT                   1
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: RST_MIB_CNT [00:00] */
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IMP0_PRT_ID - IMP/IMP0 Port ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP0_PRT_ID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: IMP0_PRT_ID :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_MASK              0x000000f0
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_SHIFT             4
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: IMP0_PRT_ID :: IMP0_PRT_ID [03:00] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_SHIFT             0
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_DEFAULT           0x00000008
+
+/***************************************************************************
+ *IMP1_PRT_ID - IMP1 Port ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP1_PRT_ID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: IMP1_PRT_ID :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_MASK              0x000000f0
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_SHIFT             4
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: IMP1_PRT_ID :: IMP1_PRT_ID [03:00] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_SHIFT             0
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_DEFAULT           0x00000005
+
+/***************************************************************************
+ *BRCM_HDR_CTRL - BRCM Header Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_MASK            0x000000f8
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_SHIFT           3
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: BRCM_HDR_EN [02:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_MASK            0x00000007
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_SHIFT           0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_DEFAULT         0x00000001
+
+/***************************************************************************
+ *SPTAGT - Aging Time Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPTAGT :: SWITCH_RESV [31:21] */
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_MASK                   0xffe00000
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_SHIFT                  21
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SPTAGT :: AGE_CHANGE_EN [20:20] */
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_MASK                 0x00100000
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_SHIFT                20
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: SPTAGT :: AGE_TIME [19:00] */
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_MASK                      0x000fffff
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_SHIFT                     0
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_DEFAULT                   0x0000012c
+
+/***************************************************************************
+ *BRCM_HDR_CTRL2 - BRCM Header Control 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_SHIFT        9
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_0 [08:05] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_MASK         0x000001e0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_SHIFT        5
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: BRCM_HDR_EN [04:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_MASK           0x0000001f
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *IPG_SHRNK_CTRL - IPG Shrink Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IPG_SHRNK_CTRL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_MASK           0xfffc0000
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_SHIFT          18
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: IPG_SHRNK_CTRL :: IPG_SHKCTRL [17:00] */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_MASK           0x0003ffff
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_SHIFT          0
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MIRCAPCTL - Mirror Capture Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MIRCAPCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: MIRCAPCTL :: MIR_EN [15:15] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_MASK                     0x00008000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_SHIFT                    15
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: BLK_NOT_MIR [14:14] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_MASK                0x00004000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_SHIFT               14
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_1 [13:06] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_MASK              0x00003fc0
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_SHIFT             6
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_0 [05:04] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_MASK              0x00000030
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_SHIFT             4
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SMIR_CAP_PORT [03:00] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_SHIFT             0
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *IGMIRCTL - Ingress Mirror Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_FLTR [15:14] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_MASK                 0x0000c000
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_SHIFT                14
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_DIV_EN [13:13] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_MASK                   0x00002000
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_SHIFT                  13
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: SWITCH_RESV [12:09] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_MASK                 0x00001e00
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_SHIFT                9
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_MSK [08:00] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IGMIRDIV - Ingress Mirror Divider Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRDIV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: IGMIRDIV :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_MASK                 0x0000fc00
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_SHIFT                10
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRDIV :: IN_MIR_DIV [09:00] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_MASK                  0x000003ff
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IGMIRMAC - Ingress Mirror Mac Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRMAC :: IN_MIR_MAC [47:00] */
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_MASK                  0x000000000000
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_DEFAULT               0x000000000000
+
+/***************************************************************************
+ *EGMIRCTL - Egress Mirror Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_FLTR [15:14] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_MASK                0x0000c000
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_SHIFT               14
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_DIV_EN [13:13] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_MASK                  0x00002000
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_SHIFT                 13
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: SWITCH_RESV [12:09] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_MASK                 0x00001e00
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_SHIFT                9
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_MSK [08:00] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_MASK                 0x000001ff
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_DEFAULT              0x00000000
+
+/***************************************************************************
+ *EGMIRDIV - Egress Mirror Divider Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRDIV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: EGMIRDIV :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_MASK                 0x0000fc00
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_SHIFT                10
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EGMIRDIV :: OUT_MIR_DIV [09:00] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_MASK                 0x000003ff
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_DEFAULT              0x00000000
+
+/***************************************************************************
+ *EGMIRMAC - Egress Mirror MAC Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRMAC :: OUT_MIR_MAC [47:00] */
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *MODEL_ID - Model ID Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MODEL_ID :: MODELID [31:00] */
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_SHIFT                    0
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_DEFAULT                  0x00053012
+
+/***************************************************************************
+ *CHIP_REVID - Chip Version ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CHIP_REVID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: CHIP_REVID :: REVID [07:00] */
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_MASK                     0x000000ff
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_SHIFT                    0
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *HL_PRTC_CTRL - High Level Protocol Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_1 [31:19] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_MASK           0xfff80000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_SHIFT          19
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_FWD_MODE [18:18] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_MASK        0x00040000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_SHIFT       18
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_EN [17:17] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_MASK              0x00020000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_SHIFT             17
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_FWD_MODE [16:16] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_MASK    0x00010000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_SHIFT   16
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_EN [15:15] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_MASK          0x00008000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_SHIFT         15
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_FWD_MODE [14:14] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_MASK       0x00004000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_SHIFT      14
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_EN [13:13] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_MASK             0x00002000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_SHIFT            13
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_FWD_MODE [12:12] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_MASK       0x00001000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_SHIFT      12
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_EN [11:11] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_MASK             0x00000800
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_SHIFT            11
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_FWD_MODE [10:10] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_MASK    0x00000400
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_SHIFT   10
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_EN [09:09] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_MASK          0x00000200
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_SHIFT         9
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_DIP_EN [08:08] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_MASK             0x00000100
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_SHIFT            8
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_0 [07:06] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_SHIFT          6
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPv6_FWD_MODE [05:05] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_MASK         0x00000020
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_SHIFT        5
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV6_EN [04:04] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_MASK               0x00000010
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_SHIFT              4
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV4_EN [03:03] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_MASK               0x00000008
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_SHIFT              3
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: DHCP_EN [02:02] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_SHIFT                2
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: RARP_EN [01:01] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_SHIFT                1
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ARP_EN [00:00] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_SHIFT                 0
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RST_MIB_CNT_EN - Reset MIB Counter Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: RST_MIB_CNT_EN [08:00] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_MASK        0x000001ff
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_SHIFT       0
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_DEFAULT     0x000001ff
+
+/***************************************************************************
+ *IPG_SHRINK_2G_WA - IPG Shrink 2G Workaround Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: VLD2_COND_DIS [08:00] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_MASK       0x000001ff
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_SHIFT      0
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *BRCM_HDR_RX_DIS - Broadcom Header RX Disable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: RX_DIS [08:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_SHIFT              0
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *BRCM_HDR_TX_DIS - Broadcom Header TX Disable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: TX_DIS [08:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_SHIFT              0
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MNGMODE_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MNGMODE_REG_SPARE0 :: MNGMODE_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MNGMODE_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MNGMODE_REG_SPARE1 :: MNGMODE_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INT_STS - External Host Raw Interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_STS :: INT_STS [31:00] */
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_MASK                      0xffffffff
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_SHIFT                     0
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *INT_EN - External Host Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_EN :: INT_EN [31:00] */
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_MASK                        0xffffffff
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_SHIFT                       0
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *IMP_SLEEP_TIMER - IMP Port(port 8) Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IMP_SLEEP_TIMER :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_MASK          0x0000e000
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: IMP_SLEEP_TIMER :: IMP_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_MASK      0x00001fff
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_SHIFT     0
+#define BCHP_SWITCH_CORE_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT7_SLEEP_TIMER - Port 7 Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_MASK        0x0000e000
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_SHIFT       13
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: PORT7_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_MASK  0x00001fff
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WAN_SLEEP_TIMER - WAN Port Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_MASK          0x0000e000
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: WAN_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_MASK      0x00001fff
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_SHIFT     0
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT_SLEEP_STS - Port Sleep Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SLEEP_STS :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_MASK           0x000000f8
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_SHIFT          3
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: PORT7_SLEEP_STS [02:02] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_MASK       0x00000004
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_SHIFT      2
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: WAN_PORT_SLEEP_STS [01:01] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_MASK    0x00000002
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_SHIFT   1
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: IMP_PORT_SLEEP_STS [00:00] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_MASK    0x00000001
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_SHIFT   0
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INT_TRIGGER - Interrupt Trigger Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_TRIGGER :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_MASK              0xfffffff8
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_SHIFT             3
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: INT_CPU_DOORBELL [02:02] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_MASK         0x00000004
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_SHIFT        2
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_DOORBELL [01:01] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_MASK         0x00000002
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_SHIFT        1
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_INT [00:00] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_MASK              0x00000001
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_SHIFT             0
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *LINK_STS_INT_EN - Link Status Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LINK_STS_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LINK_STS_INT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: LINK_STS_INT_EN :: LINK_STS_INT_EN [08:00] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_SHIFT     0
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_DEFAULT   0x000001ff
+
+/***************************************************************************
+ *ENG_DET_INT_EN - Energy Detection Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_SHIFT        9
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_0 [08:05] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_MASK         0x000001e0
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_SHIFT        5
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: ENG_DET_INT_EN [04:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_MASK        0x0000001f
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_SHIFT       0
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LPI_STS_CHG_INT_EN - LPI Status Change Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: LPI_STS_CHG_INT_EN [08:00] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *CPU_RESOURCE_ARBITER - CPU Resource Arbitor Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: SWITCH_RESV [07:02] */
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_MASK     0x000000fc
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_SHIFT    2
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: EXT_CPU_REQ [01:01] */
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_MASK     0x00000002
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_SHIFT    1
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: CPU_RESOURCE_ARBITER :: EXT_CPU_GNT [00:00] */
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_MASK     0x00000001
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_SHIFT    0
+#define BCHP_SWITCH_CORE_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_DATA_SHARE - CPU Data Share Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CPU_DATA_SHARE :: CPU_DATA_SHARE [63:00] */
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_MASK        0x0000000000000000
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_SHIFT       0
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_CPU_DATA_SHARE_DEFAULT     0x0000000000000000
+
+/***************************************************************************
+ *CPU_DATA_SHARE_1 - CPU Data Share 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CPU_DATA_SHARE_1 :: CPU_DATA_SHARE [63:00] */
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_MASK      0x0000000000000000
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_SHIFT     0
+#define BCHP_SWITCH_CORE_CPU_DATA_SHARE_1_CPU_DATA_SHARE_DEFAULT   0x0000000000000000
+
+/***************************************************************************
+ *MEM_ECC_ERR_INT_STS - Memory ECC Double-Error-Detection Interrupt Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_MASK      0x0000f800
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_SHIFT     11
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TXQ_ECC_DED_INT_STS [10:10] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_MASK 0x00000400
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_SHIFT 10
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: MIB_ECC_DED_INT_STS [09:09] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_MASK 0x00000200
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_SHIFT 9
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: EVT_ECC_DED_INT_STS [08:08] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_MASK 0x00000100
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_SHIFT 8
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: STS_ECC_DED_INT_STS [07:07] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_MASK 0x00000080
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_SHIFT 7
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ACTRAT_ECC_DED_INT_STS [06:06] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_MASK 0x00000040
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_SHIFT 6
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TCS_ECC_DED_INT_STS [05:05] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_MASK 0x00000020
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_SHIFT 5
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: FM_ECC_DED_INT_STS [04:04] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_SHIFT 4
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: BT_ECC_DED_INT_STS [03:03] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_MASK 0x00000008
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_SHIFT 3
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: VL_ECC_DED_INT_STS [02:02] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_MASK 0x00000004
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_SHIFT 2
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_SCON_ECC_DED_INT_STS [01:01] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_MASK 0x00000002
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_SHIFT 1
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_ATMU_ECC_DED_INT_STS [00:00] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_MASK 0x00000001
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEM_ECC_ERR_INT_EN - Memory ECC Double-Error-Detection Interrupt Enable (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TXQ_ECC_DED_INT_EN [10:10] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_MASK 0x00000400
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_SHIFT 10
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: MIB_ECC_DED_INT_EN [09:09] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_MASK 0x00000200
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_SHIFT 9
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: EVT_ECC_DED_INT_EN [08:08] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_MASK 0x00000100
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_SHIFT 8
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: STS_ECC_DED_INT_EN [07:07] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_MASK 0x00000080
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ACTRAT_ECC_DED_INT_EN [06:06] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_MASK 0x00000040
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_SHIFT 6
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TCS_ECC_DED_INT_EN [05:05] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_MASK 0x00000020
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_SHIFT 5
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: FM_ECC_DED_INT_EN [04:04] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: BT_ECC_DED_INT_EN [03:03] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_MASK 0x00000008
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_SHIFT 3
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: VL_ECC_DED_INT_EN [02:02] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_MASK 0x00000004
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_SCON_ECC_DED_INT_EN [01:01] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_MASK 0x00000002
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_SHIFT 1
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_ATMU_ECC_DED_INT_EN [00:00] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_MASK 0x00000001
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PORT_EVT_ECC_ERR_STS - Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: EVT_ECC_ERR_STS [08:00] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_MIB_ECC_ERR_STS - Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fc00
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_SHIFT    10
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: MIB_ECC_ERR_STS [09:00] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_MASK 0x000003ff
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_TXQ_ECC_ERR_STS - Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: TXQ_ECC_ERR_STS [08:00] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PROBE_BUS_CTL - Probe Bus Control Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_DEBUG_CTL [31:24] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_MASK        0xff000000
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_SHIFT       24
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_CLK_SEL [23:16] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_MASK          0x00ff0000
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_SHIFT         16
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_DEBUG_SEL [15:08] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_MASK     0x0000ff00
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_SHIFT    8
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_PROBE_SEL [07:00] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_MASK     0x000000ff
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_SHIFT    0
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MDC_EXTEND_CTRL - MDC Extend Clock Control Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_MASK          0x000000fe
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_SHIFT         1
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: EXTENDED_MDC_EN [00:00] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_MASK      0x00000001
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_SHIFT     0
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PPPOE_SESSION_PARSE_EN - PPPoE Session Packet Parsing Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: SWITCH_RESV [31:25] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_MASK   0xfe000000
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_SHIFT  25
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_PARSE_EN [24:16] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_MASK 0x01ff0000
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_SHIFT 16
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_ETYPE [15:00] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_SHIFT 0
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_DEFAULT 0x00008864
+
+/***************************************************************************
+ *CTLREG_1_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_1_REG_SPARE0 :: CTLREG_1_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CTLREG_1_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_1_REG_SPARE1 :: CTLREG_1_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GARLCFG - Global ARL Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: GARLCFG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_1 [07:03] */
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_MASK                0x000000f8
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_SHIFT               3
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: GARLCFG :: AGE_ACC [02:02] */
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_MASK                      0x00000004
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_SHIFT                     2
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_0 [01:01] */
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_MASK                0x00000002
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_SHIFT               1
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_DEFAULT             0x00000001
+
+/* SWITCH_CORE :: GARLCFG :: HASH_DISABLE [00:00] */
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_SHIFT                0
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *BPDU_MCADDR - BPDU Multicast Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BPDU_MCADDR :: BPDU_MC_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_DEFAULT          0x0180c2000000
+
+/***************************************************************************
+ *MULTI_PORT_CTL - Multiport Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTI_PORT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT0_TS_EN [15:15] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_MASK          0x00008000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_SHIFT         15
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_DA_HIT_EN [14:14] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_MASK       0x00004000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_SHIFT      14
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: SWITCH_RESV [13:12] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_MASK           0x00003000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_SHIFT          12
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL5 [11:10] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_MASK           0x00000c00
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_SHIFT          10
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL4 [09:08] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_MASK           0x00000300
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_SHIFT          8
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL3 [07:06] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_SHIFT          6
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL2 [05:04] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_MASK           0x00000030
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_SHIFT          4
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL1 [03:02] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_SHIFT          2
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL0 [01:00] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_MASK           0x00000003
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR0 - Multiport Address 0 Register (Default for TS)
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC0 - Multiport Vector 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC0 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC0 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR1 - Multiport Address 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC1 - Multiport Vector 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC1 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC1 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR2 - Multiport Address 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC2 - Multiport Vector 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC2 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC2 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR3 - Multiport Address 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC3 - Multiport Vector 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC3 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC3 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR4 - Multiport Address 4 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC4 - Multiport Vector 4 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC4 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC4 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR5 - Multiport Address 5 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC5 - Multiport Vector 5 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC5 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC5 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *ARL_BIN_FULL_CNTR - ARL Bin Full Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARL_BIN_FULL_CNTR :: ARL_BIN_FUL_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_SHIFT  0
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARL_BIN_FULL_FWD - ARL Biin Full Forward Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: Reserved [15:01] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_MASK            0x0000fffe
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_SHIFT           1
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: ARL_BIN_FULL_FWD_EN [00:00] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_MASK 0x00000001
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLCTL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLCTL_REG_SPARE0 :: ARLCTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLCTL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLCTL_REG_SPARE1 :: ARLCTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLA_RWCTL - ARL Read/Write Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_RWCTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: ARLA_RWCTL :: ARL_STRTDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_MASK                0x00000080
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_SHIFT               7
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: IVL_SVL_SELECT [06:06] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_MASK            0x00000040
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_SHIFT           6
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: SWITCH_RESV [05:01] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_MASK               0x0000003e
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_SHIFT              1
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: ARL_RW [00:00] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_SHIFT                   0
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ARLA_MAC - MAC Address Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MAC :: MAC_ADDR_INDX [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_MASK               0x000000000000
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_DEFAULT            0x000000000000
+
+/***************************************************************************
+ *ARLA_VID - VID Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_RSRV0 [15:12] */
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_MASK           0x0000f000
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_SHIFT          12
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_INDX [11:00] */
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY0 - ARL MAC/VID Entry 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY0 - ARL FWD Entry 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY1 - ARL MAC/VID Entry 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY1 - ARL FWD Entry 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY2 - ARL MAC/VID Entry 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY2 - ARL FWD Entry 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY3 - ARL MAC/VID Entry 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY3 - ARL FWD Entry 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_CTL - ARL Search Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_STDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_MASK         0x00000080
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_SHIFT        7
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: SWITCH_RESV [06:01] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_MASK            0x0000007e
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_SHIFT           1
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_VLID [00:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_MASK         0x00000001
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_SHIFT        0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_DEFAULT      0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_ADR - ARL Search Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADR_VALID [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_MASK    0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_SHIFT   15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADDRESS [14:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_MASK      0x00007fff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_SHIFT     0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_DEFAULT   0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_0_MACVID - ARL Search MAC/VID Result 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_MASK  0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_SHIFT 60
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_RSLT_VID_0 [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_MASK 0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_SHIFT 48
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_MACADDR_0 [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_0 - ARL Search Result 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_MASK         0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_SHIFT        17
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_VLID_0 [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_MASK 0x00010000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_SHIFT 16
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_STATIC_0 [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_MASK 0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_SHIFT 15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_AGE_0 [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_MASK 0x00004000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_SHIFT 14
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_PRI_0 [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_MASK 0x00003800
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_SHIFT 11
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARL_CON_0 [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_MASK           0x00000600
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_SHIFT          9
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: PORTID_0 [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_1_MACVID - ARL Search MAC/VID Result 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_MASK  0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_SHIFT 60
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_RSLT_VID_1 [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_MASK 0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_SHIFT 48
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_MACADDR_1 [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_1 - ARL Search Result 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_MASK         0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_SHIFT        17
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_VLID_1 [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_MASK 0x00010000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_SHIFT 16
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_STATIC_1 [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_SHIFT 15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_AGE_1 [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_MASK 0x00004000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_SHIFT 14
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_PRI_1 [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_MASK 0x00003800
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_SHIFT 11
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARL_CON_1 [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_MASK           0x00000600
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_SHIFT          9
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: PORTID_1 [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_RWCTRL - VTBL Read/Write/Clear Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_STDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_MASK      0x00000080
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_SHIFT     7
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: SWITCH_RESV [06:02] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_MASK         0x0000007c
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_SHIFT        2
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_RW_CLR [01:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_MASK    0x00000003
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_SHIFT   0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_ADDR - VTBL Address Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_MASK           0x0000f000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_SHIFT          12
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: VTBL_ADDR_INDEX [11:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_MASK       0x00000fff
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_DEFAULT    0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_ENTRY - VTBL Entry Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: SWITCH_RESV [31:22] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_MASK          0xffc00000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_SHIFT         22
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MODE [21:21] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_MASK             0x00200000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_SHIFT            21
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: MSPT_INDEX [20:18] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_MASK           0x001c0000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_SHIFT          18
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: UNTAG_MAP [17:09] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_MASK            0x0003fe00
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_SHIFT           9
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_SHIFT             0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_DEFAULT           0x00000000
+
+/***************************************************************************
+ *ARLACCS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLACCS_REG_SPARE0 :: ARLACCS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLACCS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLACCS_REG_SPARE1 :: ARLACCS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEM_CTRL - Memory Debug Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: MEM_CTRL :: MEM_TYPE [07:06] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_MASK                    0x000000c0
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_SHIFT                   6
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_1 [05:04] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_MASK               0x00000030
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_SHIFT              4
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_MASK               0x0000000f
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_ADDR - Memory Debug Address RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_STDN [15:15] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_MASK                    0x00008000
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_SHIFT                   15
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_RW [14:14] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_MASK                      0x00004000
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_SHIFT                     14
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_ADR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_MASK                     0x00003fff
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_SHIFT                    0
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_0_0 - Memory Debug Data 0_0 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_0 :: MEM_DAT [63:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_0_1 - Memory Debug Data 0_1 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: MEM_DAT [15:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_1_0 - Memory Debug Data 1_0 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_0 :: MEM_DAT [63:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_1_1 - Memory Debug Data 1_1 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: MEM_DAT [15:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MEM_FRM_ADDR - Frame Memory Address RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_STDN [15:15] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_MASK                0x00008000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_SHIFT               15
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_RW [14:14] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_MASK                  0x00004000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_SHIFT                 14
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_ADR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_MASK                 0x00003fff
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_FRM_DATA0 - Frame Memory Data 1st RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA0 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA1 - Frame Memory Data 2st RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA1 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA2 - Frame Memory Data 3st RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA2 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA3 - Frame Memory Data 4th RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA3 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_BTM_DATA0 - Buffer Tag Memory Register 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BTM_DATA0 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_BTM_DATA1 - Buffer Tag Memory Register 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BTM_DATA1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_BTM_DATA1 :: MEM_DATA [15:00] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_MASK               0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_BFC_ADDR - Buffer Control Memory Address RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BFC_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: MEM_REQ [15:15] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_MASK                 0x00008000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_SHIFT                15
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: RW_CTRL [14:14] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_MASK                 0x00004000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_SHIFT                14
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: BFC_ADDR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_MASK                0x00003fff
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_BFC_DATA - Buffer Control Memory Data RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BFC_DATA :: BFC_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *PRS_FIFO_DEBUG_CTRL - PRS_FIFO Debug Control Register(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_MASK      0x000000f0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_SHIFT     4
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: PRS_FIFO_DBG_CTRL [03:00] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_SHIFT 0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PRS_FIFO_DEBUG_DATA - PRS_FIFO Debug Data Register(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_DATA :: PRS_FIFO_DBG_DATA [63:00] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_SHIFT 0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *MEM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_REG_SPARE0 :: MEM_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MEM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_REG_SPARE1 :: MEM_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MEM_MISC_CTRL - Memory Misc Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_MISC_CTRL :: SWITCH_RESV [31:05] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_MASK            0xffffffe0
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_SHIFT           5
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: TXQ_DCM [04:04] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_MASK                0x00000010
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_SHIFT               4
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: PB_DCM [03:03] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_SHIFT                3
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: BT_DCM [02:02] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_SHIFT                2
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: ARL_DCM [01:01] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_MASK                0x00000002
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_SHIFT               1
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: CK_AON [00:00] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_DEFAULT              0x00000001
+
+/***************************************************************************
+ *MEM_TEST_CTRL0 - Memory Test Control 0 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: VL_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_MASK                 0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_SHIFT                20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: ARL_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_MASK                0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL1 - Memory Test Control 1 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: ACTRAT_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_MASK             0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_SHIFT            20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: BT_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_MASK                 0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL2 - Memory Test Control 2 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: STS_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_MASK                0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_SHIFT               20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: PB_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_MASK                 0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL3 - Memory Test Control 3 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: EVT_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_MASK                0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_SHIFT               20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: TXQ_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_MASK                0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL4 - Memory Test Control 4 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_1 [31:26] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_MASK         0xfc000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_SHIFT        26
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_CHKSUM_TM [25:16] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_MASK        0x03ff0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_SHIFT       16
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_0 [15:14] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_SHIFT        14
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_TM [13:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_MASK               0x00003fff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL5 - Memory Test Control 5 RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL5 :: SWITCH_RESV [31:06] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_MASK           0xffffffc0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL5 :: MIB_TM [05:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_MASK                0x0000003f
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_PSM_VDD_CTRL - Memory PSM_VDD Pin Control registerNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: SWITCH_RESV [31:22] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_MASK         0xffc00000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_SHIFT        22
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: STS_PSM_VDD [21:20] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_MASK         0x00300000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_SHIFT        20
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: ACTRAT_PSM_VDD [19:18] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_MASK      0x000c0000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_SHIFT     18
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: IMP_TXQ_PSM_VDD [17:16] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_MASK     0x00030000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_SHIFT    16
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P7_TXQ_PSM_VDD [15:14] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_MASK      0x0000c000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_SHIFT     14
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P6_TXQ_PSM_VDD [13:12] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_MASK      0x00003000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_SHIFT     12
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P5_TXQ_PSM_VDD [11:10] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_MASK      0x00000c00
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_SHIFT     10
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P4_TXQ_PSM_VDD [09:08] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_MASK      0x00000300
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_SHIFT     8
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P3_TXQ_PSM_VDD [07:06] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_MASK      0x000000c0
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_SHIFT     6
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P2_TXQ_PSM_VDD [05:04] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_MASK      0x00000030
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_SHIFT     4
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P1_TXQ_PSM_VDD [03:02] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_SHIFT     2
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P0_TXQ_PSM_VDD [01:00] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_MASK      0x00000003
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_SHIFT     0
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT0_DEBUG - PORT0 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT0_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT1_DEBUG - PORT1 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT1_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT2_DEBUG - PORT2 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT2_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT3_DEBUG - PORT3 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT3_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT4_DEBUG - PORT4 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT4_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT5_DEBUG - PORT5 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT5_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT6_DEBUG - PORT6 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT6_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT7_DEBUG - PORT7 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT7_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT8_DEBUG - PORT8 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT8_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *FC_DIAG_CTRL - Flowcon Diagnosis Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_DIAG_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_DIAG_CTRL :: SWITCH_RESV [15:04] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_MASK             0x0000fff0
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_DIAG_CTRL :: DIAG_FLOWCON_PORT [03:00] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_CTRL_MODE - Flow Control Mode Selection RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CTRL_MODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: FC_CTRL_MODE :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_MASK             0x000000fe
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_SHIFT            1
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_CTRL_MODE :: FC_MODE [00:00] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_SHIFT                0
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FC_CTRL_PORT - Flow Control Port Selection RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CTRL_PORT :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: FC_CTRL_PORT :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_MASK             0x000000f0
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_CTRL_PORT :: FC_PORT_SEL [03:00] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_MASK             0x0000000f
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_SHIFT            0
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FC_OOB_PAUSE_EN - OOB Pause Signal Enable Register (Release2Customer)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: OOB_PAUSE_EN [08:00] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PAUSE_TIME_MAX - MAX Quantum Pause Time RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_MAX :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_MAX :: PAUSE_TIME_MAX [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_MASK        0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_SHIFT       0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_DEFAULT     0x00008000
+
+/***************************************************************************
+ *PAUSE_TIME_MIN - MIN Quantum Pause Time RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_MIN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_MIN :: PAUSE_TIME_MIN [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_MASK        0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_SHIFT       0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_DEFAULT     0x00000400
+
+/***************************************************************************
+ *PAUSE_TIME_RESET_THD - Quantum Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_MASK     0x0000f800
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_SHIFT    11
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: PAUSE_TIME_RESET_THD [10:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_DEFAULT 0x00000100
+
+/***************************************************************************
+ *PAUSE_TIME_UPDATE_PERIOD - Quantum Pause Update Period RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: PAUSE_TIME_UPDATE_PERIOD [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_DEFAULT 0x00001000
+
+/***************************************************************************
+ *PAUSE_TIME_DEFAULT - Default Quantum Pause Time RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: PAUSE_TIME_DEFAULT [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_DEFAULT 0x00001000
+
+/***************************************************************************
+ *FC_MCAST_DROP_CTRL - Multicast Drop Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: MCAST_PARTIAL_DROP_EN [08:00] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *FC_PAUSE_DROP_CTRL - Pause/Drop Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: QUEUE_BASED_PAUSE_EN [12:12] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_MASK 0x00001000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_SHIFT 12
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TOTAL_PAUSE_EN [11:11] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_MASK 0x00000800
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TXQ_PAUSE_EN [10:10] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_MASK 0x00000400
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_SHIFT 10
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TOTAL_PAUSE_EN [09:09] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_MASK 0x00000200
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_SHIFT 9
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TXQ_PAUSE_EN [08:08] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_MASK 0x00000100
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_SHIFT 8
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_PAUSE_EN [07:07] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_MASK 0x00000080
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_PAUSE_EN [06:06] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_MASK   0x00000040
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_SHIFT  6
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_DROP_EN [05:05] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_MASK        0x00000020
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_SHIFT       5
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_DROP_EN [04:04] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_MASK  0x00000010
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_DROP_EN [03:03] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_MASK    0x00000008
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_SHIFT   3
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_BASED_CTRL_EN [02:02] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_MASK  0x00000004
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_QUANTUM_CTRL_EN [01:01] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_MASK 0x00000002
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_SHIFT 1
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_BASED_CTRL_EN [00:00] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_MASK  0x00000001
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FC_TXQ_THD_PAUSE_OFF - TXQ Pause Off Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_MASK     0x0000f800
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_SHIFT    11
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: TXQ_THD_PAUSE_OFF [10:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_DEFAULT 0x00000008
+
+/***************************************************************************
+ *FC_RX_RUNOFF - RX-Based Run-Off RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_RUNOFF :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_RX_RUNOFF :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_RX_RUNOFF :: RX_RUN_OFF_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_DEFAULT       0x00000013
+
+/***************************************************************************
+ *FC_RX_RSV_THD - RX-Based Reserved RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_RSV_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_RSV_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_RX_RSV_THD :: RX_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_DEFAULT          0x0000000a
+
+/***************************************************************************
+ *FC_RX_HYST_THD - RX-Based Hysteresis RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_HYST_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_HYST_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_SHIFT          11
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FC_RX_HYST_THD :: RX_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_DEFAULT        0x00000014
+
+/***************************************************************************
+ *FC_RX_MAX_PTR - RX-Based Maximum Buffer Remap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: EN_REMAP [15:15] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_MASK               0x00008000
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_SHIFT              15
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: SWITCH_RESV [14:11] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_MASK            0x00007800
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: MAXBUF_REMAP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_DEFAULT    0x000001ea
+
+/***************************************************************************
+ *FC_SPARE_ZERO_REG - Flow Control Spare Zero RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: SPARE_ZERO [15:00] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_MASK         0x0000ffff
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_SPARE_ONE_REG - Flow Control Spare One RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_SPARE_ONE_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_SPARE_ONE_REG :: SPARE_ONE [15:00] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_DEFAULT        0x0000ffff
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_0 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_0 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_0_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_1 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_1 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_1_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_2 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_2 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_2_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_3 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_3 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_3_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_4 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_4 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_4_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_5 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_5 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_5_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_6 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_6 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_6_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_MON_TXQ_Port_7 - Monitored TXQ N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_MON_TXQ_Port_7 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MON_TXQ_Port_7_MONITORED_TXQ_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_0 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_0 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_0_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_1 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_1 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_1_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_2 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_2 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_2_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_3 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_3 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_3_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_4 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_4 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_4_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_5 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_5 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_5_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_6 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_6 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_6_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TXQ_Port_7 - Peak TXQ N Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TXQ_Port_7 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_MASK      0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_FC_PEAK_TXQ_Port_7_PEAK_TXQ_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TOTAL_USED - Peak Total Used Count RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: PEAK_TOTAL_USE_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_USED - Total Used Count RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_USED :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_USED :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_TOTAL_USED :: TOTAL_USE_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_SHIFT         0
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *FC_PEAK_RX_CNT - Peak RX Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_SHIFT          11
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: PEAK_RXBUF_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *FC_LINK_PORTMAP - PHY Link Information RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: LINK_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_GIGA_PORTMAP - Giga Speed Information RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: GIGA_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_0 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_0 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_0_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_1 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_1 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_1_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_2 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_2 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_2_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_3 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_3 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_3_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_4 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_4 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_4_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_PN_Port_5 - Port N Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_PN_Port_5 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_PN_Port_5_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P7 - Port 7 Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P8 - Port 8 Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_PAUSE_HIS - Pause History RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_HIS :: PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_SHIFT              0
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *FC_TX_QUANTUM_PAUSE_HIS - TX Quantum Pause History RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: TX_QUANTUM_PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_RX_PAUSE_HIS - RX Based Pause History RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: RX_PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_RXBUF_ERR_HIS - RX Buffer Error History RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: RXBUF_ERR_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_MASK       0x000001ff
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_0 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_0 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_0_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_1 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_1 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_1_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_2 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_2 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_2_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_3 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_3 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_3_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_4 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_4 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_4_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_PN_Port_5 - Port N TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_PN_Port_5 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_PN_Port_5_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P7 - Port 7 TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P8 - Port 8 TXQ Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_0 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_0 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_0_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_1 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_1 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_1_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_2 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_2 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_2_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_3 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_3 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_3_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_4 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_4 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_4_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_PN_Port_5 - Port N Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_PN_Port_5 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_PN_Port_5_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P7 - Port 7 Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P8 - Port 8 Total Congested PortMap RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_0 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_1 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_2 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_3 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_4 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_5 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_6 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_QN_Port_7 - LAN Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_0 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x0000004b
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_1 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x0000004f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_2 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x00000053
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_3 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x00000057
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_4 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x0000005b
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_5 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x0000005f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_6 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x00000063
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_QN_Port_7 - LAN Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_0 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x00000097
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_1 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x0000009f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_2 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000a7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_3 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000af
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_4 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000b7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_5 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000bf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_6 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000c7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_QN_Port_7 - LAN Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_0 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_1 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_2 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_3 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_4 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_5 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_6 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_QN_Port_7 - LAN Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_0 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_1 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_2 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_3 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_4 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_5 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_6 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_QN_Port_7 - LAN Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x0000040f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x00000417
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x0000041f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x00000427
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x0000042f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x00000437
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 - LAN Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_0 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x0000058f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_1 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x00000597
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_2 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x0000059f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_3 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005a7
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_4 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005af
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_5 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005b7
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_6 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005bf
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_QN_Port_7 - LAN Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *P0_DEBUG_MUX - P0 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P0_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P1_DEBUG_MUX - P1 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P1_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P2_DEBUG_MUX - P2 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P2_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P3_DEBUG_MUX - P3 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P3_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P4_DEBUG_MUX - P4 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P4_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P5_DEBUG_MUX - P5 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P5_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P6_DEBUG_MUX - P6 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P6_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P7_DEBUG_MUX - P7 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P7_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *IMP_DEBUG_MUX - IMP DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_SHIFT           0
+#define BCHP_SWITCH_CORE_IMP_DEBUG_MUX_SWITCH_RESV_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DEBUG_BUS_0 - CFP DEBUG BUS 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DEBUG_BUS_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_SHIFT         0
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_DEFAULT       0x00000021
+
+/***************************************************************************
+ *CFP_DEBUG_BUS_1 - CFP DEBUG BUS 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DEBUG_BUS_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_SHIFT         0
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_DEFAULT       0x00000000
+
+/***************************************************************************
+ *WRED_DEBUG_0 - WRED DEBUG 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_DEBUG_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *WRED_DEBUG_1 - WRED DEBUG 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_DEBUG_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TOP_MISC_DEBUG_0 - TOP MISC DEBUG 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TOP_MISC_DEBUG_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_SHIFT        0
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_DEFAULT      0x00000002
+
+/***************************************************************************
+ *TOP_MISC_DEBUG_1 - TOP MISC DEBUG 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TOP_MISC_DEBUG_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_SHIFT        0
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_DEFAULT      0x00000000
+
+/***************************************************************************
+ *DIAGREG_BUFCON - DIAGREG BUFCONNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DIAGREG_BUFCON :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_SHIFT          0
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_DEFAULT        0x0000fffc
+
+/***************************************************************************
+ *TESTBUS_P1588 - TESTBUS P1588Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TESTBUS_P1588 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_SHIFT           0
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_DEFAULT         0x00000000
+
+/***************************************************************************
+ *FLOWCON_DEBUG_BUS - FLOWCON DEBUG BUSNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FLOWCON_DEBUG_BUS :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_SHIFT       0
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_DEFAULT     0x00000000
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_0 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_1 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_2 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_3 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_4 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_5 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_6 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_QN_Port_7 - IMP0 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_0 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x00000063
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_1 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_2 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x0000006b
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_3 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x0000006f
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_4 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x00000073
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_5 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x00000077
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_6 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x0000007b
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_QN_Port_7 - IMP0 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x0000007f
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x000000c7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000d7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000df
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000e7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000ef
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000f7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 - IMP0 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x000000ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_0 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_1 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_2 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_3 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_4 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_5 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_6 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_QN_Port_7 - IMP0 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_0 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_1 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_2 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_3 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_4 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_5 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_6 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_QN_Port_7 - IMP0 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x00000457
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x00000467
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 - IMP0 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x00000477
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_0 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x000005bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_1 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_2 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_3 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005d7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_4 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005df
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_5 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005e7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_6 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005ef
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_QN_Port_7 - IMP0 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005f7
+
+/***************************************************************************
+ *FC_IMP0_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: FC_IMP0_REG_SPARE0 [15:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_IMP0_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: FC_IMP0_REG_SPARE1 [15:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 - WAN/IMP1 Port Queue N Reserved Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_QN_Port_7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_0_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_1_TXQ_HYST_THD_DEFAULT 0x0000006b
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_2_TXQ_HYST_THD_DEFAULT 0x0000006f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_3_TXQ_HYST_THD_DEFAULT 0x00000073
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_4_TXQ_HYST_THD_DEFAULT 0x00000077
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_5_TXQ_HYST_THD_DEFAULT 0x0000007b
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_6_TXQ_HYST_THD_DEFAULT 0x0000007f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 - WAN/IMP1 Port Queue N Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_QN_Port_7_TXQ_HYST_THD_DEFAULT 0x00000083
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_0_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_1_TXQ_PAUSE_THD_DEFAULT 0x000000d7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_2_TXQ_PAUSE_THD_DEFAULT 0x000000df
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_3_TXQ_PAUSE_THD_DEFAULT 0x000000e7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_4_TXQ_PAUSE_THD_DEFAULT 0x000000ef
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_5_TXQ_PAUSE_THD_DEFAULT 0x000000f7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_6_TXQ_PAUSE_THD_DEFAULT 0x000000ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 - WAN/IMP1 Port Queue N Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_QN_Port_7_TXQ_PAUSE_THD_DEFAULT 0x00000107
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_0_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_1_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_2_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_3_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_4_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_5_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 - WAN/IMP1 Port Queue N DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_QN_Port_7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_0_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_1_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_2_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_3_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_4_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_5_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_6_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 - WAN/IMP1 Port Queue N Total Hysteresis Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_QN_Port_7_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_0_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_1_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_2_TOTAL_PAUSE_THD_DEFAULT 0x00000457
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_3_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_4_TOTAL_PAUSE_THD_DEFAULT 0x00000467
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_5_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_6_TOTAL_PAUSE_THD_DEFAULT 0x00000477
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 - WAN/IMP1 Port Queue N Total Pause Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_QN_Port_7_TOTAL_PAUSE_THD_DEFAULT 0x0000047f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_0_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_1_TOTAL_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_2_TOTAL_DROP_THD_DEFAULT 0x000005d7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_3_TOTAL_DROP_THD_DEFAULT 0x000005df
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_4_TOTAL_DROP_THD_DEFAULT 0x000005e7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_5_TOTAL_DROP_THD_DEFAULT 0x000005ef
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_6_TOTAL_DROP_THD_DEFAULT 0x000005f7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 - WAN/IMP1 Port Queue N Total DROP Threshold RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_QN_Port_7_TOTAL_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: FC_WAN_IMP1_REG_SPARE0 [15:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_WAN_IMP1_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: FC_WAN_IMP1_REG_SPARE1 [15:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEMP_MON_CTL - Temperature Monitor Control Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: TEMP_MON_CTL :: BIAS_ADJUST [07:01] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_MASK             0x000000fe
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_SHIFT            1
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_CTL :: ADC_TEST_EN [00:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_MASK             0x00000001
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_SHIFT            0
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_DEFAULT          0x00000001
+
+/***************************************************************************
+ *TEMP_MON_RESU - Temperature Monitor Result Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TEMP_MON_RESU :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_RESU :: TEMP_DATA [08:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_DEFAULT           0x000001ff
+
+/***************************************************************************
+ *PEAK_TEMP_MON_RESU - Peak Temperature Monitor Result Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: PEAK_TEMP_DATA [08:00] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_SHIFT   0
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *TEMP_MON_CAL - Temperature Monitor Calibration Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_CAL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: TEMP_MON_CAL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_CAL :: TEMP_DATA_25C [08:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_SHIFT          0
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_DEFAULT        0x0000015a
+
+/***************************************************************************
+ *TEMP_MON_SPEC_CTL - Temperature Monitor Special Control Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_MASK        0x000000fe
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_SHIFT       1
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: TEMP_PWRDN [00:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_MASK         0x00000001
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_SHIFT        0
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxOctets_P0 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P0 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P0 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P0 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P0 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P0 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P0 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P0 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P0 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P0 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P0 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P0 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P0 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P0 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P0 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P0 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P0 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P0 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P0 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P0 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P0 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P0 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P0 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P0 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P0 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P0 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P0 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P0 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P0 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P0 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P0 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P0 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P0 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P0 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P0 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P0 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P0 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P0 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P0 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P0 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P0 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P0 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P0 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P0 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P0 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P0 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P0 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P0 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P0 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P0 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P0 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P0 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P0 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P0 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P1 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P1 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P1 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P1 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P1 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P1 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P1 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P1 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P1 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P1 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P1 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P1 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P1 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P1 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P1 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P1 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P1 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P1 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P1 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P1 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P1 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P1 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P1 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P1 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P1 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P1 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P1 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P1 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P1 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P1 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P1 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P1 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P1 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P1 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P1 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P1 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P1 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P1 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P1 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P1 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P1 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P1 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P1 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P1 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P1 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P1 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P1 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P1 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P1 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P1 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P1 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P1 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P1 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P1 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P2 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P2 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P2 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P2 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P2 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P2 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P2 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P2 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P2 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P2 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P2 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P2 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P2 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P2 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P2 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P2 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P2 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P2 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P2 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P2 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P2 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P2 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P2 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P2 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P2 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P2 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P2 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P2 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P2 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P2 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P2 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P2 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P2 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P2 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P2 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P2 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P2 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P2 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P2 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P2 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P2 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P2 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P2 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P2 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P2 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P2 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P2 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P2 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P2 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P2 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P2 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P2 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P2 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P2 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P3 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P3 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P3 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P3 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P3 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P3 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P3 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P3 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P3 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P3 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P3 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P3 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P3 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P3 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P3 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P3 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P3 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P3 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P3 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P3 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P3 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P3 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P3 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P3 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P3 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P3 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P3 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P3 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P3 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P3 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P3 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P3 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P3 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P3 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P3 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P3 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P3 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P3 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P3 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P3 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P3 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P3 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P3 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P3 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P3 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P3 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P3 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P3 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P3 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P3 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P3 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P3 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P3 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P3 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P4 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P4 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P4 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P4 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P4 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P4 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P4 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P4 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P4 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P4 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P4 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P4 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P4 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P4 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P4 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P4 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P4 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P4 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P4 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P4 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P4 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P4 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P4 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P4 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P4 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P4 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P4 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P4 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P4 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P4 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P4 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P4 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P4 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P4 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P4 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P4 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P4 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P4 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P4 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P4 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P4 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P4 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P4 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P4 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P4 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P4 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P4 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P4 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P4 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P4 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P4 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P4 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P4 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P4 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P5 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P5 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P5 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P5 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P5 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P5 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P5 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P5 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P5 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P5 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P5 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P5 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P5 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P5 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P5 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P5 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P5 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P5 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P5 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P5 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P5 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P5 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P5 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P5 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P5 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P5 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P5 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P5 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P5 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P5 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P5 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P5 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P5 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P5 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P5 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P5 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P5 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P5 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P5 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P5 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P5 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P5 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P5 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P5 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P5 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P5 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P5 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P5 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P5 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P5 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P5 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P5 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P5 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P5 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P7 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P7 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P7 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P7 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P7 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P7 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P7 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P7 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P7 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P7 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P7 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P7 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P7 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P7 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P7 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P7 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P7 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P7 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P7 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P7 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P7 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P7 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P7 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P7 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P7 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P7 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P7 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P7 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P7 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P7 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P7 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P7 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P7 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P7 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P7 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P7 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P7 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P7 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P7 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P7 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P7 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P7 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P7 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P7 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P7 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P7 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P7 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P7 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P7 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P7 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P7 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P7 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P7 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P7 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_IMP - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_MASK                   0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_DEFAULT                0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_IMP - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_IMP - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_IMP - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_IMP - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_IMP - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxCollisions_IMP - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_IMP - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_IMP - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_IMP - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxLateCollision_IMP - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_IMP - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_IMP - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPausePkts_IMP - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_IMP - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_IMP - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_IMP - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_IMP - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_IMP - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxOctets_IMP - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_MASK                   0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_DEFAULT                0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_IMP - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxPausePkts_IMP - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_IMP - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_IMP - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_IMP - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_IMP - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_IMP - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_SHIFT     0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_IMP - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT  0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_IMP - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxJabbers_IMP - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_IMP - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_IMP - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_IMP - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_IMP - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_IMP - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_IMP - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_IMP - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxSAChanges_IMP - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxFragments_IMP - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_IMP - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxSymblErr_IMP - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_IMP - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_IMP - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_IMP - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_IMP - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxDiscard_IMP - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_IMP - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_IMP - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_IMP - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_IMP - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_IMP - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_IMP - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_IMP - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_SHIFT     0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_IMP - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT  0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QOS_GLOBAL_CTRL - QOS Global Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P8_AGGREGATION_MODE [07:07] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_MASK  0x00000080
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_1 [06:05] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_MASK        0x00000060
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_SHIFT       5
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P5_AGGREGATION_MODE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_MASK  0x00000010
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_MASK        0x0000000f
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *QOS_1P_EN - QoS 802.1P Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_1P_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: QOS_1P_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: QOS_1P_EN :: QOS_1P_EN [08:00] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_SHIFT                 0
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *QOS_EN_DIFFSERV - QOS DiffServ Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: QOS_EN_DIFFSERV [08:00] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_0 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_0_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_1 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_1_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_2 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_2 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_2_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_3 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_3 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_3_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_4 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_4 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_4_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI0_Port_5 - Port N PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI0_Port_5 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI0_Port_5_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PCP2TC_DEI0 - Port 7 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI0_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *IMP_PCP2TC_DEI0 - Port 8 (IMP) PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_MASK          0xff000000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_SHIFT         24
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_MASK       0x00e00000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT      21
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_DEFAULT    0x00000007
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_MASK       0x001c0000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT      18
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_DEFAULT    0x00000006
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_MASK       0x00038000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT      15
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_DEFAULT    0x00000005
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_MASK       0x00007000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT      12
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_DEFAULT    0x00000004
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_MASK       0x00000e00
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT      9
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_DEFAULT    0x00000003
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_MASK       0x000001c0
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT      6
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_DEFAULT    0x00000002
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_MASK       0x00000038
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT      3
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_MASK       0x00000007
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT      0
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_DEFAULT    0x00000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP0 - DiffServ Priority Map 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP1 - DiffServ Priority Map 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP2 - DiffServ Priority Map 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP3 - DiffServ Priority Map 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *PID2TC - Port ID to TC Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PID2TC :: SWITCH_RESV [31:27] */
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_MASK                   0xf8000000
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_SHIFT                  27
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: PID2TC :: PID2TC [26:00] */
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_MASK                        0x07ffffff
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_SHIFT                       0
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_0 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_0 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_0_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_1 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_1 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_1_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_2 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_2 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_2_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_3 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_3 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_3_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_4 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_4 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_4_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_Port_5 - Port N TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_SHIFT        14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_7_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_MASK         0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_SHIFT        12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_6_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_MASK         0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_SHIFT        10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_5_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_MASK         0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_SHIFT        8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_4_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_MASK         0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_SHIFT        6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_3_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_MASK         0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_SHIFT        4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_MASK         0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_SHIFT        2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_Port_5 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_MASK         0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_SHIFT        0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_Port_5_TC_SEL_0_DEFAULT      0x00000000
+
+/***************************************************************************
+ *P7_TC_SEL_TABLE - Port 7 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: P7_TC_SEL_TABLE :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_P7_TC_SEL_TABLE_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *IMP_TC_SEL_TABLE - Port 8 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_MASK            0x0000c000
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_SHIFT           14
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_7_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_MASK            0x00003000
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_SHIFT           12
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_6_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_MASK            0x00000c00
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_SHIFT           10
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_5_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_MASK            0x00000300
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_SHIFT           8
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_4_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_MASK            0x000000c0
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_SHIFT           6
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_3_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_MASK            0x00000030
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_SHIFT           4
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_2_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_MASK            0x0000000c
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_SHIFT           2
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: IMP_TC_SEL_TABLE :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_MASK            0x00000003
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_SHIFT           0
+#define BCHP_SWITCH_CORE_IMP_TC_SEL_TABLE_TC_SEL_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU2COS_MAP - CPU to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CPU2COS_MAP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_MASK              0xfffc0000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_SHIFT             18
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: EXCPT_PRCS [17:15] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_MASK               0x00038000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_SHIFT              15
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_SNOOP [14:12] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_MASK               0x00007000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_SHIFT              12
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_TRMNT [11:09] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_MASK               0x00000e00
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_SHIFT              9
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: SW_FLD [08:06] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_MASK                   0x000001c0
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_SHIFT                  6
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: SA_LRN [05:03] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_MASK                   0x00000038
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_SHIFT                  3
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: MIRROR [02:00] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_MASK                   0x00000007
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_SHIFT                  0
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_0 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_0 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_0_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_1 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_1 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_1_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_2 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_2 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_2_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_3 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_3 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_3_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_4 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_4 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_4_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_TC2COS_MAP_Port_5 - Port N TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_MASK 0xff000000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_BCAST_DLF_DROP_TC_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_MASK   0x00e00000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_SHIFT  21
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT111_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_MASK   0x001c0000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_SHIFT  18
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT110_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_MASK   0x00038000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_SHIFT  15
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT101_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_MASK   0x00007000
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_SHIFT  12
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT100_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_MASK   0x00000e00
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_SHIFT  9
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT011_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_MASK   0x000001c0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_SHIFT  6
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT010_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_MASK   0x00000038
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_SHIFT  3
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT001_TO_QID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_TC2COS_MAP_Port_5 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_MASK   0x00000007
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_SHIFT  0
+#define BCHP_SWITCH_CORE_PN_TC2COS_MAP_Port_5_PRT000_TO_QID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_TC2COS_MAP - Port 7 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_TC2COS_MAP :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: P7_TC2COS_MAP :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_P7_TC2COS_MAP_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *IMP_TC2COS_MAP - Port 8 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK     0xff000000
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT    24
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_MASK         0x00e00000
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_SHIFT        21
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT111_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_SHIFT        18
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT110_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_MASK         0x00038000
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_SHIFT        15
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT101_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_MASK         0x00007000
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_SHIFT        12
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT100_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_MASK         0x00000e00
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_SHIFT        9
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT011_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_MASK         0x000001c0
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_SHIFT        6
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT010_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_MASK         0x00000038
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_SHIFT        3
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT001_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IMP_TC2COS_MAP :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_MASK         0x00000007
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_SHIFT        0
+#define BCHP_SWITCH_CORE_IMP_TC2COS_MAP_PRT000_TO_QID_DEFAULT      0x00000000
+
+/***************************************************************************
+ *QOS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_REG_SPARE0 :: QOS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *QOS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_REG_SPARE1 :: QOS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_0 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_0_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_1 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_1_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_2 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_2 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_2_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_3 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_3 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_3_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_4 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_4 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_4_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PCP2TC_DEI1_Port_5 - Port N PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_MASK    0xff000000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_SHIFT   24
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_MASK 0x00e00000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_SHIFT 21
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG111_PRI_MAP_DEFAULT 0x00000007
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_MASK 0x001c0000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG110_PRI_MAP_DEFAULT 0x00000006
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_MASK 0x00038000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG101_PRI_MAP_DEFAULT 0x00000005
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_MASK 0x00007000
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG100_PRI_MAP_DEFAULT 0x00000004
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_MASK 0x00000e00
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG011_PRI_MAP_DEFAULT 0x00000003
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_MASK 0x000001c0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG010_PRI_MAP_DEFAULT 0x00000002
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_MASK 0x00000038
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG001_PRI_MAP_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PCP2TC_DEI1_Port_5 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PCP2TC_DEI1_Port_5_TAG000_PRI_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PCP2TC_DEI1 - Port 7 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: P7_PCP2TC_DEI1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_P7_PCP2TC_DEI1_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *IMP_PCP2TC_DEI1 - Port 8 (IMP) PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_MASK          0xff000000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_SHIFT         24
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_MASK       0x00e00000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT      21
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_DEFAULT    0x00000007
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_MASK       0x001c0000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT      18
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_DEFAULT    0x00000006
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_MASK       0x00038000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT      15
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_DEFAULT    0x00000005
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_MASK       0x00007000
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT      12
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_DEFAULT    0x00000004
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_MASK       0x00000e00
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT      9
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_DEFAULT    0x00000003
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_MASK       0x000001c0
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT      6
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_DEFAULT    0x00000002
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_MASK       0x00000038
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT      3
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: IMP_PCP2TC_DEI1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_MASK       0x00000007
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT      0
+#define BCHP_SWITCH_CORE_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_0 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_0 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_0_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_1 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_1 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_1_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_2 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_2 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_2_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_3 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_3 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_3_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_4 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_4 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_4_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_Port_5 - PORT N VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_Port_5 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_Port_5_PORT_EGRESS_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_P7 - PORT 7 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_P7 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_SHIFT     0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_DEFAULT   0x000001ff
+
+/***************************************************************************
+ *PORT_VLAN_CTL_IMP - PORT 8 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_MASK        0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PORT_VLAN_CTL_IMP :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_MASK     0x000001ff
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_SHIFT    0
+#define BCHP_SWITCH_CORE_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_DEFAULT  0x000001ff
+
+/***************************************************************************
+ *VLAN_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_REG_SPARE0 :: VLAN_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_SHIFT     0
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *VLAN_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_REG_SPARE1 :: VLAN_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_SHIFT     0
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MAC_TRUNK_CTL - MAC Trunk Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_1 [07:04] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_MASK          0x000000f0
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_SHIFT         4
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: EN_TRUNK_LOCAL [03:03] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_MASK         0x00000008
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_SHIFT        3
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_0 [02:02] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_MASK          0x00000004
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_SHIFT         2
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: HASH_SEL [01:00] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_MASK               0x00000003
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_SHIFT              0
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *IMP0_GRP_CTL - IMP0 Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP0_GRP_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: IMP0_GRP_CTL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: IMP0_GRP_CTL :: IMP0_GRP_CTL [08:00] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_SHIFT           0
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_DEFAULT         0x00000100
+
+/***************************************************************************
+ *TRUNK_GRP_CTL_Port_0 - Trunk N Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_0 :: EN_TRUNK_GRP [08:00] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_0_EN_TRUNK_GRP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRUNK_GRP_CTL_Port_1 - Trunk N Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL_Port_1 :: EN_TRUNK_GRP [08:00] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL_Port_1_EN_TRUNK_GRP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRUNK_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_REG_SPARE0 :: TRUNK_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRUNK_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_REG_SPARE1 :: TRUNK_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL0 - 802.1Q VLAN Control 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_EN [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_MASK                   0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_SHIFT                  7
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_LEARN_MODE [06:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_MASK           0x00000060
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_SHIFT          5
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_DEFAULT        0x00000003
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_1 [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_MASK             0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_SHIFT            4
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1Q_VID [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_MASK             0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_SHIFT            3
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_0 [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_MASK             0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_SHIFT            2
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_OUTER [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_MASK       0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_SHIFT      1
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_INNER [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_MASK       0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_SHIFT      0
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_DEFAULT    0x00000001
+
+/***************************************************************************
+ *VLAN_CTRL1 - 802.1Q VLAN Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_3 [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_MASK             0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_SHIFT            7
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_UNTAG [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_MASK      0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_SHIFT     6
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_FWDMAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_MASK     0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_SHIFT    5
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_2 [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_MASK             0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_SHIFT            4
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_UNTAG [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_MASK        0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_SHIFT       3
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_FWDMAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_MASK       0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_SHIFT      2
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_1 [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_MASK             0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_DEFAULT          0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_0 [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_MASK             0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL2 - 802.1Q VLAN Control 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_MASK               0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_SHIFT              7
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_UNTAG_MAP [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_MASK    0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_SHIFT   6
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_V_FWDMAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_MASK     0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_SHIFT    5
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_2 [04:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_MASK             0x00000018
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_SHIFT            3
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_MIIM_BYPASS_V_FWDMAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_MASK   0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_SHIFT  2
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_0 [01:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL3 - 802.1Q VLAN Control 3 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_MASK     0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_SHIFT    16
+
+/* SWITCH_CORE :: VLAN_CTRL3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_MASK               0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_SHIFT              9
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL3 :: EN_DROP_NON1Q [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_MASK             0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL4 - 802.1Q VLAN Control 4 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: INGR_VID_CHK [07:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_MASK              0x000000c0
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_SHIFT             6
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_DEFAULT           0x00000003
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GVRP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_MASK           0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_SHIFT          5
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GMRP [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_MASK           0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_SHIFT          4
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_DOUBLE_TAG [03:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_SHIFT            2
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: RESV_MCAST_FLOOD [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_MASK          0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_SHIFT         1
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: SWITCH_RESV_1 [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_MASK             0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL5 - 802.1Q VLAN Control 5 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_2 [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_MASK             0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_SHIFT            7
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: PRESV_NON1Q [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_MASK               0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_SHIFT              6
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_1 [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_MASK             0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_SHIFT            5
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EGRESS_DIR_FRM_BYPASS_TRUNK_EN [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: DROP_VTABLE_MISS [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_MASK          0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_SHIFT         3
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EN_VID_FFF_FWD [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_MASK            0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_SHIFT           2
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_0 [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_MASK             0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EN_CPU_RX_BYP_INNER_CRCCHK [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_MASK 0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_SHIFT 0
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL6 - 802.1Q VLAN Control 6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_1 [07:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_MASK             0x000000e0
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_SHIFT            5
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: DIS_ARL_BUST_LMT [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_MASK          0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_SHIFT         4
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_0 [03:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_MASK             0x0000000e
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: STRICT_SFD_DETECT [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_MASK         0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_SHIFT        0
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *VLAN_MULTI_PORT_ADDR_CTL - VLAN Multiport Address Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_MASK 0x0000f000
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_SHIFT 12
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_UTG_MAP [11:11] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_MASK 0x00000800
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_SHIFT 11
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_V_FWD_MAP [10:10] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_MASK 0x00000400
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_SHIFT 10
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_UTG_MAP [09:09] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_MASK 0x00000200
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_V_FWD_MAP [08:08] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_MASK 0x00000100
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_SHIFT 8
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_UTG_MAP [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_MASK 0x00000080
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_SHIFT 7
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_V_FWD_MAP [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_MASK 0x00000040
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_UTG_MAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_MASK 0x00000020
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_SHIFT 5
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_V_FWD_MAP [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_MASK 0x00000010
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_SHIFT 4
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_UTG_MAP [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_MASK 0x00000008
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_V_FWD_MAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_MASK 0x00000004
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_SHIFT 2
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_UTG_MAP [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_MASK 0x00000002
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_SHIFT 1
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_V_FWD_MAP [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_MASK 0x00000001
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_0 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_0 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_0_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_1 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_1 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_1_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_2 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_2 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_2_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_3 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_3 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_3_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_4 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_4 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_4_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_Port_5 - Port N 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_MASK            0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_SHIFT           13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_PRI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_MASK            0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_SHIFT           12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_CFI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_Port_5 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_SHIFT           0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_Port_5_VID_DEFAULT         0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P7 - Port 7 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_IMP - Port 8 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_MASK               0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_SHIFT              13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_MASK               0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_SHIFT              12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_MASK               0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_SHIFT              0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_DEFAULT            0x00000001
+
+/***************************************************************************
+ *DTAG_TPID - Double Tagging TPID Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DTAG_TPID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: DTAG_TPID :: ISP_TPID [15:00] */
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_MASK                   0x0000ffff
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_SHIFT                  0
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_DEFAULT                0x000088a8
+
+/***************************************************************************
+ *ISP_SEL_PORTMAP - ISP Port Selection Portmap Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: ISP_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_SHIFT         0
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_DEFAULT       0x00000000
+
+/***************************************************************************
+ *EGRESS_VID_RMK_TBL_ACS - Egress VID Remarking Table Access Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: GLOBAL_WR_EN [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_MASK  0x80000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV1 [30:16] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_MASK  0x7fff0000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: TBL_ADDR [15:08] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_MASK      0x0000ff00
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_SHIFT     8
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: EGRESS_PORT [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_MASK   0x000000f0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_SHIFT  4
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV2 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_MASK  0x00000008
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: RESET_EVT [02:02] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_MASK     0x00000004
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_SHIFT    2
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: OP [01:01] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_MASK            0x00000002
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_SHIFT           1
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: START_DONE [00:00] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_MASK    0x00000001
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_SHIFT   0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_VID_RMK_TBL_DATA - Egress VID Remarking Table Data Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV1 [31:30] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_MASK 0xc0000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_SHIFT 30
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_OP [29:28] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_MASK     0x30000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_SHIFT    28
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_VID [27:16] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_MASK    0x0fff0000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_SHIFT   16
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV2 [15:14] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_SHIFT 14
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_OP [13:12] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_MASK     0x00003000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_SHIFT    12
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_VID [11:00] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_MASK    0x00000fff
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_SHIFT   0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *JOIN_ALL_VLAN_EN - Join All VLAN Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: JOIN_ALL_VLAN_EN [08:00] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_SHIFT   0
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_IVL_SVL_CTRL - Port IVL or SVL Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_EN [15:15] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_MASK    0x00008000
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_SHIFT   15
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: SWITCH_RESV [14:09] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_MASK        0x00007e00
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_SEL [08:00] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_MASK   0x000001ff
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM8021Q_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BCM8021Q_REG_SPARE0 :: BCM8021Q_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM8021Q_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BCM8021Q_REG_SPARE1 :: BCM8021Q_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DOS_CTRL - DoS Control RegisterRegister
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_1 [31:14] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_MASK               0xffffc000
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_SHIFT              14
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_LONG_PING_DROP_EN [13:13] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_MASK    0x00002000
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_SHIFT   13
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_LONG_PING_DROP_EN [12:12] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_MASK    0x00001000
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_SHIFT   12
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_FRAGMENT_DROP_EN [11:11] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_MASK     0x00000800
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_SHIFT    11
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_FRAGMENT_DROP_EN [10:10] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_MASK     0x00000400
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_SHIFT    10
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_FRAG_ERR_DROP_EN [09:09] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_MASK        0x00000200
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_SHIFT       9
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SHORT_HDR_DROP_EN [08:08] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_MASK       0x00000100
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_SHIFT      8
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SYN_ERR_DROP_EN [07:07] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_MASK         0x00000080
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_SHIFT        7
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SYNFIN_SCAN_DROP_EN [06:06] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_MASK     0x00000040
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_SHIFT    6
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_XMASS_SCAN_DROP_EN [05:05] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_MASK      0x00000020
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_SHIFT     5
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_NULL_SCAN_DROP_EN [04:04] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_MASK       0x00000010
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_SHIFT      4
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: UDP_BLAT_DROP_EN [03:03] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_SHIFT           3
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_BLAT_DROP_EN [02:02] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_MASK            0x00000004
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_SHIFT           2
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: IP_LAND_DROP_EN [01:01] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_MASK             0x00000002
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_SHIFT            1
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_0 [00:00] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_MASK               0x00000001
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_SHIFT              0
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_DEFAULT            0x00000001
+
+/***************************************************************************
+ *MINIMUM_TCP_HDR_SZ - Minimum TCP Header Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: MIN_TCP_HDR_SZ [07:00] */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_MASK    0x000000ff
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_SHIFT   0
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MAX_ICMPV4_SIZE_REG - Maximum ICMPv4 Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAX_ICMPV4_SIZE_REG :: MAX_ICMPV4_SIZE [31:00] */
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_SHIFT 0
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_DEFAULT 0x00000200
+
+/***************************************************************************
+ *MAX_ICMPV6_SIZE_REG - Maximum ICMPv6 Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAX_ICMPV6_SIZE_REG :: MAX_ICMPV6_SIZE [31:00] */
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_SHIFT 0
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_DEFAULT 0x00000200
+
+/***************************************************************************
+ *DOS_DIS_LRN_REG - DoS Disable Learn Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_MASK          0x000000fe
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_SHIFT         1
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: DOS_DIS_LRN [00:00] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_MASK          0x00000001
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_SHIFT         0
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DOS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_REG_SPARE0 :: DOS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DOS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_REG_SPARE1 :: DOS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *JUMBO_PORT_MASK - Jumbo Frame Port Mask Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_MASK        0xfe000000
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_SHIFT       25
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: EN_10_100_JUMBO [24:24] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_MASK      0x01000000
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_SHIFT     24
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_0 [23:09] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_MASK        0x00fffe00
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_SHIFT       9
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: JUMBO_FM_PORT_MASK [08:00] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_MASK   0x000001ff
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_SHIFT  0
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MIB_GD_FM_MAX_SIZE - Jumbo MIB Good Frame Max Size Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: SWITCH_RESV [15:14] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_MASK       0x0000c000
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_SHIFT      14
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: MAX_SIZE [13:00] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_MASK          0x00003fff
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_SHIFT         0
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_DEFAULT       0x000007d0
+
+/***************************************************************************
+ *JUMBO_CTRL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE0 :: JUMBO_CTRL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *JUMBO_CTRL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE1 :: JUMBO_CTRL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *COMM_IRC_CON - Common Ingress rate Control Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_2 [31:18] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_MASK           0xfffc0000
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_SHIFT          18
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE1 [17:17] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_MASK              0x00020000
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_SHIFT             17
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_1 [16:09] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_MASK           0x0001fe00
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_SHIFT          9
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE0 [08:08] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_MASK              0x00000100
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_SHIFT             8
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_0 [07:00] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_MASK           0x000000ff
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_SHIFT          0
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *IRC_VIRTUAL_ZERO_THD - Ingress Rate Control Virtual Zero Threshold Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: IRC_VIRTUAL_ZERO_THD [15:00] */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_DEFAULT 0x00002fff
+
+/***************************************************************************
+ *IRC_ALARM_THD - Ingress Rate Control Alarm Threshold Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IRC_ALARM_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IRC_ALARM_THD :: IRC_ALARM_THD [15:00] */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_MASK          0x0000ffff
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_DEFAULT       0x00000bff
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_0 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_0 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_0_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_1 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_1 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_1_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_2 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_2 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_2_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_3 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_3 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_3_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_4 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_4 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_4_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P_Port_5 - Port N Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_MASK 0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_SHIFT 31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_MASK 0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_SHIFT 30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE1_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_MASK 0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_SHIFT 29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET_MODE0_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_MASK 0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_SHIFT 24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_MASK  0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_SHIFT 23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_MASK  0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_SHIFT 22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_EN_BUCKET0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_MASK 0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_SHIFT 19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_MASK 0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_MASK 0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_SIZE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P_Port_5 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P_Port_5_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P7 - Port 7 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_IMP - Port 8 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_MASK    0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_SHIFT   31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_MASK     0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_SHIFT    30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_DEFAULT  0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_MASK     0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_SHIFT    29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_DEFAULT  0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_MASK    0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_SHIFT   24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_MASK       0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_SHIFT      23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_MASK       0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_SHIFT      22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_MASK     0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_SHIFT    19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_MASK  0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_MASK     0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_SHIFT    8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_MASK  0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_0 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_0 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_0_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_1 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_1 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_1_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_2 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_2 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_2_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_3 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_3 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_3_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_4 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_4 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_4_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P_Port_5 - Port N Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_SHIFT 15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_MASK  0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_SHIFT 8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_MASK 0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_SHIFT 7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_IFG_BYTES0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P_Port_5 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_MASK  0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P_Port_5_PKT_MSK0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P7 - Port 7 Receive Rate Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_IMP - Port 8 Receive Rate Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_MASK     0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_SHIFT    15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_MASK       0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_SHIFT      8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_MASK     0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_SHIFT    7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_MASK       0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_SHIFT      0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_DEFAULT    0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_0 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_0 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_0_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_1 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_1 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_1_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_2 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_2 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_2_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_3 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_3 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_3_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_4 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_4 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_4_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P_Port_5 - Port N Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P_Port_5 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P_Port_5_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P7 - Port 7 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P7 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_IMP - Port 8 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_IMP :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUPPRESS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE0 :: BC_SUPPRESS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUPPRESS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE1 :: BC_SUPPRESS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EAP_GLO_CON - EAP Global Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_GLO_CON :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV_0 [07:07] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_MASK            0x00000080
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_SHIFT           7
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_RARP [06:06] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_MASK                  0x00000040
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_SHIFT                 6
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_BPDU [05:05] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_MASK                  0x00000020
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_SHIFT                 5
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_RMC [04:04] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_MASK                   0x00000010
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_SHIFT                  4
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_DHCP [03:03] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_MASK                  0x00000008
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_SHIFT                 3
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_ARP [02:02] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_MASK                   0x00000004
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_SHIFT                  2
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_2_DIP [01:01] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_SHIFT                1
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV [00:00] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_MASK              0x00000001
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *EAP_MULTI_ADDR_CTRL - EAP Multiport Address Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: SWITCH_RESV [07:06] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_MASK      0x000000c0
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_SHIFT     6
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT5 [05:05] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_MASK        0x00000020
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_SHIFT       5
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT4 [04:04] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_MASK        0x00000010
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_SHIFT       4
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT3 [03:03] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_MASK        0x00000008
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_SHIFT       3
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT2 [02:02] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_MASK        0x00000004
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_SHIFT       2
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT1 [01:01] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_MASK        0x00000002
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_SHIFT       1
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT0 [00:00] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_MASK        0x00000001
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_SHIFT       0
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *EAP_DIP_Port_0 - EAP Destination IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_DIP_Port_0 :: DIP_SUB_REG [63:32] */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_MASK           0xffffffff00000000
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_SHIFT          32
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_SUB_REG_DEFAULT        0x0000000000000000
+
+/* SWITCH_CORE :: EAP_DIP_Port_0 :: DIP_MASK_REG [31:00] */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_MASK          0x00000000ffffffff
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_SHIFT         0
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_0_DIP_MASK_REG_DEFAULT       0x0000000000000000
+
+/***************************************************************************
+ *EAP_DIP_Port_1 - EAP Destination IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_DIP_Port_1 :: DIP_SUB_REG [63:32] */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_MASK           0xffffffff00000000
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_SHIFT          32
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_SUB_REG_DEFAULT        0x0000000000000000
+
+/* SWITCH_CORE :: EAP_DIP_Port_1 :: DIP_MASK_REG [31:00] */
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_MASK          0x00000000ffffffff
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_SHIFT         0
+#define BCHP_SWITCH_CORE_EAP_DIP_Port_1_DIP_MASK_REG_DEFAULT       0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_0 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_0 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_0_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_1 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_1 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_1_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_2 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_2 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_2_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_3 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_3 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_3_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_4 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_4 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_4_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_Port_5 - Port N EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_MASK      0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_SHIFT     53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_SWITCH_RESV_DEFAULT   0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_MASK         0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_SHIFT        51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_MASK     0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_SHIFT    49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_BLK_MODE_DEFAULT  0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_MASK    0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_SHIFT   48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_Port_5 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_Port_5_EAP_UNI_DA_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_P7 - Port 7 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_P7 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_MASK          0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_SHIFT         53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_SWITCH_RESV_DEFAULT       0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_MASK             0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_SHIFT            51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_MODE_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_MASK         0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_SHIFT        49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_BLK_MODE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_MASK        0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_SHIFT       48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_EN_UNI_DA_DEFAULT     0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_P7 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_SHIFT          0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_P7_EAP_UNI_DA_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *PORT_EAP_CON_IMP - IMP EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EAP_CON_IMP :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_MASK         0xffe0000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_SHIFT        53
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_SWITCH_RESV_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_MASK            0x0018000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_SHIFT           51
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_MODE_DEFAULT         0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_MASK        0x0006000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_SHIFT       49
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_BLK_MODE_DEFAULT     0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_MASK       0x0001000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_SHIFT      48
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: PORT_EAP_CON_IMP :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_MASK          0x0000000000000000
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_SHIFT         0
+#define BCHP_SWITCH_CORE_PORT_EAP_CON_IMP_EAP_UNI_DA_DEFAULT       0x0000000000000000
+
+/***************************************************************************
+ *IEEE8021X_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021X_REG_SPARE0 :: IEEE8021X_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021X_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021X_REG_SPARE1 :: IEEE8021X_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MST_CON - MST Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_CON :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: MST_CON :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_MASK                  0x000000fe
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_SHIFT                 1
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MST_CON :: EN_802_1S [00:00] */
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_AGE - MST Ageing Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_AGE :: SWITCH_RESV [31:08] */
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_MASK                  0xffffff00
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_SHIFT                 8
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MST_AGE :: AGE_EN_PRT [07:00] */
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_MASK                   0x000000ff
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_SHIFT                  0
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_0 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_0 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_0 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_0_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_1 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_1 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_1 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_1_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_2 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_2 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_2 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_2_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_3 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_3 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_3 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_3_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_4 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_4 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_4 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_4_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_5 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_5 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_5 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_5_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_6 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_6 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_6 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_6_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *MST_TAB_Port_7 - MST Table N Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB_Port_7 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_MASK          0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_SHIFT         27
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_MST_TAB_RSRV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_MASK         0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_SHIFT        24
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_MASK              0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_SHIFT             21
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA7_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_SHIFT        18
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_MASK              0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_SHIFT             15
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_MASK              0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_SHIFT             12
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_MASK              0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_SHIFT             9
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_MASK              0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_SHIFT             6
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_MASK              0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_SHIFT             3
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MST_TAB_Port_7 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_MASK              0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_SHIFT             0
+#define BCHP_SWITCH_CORE_MST_TAB_Port_7_SPT_STA0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPT_MULTI_ADDR_BPS_CTRL - STP Multiport Address Bypass Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: SWITCH_RESV [15:06] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_MASK  0x0000ffc0
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_SHIFT 6
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT5_BYPASS_SPT [05:05] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_MASK 0x00000020
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_SHIFT 5
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT4_BYPASS_SPT [04:04] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_MASK 0x00000010
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_SHIFT 4
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT3_BYPASS_SPT [03:03] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_MASK 0x00000008
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_SHIFT 3
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT2_BYPASS_SPT [02:02] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_MASK 0x00000004
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_SHIFT 2
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT1_BYPASS_SPT [01:01] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_MASK 0x00000002
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_SHIFT 1
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT0_BYPASS_SPT [00:00] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_MASK 0x00000001
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_SHIFT 0
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021S_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021S_REG_SPARE0 :: IEEE8021S_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021S_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021S_REG_SPARE1 :: IEEE8021S_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_LIMIT_ENABLE - SA Limit Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SA_LIMIT_EN [08:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_SHIFT         0
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_RST - SA Learned Counters Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: TOTAL_SA_LRN_CNTR_RST [15:15] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_MASK 0x00008000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_SHIFT 15
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: SWITCH_RESV [14:09] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_MASK          0x00007e00
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: PORT_SA_LRN_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_RST - SA Over Limit Counters Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_MASK    0x0000fe00
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_SHIFT   9
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: PORT_SA_OVER_LIMIT_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TOTAL_SA_LIMIT_CTL - Total SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: TOTAL_SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_DEFAULT 0x00001000
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_0 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_0 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_0_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_1 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_1 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_1_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_2 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_2 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_2_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_3 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_3 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_3_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_4 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_4 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_4_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_N_SA_LIMIT_CTL_Port_5 - Port N SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_MASK 0x00002000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LIMIT_CTL_Port_5 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LIMIT_CTL_Port_5_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_7_SA_LIMIT_CTL - Port 7 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_MASK      0x00002000
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_SHIFT     13
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: PORT_7_SA_LIMIT_CTL :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK   0x00001fff
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT  0
+#define BCHP_SWITCH_CORE_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *PORT_8_SA_LIMIT_CTL - Port 8 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_MASK      0x00002000
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_SHIFT     13
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: PORT_8_SA_LIMIT_CTL :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK   0x00001fff
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT  0
+#define BCHP_SWITCH_CORE_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_DEFAULT 0x00000400
+
+/***************************************************************************
+ *TOTAL_SA_LRN_CNTR - Total SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_MASK        0x0000e000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_SHIFT       13
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: TOTAL_SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_0 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_0 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_0_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_1 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_1 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_1_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_2 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_2 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_2_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_3 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_3 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_3_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_4 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_4 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_4_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_LRN_CNTR_Port_5 - Port N SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_MASK 0x0000e000
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_SHIFT 13
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_N_SA_LRN_CNTR_Port_5 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_LRN_CNTR_Port_5_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_7_SA_LRN_CNTR - Port 7 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_7_SA_LRN_CNTR :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK     0x00001fff
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT    0
+#define BCHP_SWITCH_CORE_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PORT_8_SA_LRN_CNTR - Port 8 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_8_SA_LRN_CNTR :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK     0x00001fff
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT    0
+#define BCHP_SWITCH_CORE_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_0 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_0 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_0_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_1 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_1 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_1_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_2 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_2 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_2_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_3 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_3 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_3_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_4 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_4 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_4_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_N_SA_OVERLIMIT_CNTR_Port_5 - Port N SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_N_SA_OVERLIMIT_CNTR_Port_5 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_N_SA_OVERLIMIT_CNTR_Port_5_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_7_SA_OVERLIMIT_CNTR - Port 7 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_7_SA_OVERLIMIT_CNTR :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_8_SA_OVERLIMIT_CNTR - Port 8 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_8_SA_OVERLIMIT_CNTR :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVER_LIMIT_COPY_REDIRECT - SA Over Limit Actions Config Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: SWITCH_RESV [15:04] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_MASK 0x0000fff0
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_SHIFT 4
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: COPY_REDIRECT_PORT_ID [03:00] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MAC_LIMIT_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE0 :: MAC_LIMIT_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MAC_LIMIT_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE1 :: MAC_LIMIT_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_0 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_0 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_0_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_1 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_1 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_1_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_2 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_2 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_2_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_3 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_3 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_3_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_4 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_4 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_4_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QOS_PRI_CTL_Port_5 - Port N, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_MASK    0x00000040
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_SHIFT   6
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_MASK 0x00000008
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_WDRR_GRANULARITY_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QOS_PRI_CTL_Port_5 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_MASK 0x00000007
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QOS_PRI_CTL_Port_5_SCHEDULER_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QOS_PRI_CTL - Port 7, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: P7_QOS_PRI_CTL :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QOS_PRI_CTL_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QOS_PRI_CTL - Port 8, QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_MASK          0x00000040
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_SHIFT         6
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_MASK     0x00000008
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT    3
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: IMP_QOS_PRI_CTL :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_MASK     0x00000007
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_0 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_0 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_0_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_1 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_1 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_1_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_2 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_2 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_2_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_3 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_3 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_3_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_4 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_4 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_4_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *PN_QOS_WEIGHT_Port_5 - Port N, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_MASK       0xff00000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_SHIFT      56
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q7_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_MASK       0x00ff000000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_SHIFT      48
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q6_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_MASK       0x0000ff0000000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_SHIFT      40
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q5_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_MASK       0x000000ff00000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_SHIFT      32
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q4_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_MASK       0x00000000ff000000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_SHIFT      24
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q3_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_MASK       0x0000000000ff0000
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_SHIFT      16
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q2_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_MASK       0x000000000000ff00
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_SHIFT      8
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q1_WEIGHT_DEFAULT    0x0000000000000001
+
+/* SWITCH_CORE :: PN_QOS_WEIGHT_Port_5 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_MASK       0x00000000000000ff
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_SHIFT      0
+#define BCHP_SWITCH_CORE_PN_QOS_WEIGHT_Port_5_Q0_WEIGHT_DEFAULT    0x0000000000000001
+
+/***************************************************************************
+ *P7_QOS_WEIGHT - Port 7, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: P7_QOS_WEIGHT :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_P7_QOS_WEIGHT_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *IMP_QOS_WEIGHT - Port 8, QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_MASK             0xff00000000000000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_SHIFT            56
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q7_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_MASK             0x00ff000000000000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_SHIFT            48
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q6_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_MASK             0x0000ff0000000000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_SHIFT            40
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q5_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_MASK             0x000000ff00000000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_SHIFT            32
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q4_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_MASK             0x00000000ff000000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_SHIFT            24
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q3_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_MASK             0x0000000000ff0000
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_SHIFT            16
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q2_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_MASK             0x000000000000ff00
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_SHIFT            8
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q1_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: IMP_QOS_WEIGHT :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_MASK             0x00000000000000ff
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_SHIFT            0
+#define BCHP_SWITCH_CORE_IMP_QOS_WEIGHT_Q0_WEIGHT_DEFAULT          0x0000000000000001
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_0 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_0 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_0_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_1 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_1 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_1_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_2 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_2 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_2_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_3 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_3 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_3_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_4 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_4 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_4_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_WDRR_PENALTY_Port_5 - Port N, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_WDRR_PENALTY_Port_5 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_WDRR_PENALTY_Port_5_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_WDRR_PENALTY - Port 7, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_WDRR_PENALTY :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: P7_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P8_WDRR_PENALTY - Port 8, WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCHEDULER_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SCHEDULER_REG_SPARE0 :: SCHEDULER_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCHEDULER_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SCHEDULER_REG_SPARE1 :: SCHEDULER_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 - Port N, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH - Port 7, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH - Port 8, Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 - Port N, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL - Port 7, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL - Port 8, Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_0 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_1 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_2 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_3 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_4 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_STS_Port_5 - Port N, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_SHAPER_STS - Port 7, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_STS_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *IMP_PORT_SHAPER_STS - Port 8, PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK  0x80000000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_MASK      0x60000000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_SHIFT     29
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_MASK       0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_STS_BUCKET_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 - Port N, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH - Port 7, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH - Port 8, Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_CTLREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE0 :: EGRESS_SHAPER_CTLREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_CTLREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE1 :: EGRESS_SHAPER_CTLREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 - Port N, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL - Port 7, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL - Port 8, Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_AVB_SHAPING_MODE - Port Shaper AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: PORT_SHAPER_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_ENABLE - Port Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: PORT_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BUCKET_COUNT_SELECT - Port Shaper Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: PORT_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BLOCKING - Port Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: PORT_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IFG_BYTES - IFG Correction Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IFG_BYTES :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: IFG_BYTES :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: IFG_BYTES :: IFG_BYTES [08:00] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_SHIFT                 0
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE0_MAX_REFRESH - Port 7, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE0_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE0_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE0_MAX_REFRESH - Port 8, Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE0_MAX_THD_SEL - Port 7, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE0_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE0_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE0_MAX_THD_SEL - Port 8, Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_0 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_1 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_2 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_3 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_4 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_SHAPER_STS_Port_5 - Port N, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE0_SHAPER_STS - Port 7, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE0_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE0_SHAPER_STS - Port 8, Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE0_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE0_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE0_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE0_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE0_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE0_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE0_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE0_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_AVB_SHAPING_MODE - Queue 0 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: QUEUE0_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_ENABLE - Queue 0 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: QUEUE0_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_BUCKET_COUNT_SELECT - Queue 0 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_BLOCKING - Queue 0 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: QUEUE0_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE1_MAX_REFRESH - Port 7, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE1_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE1_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE1_MAX_REFRESH - Port 8, Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE1_MAX_THD_SEL - Port 7, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE1_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE1_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE1_MAX_THD_SEL - Port 8, Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_0 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_1 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_2 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_3 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_4 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_SHAPER_STS_Port_5 - Port N, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE1_SHAPER_STS - Port 7, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE1_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE1_SHAPER_STS - Port 8, Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE1_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE1_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE1_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE1_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE1_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE1_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE1_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE1_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_AVB_SHAPING_MODE - Queue 1 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: QUEUE1_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_ENABLE - Queue 1 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: QUEUE1_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_BUCKET_COUNT_SELECT - Queue 1 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_BLOCKING - Queue 1 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: QUEUE1_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE2_MAX_REFRESH - Port 7, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE2_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE2_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE2_MAX_REFRESH - Port 8, Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE2_MAX_THD_SEL - Port 7, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE2_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE2_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE2_MAX_THD_SEL - Port 8, Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_0 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_1 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_2 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_3 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_4 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_SHAPER_STS_Port_5 - Port N, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE2_SHAPER_STS - Port 7, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE2_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE2_SHAPER_STS - Port 8, Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE2_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE2_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE2_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE2_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE2_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE2_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE2_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE2_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_AVB_SHAPING_MODE - Queue 2 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: QUEUE2_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_ENABLE - Queue 2 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: QUEUE2_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_BUCKET_COUNT_SELECT - Queue 2 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_BLOCKING - Queue 2 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: QUEUE2_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE3_MAX_REFRESH - Port 7, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE3_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE3_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE3_MAX_REFRESH - Port 8, Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE3_MAX_THD_SEL - Port 7, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE3_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE3_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE3_MAX_THD_SEL - Port 8, Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_0 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_1 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_2 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_3 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_4 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_SHAPER_STS_Port_5 - Port N, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE3_SHAPER_STS - Port 7, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE3_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE3_SHAPER_STS - Port 8, Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE3_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE3_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE3_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE3_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE3_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE3_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE3_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE3_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_AVB_SHAPING_MODE - Queue 3 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: QUEUE3_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_ENABLE - Queue 3 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: QUEUE3_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_BUCKET_COUNT_SELECT - Queue 3 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_BLOCKING - Queue 3 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: QUEUE3_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE4_MAX_REFRESH - Port 7, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE4_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE4_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE4_MAX_REFRESH - Port 8, Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE4_MAX_THD_SEL - Port 7, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE4_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE4_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE4_MAX_THD_SEL - Port 8, Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_0 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_1 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_2 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_3 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_4 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_SHAPER_STS_Port_5 - Port N, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE4_SHAPER_STS - Port 7, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE4_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE4_SHAPER_STS - Port 8, Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE4_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE4_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE4_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE4_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE4_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE4_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE4_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE4_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_AVB_SHAPING_MODE - Queue 4 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: QUEUE4_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_ENABLE - Queue 4 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: QUEUE4_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_BUCKET_COUNT_SELECT - Queue 4 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_BLOCKING - Queue 4 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: QUEUE4_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE5_MAX_REFRESH - Port 7, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE5_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE5_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE5_MAX_REFRESH - Port 8, Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE5_MAX_THD_SEL - Port 7, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE5_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE5_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE5_MAX_THD_SEL - Port 8, Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_0 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_1 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_2 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_3 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_4 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_SHAPER_STS_Port_5 - Port N, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE5_SHAPER_STS - Port 7, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE5_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE5_SHAPER_STS - Port 8, Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE5_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE5_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE5_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE5_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE5_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE5_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE5_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE5_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_AVB_SHAPING_MODE - Queue 5 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: QUEUE5_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_ENABLE - Queue 5 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: QUEUE5_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_BUCKET_COUNT_SELECT - Queue 5 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_BLOCKING - Queue 5 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: QUEUE5_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE6_MAX_REFRESH - Port 7, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE6_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE6_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE6_MAX_REFRESH - Port 8, Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE6_MAX_THD_SEL - Port 7, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE6_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE6_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE6_MAX_THD_SEL - Port 8, Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_0 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_1 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_2 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_3 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_4 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_SHAPER_STS_Port_5 - Port N, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE6_SHAPER_STS - Port 7, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE6_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE6_SHAPER_STS - Port 8, Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE6_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE6_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE6_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE6_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE6_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE6_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE6_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE6_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_AVB_SHAPING_MODE - Queue 6 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: QUEUE6_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_ENABLE - Queue 6 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: QUEUE6_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_BUCKET_COUNT_SELECT - Queue 6 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_BLOCKING - Queue 6 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: QUEUE6_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_0 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_1 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_2 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_3 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_4 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_REFRESH_Port_5 - Port N, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE7_MAX_REFRESH - Port 7, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE7_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE7_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE7_MAX_REFRESH - Port 8, Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_0 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_1 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_2 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_3 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_4 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_THD_SEL_Port_5 - Port N, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE7_MAX_THD_SEL - Port 7, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE7_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE7_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE7_MAX_THD_SEL - Port 8, Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_0 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_0_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_1 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_1_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_2 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_2_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_3 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_3_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_4 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_4_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_SHAPER_STS_Port_5 - Port N, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_MASK 0x60000000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_SHIFT 29
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_SHAPER_STS_Port_5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_MASK 0x1fffffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_SHAPER_STS_Port_5_BUCKET_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE7_SHAPER_STS - Port 7, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE7_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE7_SHAPER_STS - Port 8, Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE7_SHAPER_STS :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 - Port N, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_REFRESH_Port_5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_REFRESH_Port_5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE7_MAX_PACKET_REFRESH - Port 7, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE7_MAX_PACKET_REFRESH - Port 8, Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_REFRESH :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_REFRESH :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 - Port N, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_QUEUE7_MAX_PACKET_THD_SEL_Port_5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_QUEUE7_MAX_PACKET_THD_SEL - Port 7, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P7_QUEUE7_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_QUEUE7_MAX_PACKET_THD_SEL - Port 8, Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_THD_SEL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: IMP_QUEUE7_MAX_PACKET_THD_SEL :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_AVB_SHAPING_MODE - Queue 7 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: QUEUE7_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_ENABLE - Queue 7 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: QUEUE7_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_BUCKET_COUNT_SELECT - Queue 7 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_BLOCKING - Queue 7 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: QUEUE7_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MIB_SNAPSHOT_CTL - MIB Snapshot Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_STDONE [07:07] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_MASK     0x00000080
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_SHIFT    7
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_MIRROR [06:06] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_MASK     0x00000040
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_SHIFT    6
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SWITCH_RESV [05:05] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_MASK         0x00000020
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_SHIFT        5
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: RST_MIB_SNAPSHOT_CNT_EN [04:04] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_PORT [03:00] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_SHIFT      0
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *S_TxOctets - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_MASK                     0x0000000000000000
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_DEFAULT                  0x0000000000000000
+
+/***************************************************************************
+ *S_TxDropPkts - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxDropPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ0 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxBroadcastPkts - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxBroadcastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxMulticastPkts - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxMulticastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxUnicastPkts - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxUnicastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_TxCollisions - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxCollisions :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *S_TxSingleCollision - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxSingleCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *S_TxMultipleCollision - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxMultipleCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_TxDeferredTransmit - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxDeferredTransmit :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *S_TxLateCollision - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxLateCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxExcessiveCollision - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxExcessiveCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxFrameInDisc - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxFrameInDisc :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_TxPausePkts - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPausePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ1 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ2 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ3 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ4 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ5 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_RxOctets - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_MASK                     0x0000000000000000
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_DEFAULT                  0x0000000000000000
+
+/***************************************************************************
+ *S_RxUndersizePkts - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxUndersizePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxPausePkts - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPausePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxPkts64Octets - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts64Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_RxPkts65to127Octets - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts65to127Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_RxPkts128to255Octets - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts128to255Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_RxPkts256to511Octets - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts256to511Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_RxPkts512to1023Octets - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts512to1023Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *S_RxPkts1024toMaxPktOctets - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts1024toMaxPktOctets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_MASK     0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_SHIFT    0
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *S_RxOversizePkts - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxOversizePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_RxJabbers - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxJabbers :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *S_RxAlignmentErrors - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxAlignmentErrors :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *S_RxFCSErrors - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxFCSErrors :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxGoodOctets - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxGoodOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_MASK                 0x0000000000000000
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_DEFAULT              0x0000000000000000
+
+/***************************************************************************
+ *S_RxDropPkts - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxDropPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_RxUnicastPkts - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxUnicastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_RxMulticastPkts - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxMulticastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxBroadcastPkts - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxBroadcastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxSAChanges - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxSAChanges :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxFragments - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxFragments :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxJumboPkt - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxJumboPkt :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_RxSymblErr - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxSymblErr :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_InRangeErrCount - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_InRangeErrCount :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_OutRangeErrCount - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_OutRangeErrCount :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *S_EEE_LPI_EVENT - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: S_EEE_LPI_EVENT :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_EEE_LPI_DURATION - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: S_EEE_LPI_DURATION :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *S_RxDiscard - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxDiscard :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ6 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ6 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ7 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxPkts64Octets - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts64Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_TxPkts65to127Octets - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts65to127Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_TxPkts128to255Octets - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts128to255Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxPkts256to511Octets - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts256to511Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxPkts512to1023Octets - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts512to1023Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *S_TxPkts1024toMaxPktOctets - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts1024toMaxPktOctets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_MASK     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_SHIFT    0
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *LPDET_CFG - Loop Detection Configuration RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: LPDET_CFG :: SWITCH_RESV [15:15] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_MASK                0x00008000
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_SHIFT               15
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL2 [14:14] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_MASK                   0x00004000
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_SHIFT                  14
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: EN_TXPASS [13:13] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_MASK                  0x00002000
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_SHIFT                 13
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: EN_LPDET [12:12] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_MASK                   0x00001000
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_SHIFT                  12
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: LOOP_IMP_SEL [11:11] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_MASK               0x00000800
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_SHIFT              11
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: LED_RST_CTL [10:03] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_MASK                0x000007f8
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_SHIFT               3
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_DEFAULT             0x00000004
+
+/* SWITCH_CORE :: LPDET_CFG :: OV_PAUSE_ON [02:02] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_MASK                0x00000004
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_SHIFT               2
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_DEFAULT             0x00000001
+
+/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL [01:00] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_MASK                    0x00000003
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_SHIFT                   0
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_DEFAULT                 0x00000001
+
+/***************************************************************************
+ *DF_TIMER - Discovery Frame Timer RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DF_TIMER :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: DF_TIMER :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_MASK                 0x000000f0
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_SHIFT                4
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: DF_TIMER :: DF_TIME [03:00] */
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_MASK                     0x0000000f
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_SHIFT                    0
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *LED_PORTMAP - LED Waming Portmap RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LED_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: LED_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LED_PORTMAP :: LED_WARNING_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_SHIFT     0
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MODULE_ID0 - Module ID 0 RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MODULE_ID0 :: MID_SA [47:00] */
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_MASK                    0x000000000000
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_SHIFT                   0
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_DEFAULT                 0x000000000000
+
+/***************************************************************************
+ *MODULE_ID1 - Module ID 1 RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MODULE_ID1 :: MID_AVAIL [47:47] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_MASK                 0x800000000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_SHIFT                47
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_DEFAULT              0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: SWITCH_RESV [46:40] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_MASK               0x7f0000000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_SHIFT              40
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_DEFAULT            0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: MID_PORTNUM [39:32] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_MASK               0x00ff00000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_SHIFT              32
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_DEFAULT            0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: MID_CRC [31:00] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_MASK                   0x0000ffffffff
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_SHIFT                  0
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_DEFAULT                0x000000000000
+
+/***************************************************************************
+ *LPDET_SA - Loop Detect Frame SA RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_SA :: LPDET_SA [47:00] */
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_MASK                    0x000000000000
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_SHIFT                   0
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_DEFAULT                 0x0180c2000001
+
+/***************************************************************************
+ *LPDET_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_REG_SPARE0 :: LPDET_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LPDET_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_REG_SPARE1 :: LPDET_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BPM_CTRL - BPM Power Switching Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: BPM_CTRL :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_MASK                 0x000000e0
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_SHIFT                5
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: RX_PORT_KEEP2PAGE [04:04] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_MASK           0x00000010
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_SHIFT          4
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PDA_CHG_OPT [03:03] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_SHIFT                3
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: BFCFIFO_RECYCLE_EN [02:02] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_MASK          0x00000004
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_SHIFT         2
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PTR_RECYCLE_EN [01:01] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_MASK              0x00000002
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_SHIFT             1
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PSM_SW_EN [00:00] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_MASK                   0x00000001
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_SHIFT                  0
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_DEFAULT                0x00000000
+
+/***************************************************************************
+ *BPM_PSM_OVR_CTRL - BPM Power Switching SW Override RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE_EN [07:07] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_MASK  0x00000080
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: SWITCH_RESV [06:03] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_MASK         0x00000078
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_SHIFT        3
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE [02:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_MASK     0x00000007
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_SHIFT    0
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *BPM_PSM_TIME_CFG - PSM_VDD Timing Parameter Configuration RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: DPSM_CNT [15:08] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_MASK            0x0000ff00
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_SHIFT           8
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_DEFAULT         0x00000017
+
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: MPSM_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_SHIFT           0
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_DEFAULT         0x00000002
+
+/***************************************************************************
+ *BPM_PSM_THD_CFG - PSM_VDD Switching Threshold Configuration RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_1 [31:28] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_MASK        0xf0000000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_SHIFT       28
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_ON_THD [27:16] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_MASK           0x0fff0000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_SHIFT          16
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_DEFAULT        0x00000027
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_0 [15:12] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_MASK        0x0000f000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_SHIFT       12
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_OFF_THD [11:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_MASK          0x00000fff
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_DEFAULT       0x00000050
+
+/***************************************************************************
+ *ROW_VMASK_OVR_CTRL - BUFCON Row Status Valid Mask SW Override Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_EN [15:15] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_MASK       0x00008000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_SHIFT      15
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: SWITCH_RESV [14:12] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_MASK       0x00007000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_SHIFT      12
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_VAL [11:00] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_MASK      0x00000fff
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_SHIFT     0
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_DEFAULT   0x00000fff
+
+/***************************************************************************
+ *BPM_STS - BPM Status RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_STS :: PBB_PWR_STS [31:29] */
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_MASK                  0xe0000000
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_SHIFT                 29
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_DEFAULT               0x00000007
+
+/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_1 [28:28] */
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_MASK                0x10000000
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_SHIFT               28
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: ROW_USE_STS [27:16] */
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_MASK                  0x0fff0000
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_SHIFT                 16
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_DEFAULT               0x00000001
+
+/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_0 [15:14] */
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_MASK                0x0000c000
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_SHIFT               14
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: CUR_PBB [13:12] */
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_MASK                      0x00003000
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_SHIFT                     12
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: ROW_VMASK [11:00] */
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_MASK                    0x00000fff
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_SHIFT                   0
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_DEFAULT                 0x00000fff
+
+/***************************************************************************
+ *BPM_PDA_OVR_CTRL - BPM PDA Switching SW Override Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_EN [15:15] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_MASK         0x00008000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_SHIFT        15
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_DONE [14:14] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_MASK       0x00004000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_SHIFT      14
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: SWITCH_RESV [13:12] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_MASK         0x00003000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_SHIFT        12
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_VAL [11:00] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_MASK        0x00000fff
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PDA_TIMEOUT_CFG - BPM PDA Switching Timeout Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: PDA_TIMEOUT_CNT [15:00] */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_MASK      0x0000ffff
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_DEFAULT   0x00000100
+
+/***************************************************************************
+ *PDA_SETUP_TIME_CFG - BPM PDA Switching Setup Time RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SETUP_TIME [10:00] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_SHIFT       0
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PDA_HOLD_TIME_CFG - BPM PDA Switching Hold Time RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: HOLD_TIME [10:00] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_SHIFT         0
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_DEFAULT       0x00000001
+
+/***************************************************************************
+ *PBB_VBUFCNT_N_Port_0 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_MASK     0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_SHIFT    10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_0 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_MASK   0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_0_VALID_BUF_CNT_DEFAULT 0x00000200
+
+/***************************************************************************
+ *PBB_VBUFCNT_N_Port_1 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_MASK     0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_SHIFT    10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_1 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_MASK   0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_1_VALID_BUF_CNT_DEFAULT 0x00000200
+
+/***************************************************************************
+ *PBB_VBUFCNT_N_Port_2 - Packet Buffer Block N Valid Buffer Count RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_MASK     0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_SHIFT    10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_N_Port_2 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_MASK   0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_N_Port_2_VALID_BUF_CNT_DEFAULT 0x00000200
+
+/***************************************************************************
+ *RCY_TIME_CFG - Recycling Check Pulse Period Counter RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: RCY_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RCY_TIME_CFG :: CHK_TIME [15:00] */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_MASK                0x0000ffff
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_SHIFT               0
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_DEFAULT             0x00000020
+
+/***************************************************************************
+ *PBB_PWRDWN_MON_CTRL - PBB Powerdown Monitor Control RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_PERIOD [15:08] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_MASK       0x0000ff00
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_SHIFT      8
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_TIME_UNIT [07:03] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_MASK    0x000000f8
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_SHIFT   3
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_DONE [02:02] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_MASK         0x00000004
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_SHIFT        2
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_CLR [01:01] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_MASK          0x00000002
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_SHIFT         1
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_EN [00:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_MASK           0x00000001
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON_N_Port_0 - PBB Powerdown Time Monitor N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_0 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_MASK   0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_0_PWRDWN_CNT_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON_N_Port_1 - PBB Powerdown Time Monitor N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_1 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_MASK   0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_1_PWRDWN_CNT_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON_N_Port_2 - PBB Powerdown Time Monitor N RegisterNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON_N_Port_2 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_MASK   0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_N_Port_2_PWRDWN_CNT_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *BPM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_REG_SPARE0 :: BPM_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BPM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_REG_SPARE1 :: BPM_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TRREG_CTRL0 - Traffic Remarking Control 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: PCP_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_MASK               0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_SHIFT              16
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: CFI_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_SHIFT              0
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TRREG_CTRL1 - Traffic Remarking Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: DEI_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_MASK               0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_SHIFT              16
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: PPPOE_DSCP_RMK_EN [15:15] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_MASK        0x00008000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_SHIFT       15
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_0 [14:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_MASK            0x00007e00
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: DSCP_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_SHIFT             0
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_DEFAULT           0x000001ff
+
+/***************************************************************************
+ *TRREG_CTRL2 - Traffic Remarking Control 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: C_PCP_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_MASK             0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_SHIFT            16
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: S_PCP_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_MASK             0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_SHIFT            0
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_0 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_0 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_0_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_1 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_1 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_1_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_2 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_2 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_2_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_3 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_3 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_3_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_4 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_4 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_4_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2PCP_MAP_Port_5 - Port N, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2PCP_MAP_Port_5 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2PCP_MAP_Port_5_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *P7_EGRESS_PKT_TC2PCP_MAP - Port 7, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *IMP_EGRESS_PKT_TC2PCP_MAP - Port 8, Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2PCP_MAP :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_0 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_0_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_1 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_1_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_2 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_2_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_3 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_3_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_4 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_4_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 - Port N, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: PN_EGRESS_PKT_TC2CPCP_MAP_Port_5 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_EGRESS_PKT_TC2CPCP_MAP_Port_5_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *P7_EGRESS_PKT_TC2CPCP_MAP - Port 7, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: P7_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *IMP_EGRESS_PKT_TC2CPCP_MAP - Port 8, Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: IMP_EGRESS_PKT_TC2CPCP_MAP :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *TRREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_REG_SPARE0 :: TRREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_REG_SPARE1 :: TRREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_EN_CTRL - EEE Enable Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_EN_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: EEE_EN_CTRL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: EEE_EN_CTRL :: EN_EEE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_MASK                   0x000001ff
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_SHIFT                  0
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_DEFAULT                0x00000000
+
+/***************************************************************************
+ *EEE_LPI_ASSERT - EEE Low Power Assert Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: LPI_ASSERT [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_INDICATE - EEE Low Power Indicate Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: LPI_INDICATE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_MASK        0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *EEE_RX_IDLE_SYMBOL - EEE Receiving Idle Symbols Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: RX_IDLE_SYMBOL [08:00] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_LPI_SYMBOL_TX_DISABLE - EEE LPI Symbol Transmit Disable Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: EEE_LPI_SYMBOL_TX_DISABLE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_PIPELINE_TIMER - EEE Pipeline Delay Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_PIPELINE_TIMER :: PIPELINE_TIMER [31:00] */
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_DEFAULT 0x00000020
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_0 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_0 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_0_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_1 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_1 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_1_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_2 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_2 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_2_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_3 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_3 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_3_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_4 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_4 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_4_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_Port_5 - EEE Port N Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_Port_5 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_Port_5_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P7 - EEE Port 7 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P7 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_IMP - EEE Port 8(IMP) Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_IMP :: SLEEP_TIMER_G_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_0 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_0 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_0_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_1 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_1 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_1_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_2 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_2 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_2_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_3 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_3 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_3_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_4 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_4 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_4_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_Port_5 - EEE Port N Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_Port_5 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_Port_5_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P7 - EEE Port 7 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P7 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_IMP - EEE Port 8(IMP) Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_IMP :: SLEEP_TIMER_H_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_0 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_0 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_0_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_1 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_1 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_1_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_2 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_2 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_2_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_3 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_3 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_3_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_4 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_4 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_4_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_Port_5 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_Port_5 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_Port_5_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P7 - EEE Port 7 Minimum Low-Power Duration Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P7 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_IMP :: MIN_LP_TIMER_G_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_0 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_0 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_0_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_1 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_1 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_1_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_2 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_2 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_2_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_3 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_3 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_3_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_4 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_4 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_4_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_Port_5 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_Port_5 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_Port_5_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P7 - EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P7 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_IMP :: MIN_LP_TIMER_H_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_0 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_0 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_0_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_1 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_1 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_1_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_2 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_2 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_2_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_3 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_3 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_3_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_4 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_4 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_4_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_Port_5 - EEE Port N Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_Port_5 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_Port_5_WAKE_TIMER_G_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P7 - EEE Port 7 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_IMP - EEE Port 8(IMP) Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_IMP :: WAKE_TIMER_G_IMP [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_0 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_0 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_0_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_1 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_1 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_1_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_2 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_2 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_2_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_3 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_3 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_3_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_4 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_4 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_4_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_Port_5 - EEE Port N Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_Port_5 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_Port_5_WAKE_TIMER_H_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P7 - EEE Port 7 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_IMP - EEE Port 8(IMP) Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: WAKE_TIMER_H_IMP [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_GLB_CONG_TH - EEE Global Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_MASK          0x0000f800
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_SHIFT         11
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: GLB_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_SHIFT         0
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_DEFAULT       0x00000300
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_0 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_0 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_0_TXQ_CONG_TH_DEFAULT 0x00000050
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_1 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_1 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_1_TXQ_CONG_TH_DEFAULT 0x00000050
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_2 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_2 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_2_TXQ_CONG_TH_DEFAULT 0x00000050
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_3 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_3 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_3_TXQ_CONG_TH_DEFAULT 0x00000050
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_4 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_4 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_4_TXQ_CONG_TH_DEFAULT 0x00000050
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH_Port_5 - EEE TXQ N Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH_Port_5 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH_Port_5_TXQ_CONG_TH_DEFAULT 0x00000001
+
+/***************************************************************************
+ *EEE_PHY_CTRL - EEE PHY Control Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_PHY_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_MASK             0x000000f0
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_100BASE_TX [03:03] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_MASK          0x00000008
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_SHIFT         3
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_1000BASE_TX [02:02] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_MASK         0x00000004
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_SHIFT        2
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_DEFAULT      0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_PHY_LPI [01:01] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_MASK              0x00000002
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_SHIFT             1
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_BIAS_10BTE [00:00] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_MASK           0x00000001
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_SHIFT          0
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_DEFAULT        0x00000000
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH6 - EEE TXQ 6 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_MASK         0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_SHIFT        11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH6 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_MASK         0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_SHIFT        0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_DEFAULT      0x00000001
+
+/***************************************************************************
+ *EEE_TXQ_CONG_TH7 - EEE TXQ 7 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_MASK         0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_SHIFT        11
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: EEE_TXQ_CONG_TH7 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_MASK         0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_SHIFT        0
+#define BCHP_SWITCH_CORE_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_DEFAULT      0x00000001
+
+/***************************************************************************
+ *EEE_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_CTL_REG_SPARE0 :: EEE_CTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_CTL_REG_SPARE1 :: EEE_CTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_DEBUG - EEE Debug Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_DEBUG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: EEE_DEBUG :: SWITCH_RESV [07:02] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_MASK                0x000000fc
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EEE_DEBUG :: DIS_EXIT_LPI_FLOW_CON_TX [01:01] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_MASK   0x00000002
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_SHIFT  1
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_DEBUG :: DIS_EMPTY_FLOW_CON [00:00] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_MASK         0x00000001
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_SHIFT        0
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_DEFAULT      0x00000000
+
+/***************************************************************************
+ *EEE_LINK_DLY_TIMER - EEE Link Delay Timer Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LINK_DLY_TIMER :: LINK_DLY_TIMER [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_DEFAULT 0x000f4240
+
+/***************************************************************************
+ *EEE_STATE - EEE Control Policy State Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_STATE :: SWITCH_RESV [31:27] */
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_SHIFT               27
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EEE_STATE :: EEE_STATE [26:00] */
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_MASK                  0x07ffffff
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_SHIFT                 0
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RED_CONTROL - RED Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_CONTROL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: RED_CONTROL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RED_CONTROL :: RED_EN [08:00] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_MASK                   0x000001ff
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_SHIFT                  0
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TC2RED_PROFILE_TABLE - RED Table Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_WR_RD [15:15] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_MASK 0x00008000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_SHIFT 15
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: SWITCH_RESV [14:13] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_MASK     0x00006000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_SHIFT    13
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_ADDR [12:04] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_MASK 0x00001ff0
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_SHIFT 4
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_DATA [03:00] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_SHIFT 0
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_EGRESS_BYPASS - RED Egress Bypass Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_MASK        0x0000fe00
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: RED_EGRESS_BYPASS [08:00] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_DEFAULT 0x00000080
+
+/***************************************************************************
+ *RED_AQD_CONTROL - RED AQD Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_AQD_CONTROL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_2 [15:12] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_MASK        0x0000f000
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_SHIFT       12
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_PERIOD [11:08] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_MASK           0x00000f00
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_SHIFT          8
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_DEFAULT        0x00000008
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_1 [07:06] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_MASK        0x000000c0
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_SHIFT       6
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_RST [05:05] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_MASK              0x00000020
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_SHIFT             5
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: RED_FAST_CORR [04:04] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_MASK        0x00000010
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_SHIFT       4
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_MASK        0x0000000f
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_SHIFT       0
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RED_EXPONENT - RED AQD Weighted Factor Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_EXPONENT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RED_EXPONENT :: SWITCH_RESV [15:08] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_MASK             0x0000ff00
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_SHIFT            8
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_EXPONENT :: RED_EXPONENT [07:00] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_DEFAULT         0x00000005
+
+/***************************************************************************
+ *RED_DROP_ADD_TO_MIB - RED Drop Add to MIB Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_MASK      0x0000fe00
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_SHIFT     9
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: RED_DROP_ADD_TO_MIB [08:00] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *RED_PROFILE_DEFAULT - Default RED profile Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: SWITCH_RESV [31:04] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_MASK      0xfffffff0
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_SHIFT     4
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: RED_PROFILE_DEFAULT [03:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WRED_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_REG_SPARE0 :: WRED_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_SHIFT     0
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *WRED_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_REG_SPARE1 :: WRED_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_SHIFT     0
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_0 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_0 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_0_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_1 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_1 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_1_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_2 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_2 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_2_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_3 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_3 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_3_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_4 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_4 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_4_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_5 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_5 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_5_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_6 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_6 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_6_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_7 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_7 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_7_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_8 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_8 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_8_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_9 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_MASK     0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_SHIFT    26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_MASK   0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_SHIFT  22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_MASK     0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_SHIFT    11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MAX_THD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_9 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_MASK     0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_SHIFT    0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_9_RED_MIN_THD_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_10 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_10 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_10_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_11 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_11 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_11_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_12 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_12 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_12_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_13 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_13 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_13_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_14 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_14 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_14_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PROFILE_N_Port_15 - RED profile N Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_MASK    0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_SHIFT   26
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_MASK  0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_SHIFT 22
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_DROP_PROB_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_MASK    0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_SHIFT   11
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MAX_THD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_N_Port_15 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_RED_PROFILE_N_Port_15_RED_MIN_THD_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_DROP_CNTR_RST - RED Drop Counter Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_MASK        0x0000fe00
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: RED_DROP_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_0 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_0 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_0_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_1 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_1 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_1_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_2 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_2 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_2_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_3 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_3 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_3_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_4 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_4 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_4_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_PKT_DROP_CNTR_Port_5 - PORT N RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_PKT_DROP_CNTR_Port_5 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_PKT_DROP_CNTR_Port_5_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P7_PORT_RED_PKT_DROP_CNTR - PORT 7 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_RED_PKT_DROP_CNTR :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IMP_PORT_RED_PKT_DROP_CNTR - PORT 8 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_RED_PKT_DROP_CNTR :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_0 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_0 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_0_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_1 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_1 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_1_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_2 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_2 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_2_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_3 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_3 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_3_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_4 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_4 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_4_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *PN_PORT_RED_BYTE_DROP_CNTR_Port_5 - PORT N RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PN_PORT_RED_BYTE_DROP_CNTR_Port_5 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_PN_PORT_RED_BYTE_DROP_CNTR_Port_5_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *P7_PORT_RED_BYTE_DROP_CNTR - PORT 7 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: P7_PORT_RED_BYTE_DROP_CNTR :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *IMP_PORT_RED_BYTE_DROP_CNTR - PORT 8 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP_PORT_RED_BYTE_DROP_CNTR :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *CFP_ACC - CFP Access Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_ACC :: RD_STS [31:28] */
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_MASK                       0xf0000000
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_SHIFT                      28
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SERCH_STS [27:27] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_MASK                    0x08000000
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_SHIFT                   27
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_MASK                0x07000000
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_SHIFT               24
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: XCESS_ADDR [23:16] */
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_MASK                   0x00ff0000
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_SHIFT                  16
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: TCAM_RST [15:15] */
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_MASK                     0x00008000
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_SHIFT                    15
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: RAM_SEL [14:10] */
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_MASK                      0x00007c00
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_SHIFT                     10
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_0 [09:06] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_MASK                0x000003c0
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_SHIFT               6
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: KEY_0_1_RAW_ENC [05:05] */
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_MASK              0x00000020
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_SHIFT             5
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: CFP_RAM_CLEAR [04:04] */
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_MASK                0x00000010
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_SHIFT               4
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: OP_SEL [03:01] */
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_MASK                       0x0000000e
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_SHIFT                      1
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: OP_STR_DONE [00:00] */
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RATE_METER_GLOBAL_CTL - CFP RATE METER Global Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: SWITCH_RESV [15:03] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_MASK    0x0000fff8
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_SHIFT   3
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: RATE_REFRESH_EN [02:02] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_MASK 0x00000004
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: PKT_LEN_CORR [01:00] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_MASK   0x00000003
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_SHIFT  0
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_0 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_0 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_0_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_1 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_1 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_1_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_2 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_2 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_2_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_3 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_3 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_3_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_4 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_4 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_4_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_5 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_5 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_5_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_6 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_6 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_6_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DATA_Port_7 - CFP TCAM Data X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA_Port_7 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_DATA_Port_7_TCAM_DATA_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_0 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_0 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_0_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_1 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_1 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_1_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_2 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_2 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_2_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_3 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_3 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_3_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_4 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_4 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_4_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_5 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_5 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_5_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_6 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_6 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_6_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_MASK_Port_7 - CFP TCAM Mask X Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK_Port_7 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_SHIFT           0
+#define BCHP_SWITCH_CORE_CFP_MASK_Port_7_TCAM_MASK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA0 - CFP Action/Policy Data 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_DSCP_IB [31:26] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_SHIFT           26
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_FWRD_MAP_IB [25:24] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_MASK     0x03000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_SHIFT    24
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: DST_MAP_IB [23:14] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_MASK             0x00ffc000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_SHIFT            14
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_TC [13:13] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_MASK              0x00002000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_SHIFT             13
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_TC [12:10] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_MASK                 0x00001c00
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_SHIFT                10
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: LOOP_BK_EN [09:09] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_MASK             0x00000200
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_SHIFT            9
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: REASON_CODE [08:03] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_MASK            0x000001f8
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_SHIFT           3
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: STP_BYP [02:02] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_MASK                0x00000004
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_SHIFT               2
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: EAP_BYP [01:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_MASK                0x00000002
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_SHIFT               1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: VLAN_BYP [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_MASK               0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_SHIFT              0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA1 - CFP Action/Policy Data 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA1 :: RED_DEFAULT [31:31] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_MASK            0x80000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_SHIFT           31
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_COLOR [30:29] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_MASK              0x60000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_SHIFT             29
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_COLOR [28:28] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_MASK           0x10000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_SHIFT          28
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHAIN_ID [27:20] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_MASK               0x0ff00000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_SHIFT              20
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_OB [19:19] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_MASK         0x00080000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_SHIFT        19
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_DSCP_OB [18:13] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_MASK            0x0007e000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_SHIFT           13
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_FWRD_MAP_OB [12:11] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_MASK     0x00001800
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_SHIFT    11
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: DST_MAP_OB [10:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_MASK             0x000007fe
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_SHIFT            1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_IB [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_MASK         0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_SHIFT        0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_DEFAULT      0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA2 - CFP Action/Policy Data 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA2 :: SWITCH_RESV [31:08] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_MASK            0xffffff00
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_SHIFT           8
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: DEI_RMK_DISABLE [07:07] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_MASK        0x00000080
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_SHIFT       7
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: CPCP_RMK_DISABLE [06:06] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_MASK       0x00000040
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_SHIFT      6
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: SPCP_RMK_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_MASK       0x00000020
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_SHIFT      5
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: NEW_TC_O [04:02] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_MASK               0x0000001c
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_SHIFT              2
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: CHANGE_TC_O [01:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_MASK            0x00000002
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_SHIFT           1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: MAC_LIMIT_BYPASS [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_MASK       0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_SHIFT      0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RATE_METER0 - CFP RATE METER DATA 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER0 :: SWITCH_RESV [31:05] */
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_MASK              0xffffffe0
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_SHIFT             5
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: POLICER_MODE [04:03] */
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_MASK             0x00000018
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_SHIFT            3
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: CF [02:02] */
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_MASK                       0x00000004
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_SHIFT                      2
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: POLICER_ACTION [01:01] */
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_MASK           0x00000002
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_SHIFT          1
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: CM [00:00] */
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_SHIFT                      0
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RATE_METER1 - CFP RATE METER DATA 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER1 :: SWITCH_RESV [31:23] */
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_MASK              0xff800000
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_SHIFT             23
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER1 :: EIR_TK_BKT [22:00] */
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_MASK               0x007fffff
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_SHIFT              0
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RATE_METER2 - CFP RATE METER DATA 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER2 :: SWITCH_RESV [31:20] */
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_MASK              0xfff00000
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_SHIFT             20
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER2 :: EIR_BKT_SIZE [19:00] */
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_MASK             0x000fffff
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_SHIFT            0
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RATE_METER3 - CFP RATE METER DATA 3 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER3 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_MASK              0xfff80000
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_SHIFT             19
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER3 :: EIR_REF_CNT [18:00] */
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_MASK              0x0007ffff
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RATE_METER4 - CFP RATE METER DATA 4 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER4 :: SWITCH_RESV [31:23] */
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_MASK              0xff800000
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_SHIFT             23
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER4 :: CIR_TK_BKT [22:00] */
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_MASK               0x007fffff
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_SHIFT              0
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RATE_METER5 - CFP RATE METER DATA 5 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER5 :: SWITCH_RESV [31:20] */
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_MASK              0xfff00000
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_SHIFT             20
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER5 :: CIR_BKT_SIZE [19:00] */
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_MASK             0x000fffff
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_SHIFT            0
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RATE_METER6 - CFP RATE METER DATA 6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER6 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_MASK              0xfff80000
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_SHIFT             19
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER6 :: CIR_REF_CNT [18:00] */
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_MASK              0x0007ffff
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TC2COLOR - TC to COLOR Mapping Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COLOR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: TC2COLOR :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_MASK                 0x0000f800
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_SHIFT                11
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_COLOR [10:09] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_MASK          0x00000600
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_DEI [08:08] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_MASK            0x00000100
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_SHIFT           8
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_TC [07:05] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_MASK             0x000000e0
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_SHIFT            5
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_ING_PORT [04:01] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_MASK       0x0000001e
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_SHIFT      1
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_RW [00:00] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_MASK             0x00000001
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_SHIFT            0
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_GREEN_CNTR - Policer Green color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_GREEN_CNTR :: GREEN_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_SHIFT          0
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *STAT_YELLOW_CNTR - Policer Yellow color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_YELLOW_CNTR :: YELLOW_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_SHIFT        0
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_RED_CNTR - Policer RED color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_RED_CNTR :: RED_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_SHIFT              0
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TCAM_BIST_CONTROL - TCAM BIST Control Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_DONE [31:31] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_MASK     0x80000000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_SHIFT    31
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_1 [30:17] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_MASK      0x7ffe0000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_SHIFT     17
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_TEST_COMPARE [16:16] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_MASK  0x00010000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_SHIFT 16
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_SKIP_ERR_CNT [15:08] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_STATUS_SEL [07:04] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_SHIFT 4
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_0 [03:02] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_SHIFT     2
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_SEL [01:01] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_MASK           0x00000002
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_SHIFT          1
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_EN [00:00] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_MASK       0x00000001
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_SHIFT      0
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TCAM_BIST_STATUS - TCAM BIST Status Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_BIST_STATUS :: SWITCH_RESV [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_SHIFT        16
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_STATUS :: TCAM_BIST_STATUS [15:00] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK    0x0000ffff
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT   0
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TCAM_TEST_COMPARE_STATUS - TCAM Test Compare Status Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_1 [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_SHIFT 16
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT [15:15] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_MASK    0x00008000
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_SHIFT   15
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_0 [14:07] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_MASK 0x00007f80
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_SHIFT 7
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT_ADDR [06:00] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_MASK 0x0000007f
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_SHIFT 0
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CFP_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_REG_SPARE0 :: CFP_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CFP_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_REG_SPARE1 :: CFP_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CFP_CTL_REG - CFP Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_CTL_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: CFP_CTL_REG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CFP_CTL_REG :: CFP_EN_MAP [08:00] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_SHIFT              0
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_0 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_0 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_0_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_1 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_1 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_1_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_2 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_2 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_2_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_3 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_3 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_3_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_4 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_4 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_4_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_5 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_5 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_5_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_6 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_6 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_6_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_7 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_7 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_7_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_Port_8 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_Port_8 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_Port_8_CFG_UDF_0_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_0 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_0 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_0_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_1 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_1 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_1_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_2 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_2 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_2_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_3 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_3 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_3_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_4 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_4 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_4_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_5 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_5 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_5_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_6 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_6 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_6_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_7 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_7 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_7_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_Port_8 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_Port_8 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_Port_8_CFG_UDF_1_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_0 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_0 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_0_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_1 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_1 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_1_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_2 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_2 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_2_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_3 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_3 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_3_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_4 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_4 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_4_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_5 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_5 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_5_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_6 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_6 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_6_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_7 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_7 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_7_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_Port_8 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_Port_8 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_Port_8_CFG_UDF_2_A_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_0 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_0 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_0_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_1 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_1 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_1_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_2 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_2 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_2_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_3 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_3 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_3_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_4 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_4 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_4_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_5 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_5 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_5_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_6 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_6 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_6_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_7 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_7 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_7_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_Port_8 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_Port_8 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_Port_8_CFG_UDF_0_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_0 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_0 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_0_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_1 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_1 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_1_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_2 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_2 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_2_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_3 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_3 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_3_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_4 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_4 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_4_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_5 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_5 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_5_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_6 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_6 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_6_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_7 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_7 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_7_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_Port_8 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_Port_8 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_Port_8_CFG_UDF_1_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_0 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_0 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_0_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_1 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_1 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_1_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_2 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_2 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_2_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_3 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_3 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_3_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_4 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_4 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_4_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_5 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_5 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_5_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_6 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_6 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_6_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_7 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_7 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_7_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_Port_8 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_Port_8 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_Port_8_CFG_UDF_2_B_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_0 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_0 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_0_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_1 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_1 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_1_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_2 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_2 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_2_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_3 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_3 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_3_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_4 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_4 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_4_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_5 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_5 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_5_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_6 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_6 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_6_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_7 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_7 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_7_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_Port_8 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_Port_8 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_Port_8_CFG_UDF_0_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_0 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_0 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_1 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_1 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_2 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_2 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_3 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_3 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_4 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_4 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_5 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_5 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_6 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_6 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_7 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_7 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_Port_8 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_Port_8 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_Port_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_0 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_0 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_1 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_1 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_2 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_2 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_3 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_3 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_4 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_4 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_5 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_5 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_6 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_6 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_7 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_7 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_Port_8 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_Port_8 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_SHIFT  0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_Port_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_0 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_0 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_0_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_1 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_1 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_1_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_2 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_2 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_2_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_3 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_3 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_3_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_4 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_4 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_4_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_5 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_5 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_5_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_6 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_6 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_6_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_7 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_7 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_7_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_8 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_8 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_8_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_9 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_9 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_9 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_9_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_10 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_10 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_10 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_10_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_Port_11 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_11 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_Port_11 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_SHIFT 0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_Port_11_CFG_UDF_0_D_0_11_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_CTL_REG - CPU OTP Control RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG :: BYPASS_OTP_CLK [31:31] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_MASK           0x80000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_SHIFT          31
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_MASK              0x60000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_SHIFT             29
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: CPU_DEBUG_SEL [28:25] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_MASK            0x1e000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_SHIFT           25
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: BURST_STAT_SEL [24:24] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_MASK           0x01000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_SHIFT          24
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: ACCESS_MODE [23:22] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_MASK              0x00c00000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_SHIFT             22
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: OTP_PROG_EN [21:21] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_MASK              0x00200000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_SHIFT             21
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: OTP_DEBUG_MODE [20:20] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_MASK           0x00100000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_SHIFT          20
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_CONTINUE_ON_FAIL [19:19] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_MASK     0x00080000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_SHIFT    19
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_TIME_MARGIN [18:16] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_MASK          0x00070000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_SHIFT         16
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_SADBYP [15:15] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_MASK               0x00008000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_SHIFT              15
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: UNUSED [14:14] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_MASK                   0x00004000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_SHIFT                  14
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PBYP [13:13] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_MASK                 0x00002000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_SHIFT                13
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PCOUNT [12:10] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_MASK               0x00001c00
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_SHIFT              10
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_VSEL [09:06] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_MASK                 0x000003c0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_SHIFT                6
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PROG_SEL [05:05] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_MASK             0x00000020
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_SHIFT            5
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: COMMAND [04:01] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_MASK                  0x0000001e
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_SHIFT                 1
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: START [00:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_SHIFT                   0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *OTP_ADDR_REG - CPU OTP Address RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_ADDR_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: OTP_ADDR_REG :: CPU_ADDR [15:00] */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_MASK                0x0000ffff
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_SHIFT               0
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_DEFAULT             0x00000000
+
+/***************************************************************************
+ *OTP_STS_REG - CPU OTP Status RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_STS_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_0 [15:12] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_MASK                 0x0000f000
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_SHIFT                12
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: CONTROL_ERR [11:11] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_MASK              0x00000800
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_SHIFT             11
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_ERROR [10:10] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_MASK                0x00000400
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_SHIFT               10
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INVALID_COMMAND [09:09] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_MASK          0x00000200
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_SHIFT         9
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_1 [08:08] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_MASK                 0x00000100
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_SHIFT                8
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INIT_WAIT_DONE [07:07] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_MASK           0x00000080
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_SHIFT          7
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_DEFAULT        0x00000001
+
+/* SWITCH_CORE :: OTP_STS_REG :: PROG_BLOCKED [06:06] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_MASK             0x00000040
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_SHIFT            6
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INVALID_PROG_REQ [05:05] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_MASK         0x00000020
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_SHIFT        5
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_FAIL [04:04] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_MASK                 0x00000010
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_SHIFT                4
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_BUSY [03:03] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_SHIFT                3
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_DOUT [02:02] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_SHIFT                2
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_DATA_READY [01:01] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_MASK           0x00000002
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_SHIFT          1
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: COMMAND_DONE [00:00] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_MASK             0x00000001
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_SHIFT            0
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OTP_WR_DATA - CPU OTP Write Data RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_WR_DATA :: CPU_WR_DATA [31:00] */
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *OTP_RD_DATA - CPU OTP Read Data RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_RD_DATA :: CPU_RD_DATA [31:00] */
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *IO_SR_CTL - I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_SR_CTL :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_MASK                0xfff80000
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_SHIFT               19
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: IO_SR_CTL :: IO_SR_CTL [18:00] */
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_MASK                  0x0007ffff
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_SHIFT                 0
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_DEFAULT               0x00000600
+
+/***************************************************************************
+ *IO_DS_SEL0 - I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_DS_SEL0 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_MASK               0xfff80000
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_SHIFT              19
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: IO_DS_SEL0 :: IO_DS_SEL0 [18:00] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_MASK                0x0007ffff
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_SHIFT               0
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_DEFAULT             0x0007ffff
+
+/***************************************************************************
+ *IO_DS_SEL2 - I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_DS_SEL2 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_MASK               0xfff80000
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_SHIFT              19
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: IO_DS_SEL2 :: IO_DS_SEL2 [18:00] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_MASK                0x0007ffff
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_SHIFT               0
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_DEFAULT             0x0007ffff
+
+/***************************************************************************
+ *GMII_IO_SR_CTL - GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_SR_CTL :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_MASK           0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_SHIFT          3
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: GMII_IO_SR_CTL :: GMII_IO_SR_CTL [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_MASK        0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_SHIFT       0
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GMII_IO_DS_SEL0 - GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_MASK          0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_SHIFT         3
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: GMII_IO_DS_SEL0 [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_MASK      0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_SHIFT     0
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_DEFAULT   0x00000007
+
+/***************************************************************************
+ *GMII_IO_DS_SEL1 - GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_MASK          0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_SHIFT         3
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: GMII_IO_DS_SEL1 [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_MASK      0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_SHIFT     0
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_DEFAULT   0x00000007
+
+/***************************************************************************
+ *OTP_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG_SPARE0 :: OTP_CTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG_SPARE1 :: OTP_CTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPIDIO0 - SPI Data I/O Registers 0
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO0_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO0_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO0 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO0_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO1 - SPI Data I/O Registers 1
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO1_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO1_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO1 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO1_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO2 - SPI Data I/O Registers 2
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO2_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO2_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO2 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO2_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO3 - SPI Data I/O Registers 3
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO3_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO3_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO3 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO3_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO4 - SPI Data I/O Registers 4
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO4_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO4_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO4 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO4_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO5 - SPI Data I/O Registers 5
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO5_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO5_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO5 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO5_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO6 - SPI Data I/O Registers 6
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO6_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO6_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO6 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO6_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SPIDIO7 - SPI Data I/O Registers 7
+ ***************************************************************************/
+/* SWITCH_CORE :: SPIDIO7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPIDIO7_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_SPIDIO7_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: SPIDIO7 :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_SPIDIO7_SWITCH_RESV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CLKSET - Clock Period Setting Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CLKSET :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_SHIFT                  0
+#define BCHP_SWITCH_CORE_CLKSET_SWITCH_RESV_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPISTS - SPI Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: SPISTS :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SPISTS_reserved_for_padding0_MASK         0xffffff00
+#define BCHP_SWITCH_CORE_SPISTS_reserved_for_padding0_SHIFT        8
+
+/* SWITCH_CORE :: SPISTS :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_MASK                   0x000000ff
+#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_SHIFT                  0
+#define BCHP_SWITCH_CORE_SPISTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PAGEREG - PAGE Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: PAGEREG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PAGEREG_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_PAGEREG_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: PAGEREG :: SWITCH_RESV [07:00] */
+#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_MASK                  0x000000ff
+#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_SHIFT                 0
+#define BCHP_SWITCH_CORE_PAGEREG_SWITCH_RESV_DEFAULT               0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_CORE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_fcb.h b/include/linux/brcmstb/3390a0/bchp_switch_fcb.h
new file mode 100644
index 000000000000..b2da85f61cc6
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_fcb.h
@@ -0,0 +1,424 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:25 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_FCB_H__
+#define BCHP_SWITCH_FCB_H__
+
+/***************************************************************************
+ *SWITCH_FCB
+ ***************************************************************************/
+#define BCHP_SWITCH_FCB_FCB_CONTROL              0x04e40400 /* Tx Pause Enable Register */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL 0x04e40404 /* P8 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT       0x04e40408 /* P8 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL 0x04e4040c /* P5 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT       0x04e40410 /* P5 Release Timeout Register */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT 0x04e40414 /* P5 Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL 0x04e40418 /* P4 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT       0x04e4041c /* P4 Release Timeout Register */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT 0x04e40420 /* P4 Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL 0x04e40424 /* LAN Failover Release Control Register */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT      0x04e40428 /* LAN Release Timeout Register */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT 0x04e4042c /* LAN Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL 0x04e40430 /* FCB Pause Override Control Register */
+
+/***************************************************************************
+ *FCB_CONTROL - Tx Pause Enable Register
+ ***************************************************************************/
+/* SWITCH_FCB :: FCB_CONTROL :: reserved0 [31:10] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_MASK                 0xfffffc00
+#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_SHIFT                10
+
+/* SWITCH_FCB :: FCB_CONTROL :: fcb_en [09:09] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_MASK                    0x00000200
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_SHIFT                   9
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_DEFAULT                 0x00000000
+
+/* SWITCH_FCB :: FCB_CONTROL :: failover_dis [08:00] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_MASK              0x000001ff
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_SHIFT             0
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_DEFAULT           0x00000000
+
+/***************************************************************************
+ *P8_FAILOVER_RELEASE_CONTROL - P8 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P8_RELEASE_TIMEOUT - P8 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P5_FAILOVER_RELEASE_CONTROL - P5 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P5_RELEASE_TIMEOUT - P5 Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P5_RELEASE_DELAY_TIMEOUT - P5 Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_MASK    0xfffffe00
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT   9
+
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *P4_FAILOVER_RELEASE_CONTROL - P4 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P4_RELEASE_TIMEOUT - P4 Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P4_RELEASE_DELAY_TIMEOUT - P4 Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_MASK    0xfffffe00
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT   9
+
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *LAN_FAILOVER_RELEASE_CONTROL - LAN Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *LAN_RELEASE_TIMEOUT - LAN Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_MASK         0xfffe0000
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_SHIFT        17
+
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_MASK  0x00010000
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_MASK   0x0000ffff
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_SHIFT  0
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *LAN_RELEASE_DELAY_TIMEOUT - LAN Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_MASK   0xfffffe00
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT  9
+
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *FCB_PAUSE_OVERRIDE_CONTROL - FCB Pause Override Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: reserved0 [31:18] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_reserved0_MASK  0xfffc0000
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_reserved0_SHIFT 18
+
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: tx_pause_ovrd_en [17:09] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_MASK 0x0003fe00
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_SHIFT 9
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: tx_pause_ovrd [08:00] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_MASK 0x000001ff
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_SHIFT 0
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_FCB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_indir_rw.h b/include/linux/brcmstb/3390a0/bchp_switch_indir_rw.h
new file mode 100644
index 000000000000..ef58b16be390
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_indir_rw.h
@@ -0,0 +1,140 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed May  8 03:09:20 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_INDIR_RW_H__
+#define BCHP_SWITCH_INDIR_RW_H__
+
+/***************************************************************************
+ *SWITCH_INDIR_RW
+ ***************************************************************************/
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0    0x04e40300 /* Indirect Address Register 0 */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0 0x04e40304 /* Indirect Data Low Register 0 */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0 0x04e40308 /* Indirect Data High Register 0 */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1    0x04e4030c /* Indirect Address Register 1 */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1 0x04e40310 /* Indirect Data Low Register 1 */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1 0x04e40314 /* Indirect Data High Register 1 */
+
+/***************************************************************************
+ *INDIR_ADDR_REG_0 - Indirect Address Register 0
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reserved0 [31:18] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_MASK       0xfffc0000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_SHIFT      18
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: start_busy [17:17] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_MASK      0x00020000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_SHIFT     17
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_DEFAULT   0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: r_w [16:16] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_MASK             0x00010000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_SHIFT            16
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_DEFAULT          0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_page [15:08] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_MASK        0x0000ff00
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_SHIFT       8
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_DEFAULT     0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_offset [07:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_MASK      0x000000ff
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_SHIFT     0
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *INDIR_DATA_LOW_REG_0 - Indirect Data Low Register 0
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_0 :: data_low [31:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_MASK    0xffffffff
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_SHIFT   0
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INDIR_DATA_HIGH_REG_0 - Indirect Data High Register 0
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_0 :: data_high [31:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_MASK  0xffffffff
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_SHIFT 0
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INDIR_ADDR_REG_1 - Indirect Address Register 1
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reserved0 [31:18] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_MASK       0xfffc0000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_SHIFT      18
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: start_busy [17:17] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_MASK      0x00020000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_SHIFT     17
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_DEFAULT   0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: r_w [16:16] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_MASK             0x00010000
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_SHIFT            16
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_DEFAULT          0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_page [15:08] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_MASK        0x0000ff00
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_SHIFT       8
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_DEFAULT     0x00000000
+
+/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_offset [07:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_MASK      0x000000ff
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_SHIFT     0
+#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *INDIR_DATA_LOW_REG_1 - Indirect Data Low Register 1
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_1 :: data_low [31:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_MASK    0xffffffff
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_SHIFT   0
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INDIR_DATA_HIGH_REG_1 - Indirect Data High Register 1
+ ***************************************************************************/
+/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_1 :: data_high [31:00] */
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_MASK  0xffffffff
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_SHIFT 0
+#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_INDIR_RW_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_intrl2_0.h b/include/linux/brcmstb/3390a0/bchp_switch_intrl2_0.h
new file mode 100644
index 000000000000..b8a19fc35c9a
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_intrl2_0.h
@@ -0,0 +1,1226 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:13 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_INTRL2_0_H__
+#define BCHP_SWITCH_INTRL2_0_H__
+
+/***************************************************************************
+ *SWITCH_INTRL2_0
+ ***************************************************************************/
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS          0x04e40340 /* CPU interrupt Status Register */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET             0x04e40344 /* CPU interrupt Set Register */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR           0x04e40348 /* CPU interrupt Clear Register */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS     0x04e4034c /* CPU interrupt Mask Status Register */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET        0x04e40350 /* CPU interrupt Mask Set Register */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR      0x04e40354 /* CPU interrupt Mask Clear Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS          0x04e40358 /* PCI interrupt Status Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET             0x04e4035c /* PCI interrupt Set Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR           0x04e40360 /* PCI interrupt Clear Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS     0x04e40364 /* PCI interrupt Mask Status Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET        0x04e40368 /* PCI interrupt Mask Set Register */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR      0x04e4036c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_MASK             0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_reserved0_SHIFT            18
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_MASK    0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_SHIFT   17
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_TCAM_soft_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_MASK     0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_SHIFT    16
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_MASK      0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_SHIFT     15
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_failover_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_MASK         0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_SHIFT        14
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_ubus_err_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_MASK         0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_SHIFT        13
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_gisb_err_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_MASK        0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_SHIFT       12
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_done_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_MASK      0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_SHIFT     11
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_mdio_err_up_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_MASK             0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_SHIFT            10
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_1588_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_MASK          0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_SHIFT         6
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_eee_lpi_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_MASK          0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_SHIFT         4
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_MASK    0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_SHIFT   3
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_MASK     0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_SHIFT    2
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_MASK     0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_SHIFT    1
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_STATUS :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_MASK       0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_SHIFT      0
+#define BCHP_SWITCH_INTRL2_0_CPU_STATUS_p0_link_up_intr_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_SET :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_MASK                0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_reserved0_SHIFT               18
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_MASK       0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_SHIFT      17
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_TCAM_soft_err_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_MASK        0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_SHIFT       16
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_off_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_MASK         0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_SHIFT        15
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_failover_on_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_MASK            0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_SHIFT           14
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_ubus_err_intr_DEFAULT         0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_MASK            0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_SHIFT           13
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_gisb_err_intr_DEFAULT         0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_MASK           0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_SHIFT          12
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_done_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_MASK         0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_SHIFT        11
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_mdio_err_up_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_MASK                0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_SHIFT               10
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_1588_intr_DEFAULT             0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_MASK   0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_SHIFT  9
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_MASK   0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_SHIFT  8
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_MASK   0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_SHIFT  7
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_MASK             0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_SHIFT            6
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_eee_lpi_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_MASK   0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_SHIFT  5
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_MASK             0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_SHIFT            4
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_MASK       0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_SHIFT      3
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_MASK        0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_SHIFT       2
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_MASK        0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_SHIFT       1
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_SET :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_MASK          0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_SHIFT         0
+#define BCHP_SWITCH_INTRL2_0_CPU_SET_p0_link_up_intr_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_MASK              0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_reserved0_SHIFT             18
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_MASK     0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_SHIFT    17
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_TCAM_soft_err_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_MASK      0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_SHIFT     16
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_off_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_MASK       0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_SHIFT      15
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_failover_on_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_MASK          0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_SHIFT         14
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_ubus_err_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_MASK          0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_SHIFT         13
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_gisb_err_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_MASK         0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_SHIFT        12
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_done_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_MASK       0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_SHIFT      11
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_mdio_err_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_MASK              0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_SHIFT             10
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_1588_intr_DEFAULT           0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_MASK           0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_SHIFT          6
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_eee_lpi_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_MASK           0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_SHIFT          4
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_MASK     0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_SHIFT    3
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_MASK      0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_SHIFT     2
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_MASK      0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_SHIFT     1
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: CPU_CLEAR :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_MASK        0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_SHIFT       0
+#define BCHP_SWITCH_INTRL2_0_CPU_CLEAR_p0_link_up_intr_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_MASK        0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_reserved0_SHIFT       18
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_MASK   0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_SHIFT  10
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_MASK           0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_reserved0_SHIFT          18
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_MASK  0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_MASK  0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_MASK  0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_MASK      0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_SHIFT     10
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_1588_intr_mask_DEFAULT   0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_MASK   0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_SHIFT  6
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_MASK   0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_SHIFT  4
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_SET :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_MASK         0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_reserved0_SHIFT        18
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_MASK    0x00000400
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_SHIFT   10
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: CPU_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_CPU_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_MASK             0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_reserved0_SHIFT            18
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_MASK    0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_SHIFT   17
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_TCAM_soft_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_MASK     0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_SHIFT    16
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_MASK      0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_SHIFT     15
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_failover_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_MASK         0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_SHIFT        14
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_ubus_err_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_MASK         0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_SHIFT        13
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_gisb_err_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_MASK        0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_SHIFT       12
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_done_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_MASK      0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_SHIFT     11
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_mdio_err_up_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_MASK             0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_SHIFT            10
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_1588_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_MASK          0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_SHIFT         6
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_eee_lpi_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_MASK          0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_SHIFT         4
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_MASK    0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_SHIFT   3
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_MASK     0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_SHIFT    2
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_MASK     0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_SHIFT    1
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_STATUS :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_MASK       0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_SHIFT      0
+#define BCHP_SWITCH_INTRL2_0_PCI_STATUS_p0_link_up_intr_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_SET :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_MASK                0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_reserved0_SHIFT               18
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_MASK       0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_SHIFT      17
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_TCAM_soft_err_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_MASK        0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_SHIFT       16
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_off_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_MASK         0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_SHIFT        15
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_failover_on_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_MASK            0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_SHIFT           14
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_ubus_err_intr_DEFAULT         0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_MASK            0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_SHIFT           13
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_gisb_err_intr_DEFAULT         0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_MASK           0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_SHIFT          12
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_done_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_MASK         0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_SHIFT        11
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_mdio_err_up_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_MASK                0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_SHIFT               10
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_1588_intr_DEFAULT             0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_MASK   0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_SHIFT  9
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_MASK   0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_SHIFT  8
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_MASK   0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_SHIFT  7
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_MASK             0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_SHIFT            6
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_eee_lpi_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_MASK   0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_SHIFT  5
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_MASK             0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_SHIFT            4
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_MASK       0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_SHIFT      3
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_MASK        0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_SHIFT       2
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_MASK        0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_SHIFT       1
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_SET :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_MASK          0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_SHIFT         0
+#define BCHP_SWITCH_INTRL2_0_PCI_SET_p0_link_up_intr_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_MASK              0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_reserved0_SHIFT             18
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: TCAM_soft_err_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_MASK     0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_SHIFT    17
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_TCAM_soft_err_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_off_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_MASK      0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_SHIFT     16
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_off_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: failover_on_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_MASK       0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_SHIFT      15
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_failover_on_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: ubus_err_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_MASK          0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_SHIFT         14
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_ubus_err_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: gisb_err_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_MASK          0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_SHIFT         13
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_gisb_err_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_done_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_MASK         0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_SHIFT        12
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_done_intr_DEFAULT      0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: mdio_err_up_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_MASK       0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_SHIFT      11
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_mdio_err_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: 1588_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_MASK              0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_SHIFT             10
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_1588_intr_DEFAULT           0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p7_cpu_wake_timer_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p7_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p8_cpu_wake_timer_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p8_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p5_cpu_wake_timer_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p5_cpu_wake_timer_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: eee_lpi_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_MASK           0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_SHIFT          6
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_eee_lpi_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: memory_double_err_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_memory_double_err_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_MASK           0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_SHIFT          4
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_MASK     0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_SHIFT    3
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_MASK      0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_SHIFT     2
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_MASK      0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_SHIFT     1
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_0 :: PCI_CLEAR :: p0_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_MASK        0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_SHIFT       0
+#define BCHP_SWITCH_INTRL2_0_PCI_CLEAR_p0_link_up_intr_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_MASK        0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_reserved0_SHIFT       18
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_MASK   0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_SHIFT  10
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_1588_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_STATUS :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_STATUS_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_MASK           0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_reserved0_SHIFT          18
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_MASK  0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_MASK  0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_MASK  0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_MASK      0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_SHIFT     10
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_1588_intr_mask_DEFAULT   0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_MASK   0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_SHIFT  6
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_MASK   0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_SHIFT  4
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_SET :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_SET_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: reserved0 [31:18] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_MASK         0xfffc0000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_reserved0_SHIFT        18
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: TCAM_soft_err_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_TCAM_soft_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_off_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: failover_on_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_failover_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: ubus_err_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_ubus_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: gisb_err_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_gisb_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_done_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_done_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: mdio_err_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_mdio_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: 1588_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_MASK    0x00000400
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_SHIFT   10
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_1588_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p7_cpu_wake_timer_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p7_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p8_cpu_wake_timer_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p8_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p5_cpu_wake_timer_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p5_cpu_wake_timer_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: eee_lpi_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_eee_lpi_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: memory_double_err_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_memory_double_err_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_0 :: PCI_MASK_CLEAR :: p0_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_0_PCI_MASK_CLEAR_p0_link_up_intr_mask_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_SWITCH_INTRL2_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_intrl2_1.h b/include/linux/brcmstb/3390a0/bchp_switch_intrl2_1.h
new file mode 100644
index 000000000000..7fc688d5b0ec
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_intrl2_1.h
@@ -0,0 +1,1944 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed May  8 03:09:25 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_INTRL2_1_H__
+#define BCHP_SWITCH_INTRL2_1_H__
+
+/***************************************************************************
+ *SWITCH_INTRL2_1
+ ***************************************************************************/
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS          0x04e40380 /* CPU interrupt Status Register */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET             0x04e40384 /* CPU interrupt Set Register */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR           0x04e40388 /* CPU interrupt Clear Register */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS     0x04e4038c /* CPU interrupt Mask Status Register */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET        0x04e40390 /* CPU interrupt Mask Set Register */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR      0x04e40394 /* CPU interrupt Mask Clear Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS          0x04e40398 /* PCI interrupt Status Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET             0x04e4039c /* PCI interrupt Set Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR           0x04e403a0 /* PCI interrupt Clear Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS     0x04e403a4 /* PCI interrupt Mask Status Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET        0x04e403a8 /* PCI interrupt Mask Set Register */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR      0x04e403ac /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_MASK             0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_SHIFT            30
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_MASK          0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_SHIFT         29
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_MASK    0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_SHIFT   28
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_MASK     0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_SHIFT    27
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_MASK     0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_SHIFT    26
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_MASK       0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_SHIFT      25
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_MASK          0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_SHIFT         24
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_MASK    0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_SHIFT   23
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_MASK     0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_SHIFT    22
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_MASK     0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_SHIFT    21
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_MASK       0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_SHIFT      20
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_MASK          0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_SHIFT         19
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_MASK    0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_SHIFT   18
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_MASK     0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_SHIFT    17
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_MASK     0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_SHIFT    16
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_MASK       0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_SHIFT      15
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_MASK          0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_SHIFT         14
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_MASK    0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_SHIFT   13
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_MASK     0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_SHIFT    12
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_MASK     0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_SHIFT    11
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_MASK       0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_SHIFT      10
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_MASK          0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_SHIFT         9
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_MASK    0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_SHIFT   8
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_MASK     0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_SHIFT    7
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_MASK     0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_SHIFT    6
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_MASK       0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_SHIFT      5
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_MASK          0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_SHIFT         4
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_MASK    0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_SHIFT   3
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_MASK     0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_SHIFT    2
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_MASK     0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_SHIFT    1
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_MASK       0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_SHIFT      0
+#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_SET :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_MASK                0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_SHIFT               30
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_MASK             0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_SHIFT            29
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_MASK       0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_SHIFT      28
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_MASK        0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_SHIFT       27
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_MASK        0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_SHIFT       26
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_MASK          0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_SHIFT         25
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_MASK             0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_SHIFT            24
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_MASK       0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_SHIFT      23
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_MASK        0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_SHIFT       22
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_MASK        0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_SHIFT       21
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_MASK          0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_SHIFT         20
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_MASK             0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_SHIFT            19
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_MASK       0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_SHIFT      18
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_MASK        0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_SHIFT       17
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_MASK        0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_SHIFT       16
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_MASK          0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_SHIFT         15
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_MASK             0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_SHIFT            14
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_MASK       0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_SHIFT      13
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_MASK        0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_SHIFT       12
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_MASK        0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_SHIFT       11
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_MASK          0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_SHIFT         10
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_MASK             0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_SHIFT            9
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_MASK       0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_SHIFT      8
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_MASK        0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_SHIFT       7
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_MASK        0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_SHIFT       6
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_MASK          0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_SHIFT         5
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_MASK             0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_SHIFT            4
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_MASK       0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_SHIFT      3
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_MASK        0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_SHIFT       2
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_MASK        0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_SHIFT       1
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_MASK          0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_SHIFT         0
+#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_MASK              0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_SHIFT             30
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_MASK           0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_SHIFT          29
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_MASK     0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_SHIFT    28
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_MASK      0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_SHIFT     27
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_MASK      0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_SHIFT     26
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_MASK        0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_SHIFT       25
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_MASK           0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_SHIFT          24
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_MASK     0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_SHIFT    23
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_MASK      0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_SHIFT     22
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_MASK      0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_SHIFT     21
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_MASK        0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_SHIFT       20
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_MASK           0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_SHIFT          19
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_MASK     0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_SHIFT    18
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_MASK      0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_SHIFT     17
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_MASK      0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_SHIFT     16
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_MASK        0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_SHIFT       15
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_MASK           0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_SHIFT          14
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_MASK     0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_SHIFT    13
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_MASK      0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_SHIFT     12
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_MASK      0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_SHIFT     11
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_MASK        0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_SHIFT       10
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_MASK           0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_SHIFT          9
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_MASK     0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_SHIFT    8
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_MASK      0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_SHIFT     7
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_MASK      0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_SHIFT     6
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_MASK        0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_SHIFT       5
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_MASK           0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_SHIFT          4
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_MASK     0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_SHIFT    3
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_MASK      0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_SHIFT     2
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_MASK      0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_SHIFT     1
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_MASK        0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_SHIFT       0
+#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_MASK        0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_SHIFT       30
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_MASK           0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_SHIFT          30
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_MASK   0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_SHIFT  29
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_MASK   0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_SHIFT  24
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_MASK   0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_SHIFT  19
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_MASK   0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_SHIFT  14
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_MASK   0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_SHIFT  9
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_MASK   0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_SHIFT  4
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_MASK         0xc0000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_SHIFT        30
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_MASK             0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_SHIFT            30
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_MASK          0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_SHIFT         29
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_MASK    0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_SHIFT   28
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_MASK     0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_SHIFT    27
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_MASK     0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_SHIFT    26
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_MASK       0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_SHIFT      25
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_MASK          0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_SHIFT         24
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_MASK    0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_SHIFT   23
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_MASK     0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_SHIFT    22
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_MASK     0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_SHIFT    21
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_MASK       0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_SHIFT      20
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_MASK          0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_SHIFT         19
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_MASK    0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_SHIFT   18
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_MASK     0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_SHIFT    17
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_MASK     0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_SHIFT    16
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_MASK       0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_SHIFT      15
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_MASK          0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_SHIFT         14
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_MASK    0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_SHIFT   13
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_MASK     0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_SHIFT    12
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_MASK     0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_SHIFT    11
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_MASK       0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_SHIFT      10
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_MASK          0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_SHIFT         9
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_MASK    0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_SHIFT   8
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_MASK     0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_SHIFT    7
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_MASK     0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_SHIFT    6
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_MASK       0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_SHIFT      5
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_MASK          0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_SHIFT         4
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_MASK    0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_SHIFT   3
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_DEFAULT 0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_MASK     0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_SHIFT    2
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_MASK     0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_SHIFT    1
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_MASK       0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_SHIFT      0
+#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_SET :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_MASK                0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_SHIFT               30
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_MASK             0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_SHIFT            29
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_MASK       0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_SHIFT      28
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_MASK        0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_SHIFT       27
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_MASK        0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_SHIFT       26
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_MASK          0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_SHIFT         25
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_MASK             0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_SHIFT            24
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_MASK       0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_SHIFT      23
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_MASK        0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_SHIFT       22
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_MASK        0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_SHIFT       21
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_MASK          0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_SHIFT         20
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_MASK             0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_SHIFT            19
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_MASK       0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_SHIFT      18
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_MASK        0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_SHIFT       17
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_MASK        0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_SHIFT       16
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_MASK          0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_SHIFT         15
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_MASK             0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_SHIFT            14
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_MASK       0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_SHIFT      13
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_MASK        0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_SHIFT       12
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_MASK        0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_SHIFT       11
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_MASK          0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_SHIFT         10
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_MASK             0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_SHIFT            9
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_MASK       0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_SHIFT      8
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_MASK        0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_SHIFT       7
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_MASK        0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_SHIFT       6
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_MASK          0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_SHIFT         5
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_DEFAULT       0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_MASK             0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_SHIFT            4
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_DEFAULT          0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_MASK       0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_SHIFT      3
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_DEFAULT    0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_MASK        0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_SHIFT       2
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_MASK        0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_SHIFT       1
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_MASK          0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_SHIFT         0
+#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_MASK              0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_SHIFT             30
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_gphy_intr [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_MASK           0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_SHIFT          29
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_off_intr [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_MASK     0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_SHIFT    28
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_on_intr [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_MASK      0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_SHIFT     27
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_down_intr [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_MASK      0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_SHIFT     26
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_up_intr [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_MASK        0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_SHIFT       25
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_gphy_intr [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_MASK           0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_SHIFT          24
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_off_intr [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_MASK     0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_SHIFT    23
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_on_intr [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_MASK      0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_SHIFT     22
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_down_intr [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_MASK      0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_SHIFT     21
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_up_intr [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_MASK        0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_SHIFT       20
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_gphy_intr [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_MASK           0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_SHIFT          19
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_off_intr [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_MASK     0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_SHIFT    18
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_on_intr [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_MASK      0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_SHIFT     17
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_down_intr [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_MASK      0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_SHIFT     16
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_up_intr [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_MASK        0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_SHIFT       15
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_gphy_intr [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_MASK           0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_SHIFT          14
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_off_intr [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_MASK     0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_SHIFT    13
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_on_intr [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_MASK      0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_SHIFT     12
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_down_intr [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_MASK      0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_SHIFT     11
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_up_intr [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_MASK        0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_SHIFT       10
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_gphy_intr [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_MASK           0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_SHIFT          9
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_off_intr [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_MASK     0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_SHIFT    8
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_on_intr [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_MASK      0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_SHIFT     7
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_down_intr [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_MASK      0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_SHIFT     6
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_up_intr [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_MASK        0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_SHIFT       5
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_DEFAULT     0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_gphy_intr [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_MASK           0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_SHIFT          4
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_DEFAULT        0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_off_intr [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_MASK     0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_SHIFT    3
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_DEFAULT  0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_on_intr [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_MASK      0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_SHIFT     2
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_down_intr [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_MASK      0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_SHIFT     1
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_DEFAULT   0x00000000
+
+/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_up_intr [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_MASK        0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_SHIFT       0
+#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_MASK        0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_SHIFT       30
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_MASK           0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_SHIFT          30
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_MASK   0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_SHIFT  29
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_MASK   0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_SHIFT  24
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_MASK   0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_SHIFT  19
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_MASK   0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_SHIFT  14
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_MASK   0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_SHIFT  9
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_MASK   0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_SHIFT  4
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: reserved0 [31:30] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_MASK         0xc0000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_SHIFT        30
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001
+
+/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
+#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_SWITCH_INTRL2_1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_mdio.h b/include/linux/brcmstb/3390a0/bchp_switch_mdio.h
new file mode 100644
index 000000000000..791e391306f0
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_mdio.h
@@ -0,0 +1,119 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Fri Oct 25 17:33:23 2013
+ *                 Full Compile MD5 Checksum 8344a9003ae3c954c1e4a33b9128d4d6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              383dbfcd91460427fa61afa66d6c98f8
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_MDIO_H__
+#define BCHP_SWITCH_MDIO_H__
+
+/***************************************************************************
+ *SWITCH_MDIO
+ ***************************************************************************/
+#define BCHP_SWITCH_MDIO_MDIO_CMD                0x04e403c0 /* MDIO Command Register */
+#define BCHP_SWITCH_MDIO_MDIO_CFG                0x04e403c4 /* MDIO Configuration Register */
+
+/***************************************************************************
+ *MDIO_CMD - MDIO Command Register
+ ***************************************************************************/
+/* SWITCH_MDIO :: MDIO_CMD :: reserved0 [31:30] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_reserved0_MASK                   0xc0000000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_reserved0_SHIFT                  30
+
+/* SWITCH_MDIO :: MDIO_CMD :: mdio_busy [29:29] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_MASK                   0x20000000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_SHIFT                  29
+#define BCHP_SWITCH_MDIO_MDIO_CMD_mdio_busy_DEFAULT                0x00000000
+
+/* SWITCH_MDIO :: MDIO_CMD :: fail [28:28] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_MASK                        0x10000000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_SHIFT                       28
+#define BCHP_SWITCH_MDIO_MDIO_CMD_fail_DEFAULT                     0x00000000
+
+/* SWITCH_MDIO :: MDIO_CMD :: op_code [27:26] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_MASK                     0x0c000000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_SHIFT                    26
+#define BCHP_SWITCH_MDIO_MDIO_CMD_op_code_DEFAULT                  0x00000000
+
+/* SWITCH_MDIO :: MDIO_CMD :: phy_prt_addr [25:21] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_MASK                0x03e00000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_SHIFT               21
+#define BCHP_SWITCH_MDIO_MDIO_CMD_phy_prt_addr_DEFAULT             0x00000000
+
+/* SWITCH_MDIO :: MDIO_CMD :: reg_dec_addr [20:16] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_MASK                0x001f0000
+#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_SHIFT               16
+#define BCHP_SWITCH_MDIO_MDIO_CMD_reg_dec_addr_DEFAULT             0x00000000
+
+/* SWITCH_MDIO :: MDIO_CMD :: data_addr [15:00] */
+#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_MASK                   0x0000ffff
+#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_SHIFT                  0
+#define BCHP_SWITCH_MDIO_MDIO_CMD_data_addr_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MDIO_CFG - MDIO Configuration Register
+ ***************************************************************************/
+/* SWITCH_MDIO :: MDIO_CFG :: reserved0 [31:13] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved0_MASK                   0xffffe000
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved0_SHIFT                  13
+
+/* SWITCH_MDIO :: MDIO_CFG :: supress_preamble [12:12] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_MASK            0x00001000
+#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_SHIFT           12
+#define BCHP_SWITCH_MDIO_MDIO_CFG_supress_preamble_DEFAULT         0x00000000
+
+/* SWITCH_MDIO :: MDIO_CFG :: reserved1 [11:10] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved1_MASK                   0x00000c00
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved1_SHIFT                  10
+
+/* SWITCH_MDIO :: MDIO_CFG :: mdio_clk_divider [09:04] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_MASK            0x000003f0
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_SHIFT           4
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clk_divider_DEFAULT         0x0000000c
+
+/* SWITCH_MDIO :: MDIO_CFG :: reserved2 [03:01] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved2_MASK                   0x0000000e
+#define BCHP_SWITCH_MDIO_MDIO_CFG_reserved2_SHIFT                  1
+
+/* SWITCH_MDIO :: MDIO_CFG :: mdio_clause [00:00] */
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_MASK                 0x00000001
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_SHIFT                0
+#define BCHP_SWITCH_MDIO_MDIO_CFG_mdio_clause_DEFAULT              0x00000001
+
+#endif /* #ifndef BCHP_SWITCH_MDIO_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_switch_reg.h b/include/linux/brcmstb/3390a0/bchp_switch_reg.h
new file mode 100644
index 000000000000..55f6ed61c194
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_switch_reg.h
@@ -0,0 +1,1439 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Jun 21 03:10:17 2014
+ *                 Full Compile MD5 Checksum 2d7cd2763f1ef55897eaef5ea8fc6daa
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              ad87f49099acb161d3ffa5d223fcb978
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_REG_H__
+#define BCHP_SWITCH_REG_H__
+
+/***************************************************************************
+ *SWITCH_REG
+ ***************************************************************************/
+#define BCHP_SWITCH_REG_SWITCH_CNTRL             0x04e40000 /* Switch Control Register */
+#define BCHP_SWITCH_REG_SWITCH_STATUS            0x04e40004 /* Switch Status Register */
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG       0x04e40008 /* Direct Data Write Register */
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG        0x04e4000c /* Direct Data Read Register */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT 0x04e40010 /* LED Serial Refresh Time Unit Register */
+#define BCHP_SWITCH_REG_SWITCH_REVISION          0x04e40018 /* SWITCH Revision Control Register */
+#define BCHP_SWITCH_REG_PHY_REVISION             0x04e4001c /* PHY Revision Control Register */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL           0x04e40020 /* PHY Test Control Register */
+#define BCHP_SWITCH_REG_QPHY_CNTRL               0x04e40024 /* Quad GPHY Control Register */
+#define BCHP_SWITCH_REG_QPHY_STATUS              0x04e40028 /* Quad GPHY Status Register */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL     0x04e40088 /* LED port Blink Rate Control Register */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL         0x04e4008c /* LED Serial Control Register */
+#define BCHP_SWITCH_REG_LED_0_CNTRL              0x04e40090 /* LED port 0 Control Register */
+#define BCHP_SWITCH_REG_LED_1_CNTRL              0x04e40094 /* LED port 1 Control Register */
+#define BCHP_SWITCH_REG_LED_2_CNTRL              0x04e40098 /* LED port 2 Control Register */
+#define BCHP_SWITCH_REG_LED_3_CNTRL              0x04e4009c /* LED port 3 Control Register */
+#define BCHP_SWITCH_REG_LED_4_CNTRL              0x04e400a0 /* LED port 4 Control Register */
+#define BCHP_SWITCH_REG_LED_5_CNTRL              0x04e400a4 /* LED port 5 Control Register */
+#define BCHP_SWITCH_REG_LED_7_CNTRL              0x04e400a8 /* LED port 7 Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL            0x04e400b0 /* RGMII port 9 Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS        0x04e400b4 /* RGMII port 9 InBand Status Register */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL 0x04e400b8 /* RGMII port 9 RX Clock Delay Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL           0x04e400bc /* RGMII port 10 Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS       0x04e400c0 /* RGMII port 10 InBand Status Register */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL 0x04e400c4 /* RGMII port 10 RX Clock Delay Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL     0x04e40150 /* RGMII port 9 ATE RX Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS    0x04e40154 /* RGMII port 9 ATE RX Status Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0   0x04e40158 /* RGMII port 9 ATE TX Control 0 Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1   0x04e4015c /* RGMII port 9 ATE TX Control 1 Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL    0x04e40160 /* RGMII port 10 ATE RX Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS   0x04e40164 /* RGMII port 10 ATE RX Status Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0  0x04e40168 /* RGMII port 10 ATE TX Control 0 Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1  0x04e4016c /* RGMII port 10 ATE TX Control 1 Register */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL      0x04e401a8 /* Aggregate LED Control Register */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL 0x04e401ac /* Aggregate LED Blink Rate Control Register */
+#define BCHP_SWITCH_REG_SPARE_CNTRL              0x04e401b0 /* Spare Control Register */
+
+/***************************************************************************
+ *SWITCH_CNTRL - Switch Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_CNTRL :: reserved0 [31:14] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_MASK                0xffffc000
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_SHIFT               14
+
+/* SWITCH_REG :: SWITCH_CNTRL :: sw_pseudo_phy_addr [13:09] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_MASK       0x00003e00
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_SHIFT      9
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_DEFAULT    0x0000001d
+
+/* SWITCH_REG :: SWITCH_CNTRL :: sw_mdio_en [08:08] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_MASK               0x00000100
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_SHIFT              8
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p5_2_5g_en [07:07] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_MASK               0x00000080
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_SHIFT              7
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p7_2_5g_en [06:06] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_MASK               0x00000040
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_SHIFT              6
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p8_2_5g_en [05:05] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_MASK               0x00000020
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_SHIFT              5
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: moca_bp_en [04:04] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_MASK               0x00000010
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_SHIFT              4
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: pda_mux_sel [03:03] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_MASK              0x00000008
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_SHIFT             3
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_DEFAULT           0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: pda_chain_en [02:02] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_MASK             0x00000004
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_SHIFT            2
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_DEFAULT          0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: spi_dis [01:01] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_MASK                  0x00000002
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_SHIFT                 1
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_DEFAULT               0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: mdio_master_sel [00:00] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_MASK          0x00000001
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_SHIFT         0
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SWITCH_STATUS - Switch Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_STATUS :: reserved0 [31:01] */
+#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_SHIFT              1
+
+/* SWITCH_REG :: SWITCH_STATUS :: sw_init_done [00:00] */
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_MASK            0x00000001
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_SHIFT           0
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DIR_DATA_WRITE_REG - Direct Data Write Register
+ ***************************************************************************/
+/* SWITCH_REG :: DIR_DATA_WRITE_REG :: write_data [31:00] */
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_MASK         0xffffffff
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_SHIFT        0
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_DEFAULT      0x00000000
+
+/***************************************************************************
+ *DIR_DATA_READ_REG - Direct Data Read Register
+ ***************************************************************************/
+/* SWITCH_REG :: DIR_DATA_READ_REG :: read_data [31:00] */
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_MASK           0xffffffff
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_SHIFT          0
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_SERIAL_REFRESH_TIME_UNIT - LED Serial Refresh Time Unit Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_SHIFT 24
+
+/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: refresh_time_unit [23:00] */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_MASK 0x00ffffff
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_SHIFT 0
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_DEFAULT 0x0001e847
+
+/***************************************************************************
+ *SWITCH_REVISION - SWITCH Revision Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_REVISION :: SF2_rev [31:16] */
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_MASK               0xffff0000
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_SHIFT              16
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_REVISION :: switch_top_rev [15:00] */
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_MASK        0x0000ffff
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_SHIFT       0
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PHY_REVISION - PHY Revision Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: PHY_REVISION :: quad_phy_rev [31:16] */
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_MASK             0xffff0000
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_SHIFT            16
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_DEFAULT          0x00000000
+
+/* SWITCH_REG :: PHY_REVISION :: single_phy_rev [15:00] */
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_MASK           0x0000ffff
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_SHIFT          0
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PHY_TEST_CNTRL - PHY Test Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: PHY_TEST_CNTRL :: reserved0 [31:06] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_MASK              0xffffffc0
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_SHIFT             6
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_sel [05:03] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_MASK                0x00000038
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_SHIFT               3
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_DEFAULT             0x00000000
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_mode [02:01] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_MASK          0x00000006
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_SHIFT         1
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_en [00:00] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_MASK            0x00000001
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_SHIFT           0
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_DEFAULT         0x00000000
+
+/***************************************************************************
+ *QPHY_CNTRL - Quad GPHY Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: QPHY_CNTRL :: reserved0 [31:17] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_MASK                  0xfffe0000
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_SHIFT                 17
+
+/* SWITCH_REG :: QPHY_CNTRL :: phy_phyad [16:12] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_MASK                  0x0001f000
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_SHIFT                 12
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_DEFAULT               0x00000001
+
+/* SWITCH_REG :: QPHY_CNTRL :: reserved1 [11:09] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_MASK                  0x00000e00
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_SHIFT                 9
+
+/* SWITCH_REG :: QPHY_CNTRL :: phy_reset [08:08] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_MASK                  0x00000100
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_SHIFT                 8
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_DEFAULT               0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: ck25_dis [07:07] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_MASK                   0x00000080
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_SHIFT                  7
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_DEFAULT                0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: iddq_global_pwr [06:06] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_MASK            0x00000040
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_SHIFT           6
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_DEFAULT         0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: force_dll_en [05:05] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_MASK               0x00000020
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_SHIFT              5
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: ext_pwr_down [04:01] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_MASK               0x0000001e
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_SHIFT              1
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_DEFAULT            0x0000000f
+
+/* SWITCH_REG :: QPHY_CNTRL :: iddq_bias [00:00] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_MASK                  0x00000001
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_SHIFT                 0
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_DEFAULT               0x00000001
+
+/***************************************************************************
+ *QPHY_STATUS - Quad GPHY Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: QPHY_STATUS :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_MASK                 0xffff0000
+#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_SHIFT                16
+
+/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_en [15:15] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_MASK      0x00008000
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_SHIFT     15
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_DEFAULT   0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_mode [14:13] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_MASK    0x00006000
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_SHIFT   13
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_DEFAULT 0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: lock_recovery_clk [12:09] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_MASK         0x00001e00
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_SHIFT        9
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_DEFAULT      0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: pll_lock [08:08] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_MASK                  0x00000100
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_SHIFT                 8
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_DEFAULT               0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: energy_det_apd [07:04] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_MASK            0x000000f0
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_SHIFT           4
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_DEFAULT         0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: energy_det_masked [03:00] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_MASK         0x0000000f
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_SHIFT        0
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_DEFAULT      0x00000000
+
+/***************************************************************************
+ *LED_BLINK_RATE_CNTRL - LED port Blink Rate Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_MASK      0xffff0000
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT     16
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT   0x00000320
+
+/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_MASK     0x0000ffff
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT    0
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT  0x00000320
+
+/***************************************************************************
+ *LED_SERIAL_CNTRL - LED Serial Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_MASK            0xffff0000
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_SHIFT           16
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: port_en [15:08] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_MASK              0x0000ff00
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_SHIFT             8
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: smode [07:07] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_MASK                0x00000080
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_SHIFT               7
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_DEFAULT             0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_frequency [06:06] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_MASK   0x00000040
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_SHIFT  6
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_pol [05:05] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_MASK         0x00000020
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_SHIFT        5
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_DEFAULT      0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: refresh_period [04:00] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_MASK       0x0000001f
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_SHIFT      0
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_DEFAULT    0x00000004
+
+/***************************************************************************
+ *LED_0_CNTRL - LED port 0 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_0_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_0_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_0_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_1_CNTRL - LED port 1 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_1_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_1_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_1_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_2_CNTRL - LED port 2 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_2_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_2_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_2_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_3_CNTRL - LED port 3 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_3_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_3_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_3_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_4_CNTRL - LED port 4 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_4_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_4_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_4_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_5_CNTRL - LED port 5 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_5_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_5_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_5_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_7_CNTRL - LED port 7 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_7_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_7_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_7_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *RGMII_9_CNTRL - RGMII port 9 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_CNTRL :: reserved0 [31:14] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_MASK               0xffffc000
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_SHIFT              14
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: lpi_count [13:09] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_MASK               0x00003e00
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_SHIFT              9
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_DEFAULT            0x0000000f
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: tx_clk_stop_en [08:08] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_MASK          0x00000100
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_SHIFT         8
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: tx_pause_en [07:07] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_MASK             0x00000080
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_SHIFT            7
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rx_pause_en [06:06] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_MASK             0x00000040
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_SHIFT            6
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rvmii_ref_sel [05:05] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_MASK           0x00000020
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_SHIFT          5
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: port_mode [04:02] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_MASK               0x0000001c
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_SHIFT              2
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_DEFAULT            0x00000003
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: id_mode_dis [01:01] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_MASK             0x00000002
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_SHIFT            1
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rgmii_mode_en [00:00] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_MASK           0x00000001
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_SHIFT          0
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RGMII_9_IB_STATUS - RGMII port 9 InBand Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: reserved0 [31:04] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_MASK           0xfffffff0
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_SHIFT          4
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: link_decode [03:03] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_MASK         0x00000008
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_SHIFT        3
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_DEFAULT      0x00000000
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: duplex_decode [02:02] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_MASK       0x00000004
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_SHIFT      2
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_DEFAULT    0x00000000
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: speed_decode [01:00] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_MASK        0x00000003
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_SHIFT       0
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RGMII_9_RX_CLOCK_DELAY_CNTRL - RGMII port 9 RX Clock Delay Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK  0x00000040
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_MASK   0x00000020
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT  5
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_MASK     0x00000010
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT    4
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_MASK     0x0000000c
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_SHIFT    2
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT  0x00000002
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_MASK     0x00000003
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT    0
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RGMII_10_CNTRL - RGMII port 10 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_CNTRL :: reserved0 [31:14] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_MASK              0xffffc000
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_SHIFT             14
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: lpi_count [13:09] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_MASK              0x00003e00
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_SHIFT             9
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_DEFAULT           0x0000000f
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: tx_clk_stop_en [08:08] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_MASK         0x00000100
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_SHIFT        8
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_DEFAULT      0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: tx_pause_en [07:07] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_MASK            0x00000080
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_SHIFT           7
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rx_pause_en [06:06] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_MASK            0x00000040
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_SHIFT           6
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rvmii_ref_sel [05:05] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_MASK          0x00000020
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_SHIFT         5
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: port_mode [04:02] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_MASK              0x0000001c
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_SHIFT             2
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_DEFAULT           0x00000003
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: id_mode_dis [01:01] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_MASK            0x00000002
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_SHIFT           1
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rgmii_mode_en [00:00] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_MASK          0x00000001
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_SHIFT         0
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_DEFAULT       0x00000000
+
+/***************************************************************************
+ *RGMII_10_IB_STATUS - RGMII port 10 InBand Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: reserved0 [31:04] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_MASK          0xfffffff0
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_SHIFT         4
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: link_decode [03:03] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_MASK        0x00000008
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_SHIFT       3
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: duplex_decode [02:02] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_MASK      0x00000004
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_SHIFT     2
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_DEFAULT   0x00000000
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: speed_decode [01:00] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_MASK       0x00000003
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_SHIFT      0
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RGMII_10_RX_CLOCK_DELAY_CNTRL - RGMII port 10 RX Clock Delay Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK 0x00000040
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_MASK  0x00000020
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT 5
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_MASK    0x00000010
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT   4
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_MASK    0x0000000c
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_SHIFT   2
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT 0x00000002
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_MASK    0x00000003
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT   0
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_RX_CNTRL - RGMII port 9 ATE RX Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_MASK        0xff000000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_SHIFT       24
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: ate_en [23:23] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_MASK           0x00800000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_SHIFT          23
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: good_count [22:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_MASK       0x007c0000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_SHIFT      18
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_DEFAULT    0x00000004
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_MASK  0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_MASK  0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_RX_STATUS - RGMII port 9 ATE RX Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: reserved0 [31:19] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_MASK       0xfff80000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_SHIFT      19
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: rx_ok [18:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_MASK           0x00040000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_SHIFT          18
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_TX_CNTRL_0 - RGMII port 9 ATE TX Control 0 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_MASK      0xfffffffc
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_SHIFT     2
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop [01:01] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_MASK     0x00000002
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_SHIFT    1
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_TX_CNTRL_1 - RGMII port 9 ATE TX Control 1 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_MASK      0xfffc0000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_SHIFT     18
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_MASK      0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_SHIFT     9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_DEFAULT   0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_MASK      0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_SHIFT     0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_RX_CNTRL - RGMII port 10 ATE RX Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_MASK       0xff000000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_SHIFT      24
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: ate_en [23:23] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_MASK          0x00800000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_SHIFT         23
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: good_count [22:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_MASK      0x007c0000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_SHIFT     18
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_DEFAULT   0x00000004
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_RX_STATUS - RGMII port 10 ATE RX Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: reserved0 [31:19] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_MASK      0xfff80000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_SHIFT     19
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: rx_ok [18:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_MASK          0x00040000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_SHIFT         18
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_TX_CNTRL_0 - RGMII port 10 ATE TX Control 0 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_MASK     0xfffffffc
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_SHIFT    2
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop [01:01] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_MASK    0x00000002
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_SHIFT   1
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_TX_CNTRL_1 - RGMII port 10 ATE TX Control 1 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_MASK     0xfffc0000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_SHIFT    18
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_MASK     0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_SHIFT    9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_MASK     0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_SHIFT    0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AGGREGATE_LED_CNTRL - Aggregate LED Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: reserved0 [31:14] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_MASK         0xffffc000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_SHIFT        14
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: lnk_pol_sel [13:13] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_MASK       0x00002000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_SHIFT      13
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_pol_sel [12:12] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_MASK       0x00001000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_SHIFT      12
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_sel [11:11] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_MASK           0x00000800
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_SHIFT          11
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_tx_en_en [10:10] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_MASK       0x00000400
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_SHIFT      10
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_DEFAULT    0x00000001
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_rx_dv_en [09:09] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_MASK       0x00000200
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_SHIFT      9
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_DEFAULT    0x00000001
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: port_en [08:00] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_MASK           0x000001ff
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_SHIFT          0
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_DEFAULT        0x00000000
+
+/***************************************************************************
+ *AGGREGATE_LED_BLINK_RATE_CNTRL - Aggregate LED Blink Rate Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_MASK 0xffff0000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT 16
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT 0x00000320
+
+/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_MASK 0x0000ffff
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT 0
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT 0x00000320
+
+/***************************************************************************
+ *SPARE_CNTRL - Spare Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SPARE_CNTRL :: spare_reg [31:00] */
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_MASK                 0xffffffff
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_SHIFT                0
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_REG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390a0/bchp_usb_ctrl.h b/include/linux/brcmstb/3390a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..7fd36f9f9d9b
--- /dev/null
+++ b/include/linux/brcmstb/3390a0/bchp_usb_ctrl.h
@@ -0,0 +1,1670 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sun Sep 14 03:14:49 2014
+ *                 Full Compile MD5 Checksum ef22086ebd4065e4fea50dbc64f17e5e
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              39fcae49037a6337517df43bfc24b21f
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x21000200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x21000204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x21000208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x2100020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x21000210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x21000214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x21000218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x2100021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x21000220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x21000224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x21000228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x2100022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x21000230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_USB_PM                     0x21000234 /* Power Management Register */
+#define BCHP_USB_CTRL_USB_PM_STATUS              0x21000238 /* usb20 Power Management Status Register */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT              0x2100023c /* OHCI ADDRESS Extension */
+#define BCHP_USB_CTRL_PLL_LDO_CTL                0x21000240 /* 28NM USBPHY LDO Control */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS            0x21000244 /* 28NM USBPHY PLLBIAS Control */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL            0x21000248 /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_AFE_USBIO_TST              0x2100024c /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC              0x21000250 /* PLL Feedback Divider Control Register */
+#define BCHP_USB_CTRL_TP_DIAG                    0x21000254 /* diagnostic for tp bus */
+#define BCHP_USB_CTRL_SPARE3                     0x21000258 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE4                     0x2100025c /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_USB30_CTL1                 0x21000260 /* USB30 CONTROL Register 1 */
+#define BCHP_USB_CTRL_USB30_CTL2                 0x21000264 /* USB30 CONTROL Register 2 */
+#define BCHP_USB_CTRL_USB30_CTL3                 0x21000268 /* USB30 CONTROL Register 3 */
+#define BCHP_USB_CTRL_USB30_CTL4                 0x2100026c /* USB30 CONTROL Register 4 */
+#define BCHP_USB_CTRL_USB30_PCTL                 0x21000270 /* USB30 PORT CONTROL Register */
+#define BCHP_USB_CTRL_USB30_CTL5                 0x21000274 /* USB30 CONTROL Register 5 */
+#define BCHP_USB_CTRL_SPARE5                     0x21000278 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE6                     0x2100027c /* Spare2 Register for future use */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1            0x21000290 /* USB DEVICE  CONTROL Register 1 */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE            0x210002a0 /* SCB0 base start and end address */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE            0x210002a4 /* SCB1 base start and end address */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE            0x210002a8 /* SCB2 base start and end address */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE            0x210002ac /* SCB0 extn start and end address */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE            0x210002b0 /* SCB1 extn start and end address */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE            0x210002b4 /* SCB2 extn start and end address */
+#define BCHP_USB_CTRL_USB20_ID                   0x210002f0 /* USB REVID */
+#define BCHP_USB_CTRL_USB30_ID                   0x210002f4 /* USB REVID */
+#define BCHP_USB_CTRL_BDC_COREID                 0x210002f8 /* USB REVID */
+#define BCHP_USB_CTRL_USB_REVID                  0x210002fc /* USB REVID */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK                       0xc0000000
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT                      30
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0x30000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK                   0x08000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT                  27
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK                     0x04000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT                    26
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: strap_ipp_sel [25:25] */
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_MASK                     0x02000000
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_SHIFT                    25
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:20] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01f00000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      20
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK                    0x00080000
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT                   19
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                   0x00040000
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                  18
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK                   0x00020000
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT                  17
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT                0x00000001
+
+/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00010000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 16
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: scb2_en [15:15] */
+#define BCHP_USB_CTRL_SETUP_scb2_en_MASK                           0x00008000
+#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT                          15
+#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT                        0x00000000
+
+/* USB_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb0_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb0_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00001000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  12
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: setup_spare1 [11:10] */
+#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK                      0x00000c00
+#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT                     10
+#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_CTL_SPARE1 [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000004
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x0000f000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000020
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000001
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000001
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:19] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ff80000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      19
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: ohci_memreq_disable [18:18] */
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_MASK             0x00040000
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_SHIFT            18
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_DEFAULT          0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0x7c000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: MDIO2_SPARE [31:16] */
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_MASK                       0xffff0000
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_SHIFT                      16
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0xf0000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              28
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK          0x08000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT         27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK               0x01800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT              23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK            0x00600000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT           21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK                0x00080000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT               19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK            0x00040000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT           18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK            0x00020000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT           17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK                  0x00010000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                 16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT               0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: PHY_TPOUT_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0             0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1             1
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2             2
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3             3
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4             4
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5             5
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6             6
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7             7
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8             8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9             9
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10            10
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11            11
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12            12
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13            13
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14            14
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15            15
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17            17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18            18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19            19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23            23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24            24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25            25
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffc00
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                10
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK              0x00000200
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT             9
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [08:07] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK                0x00000180
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT               7
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK                  0x00000040
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT                 6
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT                5
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK                0x00000010
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT               4
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x0000000f
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK              0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT             21
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK                 0x80000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT                31
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK                 0x40000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT                30
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT                29
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0x1fffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK           0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT          27
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK              0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT             26
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK       0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT      25
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK        0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT       24
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT     0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host                  0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device                1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG                   2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10                  3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK              0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT             11
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT           0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK                 0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT                10
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK          0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT         9
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT       0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK           0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT          8
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host                     0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device                   1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG                      2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10                     3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB_PM - Power Management Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM :: USB_PWRDN [31:31] */
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK                        0x80000000
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_SHIFT                       31
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_DEFAULT                     0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE2 [30:28] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_MASK                    0x70000000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_SHIFT                   28
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_p1 [27:27] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_MASK                      0x08000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_SHIFT                     27
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_p0 [26:26] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_MASK                      0x04000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_SHIFT                     26
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_usb30 [25:25] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_MASK                   0x02000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_SHIFT                  25
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_usb30_p1 [24:24] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_MASK                0x01000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_SHIFT               24
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: xdc_soft_resetb [23:23] */
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK                  0x00800000
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT                 23
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_soft_resetb [22:22] */
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK                  0x00400000
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT                 22
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [21:21] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT                21
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [20:20] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK                 0x00100000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT                20
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [19:16] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK                    0x000f0000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT                   16
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK            0x00008000
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT           15
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK            0x00004000
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT           14
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK                     0x00003fe0
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT                    5
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK                       0x00000010
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT                      4
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK                0x00000008
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT               3
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK                0x00000004
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT               2
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK                      0x00000002
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT                     1
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK                       0x00000001
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT                      0
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *USB_PM_STATUS - usb20 Power Management Status Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK               0xffff0000
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT              16
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK                 0x0000ffff
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT                0
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *OHCI_ADDR_EXT - OHCI ADDRESS Extension
+ ***************************************************************************/
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK           0xffffff00
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT          8
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK             0x000000ff
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT            0
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_LDO_CTL - 28NM USBPHY LDO Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK            0xffff0000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT           16
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT         0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK                0x0000f000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT               12
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK                0x00000f00
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT               8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK               0x000000f8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT              3
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK            0x00000004
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT           2
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT         0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK             0x00000002
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT            1
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT          0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK              0x00000001
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT             0
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK           0xfffc0000
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT          18
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK    0x0003ffff
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT   0
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK        0xfffe0000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT       17
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT     0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK             0x0001f000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT            12
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT          0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK     0x0000000f
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT    0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK           0x80000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT          31
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT        0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK                   0x40000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT                  30
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT                0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK       0x3fff0000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT      16
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT    0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK          0x0000ff00
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT         8
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT       0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK          0x000000ff
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT         0
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK      0xfff00000
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT     20
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT   0x00000000
+
+/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK             0x000fffff
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT            0
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TP_DIAG - diagnostic for tp bus
+ ***************************************************************************/
+/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK                    0xffffffff
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT                   0
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SPARE3 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE4 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB30_CTL1 - USB30 CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:23] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK            0xff800000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT           23
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_rxelectidle_sel [22:22] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_MASK        0x00400000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_SHIFT       22
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT      21
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK            0x00100000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT           20
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK                  0x00080000
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT                 19
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK                   0x00040000
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT                  18
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK                    0x00020000
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT                   17
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK                  0x00010000
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT                 16
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK            0x0000ff80
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT           7
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK          0x00000040
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT         6
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT                5
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK           0x00000010
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK          0x0000000e
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT         1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT       0x00000004
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk    0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL          1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N     2
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk   4
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK          0x00000001
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT         0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *USB30_CTL2 - USB30 CONTROL Register 2
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK            0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT         0x00000020
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK          0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT         16
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK          0x0000ff00
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT         8
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK            0x000000f8
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT           3
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK          0x00000004
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT         2
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_CTL3 - USB30 CONTROL Register 3
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK     0x20000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT    29
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK        0x1f000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT       24
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT     0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK        0x00f00000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT       20
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT     0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK           0x00080000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT          19
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK     0x00040000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT    18
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK         0x00020000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT        17
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT      0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK            0x00010000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK            0x0000c000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT           14
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK        0x00002000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT       13
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK           0x00001f00
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT          8
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT        0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK           0x000000f0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT        0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK              0x00000008
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT             3
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK        0x00000004
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT       2
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK            0x00000002
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT           1
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK               0x00000001
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT            0x00000001
+
+/***************************************************************************
+ *USB30_CTL4 - USB30 CONTROL Register 4
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL4 :: phy3_phystatus_override [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_MASK      0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_SHIFT     30
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: phy3_rxstatus_override [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_MASK       0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_SHIFT      24
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK            0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_PCTL - USB30 PORT CONTROL Register
+ ***************************************************************************/
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK             0xe0000000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT            29
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK           0x10000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT          28
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT      21
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK       0x00100000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT      20
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK                 0x000c0000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT                18
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK      0x00010000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT     16
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK           0x00008000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT          15
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK             0x00006000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT            13
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK              0x00001000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT             12
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT           0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK    0x00000100
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT   8
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK    0x00000080
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT   7
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK    0x00000040
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT   6
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK          0x00000020
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT         5
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK          0x00000010
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT         4
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK                    0x0000000c
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT                   2
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK         0x00000001
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT        0
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT      0x00000000
+
+/***************************************************************************
+ *USB30_CTL5 - USB30 CONTROL Register 5
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK                   0xffffffff
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT                  0
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPARE5 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE6 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB_DEVICE_CTL1 - USB DEVICE  CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare3 [31:20] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_MASK  0xfff00000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_SHIFT 20
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_spd [19:17] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_MASK      0x000e0000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_SHIFT     17
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_ndr [16:16] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_MASK      0x00010000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_SHIFT     16
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_DEFAULT   0x00000001
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare2 [15:11] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_MASK  0x0000f800
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_SHIFT 11
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_vdd_retention [10:10] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_MASK 0x00000400
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_SHIFT 10
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_rmt_wkup [09:09] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_MASK     0x00000200
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_SHIFT    9
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_buspwr [08:08] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_MASK   0x00000100
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_SHIFT  8
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare1 [07:04] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_MASK  0x000000f0
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_SHIFT 4
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: device_pullup_dis [03:03] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_MASK       0x00000008
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_SHIFT      3
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usbphy_host_override [02:02] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_MASK    0x00000004
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_SHIFT   2
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: port_mode [01:00] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCB0_BASE_RANGE - SCB0 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT   0x00000007
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCB1_BASE_RANGE - SCB1 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB2_BASE_RANGE - SCB2 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT   0x0000000f
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *SCB0_EXTN_RANGE - SCB0 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT   0x0000001b
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010
+
+/***************************************************************************
+ *SCB1_EXTN_RANGE - SCB1 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT   0x0000003b
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030
+
+/***************************************************************************
+ *SCB2_EXTN_RANGE - SCB2 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT   0x000000cb
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0
+
+/***************************************************************************
+ *USB20_ID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB20_ID :: USB20PHY_ID [31:16] */
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_MASK                    0xffff0000
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_SHIFT                   16
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_DEFAULT                 0x0000d034
+
+/* USB_CTRL :: USB20_ID :: SYNOPSYS_CORE_ID [15:00] */
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_SHIFT              0
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_DEFAULT            0x0000298a
+
+/***************************************************************************
+ *USB30_ID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB30_ID :: USB30PHY_ID [31:16] */
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_MASK                    0xffff0000
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_SHIFT                   16
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_DEFAULT                 0x0000c000
+
+/* USB_CTRL :: USB30_ID :: XHC_CORE_ID [15:00] */
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_MASK                    0x0000ffff
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_SHIFT                   0
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_DEFAULT                 0x00000200
+
+/***************************************************************************
+ *BDC_COREID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: BDC_COREID :: BDC3_COREID [31:16] */
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_SHIFT                 16
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_DEFAULT               0x0000c000
+
+/* USB_CTRL :: BDC_COREID :: BDC2_COREID [15:00] */
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_MASK                  0x0000ffff
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_SHIFT                 0
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_DEFAULT               0x00000200
+
+/***************************************************************************
+ *USB_REVID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK                     0xffffffff
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT                    0
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT                  0x00000001
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_bspi.h b/include/linux/brcmstb/3390b0/bchp_bspi.h
new file mode 100644
index 000000000000..d5c5f53248f7
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_bspi.h
@@ -0,0 +1,436 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:13 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x204a3200 /* [RO] Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x204a3204 /* [RW] Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x204a3208 /* [RW] Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x204a320c /* [RO] BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x204a3210 /* [RO] Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x204a3214 /* [RO] Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x204a3218 /* [WO] Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x204a321c /* [RO] Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x204a3220 /* [WO] Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x204a3224 /* [RW] Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x204a3228 /* [RW] Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x204a322c /* [RW] Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x204a3230 /* [RW] Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x204a3234 /* [RW] Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x204a3238 /* [RW] Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x204a323c /* [RW] BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x204a3240 /* [RW] BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x204a3244 /* [RW] BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x204a3248 /* [RW] BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x204a324c /* [RW] BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000002
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000e00
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000001
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_bspi_raf.h b/include/linux/brcmstb/3390b0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..b7efe69bfbd2
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_bspi_raf.h
@@ -0,0 +1,153 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Wed Jun 10 03:09:40 2015
+ *                 Full Compile MD5 Checksum  e8bde4108283f67d401938287dbb6bde
+ *                     (minus title and desc)
+ *                 MD5 Checksum               56f0f944fbd407545cd964e7b4e7f7b0
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008008
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x204a3300 /* [RW] Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x204a3304 /* [RW] Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x204a3308 /* [RW] RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x204a330c /* [RO] Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x204a3310 /* [RW] Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x204a3314 /* [RO] Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x204a3318 /* [RO] Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x204a331c /* [RO] Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x204a3320 /* [RO] Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_common.h b/include/linux/brcmstb/3390b0/bchp_common.h
new file mode 100644
index 000000000000..5d401052aee2
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_common.h
@@ -0,0 +1,6254 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Wed Jun 10 03:09:12 2015
+ *                 Full Compile MD5 Checksum  e8bde4108283f67d401938287dbb6bde
+ *                     (minus title and desc)
+ *                 MD5 Checksum               56f0f944fbd407545cd964e7b4e7f7b0
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008008
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM3390_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0xd0000000
+#define BCHP_REGISTER_START                                0x000000e0 /* MC_BPM_CTRL_0 is first */
+#define BCHP_REGISTER_END                                  0x21504d1c /* PHY_ECC_LANE_0 is last */
+#define BCHP_REGISTER_SIZE                                 0x0854130f /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_MC_BPM_CTRL_0_REG_START                       0x000000e0
+#define BCHP_MC_BPM_CTRL_0_REG_END                         0x000000e4
+#define BCHP_MBDMA_UNI3_REG_START                          0x00400000
+#define BCHP_MBDMA_UNI3_REG_END                            0x00400508
+#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_START              0x00400600
+#define BCHP_UNIMAC_INTERFACE0_UNI3_REG_END                0x00400714
+#define BCHP_UNIMAC_CORE0_UNI3_REG_START                   0x00400800
+#define BCHP_UNIMAC_CORE0_UNI3_REG_END                     0x00400b44
+#define BCHP_MIB0_UNI3_REG_START                           0x00400c00
+#define BCHP_MIB0_UNI3_REG_END                             0x00400cf4
+#define BCHP_HFB0_UNI3_REG_START                           0x00401000
+#define BCHP_HFB0_UNI3_REG_END                             0x00401ffc
+#define BCHP_BaseReserved_UTP_REG_START                    0x00a00000
+#define BCHP_BaseReserved_UTP_REG_END                      0x00a00000
+#define BCHP_Control_UTP_REG_START                         0x00a01000
+#define BCHP_Control_UTP_REG_END                           0x00a010fc
+#define BCHP_OutgoingMessageFIFO_UTP_REG_START             0x00a01100
+#define BCHP_OutgoingMessageFIFO_UTP_REG_END               0x00a0117c
+#define BCHP_IncomingMessageFIFO_UTP_REG_START             0x00a01200
+#define BCHP_IncomingMessageFIFO_UTP_REG_END               0x00a0127c
+#define BCHP_DMA0_UTP_REG_START                            0x00a01300
+#define BCHP_DMA0_UTP_REG_END                              0x00a0131c
+#define BCHP_DMA1_UTP_REG_START                            0x00a01320
+#define BCHP_DMA1_UTP_REG_END                              0x00a0133c
+#define BCHP_DMAHI0_UTP_REG_START                          0x00a01340
+#define BCHP_DMAHI0_UTP_REG_END                            0x00a0134c
+#define BCHP_DMAHI1_UTP_REG_START                          0x00a01350
+#define BCHP_DMAHI1_UTP_REG_END                            0x00a0135c
+#define BCHP_Token_UTP_REG_START                           0x00a01400
+#define BCHP_Token_UTP_REG_END                             0x00a01420
+#define BCHP_PerfPower_UTP_REG_START                       0x00a01600
+#define BCHP_PerfPower_UTP_REG_END                         0x00a01640
+#define BCHP_MessageID_UTP_REG_START                       0x00a01700
+#define BCHP_MessageID_UTP_REG_END                         0x00a0177c
+#define BCHP_HWCounters_UTP_REG_START                      0x00a01900
+#define BCHP_HWCounters_UTP_REG_END                        0x00a01944
+#define BCHP_DQM_0_31_UTP_REG_START                        0x00a01c00
+#define BCHP_DQM_0_31_UTP_REG_END                          0x00a01c48
+#define BCHP_DQM_32_63_UTP_REG_START                       0x00a01d00
+#define BCHP_DQM_32_63_UTP_REG_END                         0x00a01d48
+#define BCHP_QUEUE_TIMER_UTP_REG_START                     0x00a02000
+#define BCHP_QUEUE_TIMER_UTP_REG_END                       0x00a021fc
+#define BCHP_QUEUE_STATUS_0_31_UTP_REG_START               0x00a02800
+#define BCHP_QUEUE_STATUS_0_31_UTP_REG_END                 0x00a0287c
+#define BCHP_QUEUE_STATUS_32_63_UTP_REG_START              0x00a02900
+#define BCHP_QUEUE_STATUS_32_63_UTP_REG_END                0x00a0297c
+#define BCHP_QUEUE_MIB_0_31_UTP_REG_START                  0x00a03000
+#define BCHP_QUEUE_MIB_0_31_UTP_REG_END                    0x00a0317c
+#define BCHP_QUEUE_MIB_32_63_UTP_REG_START                 0x00a03200
+#define BCHP_QUEUE_MIB_32_63_UTP_REG_END                   0x00a0337c
+#define BCHP_QUEUE_0_CNTRL_UTP_REG_START                   0x00a04000
+#define BCHP_QUEUE_0_CNTRL_UTP_REG_END                     0x00a0400c
+#define BCHP_QUEUE_1_CNTRL_UTP_REG_START                   0x00a04010
+#define BCHP_QUEUE_1_CNTRL_UTP_REG_END                     0x00a0401c
+#define BCHP_QUEUE_2_CNTRL_UTP_REG_START                   0x00a04020
+#define BCHP_QUEUE_2_CNTRL_UTP_REG_END                     0x00a0402c
+#define BCHP_QUEUE_3_CNTRL_UTP_REG_START                   0x00a04030
+#define BCHP_QUEUE_3_CNTRL_UTP_REG_END                     0x00a0403c
+#define BCHP_QUEUE_4_CNTRL_UTP_REG_START                   0x00a04040
+#define BCHP_QUEUE_4_CNTRL_UTP_REG_END                     0x00a0404c
+#define BCHP_QUEUE_5_CNTRL_UTP_REG_START                   0x00a04050
+#define BCHP_QUEUE_5_CNTRL_UTP_REG_END                     0x00a0405c
+#define BCHP_QUEUE_6_CNTRL_UTP_REG_START                   0x00a04060
+#define BCHP_QUEUE_6_CNTRL_UTP_REG_END                     0x00a0406c
+#define BCHP_QUEUE_7_CNTRL_UTP_REG_START                   0x00a04070
+#define BCHP_QUEUE_7_CNTRL_UTP_REG_END                     0x00a0407c
+#define BCHP_QUEUE_8_CNTRL_UTP_REG_START                   0x00a04080
+#define BCHP_QUEUE_8_CNTRL_UTP_REG_END                     0x00a0408c
+#define BCHP_QUEUE_9_CNTRL_UTP_REG_START                   0x00a04090
+#define BCHP_QUEUE_9_CNTRL_UTP_REG_END                     0x00a0409c
+#define BCHP_QUEUE_10_CNTRL_UTP_REG_START                  0x00a040a0
+#define BCHP_QUEUE_10_CNTRL_UTP_REG_END                    0x00a040ac
+#define BCHP_QUEUE_11_CNTRL_UTP_REG_START                  0x00a040b0
+#define BCHP_QUEUE_11_CNTRL_UTP_REG_END                    0x00a040bc
+#define BCHP_QUEUE_12_CNTRL_UTP_REG_START                  0x00a040c0
+#define BCHP_QUEUE_12_CNTRL_UTP_REG_END                    0x00a040cc
+#define BCHP_QUEUE_13_CNTRL_UTP_REG_START                  0x00a040d0
+#define BCHP_QUEUE_13_CNTRL_UTP_REG_END                    0x00a040dc
+#define BCHP_QUEUE_14_CNTRL_UTP_REG_START                  0x00a040e0
+#define BCHP_QUEUE_14_CNTRL_UTP_REG_END                    0x00a040ec
+#define BCHP_QUEUE_15_CNTRL_UTP_REG_START                  0x00a040f0
+#define BCHP_QUEUE_15_CNTRL_UTP_REG_END                    0x00a040fc
+#define BCHP_QUEUE_16_CNTRL_UTP_REG_START                  0x00a04100
+#define BCHP_QUEUE_16_CNTRL_UTP_REG_END                    0x00a0410c
+#define BCHP_QUEUE_17_CNTRL_UTP_REG_START                  0x00a04110
+#define BCHP_QUEUE_17_CNTRL_UTP_REG_END                    0x00a0411c
+#define BCHP_QUEUE_18_CNTRL_UTP_REG_START                  0x00a04120
+#define BCHP_QUEUE_18_CNTRL_UTP_REG_END                    0x00a0412c
+#define BCHP_QUEUE_19_CNTRL_UTP_REG_START                  0x00a04130
+#define BCHP_QUEUE_19_CNTRL_UTP_REG_END                    0x00a0413c
+#define BCHP_QUEUE_20_CNTRL_UTP_REG_START                  0x00a04140
+#define BCHP_QUEUE_20_CNTRL_UTP_REG_END                    0x00a0414c
+#define BCHP_QUEUE_21_CNTRL_UTP_REG_START                  0x00a04150
+#define BCHP_QUEUE_21_CNTRL_UTP_REG_END                    0x00a0415c
+#define BCHP_QUEUE_22_CNTRL_UTP_REG_START                  0x00a04160
+#define BCHP_QUEUE_22_CNTRL_UTP_REG_END                    0x00a0416c
+#define BCHP_QUEUE_23_CNTRL_UTP_REG_START                  0x00a04170
+#define BCHP_QUEUE_23_CNTRL_UTP_REG_END                    0x00a0417c
+#define BCHP_QUEUE_24_CNTRL_UTP_REG_START                  0x00a04180
+#define BCHP_QUEUE_24_CNTRL_UTP_REG_END                    0x00a0418c
+#define BCHP_QUEUE_25_CNTRL_UTP_REG_START                  0x00a04190
+#define BCHP_QUEUE_25_CNTRL_UTP_REG_END                    0x00a0419c
+#define BCHP_QUEUE_26_CNTRL_UTP_REG_START                  0x00a041a0
+#define BCHP_QUEUE_26_CNTRL_UTP_REG_END                    0x00a041ac
+#define BCHP_QUEUE_27_CNTRL_UTP_REG_START                  0x00a041b0
+#define BCHP_QUEUE_27_CNTRL_UTP_REG_END                    0x00a041bc
+#define BCHP_QUEUE_28_CNTRL_UTP_REG_START                  0x00a041c0
+#define BCHP_QUEUE_28_CNTRL_UTP_REG_END                    0x00a041cc
+#define BCHP_QUEUE_29_CNTRL_UTP_REG_START                  0x00a041d0
+#define BCHP_QUEUE_29_CNTRL_UTP_REG_END                    0x00a041dc
+#define BCHP_QUEUE_30_CNTRL_UTP_REG_START                  0x00a041e0
+#define BCHP_QUEUE_30_CNTRL_UTP_REG_END                    0x00a041ec
+#define BCHP_QUEUE_31_CNTRL_UTP_REG_START                  0x00a041f0
+#define BCHP_QUEUE_31_CNTRL_UTP_REG_END                    0x00a041fc
+#define BCHP_QUEUE_32_CNTRL_UTP_REG_START                  0x00a04200
+#define BCHP_QUEUE_32_CNTRL_UTP_REG_END                    0x00a0420c
+#define BCHP_QUEUE_33_CNTRL_UTP_REG_START                  0x00a04210
+#define BCHP_QUEUE_33_CNTRL_UTP_REG_END                    0x00a0421c
+#define BCHP_QUEUE_34_CNTRL_UTP_REG_START                  0x00a04220
+#define BCHP_QUEUE_34_CNTRL_UTP_REG_END                    0x00a0422c
+#define BCHP_QUEUE_35_CNTRL_UTP_REG_START                  0x00a04230
+#define BCHP_QUEUE_35_CNTRL_UTP_REG_END                    0x00a0423c
+#define BCHP_QUEUE_36_CNTRL_UTP_REG_START                  0x00a04240
+#define BCHP_QUEUE_36_CNTRL_UTP_REG_END                    0x00a0424c
+#define BCHP_QUEUE_37_CNTRL_UTP_REG_START                  0x00a04250
+#define BCHP_QUEUE_37_CNTRL_UTP_REG_END                    0x00a0425c
+#define BCHP_QUEUE_38_CNTRL_UTP_REG_START                  0x00a04260
+#define BCHP_QUEUE_38_CNTRL_UTP_REG_END                    0x00a0426c
+#define BCHP_QUEUE_39_CNTRL_UTP_REG_START                  0x00a04270
+#define BCHP_QUEUE_39_CNTRL_UTP_REG_END                    0x00a0427c
+#define BCHP_QUEUE_40_CNTRL_UTP_REG_START                  0x00a04280
+#define BCHP_QUEUE_40_CNTRL_UTP_REG_END                    0x00a0428c
+#define BCHP_QUEUE_41_CNTRL_UTP_REG_START                  0x00a04290
+#define BCHP_QUEUE_41_CNTRL_UTP_REG_END                    0x00a0429c
+#define BCHP_QUEUE_42_CNTRL_UTP_REG_START                  0x00a042a0
+#define BCHP_QUEUE_42_CNTRL_UTP_REG_END                    0x00a042ac
+#define BCHP_QUEUE_43_CNTRL_UTP_REG_START                  0x00a042b0
+#define BCHP_QUEUE_43_CNTRL_UTP_REG_END                    0x00a042bc
+#define BCHP_QUEUE_44_CNTRL_UTP_REG_START                  0x00a042c0
+#define BCHP_QUEUE_44_CNTRL_UTP_REG_END                    0x00a042cc
+#define BCHP_QUEUE_45_CNTRL_UTP_REG_START                  0x00a042d0
+#define BCHP_QUEUE_45_CNTRL_UTP_REG_END                    0x00a042dc
+#define BCHP_QUEUE_46_CNTRL_UTP_REG_START                  0x00a042e0
+#define BCHP_QUEUE_46_CNTRL_UTP_REG_END                    0x00a042ec
+#define BCHP_QUEUE_47_CNTRL_UTP_REG_START                  0x00a042f0
+#define BCHP_QUEUE_47_CNTRL_UTP_REG_END                    0x00a042fc
+#define BCHP_QUEUE_48_CNTRL_UTP_REG_START                  0x00a04300
+#define BCHP_QUEUE_48_CNTRL_UTP_REG_END                    0x00a0430c
+#define BCHP_QUEUE_49_CNTRL_UTP_REG_START                  0x00a04310
+#define BCHP_QUEUE_49_CNTRL_UTP_REG_END                    0x00a0431c
+#define BCHP_QUEUE_50_CNTRL_UTP_REG_START                  0x00a04320
+#define BCHP_QUEUE_50_CNTRL_UTP_REG_END                    0x00a0432c
+#define BCHP_QUEUE_51_CNTRL_UTP_REG_START                  0x00a04330
+#define BCHP_QUEUE_51_CNTRL_UTP_REG_END                    0x00a0433c
+#define BCHP_QUEUE_52_CNTRL_UTP_REG_START                  0x00a04340
+#define BCHP_QUEUE_52_CNTRL_UTP_REG_END                    0x00a0434c
+#define BCHP_QUEUE_53_CNTRL_UTP_REG_START                  0x00a04350
+#define BCHP_QUEUE_53_CNTRL_UTP_REG_END                    0x00a0435c
+#define BCHP_QUEUE_54_CNTRL_UTP_REG_START                  0x00a04360
+#define BCHP_QUEUE_54_CNTRL_UTP_REG_END                    0x00a0436c
+#define BCHP_QUEUE_55_CNTRL_UTP_REG_START                  0x00a04370
+#define BCHP_QUEUE_55_CNTRL_UTP_REG_END                    0x00a0437c
+#define BCHP_QUEUE_56_CNTRL_UTP_REG_START                  0x00a04380
+#define BCHP_QUEUE_56_CNTRL_UTP_REG_END                    0x00a0438c
+#define BCHP_QUEUE_57_CNTRL_UTP_REG_START                  0x00a04390
+#define BCHP_QUEUE_57_CNTRL_UTP_REG_END                    0x00a0439c
+#define BCHP_QUEUE_58_CNTRL_UTP_REG_START                  0x00a043a0
+#define BCHP_QUEUE_58_CNTRL_UTP_REG_END                    0x00a043ac
+#define BCHP_QUEUE_59_CNTRL_UTP_REG_START                  0x00a043b0
+#define BCHP_QUEUE_59_CNTRL_UTP_REG_END                    0x00a043bc
+#define BCHP_QUEUE_60_CNTRL_UTP_REG_START                  0x00a043c0
+#define BCHP_QUEUE_60_CNTRL_UTP_REG_END                    0x00a043cc
+#define BCHP_QUEUE_61_CNTRL_UTP_REG_START                  0x00a043d0
+#define BCHP_QUEUE_61_CNTRL_UTP_REG_END                    0x00a043dc
+#define BCHP_QUEUE_62_CNTRL_UTP_REG_START                  0x00a043e0
+#define BCHP_QUEUE_62_CNTRL_UTP_REG_END                    0x00a043ec
+#define BCHP_QUEUE_63_CNTRL_UTP_REG_START                  0x00a043f0
+#define BCHP_QUEUE_63_CNTRL_UTP_REG_END                    0x00a043fc
+#define BCHP_QUEUE_0_DATA_UTP_REG_START                    0x00a05000
+#define BCHP_QUEUE_0_DATA_UTP_REG_END                      0x00a0500c
+#define BCHP_QUEUE_1_DATA_UTP_REG_START                    0x00a05010
+#define BCHP_QUEUE_1_DATA_UTP_REG_END                      0x00a0501c
+#define BCHP_QUEUE_2_DATA_UTP_REG_START                    0x00a05020
+#define BCHP_QUEUE_2_DATA_UTP_REG_END                      0x00a0502c
+#define BCHP_QUEUE_3_DATA_UTP_REG_START                    0x00a05030
+#define BCHP_QUEUE_3_DATA_UTP_REG_END                      0x00a0503c
+#define BCHP_QUEUE_4_DATA_UTP_REG_START                    0x00a05040
+#define BCHP_QUEUE_4_DATA_UTP_REG_END                      0x00a0504c
+#define BCHP_QUEUE_5_DATA_UTP_REG_START                    0x00a05050
+#define BCHP_QUEUE_5_DATA_UTP_REG_END                      0x00a0505c
+#define BCHP_QUEUE_6_DATA_UTP_REG_START                    0x00a05060
+#define BCHP_QUEUE_6_DATA_UTP_REG_END                      0x00a0506c
+#define BCHP_QUEUE_7_DATA_UTP_REG_START                    0x00a05070
+#define BCHP_QUEUE_7_DATA_UTP_REG_END                      0x00a0507c
+#define BCHP_QUEUE_8_DATA_UTP_REG_START                    0x00a05080
+#define BCHP_QUEUE_8_DATA_UTP_REG_END                      0x00a0508c
+#define BCHP_QUEUE_9_DATA_UTP_REG_START                    0x00a05090
+#define BCHP_QUEUE_9_DATA_UTP_REG_END                      0x00a0509c
+#define BCHP_QUEUE_10_DATA_UTP_REG_START                   0x00a050a0
+#define BCHP_QUEUE_10_DATA_UTP_REG_END                     0x00a050ac
+#define BCHP_QUEUE_11_DATA_UTP_REG_START                   0x00a050b0
+#define BCHP_QUEUE_11_DATA_UTP_REG_END                     0x00a050bc
+#define BCHP_QUEUE_12_DATA_UTP_REG_START                   0x00a050c0
+#define BCHP_QUEUE_12_DATA_UTP_REG_END                     0x00a050cc
+#define BCHP_QUEUE_13_DATA_UTP_REG_START                   0x00a050d0
+#define BCHP_QUEUE_13_DATA_UTP_REG_END                     0x00a050dc
+#define BCHP_QUEUE_14_DATA_UTP_REG_START                   0x00a050e0
+#define BCHP_QUEUE_14_DATA_UTP_REG_END                     0x00a050ec
+#define BCHP_QUEUE_15_DATA_UTP_REG_START                   0x00a050f0
+#define BCHP_QUEUE_15_DATA_UTP_REG_END                     0x00a050fc
+#define BCHP_QUEUE_16_DATA_UTP_REG_START                   0x00a05100
+#define BCHP_QUEUE_16_DATA_UTP_REG_END                     0x00a0510c
+#define BCHP_QUEUE_17_DATA_UTP_REG_START                   0x00a05110
+#define BCHP_QUEUE_17_DATA_UTP_REG_END                     0x00a0511c
+#define BCHP_QUEUE_18_DATA_UTP_REG_START                   0x00a05120
+#define BCHP_QUEUE_18_DATA_UTP_REG_END                     0x00a0512c
+#define BCHP_QUEUE_19_DATA_UTP_REG_START                   0x00a05130
+#define BCHP_QUEUE_19_DATA_UTP_REG_END                     0x00a0513c
+#define BCHP_QUEUE_20_DATA_UTP_REG_START                   0x00a05140
+#define BCHP_QUEUE_20_DATA_UTP_REG_END                     0x00a0514c
+#define BCHP_QUEUE_21_DATA_UTP_REG_START                   0x00a05150
+#define BCHP_QUEUE_21_DATA_UTP_REG_END                     0x00a0515c
+#define BCHP_QUEUE_22_DATA_UTP_REG_START                   0x00a05160
+#define BCHP_QUEUE_22_DATA_UTP_REG_END                     0x00a0516c
+#define BCHP_QUEUE_23_DATA_UTP_REG_START                   0x00a05170
+#define BCHP_QUEUE_23_DATA_UTP_REG_END                     0x00a0517c
+#define BCHP_QUEUE_24_DATA_UTP_REG_START                   0x00a05180
+#define BCHP_QUEUE_24_DATA_UTP_REG_END                     0x00a0518c
+#define BCHP_QUEUE_25_DATA_UTP_REG_START                   0x00a05190
+#define BCHP_QUEUE_25_DATA_UTP_REG_END                     0x00a0519c
+#define BCHP_QUEUE_26_DATA_UTP_REG_START                   0x00a051a0
+#define BCHP_QUEUE_26_DATA_UTP_REG_END                     0x00a051ac
+#define BCHP_QUEUE_27_DATA_UTP_REG_START                   0x00a051b0
+#define BCHP_QUEUE_27_DATA_UTP_REG_END                     0x00a051bc
+#define BCHP_QUEUE_28_DATA_UTP_REG_START                   0x00a051c0
+#define BCHP_QUEUE_28_DATA_UTP_REG_END                     0x00a051cc
+#define BCHP_QUEUE_29_DATA_UTP_REG_START                   0x00a051d0
+#define BCHP_QUEUE_29_DATA_UTP_REG_END                     0x00a051dc
+#define BCHP_QUEUE_30_DATA_UTP_REG_START                   0x00a051e0
+#define BCHP_QUEUE_30_DATA_UTP_REG_END                     0x00a051ec
+#define BCHP_QUEUE_31_DATA_UTP_REG_START                   0x00a051f0
+#define BCHP_QUEUE_31_DATA_UTP_REG_END                     0x00a051fc
+#define BCHP_QUEUE_32_DATA_UTP_REG_START                   0x00a05200
+#define BCHP_QUEUE_32_DATA_UTP_REG_END                     0x00a0520c
+#define BCHP_QUEUE_33_DATA_UTP_REG_START                   0x00a05210
+#define BCHP_QUEUE_33_DATA_UTP_REG_END                     0x00a0521c
+#define BCHP_QUEUE_34_DATA_UTP_REG_START                   0x00a05220
+#define BCHP_QUEUE_34_DATA_UTP_REG_END                     0x00a0522c
+#define BCHP_QUEUE_35_DATA_UTP_REG_START                   0x00a05230
+#define BCHP_QUEUE_35_DATA_UTP_REG_END                     0x00a0523c
+#define BCHP_QUEUE_36_DATA_UTP_REG_START                   0x00a05240
+#define BCHP_QUEUE_36_DATA_UTP_REG_END                     0x00a0524c
+#define BCHP_QUEUE_37_DATA_UTP_REG_START                   0x00a05250
+#define BCHP_QUEUE_37_DATA_UTP_REG_END                     0x00a0525c
+#define BCHP_QUEUE_38_DATA_UTP_REG_START                   0x00a05260
+#define BCHP_QUEUE_38_DATA_UTP_REG_END                     0x00a0526c
+#define BCHP_QUEUE_39_DATA_UTP_REG_START                   0x00a05270
+#define BCHP_QUEUE_39_DATA_UTP_REG_END                     0x00a0527c
+#define BCHP_QUEUE_40_DATA_UTP_REG_START                   0x00a05280
+#define BCHP_QUEUE_40_DATA_UTP_REG_END                     0x00a0528c
+#define BCHP_QUEUE_41_DATA_UTP_REG_START                   0x00a05290
+#define BCHP_QUEUE_41_DATA_UTP_REG_END                     0x00a0529c
+#define BCHP_QUEUE_42_DATA_UTP_REG_START                   0x00a052a0
+#define BCHP_QUEUE_42_DATA_UTP_REG_END                     0x00a052ac
+#define BCHP_QUEUE_43_DATA_UTP_REG_START                   0x00a052b0
+#define BCHP_QUEUE_43_DATA_UTP_REG_END                     0x00a052bc
+#define BCHP_QUEUE_44_DATA_UTP_REG_START                   0x00a052c0
+#define BCHP_QUEUE_44_DATA_UTP_REG_END                     0x00a052cc
+#define BCHP_QUEUE_45_DATA_UTP_REG_START                   0x00a052d0
+#define BCHP_QUEUE_45_DATA_UTP_REG_END                     0x00a052dc
+#define BCHP_QUEUE_46_DATA_UTP_REG_START                   0x00a052e0
+#define BCHP_QUEUE_46_DATA_UTP_REG_END                     0x00a052ec
+#define BCHP_QUEUE_47_DATA_UTP_REG_START                   0x00a052f0
+#define BCHP_QUEUE_47_DATA_UTP_REG_END                     0x00a052fc
+#define BCHP_QUEUE_48_DATA_UTP_REG_START                   0x00a05300
+#define BCHP_QUEUE_48_DATA_UTP_REG_END                     0x00a0530c
+#define BCHP_QUEUE_49_DATA_UTP_REG_START                   0x00a05310
+#define BCHP_QUEUE_49_DATA_UTP_REG_END                     0x00a0531c
+#define BCHP_QUEUE_50_DATA_UTP_REG_START                   0x00a05320
+#define BCHP_QUEUE_50_DATA_UTP_REG_END                     0x00a0532c
+#define BCHP_QUEUE_51_DATA_UTP_REG_START                   0x00a05330
+#define BCHP_QUEUE_51_DATA_UTP_REG_END                     0x00a0533c
+#define BCHP_QUEUE_52_DATA_UTP_REG_START                   0x00a05340
+#define BCHP_QUEUE_52_DATA_UTP_REG_END                     0x00a0534c
+#define BCHP_QUEUE_53_DATA_UTP_REG_START                   0x00a05350
+#define BCHP_QUEUE_53_DATA_UTP_REG_END                     0x00a0535c
+#define BCHP_QUEUE_54_DATA_UTP_REG_START                   0x00a05360
+#define BCHP_QUEUE_54_DATA_UTP_REG_END                     0x00a0536c
+#define BCHP_QUEUE_55_DATA_UTP_REG_START                   0x00a05370
+#define BCHP_QUEUE_55_DATA_UTP_REG_END                     0x00a0537c
+#define BCHP_QUEUE_56_DATA_UTP_REG_START                   0x00a05380
+#define BCHP_QUEUE_56_DATA_UTP_REG_END                     0x00a0538c
+#define BCHP_QUEUE_57_DATA_UTP_REG_START                   0x00a05390
+#define BCHP_QUEUE_57_DATA_UTP_REG_END                     0x00a0539c
+#define BCHP_QUEUE_58_DATA_UTP_REG_START                   0x00a053a0
+#define BCHP_QUEUE_58_DATA_UTP_REG_END                     0x00a053ac
+#define BCHP_QUEUE_59_DATA_UTP_REG_START                   0x00a053b0
+#define BCHP_QUEUE_59_DATA_UTP_REG_END                     0x00a053bc
+#define BCHP_QUEUE_60_DATA_UTP_REG_START                   0x00a053c0
+#define BCHP_QUEUE_60_DATA_UTP_REG_END                     0x00a053cc
+#define BCHP_QUEUE_61_DATA_UTP_REG_START                   0x00a053d0
+#define BCHP_QUEUE_61_DATA_UTP_REG_END                     0x00a053dc
+#define BCHP_QUEUE_62_DATA_UTP_REG_START                   0x00a053e0
+#define BCHP_QUEUE_62_DATA_UTP_REG_END                     0x00a053ec
+#define BCHP_QUEUE_63_DATA_UTP_REG_START                   0x00a053f0
+#define BCHP_QUEUE_63_DATA_UTP_REG_END                     0x00a053fc
+#define BCHP_OL_DQM_UTP_REG_START                          0x00a06c00
+#define BCHP_OL_DQM_UTP_REG_END                            0x00a06c5c
+#define BCHP_OL_QUEUE_STATUS_UTP_REG_START                 0x00a07400
+#define BCHP_OL_QUEUE_STATUS_UTP_REG_END                   0x00a0747c
+#define BCHP_OL_QUEUE_0_DEBUG_UTP_REG_START                0x00a07c00
+#define BCHP_OL_QUEUE_0_DEBUG_UTP_REG_END                  0x00a07c04
+#define BCHP_OL_QUEUE_1_DEBUG_UTP_REG_START                0x00a07c08
+#define BCHP_OL_QUEUE_1_DEBUG_UTP_REG_END                  0x00a07c0c
+#define BCHP_OL_QUEUE_2_DEBUG_UTP_REG_START                0x00a07c10
+#define BCHP_OL_QUEUE_2_DEBUG_UTP_REG_END                  0x00a07c14
+#define BCHP_OL_QUEUE_3_DEBUG_UTP_REG_START                0x00a07c18
+#define BCHP_OL_QUEUE_3_DEBUG_UTP_REG_END                  0x00a07c1c
+#define BCHP_OL_QUEUE_4_DEBUG_UTP_REG_START                0x00a07c20
+#define BCHP_OL_QUEUE_4_DEBUG_UTP_REG_END                  0x00a07c24
+#define BCHP_OL_QUEUE_5_DEBUG_UTP_REG_START                0x00a07c28
+#define BCHP_OL_QUEUE_5_DEBUG_UTP_REG_END                  0x00a07c2c
+#define BCHP_OL_QUEUE_6_DEBUG_UTP_REG_START                0x00a07c30
+#define BCHP_OL_QUEUE_6_DEBUG_UTP_REG_END                  0x00a07c34
+#define BCHP_OL_QUEUE_7_DEBUG_UTP_REG_START                0x00a07c38
+#define BCHP_OL_QUEUE_7_DEBUG_UTP_REG_END                  0x00a07c3c
+#define BCHP_OL_QUEUE_8_DEBUG_UTP_REG_START                0x00a07c40
+#define BCHP_OL_QUEUE_8_DEBUG_UTP_REG_END                  0x00a07c44
+#define BCHP_OL_QUEUE_9_DEBUG_UTP_REG_START                0x00a07c48
+#define BCHP_OL_QUEUE_9_DEBUG_UTP_REG_END                  0x00a07c4c
+#define BCHP_OL_QUEUE_10_DEBUG_UTP_REG_START               0x00a07c50
+#define BCHP_OL_QUEUE_10_DEBUG_UTP_REG_END                 0x00a07c54
+#define BCHP_OL_QUEUE_11_DEBUG_UTP_REG_START               0x00a07c58
+#define BCHP_OL_QUEUE_11_DEBUG_UTP_REG_END                 0x00a07c5c
+#define BCHP_OL_QUEUE_12_DEBUG_UTP_REG_START               0x00a07c60
+#define BCHP_OL_QUEUE_12_DEBUG_UTP_REG_END                 0x00a07c64
+#define BCHP_OL_QUEUE_13_DEBUG_UTP_REG_START               0x00a07c68
+#define BCHP_OL_QUEUE_13_DEBUG_UTP_REG_END                 0x00a07c6c
+#define BCHP_OL_QUEUE_14_DEBUG_UTP_REG_START               0x00a07c70
+#define BCHP_OL_QUEUE_14_DEBUG_UTP_REG_END                 0x00a07c74
+#define BCHP_OL_QUEUE_15_DEBUG_UTP_REG_START               0x00a07c78
+#define BCHP_OL_QUEUE_15_DEBUG_UTP_REG_END                 0x00a07c7c
+#define BCHP_OL_QUEUE_16_DEBUG_UTP_REG_START               0x00a07c80
+#define BCHP_OL_QUEUE_16_DEBUG_UTP_REG_END                 0x00a07c84
+#define BCHP_OL_QUEUE_17_DEBUG_UTP_REG_START               0x00a07c88
+#define BCHP_OL_QUEUE_17_DEBUG_UTP_REG_END                 0x00a07c8c
+#define BCHP_OL_QUEUE_18_DEBUG_UTP_REG_START               0x00a07c90
+#define BCHP_OL_QUEUE_18_DEBUG_UTP_REG_END                 0x00a07c94
+#define BCHP_OL_QUEUE_19_DEBUG_UTP_REG_START               0x00a07c98
+#define BCHP_OL_QUEUE_19_DEBUG_UTP_REG_END                 0x00a07c9c
+#define BCHP_OL_QUEUE_20_DEBUG_UTP_REG_START               0x00a07ca0
+#define BCHP_OL_QUEUE_20_DEBUG_UTP_REG_END                 0x00a07ca4
+#define BCHP_OL_QUEUE_21_DEBUG_UTP_REG_START               0x00a07ca8
+#define BCHP_OL_QUEUE_21_DEBUG_UTP_REG_END                 0x00a07cac
+#define BCHP_OL_QUEUE_22_DEBUG_UTP_REG_START               0x00a07cb0
+#define BCHP_OL_QUEUE_22_DEBUG_UTP_REG_END                 0x00a07cb4
+#define BCHP_OL_QUEUE_23_DEBUG_UTP_REG_START               0x00a07cb8
+#define BCHP_OL_QUEUE_23_DEBUG_UTP_REG_END                 0x00a07cbc
+#define BCHP_OL_QUEUE_24_DEBUG_UTP_REG_START               0x00a07cc0
+#define BCHP_OL_QUEUE_24_DEBUG_UTP_REG_END                 0x00a07cc4
+#define BCHP_OL_QUEUE_25_DEBUG_UTP_REG_START               0x00a07cc8
+#define BCHP_OL_QUEUE_25_DEBUG_UTP_REG_END                 0x00a07ccc
+#define BCHP_OL_QUEUE_26_DEBUG_UTP_REG_START               0x00a07cd0
+#define BCHP_OL_QUEUE_26_DEBUG_UTP_REG_END                 0x00a07cd4
+#define BCHP_OL_QUEUE_27_DEBUG_UTP_REG_START               0x00a07cd8
+#define BCHP_OL_QUEUE_27_DEBUG_UTP_REG_END                 0x00a07cdc
+#define BCHP_OL_QUEUE_28_DEBUG_UTP_REG_START               0x00a07ce0
+#define BCHP_OL_QUEUE_28_DEBUG_UTP_REG_END                 0x00a07ce4
+#define BCHP_OL_QUEUE_29_DEBUG_UTP_REG_START               0x00a07ce8
+#define BCHP_OL_QUEUE_29_DEBUG_UTP_REG_END                 0x00a07cec
+#define BCHP_OL_QUEUE_30_DEBUG_UTP_REG_START               0x00a07cf0
+#define BCHP_OL_QUEUE_30_DEBUG_UTP_REG_END                 0x00a07cf4
+#define BCHP_OL_QUEUE_31_DEBUG_UTP_REG_START               0x00a07cf8
+#define BCHP_OL_QUEUE_31_DEBUG_UTP_REG_END                 0x00a07cfc
+#define BCHP_OL_QUEUE_0_CNTRL_UTP_REG_START                0x00a08000
+#define BCHP_OL_QUEUE_0_CNTRL_UTP_REG_END                  0x00a0801c
+#define BCHP_OL_QUEUE_1_CNTRL_UTP_REG_START                0x00a08020
+#define BCHP_OL_QUEUE_1_CNTRL_UTP_REG_END                  0x00a0803c
+#define BCHP_OL_QUEUE_2_CNTRL_UTP_REG_START                0x00a08040
+#define BCHP_OL_QUEUE_2_CNTRL_UTP_REG_END                  0x00a0805c
+#define BCHP_OL_QUEUE_3_CNTRL_UTP_REG_START                0x00a08060
+#define BCHP_OL_QUEUE_3_CNTRL_UTP_REG_END                  0x00a0807c
+#define BCHP_OL_QUEUE_4_CNTRL_UTP_REG_START                0x00a08080
+#define BCHP_OL_QUEUE_4_CNTRL_UTP_REG_END                  0x00a0809c
+#define BCHP_OL_QUEUE_5_CNTRL_UTP_REG_START                0x00a080a0
+#define BCHP_OL_QUEUE_5_CNTRL_UTP_REG_END                  0x00a080bc
+#define BCHP_OL_QUEUE_6_CNTRL_UTP_REG_START                0x00a080c0
+#define BCHP_OL_QUEUE_6_CNTRL_UTP_REG_END                  0x00a080dc
+#define BCHP_OL_QUEUE_7_CNTRL_UTP_REG_START                0x00a080e0
+#define BCHP_OL_QUEUE_7_CNTRL_UTP_REG_END                  0x00a080fc
+#define BCHP_OL_QUEUE_8_CNTRL_UTP_REG_START                0x00a08100
+#define BCHP_OL_QUEUE_8_CNTRL_UTP_REG_END                  0x00a0811c
+#define BCHP_OL_QUEUE_9_CNTRL_UTP_REG_START                0x00a08120
+#define BCHP_OL_QUEUE_9_CNTRL_UTP_REG_END                  0x00a0813c
+#define BCHP_OL_QUEUE_10_CNTRL_UTP_REG_START               0x00a08140
+#define BCHP_OL_QUEUE_10_CNTRL_UTP_REG_END                 0x00a0815c
+#define BCHP_OL_QUEUE_11_CNTRL_UTP_REG_START               0x00a08160
+#define BCHP_OL_QUEUE_11_CNTRL_UTP_REG_END                 0x00a0817c
+#define BCHP_OL_QUEUE_12_CNTRL_UTP_REG_START               0x00a08180
+#define BCHP_OL_QUEUE_12_CNTRL_UTP_REG_END                 0x00a0819c
+#define BCHP_OL_QUEUE_13_CNTRL_UTP_REG_START               0x00a081a0
+#define BCHP_OL_QUEUE_13_CNTRL_UTP_REG_END                 0x00a081bc
+#define BCHP_OL_QUEUE_14_CNTRL_UTP_REG_START               0x00a081c0
+#define BCHP_OL_QUEUE_14_CNTRL_UTP_REG_END                 0x00a081dc
+#define BCHP_OL_QUEUE_15_CNTRL_UTP_REG_START               0x00a081e0
+#define BCHP_OL_QUEUE_15_CNTRL_UTP_REG_END                 0x00a081fc
+#define BCHP_OL_QUEUE_16_CNTRL_UTP_REG_START               0x00a08200
+#define BCHP_OL_QUEUE_16_CNTRL_UTP_REG_END                 0x00a0821c
+#define BCHP_OL_QUEUE_17_CNTRL_UTP_REG_START               0x00a08220
+#define BCHP_OL_QUEUE_17_CNTRL_UTP_REG_END                 0x00a0823c
+#define BCHP_OL_QUEUE_18_CNTRL_UTP_REG_START               0x00a08240
+#define BCHP_OL_QUEUE_18_CNTRL_UTP_REG_END                 0x00a0825c
+#define BCHP_OL_QUEUE_19_CNTRL_UTP_REG_START               0x00a08260
+#define BCHP_OL_QUEUE_19_CNTRL_UTP_REG_END                 0x00a0827c
+#define BCHP_OL_QUEUE_20_CNTRL_UTP_REG_START               0x00a08280
+#define BCHP_OL_QUEUE_20_CNTRL_UTP_REG_END                 0x00a0829c
+#define BCHP_OL_QUEUE_21_CNTRL_UTP_REG_START               0x00a082a0
+#define BCHP_OL_QUEUE_21_CNTRL_UTP_REG_END                 0x00a082bc
+#define BCHP_OL_QUEUE_22_CNTRL_UTP_REG_START               0x00a082c0
+#define BCHP_OL_QUEUE_22_CNTRL_UTP_REG_END                 0x00a082dc
+#define BCHP_OL_QUEUE_23_CNTRL_UTP_REG_START               0x00a082e0
+#define BCHP_OL_QUEUE_23_CNTRL_UTP_REG_END                 0x00a082fc
+#define BCHP_OL_QUEUE_24_CNTRL_UTP_REG_START               0x00a08300
+#define BCHP_OL_QUEUE_24_CNTRL_UTP_REG_END                 0x00a0831c
+#define BCHP_OL_QUEUE_25_CNTRL_UTP_REG_START               0x00a08320
+#define BCHP_OL_QUEUE_25_CNTRL_UTP_REG_END                 0x00a0833c
+#define BCHP_OL_QUEUE_26_CNTRL_UTP_REG_START               0x00a08340
+#define BCHP_OL_QUEUE_26_CNTRL_UTP_REG_END                 0x00a0835c
+#define BCHP_OL_QUEUE_27_CNTRL_UTP_REG_START               0x00a08360
+#define BCHP_OL_QUEUE_27_CNTRL_UTP_REG_END                 0x00a0837c
+#define BCHP_OL_QUEUE_28_CNTRL_UTP_REG_START               0x00a08380
+#define BCHP_OL_QUEUE_28_CNTRL_UTP_REG_END                 0x00a0839c
+#define BCHP_OL_QUEUE_29_CNTRL_UTP_REG_START               0x00a083a0
+#define BCHP_OL_QUEUE_29_CNTRL_UTP_REG_END                 0x00a083bc
+#define BCHP_OL_QUEUE_30_CNTRL_UTP_REG_START               0x00a083c0
+#define BCHP_OL_QUEUE_30_CNTRL_UTP_REG_END                 0x00a083dc
+#define BCHP_OL_QUEUE_31_CNTRL_UTP_REG_START               0x00a083e0
+#define BCHP_OL_QUEUE_31_CNTRL_UTP_REG_END                 0x00a083fc
+#define BCHP_OL_QUEUE_0_DATA_UTP_REG_START                 0x00a09000
+#define BCHP_OL_QUEUE_0_DATA_UTP_REG_END                   0x00a0901c
+#define BCHP_OL_QUEUE_1_DATA_UTP_REG_START                 0x00a09020
+#define BCHP_OL_QUEUE_1_DATA_UTP_REG_END                   0x00a0903c
+#define BCHP_OL_QUEUE_2_DATA_UTP_REG_START                 0x00a09040
+#define BCHP_OL_QUEUE_2_DATA_UTP_REG_END                   0x00a0905c
+#define BCHP_OL_QUEUE_3_DATA_UTP_REG_START                 0x00a09060
+#define BCHP_OL_QUEUE_3_DATA_UTP_REG_END                   0x00a0907c
+#define BCHP_OL_QUEUE_4_DATA_UTP_REG_START                 0x00a09080
+#define BCHP_OL_QUEUE_4_DATA_UTP_REG_END                   0x00a0909c
+#define BCHP_OL_QUEUE_5_DATA_UTP_REG_START                 0x00a090a0
+#define BCHP_OL_QUEUE_5_DATA_UTP_REG_END                   0x00a090bc
+#define BCHP_OL_QUEUE_6_DATA_UTP_REG_START                 0x00a090c0
+#define BCHP_OL_QUEUE_6_DATA_UTP_REG_END                   0x00a090dc
+#define BCHP_OL_QUEUE_7_DATA_UTP_REG_START                 0x00a090e0
+#define BCHP_OL_QUEUE_7_DATA_UTP_REG_END                   0x00a090fc
+#define BCHP_OL_QUEUE_8_DATA_UTP_REG_START                 0x00a09100
+#define BCHP_OL_QUEUE_8_DATA_UTP_REG_END                   0x00a0911c
+#define BCHP_OL_QUEUE_9_DATA_UTP_REG_START                 0x00a09120
+#define BCHP_OL_QUEUE_9_DATA_UTP_REG_END                   0x00a0913c
+#define BCHP_OL_QUEUE_10_DATA_UTP_REG_START                0x00a09140
+#define BCHP_OL_QUEUE_10_DATA_UTP_REG_END                  0x00a0915c
+#define BCHP_OL_QUEUE_11_DATA_UTP_REG_START                0x00a09160
+#define BCHP_OL_QUEUE_11_DATA_UTP_REG_END                  0x00a0917c
+#define BCHP_OL_QUEUE_12_DATA_UTP_REG_START                0x00a09180
+#define BCHP_OL_QUEUE_12_DATA_UTP_REG_END                  0x00a0919c
+#define BCHP_OL_QUEUE_13_DATA_UTP_REG_START                0x00a091a0
+#define BCHP_OL_QUEUE_13_DATA_UTP_REG_END                  0x00a091bc
+#define BCHP_OL_QUEUE_14_DATA_UTP_REG_START                0x00a091c0
+#define BCHP_OL_QUEUE_14_DATA_UTP_REG_END                  0x00a091dc
+#define BCHP_OL_QUEUE_15_DATA_UTP_REG_START                0x00a091e0
+#define BCHP_OL_QUEUE_15_DATA_UTP_REG_END                  0x00a091fc
+#define BCHP_OL_QUEUE_16_DATA_UTP_REG_START                0x00a09200
+#define BCHP_OL_QUEUE_16_DATA_UTP_REG_END                  0x00a0921c
+#define BCHP_OL_QUEUE_17_DATA_UTP_REG_START                0x00a09220
+#define BCHP_OL_QUEUE_17_DATA_UTP_REG_END                  0x00a0923c
+#define BCHP_OL_QUEUE_18_DATA_UTP_REG_START                0x00a09240
+#define BCHP_OL_QUEUE_18_DATA_UTP_REG_END                  0x00a0925c
+#define BCHP_OL_QUEUE_19_DATA_UTP_REG_START                0x00a09260
+#define BCHP_OL_QUEUE_19_DATA_UTP_REG_END                  0x00a0927c
+#define BCHP_OL_QUEUE_20_DATA_UTP_REG_START                0x00a09280
+#define BCHP_OL_QUEUE_20_DATA_UTP_REG_END                  0x00a0929c
+#define BCHP_OL_QUEUE_21_DATA_UTP_REG_START                0x00a092a0
+#define BCHP_OL_QUEUE_21_DATA_UTP_REG_END                  0x00a092bc
+#define BCHP_OL_QUEUE_22_DATA_UTP_REG_START                0x00a092c0
+#define BCHP_OL_QUEUE_22_DATA_UTP_REG_END                  0x00a092dc
+#define BCHP_OL_QUEUE_23_DATA_UTP_REG_START                0x00a092e0
+#define BCHP_OL_QUEUE_23_DATA_UTP_REG_END                  0x00a092fc
+#define BCHP_OL_QUEUE_24_DATA_UTP_REG_START                0x00a09300
+#define BCHP_OL_QUEUE_24_DATA_UTP_REG_END                  0x00a0931c
+#define BCHP_OL_QUEUE_25_DATA_UTP_REG_START                0x00a09320
+#define BCHP_OL_QUEUE_25_DATA_UTP_REG_END                  0x00a0933c
+#define BCHP_OL_QUEUE_26_DATA_UTP_REG_START                0x00a09340
+#define BCHP_OL_QUEUE_26_DATA_UTP_REG_END                  0x00a0935c
+#define BCHP_OL_QUEUE_27_DATA_UTP_REG_START                0x00a09360
+#define BCHP_OL_QUEUE_27_DATA_UTP_REG_END                  0x00a0937c
+#define BCHP_OL_QUEUE_28_DATA_UTP_REG_START                0x00a09380
+#define BCHP_OL_QUEUE_28_DATA_UTP_REG_END                  0x00a0939c
+#define BCHP_OL_QUEUE_29_DATA_UTP_REG_START                0x00a093a0
+#define BCHP_OL_QUEUE_29_DATA_UTP_REG_END                  0x00a093bc
+#define BCHP_OL_QUEUE_30_DATA_UTP_REG_START                0x00a093c0
+#define BCHP_OL_QUEUE_30_DATA_UTP_REG_END                  0x00a093dc
+#define BCHP_OL_QUEUE_31_DATA_UTP_REG_START                0x00a093e0
+#define BCHP_OL_QUEUE_31_DATA_UTP_REG_END                  0x00a093fc
+#define BCHP_OL_QUEUE_MIB_UTP_REG_START                    0x00a0a000
+#define BCHP_OL_QUEUE_MIB_UTP_REG_END                      0x00a0a17c
+#define BCHP_SEGDMA_CONFIG_UTP_REG_START                   0x00a20000
+#define BCHP_SEGDMA_CONFIG_UTP_REG_END                     0x00a2003c
+#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_START                 0x00a20100
+#define BCHP_SEGDMA_IRQ_HOST_UTP_REG_END                   0x00a2013c
+#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_START                  0x00a20200
+#define BCHP_SEGDMA_IRQ_UTP_UTP_REG_END                    0x00a2023c
+#define BCHP_SEGDMA_STAT_UTP_REG_START                     0x00a20300
+#define BCHP_SEGDMA_STAT_UTP_REG_END                       0x00a203a4
+#define BCHP_SEGDMA_TEST_UTP_REG_START                     0x00a20400
+#define BCHP_SEGDMA_TEST_UTP_REG_END                       0x00a20464
+#define BCHP_SEGDMA_CHAN0_UTP_REG_START                    0x00a21000
+#define BCHP_SEGDMA_CHAN0_UTP_REG_END                      0x00a2103c
+#define BCHP_SEGDMA_CHAN1_UTP_REG_START                    0x00a21100
+#define BCHP_SEGDMA_CHAN1_UTP_REG_END                      0x00a2113c
+#define BCHP_SEGDMA_CHAN2_UTP_REG_START                    0x00a21200
+#define BCHP_SEGDMA_CHAN2_UTP_REG_END                      0x00a2123c
+#define BCHP_SEGDMA_CHAN3_UTP_REG_START                    0x00a21300
+#define BCHP_SEGDMA_CHAN3_UTP_REG_END                      0x00a2133c
+#define BCHP_SEGDMA_CHAN4_UTP_REG_START                    0x00a21400
+#define BCHP_SEGDMA_CHAN4_UTP_REG_END                      0x00a2143c
+#define BCHP_SEGDMA_CHAN5_UTP_REG_START                    0x00a21500
+#define BCHP_SEGDMA_CHAN5_UTP_REG_END                      0x00a2153c
+#define BCHP_SEGDMA_CHAN6_UTP_REG_START                    0x00a21600
+#define BCHP_SEGDMA_CHAN6_UTP_REG_END                      0x00a2163c
+#define BCHP_SEGDMA_CHAN7_UTP_REG_START                    0x00a21700
+#define BCHP_SEGDMA_CHAN7_UTP_REG_END                      0x00a2173c
+#define BCHP_SEGDMA_CHAN8_UTP_REG_START                    0x00a21800
+#define BCHP_SEGDMA_CHAN8_UTP_REG_END                      0x00a2183c
+#define BCHP_SEGDMA_CHAN9_UTP_REG_START                    0x00a21900
+#define BCHP_SEGDMA_CHAN9_UTP_REG_END                      0x00a2193c
+#define BCHP_SEGDMA_FLOW0_UTP_REG_START                    0x00a22000
+#define BCHP_SEGDMA_FLOW0_UTP_REG_END                      0x00a2207c
+#define BCHP_SEGDMA_FLOW1_UTP_REG_START                    0x00a22100
+#define BCHP_SEGDMA_FLOW1_UTP_REG_END                      0x00a2217c
+#define BCHP_SEGDMA_FLOW2_UTP_REG_START                    0x00a22200
+#define BCHP_SEGDMA_FLOW2_UTP_REG_END                      0x00a2227c
+#define BCHP_SEGDMA_FLOW3_UTP_REG_START                    0x00a22300
+#define BCHP_SEGDMA_FLOW3_UTP_REG_END                      0x00a2237c
+#define BCHP_SEGDMA_FLOW4_UTP_REG_START                    0x00a22400
+#define BCHP_SEGDMA_FLOW4_UTP_REG_END                      0x00a2247c
+#define BCHP_SEGDMA_FLOW5_UTP_REG_START                    0x00a22500
+#define BCHP_SEGDMA_FLOW5_UTP_REG_END                      0x00a2257c
+#define BCHP_SEGDMA_FLOW6_UTP_REG_START                    0x00a22600
+#define BCHP_SEGDMA_FLOW6_UTP_REG_END                      0x00a2267c
+#define BCHP_SEGDMA_FLOW7_UTP_REG_START                    0x00a22700
+#define BCHP_SEGDMA_FLOW7_UTP_REG_END                      0x00a2277c
+#define BCHP_SEGDMA_FLOW8_UTP_REG_START                    0x00a22800
+#define BCHP_SEGDMA_FLOW8_UTP_REG_END                      0x00a2287c
+#define BCHP_SEGDMA_FLOW9_UTP_REG_START                    0x00a22900
+#define BCHP_SEGDMA_FLOW9_UTP_REG_END                      0x00a2297c
+#define BCHP_SEGDMA_FLOW10_UTP_REG_START                   0x00a22a00
+#define BCHP_SEGDMA_FLOW10_UTP_REG_END                     0x00a22a7c
+#define BCHP_SEGDMA_FLOW11_UTP_REG_START                   0x00a22b00
+#define BCHP_SEGDMA_FLOW11_UTP_REG_END                     0x00a22b7c
+#define BCHP_SEGDMA_FLOW12_UTP_REG_START                   0x00a22c00
+#define BCHP_SEGDMA_FLOW12_UTP_REG_END                     0x00a22c7c
+#define BCHP_SEGDMA_FLOW13_UTP_REG_START                   0x00a22d00
+#define BCHP_SEGDMA_FLOW13_UTP_REG_END                     0x00a22d7c
+#define BCHP_SEGDMA_FLOW14_UTP_REG_START                   0x00a22e00
+#define BCHP_SEGDMA_FLOW14_UTP_REG_END                     0x00a22e7c
+#define BCHP_SEGDMA_FLOW15_UTP_REG_START                   0x00a22f00
+#define BCHP_SEGDMA_FLOW15_UTP_REG_END                     0x00a22f7c
+#define BCHP_SEGDMA_FLOW16_UTP_REG_START                   0x00a23000
+#define BCHP_SEGDMA_FLOW16_UTP_REG_END                     0x00a2307c
+#define BCHP_SEGDMA_FLOW17_UTP_REG_START                   0x00a23100
+#define BCHP_SEGDMA_FLOW17_UTP_REG_END                     0x00a2317c
+#define BCHP_SEGDMA_FLOW18_UTP_REG_START                   0x00a23200
+#define BCHP_SEGDMA_FLOW18_UTP_REG_END                     0x00a2327c
+#define BCHP_SEGDMA_FLOW19_UTP_REG_START                   0x00a23300
+#define BCHP_SEGDMA_FLOW19_UTP_REG_END                     0x00a2337c
+#define BCHP_SEGDMA_FLOW20_UTP_REG_START                   0x00a23400
+#define BCHP_SEGDMA_FLOW20_UTP_REG_END                     0x00a2347c
+#define BCHP_SEGDMA_FLOW21_UTP_REG_START                   0x00a23500
+#define BCHP_SEGDMA_FLOW21_UTP_REG_END                     0x00a2357c
+#define BCHP_SEGDMA_FLOW22_UTP_REG_START                   0x00a23600
+#define BCHP_SEGDMA_FLOW22_UTP_REG_END                     0x00a2367c
+#define BCHP_SEGDMA_FLOW23_UTP_REG_START                   0x00a23700
+#define BCHP_SEGDMA_FLOW23_UTP_REG_END                     0x00a2377c
+#define BCHP_SEGDMA_FLOW24_UTP_REG_START                   0x00a23800
+#define BCHP_SEGDMA_FLOW24_UTP_REG_END                     0x00a2387c
+#define BCHP_SEGDMA_FLOW25_UTP_REG_START                   0x00a23900
+#define BCHP_SEGDMA_FLOW25_UTP_REG_END                     0x00a2397c
+#define BCHP_SEGDMA_FLOW26_UTP_REG_START                   0x00a23a00
+#define BCHP_SEGDMA_FLOW26_UTP_REG_END                     0x00a23a7c
+#define BCHP_SEGDMA_FLOW27_UTP_REG_START                   0x00a23b00
+#define BCHP_SEGDMA_FLOW27_UTP_REG_END                     0x00a23b7c
+#define BCHP_SEGDMA_FLOW28_UTP_REG_START                   0x00a23c00
+#define BCHP_SEGDMA_FLOW28_UTP_REG_END                     0x00a23c7c
+#define BCHP_SEGDMA_FLOW29_UTP_REG_START                   0x00a23d00
+#define BCHP_SEGDMA_FLOW29_UTP_REG_END                     0x00a23d7c
+#define BCHP_SEGDMA_FLOW30_UTP_REG_START                   0x00a23e00
+#define BCHP_SEGDMA_FLOW30_UTP_REG_END                     0x00a23e7c
+#define BCHP_SEGDMA_FLOW31_UTP_REG_START                   0x00a23f00
+#define BCHP_SEGDMA_FLOW31_UTP_REG_END                     0x00a23f7c
+#define BCHP_SEGDMA_TEST_FLOW_UTP_REG_START                0x00a24000
+#define BCHP_SEGDMA_TEST_FLOW_UTP_REG_END                  0x00a2407c
+#define BCHP_SEGDMA_TEST_FIFO_UTP_REG_START                0x00a24100
+#define BCHP_SEGDMA_TEST_FIFO_UTP_REG_END                  0x00a24108
+#define BCHP_CRYPTO_UTP_REG_START                          0x00a30000
+#define BCHP_CRYPTO_UTP_REG_END                            0x00a3d000
+#define BCHP_QueueSharedMem_UTP_REG_START                  0x00a40000
+#define BCHP_QueueSharedMem_UTP_REG_END                    0x00a4bffc
+#define BCHP_PacketSharedMemory_UTP_REG_START              0x00a80000
+#define BCHP_PacketSharedMemory_UTP_REG_END                0x00a80ffc
+#define BCHP_QListMem_UTP_REG_START                        0x00b00000
+#define BCHP_QListMem_UTP_REG_END                          0x00b03ffc
+#define BCHP_QueueListConfig_UTP_REG_START                 0x00b05000
+#define BCHP_QueueListConfig_UTP_REG_END                   0x00b0521c
+#define BCHP_QiThreshold_UTP_REG_START                     0x00b05400
+#define BCHP_QiThreshold_UTP_REG_END                       0x00b0547c
+#define BCHP_AckCelMaxCnt_UTP_REG_START                    0x00b05500
+#define BCHP_AckCelMaxCnt_UTP_REG_END                      0x00b0553c
+#define BCHP_MIBs_UTP_REG_START                            0x00b05600
+#define BCHP_MIBs_UTP_REG_END                              0x00b05634
+#define BCHP_UTPIncomingMessageFIFO_UTP_REG_START          0x00b05700
+#define BCHP_UTPIncomingMessageFIFO_UTP_REG_END            0x00b05740
+#define BCHP_QueueListHeadTail_UTP_REG_START               0x00b05800
+#define BCHP_QueueListHeadTail_UTP_REG_END                 0x00b058fc
+#define BCHP_TokenInsertion_UTP_REG_START                  0x00b05a00
+#define BCHP_TokenInsertion_UTP_REG_END                    0x00b05a1c
+#define BCHP_TokenDeletion_UTP_REG_START                   0x00b05a20
+#define BCHP_TokenDeletion_UTP_REG_END                     0x00b05a30
+#define BCHP_TamMisc_UTP_REG_START                         0x00b05a40
+#define BCHP_TamMisc_UTP_REG_END                           0x00b05ab0
+#define BCHP_QueueAvailSize_UTP_REG_START                  0x00b05b00
+#define BCHP_QueueAvailSize_UTP_REG_END                    0x00b05bfc
+#define BCHP_UTPMaxRate_FLOW0_UTP_REG_START                0x00b05c00
+#define BCHP_UTPMaxRate_FLOW0_UTP_REG_END                  0x00b05c0c
+#define BCHP_UTPMaxRate_FLOW1_UTP_REG_START                0x00b05c10
+#define BCHP_UTPMaxRate_FLOW1_UTP_REG_END                  0x00b05c1c
+#define BCHP_UTPMaxRate_FLOW2_UTP_REG_START                0x00b05c20
+#define BCHP_UTPMaxRate_FLOW2_UTP_REG_END                  0x00b05c2c
+#define BCHP_UTPMaxRate_FLOW3_UTP_REG_START                0x00b05c30
+#define BCHP_UTPMaxRate_FLOW3_UTP_REG_END                  0x00b05c3c
+#define BCHP_UTPMaxRate_FLOW4_UTP_REG_START                0x00b05c40
+#define BCHP_UTPMaxRate_FLOW4_UTP_REG_END                  0x00b05c4c
+#define BCHP_UTPMaxRate_FLOW5_UTP_REG_START                0x00b05c50
+#define BCHP_UTPMaxRate_FLOW5_UTP_REG_END                  0x00b05c5c
+#define BCHP_UTPMaxRate_FLOW6_UTP_REG_START                0x00b05c60
+#define BCHP_UTPMaxRate_FLOW6_UTP_REG_END                  0x00b05c6c
+#define BCHP_UTPMaxRate_FLOW7_UTP_REG_START                0x00b05c70
+#define BCHP_UTPMaxRate_FLOW7_UTP_REG_END                  0x00b05c7c
+#define BCHP_UTPMaxRate_FLOW8_UTP_REG_START                0x00b05c80
+#define BCHP_UTPMaxRate_FLOW8_UTP_REG_END                  0x00b05c8c
+#define BCHP_UTPMaxRate_FLOW9_UTP_REG_START                0x00b05c90
+#define BCHP_UTPMaxRate_FLOW9_UTP_REG_END                  0x00b05c9c
+#define BCHP_UTPMaxRate_FLOW10_UTP_REG_START               0x00b05ca0
+#define BCHP_UTPMaxRate_FLOW10_UTP_REG_END                 0x00b05cac
+#define BCHP_UTPMaxRate_FLOW11_UTP_REG_START               0x00b05cb0
+#define BCHP_UTPMaxRate_FLOW11_UTP_REG_END                 0x00b05cbc
+#define BCHP_UTPMaxRate_FLOW12_UTP_REG_START               0x00b05cc0
+#define BCHP_UTPMaxRate_FLOW12_UTP_REG_END                 0x00b05ccc
+#define BCHP_UTPMaxRate_FLOW13_UTP_REG_START               0x00b05cd0
+#define BCHP_UTPMaxRate_FLOW13_UTP_REG_END                 0x00b05cdc
+#define BCHP_UTPMaxRate_FLOW14_UTP_REG_START               0x00b05ce0
+#define BCHP_UTPMaxRate_FLOW14_UTP_REG_END                 0x00b05cec
+#define BCHP_UTPMaxRate_FLOW15_UTP_REG_START               0x00b05cf0
+#define BCHP_UTPMaxRate_FLOW15_UTP_REG_END                 0x00b05cfc
+#define BCHP_UTPPeakRate_FLOW0_UTP_REG_START               0x00b05d00
+#define BCHP_UTPPeakRate_FLOW0_UTP_REG_END                 0x00b05d0c
+#define BCHP_UTPPeakRate_FLOW1_UTP_REG_START               0x00b05d10
+#define BCHP_UTPPeakRate_FLOW1_UTP_REG_END                 0x00b05d1c
+#define BCHP_UTPPeakRate_FLOW2_UTP_REG_START               0x00b05d20
+#define BCHP_UTPPeakRate_FLOW2_UTP_REG_END                 0x00b05d2c
+#define BCHP_UTPPeakRate_FLOW3_UTP_REG_START               0x00b05d30
+#define BCHP_UTPPeakRate_FLOW3_UTP_REG_END                 0x00b05d3c
+#define BCHP_UTPPeakRate_FLOW4_UTP_REG_START               0x00b05d40
+#define BCHP_UTPPeakRate_FLOW4_UTP_REG_END                 0x00b05d4c
+#define BCHP_UTPPeakRate_FLOW5_UTP_REG_START               0x00b05d50
+#define BCHP_UTPPeakRate_FLOW5_UTP_REG_END                 0x00b05d5c
+#define BCHP_UTPPeakRate_FLOW6_UTP_REG_START               0x00b05d60
+#define BCHP_UTPPeakRate_FLOW6_UTP_REG_END                 0x00b05d6c
+#define BCHP_UTPPeakRate_FLOW7_UTP_REG_START               0x00b05d70
+#define BCHP_UTPPeakRate_FLOW7_UTP_REG_END                 0x00b05d7c
+#define BCHP_UTPPeakRate_FLOW8_UTP_REG_START               0x00b05d80
+#define BCHP_UTPPeakRate_FLOW8_UTP_REG_END                 0x00b05d8c
+#define BCHP_UTPPeakRate_FLOW9_UTP_REG_START               0x00b05d90
+#define BCHP_UTPPeakRate_FLOW9_UTP_REG_END                 0x00b05d9c
+#define BCHP_UTPPeakRate_FLOW10_UTP_REG_START              0x00b05da0
+#define BCHP_UTPPeakRate_FLOW10_UTP_REG_END                0x00b05dac
+#define BCHP_UTPPeakRate_FLOW11_UTP_REG_START              0x00b05db0
+#define BCHP_UTPPeakRate_FLOW11_UTP_REG_END                0x00b05dbc
+#define BCHP_UTPPeakRate_FLOW12_UTP_REG_START              0x00b05dc0
+#define BCHP_UTPPeakRate_FLOW12_UTP_REG_END                0x00b05dcc
+#define BCHP_UTPPeakRate_FLOW13_UTP_REG_START              0x00b05dd0
+#define BCHP_UTPPeakRate_FLOW13_UTP_REG_END                0x00b05ddc
+#define BCHP_UTPPeakRate_FLOW14_UTP_REG_START              0x00b05de0
+#define BCHP_UTPPeakRate_FLOW14_UTP_REG_END                0x00b05dec
+#define BCHP_UTPPeakRate_FLOW15_UTP_REG_START              0x00b05df0
+#define BCHP_UTPPeakRate_FLOW15_UTP_REG_END                0x00b05dfc
+#define BCHP_UTPTimer_0_UTP_REG_START                      0x00b05e00
+#define BCHP_UTPTimer_0_UTP_REG_END                        0x00b05e04
+#define BCHP_UTPTimer_1_UTP_REG_START                      0x00b05e08
+#define BCHP_UTPTimer_1_UTP_REG_END                        0x00b05e0c
+#define BCHP_UTPTimer_2_UTP_REG_START                      0x00b05e10
+#define BCHP_UTPTimer_2_UTP_REG_END                        0x00b05e14
+#define BCHP_UTPTimer_3_UTP_REG_START                      0x00b05e18
+#define BCHP_UTPTimer_3_UTP_REG_END                        0x00b05e1c
+#define BCHP_UTPTimer_4_UTP_REG_START                      0x00b05e20
+#define BCHP_UTPTimer_4_UTP_REG_END                        0x00b05e24
+#define BCHP_UTPTimer_5_UTP_REG_START                      0x00b05e28
+#define BCHP_UTPTimer_5_UTP_REG_END                        0x00b05e2c
+#define BCHP_UTPTimer_6_UTP_REG_START                      0x00b05e30
+#define BCHP_UTPTimer_6_UTP_REG_END                        0x00b05e34
+#define BCHP_UTPTimer_7_UTP_REG_START                      0x00b05e38
+#define BCHP_UTPTimer_7_UTP_REG_END                        0x00b05e3c
+#define BCHP_UTPTimer_8_UTP_REG_START                      0x00b05e40
+#define BCHP_UTPTimer_8_UTP_REG_END                        0x00b05e44
+#define BCHP_UTPTimer_9_UTP_REG_START                      0x00b05e48
+#define BCHP_UTPTimer_9_UTP_REG_END                        0x00b05e4c
+#define BCHP_UTPTimer_10_UTP_REG_START                     0x00b05e50
+#define BCHP_UTPTimer_10_UTP_REG_END                       0x00b05e54
+#define BCHP_UTPTimer_11_UTP_REG_START                     0x00b05e58
+#define BCHP_UTPTimer_11_UTP_REG_END                       0x00b05e5c
+#define BCHP_UTPTimer_12_UTP_REG_START                     0x00b05e60
+#define BCHP_UTPTimer_12_UTP_REG_END                       0x00b05e64
+#define BCHP_UTPTimer_13_UTP_REG_START                     0x00b05e68
+#define BCHP_UTPTimer_13_UTP_REG_END                       0x00b05e6c
+#define BCHP_UTPTimer_14_UTP_REG_START                     0x00b05e70
+#define BCHP_UTPTimer_14_UTP_REG_END                       0x00b05e74
+#define BCHP_UTPTimer_15_UTP_REG_START                     0x00b05e78
+#define BCHP_UTPTimer_15_UTP_REG_END                       0x00b05e7c
+#define BCHP_UTPTimer_16_UTP_REG_START                     0x00b05e80
+#define BCHP_UTPTimer_16_UTP_REG_END                       0x00b05e84
+#define BCHP_UTPTimer_17_UTP_REG_START                     0x00b05e88
+#define BCHP_UTPTimer_17_UTP_REG_END                       0x00b05e8c
+#define BCHP_UTPBytesSent_FLOW0_UTP_REG_START              0x00b05f00
+#define BCHP_UTPBytesSent_FLOW0_UTP_REG_END                0x00b05f04
+#define BCHP_UTPBytesSent_FLOW1_UTP_REG_START              0x00b05f08
+#define BCHP_UTPBytesSent_FLOW1_UTP_REG_END                0x00b05f0c
+#define BCHP_UTPBytesSent_FLOW2_UTP_REG_START              0x00b05f10
+#define BCHP_UTPBytesSent_FLOW2_UTP_REG_END                0x00b05f14
+#define BCHP_UTPBytesSent_FLOW3_UTP_REG_START              0x00b05f18
+#define BCHP_UTPBytesSent_FLOW3_UTP_REG_END                0x00b05f1c
+#define BCHP_UTPBytesSent_FLOW4_UTP_REG_START              0x00b05f20
+#define BCHP_UTPBytesSent_FLOW4_UTP_REG_END                0x00b05f24
+#define BCHP_UTPBytesSent_FLOW5_UTP_REG_START              0x00b05f28
+#define BCHP_UTPBytesSent_FLOW5_UTP_REG_END                0x00b05f2c
+#define BCHP_UTPBytesSent_FLOW6_UTP_REG_START              0x00b05f30
+#define BCHP_UTPBytesSent_FLOW6_UTP_REG_END                0x00b05f34
+#define BCHP_UTPBytesSent_FLOW7_UTP_REG_START              0x00b05f38
+#define BCHP_UTPBytesSent_FLOW7_UTP_REG_END                0x00b05f3c
+#define BCHP_UTPBytesSent_FLOW8_UTP_REG_START              0x00b05f40
+#define BCHP_UTPBytesSent_FLOW8_UTP_REG_END                0x00b05f44
+#define BCHP_UTPBytesSent_FLOW9_UTP_REG_START              0x00b05f48
+#define BCHP_UTPBytesSent_FLOW9_UTP_REG_END                0x00b05f4c
+#define BCHP_UTPBytesSent_FLOW10_UTP_REG_START             0x00b05f50
+#define BCHP_UTPBytesSent_FLOW10_UTP_REG_END               0x00b05f54
+#define BCHP_UTPBytesSent_FLOW11_UTP_REG_START             0x00b05f58
+#define BCHP_UTPBytesSent_FLOW11_UTP_REG_END               0x00b05f5c
+#define BCHP_UTPBytesSent_FLOW12_UTP_REG_START             0x00b05f60
+#define BCHP_UTPBytesSent_FLOW12_UTP_REG_END               0x00b05f64
+#define BCHP_UTPBytesSent_FLOW13_UTP_REG_START             0x00b05f68
+#define BCHP_UTPBytesSent_FLOW13_UTP_REG_END               0x00b05f6c
+#define BCHP_UTPBytesSent_FLOW14_UTP_REG_START             0x00b05f70
+#define BCHP_UTPBytesSent_FLOW14_UTP_REG_END               0x00b05f74
+#define BCHP_UTPBytesSent_FLOW15_UTP_REG_START             0x00b05f78
+#define BCHP_UTPBytesSent_FLOW15_UTP_REG_END               0x00b05f7c
+#define BCHP_UTPBytesSent_FLOW16_UTP_REG_START             0x00b05f80
+#define BCHP_UTPBytesSent_FLOW16_UTP_REG_END               0x00b05f84
+#define BCHP_UTPBytesSent_FLOW17_UTP_REG_START             0x00b05f88
+#define BCHP_UTPBytesSent_FLOW17_UTP_REG_END               0x00b05f8c
+#define BCHP_UTPBytesSent_FLOW18_UTP_REG_START             0x00b05f90
+#define BCHP_UTPBytesSent_FLOW18_UTP_REG_END               0x00b05f94
+#define BCHP_UTPBytesSent_FLOW19_UTP_REG_START             0x00b05f98
+#define BCHP_UTPBytesSent_FLOW19_UTP_REG_END               0x00b05f9c
+#define BCHP_UTPBytesSent_FLOW20_UTP_REG_START             0x00b05fa0
+#define BCHP_UTPBytesSent_FLOW20_UTP_REG_END               0x00b05fa4
+#define BCHP_UTPBytesSent_FLOW21_UTP_REG_START             0x00b05fa8
+#define BCHP_UTPBytesSent_FLOW21_UTP_REG_END               0x00b05fac
+#define BCHP_UTPBytesSent_FLOW22_UTP_REG_START             0x00b05fb0
+#define BCHP_UTPBytesSent_FLOW22_UTP_REG_END               0x00b05fb4
+#define BCHP_UTPBytesSent_FLOW23_UTP_REG_START             0x00b05fb8
+#define BCHP_UTPBytesSent_FLOW23_UTP_REG_END               0x00b05fbc
+#define BCHP_UTPBytesSent_FLOW24_UTP_REG_START             0x00b05fc0
+#define BCHP_UTPBytesSent_FLOW24_UTP_REG_END               0x00b05fc4
+#define BCHP_UTPBytesSent_FLOW25_UTP_REG_START             0x00b05fc8
+#define BCHP_UTPBytesSent_FLOW25_UTP_REG_END               0x00b05fcc
+#define BCHP_UTPBytesSent_FLOW26_UTP_REG_START             0x00b05fd0
+#define BCHP_UTPBytesSent_FLOW26_UTP_REG_END               0x00b05fd4
+#define BCHP_UTPBytesSent_FLOW27_UTP_REG_START             0x00b05fd8
+#define BCHP_UTPBytesSent_FLOW27_UTP_REG_END               0x00b05fdc
+#define BCHP_UTPBytesSent_FLOW28_UTP_REG_START             0x00b05fe0
+#define BCHP_UTPBytesSent_FLOW28_UTP_REG_END               0x00b05fe4
+#define BCHP_UTPBytesSent_FLOW29_UTP_REG_START             0x00b05fe8
+#define BCHP_UTPBytesSent_FLOW29_UTP_REG_END               0x00b05fec
+#define BCHP_UTPBytesSent_FLOW30_UTP_REG_START             0x00b05ff0
+#define BCHP_UTPBytesSent_FLOW30_UTP_REG_END               0x00b05ff4
+#define BCHP_UTPBytesSent_FLOW31_UTP_REG_START             0x00b05ff8
+#define BCHP_UTPBytesSent_FLOW31_UTP_REG_END               0x00b05ffc
+#define BCHP_UTPTokensInserted0_UTP_REG_START              0x00b06000
+#define BCHP_UTPTokensInserted0_UTP_REG_END                0x00b06004
+#define BCHP_UTPTokensInserted1_UTP_REG_START              0x00b06008
+#define BCHP_UTPTokensInserted1_UTP_REG_END                0x00b0600c
+#define BCHP_UTPTokensInserted2_UTP_REG_START              0x00b06010
+#define BCHP_UTPTokensInserted2_UTP_REG_END                0x00b06014
+#define BCHP_UTPTokensInserted3_UTP_REG_START              0x00b06018
+#define BCHP_UTPTokensInserted3_UTP_REG_END                0x00b0601c
+#define BCHP_UTPTokensInserted4_UTP_REG_START              0x00b06020
+#define BCHP_UTPTokensInserted4_UTP_REG_END                0x00b06024
+#define BCHP_UTPTokensInserted5_UTP_REG_START              0x00b06028
+#define BCHP_UTPTokensInserted5_UTP_REG_END                0x00b0602c
+#define BCHP_UTPTokensInserted6_UTP_REG_START              0x00b06030
+#define BCHP_UTPTokensInserted6_UTP_REG_END                0x00b06034
+#define BCHP_UTPTokensInserted7_UTP_REG_START              0x00b06038
+#define BCHP_UTPTokensInserted7_UTP_REG_END                0x00b0603c
+#define BCHP_UTPTokensInserted8_UTP_REG_START              0x00b06040
+#define BCHP_UTPTokensInserted8_UTP_REG_END                0x00b06044
+#define BCHP_UTPTokensInserted9_UTP_REG_START              0x00b06048
+#define BCHP_UTPTokensInserted9_UTP_REG_END                0x00b0604c
+#define BCHP_UTPTokensInserted10_UTP_REG_START             0x00b06050
+#define BCHP_UTPTokensInserted10_UTP_REG_END               0x00b06054
+#define BCHP_UTPTokensInserted11_UTP_REG_START             0x00b06058
+#define BCHP_UTPTokensInserted11_UTP_REG_END               0x00b0605c
+#define BCHP_UTPTokensInserted12_UTP_REG_START             0x00b06060
+#define BCHP_UTPTokensInserted12_UTP_REG_END               0x00b06064
+#define BCHP_UTPTokensInserted13_UTP_REG_START             0x00b06068
+#define BCHP_UTPTokensInserted13_UTP_REG_END               0x00b0606c
+#define BCHP_UTPTokensInserted14_UTP_REG_START             0x00b06070
+#define BCHP_UTPTokensInserted14_UTP_REG_END               0x00b06074
+#define BCHP_UTPTokensInserted15_UTP_REG_START             0x00b06078
+#define BCHP_UTPTokensInserted15_UTP_REG_END               0x00b0607c
+#define BCHP_UTPTokensInserted16_UTP_REG_START             0x00b06080
+#define BCHP_UTPTokensInserted16_UTP_REG_END               0x00b06084
+#define BCHP_UTPTokensInserted17_UTP_REG_START             0x00b06088
+#define BCHP_UTPTokensInserted17_UTP_REG_END               0x00b0608c
+#define BCHP_UTPTokensInserted18_UTP_REG_START             0x00b06090
+#define BCHP_UTPTokensInserted18_UTP_REG_END               0x00b06094
+#define BCHP_UTPTokensInserted19_UTP_REG_START             0x00b06098
+#define BCHP_UTPTokensInserted19_UTP_REG_END               0x00b0609c
+#define BCHP_UTPTokensInserted20_UTP_REG_START             0x00b060a0
+#define BCHP_UTPTokensInserted20_UTP_REG_END               0x00b060a4
+#define BCHP_UTPTokensInserted21_UTP_REG_START             0x00b060a8
+#define BCHP_UTPTokensInserted21_UTP_REG_END               0x00b060ac
+#define BCHP_UTPTokensInserted22_UTP_REG_START             0x00b060b0
+#define BCHP_UTPTokensInserted22_UTP_REG_END               0x00b060b4
+#define BCHP_UTPTokensInserted23_UTP_REG_START             0x00b060b8
+#define BCHP_UTPTokensInserted23_UTP_REG_END               0x00b060bc
+#define BCHP_UTPTokensInserted24_UTP_REG_START             0x00b060c0
+#define BCHP_UTPTokensInserted24_UTP_REG_END               0x00b060c4
+#define BCHP_UTPTokensInserted25_UTP_REG_START             0x00b060c8
+#define BCHP_UTPTokensInserted25_UTP_REG_END               0x00b060cc
+#define BCHP_UTPTokensInserted26_UTP_REG_START             0x00b060d0
+#define BCHP_UTPTokensInserted26_UTP_REG_END               0x00b060d4
+#define BCHP_UTPTokensInserted27_UTP_REG_START             0x00b060d8
+#define BCHP_UTPTokensInserted27_UTP_REG_END               0x00b060dc
+#define BCHP_UTPTokensInserted28_UTP_REG_START             0x00b060e0
+#define BCHP_UTPTokensInserted28_UTP_REG_END               0x00b060e4
+#define BCHP_UTPTokensInserted29_UTP_REG_START             0x00b060e8
+#define BCHP_UTPTokensInserted29_UTP_REG_END               0x00b060ec
+#define BCHP_UTPTokensInserted30_UTP_REG_START             0x00b060f0
+#define BCHP_UTPTokensInserted30_UTP_REG_END               0x00b060f4
+#define BCHP_UTPTokensInserted31_UTP_REG_START             0x00b060f8
+#define BCHP_UTPTokensInserted31_UTP_REG_END               0x00b060fc
+#define BCHP_UTPTokensDeleted_UTP_REG_START                0x00b06100
+#define BCHP_UTPTokensDeleted_UTP_REG_END                  0x00b0617c
+#define BCHP_UTPTokensReplaced_UTP_REG_START               0x00b06180
+#define BCHP_UTPTokensReplaced_UTP_REG_END                 0x00b061fc
+#define BCHP_IncMsgFifoCntr_UTP_REG_START                  0x00b06200
+#define BCHP_IncMsgFifoCntr_UTP_REG_END                    0x00b0627c
+#define BCHP_UTPAutoDelete_UTP_REG_START                   0x00b06400
+#define BCHP_UTPAutoDelete_UTP_REG_END                     0x00b06418
+#define BCHP_UTPInMsgEngine_UTP_REG_START                  0x00b06500
+#define BCHP_UTPInMsgEngine_UTP_REG_END                    0x00b06594
+#define BCHP_UTPDQMMsgEngine_UTP_REG_START                 0x00b06600
+#define BCHP_UTPDQMMsgEngine_UTP_REG_END                   0x00b06698
+#define BCHP_UTPMIBCounters_UTP_REG_START                  0x00b06700
+#define BCHP_UTPMIBCounters_UTP_REG_END                    0x00b06cbc
+#define BCHP_UTPAQMEngine_UTP_REG_START                    0x00b07000
+#define BCHP_UTPAQMEngine_UTP_REG_END                      0x00b07218
+#define BCHP_DLSTimer_0_UTP_REG_START                      0x00b07400
+#define BCHP_DLSTimer_0_UTP_REG_END                        0x00b07404
+#define BCHP_DLSTimer_1_UTP_REG_START                      0x00b07408
+#define BCHP_DLSTimer_1_UTP_REG_END                        0x00b0740c
+#define BCHP_DLSTimer_2_UTP_REG_START                      0x00b07410
+#define BCHP_DLSTimer_2_UTP_REG_END                        0x00b07414
+#define BCHP_DLSTimer_3_UTP_REG_START                      0x00b07418
+#define BCHP_DLSTimer_3_UTP_REG_END                        0x00b0741c
+#define BCHP_DLSTimer_4_UTP_REG_START                      0x00b07420
+#define BCHP_DLSTimer_4_UTP_REG_END                        0x00b07424
+#define BCHP_DLSTimer_5_UTP_REG_START                      0x00b07428
+#define BCHP_DLSTimer_5_UTP_REG_END                        0x00b0742c
+#define BCHP_DLSTimer_6_UTP_REG_START                      0x00b07430
+#define BCHP_DLSTimer_6_UTP_REG_END                        0x00b07434
+#define BCHP_DLSTimer_7_UTP_REG_START                      0x00b07438
+#define BCHP_DLSTimer_7_UTP_REG_END                        0x00b0743c
+#define BCHP_DLSTimer_8_UTP_REG_START                      0x00b07440
+#define BCHP_DLSTimer_8_UTP_REG_END                        0x00b07444
+#define BCHP_DLSTimer_9_UTP_REG_START                      0x00b07448
+#define BCHP_DLSTimer_9_UTP_REG_END                        0x00b0744c
+#define BCHP_DLSTimer_10_UTP_REG_START                     0x00b07450
+#define BCHP_DLSTimer_10_UTP_REG_END                       0x00b07454
+#define BCHP_DLSTimer_11_UTP_REG_START                     0x00b07458
+#define BCHP_DLSTimer_11_UTP_REG_END                       0x00b0745c
+#define BCHP_DLSTimer_12_UTP_REG_START                     0x00b07460
+#define BCHP_DLSTimer_12_UTP_REG_END                       0x00b07464
+#define BCHP_DLSTimer_13_UTP_REG_START                     0x00b07468
+#define BCHP_DLSTimer_13_UTP_REG_END                       0x00b0746c
+#define BCHP_DLSTimer_14_UTP_REG_START                     0x00b07470
+#define BCHP_DLSTimer_14_UTP_REG_END                       0x00b07474
+#define BCHP_DLSTimer_15_UTP_REG_START                     0x00b07478
+#define BCHP_DLSTimer_15_UTP_REG_END                       0x00b0747c
+#define BCHP_DLSThreshold_UTP_REG_START                    0x00b07500
+#define BCHP_DLSThreshold_UTP_REG_END                      0x00b0753c
+#define BCHP_TokenMem_UTP_REG_START                        0x00b10000
+#define BCHP_TokenMem_UTP_REG_END                          0x00b1fffc
+#define BCHP_LEGACY_MAC_USM20_REG_START                    0x00e00000
+#define BCHP_LEGACY_MAC_USM20_REG_END                      0x00e00a00
+#define BCHP_TC_0_REG_START                                0x00e08000
+#define BCHP_TC_0_REG_END                                  0x00e080bc
+#define BCHP_TC_BANK0_0_REG_START                          0x00e08100
+#define BCHP_TC_BANK0_0_REG_END                            0x00e0811c
+#define BCHP_TC_BANK1_0_REG_START                          0x00e08120
+#define BCHP_TC_BANK1_0_REG_END                            0x00e0813c
+#define BCHP_TC_BANK2_0_REG_START                          0x00e08140
+#define BCHP_TC_BANK2_0_REG_END                            0x00e0815c
+#define BCHP_TC_BANK3_0_REG_START                          0x00e08160
+#define BCHP_TC_BANK3_0_REG_END                            0x00e0817c
+#define BCHP_TC_BANK4_0_REG_START                          0x00e08180
+#define BCHP_TC_BANK4_0_REG_END                            0x00e0819c
+#define BCHP_TC_BANK5_0_REG_START                          0x00e081a0
+#define BCHP_TC_BANK5_0_REG_END                            0x00e081bc
+#define BCHP_TC_BANK6_0_REG_START                          0x00e081c0
+#define BCHP_TC_BANK6_0_REG_END                            0x00e081dc
+#define BCHP_TC_BANK7_0_REG_START                          0x00e081e0
+#define BCHP_TC_BANK7_0_REG_END                            0x00e081fc
+#define BCHP_TC_BANK8_0_REG_START                          0x00e08200
+#define BCHP_TC_BANK8_0_REG_END                            0x00e0821c
+#define BCHP_TC_AUX_0_REG_START                            0x00e08300
+#define BCHP_TC_AUX_0_REG_END                              0x00e08394
+#define BCHP_TC_PRMBL_0_REG_START                          0x00e08400
+#define BCHP_TC_PRMBL_0_REG_END                            0x00e084bc
+#define BCHP_TC_AUX_EXT_0_REG_START                        0x00e084f0
+#define BCHP_TC_AUX_EXT_0_REG_END                          0x00e084f4
+#define BCHP_TC_1_REG_START                                0x00e09000
+#define BCHP_TC_1_REG_END                                  0x00e090bc
+#define BCHP_TC_BANK0_1_REG_START                          0x00e09100
+#define BCHP_TC_BANK0_1_REG_END                            0x00e0911c
+#define BCHP_TC_BANK1_1_REG_START                          0x00e09120
+#define BCHP_TC_BANK1_1_REG_END                            0x00e0913c
+#define BCHP_TC_BANK2_1_REG_START                          0x00e09140
+#define BCHP_TC_BANK2_1_REG_END                            0x00e0915c
+#define BCHP_TC_BANK3_1_REG_START                          0x00e09160
+#define BCHP_TC_BANK3_1_REG_END                            0x00e0917c
+#define BCHP_TC_BANK4_1_REG_START                          0x00e09180
+#define BCHP_TC_BANK4_1_REG_END                            0x00e0919c
+#define BCHP_TC_BANK5_1_REG_START                          0x00e091a0
+#define BCHP_TC_BANK5_1_REG_END                            0x00e091bc
+#define BCHP_TC_BANK6_1_REG_START                          0x00e091c0
+#define BCHP_TC_BANK6_1_REG_END                            0x00e091dc
+#define BCHP_TC_BANK7_1_REG_START                          0x00e091e0
+#define BCHP_TC_BANK7_1_REG_END                            0x00e091fc
+#define BCHP_TC_BANK8_1_REG_START                          0x00e09200
+#define BCHP_TC_BANK8_1_REG_END                            0x00e0921c
+#define BCHP_TC_AUX_1_REG_START                            0x00e09300
+#define BCHP_TC_AUX_1_REG_END                              0x00e09394
+#define BCHP_TC_PRMBL_1_REG_START                          0x00e09400
+#define BCHP_TC_PRMBL_1_REG_END                            0x00e094bc
+#define BCHP_TC_AUX_EXT_1_REG_START                        0x00e094f0
+#define BCHP_TC_AUX_EXT_1_REG_END                          0x00e094f4
+#define BCHP_TC_2_REG_START                                0x00e0a000
+#define BCHP_TC_2_REG_END                                  0x00e0a0bc
+#define BCHP_TC_BANK0_2_REG_START                          0x00e0a100
+#define BCHP_TC_BANK0_2_REG_END                            0x00e0a11c
+#define BCHP_TC_BANK1_2_REG_START                          0x00e0a120
+#define BCHP_TC_BANK1_2_REG_END                            0x00e0a13c
+#define BCHP_TC_BANK2_2_REG_START                          0x00e0a140
+#define BCHP_TC_BANK2_2_REG_END                            0x00e0a15c
+#define BCHP_TC_BANK3_2_REG_START                          0x00e0a160
+#define BCHP_TC_BANK3_2_REG_END                            0x00e0a17c
+#define BCHP_TC_BANK4_2_REG_START                          0x00e0a180
+#define BCHP_TC_BANK4_2_REG_END                            0x00e0a19c
+#define BCHP_TC_BANK5_2_REG_START                          0x00e0a1a0
+#define BCHP_TC_BANK5_2_REG_END                            0x00e0a1bc
+#define BCHP_TC_BANK6_2_REG_START                          0x00e0a1c0
+#define BCHP_TC_BANK6_2_REG_END                            0x00e0a1dc
+#define BCHP_TC_BANK7_2_REG_START                          0x00e0a1e0
+#define BCHP_TC_BANK7_2_REG_END                            0x00e0a1fc
+#define BCHP_TC_BANK8_2_REG_START                          0x00e0a200
+#define BCHP_TC_BANK8_2_REG_END                            0x00e0a21c
+#define BCHP_TC_AUX_2_REG_START                            0x00e0a300
+#define BCHP_TC_AUX_2_REG_END                              0x00e0a394
+#define BCHP_TC_PRMBL_2_REG_START                          0x00e0a400
+#define BCHP_TC_PRMBL_2_REG_END                            0x00e0a4bc
+#define BCHP_TC_AUX_EXT_2_REG_START                        0x00e0a4f0
+#define BCHP_TC_AUX_EXT_2_REG_END                          0x00e0a4f4
+#define BCHP_TC_3_REG_START                                0x00e0b000
+#define BCHP_TC_3_REG_END                                  0x00e0b0bc
+#define BCHP_TC_BANK0_3_REG_START                          0x00e0b100
+#define BCHP_TC_BANK0_3_REG_END                            0x00e0b11c
+#define BCHP_TC_BANK1_3_REG_START                          0x00e0b120
+#define BCHP_TC_BANK1_3_REG_END                            0x00e0b13c
+#define BCHP_TC_BANK2_3_REG_START                          0x00e0b140
+#define BCHP_TC_BANK2_3_REG_END                            0x00e0b15c
+#define BCHP_TC_BANK3_3_REG_START                          0x00e0b160
+#define BCHP_TC_BANK3_3_REG_END                            0x00e0b17c
+#define BCHP_TC_BANK4_3_REG_START                          0x00e0b180
+#define BCHP_TC_BANK4_3_REG_END                            0x00e0b19c
+#define BCHP_TC_BANK5_3_REG_START                          0x00e0b1a0
+#define BCHP_TC_BANK5_3_REG_END                            0x00e0b1bc
+#define BCHP_TC_BANK6_3_REG_START                          0x00e0b1c0
+#define BCHP_TC_BANK6_3_REG_END                            0x00e0b1dc
+#define BCHP_TC_BANK7_3_REG_START                          0x00e0b1e0
+#define BCHP_TC_BANK7_3_REG_END                            0x00e0b1fc
+#define BCHP_TC_BANK8_3_REG_START                          0x00e0b200
+#define BCHP_TC_BANK8_3_REG_END                            0x00e0b21c
+#define BCHP_TC_AUX_3_REG_START                            0x00e0b300
+#define BCHP_TC_AUX_3_REG_END                              0x00e0b394
+#define BCHP_TC_PRMBL_3_REG_START                          0x00e0b400
+#define BCHP_TC_PRMBL_3_REG_END                            0x00e0b4bc
+#define BCHP_TC_AUX_EXT_3_REG_START                        0x00e0b4f0
+#define BCHP_TC_AUX_EXT_3_REG_END                          0x00e0b4f4
+#define BCHP_TC_4_REG_START                                0x00e0c000
+#define BCHP_TC_4_REG_END                                  0x00e0c0bc
+#define BCHP_TC_BANK0_4_REG_START                          0x00e0c100
+#define BCHP_TC_BANK0_4_REG_END                            0x00e0c11c
+#define BCHP_TC_BANK1_4_REG_START                          0x00e0c120
+#define BCHP_TC_BANK1_4_REG_END                            0x00e0c13c
+#define BCHP_TC_BANK2_4_REG_START                          0x00e0c140
+#define BCHP_TC_BANK2_4_REG_END                            0x00e0c15c
+#define BCHP_TC_BANK3_4_REG_START                          0x00e0c160
+#define BCHP_TC_BANK3_4_REG_END                            0x00e0c17c
+#define BCHP_TC_BANK4_4_REG_START                          0x00e0c180
+#define BCHP_TC_BANK4_4_REG_END                            0x00e0c19c
+#define BCHP_TC_BANK5_4_REG_START                          0x00e0c1a0
+#define BCHP_TC_BANK5_4_REG_END                            0x00e0c1bc
+#define BCHP_TC_BANK6_4_REG_START                          0x00e0c1c0
+#define BCHP_TC_BANK6_4_REG_END                            0x00e0c1dc
+#define BCHP_TC_BANK7_4_REG_START                          0x00e0c1e0
+#define BCHP_TC_BANK7_4_REG_END                            0x00e0c1fc
+#define BCHP_TC_BANK8_4_REG_START                          0x00e0c200
+#define BCHP_TC_BANK8_4_REG_END                            0x00e0c21c
+#define BCHP_TC_AUX_4_REG_START                            0x00e0c300
+#define BCHP_TC_AUX_4_REG_END                              0x00e0c394
+#define BCHP_TC_PRMBL_4_REG_START                          0x00e0c400
+#define BCHP_TC_PRMBL_4_REG_END                            0x00e0c4bc
+#define BCHP_TC_AUX_EXT_4_REG_START                        0x00e0c4f0
+#define BCHP_TC_AUX_EXT_4_REG_END                          0x00e0c4f4
+#define BCHP_TC_5_REG_START                                0x00e0d000
+#define BCHP_TC_5_REG_END                                  0x00e0d0bc
+#define BCHP_TC_BANK0_5_REG_START                          0x00e0d100
+#define BCHP_TC_BANK0_5_REG_END                            0x00e0d11c
+#define BCHP_TC_BANK1_5_REG_START                          0x00e0d120
+#define BCHP_TC_BANK1_5_REG_END                            0x00e0d13c
+#define BCHP_TC_BANK2_5_REG_START                          0x00e0d140
+#define BCHP_TC_BANK2_5_REG_END                            0x00e0d15c
+#define BCHP_TC_BANK3_5_REG_START                          0x00e0d160
+#define BCHP_TC_BANK3_5_REG_END                            0x00e0d17c
+#define BCHP_TC_BANK4_5_REG_START                          0x00e0d180
+#define BCHP_TC_BANK4_5_REG_END                            0x00e0d19c
+#define BCHP_TC_BANK5_5_REG_START                          0x00e0d1a0
+#define BCHP_TC_BANK5_5_REG_END                            0x00e0d1bc
+#define BCHP_TC_BANK6_5_REG_START                          0x00e0d1c0
+#define BCHP_TC_BANK6_5_REG_END                            0x00e0d1dc
+#define BCHP_TC_BANK7_5_REG_START                          0x00e0d1e0
+#define BCHP_TC_BANK7_5_REG_END                            0x00e0d1fc
+#define BCHP_TC_BANK8_5_REG_START                          0x00e0d200
+#define BCHP_TC_BANK8_5_REG_END                            0x00e0d21c
+#define BCHP_TC_AUX_5_REG_START                            0x00e0d300
+#define BCHP_TC_AUX_5_REG_END                              0x00e0d394
+#define BCHP_TC_PRMBL_5_REG_START                          0x00e0d400
+#define BCHP_TC_PRMBL_5_REG_END                            0x00e0d4bc
+#define BCHP_TC_AUX_EXT_5_REG_START                        0x00e0d4f0
+#define BCHP_TC_AUX_EXT_5_REG_END                          0x00e0d4f4
+#define BCHP_TC_6_REG_START                                0x00e0e000
+#define BCHP_TC_6_REG_END                                  0x00e0e0bc
+#define BCHP_TC_BANK0_6_REG_START                          0x00e0e100
+#define BCHP_TC_BANK0_6_REG_END                            0x00e0e11c
+#define BCHP_TC_BANK1_6_REG_START                          0x00e0e120
+#define BCHP_TC_BANK1_6_REG_END                            0x00e0e13c
+#define BCHP_TC_BANK2_6_REG_START                          0x00e0e140
+#define BCHP_TC_BANK2_6_REG_END                            0x00e0e15c
+#define BCHP_TC_BANK3_6_REG_START                          0x00e0e160
+#define BCHP_TC_BANK3_6_REG_END                            0x00e0e17c
+#define BCHP_TC_BANK4_6_REG_START                          0x00e0e180
+#define BCHP_TC_BANK4_6_REG_END                            0x00e0e19c
+#define BCHP_TC_BANK5_6_REG_START                          0x00e0e1a0
+#define BCHP_TC_BANK5_6_REG_END                            0x00e0e1bc
+#define BCHP_TC_BANK6_6_REG_START                          0x00e0e1c0
+#define BCHP_TC_BANK6_6_REG_END                            0x00e0e1dc
+#define BCHP_TC_BANK7_6_REG_START                          0x00e0e1e0
+#define BCHP_TC_BANK7_6_REG_END                            0x00e0e1fc
+#define BCHP_TC_BANK8_6_REG_START                          0x00e0e200
+#define BCHP_TC_BANK8_6_REG_END                            0x00e0e21c
+#define BCHP_TC_AUX_6_REG_START                            0x00e0e300
+#define BCHP_TC_AUX_6_REG_END                              0x00e0e394
+#define BCHP_TC_PRMBL_6_REG_START                          0x00e0e400
+#define BCHP_TC_PRMBL_6_REG_END                            0x00e0e4bc
+#define BCHP_TC_AUX_EXT_6_REG_START                        0x00e0e4f0
+#define BCHP_TC_AUX_EXT_6_REG_END                          0x00e0e4f4
+#define BCHP_TC_7_REG_START                                0x00e0f000
+#define BCHP_TC_7_REG_END                                  0x00e0f0bc
+#define BCHP_TC_BANK0_7_REG_START                          0x00e0f100
+#define BCHP_TC_BANK0_7_REG_END                            0x00e0f11c
+#define BCHP_TC_BANK1_7_REG_START                          0x00e0f120
+#define BCHP_TC_BANK1_7_REG_END                            0x00e0f13c
+#define BCHP_TC_BANK2_7_REG_START                          0x00e0f140
+#define BCHP_TC_BANK2_7_REG_END                            0x00e0f15c
+#define BCHP_TC_BANK3_7_REG_START                          0x00e0f160
+#define BCHP_TC_BANK3_7_REG_END                            0x00e0f17c
+#define BCHP_TC_BANK4_7_REG_START                          0x00e0f180
+#define BCHP_TC_BANK4_7_REG_END                            0x00e0f19c
+#define BCHP_TC_BANK5_7_REG_START                          0x00e0f1a0
+#define BCHP_TC_BANK5_7_REG_END                            0x00e0f1bc
+#define BCHP_TC_BANK6_7_REG_START                          0x00e0f1c0
+#define BCHP_TC_BANK6_7_REG_END                            0x00e0f1dc
+#define BCHP_TC_BANK7_7_REG_START                          0x00e0f1e0
+#define BCHP_TC_BANK7_7_REG_END                            0x00e0f1fc
+#define BCHP_TC_BANK8_7_REG_START                          0x00e0f200
+#define BCHP_TC_BANK8_7_REG_END                            0x00e0f21c
+#define BCHP_TC_AUX_7_REG_START                            0x00e0f300
+#define BCHP_TC_AUX_7_REG_END                              0x00e0f394
+#define BCHP_TC_PRMBL_7_REG_START                          0x00e0f400
+#define BCHP_TC_PRMBL_7_REG_END                            0x00e0f4bc
+#define BCHP_TC_AUX_EXT_7_REG_START                        0x00e0f4f0
+#define BCHP_TC_AUX_EXT_7_REG_END                          0x00e0f4f4
+#define BCHP_US_TOP_REG_START                              0x00e10000
+#define BCHP_US_TOP_REG_END                                0x00e107fc
+#define BCHP_US_MBSC_REG_START                             0x00e10c00
+#define BCHP_US_MBSC_REG_END                               0x00e10c7c
+#define BCHP_US_NOISE_REG_START                            0x00e10d00
+#define BCHP_US_NOISE_REG_END                              0x00e10dfc
+#define BCHP_US_WDAC0_REG_START                            0x00e11c00
+#define BCHP_US_WDAC0_REG_END                              0x00e11cfc
+#define BCHP_US_OFDM0_REG_START                            0x00e12000
+#define BCHP_US_OFDM0_REG_END                              0x00e12204
+#define BCHP_US_OFDM1_REG_START                            0x00e12400
+#define BCHP_US_OFDM1_REG_END                              0x00e12604
+#define BCHP_US_CORE0_REG_START                            0x00e14000
+#define BCHP_US_CORE0_REG_END                              0x00e143fc
+#define BCHP_US_CORE1_REG_START                            0x00e14400
+#define BCHP_US_CORE1_REG_END                              0x00e147fc
+#define BCHP_US_CORE2_REG_START                            0x00e14800
+#define BCHP_US_CORE2_REG_END                              0x00e14bfc
+#define BCHP_US_CORE3_REG_START                            0x00e14c00
+#define BCHP_US_CORE3_REG_END                              0x00e14ffc
+#define BCHP_US_CORE4_REG_START                            0x00e15000
+#define BCHP_US_CORE4_REG_END                              0x00e153fc
+#define BCHP_US_CORE5_REG_START                            0x00e15400
+#define BCHP_US_CORE5_REG_END                              0x00e157fc
+#define BCHP_US_CORE6_REG_START                            0x00e15800
+#define BCHP_US_CORE6_REG_END                              0x00e15bfc
+#define BCHP_US_CORE7_REG_START                            0x00e15c00
+#define BCHP_US_CORE7_REG_END                              0x00e15ffc
+#define BCHP_ChannelRegs_USM30_REG_START                   0x00e18000
+#define BCHP_ChannelRegs_USM30_REG_END                     0x00e183bc
+#define BCHP_ChannelQueRegs_USM30_REG_START                0x00e18600
+#define BCHP_ChannelQueRegs_USM30_REG_END                  0x00e1902b
+#define BCHP_QueueRegs_USM30_REG_START                     0x00e19100
+#define BCHP_QueueRegs_USM30_REG_END                       0x00e194fc
+#define BCHP_SIDRegs_USM30_REG_START                       0x00e1a000
+#define BCHP_SIDRegs_USM30_REG_END                         0x00e1a7f2
+#define BCHP_GroupSIDRegs_USM30_REG_START                  0x00e1a800
+#define BCHP_GroupSIDRegs_USM30_REG_END                    0x00e1a81e
+#define BCHP_CalcPhyRegs_USM30_REG_START                   0x00e1a900
+#define BCHP_CalcPhyRegs_USM30_REG_END                     0x00e1a934
+#define BCHP_SimControlRegs_USM30_REG_START                0x00e1aa00
+#define BCHP_SimControlRegs_USM30_REG_END                  0x00e1aa84
+#define BCHP_InterruptRegs_USM30_REG_START                 0x00e1ab00
+#define BCHP_InterruptRegs_USM30_REG_END                   0x00e1ab99
+#define BCHP_MiscRegs_USM30_REG_START                      0x00e1ac00
+#define BCHP_MiscRegs_USM30_REG_END                        0x00e1accc
+#define BCHP_QueueRegs_ReadOnly_USM30_REG_START            0x00e1b000
+#define BCHP_QueueRegs_ReadOnly_USM30_REG_END              0x00e1b3f0
+#define BCHP_MIBCountersRegs_USM30_REG_START               0x00e1b800
+#define BCHP_MIBCountersRegs_USM30_REG_END                 0x00e1bffc
+#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_START       0x00e1c300
+#define BCHP_FlowDiagMIBCountersRegs_USM30_REG_END         0x00e1c4fc
+#define BCHP_DiagConfigRegs_USM30_REG_START                0x00e1c500
+#define BCHP_DiagConfigRegs_USM30_REG_END                  0x00e1c54c
+#define BCHP_DiagMsgRegs_USM30_REG_START                   0x00e1c600
+#define BCHP_DiagMsgRegs_USM30_REG_END                     0x00e1c788
+#define BCHP_BaseReserved_DTP_REG_START                    0x01000000
+#define BCHP_BaseReserved_DTP_REG_END                      0x01000000
+#define BCHP_Control_DTP_REG_START                         0x01001000
+#define BCHP_Control_DTP_REG_END                           0x010010fc
+#define BCHP_OutgoingMessageFIFO_DTP_REG_START             0x01001100
+#define BCHP_OutgoingMessageFIFO_DTP_REG_END               0x0100117c
+#define BCHP_IncomingMessageFIFO_DTP_REG_START             0x01001200
+#define BCHP_IncomingMessageFIFO_DTP_REG_END               0x0100127c
+#define BCHP_DMA0_DTP_REG_START                            0x01001300
+#define BCHP_DMA0_DTP_REG_END                              0x0100131c
+#define BCHP_DMA1_DTP_REG_START                            0x01001320
+#define BCHP_DMA1_DTP_REG_END                              0x0100133c
+#define BCHP_DMAHI0_DTP_REG_START                          0x01001340
+#define BCHP_DMAHI0_DTP_REG_END                            0x0100134c
+#define BCHP_DMAHI1_DTP_REG_START                          0x01001350
+#define BCHP_DMAHI1_DTP_REG_END                            0x0100135c
+#define BCHP_Token_DTP_REG_START                           0x01001400
+#define BCHP_Token_DTP_REG_END                             0x01001420
+#define BCHP_PerfPower_DTP_REG_START                       0x01001600
+#define BCHP_PerfPower_DTP_REG_END                         0x01001640
+#define BCHP_MessageID_DTP_REG_START                       0x01001700
+#define BCHP_MessageID_DTP_REG_END                         0x0100177c
+#define BCHP_HWCounters_DTP_REG_START                      0x01001900
+#define BCHP_HWCounters_DTP_REG_END                        0x01001944
+#define BCHP_DQM_0_31_DTP_REG_START                        0x01001c00
+#define BCHP_DQM_0_31_DTP_REG_END                          0x01001c48
+#define BCHP_DQM_32_63_DTP_REG_START                       0x01001d00
+#define BCHP_DQM_32_63_DTP_REG_END                         0x01001d48
+#define BCHP_QUEUE_TIMER_DTP_REG_START                     0x01002000
+#define BCHP_QUEUE_TIMER_DTP_REG_END                       0x010021fc
+#define BCHP_QUEUE_STATUS_0_31_DTP_REG_START               0x01002800
+#define BCHP_QUEUE_STATUS_0_31_DTP_REG_END                 0x0100287c
+#define BCHP_QUEUE_STATUS_32_63_DTP_REG_START              0x01002900
+#define BCHP_QUEUE_STATUS_32_63_DTP_REG_END                0x0100297c
+#define BCHP_QUEUE_MIB_0_31_DTP_REG_START                  0x01003000
+#define BCHP_QUEUE_MIB_0_31_DTP_REG_END                    0x0100317c
+#define BCHP_QUEUE_MIB_32_63_DTP_REG_START                 0x01003200
+#define BCHP_QUEUE_MIB_32_63_DTP_REG_END                   0x0100337c
+#define BCHP_QUEUE_0_CNTRL_DTP_REG_START                   0x01004000
+#define BCHP_QUEUE_0_CNTRL_DTP_REG_END                     0x0100400c
+#define BCHP_QUEUE_1_CNTRL_DTP_REG_START                   0x01004010
+#define BCHP_QUEUE_1_CNTRL_DTP_REG_END                     0x0100401c
+#define BCHP_QUEUE_2_CNTRL_DTP_REG_START                   0x01004020
+#define BCHP_QUEUE_2_CNTRL_DTP_REG_END                     0x0100402c
+#define BCHP_QUEUE_3_CNTRL_DTP_REG_START                   0x01004030
+#define BCHP_QUEUE_3_CNTRL_DTP_REG_END                     0x0100403c
+#define BCHP_QUEUE_4_CNTRL_DTP_REG_START                   0x01004040
+#define BCHP_QUEUE_4_CNTRL_DTP_REG_END                     0x0100404c
+#define BCHP_QUEUE_5_CNTRL_DTP_REG_START                   0x01004050
+#define BCHP_QUEUE_5_CNTRL_DTP_REG_END                     0x0100405c
+#define BCHP_QUEUE_6_CNTRL_DTP_REG_START                   0x01004060
+#define BCHP_QUEUE_6_CNTRL_DTP_REG_END                     0x0100406c
+#define BCHP_QUEUE_7_CNTRL_DTP_REG_START                   0x01004070
+#define BCHP_QUEUE_7_CNTRL_DTP_REG_END                     0x0100407c
+#define BCHP_QUEUE_8_CNTRL_DTP_REG_START                   0x01004080
+#define BCHP_QUEUE_8_CNTRL_DTP_REG_END                     0x0100408c
+#define BCHP_QUEUE_9_CNTRL_DTP_REG_START                   0x01004090
+#define BCHP_QUEUE_9_CNTRL_DTP_REG_END                     0x0100409c
+#define BCHP_QUEUE_10_CNTRL_DTP_REG_START                  0x010040a0
+#define BCHP_QUEUE_10_CNTRL_DTP_REG_END                    0x010040ac
+#define BCHP_QUEUE_11_CNTRL_DTP_REG_START                  0x010040b0
+#define BCHP_QUEUE_11_CNTRL_DTP_REG_END                    0x010040bc
+#define BCHP_QUEUE_12_CNTRL_DTP_REG_START                  0x010040c0
+#define BCHP_QUEUE_12_CNTRL_DTP_REG_END                    0x010040cc
+#define BCHP_QUEUE_13_CNTRL_DTP_REG_START                  0x010040d0
+#define BCHP_QUEUE_13_CNTRL_DTP_REG_END                    0x010040dc
+#define BCHP_QUEUE_14_CNTRL_DTP_REG_START                  0x010040e0
+#define BCHP_QUEUE_14_CNTRL_DTP_REG_END                    0x010040ec
+#define BCHP_QUEUE_15_CNTRL_DTP_REG_START                  0x010040f0
+#define BCHP_QUEUE_15_CNTRL_DTP_REG_END                    0x010040fc
+#define BCHP_QUEUE_16_CNTRL_DTP_REG_START                  0x01004100
+#define BCHP_QUEUE_16_CNTRL_DTP_REG_END                    0x0100410c
+#define BCHP_QUEUE_17_CNTRL_DTP_REG_START                  0x01004110
+#define BCHP_QUEUE_17_CNTRL_DTP_REG_END                    0x0100411c
+#define BCHP_QUEUE_18_CNTRL_DTP_REG_START                  0x01004120
+#define BCHP_QUEUE_18_CNTRL_DTP_REG_END                    0x0100412c
+#define BCHP_QUEUE_19_CNTRL_DTP_REG_START                  0x01004130
+#define BCHP_QUEUE_19_CNTRL_DTP_REG_END                    0x0100413c
+#define BCHP_QUEUE_20_CNTRL_DTP_REG_START                  0x01004140
+#define BCHP_QUEUE_20_CNTRL_DTP_REG_END                    0x0100414c
+#define BCHP_QUEUE_21_CNTRL_DTP_REG_START                  0x01004150
+#define BCHP_QUEUE_21_CNTRL_DTP_REG_END                    0x0100415c
+#define BCHP_QUEUE_22_CNTRL_DTP_REG_START                  0x01004160
+#define BCHP_QUEUE_22_CNTRL_DTP_REG_END                    0x0100416c
+#define BCHP_QUEUE_23_CNTRL_DTP_REG_START                  0x01004170
+#define BCHP_QUEUE_23_CNTRL_DTP_REG_END                    0x0100417c
+#define BCHP_QUEUE_24_CNTRL_DTP_REG_START                  0x01004180
+#define BCHP_QUEUE_24_CNTRL_DTP_REG_END                    0x0100418c
+#define BCHP_QUEUE_25_CNTRL_DTP_REG_START                  0x01004190
+#define BCHP_QUEUE_25_CNTRL_DTP_REG_END                    0x0100419c
+#define BCHP_QUEUE_26_CNTRL_DTP_REG_START                  0x010041a0
+#define BCHP_QUEUE_26_CNTRL_DTP_REG_END                    0x010041ac
+#define BCHP_QUEUE_27_CNTRL_DTP_REG_START                  0x010041b0
+#define BCHP_QUEUE_27_CNTRL_DTP_REG_END                    0x010041bc
+#define BCHP_QUEUE_28_CNTRL_DTP_REG_START                  0x010041c0
+#define BCHP_QUEUE_28_CNTRL_DTP_REG_END                    0x010041cc
+#define BCHP_QUEUE_29_CNTRL_DTP_REG_START                  0x010041d0
+#define BCHP_QUEUE_29_CNTRL_DTP_REG_END                    0x010041dc
+#define BCHP_QUEUE_30_CNTRL_DTP_REG_START                  0x010041e0
+#define BCHP_QUEUE_30_CNTRL_DTP_REG_END                    0x010041ec
+#define BCHP_QUEUE_31_CNTRL_DTP_REG_START                  0x010041f0
+#define BCHP_QUEUE_31_CNTRL_DTP_REG_END                    0x010041fc
+#define BCHP_QUEUE_32_CNTRL_DTP_REG_START                  0x01004200
+#define BCHP_QUEUE_32_CNTRL_DTP_REG_END                    0x0100420c
+#define BCHP_QUEUE_33_CNTRL_DTP_REG_START                  0x01004210
+#define BCHP_QUEUE_33_CNTRL_DTP_REG_END                    0x0100421c
+#define BCHP_QUEUE_34_CNTRL_DTP_REG_START                  0x01004220
+#define BCHP_QUEUE_34_CNTRL_DTP_REG_END                    0x0100422c
+#define BCHP_QUEUE_35_CNTRL_DTP_REG_START                  0x01004230
+#define BCHP_QUEUE_35_CNTRL_DTP_REG_END                    0x0100423c
+#define BCHP_QUEUE_36_CNTRL_DTP_REG_START                  0x01004240
+#define BCHP_QUEUE_36_CNTRL_DTP_REG_END                    0x0100424c
+#define BCHP_QUEUE_37_CNTRL_DTP_REG_START                  0x01004250
+#define BCHP_QUEUE_37_CNTRL_DTP_REG_END                    0x0100425c
+#define BCHP_QUEUE_38_CNTRL_DTP_REG_START                  0x01004260
+#define BCHP_QUEUE_38_CNTRL_DTP_REG_END                    0x0100426c
+#define BCHP_QUEUE_39_CNTRL_DTP_REG_START                  0x01004270
+#define BCHP_QUEUE_39_CNTRL_DTP_REG_END                    0x0100427c
+#define BCHP_QUEUE_40_CNTRL_DTP_REG_START                  0x01004280
+#define BCHP_QUEUE_40_CNTRL_DTP_REG_END                    0x0100428c
+#define BCHP_QUEUE_41_CNTRL_DTP_REG_START                  0x01004290
+#define BCHP_QUEUE_41_CNTRL_DTP_REG_END                    0x0100429c
+#define BCHP_QUEUE_42_CNTRL_DTP_REG_START                  0x010042a0
+#define BCHP_QUEUE_42_CNTRL_DTP_REG_END                    0x010042ac
+#define BCHP_QUEUE_43_CNTRL_DTP_REG_START                  0x010042b0
+#define BCHP_QUEUE_43_CNTRL_DTP_REG_END                    0x010042bc
+#define BCHP_QUEUE_44_CNTRL_DTP_REG_START                  0x010042c0
+#define BCHP_QUEUE_44_CNTRL_DTP_REG_END                    0x010042cc
+#define BCHP_QUEUE_45_CNTRL_DTP_REG_START                  0x010042d0
+#define BCHP_QUEUE_45_CNTRL_DTP_REG_END                    0x010042dc
+#define BCHP_QUEUE_46_CNTRL_DTP_REG_START                  0x010042e0
+#define BCHP_QUEUE_46_CNTRL_DTP_REG_END                    0x010042ec
+#define BCHP_QUEUE_47_CNTRL_DTP_REG_START                  0x010042f0
+#define BCHP_QUEUE_47_CNTRL_DTP_REG_END                    0x010042fc
+#define BCHP_QUEUE_48_CNTRL_DTP_REG_START                  0x01004300
+#define BCHP_QUEUE_48_CNTRL_DTP_REG_END                    0x0100430c
+#define BCHP_QUEUE_49_CNTRL_DTP_REG_START                  0x01004310
+#define BCHP_QUEUE_49_CNTRL_DTP_REG_END                    0x0100431c
+#define BCHP_QUEUE_50_CNTRL_DTP_REG_START                  0x01004320
+#define BCHP_QUEUE_50_CNTRL_DTP_REG_END                    0x0100432c
+#define BCHP_QUEUE_51_CNTRL_DTP_REG_START                  0x01004330
+#define BCHP_QUEUE_51_CNTRL_DTP_REG_END                    0x0100433c
+#define BCHP_QUEUE_52_CNTRL_DTP_REG_START                  0x01004340
+#define BCHP_QUEUE_52_CNTRL_DTP_REG_END                    0x0100434c
+#define BCHP_QUEUE_53_CNTRL_DTP_REG_START                  0x01004350
+#define BCHP_QUEUE_53_CNTRL_DTP_REG_END                    0x0100435c
+#define BCHP_QUEUE_54_CNTRL_DTP_REG_START                  0x01004360
+#define BCHP_QUEUE_54_CNTRL_DTP_REG_END                    0x0100436c
+#define BCHP_QUEUE_55_CNTRL_DTP_REG_START                  0x01004370
+#define BCHP_QUEUE_55_CNTRL_DTP_REG_END                    0x0100437c
+#define BCHP_QUEUE_56_CNTRL_DTP_REG_START                  0x01004380
+#define BCHP_QUEUE_56_CNTRL_DTP_REG_END                    0x0100438c
+#define BCHP_QUEUE_57_CNTRL_DTP_REG_START                  0x01004390
+#define BCHP_QUEUE_57_CNTRL_DTP_REG_END                    0x0100439c
+#define BCHP_QUEUE_58_CNTRL_DTP_REG_START                  0x010043a0
+#define BCHP_QUEUE_58_CNTRL_DTP_REG_END                    0x010043ac
+#define BCHP_QUEUE_59_CNTRL_DTP_REG_START                  0x010043b0
+#define BCHP_QUEUE_59_CNTRL_DTP_REG_END                    0x010043bc
+#define BCHP_QUEUE_60_CNTRL_DTP_REG_START                  0x010043c0
+#define BCHP_QUEUE_60_CNTRL_DTP_REG_END                    0x010043cc
+#define BCHP_QUEUE_61_CNTRL_DTP_REG_START                  0x010043d0
+#define BCHP_QUEUE_61_CNTRL_DTP_REG_END                    0x010043dc
+#define BCHP_QUEUE_62_CNTRL_DTP_REG_START                  0x010043e0
+#define BCHP_QUEUE_62_CNTRL_DTP_REG_END                    0x010043ec
+#define BCHP_QUEUE_63_CNTRL_DTP_REG_START                  0x010043f0
+#define BCHP_QUEUE_63_CNTRL_DTP_REG_END                    0x010043fc
+#define BCHP_QUEUE_0_DATA_DTP_REG_START                    0x01005000
+#define BCHP_QUEUE_0_DATA_DTP_REG_END                      0x0100500c
+#define BCHP_QUEUE_1_DATA_DTP_REG_START                    0x01005010
+#define BCHP_QUEUE_1_DATA_DTP_REG_END                      0x0100501c
+#define BCHP_QUEUE_2_DATA_DTP_REG_START                    0x01005020
+#define BCHP_QUEUE_2_DATA_DTP_REG_END                      0x0100502c
+#define BCHP_QUEUE_3_DATA_DTP_REG_START                    0x01005030
+#define BCHP_QUEUE_3_DATA_DTP_REG_END                      0x0100503c
+#define BCHP_QUEUE_4_DATA_DTP_REG_START                    0x01005040
+#define BCHP_QUEUE_4_DATA_DTP_REG_END                      0x0100504c
+#define BCHP_QUEUE_5_DATA_DTP_REG_START                    0x01005050
+#define BCHP_QUEUE_5_DATA_DTP_REG_END                      0x0100505c
+#define BCHP_QUEUE_6_DATA_DTP_REG_START                    0x01005060
+#define BCHP_QUEUE_6_DATA_DTP_REG_END                      0x0100506c
+#define BCHP_QUEUE_7_DATA_DTP_REG_START                    0x01005070
+#define BCHP_QUEUE_7_DATA_DTP_REG_END                      0x0100507c
+#define BCHP_QUEUE_8_DATA_DTP_REG_START                    0x01005080
+#define BCHP_QUEUE_8_DATA_DTP_REG_END                      0x0100508c
+#define BCHP_QUEUE_9_DATA_DTP_REG_START                    0x01005090
+#define BCHP_QUEUE_9_DATA_DTP_REG_END                      0x0100509c
+#define BCHP_QUEUE_10_DATA_DTP_REG_START                   0x010050a0
+#define BCHP_QUEUE_10_DATA_DTP_REG_END                     0x010050ac
+#define BCHP_QUEUE_11_DATA_DTP_REG_START                   0x010050b0
+#define BCHP_QUEUE_11_DATA_DTP_REG_END                     0x010050bc
+#define BCHP_QUEUE_12_DATA_DTP_REG_START                   0x010050c0
+#define BCHP_QUEUE_12_DATA_DTP_REG_END                     0x010050cc
+#define BCHP_QUEUE_13_DATA_DTP_REG_START                   0x010050d0
+#define BCHP_QUEUE_13_DATA_DTP_REG_END                     0x010050dc
+#define BCHP_QUEUE_14_DATA_DTP_REG_START                   0x010050e0
+#define BCHP_QUEUE_14_DATA_DTP_REG_END                     0x010050ec
+#define BCHP_QUEUE_15_DATA_DTP_REG_START                   0x010050f0
+#define BCHP_QUEUE_15_DATA_DTP_REG_END                     0x010050fc
+#define BCHP_QUEUE_16_DATA_DTP_REG_START                   0x01005100
+#define BCHP_QUEUE_16_DATA_DTP_REG_END                     0x0100510c
+#define BCHP_QUEUE_17_DATA_DTP_REG_START                   0x01005110
+#define BCHP_QUEUE_17_DATA_DTP_REG_END                     0x0100511c
+#define BCHP_QUEUE_18_DATA_DTP_REG_START                   0x01005120
+#define BCHP_QUEUE_18_DATA_DTP_REG_END                     0x0100512c
+#define BCHP_QUEUE_19_DATA_DTP_REG_START                   0x01005130
+#define BCHP_QUEUE_19_DATA_DTP_REG_END                     0x0100513c
+#define BCHP_QUEUE_20_DATA_DTP_REG_START                   0x01005140
+#define BCHP_QUEUE_20_DATA_DTP_REG_END                     0x0100514c
+#define BCHP_QUEUE_21_DATA_DTP_REG_START                   0x01005150
+#define BCHP_QUEUE_21_DATA_DTP_REG_END                     0x0100515c
+#define BCHP_QUEUE_22_DATA_DTP_REG_START                   0x01005160
+#define BCHP_QUEUE_22_DATA_DTP_REG_END                     0x0100516c
+#define BCHP_QUEUE_23_DATA_DTP_REG_START                   0x01005170
+#define BCHP_QUEUE_23_DATA_DTP_REG_END                     0x0100517c
+#define BCHP_QUEUE_24_DATA_DTP_REG_START                   0x01005180
+#define BCHP_QUEUE_24_DATA_DTP_REG_END                     0x0100518c
+#define BCHP_QUEUE_25_DATA_DTP_REG_START                   0x01005190
+#define BCHP_QUEUE_25_DATA_DTP_REG_END                     0x0100519c
+#define BCHP_QUEUE_26_DATA_DTP_REG_START                   0x010051a0
+#define BCHP_QUEUE_26_DATA_DTP_REG_END                     0x010051ac
+#define BCHP_QUEUE_27_DATA_DTP_REG_START                   0x010051b0
+#define BCHP_QUEUE_27_DATA_DTP_REG_END                     0x010051bc
+#define BCHP_QUEUE_28_DATA_DTP_REG_START                   0x010051c0
+#define BCHP_QUEUE_28_DATA_DTP_REG_END                     0x010051cc
+#define BCHP_QUEUE_29_DATA_DTP_REG_START                   0x010051d0
+#define BCHP_QUEUE_29_DATA_DTP_REG_END                     0x010051dc
+#define BCHP_QUEUE_30_DATA_DTP_REG_START                   0x010051e0
+#define BCHP_QUEUE_30_DATA_DTP_REG_END                     0x010051ec
+#define BCHP_QUEUE_31_DATA_DTP_REG_START                   0x010051f0
+#define BCHP_QUEUE_31_DATA_DTP_REG_END                     0x010051fc
+#define BCHP_QUEUE_32_DATA_DTP_REG_START                   0x01005200
+#define BCHP_QUEUE_32_DATA_DTP_REG_END                     0x0100520c
+#define BCHP_QUEUE_33_DATA_DTP_REG_START                   0x01005210
+#define BCHP_QUEUE_33_DATA_DTP_REG_END                     0x0100521c
+#define BCHP_QUEUE_34_DATA_DTP_REG_START                   0x01005220
+#define BCHP_QUEUE_34_DATA_DTP_REG_END                     0x0100522c
+#define BCHP_QUEUE_35_DATA_DTP_REG_START                   0x01005230
+#define BCHP_QUEUE_35_DATA_DTP_REG_END                     0x0100523c
+#define BCHP_QUEUE_36_DATA_DTP_REG_START                   0x01005240
+#define BCHP_QUEUE_36_DATA_DTP_REG_END                     0x0100524c
+#define BCHP_QUEUE_37_DATA_DTP_REG_START                   0x01005250
+#define BCHP_QUEUE_37_DATA_DTP_REG_END                     0x0100525c
+#define BCHP_QUEUE_38_DATA_DTP_REG_START                   0x01005260
+#define BCHP_QUEUE_38_DATA_DTP_REG_END                     0x0100526c
+#define BCHP_QUEUE_39_DATA_DTP_REG_START                   0x01005270
+#define BCHP_QUEUE_39_DATA_DTP_REG_END                     0x0100527c
+#define BCHP_QUEUE_40_DATA_DTP_REG_START                   0x01005280
+#define BCHP_QUEUE_40_DATA_DTP_REG_END                     0x0100528c
+#define BCHP_QUEUE_41_DATA_DTP_REG_START                   0x01005290
+#define BCHP_QUEUE_41_DATA_DTP_REG_END                     0x0100529c
+#define BCHP_QUEUE_42_DATA_DTP_REG_START                   0x010052a0
+#define BCHP_QUEUE_42_DATA_DTP_REG_END                     0x010052ac
+#define BCHP_QUEUE_43_DATA_DTP_REG_START                   0x010052b0
+#define BCHP_QUEUE_43_DATA_DTP_REG_END                     0x010052bc
+#define BCHP_QUEUE_44_DATA_DTP_REG_START                   0x010052c0
+#define BCHP_QUEUE_44_DATA_DTP_REG_END                     0x010052cc
+#define BCHP_QUEUE_45_DATA_DTP_REG_START                   0x010052d0
+#define BCHP_QUEUE_45_DATA_DTP_REG_END                     0x010052dc
+#define BCHP_QUEUE_46_DATA_DTP_REG_START                   0x010052e0
+#define BCHP_QUEUE_46_DATA_DTP_REG_END                     0x010052ec
+#define BCHP_QUEUE_47_DATA_DTP_REG_START                   0x010052f0
+#define BCHP_QUEUE_47_DATA_DTP_REG_END                     0x010052fc
+#define BCHP_QUEUE_48_DATA_DTP_REG_START                   0x01005300
+#define BCHP_QUEUE_48_DATA_DTP_REG_END                     0x0100530c
+#define BCHP_QUEUE_49_DATA_DTP_REG_START                   0x01005310
+#define BCHP_QUEUE_49_DATA_DTP_REG_END                     0x0100531c
+#define BCHP_QUEUE_50_DATA_DTP_REG_START                   0x01005320
+#define BCHP_QUEUE_50_DATA_DTP_REG_END                     0x0100532c
+#define BCHP_QUEUE_51_DATA_DTP_REG_START                   0x01005330
+#define BCHP_QUEUE_51_DATA_DTP_REG_END                     0x0100533c
+#define BCHP_QUEUE_52_DATA_DTP_REG_START                   0x01005340
+#define BCHP_QUEUE_52_DATA_DTP_REG_END                     0x0100534c
+#define BCHP_QUEUE_53_DATA_DTP_REG_START                   0x01005350
+#define BCHP_QUEUE_53_DATA_DTP_REG_END                     0x0100535c
+#define BCHP_QUEUE_54_DATA_DTP_REG_START                   0x01005360
+#define BCHP_QUEUE_54_DATA_DTP_REG_END                     0x0100536c
+#define BCHP_QUEUE_55_DATA_DTP_REG_START                   0x01005370
+#define BCHP_QUEUE_55_DATA_DTP_REG_END                     0x0100537c
+#define BCHP_QUEUE_56_DATA_DTP_REG_START                   0x01005380
+#define BCHP_QUEUE_56_DATA_DTP_REG_END                     0x0100538c
+#define BCHP_QUEUE_57_DATA_DTP_REG_START                   0x01005390
+#define BCHP_QUEUE_57_DATA_DTP_REG_END                     0x0100539c
+#define BCHP_QUEUE_58_DATA_DTP_REG_START                   0x010053a0
+#define BCHP_QUEUE_58_DATA_DTP_REG_END                     0x010053ac
+#define BCHP_QUEUE_59_DATA_DTP_REG_START                   0x010053b0
+#define BCHP_QUEUE_59_DATA_DTP_REG_END                     0x010053bc
+#define BCHP_QUEUE_60_DATA_DTP_REG_START                   0x010053c0
+#define BCHP_QUEUE_60_DATA_DTP_REG_END                     0x010053cc
+#define BCHP_QUEUE_61_DATA_DTP_REG_START                   0x010053d0
+#define BCHP_QUEUE_61_DATA_DTP_REG_END                     0x010053dc
+#define BCHP_QUEUE_62_DATA_DTP_REG_START                   0x010053e0
+#define BCHP_QUEUE_62_DATA_DTP_REG_END                     0x010053ec
+#define BCHP_QUEUE_63_DATA_DTP_REG_START                   0x010053f0
+#define BCHP_QUEUE_63_DATA_DTP_REG_END                     0x010053fc
+#define BCHP_OL_DQM_DTP_REG_START                          0x01006c00
+#define BCHP_OL_DQM_DTP_REG_END                            0x01006c5c
+#define BCHP_OL_QUEUE_STATUS_DTP_REG_START                 0x01007400
+#define BCHP_OL_QUEUE_STATUS_DTP_REG_END                   0x0100747c
+#define BCHP_OL_QUEUE_0_DEBUG_DTP_REG_START                0x01007c00
+#define BCHP_OL_QUEUE_0_DEBUG_DTP_REG_END                  0x01007c04
+#define BCHP_OL_QUEUE_1_DEBUG_DTP_REG_START                0x01007c08
+#define BCHP_OL_QUEUE_1_DEBUG_DTP_REG_END                  0x01007c0c
+#define BCHP_OL_QUEUE_2_DEBUG_DTP_REG_START                0x01007c10
+#define BCHP_OL_QUEUE_2_DEBUG_DTP_REG_END                  0x01007c14
+#define BCHP_OL_QUEUE_3_DEBUG_DTP_REG_START                0x01007c18
+#define BCHP_OL_QUEUE_3_DEBUG_DTP_REG_END                  0x01007c1c
+#define BCHP_OL_QUEUE_4_DEBUG_DTP_REG_START                0x01007c20
+#define BCHP_OL_QUEUE_4_DEBUG_DTP_REG_END                  0x01007c24
+#define BCHP_OL_QUEUE_5_DEBUG_DTP_REG_START                0x01007c28
+#define BCHP_OL_QUEUE_5_DEBUG_DTP_REG_END                  0x01007c2c
+#define BCHP_OL_QUEUE_6_DEBUG_DTP_REG_START                0x01007c30
+#define BCHP_OL_QUEUE_6_DEBUG_DTP_REG_END                  0x01007c34
+#define BCHP_OL_QUEUE_7_DEBUG_DTP_REG_START                0x01007c38
+#define BCHP_OL_QUEUE_7_DEBUG_DTP_REG_END                  0x01007c3c
+#define BCHP_OL_QUEUE_8_DEBUG_DTP_REG_START                0x01007c40
+#define BCHP_OL_QUEUE_8_DEBUG_DTP_REG_END                  0x01007c44
+#define BCHP_OL_QUEUE_9_DEBUG_DTP_REG_START                0x01007c48
+#define BCHP_OL_QUEUE_9_DEBUG_DTP_REG_END                  0x01007c4c
+#define BCHP_OL_QUEUE_10_DEBUG_DTP_REG_START               0x01007c50
+#define BCHP_OL_QUEUE_10_DEBUG_DTP_REG_END                 0x01007c54
+#define BCHP_OL_QUEUE_11_DEBUG_DTP_REG_START               0x01007c58
+#define BCHP_OL_QUEUE_11_DEBUG_DTP_REG_END                 0x01007c5c
+#define BCHP_OL_QUEUE_12_DEBUG_DTP_REG_START               0x01007c60
+#define BCHP_OL_QUEUE_12_DEBUG_DTP_REG_END                 0x01007c64
+#define BCHP_OL_QUEUE_13_DEBUG_DTP_REG_START               0x01007c68
+#define BCHP_OL_QUEUE_13_DEBUG_DTP_REG_END                 0x01007c6c
+#define BCHP_OL_QUEUE_14_DEBUG_DTP_REG_START               0x01007c70
+#define BCHP_OL_QUEUE_14_DEBUG_DTP_REG_END                 0x01007c74
+#define BCHP_OL_QUEUE_15_DEBUG_DTP_REG_START               0x01007c78
+#define BCHP_OL_QUEUE_15_DEBUG_DTP_REG_END                 0x01007c7c
+#define BCHP_OL_QUEUE_16_DEBUG_DTP_REG_START               0x01007c80
+#define BCHP_OL_QUEUE_16_DEBUG_DTP_REG_END                 0x01007c84
+#define BCHP_OL_QUEUE_17_DEBUG_DTP_REG_START               0x01007c88
+#define BCHP_OL_QUEUE_17_DEBUG_DTP_REG_END                 0x01007c8c
+#define BCHP_OL_QUEUE_18_DEBUG_DTP_REG_START               0x01007c90
+#define BCHP_OL_QUEUE_18_DEBUG_DTP_REG_END                 0x01007c94
+#define BCHP_OL_QUEUE_19_DEBUG_DTP_REG_START               0x01007c98
+#define BCHP_OL_QUEUE_19_DEBUG_DTP_REG_END                 0x01007c9c
+#define BCHP_OL_QUEUE_20_DEBUG_DTP_REG_START               0x01007ca0
+#define BCHP_OL_QUEUE_20_DEBUG_DTP_REG_END                 0x01007ca4
+#define BCHP_OL_QUEUE_21_DEBUG_DTP_REG_START               0x01007ca8
+#define BCHP_OL_QUEUE_21_DEBUG_DTP_REG_END                 0x01007cac
+#define BCHP_OL_QUEUE_22_DEBUG_DTP_REG_START               0x01007cb0
+#define BCHP_OL_QUEUE_22_DEBUG_DTP_REG_END                 0x01007cb4
+#define BCHP_OL_QUEUE_23_DEBUG_DTP_REG_START               0x01007cb8
+#define BCHP_OL_QUEUE_23_DEBUG_DTP_REG_END                 0x01007cbc
+#define BCHP_OL_QUEUE_24_DEBUG_DTP_REG_START               0x01007cc0
+#define BCHP_OL_QUEUE_24_DEBUG_DTP_REG_END                 0x01007cc4
+#define BCHP_OL_QUEUE_25_DEBUG_DTP_REG_START               0x01007cc8
+#define BCHP_OL_QUEUE_25_DEBUG_DTP_REG_END                 0x01007ccc
+#define BCHP_OL_QUEUE_26_DEBUG_DTP_REG_START               0x01007cd0
+#define BCHP_OL_QUEUE_26_DEBUG_DTP_REG_END                 0x01007cd4
+#define BCHP_OL_QUEUE_27_DEBUG_DTP_REG_START               0x01007cd8
+#define BCHP_OL_QUEUE_27_DEBUG_DTP_REG_END                 0x01007cdc
+#define BCHP_OL_QUEUE_28_DEBUG_DTP_REG_START               0x01007ce0
+#define BCHP_OL_QUEUE_28_DEBUG_DTP_REG_END                 0x01007ce4
+#define BCHP_OL_QUEUE_29_DEBUG_DTP_REG_START               0x01007ce8
+#define BCHP_OL_QUEUE_29_DEBUG_DTP_REG_END                 0x01007cec
+#define BCHP_OL_QUEUE_30_DEBUG_DTP_REG_START               0x01007cf0
+#define BCHP_OL_QUEUE_30_DEBUG_DTP_REG_END                 0x01007cf4
+#define BCHP_OL_QUEUE_31_DEBUG_DTP_REG_START               0x01007cf8
+#define BCHP_OL_QUEUE_31_DEBUG_DTP_REG_END                 0x01007cfc
+#define BCHP_OL_QUEUE_0_CNTRL_DTP_REG_START                0x01008000
+#define BCHP_OL_QUEUE_0_CNTRL_DTP_REG_END                  0x0100801c
+#define BCHP_OL_QUEUE_1_CNTRL_DTP_REG_START                0x01008020
+#define BCHP_OL_QUEUE_1_CNTRL_DTP_REG_END                  0x0100803c
+#define BCHP_OL_QUEUE_2_CNTRL_DTP_REG_START                0x01008040
+#define BCHP_OL_QUEUE_2_CNTRL_DTP_REG_END                  0x0100805c
+#define BCHP_OL_QUEUE_3_CNTRL_DTP_REG_START                0x01008060
+#define BCHP_OL_QUEUE_3_CNTRL_DTP_REG_END                  0x0100807c
+#define BCHP_OL_QUEUE_4_CNTRL_DTP_REG_START                0x01008080
+#define BCHP_OL_QUEUE_4_CNTRL_DTP_REG_END                  0x0100809c
+#define BCHP_OL_QUEUE_5_CNTRL_DTP_REG_START                0x010080a0
+#define BCHP_OL_QUEUE_5_CNTRL_DTP_REG_END                  0x010080bc
+#define BCHP_OL_QUEUE_6_CNTRL_DTP_REG_START                0x010080c0
+#define BCHP_OL_QUEUE_6_CNTRL_DTP_REG_END                  0x010080dc
+#define BCHP_OL_QUEUE_7_CNTRL_DTP_REG_START                0x010080e0
+#define BCHP_OL_QUEUE_7_CNTRL_DTP_REG_END                  0x010080fc
+#define BCHP_OL_QUEUE_8_CNTRL_DTP_REG_START                0x01008100
+#define BCHP_OL_QUEUE_8_CNTRL_DTP_REG_END                  0x0100811c
+#define BCHP_OL_QUEUE_9_CNTRL_DTP_REG_START                0x01008120
+#define BCHP_OL_QUEUE_9_CNTRL_DTP_REG_END                  0x0100813c
+#define BCHP_OL_QUEUE_10_CNTRL_DTP_REG_START               0x01008140
+#define BCHP_OL_QUEUE_10_CNTRL_DTP_REG_END                 0x0100815c
+#define BCHP_OL_QUEUE_11_CNTRL_DTP_REG_START               0x01008160
+#define BCHP_OL_QUEUE_11_CNTRL_DTP_REG_END                 0x0100817c
+#define BCHP_OL_QUEUE_12_CNTRL_DTP_REG_START               0x01008180
+#define BCHP_OL_QUEUE_12_CNTRL_DTP_REG_END                 0x0100819c
+#define BCHP_OL_QUEUE_13_CNTRL_DTP_REG_START               0x010081a0
+#define BCHP_OL_QUEUE_13_CNTRL_DTP_REG_END                 0x010081bc
+#define BCHP_OL_QUEUE_14_CNTRL_DTP_REG_START               0x010081c0
+#define BCHP_OL_QUEUE_14_CNTRL_DTP_REG_END                 0x010081dc
+#define BCHP_OL_QUEUE_15_CNTRL_DTP_REG_START               0x010081e0
+#define BCHP_OL_QUEUE_15_CNTRL_DTP_REG_END                 0x010081fc
+#define BCHP_OL_QUEUE_16_CNTRL_DTP_REG_START               0x01008200
+#define BCHP_OL_QUEUE_16_CNTRL_DTP_REG_END                 0x0100821c
+#define BCHP_OL_QUEUE_17_CNTRL_DTP_REG_START               0x01008220
+#define BCHP_OL_QUEUE_17_CNTRL_DTP_REG_END                 0x0100823c
+#define BCHP_OL_QUEUE_18_CNTRL_DTP_REG_START               0x01008240
+#define BCHP_OL_QUEUE_18_CNTRL_DTP_REG_END                 0x0100825c
+#define BCHP_OL_QUEUE_19_CNTRL_DTP_REG_START               0x01008260
+#define BCHP_OL_QUEUE_19_CNTRL_DTP_REG_END                 0x0100827c
+#define BCHP_OL_QUEUE_20_CNTRL_DTP_REG_START               0x01008280
+#define BCHP_OL_QUEUE_20_CNTRL_DTP_REG_END                 0x0100829c
+#define BCHP_OL_QUEUE_21_CNTRL_DTP_REG_START               0x010082a0
+#define BCHP_OL_QUEUE_21_CNTRL_DTP_REG_END                 0x010082bc
+#define BCHP_OL_QUEUE_22_CNTRL_DTP_REG_START               0x010082c0
+#define BCHP_OL_QUEUE_22_CNTRL_DTP_REG_END                 0x010082dc
+#define BCHP_OL_QUEUE_23_CNTRL_DTP_REG_START               0x010082e0
+#define BCHP_OL_QUEUE_23_CNTRL_DTP_REG_END                 0x010082fc
+#define BCHP_OL_QUEUE_24_CNTRL_DTP_REG_START               0x01008300
+#define BCHP_OL_QUEUE_24_CNTRL_DTP_REG_END                 0x0100831c
+#define BCHP_OL_QUEUE_25_CNTRL_DTP_REG_START               0x01008320
+#define BCHP_OL_QUEUE_25_CNTRL_DTP_REG_END                 0x0100833c
+#define BCHP_OL_QUEUE_26_CNTRL_DTP_REG_START               0x01008340
+#define BCHP_OL_QUEUE_26_CNTRL_DTP_REG_END                 0x0100835c
+#define BCHP_OL_QUEUE_27_CNTRL_DTP_REG_START               0x01008360
+#define BCHP_OL_QUEUE_27_CNTRL_DTP_REG_END                 0x0100837c
+#define BCHP_OL_QUEUE_28_CNTRL_DTP_REG_START               0x01008380
+#define BCHP_OL_QUEUE_28_CNTRL_DTP_REG_END                 0x0100839c
+#define BCHP_OL_QUEUE_29_CNTRL_DTP_REG_START               0x010083a0
+#define BCHP_OL_QUEUE_29_CNTRL_DTP_REG_END                 0x010083bc
+#define BCHP_OL_QUEUE_30_CNTRL_DTP_REG_START               0x010083c0
+#define BCHP_OL_QUEUE_30_CNTRL_DTP_REG_END                 0x010083dc
+#define BCHP_OL_QUEUE_31_CNTRL_DTP_REG_START               0x010083e0
+#define BCHP_OL_QUEUE_31_CNTRL_DTP_REG_END                 0x010083fc
+#define BCHP_OL_QUEUE_0_DATA_DTP_REG_START                 0x01009000
+#define BCHP_OL_QUEUE_0_DATA_DTP_REG_END                   0x0100901c
+#define BCHP_OL_QUEUE_1_DATA_DTP_REG_START                 0x01009020
+#define BCHP_OL_QUEUE_1_DATA_DTP_REG_END                   0x0100903c
+#define BCHP_OL_QUEUE_2_DATA_DTP_REG_START                 0x01009040
+#define BCHP_OL_QUEUE_2_DATA_DTP_REG_END                   0x0100905c
+#define BCHP_OL_QUEUE_3_DATA_DTP_REG_START                 0x01009060
+#define BCHP_OL_QUEUE_3_DATA_DTP_REG_END                   0x0100907c
+#define BCHP_OL_QUEUE_4_DATA_DTP_REG_START                 0x01009080
+#define BCHP_OL_QUEUE_4_DATA_DTP_REG_END                   0x0100909c
+#define BCHP_OL_QUEUE_5_DATA_DTP_REG_START                 0x010090a0
+#define BCHP_OL_QUEUE_5_DATA_DTP_REG_END                   0x010090bc
+#define BCHP_OL_QUEUE_6_DATA_DTP_REG_START                 0x010090c0
+#define BCHP_OL_QUEUE_6_DATA_DTP_REG_END                   0x010090dc
+#define BCHP_OL_QUEUE_7_DATA_DTP_REG_START                 0x010090e0
+#define BCHP_OL_QUEUE_7_DATA_DTP_REG_END                   0x010090fc
+#define BCHP_OL_QUEUE_8_DATA_DTP_REG_START                 0x01009100
+#define BCHP_OL_QUEUE_8_DATA_DTP_REG_END                   0x0100911c
+#define BCHP_OL_QUEUE_9_DATA_DTP_REG_START                 0x01009120
+#define BCHP_OL_QUEUE_9_DATA_DTP_REG_END                   0x0100913c
+#define BCHP_OL_QUEUE_10_DATA_DTP_REG_START                0x01009140
+#define BCHP_OL_QUEUE_10_DATA_DTP_REG_END                  0x0100915c
+#define BCHP_OL_QUEUE_11_DATA_DTP_REG_START                0x01009160
+#define BCHP_OL_QUEUE_11_DATA_DTP_REG_END                  0x0100917c
+#define BCHP_OL_QUEUE_12_DATA_DTP_REG_START                0x01009180
+#define BCHP_OL_QUEUE_12_DATA_DTP_REG_END                  0x0100919c
+#define BCHP_OL_QUEUE_13_DATA_DTP_REG_START                0x010091a0
+#define BCHP_OL_QUEUE_13_DATA_DTP_REG_END                  0x010091bc
+#define BCHP_OL_QUEUE_14_DATA_DTP_REG_START                0x010091c0
+#define BCHP_OL_QUEUE_14_DATA_DTP_REG_END                  0x010091dc
+#define BCHP_OL_QUEUE_15_DATA_DTP_REG_START                0x010091e0
+#define BCHP_OL_QUEUE_15_DATA_DTP_REG_END                  0x010091fc
+#define BCHP_OL_QUEUE_16_DATA_DTP_REG_START                0x01009200
+#define BCHP_OL_QUEUE_16_DATA_DTP_REG_END                  0x0100921c
+#define BCHP_OL_QUEUE_17_DATA_DTP_REG_START                0x01009220
+#define BCHP_OL_QUEUE_17_DATA_DTP_REG_END                  0x0100923c
+#define BCHP_OL_QUEUE_18_DATA_DTP_REG_START                0x01009240
+#define BCHP_OL_QUEUE_18_DATA_DTP_REG_END                  0x0100925c
+#define BCHP_OL_QUEUE_19_DATA_DTP_REG_START                0x01009260
+#define BCHP_OL_QUEUE_19_DATA_DTP_REG_END                  0x0100927c
+#define BCHP_OL_QUEUE_20_DATA_DTP_REG_START                0x01009280
+#define BCHP_OL_QUEUE_20_DATA_DTP_REG_END                  0x0100929c
+#define BCHP_OL_QUEUE_21_DATA_DTP_REG_START                0x010092a0
+#define BCHP_OL_QUEUE_21_DATA_DTP_REG_END                  0x010092bc
+#define BCHP_OL_QUEUE_22_DATA_DTP_REG_START                0x010092c0
+#define BCHP_OL_QUEUE_22_DATA_DTP_REG_END                  0x010092dc
+#define BCHP_OL_QUEUE_23_DATA_DTP_REG_START                0x010092e0
+#define BCHP_OL_QUEUE_23_DATA_DTP_REG_END                  0x010092fc
+#define BCHP_OL_QUEUE_24_DATA_DTP_REG_START                0x01009300
+#define BCHP_OL_QUEUE_24_DATA_DTP_REG_END                  0x0100931c
+#define BCHP_OL_QUEUE_25_DATA_DTP_REG_START                0x01009320
+#define BCHP_OL_QUEUE_25_DATA_DTP_REG_END                  0x0100933c
+#define BCHP_OL_QUEUE_26_DATA_DTP_REG_START                0x01009340
+#define BCHP_OL_QUEUE_26_DATA_DTP_REG_END                  0x0100935c
+#define BCHP_OL_QUEUE_27_DATA_DTP_REG_START                0x01009360
+#define BCHP_OL_QUEUE_27_DATA_DTP_REG_END                  0x0100937c
+#define BCHP_OL_QUEUE_28_DATA_DTP_REG_START                0x01009380
+#define BCHP_OL_QUEUE_28_DATA_DTP_REG_END                  0x0100939c
+#define BCHP_OL_QUEUE_29_DATA_DTP_REG_START                0x010093a0
+#define BCHP_OL_QUEUE_29_DATA_DTP_REG_END                  0x010093bc
+#define BCHP_OL_QUEUE_30_DATA_DTP_REG_START                0x010093c0
+#define BCHP_OL_QUEUE_30_DATA_DTP_REG_END                  0x010093dc
+#define BCHP_OL_QUEUE_31_DATA_DTP_REG_START                0x010093e0
+#define BCHP_OL_QUEUE_31_DATA_DTP_REG_END                  0x010093fc
+#define BCHP_OL_QUEUE_MIB_DTP_REG_START                    0x0100a000
+#define BCHP_OL_QUEUE_MIB_DTP_REG_END                      0x0100a17c
+#define BCHP_QueueSharedMem_DTP_REG_START                  0x01040000
+#define BCHP_QueueSharedMem_DTP_REG_END                    0x0104bffc
+#define BCHP_PacketSharedMemory_DTP_REG_START              0x01080000
+#define BCHP_PacketSharedMemory_DTP_REG_END                0x01080ffc
+#define BCHP_DSRM_DTP_REG_START                            0x01100000
+#define BCHP_DSRM_DTP_REG_END                              0x011006ec
+#define BCHP_DSRM_MAX_RATE_DTP_REG_START                   0x01100700
+#define BCHP_DSRM_MAX_RATE_DTP_REG_END                     0x0110070c
+#define BCHP_DSRM_PEAK_RATE_DTP_REG_START                  0x01100710
+#define BCHP_DSRM_PEAK_RATE_DTP_REG_END                    0x0110071c
+#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_START              0x01100800
+#define BCHP_DSRM_TAG_CACHE_MEM_DTP_REG_END                0x011008fc
+#define BCHP_DSRM_STATE_MEM_DTP_REG_START                  0x01101000
+#define BCHP_DSRM_STATE_MEM_DTP_REG_END                    0x011017fc
+#define BCHP_DSRM_STATS_MEM_DTP_REG_START                  0x01102000
+#define BCHP_DSRM_STATS_MEM_DTP_REG_END                    0x01102ffc
+#define BCHP_DSRM_TMOUT_MEM_DTP_REG_START                  0x01103000
+#define BCHP_DSRM_TMOUT_MEM_DTP_REG_END                    0x01103ffc
+#define BCHP_DSRM_TAG_MEM_DTP_REG_START                    0x01104000
+#define BCHP_DSRM_TAG_MEM_DTP_REG_END                      0x011057fc
+#define BCHP_DSRM_RLD_MEM_DTP_REG_START                    0x01106000
+#define BCHP_DSRM_RLD_MEM_DTP_REG_END                      0x01107fc4
+#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_START             0x01108000
+#define BCHP_DSRM_FREE_CLSTR_MEM_DTP_REG_END               0x011082fc
+#define BCHP_DSRM_CLSTR_MEM_DTP_REG_START                  0x01110000
+#define BCHP_DSRM_CLSTR_MEM_DTP_REG_END                    0x01117ffc
+#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_START             0x01180000
+#define BCHP_DSRM_SPARSE_ARY_MEM_DTP_REG_END               0x011afffc
+#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_START         0x011c0000
+#define BCHP_DSRM_SPARSE_ARY_AUX_MEM_DTP_REG_END           0x011efffc
+#define BCHP_BaseReserved_DFAP_REG_START                   0x01200000
+#define BCHP_BaseReserved_DFAP_REG_END                     0x01200000
+#define BCHP_Control_DFAP_REG_START                        0x01201000
+#define BCHP_Control_DFAP_REG_END                          0x012010fc
+#define BCHP_OutgoingMessageFIFO_DFAP_REG_START            0x01201100
+#define BCHP_OutgoingMessageFIFO_DFAP_REG_END              0x0120117c
+#define BCHP_IncomingMessageFIFO_DFAP_REG_START            0x01201200
+#define BCHP_IncomingMessageFIFO_DFAP_REG_END              0x0120127c
+#define BCHP_DMA0_DFAP_REG_START                           0x01201300
+#define BCHP_DMA0_DFAP_REG_END                             0x0120131c
+#define BCHP_DMA1_DFAP_REG_START                           0x01201320
+#define BCHP_DMA1_DFAP_REG_END                             0x0120133c
+#define BCHP_DMAHI0_DFAP_REG_START                         0x01201340
+#define BCHP_DMAHI0_DFAP_REG_END                           0x0120134c
+#define BCHP_DMAHI1_DFAP_REG_START                         0x01201350
+#define BCHP_DMAHI1_DFAP_REG_END                           0x0120135c
+#define BCHP_Token_DFAP_REG_START                          0x01201400
+#define BCHP_Token_DFAP_REG_END                            0x01201420
+#define BCHP_PerfPower_DFAP_REG_START                      0x01201600
+#define BCHP_PerfPower_DFAP_REG_END                        0x01201640
+#define BCHP_MessageID_DFAP_REG_START                      0x01201700
+#define BCHP_MessageID_DFAP_REG_END                        0x0120177c
+#define BCHP_HWCounters_DFAP_REG_START                     0x01201900
+#define BCHP_HWCounters_DFAP_REG_END                       0x01201944
+#define BCHP_DQM_0_31_DFAP_REG_START                       0x01201c00
+#define BCHP_DQM_0_31_DFAP_REG_END                         0x01201c48
+#define BCHP_DQM_32_63_DFAP_REG_START                      0x01201d00
+#define BCHP_DQM_32_63_DFAP_REG_END                        0x01201d48
+#define BCHP_QUEUE_TIMER_DFAP_REG_START                    0x01202000
+#define BCHP_QUEUE_TIMER_DFAP_REG_END                      0x012021fc
+#define BCHP_QUEUE_STATUS_0_31_DFAP_REG_START              0x01202800
+#define BCHP_QUEUE_STATUS_0_31_DFAP_REG_END                0x0120287c
+#define BCHP_QUEUE_STATUS_32_63_DFAP_REG_START             0x01202900
+#define BCHP_QUEUE_STATUS_32_63_DFAP_REG_END               0x0120297c
+#define BCHP_QUEUE_MIB_0_31_DFAP_REG_START                 0x01203000
+#define BCHP_QUEUE_MIB_0_31_DFAP_REG_END                   0x0120317c
+#define BCHP_QUEUE_MIB_32_63_DFAP_REG_START                0x01203200
+#define BCHP_QUEUE_MIB_32_63_DFAP_REG_END                  0x0120337c
+#define BCHP_QUEUE_0_CNTRL_DFAP_REG_START                  0x01204000
+#define BCHP_QUEUE_0_CNTRL_DFAP_REG_END                    0x0120400c
+#define BCHP_QUEUE_1_CNTRL_DFAP_REG_START                  0x01204010
+#define BCHP_QUEUE_1_CNTRL_DFAP_REG_END                    0x0120401c
+#define BCHP_QUEUE_2_CNTRL_DFAP_REG_START                  0x01204020
+#define BCHP_QUEUE_2_CNTRL_DFAP_REG_END                    0x0120402c
+#define BCHP_QUEUE_3_CNTRL_DFAP_REG_START                  0x01204030
+#define BCHP_QUEUE_3_CNTRL_DFAP_REG_END                    0x0120403c
+#define BCHP_QUEUE_4_CNTRL_DFAP_REG_START                  0x01204040
+#define BCHP_QUEUE_4_CNTRL_DFAP_REG_END                    0x0120404c
+#define BCHP_QUEUE_5_CNTRL_DFAP_REG_START                  0x01204050
+#define BCHP_QUEUE_5_CNTRL_DFAP_REG_END                    0x0120405c
+#define BCHP_QUEUE_6_CNTRL_DFAP_REG_START                  0x01204060
+#define BCHP_QUEUE_6_CNTRL_DFAP_REG_END                    0x0120406c
+#define BCHP_QUEUE_7_CNTRL_DFAP_REG_START                  0x01204070
+#define BCHP_QUEUE_7_CNTRL_DFAP_REG_END                    0x0120407c
+#define BCHP_QUEUE_8_CNTRL_DFAP_REG_START                  0x01204080
+#define BCHP_QUEUE_8_CNTRL_DFAP_REG_END                    0x0120408c
+#define BCHP_QUEUE_9_CNTRL_DFAP_REG_START                  0x01204090
+#define BCHP_QUEUE_9_CNTRL_DFAP_REG_END                    0x0120409c
+#define BCHP_QUEUE_10_CNTRL_DFAP_REG_START                 0x012040a0
+#define BCHP_QUEUE_10_CNTRL_DFAP_REG_END                   0x012040ac
+#define BCHP_QUEUE_11_CNTRL_DFAP_REG_START                 0x012040b0
+#define BCHP_QUEUE_11_CNTRL_DFAP_REG_END                   0x012040bc
+#define BCHP_QUEUE_12_CNTRL_DFAP_REG_START                 0x012040c0
+#define BCHP_QUEUE_12_CNTRL_DFAP_REG_END                   0x012040cc
+#define BCHP_QUEUE_13_CNTRL_DFAP_REG_START                 0x012040d0
+#define BCHP_QUEUE_13_CNTRL_DFAP_REG_END                   0x012040dc
+#define BCHP_QUEUE_14_CNTRL_DFAP_REG_START                 0x012040e0
+#define BCHP_QUEUE_14_CNTRL_DFAP_REG_END                   0x012040ec
+#define BCHP_QUEUE_15_CNTRL_DFAP_REG_START                 0x012040f0
+#define BCHP_QUEUE_15_CNTRL_DFAP_REG_END                   0x012040fc
+#define BCHP_QUEUE_16_CNTRL_DFAP_REG_START                 0x01204100
+#define BCHP_QUEUE_16_CNTRL_DFAP_REG_END                   0x0120410c
+#define BCHP_QUEUE_17_CNTRL_DFAP_REG_START                 0x01204110
+#define BCHP_QUEUE_17_CNTRL_DFAP_REG_END                   0x0120411c
+#define BCHP_QUEUE_18_CNTRL_DFAP_REG_START                 0x01204120
+#define BCHP_QUEUE_18_CNTRL_DFAP_REG_END                   0x0120412c
+#define BCHP_QUEUE_19_CNTRL_DFAP_REG_START                 0x01204130
+#define BCHP_QUEUE_19_CNTRL_DFAP_REG_END                   0x0120413c
+#define BCHP_QUEUE_20_CNTRL_DFAP_REG_START                 0x01204140
+#define BCHP_QUEUE_20_CNTRL_DFAP_REG_END                   0x0120414c
+#define BCHP_QUEUE_21_CNTRL_DFAP_REG_START                 0x01204150
+#define BCHP_QUEUE_21_CNTRL_DFAP_REG_END                   0x0120415c
+#define BCHP_QUEUE_22_CNTRL_DFAP_REG_START                 0x01204160
+#define BCHP_QUEUE_22_CNTRL_DFAP_REG_END                   0x0120416c
+#define BCHP_QUEUE_23_CNTRL_DFAP_REG_START                 0x01204170
+#define BCHP_QUEUE_23_CNTRL_DFAP_REG_END                   0x0120417c
+#define BCHP_QUEUE_24_CNTRL_DFAP_REG_START                 0x01204180
+#define BCHP_QUEUE_24_CNTRL_DFAP_REG_END                   0x0120418c
+#define BCHP_QUEUE_25_CNTRL_DFAP_REG_START                 0x01204190
+#define BCHP_QUEUE_25_CNTRL_DFAP_REG_END                   0x0120419c
+#define BCHP_QUEUE_26_CNTRL_DFAP_REG_START                 0x012041a0
+#define BCHP_QUEUE_26_CNTRL_DFAP_REG_END                   0x012041ac
+#define BCHP_QUEUE_27_CNTRL_DFAP_REG_START                 0x012041b0
+#define BCHP_QUEUE_27_CNTRL_DFAP_REG_END                   0x012041bc
+#define BCHP_QUEUE_28_CNTRL_DFAP_REG_START                 0x012041c0
+#define BCHP_QUEUE_28_CNTRL_DFAP_REG_END                   0x012041cc
+#define BCHP_QUEUE_29_CNTRL_DFAP_REG_START                 0x012041d0
+#define BCHP_QUEUE_29_CNTRL_DFAP_REG_END                   0x012041dc
+#define BCHP_QUEUE_30_CNTRL_DFAP_REG_START                 0x012041e0
+#define BCHP_QUEUE_30_CNTRL_DFAP_REG_END                   0x012041ec
+#define BCHP_QUEUE_31_CNTRL_DFAP_REG_START                 0x012041f0
+#define BCHP_QUEUE_31_CNTRL_DFAP_REG_END                   0x012041fc
+#define BCHP_QUEUE_32_CNTRL_DFAP_REG_START                 0x01204200
+#define BCHP_QUEUE_32_CNTRL_DFAP_REG_END                   0x0120420c
+#define BCHP_QUEUE_33_CNTRL_DFAP_REG_START                 0x01204210
+#define BCHP_QUEUE_33_CNTRL_DFAP_REG_END                   0x0120421c
+#define BCHP_QUEUE_34_CNTRL_DFAP_REG_START                 0x01204220
+#define BCHP_QUEUE_34_CNTRL_DFAP_REG_END                   0x0120422c
+#define BCHP_QUEUE_35_CNTRL_DFAP_REG_START                 0x01204230
+#define BCHP_QUEUE_35_CNTRL_DFAP_REG_END                   0x0120423c
+#define BCHP_QUEUE_36_CNTRL_DFAP_REG_START                 0x01204240
+#define BCHP_QUEUE_36_CNTRL_DFAP_REG_END                   0x0120424c
+#define BCHP_QUEUE_37_CNTRL_DFAP_REG_START                 0x01204250
+#define BCHP_QUEUE_37_CNTRL_DFAP_REG_END                   0x0120425c
+#define BCHP_QUEUE_38_CNTRL_DFAP_REG_START                 0x01204260
+#define BCHP_QUEUE_38_CNTRL_DFAP_REG_END                   0x0120426c
+#define BCHP_QUEUE_39_CNTRL_DFAP_REG_START                 0x01204270
+#define BCHP_QUEUE_39_CNTRL_DFAP_REG_END                   0x0120427c
+#define BCHP_QUEUE_40_CNTRL_DFAP_REG_START                 0x01204280
+#define BCHP_QUEUE_40_CNTRL_DFAP_REG_END                   0x0120428c
+#define BCHP_QUEUE_41_CNTRL_DFAP_REG_START                 0x01204290
+#define BCHP_QUEUE_41_CNTRL_DFAP_REG_END                   0x0120429c
+#define BCHP_QUEUE_42_CNTRL_DFAP_REG_START                 0x012042a0
+#define BCHP_QUEUE_42_CNTRL_DFAP_REG_END                   0x012042ac
+#define BCHP_QUEUE_43_CNTRL_DFAP_REG_START                 0x012042b0
+#define BCHP_QUEUE_43_CNTRL_DFAP_REG_END                   0x012042bc
+#define BCHP_QUEUE_44_CNTRL_DFAP_REG_START                 0x012042c0
+#define BCHP_QUEUE_44_CNTRL_DFAP_REG_END                   0x012042cc
+#define BCHP_QUEUE_45_CNTRL_DFAP_REG_START                 0x012042d0
+#define BCHP_QUEUE_45_CNTRL_DFAP_REG_END                   0x012042dc
+#define BCHP_QUEUE_46_CNTRL_DFAP_REG_START                 0x012042e0
+#define BCHP_QUEUE_46_CNTRL_DFAP_REG_END                   0x012042ec
+#define BCHP_QUEUE_47_CNTRL_DFAP_REG_START                 0x012042f0
+#define BCHP_QUEUE_47_CNTRL_DFAP_REG_END                   0x012042fc
+#define BCHP_QUEUE_48_CNTRL_DFAP_REG_START                 0x01204300
+#define BCHP_QUEUE_48_CNTRL_DFAP_REG_END                   0x0120430c
+#define BCHP_QUEUE_49_CNTRL_DFAP_REG_START                 0x01204310
+#define BCHP_QUEUE_49_CNTRL_DFAP_REG_END                   0x0120431c
+#define BCHP_QUEUE_50_CNTRL_DFAP_REG_START                 0x01204320
+#define BCHP_QUEUE_50_CNTRL_DFAP_REG_END                   0x0120432c
+#define BCHP_QUEUE_51_CNTRL_DFAP_REG_START                 0x01204330
+#define BCHP_QUEUE_51_CNTRL_DFAP_REG_END                   0x0120433c
+#define BCHP_QUEUE_52_CNTRL_DFAP_REG_START                 0x01204340
+#define BCHP_QUEUE_52_CNTRL_DFAP_REG_END                   0x0120434c
+#define BCHP_QUEUE_53_CNTRL_DFAP_REG_START                 0x01204350
+#define BCHP_QUEUE_53_CNTRL_DFAP_REG_END                   0x0120435c
+#define BCHP_QUEUE_54_CNTRL_DFAP_REG_START                 0x01204360
+#define BCHP_QUEUE_54_CNTRL_DFAP_REG_END                   0x0120436c
+#define BCHP_QUEUE_55_CNTRL_DFAP_REG_START                 0x01204370
+#define BCHP_QUEUE_55_CNTRL_DFAP_REG_END                   0x0120437c
+#define BCHP_QUEUE_56_CNTRL_DFAP_REG_START                 0x01204380
+#define BCHP_QUEUE_56_CNTRL_DFAP_REG_END                   0x0120438c
+#define BCHP_QUEUE_57_CNTRL_DFAP_REG_START                 0x01204390
+#define BCHP_QUEUE_57_CNTRL_DFAP_REG_END                   0x0120439c
+#define BCHP_QUEUE_58_CNTRL_DFAP_REG_START                 0x012043a0
+#define BCHP_QUEUE_58_CNTRL_DFAP_REG_END                   0x012043ac
+#define BCHP_QUEUE_59_CNTRL_DFAP_REG_START                 0x012043b0
+#define BCHP_QUEUE_59_CNTRL_DFAP_REG_END                   0x012043bc
+#define BCHP_QUEUE_60_CNTRL_DFAP_REG_START                 0x012043c0
+#define BCHP_QUEUE_60_CNTRL_DFAP_REG_END                   0x012043cc
+#define BCHP_QUEUE_61_CNTRL_DFAP_REG_START                 0x012043d0
+#define BCHP_QUEUE_61_CNTRL_DFAP_REG_END                   0x012043dc
+#define BCHP_QUEUE_62_CNTRL_DFAP_REG_START                 0x012043e0
+#define BCHP_QUEUE_62_CNTRL_DFAP_REG_END                   0x012043ec
+#define BCHP_QUEUE_63_CNTRL_DFAP_REG_START                 0x012043f0
+#define BCHP_QUEUE_63_CNTRL_DFAP_REG_END                   0x012043fc
+#define BCHP_QUEUE_0_DATA_DFAP_REG_START                   0x01205000
+#define BCHP_QUEUE_0_DATA_DFAP_REG_END                     0x0120500c
+#define BCHP_QUEUE_1_DATA_DFAP_REG_START                   0x01205010
+#define BCHP_QUEUE_1_DATA_DFAP_REG_END                     0x0120501c
+#define BCHP_QUEUE_2_DATA_DFAP_REG_START                   0x01205020
+#define BCHP_QUEUE_2_DATA_DFAP_REG_END                     0x0120502c
+#define BCHP_QUEUE_3_DATA_DFAP_REG_START                   0x01205030
+#define BCHP_QUEUE_3_DATA_DFAP_REG_END                     0x0120503c
+#define BCHP_QUEUE_4_DATA_DFAP_REG_START                   0x01205040
+#define BCHP_QUEUE_4_DATA_DFAP_REG_END                     0x0120504c
+#define BCHP_QUEUE_5_DATA_DFAP_REG_START                   0x01205050
+#define BCHP_QUEUE_5_DATA_DFAP_REG_END                     0x0120505c
+#define BCHP_QUEUE_6_DATA_DFAP_REG_START                   0x01205060
+#define BCHP_QUEUE_6_DATA_DFAP_REG_END                     0x0120506c
+#define BCHP_QUEUE_7_DATA_DFAP_REG_START                   0x01205070
+#define BCHP_QUEUE_7_DATA_DFAP_REG_END                     0x0120507c
+#define BCHP_QUEUE_8_DATA_DFAP_REG_START                   0x01205080
+#define BCHP_QUEUE_8_DATA_DFAP_REG_END                     0x0120508c
+#define BCHP_QUEUE_9_DATA_DFAP_REG_START                   0x01205090
+#define BCHP_QUEUE_9_DATA_DFAP_REG_END                     0x0120509c
+#define BCHP_QUEUE_10_DATA_DFAP_REG_START                  0x012050a0
+#define BCHP_QUEUE_10_DATA_DFAP_REG_END                    0x012050ac
+#define BCHP_QUEUE_11_DATA_DFAP_REG_START                  0x012050b0
+#define BCHP_QUEUE_11_DATA_DFAP_REG_END                    0x012050bc
+#define BCHP_QUEUE_12_DATA_DFAP_REG_START                  0x012050c0
+#define BCHP_QUEUE_12_DATA_DFAP_REG_END                    0x012050cc
+#define BCHP_QUEUE_13_DATA_DFAP_REG_START                  0x012050d0
+#define BCHP_QUEUE_13_DATA_DFAP_REG_END                    0x012050dc
+#define BCHP_QUEUE_14_DATA_DFAP_REG_START                  0x012050e0
+#define BCHP_QUEUE_14_DATA_DFAP_REG_END                    0x012050ec
+#define BCHP_QUEUE_15_DATA_DFAP_REG_START                  0x012050f0
+#define BCHP_QUEUE_15_DATA_DFAP_REG_END                    0x012050fc
+#define BCHP_QUEUE_16_DATA_DFAP_REG_START                  0x01205100
+#define BCHP_QUEUE_16_DATA_DFAP_REG_END                    0x0120510c
+#define BCHP_QUEUE_17_DATA_DFAP_REG_START                  0x01205110
+#define BCHP_QUEUE_17_DATA_DFAP_REG_END                    0x0120511c
+#define BCHP_QUEUE_18_DATA_DFAP_REG_START                  0x01205120
+#define BCHP_QUEUE_18_DATA_DFAP_REG_END                    0x0120512c
+#define BCHP_QUEUE_19_DATA_DFAP_REG_START                  0x01205130
+#define BCHP_QUEUE_19_DATA_DFAP_REG_END                    0x0120513c
+#define BCHP_QUEUE_20_DATA_DFAP_REG_START                  0x01205140
+#define BCHP_QUEUE_20_DATA_DFAP_REG_END                    0x0120514c
+#define BCHP_QUEUE_21_DATA_DFAP_REG_START                  0x01205150
+#define BCHP_QUEUE_21_DATA_DFAP_REG_END                    0x0120515c
+#define BCHP_QUEUE_22_DATA_DFAP_REG_START                  0x01205160
+#define BCHP_QUEUE_22_DATA_DFAP_REG_END                    0x0120516c
+#define BCHP_QUEUE_23_DATA_DFAP_REG_START                  0x01205170
+#define BCHP_QUEUE_23_DATA_DFAP_REG_END                    0x0120517c
+#define BCHP_QUEUE_24_DATA_DFAP_REG_START                  0x01205180
+#define BCHP_QUEUE_24_DATA_DFAP_REG_END                    0x0120518c
+#define BCHP_QUEUE_25_DATA_DFAP_REG_START                  0x01205190
+#define BCHP_QUEUE_25_DATA_DFAP_REG_END                    0x0120519c
+#define BCHP_QUEUE_26_DATA_DFAP_REG_START                  0x012051a0
+#define BCHP_QUEUE_26_DATA_DFAP_REG_END                    0x012051ac
+#define BCHP_QUEUE_27_DATA_DFAP_REG_START                  0x012051b0
+#define BCHP_QUEUE_27_DATA_DFAP_REG_END                    0x012051bc
+#define BCHP_QUEUE_28_DATA_DFAP_REG_START                  0x012051c0
+#define BCHP_QUEUE_28_DATA_DFAP_REG_END                    0x012051cc
+#define BCHP_QUEUE_29_DATA_DFAP_REG_START                  0x012051d0
+#define BCHP_QUEUE_29_DATA_DFAP_REG_END                    0x012051dc
+#define BCHP_QUEUE_30_DATA_DFAP_REG_START                  0x012051e0
+#define BCHP_QUEUE_30_DATA_DFAP_REG_END                    0x012051ec
+#define BCHP_QUEUE_31_DATA_DFAP_REG_START                  0x012051f0
+#define BCHP_QUEUE_31_DATA_DFAP_REG_END                    0x012051fc
+#define BCHP_QUEUE_32_DATA_DFAP_REG_START                  0x01205200
+#define BCHP_QUEUE_32_DATA_DFAP_REG_END                    0x0120520c
+#define BCHP_QUEUE_33_DATA_DFAP_REG_START                  0x01205210
+#define BCHP_QUEUE_33_DATA_DFAP_REG_END                    0x0120521c
+#define BCHP_QUEUE_34_DATA_DFAP_REG_START                  0x01205220
+#define BCHP_QUEUE_34_DATA_DFAP_REG_END                    0x0120522c
+#define BCHP_QUEUE_35_DATA_DFAP_REG_START                  0x01205230
+#define BCHP_QUEUE_35_DATA_DFAP_REG_END                    0x0120523c
+#define BCHP_QUEUE_36_DATA_DFAP_REG_START                  0x01205240
+#define BCHP_QUEUE_36_DATA_DFAP_REG_END                    0x0120524c
+#define BCHP_QUEUE_37_DATA_DFAP_REG_START                  0x01205250
+#define BCHP_QUEUE_37_DATA_DFAP_REG_END                    0x0120525c
+#define BCHP_QUEUE_38_DATA_DFAP_REG_START                  0x01205260
+#define BCHP_QUEUE_38_DATA_DFAP_REG_END                    0x0120526c
+#define BCHP_QUEUE_39_DATA_DFAP_REG_START                  0x01205270
+#define BCHP_QUEUE_39_DATA_DFAP_REG_END                    0x0120527c
+#define BCHP_QUEUE_40_DATA_DFAP_REG_START                  0x01205280
+#define BCHP_QUEUE_40_DATA_DFAP_REG_END                    0x0120528c
+#define BCHP_QUEUE_41_DATA_DFAP_REG_START                  0x01205290
+#define BCHP_QUEUE_41_DATA_DFAP_REG_END                    0x0120529c
+#define BCHP_QUEUE_42_DATA_DFAP_REG_START                  0x012052a0
+#define BCHP_QUEUE_42_DATA_DFAP_REG_END                    0x012052ac
+#define BCHP_QUEUE_43_DATA_DFAP_REG_START                  0x012052b0
+#define BCHP_QUEUE_43_DATA_DFAP_REG_END                    0x012052bc
+#define BCHP_QUEUE_44_DATA_DFAP_REG_START                  0x012052c0
+#define BCHP_QUEUE_44_DATA_DFAP_REG_END                    0x012052cc
+#define BCHP_QUEUE_45_DATA_DFAP_REG_START                  0x012052d0
+#define BCHP_QUEUE_45_DATA_DFAP_REG_END                    0x012052dc
+#define BCHP_QUEUE_46_DATA_DFAP_REG_START                  0x012052e0
+#define BCHP_QUEUE_46_DATA_DFAP_REG_END                    0x012052ec
+#define BCHP_QUEUE_47_DATA_DFAP_REG_START                  0x012052f0
+#define BCHP_QUEUE_47_DATA_DFAP_REG_END                    0x012052fc
+#define BCHP_QUEUE_48_DATA_DFAP_REG_START                  0x01205300
+#define BCHP_QUEUE_48_DATA_DFAP_REG_END                    0x0120530c
+#define BCHP_QUEUE_49_DATA_DFAP_REG_START                  0x01205310
+#define BCHP_QUEUE_49_DATA_DFAP_REG_END                    0x0120531c
+#define BCHP_QUEUE_50_DATA_DFAP_REG_START                  0x01205320
+#define BCHP_QUEUE_50_DATA_DFAP_REG_END                    0x0120532c
+#define BCHP_QUEUE_51_DATA_DFAP_REG_START                  0x01205330
+#define BCHP_QUEUE_51_DATA_DFAP_REG_END                    0x0120533c
+#define BCHP_QUEUE_52_DATA_DFAP_REG_START                  0x01205340
+#define BCHP_QUEUE_52_DATA_DFAP_REG_END                    0x0120534c
+#define BCHP_QUEUE_53_DATA_DFAP_REG_START                  0x01205350
+#define BCHP_QUEUE_53_DATA_DFAP_REG_END                    0x0120535c
+#define BCHP_QUEUE_54_DATA_DFAP_REG_START                  0x01205360
+#define BCHP_QUEUE_54_DATA_DFAP_REG_END                    0x0120536c
+#define BCHP_QUEUE_55_DATA_DFAP_REG_START                  0x01205370
+#define BCHP_QUEUE_55_DATA_DFAP_REG_END                    0x0120537c
+#define BCHP_QUEUE_56_DATA_DFAP_REG_START                  0x01205380
+#define BCHP_QUEUE_56_DATA_DFAP_REG_END                    0x0120538c
+#define BCHP_QUEUE_57_DATA_DFAP_REG_START                  0x01205390
+#define BCHP_QUEUE_57_DATA_DFAP_REG_END                    0x0120539c
+#define BCHP_QUEUE_58_DATA_DFAP_REG_START                  0x012053a0
+#define BCHP_QUEUE_58_DATA_DFAP_REG_END                    0x012053ac
+#define BCHP_QUEUE_59_DATA_DFAP_REG_START                  0x012053b0
+#define BCHP_QUEUE_59_DATA_DFAP_REG_END                    0x012053bc
+#define BCHP_QUEUE_60_DATA_DFAP_REG_START                  0x012053c0
+#define BCHP_QUEUE_60_DATA_DFAP_REG_END                    0x012053cc
+#define BCHP_QUEUE_61_DATA_DFAP_REG_START                  0x012053d0
+#define BCHP_QUEUE_61_DATA_DFAP_REG_END                    0x012053dc
+#define BCHP_QUEUE_62_DATA_DFAP_REG_START                  0x012053e0
+#define BCHP_QUEUE_62_DATA_DFAP_REG_END                    0x012053ec
+#define BCHP_QUEUE_63_DATA_DFAP_REG_START                  0x012053f0
+#define BCHP_QUEUE_63_DATA_DFAP_REG_END                    0x012053fc
+#define BCHP_OL_DQM_DFAP_REG_START                         0x01206c00
+#define BCHP_OL_DQM_DFAP_REG_END                           0x01206c5c
+#define BCHP_OL_QUEUE_STATUS_DFAP_REG_START                0x01207400
+#define BCHP_OL_QUEUE_STATUS_DFAP_REG_END                  0x0120747c
+#define BCHP_OL_QUEUE_0_DEBUG_DFAP_REG_START               0x01207c00
+#define BCHP_OL_QUEUE_0_DEBUG_DFAP_REG_END                 0x01207c04
+#define BCHP_OL_QUEUE_1_DEBUG_DFAP_REG_START               0x01207c08
+#define BCHP_OL_QUEUE_1_DEBUG_DFAP_REG_END                 0x01207c0c
+#define BCHP_OL_QUEUE_2_DEBUG_DFAP_REG_START               0x01207c10
+#define BCHP_OL_QUEUE_2_DEBUG_DFAP_REG_END                 0x01207c14
+#define BCHP_OL_QUEUE_3_DEBUG_DFAP_REG_START               0x01207c18
+#define BCHP_OL_QUEUE_3_DEBUG_DFAP_REG_END                 0x01207c1c
+#define BCHP_OL_QUEUE_4_DEBUG_DFAP_REG_START               0x01207c20
+#define BCHP_OL_QUEUE_4_DEBUG_DFAP_REG_END                 0x01207c24
+#define BCHP_OL_QUEUE_5_DEBUG_DFAP_REG_START               0x01207c28
+#define BCHP_OL_QUEUE_5_DEBUG_DFAP_REG_END                 0x01207c2c
+#define BCHP_OL_QUEUE_6_DEBUG_DFAP_REG_START               0x01207c30
+#define BCHP_OL_QUEUE_6_DEBUG_DFAP_REG_END                 0x01207c34
+#define BCHP_OL_QUEUE_7_DEBUG_DFAP_REG_START               0x01207c38
+#define BCHP_OL_QUEUE_7_DEBUG_DFAP_REG_END                 0x01207c3c
+#define BCHP_OL_QUEUE_8_DEBUG_DFAP_REG_START               0x01207c40
+#define BCHP_OL_QUEUE_8_DEBUG_DFAP_REG_END                 0x01207c44
+#define BCHP_OL_QUEUE_9_DEBUG_DFAP_REG_START               0x01207c48
+#define BCHP_OL_QUEUE_9_DEBUG_DFAP_REG_END                 0x01207c4c
+#define BCHP_OL_QUEUE_10_DEBUG_DFAP_REG_START              0x01207c50
+#define BCHP_OL_QUEUE_10_DEBUG_DFAP_REG_END                0x01207c54
+#define BCHP_OL_QUEUE_11_DEBUG_DFAP_REG_START              0x01207c58
+#define BCHP_OL_QUEUE_11_DEBUG_DFAP_REG_END                0x01207c5c
+#define BCHP_OL_QUEUE_12_DEBUG_DFAP_REG_START              0x01207c60
+#define BCHP_OL_QUEUE_12_DEBUG_DFAP_REG_END                0x01207c64
+#define BCHP_OL_QUEUE_13_DEBUG_DFAP_REG_START              0x01207c68
+#define BCHP_OL_QUEUE_13_DEBUG_DFAP_REG_END                0x01207c6c
+#define BCHP_OL_QUEUE_14_DEBUG_DFAP_REG_START              0x01207c70
+#define BCHP_OL_QUEUE_14_DEBUG_DFAP_REG_END                0x01207c74
+#define BCHP_OL_QUEUE_15_DEBUG_DFAP_REG_START              0x01207c78
+#define BCHP_OL_QUEUE_15_DEBUG_DFAP_REG_END                0x01207c7c
+#define BCHP_OL_QUEUE_16_DEBUG_DFAP_REG_START              0x01207c80
+#define BCHP_OL_QUEUE_16_DEBUG_DFAP_REG_END                0x01207c84
+#define BCHP_OL_QUEUE_17_DEBUG_DFAP_REG_START              0x01207c88
+#define BCHP_OL_QUEUE_17_DEBUG_DFAP_REG_END                0x01207c8c
+#define BCHP_OL_QUEUE_18_DEBUG_DFAP_REG_START              0x01207c90
+#define BCHP_OL_QUEUE_18_DEBUG_DFAP_REG_END                0x01207c94
+#define BCHP_OL_QUEUE_19_DEBUG_DFAP_REG_START              0x01207c98
+#define BCHP_OL_QUEUE_19_DEBUG_DFAP_REG_END                0x01207c9c
+#define BCHP_OL_QUEUE_20_DEBUG_DFAP_REG_START              0x01207ca0
+#define BCHP_OL_QUEUE_20_DEBUG_DFAP_REG_END                0x01207ca4
+#define BCHP_OL_QUEUE_21_DEBUG_DFAP_REG_START              0x01207ca8
+#define BCHP_OL_QUEUE_21_DEBUG_DFAP_REG_END                0x01207cac
+#define BCHP_OL_QUEUE_22_DEBUG_DFAP_REG_START              0x01207cb0
+#define BCHP_OL_QUEUE_22_DEBUG_DFAP_REG_END                0x01207cb4
+#define BCHP_OL_QUEUE_23_DEBUG_DFAP_REG_START              0x01207cb8
+#define BCHP_OL_QUEUE_23_DEBUG_DFAP_REG_END                0x01207cbc
+#define BCHP_OL_QUEUE_24_DEBUG_DFAP_REG_START              0x01207cc0
+#define BCHP_OL_QUEUE_24_DEBUG_DFAP_REG_END                0x01207cc4
+#define BCHP_OL_QUEUE_25_DEBUG_DFAP_REG_START              0x01207cc8
+#define BCHP_OL_QUEUE_25_DEBUG_DFAP_REG_END                0x01207ccc
+#define BCHP_OL_QUEUE_26_DEBUG_DFAP_REG_START              0x01207cd0
+#define BCHP_OL_QUEUE_26_DEBUG_DFAP_REG_END                0x01207cd4
+#define BCHP_OL_QUEUE_27_DEBUG_DFAP_REG_START              0x01207cd8
+#define BCHP_OL_QUEUE_27_DEBUG_DFAP_REG_END                0x01207cdc
+#define BCHP_OL_QUEUE_28_DEBUG_DFAP_REG_START              0x01207ce0
+#define BCHP_OL_QUEUE_28_DEBUG_DFAP_REG_END                0x01207ce4
+#define BCHP_OL_QUEUE_29_DEBUG_DFAP_REG_START              0x01207ce8
+#define BCHP_OL_QUEUE_29_DEBUG_DFAP_REG_END                0x01207cec
+#define BCHP_OL_QUEUE_30_DEBUG_DFAP_REG_START              0x01207cf0
+#define BCHP_OL_QUEUE_30_DEBUG_DFAP_REG_END                0x01207cf4
+#define BCHP_OL_QUEUE_31_DEBUG_DFAP_REG_START              0x01207cf8
+#define BCHP_OL_QUEUE_31_DEBUG_DFAP_REG_END                0x01207cfc
+#define BCHP_OL_QUEUE_0_CNTRL_DFAP_REG_START               0x01208000
+#define BCHP_OL_QUEUE_0_CNTRL_DFAP_REG_END                 0x0120801c
+#define BCHP_OL_QUEUE_1_CNTRL_DFAP_REG_START               0x01208020
+#define BCHP_OL_QUEUE_1_CNTRL_DFAP_REG_END                 0x0120803c
+#define BCHP_OL_QUEUE_2_CNTRL_DFAP_REG_START               0x01208040
+#define BCHP_OL_QUEUE_2_CNTRL_DFAP_REG_END                 0x0120805c
+#define BCHP_OL_QUEUE_3_CNTRL_DFAP_REG_START               0x01208060
+#define BCHP_OL_QUEUE_3_CNTRL_DFAP_REG_END                 0x0120807c
+#define BCHP_OL_QUEUE_4_CNTRL_DFAP_REG_START               0x01208080
+#define BCHP_OL_QUEUE_4_CNTRL_DFAP_REG_END                 0x0120809c
+#define BCHP_OL_QUEUE_5_CNTRL_DFAP_REG_START               0x012080a0
+#define BCHP_OL_QUEUE_5_CNTRL_DFAP_REG_END                 0x012080bc
+#define BCHP_OL_QUEUE_6_CNTRL_DFAP_REG_START               0x012080c0
+#define BCHP_OL_QUEUE_6_CNTRL_DFAP_REG_END                 0x012080dc
+#define BCHP_OL_QUEUE_7_CNTRL_DFAP_REG_START               0x012080e0
+#define BCHP_OL_QUEUE_7_CNTRL_DFAP_REG_END                 0x012080fc
+#define BCHP_OL_QUEUE_8_CNTRL_DFAP_REG_START               0x01208100
+#define BCHP_OL_QUEUE_8_CNTRL_DFAP_REG_END                 0x0120811c
+#define BCHP_OL_QUEUE_9_CNTRL_DFAP_REG_START               0x01208120
+#define BCHP_OL_QUEUE_9_CNTRL_DFAP_REG_END                 0x0120813c
+#define BCHP_OL_QUEUE_10_CNTRL_DFAP_REG_START              0x01208140
+#define BCHP_OL_QUEUE_10_CNTRL_DFAP_REG_END                0x0120815c
+#define BCHP_OL_QUEUE_11_CNTRL_DFAP_REG_START              0x01208160
+#define BCHP_OL_QUEUE_11_CNTRL_DFAP_REG_END                0x0120817c
+#define BCHP_OL_QUEUE_12_CNTRL_DFAP_REG_START              0x01208180
+#define BCHP_OL_QUEUE_12_CNTRL_DFAP_REG_END                0x0120819c
+#define BCHP_OL_QUEUE_13_CNTRL_DFAP_REG_START              0x012081a0
+#define BCHP_OL_QUEUE_13_CNTRL_DFAP_REG_END                0x012081bc
+#define BCHP_OL_QUEUE_14_CNTRL_DFAP_REG_START              0x012081c0
+#define BCHP_OL_QUEUE_14_CNTRL_DFAP_REG_END                0x012081dc
+#define BCHP_OL_QUEUE_15_CNTRL_DFAP_REG_START              0x012081e0
+#define BCHP_OL_QUEUE_15_CNTRL_DFAP_REG_END                0x012081fc
+#define BCHP_OL_QUEUE_16_CNTRL_DFAP_REG_START              0x01208200
+#define BCHP_OL_QUEUE_16_CNTRL_DFAP_REG_END                0x0120821c
+#define BCHP_OL_QUEUE_17_CNTRL_DFAP_REG_START              0x01208220
+#define BCHP_OL_QUEUE_17_CNTRL_DFAP_REG_END                0x0120823c
+#define BCHP_OL_QUEUE_18_CNTRL_DFAP_REG_START              0x01208240
+#define BCHP_OL_QUEUE_18_CNTRL_DFAP_REG_END                0x0120825c
+#define BCHP_OL_QUEUE_19_CNTRL_DFAP_REG_START              0x01208260
+#define BCHP_OL_QUEUE_19_CNTRL_DFAP_REG_END                0x0120827c
+#define BCHP_OL_QUEUE_20_CNTRL_DFAP_REG_START              0x01208280
+#define BCHP_OL_QUEUE_20_CNTRL_DFAP_REG_END                0x0120829c
+#define BCHP_OL_QUEUE_21_CNTRL_DFAP_REG_START              0x012082a0
+#define BCHP_OL_QUEUE_21_CNTRL_DFAP_REG_END                0x012082bc
+#define BCHP_OL_QUEUE_22_CNTRL_DFAP_REG_START              0x012082c0
+#define BCHP_OL_QUEUE_22_CNTRL_DFAP_REG_END                0x012082dc
+#define BCHP_OL_QUEUE_23_CNTRL_DFAP_REG_START              0x012082e0
+#define BCHP_OL_QUEUE_23_CNTRL_DFAP_REG_END                0x012082fc
+#define BCHP_OL_QUEUE_24_CNTRL_DFAP_REG_START              0x01208300
+#define BCHP_OL_QUEUE_24_CNTRL_DFAP_REG_END                0x0120831c
+#define BCHP_OL_QUEUE_25_CNTRL_DFAP_REG_START              0x01208320
+#define BCHP_OL_QUEUE_25_CNTRL_DFAP_REG_END                0x0120833c
+#define BCHP_OL_QUEUE_26_CNTRL_DFAP_REG_START              0x01208340
+#define BCHP_OL_QUEUE_26_CNTRL_DFAP_REG_END                0x0120835c
+#define BCHP_OL_QUEUE_27_CNTRL_DFAP_REG_START              0x01208360
+#define BCHP_OL_QUEUE_27_CNTRL_DFAP_REG_END                0x0120837c
+#define BCHP_OL_QUEUE_28_CNTRL_DFAP_REG_START              0x01208380
+#define BCHP_OL_QUEUE_28_CNTRL_DFAP_REG_END                0x0120839c
+#define BCHP_OL_QUEUE_29_CNTRL_DFAP_REG_START              0x012083a0
+#define BCHP_OL_QUEUE_29_CNTRL_DFAP_REG_END                0x012083bc
+#define BCHP_OL_QUEUE_30_CNTRL_DFAP_REG_START              0x012083c0
+#define BCHP_OL_QUEUE_30_CNTRL_DFAP_REG_END                0x012083dc
+#define BCHP_OL_QUEUE_31_CNTRL_DFAP_REG_START              0x012083e0
+#define BCHP_OL_QUEUE_31_CNTRL_DFAP_REG_END                0x012083fc
+#define BCHP_OL_QUEUE_0_DATA_DFAP_REG_START                0x01209000
+#define BCHP_OL_QUEUE_0_DATA_DFAP_REG_END                  0x0120901c
+#define BCHP_OL_QUEUE_1_DATA_DFAP_REG_START                0x01209020
+#define BCHP_OL_QUEUE_1_DATA_DFAP_REG_END                  0x0120903c
+#define BCHP_OL_QUEUE_2_DATA_DFAP_REG_START                0x01209040
+#define BCHP_OL_QUEUE_2_DATA_DFAP_REG_END                  0x0120905c
+#define BCHP_OL_QUEUE_3_DATA_DFAP_REG_START                0x01209060
+#define BCHP_OL_QUEUE_3_DATA_DFAP_REG_END                  0x0120907c
+#define BCHP_OL_QUEUE_4_DATA_DFAP_REG_START                0x01209080
+#define BCHP_OL_QUEUE_4_DATA_DFAP_REG_END                  0x0120909c
+#define BCHP_OL_QUEUE_5_DATA_DFAP_REG_START                0x012090a0
+#define BCHP_OL_QUEUE_5_DATA_DFAP_REG_END                  0x012090bc
+#define BCHP_OL_QUEUE_6_DATA_DFAP_REG_START                0x012090c0
+#define BCHP_OL_QUEUE_6_DATA_DFAP_REG_END                  0x012090dc
+#define BCHP_OL_QUEUE_7_DATA_DFAP_REG_START                0x012090e0
+#define BCHP_OL_QUEUE_7_DATA_DFAP_REG_END                  0x012090fc
+#define BCHP_OL_QUEUE_8_DATA_DFAP_REG_START                0x01209100
+#define BCHP_OL_QUEUE_8_DATA_DFAP_REG_END                  0x0120911c
+#define BCHP_OL_QUEUE_9_DATA_DFAP_REG_START                0x01209120
+#define BCHP_OL_QUEUE_9_DATA_DFAP_REG_END                  0x0120913c
+#define BCHP_OL_QUEUE_10_DATA_DFAP_REG_START               0x01209140
+#define BCHP_OL_QUEUE_10_DATA_DFAP_REG_END                 0x0120915c
+#define BCHP_OL_QUEUE_11_DATA_DFAP_REG_START               0x01209160
+#define BCHP_OL_QUEUE_11_DATA_DFAP_REG_END                 0x0120917c
+#define BCHP_OL_QUEUE_12_DATA_DFAP_REG_START               0x01209180
+#define BCHP_OL_QUEUE_12_DATA_DFAP_REG_END                 0x0120919c
+#define BCHP_OL_QUEUE_13_DATA_DFAP_REG_START               0x012091a0
+#define BCHP_OL_QUEUE_13_DATA_DFAP_REG_END                 0x012091bc
+#define BCHP_OL_QUEUE_14_DATA_DFAP_REG_START               0x012091c0
+#define BCHP_OL_QUEUE_14_DATA_DFAP_REG_END                 0x012091dc
+#define BCHP_OL_QUEUE_15_DATA_DFAP_REG_START               0x012091e0
+#define BCHP_OL_QUEUE_15_DATA_DFAP_REG_END                 0x012091fc
+#define BCHP_OL_QUEUE_16_DATA_DFAP_REG_START               0x01209200
+#define BCHP_OL_QUEUE_16_DATA_DFAP_REG_END                 0x0120921c
+#define BCHP_OL_QUEUE_17_DATA_DFAP_REG_START               0x01209220
+#define BCHP_OL_QUEUE_17_DATA_DFAP_REG_END                 0x0120923c
+#define BCHP_OL_QUEUE_18_DATA_DFAP_REG_START               0x01209240
+#define BCHP_OL_QUEUE_18_DATA_DFAP_REG_END                 0x0120925c
+#define BCHP_OL_QUEUE_19_DATA_DFAP_REG_START               0x01209260
+#define BCHP_OL_QUEUE_19_DATA_DFAP_REG_END                 0x0120927c
+#define BCHP_OL_QUEUE_20_DATA_DFAP_REG_START               0x01209280
+#define BCHP_OL_QUEUE_20_DATA_DFAP_REG_END                 0x0120929c
+#define BCHP_OL_QUEUE_21_DATA_DFAP_REG_START               0x012092a0
+#define BCHP_OL_QUEUE_21_DATA_DFAP_REG_END                 0x012092bc
+#define BCHP_OL_QUEUE_22_DATA_DFAP_REG_START               0x012092c0
+#define BCHP_OL_QUEUE_22_DATA_DFAP_REG_END                 0x012092dc
+#define BCHP_OL_QUEUE_23_DATA_DFAP_REG_START               0x012092e0
+#define BCHP_OL_QUEUE_23_DATA_DFAP_REG_END                 0x012092fc
+#define BCHP_OL_QUEUE_24_DATA_DFAP_REG_START               0x01209300
+#define BCHP_OL_QUEUE_24_DATA_DFAP_REG_END                 0x0120931c
+#define BCHP_OL_QUEUE_25_DATA_DFAP_REG_START               0x01209320
+#define BCHP_OL_QUEUE_25_DATA_DFAP_REG_END                 0x0120933c
+#define BCHP_OL_QUEUE_26_DATA_DFAP_REG_START               0x01209340
+#define BCHP_OL_QUEUE_26_DATA_DFAP_REG_END                 0x0120935c
+#define BCHP_OL_QUEUE_27_DATA_DFAP_REG_START               0x01209360
+#define BCHP_OL_QUEUE_27_DATA_DFAP_REG_END                 0x0120937c
+#define BCHP_OL_QUEUE_28_DATA_DFAP_REG_START               0x01209380
+#define BCHP_OL_QUEUE_28_DATA_DFAP_REG_END                 0x0120939c
+#define BCHP_OL_QUEUE_29_DATA_DFAP_REG_START               0x012093a0
+#define BCHP_OL_QUEUE_29_DATA_DFAP_REG_END                 0x012093bc
+#define BCHP_OL_QUEUE_30_DATA_DFAP_REG_START               0x012093c0
+#define BCHP_OL_QUEUE_30_DATA_DFAP_REG_END                 0x012093dc
+#define BCHP_OL_QUEUE_31_DATA_DFAP_REG_START               0x012093e0
+#define BCHP_OL_QUEUE_31_DATA_DFAP_REG_END                 0x012093fc
+#define BCHP_OL_QUEUE_MIB_DFAP_REG_START                   0x0120a000
+#define BCHP_OL_QUEUE_MIB_DFAP_REG_END                     0x0120a17c
+#define BCHP_QueueSharedMem_DFAP_REG_START                 0x01240000
+#define BCHP_QueueSharedMem_DFAP_REG_END                   0x0124bffc
+#define BCHP_Memory_DFAP_REG_START                         0x01280000
+#define BCHP_Memory_DFAP_REG_END                           0x01287ffc
+#define BCHP_DPE_BASIC_DFAP_REG_START                      0x01300000
+#define BCHP_DPE_BASIC_DFAP_REG_END                        0x01300094
+#define BCHP_DPE_MPEG_DFAP_REG_START                       0x01300200
+#define BCHP_DPE_MPEG_DFAP_REG_END                         0x0130034c
+#define BCHP_DPE_HW_DFAP_REG_START                         0x01300400
+#define BCHP_DPE_HW_DFAP_REG_END                           0x0130169c
+#define BCHP_DPE_EXT_DROP_DFAP_REG_START                   0x01305000
+#define BCHP_DPE_EXT_DROP_DFAP_REG_END                     0x01305200
+#define BCHP_NATC_REG_DFAP_REG_START                       0x01306000
+#define BCHP_NATC_REG_DFAP_REG_END                         0x01306164
+#define BCHP_NATC_SMEM_DFAP_REG_START                      0x01307000
+#define BCHP_NATC_SMEM_DFAP_REG_END                        0x01307ffc
+#define BCHP_NATC_MEM_DFAP_REG_START                       0x01308000
+#define BCHP_NATC_MEM_DFAP_REG_END                         0x0130fffc
+#define BCHP_FAP_PT_MEM_DFAP_REG_START                     0x01310000
+#define BCHP_FAP_PT_MEM_DFAP_REG_END                       0x01317ffc
+#define BCHP_FPM_PT_CTRL_DFAP_REG_START                    0x01320000
+#define BCHP_FPM_PT_CTRL_DFAP_REG_END                      0x01320154
+#define BCHP_FPM_PT_POOL_DFAP_REG_START                    0x01320200
+#define BCHP_FPM_PT_POOL_DFAP_REG_END                      0x01320224
+#define BCHP_FPM_PT_SEARCH_DFAP_REG_START                  0x01324000
+#define BCHP_FPM_PT_SEARCH_DFAP_REG_END                    0x013248b8
+#define BCHP_FPM_PT_MULTI_DFAP_REG_START                   0x01330000
+#define BCHP_FPM_PT_MULTI_DFAP_REG_END                     0x0133fff8
+#define BCHP_FFE_N_0_DFAP_REG_START                        0x01380000
+#define BCHP_FFE_N_0_DFAP_REG_END                          0x013803fc
+#define BCHP_FFE_P_0_DFAP_REG_START                        0x01381000
+#define BCHP_FFE_P_0_DFAP_REG_END                          0x013817fc
+#define BCHP_FFE_I_0_DFAP_REG_START                        0x01384000
+#define BCHP_FFE_I_0_DFAP_REG_END                          0x01387ffc
+#define BCHP_FFE_N_1_DFAP_REG_START                        0x01390000
+#define BCHP_FFE_N_1_DFAP_REG_END                          0x013903fc
+#define BCHP_FFE_P_1_DFAP_REG_START                        0x01391000
+#define BCHP_FFE_P_1_DFAP_REG_END                          0x013917fc
+#define BCHP_FFE_I_1_DFAP_REG_START                        0x01394000
+#define BCHP_FFE_I_1_DFAP_REG_END                          0x01397ffc
+#define BCHP_FFE_N_2_DFAP_REG_START                        0x013a0000
+#define BCHP_FFE_N_2_DFAP_REG_END                          0x013a03fc
+#define BCHP_FFE_P_2_DFAP_REG_START                        0x013a1000
+#define BCHP_FFE_P_2_DFAP_REG_END                          0x013a17fc
+#define BCHP_FFE_I_2_DFAP_REG_START                        0x013a4000
+#define BCHP_FFE_I_2_DFAP_REG_END                          0x013a7ffc
+#define BCHP_FFE_N_3_DFAP_REG_START                        0x013b0000
+#define BCHP_FFE_N_3_DFAP_REG_END                          0x013b03fc
+#define BCHP_FFE_P_3_DFAP_REG_START                        0x013b1000
+#define BCHP_FFE_P_3_DFAP_REG_END                          0x013b17fc
+#define BCHP_FFE_I_3_DFAP_REG_START                        0x013b4000
+#define BCHP_FFE_I_3_DFAP_REG_END                          0x013b7ffc
+#define BCHP_FFE_N_4_DFAP_REG_START                        0x013c0000
+#define BCHP_FFE_N_4_DFAP_REG_END                          0x013c03fc
+#define BCHP_FFE_P_4_DFAP_REG_START                        0x013c1000
+#define BCHP_FFE_P_4_DFAP_REG_END                          0x013c17fc
+#define BCHP_FFE_I_4_DFAP_REG_START                        0x013c4000
+#define BCHP_FFE_I_4_DFAP_REG_END                          0x013c7ffc
+#define BCHP_FFE_N_5_DFAP_REG_START                        0x013d0000
+#define BCHP_FFE_N_5_DFAP_REG_END                          0x013d03fc
+#define BCHP_FFE_P_5_DFAP_REG_START                        0x013d1000
+#define BCHP_FFE_P_5_DFAP_REG_END                          0x013d17fc
+#define BCHP_FFE_I_5_DFAP_REG_START                        0x013d4000
+#define BCHP_FFE_I_5_DFAP_REG_END                          0x013d7ffc
+#define BCHP_FFE_N_6_DFAP_REG_START                        0x013e0000
+#define BCHP_FFE_N_6_DFAP_REG_END                          0x013e03fc
+#define BCHP_FFE_P_6_DFAP_REG_START                        0x013e1000
+#define BCHP_FFE_P_6_DFAP_REG_END                          0x013e17fc
+#define BCHP_FFE_I_6_DFAP_REG_START                        0x013e4000
+#define BCHP_FFE_I_6_DFAP_REG_END                          0x013e7ffc
+#define BCHP_FFE_N_7_DFAP_REG_START                        0x013f0000
+#define BCHP_FFE_N_7_DFAP_REG_END                          0x013f03fc
+#define BCHP_FFE_P_7_DFAP_REG_START                        0x013f1000
+#define BCHP_FFE_P_7_DFAP_REG_END                          0x013f17fc
+#define BCHP_FFE_I_7_DFAP_REG_START                        0x013f4000
+#define BCHP_FFE_I_7_DFAP_REG_END                          0x013f7ffc
+#define BCHP_DOWNSTREAM_REG_START                          0x01400000
+#define BCHP_DOWNSTREAM_REG_END                            0x014073e0
+#define BCHP_D31DSMAC_A_REG_START                          0x01600000
+#define BCHP_D31DSMAC_A_REG_END                            0x016073e0
+#define BCHP_D31DSMAC_B_REG_START                          0x01800000
+#define BCHP_D31DSMAC_B_REG_END                            0x018073e0
+#define BCHP_TCOFDM_0_REG_START                            0x01a00000
+#define BCHP_TCOFDM_0_REG_END                              0x01a00874
+#define BCHP_TCOFDM_1_REG_START                            0x01a10000
+#define BCHP_TCOFDM_1_REG_END                              0x01a10874
+#define BCHP_TCDTR_0_REG_START                             0x01a20000
+#define BCHP_TCDTR_0_REG_END                               0x01a200fc
+#define BCHP_APM_COMMON_APM_REG_START                      0x01c00000
+#define BCHP_APM_COMMON_APM_REG_END                        0x01c0005c
+#define BCHP_APM_ADC_BIST_APM_REG_START                    0x01c00100
+#define BCHP_APM_ADC_BIST_APM_REG_END                      0x01c001a0
+#define BCHP_APM_ACP_CMN_APM_REG_START                     0x01c00400
+#define BCHP_APM_ACP_CMN_APM_REG_END                       0x01c00424
+#define BCHP_APM_ACP_ChA_APM_REG_START                     0x01c00500
+#define BCHP_APM_ACP_ChA_APM_REG_END                       0x01c0056c
+#define BCHP_APM_ACP_ChB_APM_REG_START                     0x01c00600
+#define BCHP_APM_ACP_ChB_APM_REG_END                       0x01c0066c
+#define BCHP_APM_HVG_CMN_APM_REG_START                     0x01c00800
+#define BCHP_APM_HVG_CMN_APM_REG_END                       0x01c00850
+#define BCHP_APM_HVG_ChA_APM_REG_START                     0x01c00900
+#define BCHP_APM_HVG_ChA_APM_REG_END                       0x01c00950
+#define BCHP_APM_HVG_ChB_APM_REG_START                     0x01c00a00
+#define BCHP_APM_HVG_ChB_APM_REG_END                       0x01c00a50
+#define BCHP_APM_PCM_APM_REG_START                         0x01c00c00
+#define BCHP_APM_PCM_APM_REG_END                           0x01c00c7c
+#define BCHP_APM_DMA_CTRL_APM_REG_START                    0x01c01800
+#define BCHP_APM_DMA_CTRL_APM_REG_END                      0x01c01844
+#define BCHP_APM_DMA_CH0_APM_REG_START                     0x01c01a00
+#define BCHP_APM_DMA_CH0_APM_REG_END                       0x01c01a0c
+#define BCHP_APM_DMA_CH1_APM_REG_START                     0x01c01a10
+#define BCHP_APM_DMA_CH1_APM_REG_END                       0x01c01a1c
+#define BCHP_APM_DMA_CH2_APM_REG_START                     0x01c01a20
+#define BCHP_APM_DMA_CH2_APM_REG_END                       0x01c01a2c
+#define BCHP_APM_DMA_CH3_APM_REG_START                     0x01c01a30
+#define BCHP_APM_DMA_CH3_APM_REG_END                       0x01c01a3c
+#define BCHP_APM_DMA_CH4_APM_REG_START                     0x01c01a40
+#define BCHP_APM_DMA_CH4_APM_REG_END                       0x01c01a4c
+#define BCHP_APM_DMA_CH5_APM_REG_START                     0x01c01a50
+#define BCHP_APM_DMA_CH5_APM_REG_END                       0x01c01a5c
+#define BCHP_APM_DMA_CH0_STATE_APM_REG_START               0x01c01c00
+#define BCHP_APM_DMA_CH0_STATE_APM_REG_END                 0x01c01c0c
+#define BCHP_APM_DMA_CH1_STATE_APM_REG_START               0x01c01c10
+#define BCHP_APM_DMA_CH1_STATE_APM_REG_END                 0x01c01c1c
+#define BCHP_APM_DMA_CH2_STATE_APM_REG_START               0x01c01c20
+#define BCHP_APM_DMA_CH2_STATE_APM_REG_END                 0x01c01c2c
+#define BCHP_APM_DMA_CH3_STATE_APM_REG_START               0x01c01c30
+#define BCHP_APM_DMA_CH3_STATE_APM_REG_END                 0x01c01c3c
+#define BCHP_APM_DMA_CH4_STATE_APM_REG_START               0x01c01c40
+#define BCHP_APM_DMA_CH4_STATE_APM_REG_END                 0x01c01c4c
+#define BCHP_APM_DMA_CH5_STATE_APM_REG_START               0x01c01c50
+#define BCHP_APM_DMA_CH5_STATE_APM_REG_END                 0x01c01c5c
+#define BCHP_APM_BMU_BMU_DMEM_APM_REG_START                0x01c02000
+#define BCHP_APM_BMU_BMU_DMEM_APM_REG_END                  0x01c023fc
+#define BCHP_APM_BMU_BMU_SMEM_APM_REG_START                0x01c02400
+#define BCHP_APM_BMU_BMU_SMEM_APM_REG_END                  0x01c025fc
+#define BCHP_APM_BMU_BMU_LS_APM_REG_START                  0x01c02800
+#define BCHP_APM_BMU_BMU_LS_APM_REG_END                    0x01c0291c
+#define BCHP_APM_BMU_BMU_CP_APM_REG_START                  0x01c02c00
+#define BCHP_APM_BMU_BMU_CP_APM_REG_END                    0x01c02d0c
+#define BCHP_APM_PICO_IMEM_APM_REG_START                   0x01c10000
+#define BCHP_APM_PICO_IMEM_APM_REG_END                     0x01c127fc
+#define BCHP_LEAP_ROM_REG_START                            0x02000000
+#define BCHP_LEAP_ROM_REG_END                              0x02007ffc
+#define BCHP_LEAP_PROG0_MEM_REG_START                      0x02040000
+#define BCHP_LEAP_PROG0_MEM_REG_END                        0x0204bffc
+#define BCHP_LEAP_CPU_CORE_REGS_REG_START                  0x020a0000
+#define BCHP_LEAP_CPU_CORE_REGS_REG_END                    0x020a00fc
+#define BCHP_LEAP_CPU_AUX_REGS_REG_START                   0x020c0000
+#define BCHP_LEAP_CPU_AUX_REGS_REG_END                     0x020c1058
+#define BCHP_LEAP_HAB_MEM_REG_START                        0x020c8000
+#define BCHP_LEAP_HAB_MEM_REG_END                          0x020c83fc
+#define BCHP_LEAP_UART_REG_START                           0x020c9000
+#define BCHP_LEAP_UART_REG_END                             0x020c9ffc
+#define BCHP_LEAP_WDG_REG_START                            0x020ca000
+#define BCHP_LEAP_WDG_REG_END                              0x020caffc
+#define BCHP_LEAP_CTRL_REG_START                           0x02100000
+#define BCHP_LEAP_CTRL_REG_END                             0x02100348
+#define BCHP_LEAP_L1_REG_START                             0x02100400
+#define BCHP_LEAP_L1_REG_END                               0x0210041c
+#define BCHP_LEAP_L2_REG_START                             0x02100500
+#define BCHP_LEAP_L2_REG_END                               0x02100514
+#define BCHP_LEAP_HOST_L1_REG_START                        0x02100600
+#define BCHP_LEAP_HOST_L1_REG_END                          0x0210061c
+#define BCHP_LEAP_HOST_L2_REG_START                        0x02100700
+#define BCHP_LEAP_HOST_L2_REG_END                          0x0210072c
+#define BCHP_LEAP_CTRL_MISC_REG_START                      0x02100800
+#define BCHP_LEAP_CTRL_MISC_REG_END                        0x0210084c
+#define BCHP_LEAP_HOST2_L1_REG_START                       0x02100900
+#define BCHP_LEAP_HOST2_L1_REG_END                         0x0210091c
+#define BCHP_LEAP_ROM_PATCH_REG_START                      0x02100a00
+#define BCHP_LEAP_ROM_PATCH_REG_END                        0x02100a3c
+#define BCHP_LEAP_CTRL_TIMERS_REG_START                    0x02100c00
+#define BCHP_LEAP_CTRL_TIMERS_REG_END                      0x02100c7c
+#define BCHP_DS_A_MICRO_REG_START                          0x02200000
+#define BCHP_DS_A_MICRO_REG_END                            0x02200020
+#define BCHP_DS_A_TOPS_REG_START                           0x02200100
+#define BCHP_DS_A_TOPS_REG_END                             0x02200148
+#define BCHP_DS_A_TP_REG_START                             0x02200400
+#define BCHP_DS_A_TP_REG_END                               0x02200418
+#define BCHP_OOB_REG_START                                 0x02201000
+#define BCHP_OOB_REG_END                                   0x022011f8
+#define BCHP_DS_A_CHAN_FE_REG_START                        0x02210000
+#define BCHP_DS_A_CHAN_FE_REG_END                          0x0221000c
+#define BCHP_DS_A_CHAN_OB_ACI_REG_START                    0x02210010
+#define BCHP_DS_A_CHAN_OB_ACI_REG_END                      0x02210010
+#define BCHP_DS_A_CHAN_ACI_ANXA_REG_START                  0x02210100
+#define BCHP_DS_A_CHAN_ACI_ANXA_REG_END                    0x02210144
+#define BCHP_DS_A_CHAN_ACI_ANXB_REG_START                  0x02210200
+#define BCHP_DS_A_CHAN_ACI_ANXB_REG_END                    0x02210244
+#define BCHP_DS_A_CHAN_SPECA_ISW_MXR_REG_START             0x02210300
+#define BCHP_DS_A_CHAN_SPECA_ISW_MXR_REG_END               0x02210308
+#define BCHP_DS_A_CHAN_SPECA_ACI_AGF_REG_START             0x02210400
+#define BCHP_DS_A_CHAN_SPECA_ACI_AGF_REG_END               0x02210414
+#define BCHP_DS_A_CHAN_OOB_ISW_MXR_REG_START               0x02210500
+#define BCHP_DS_A_CHAN_OOB_ISW_MXR_REG_END                 0x02210508
+#define BCHP_DS_A_CHAN_OOB_ACI_AGF_REG_START               0x02210600
+#define BCHP_DS_A_CHAN_OOB_ACI_AGF_REG_END                 0x02210614
+#define BCHP_DS_A_CHAN_CPPM_ISW_MXR_REG_START              0x02210700
+#define BCHP_DS_A_CHAN_CPPM_ISW_MXR_REG_END                0x02210708
+#define BCHP_DS_A_CHAN_CPPM_ACI_AGF_REG_START              0x02210800
+#define BCHP_DS_A_CHAN_CPPM_ACI_AGF_REG_END                0x02210814
+#define BCHP_DS_A_00_ISW_MXR_REG_START                     0x02220000
+#define BCHP_DS_A_00_ISW_MXR_REG_END                       0x02220008
+#define BCHP_DS_A_00_ACI_AGF_REG_START                     0x02220200
+#define BCHP_DS_A_00_ACI_AGF_REG_END                       0x0222037c
+#define BCHP_DS_A_00_TRL_REG_START                         0x02220400
+#define BCHP_DS_A_00_TRL_REG_END                           0x022206fc
+#define BCHP_DS_A_00_EQ_REG_START                          0x02220800
+#define BCHP_DS_A_00_EQ_REG_END                            0x02220bbc
+#define BCHP_DS_A_00_FECF_REG_START                        0x02220c00
+#define BCHP_DS_A_00_FECF_REG_END                          0x02220d7c
+#define BCHP_DS_A_00_FECB_REG_START                        0x02220e00
+#define BCHP_DS_A_00_FECB_REG_END                          0x02220ebc
+#define BCHP_DS_A_00_FFT_REG_START                         0x02221000
+#define BCHP_DS_A_00_FFT_REG_END                           0x0222117c
+#define BCHP_DS_A_00_OI_REG_START                          0x02221200
+#define BCHP_DS_A_00_OI_REG_END                            0x0222123c
+#define BCHP_DS_A_00_IRQ_REG_START                         0x02221300
+#define BCHP_DS_A_00_IRQ_REG_END                           0x02221314
+#define BCHP_DS_A_01_ISW_MXR_REG_START                     0x02222000
+#define BCHP_DS_A_01_ISW_MXR_REG_END                       0x02222008
+#define BCHP_DS_A_01_ACI_AGF_REG_START                     0x02222200
+#define BCHP_DS_A_01_ACI_AGF_REG_END                       0x0222237c
+#define BCHP_DS_A_01_TRL_REG_START                         0x02222400
+#define BCHP_DS_A_01_TRL_REG_END                           0x022226fc
+#define BCHP_DS_A_01_EQ_REG_START                          0x02222800
+#define BCHP_DS_A_01_EQ_REG_END                            0x02222bbc
+#define BCHP_DS_A_01_FECF_REG_START                        0x02222c00
+#define BCHP_DS_A_01_FECF_REG_END                          0x02222d7c
+#define BCHP_DS_A_01_FECB_REG_START                        0x02222e00
+#define BCHP_DS_A_01_FECB_REG_END                          0x02222ebc
+#define BCHP_DS_A_01_FFT_REG_START                         0x02223000
+#define BCHP_DS_A_01_FFT_REG_END                           0x0222317c
+#define BCHP_DS_A_01_OI_REG_START                          0x02223200
+#define BCHP_DS_A_01_OI_REG_END                            0x0222323c
+#define BCHP_DS_A_01_IRQ_REG_START                         0x02223300
+#define BCHP_DS_A_01_IRQ_REG_END                           0x02223314
+#define BCHP_DS_A_02_ISW_MXR_REG_START                     0x02224000
+#define BCHP_DS_A_02_ISW_MXR_REG_END                       0x02224008
+#define BCHP_DS_A_02_ACI_AGF_REG_START                     0x02224200
+#define BCHP_DS_A_02_ACI_AGF_REG_END                       0x0222437c
+#define BCHP_DS_A_02_TRL_REG_START                         0x02224400
+#define BCHP_DS_A_02_TRL_REG_END                           0x022246fc
+#define BCHP_DS_A_02_EQ_REG_START                          0x02224800
+#define BCHP_DS_A_02_EQ_REG_END                            0x02224bbc
+#define BCHP_DS_A_02_FECF_REG_START                        0x02224c00
+#define BCHP_DS_A_02_FECF_REG_END                          0x02224d7c
+#define BCHP_DS_A_02_FECB_REG_START                        0x02224e00
+#define BCHP_DS_A_02_FECB_REG_END                          0x02224ebc
+#define BCHP_DS_A_02_FFT_REG_START                         0x02225000
+#define BCHP_DS_A_02_FFT_REG_END                           0x0222517c
+#define BCHP_DS_A_02_OI_REG_START                          0x02225200
+#define BCHP_DS_A_02_OI_REG_END                            0x0222523c
+#define BCHP_DS_A_02_IRQ_REG_START                         0x02225300
+#define BCHP_DS_A_02_IRQ_REG_END                           0x02225314
+#define BCHP_DS_A_03_ISW_MXR_REG_START                     0x02226000
+#define BCHP_DS_A_03_ISW_MXR_REG_END                       0x02226008
+#define BCHP_DS_A_03_ACI_AGF_REG_START                     0x02226200
+#define BCHP_DS_A_03_ACI_AGF_REG_END                       0x0222637c
+#define BCHP_DS_A_03_TRL_REG_START                         0x02226400
+#define BCHP_DS_A_03_TRL_REG_END                           0x022266fc
+#define BCHP_DS_A_03_EQ_REG_START                          0x02226800
+#define BCHP_DS_A_03_EQ_REG_END                            0x02226bbc
+#define BCHP_DS_A_03_FECF_REG_START                        0x02226c00
+#define BCHP_DS_A_03_FECF_REG_END                          0x02226d7c
+#define BCHP_DS_A_03_FECB_REG_START                        0x02226e00
+#define BCHP_DS_A_03_FECB_REG_END                          0x02226ebc
+#define BCHP_DS_A_03_FFT_REG_START                         0x02227000
+#define BCHP_DS_A_03_FFT_REG_END                           0x0222717c
+#define BCHP_DS_A_03_OI_REG_START                          0x02227200
+#define BCHP_DS_A_03_OI_REG_END                            0x0222723c
+#define BCHP_DS_A_03_IRQ_REG_START                         0x02227300
+#define BCHP_DS_A_03_IRQ_REG_END                           0x02227314
+#define BCHP_DS_A_04_ISW_MXR_REG_START                     0x02228000
+#define BCHP_DS_A_04_ISW_MXR_REG_END                       0x02228008
+#define BCHP_DS_A_04_ACI_AGF_REG_START                     0x02228200
+#define BCHP_DS_A_04_ACI_AGF_REG_END                       0x0222837c
+#define BCHP_DS_A_04_TRL_REG_START                         0x02228400
+#define BCHP_DS_A_04_TRL_REG_END                           0x022286fc
+#define BCHP_DS_A_04_EQ_REG_START                          0x02228800
+#define BCHP_DS_A_04_EQ_REG_END                            0x02228bbc
+#define BCHP_DS_A_04_FECF_REG_START                        0x02228c00
+#define BCHP_DS_A_04_FECF_REG_END                          0x02228d7c
+#define BCHP_DS_A_04_FECB_REG_START                        0x02228e00
+#define BCHP_DS_A_04_FECB_REG_END                          0x02228ebc
+#define BCHP_DS_A_04_FFT_REG_START                         0x02229000
+#define BCHP_DS_A_04_FFT_REG_END                           0x0222917c
+#define BCHP_DS_A_04_OI_REG_START                          0x02229200
+#define BCHP_DS_A_04_OI_REG_END                            0x0222923c
+#define BCHP_DS_A_04_IRQ_REG_START                         0x02229300
+#define BCHP_DS_A_04_IRQ_REG_END                           0x02229314
+#define BCHP_DS_A_05_ISW_MXR_REG_START                     0x0222a000
+#define BCHP_DS_A_05_ISW_MXR_REG_END                       0x0222a008
+#define BCHP_DS_A_05_ACI_AGF_REG_START                     0x0222a200
+#define BCHP_DS_A_05_ACI_AGF_REG_END                       0x0222a37c
+#define BCHP_DS_A_05_TRL_REG_START                         0x0222a400
+#define BCHP_DS_A_05_TRL_REG_END                           0x0222a6fc
+#define BCHP_DS_A_05_EQ_REG_START                          0x0222a800
+#define BCHP_DS_A_05_EQ_REG_END                            0x0222abbc
+#define BCHP_DS_A_05_FECF_REG_START                        0x0222ac00
+#define BCHP_DS_A_05_FECF_REG_END                          0x0222ad7c
+#define BCHP_DS_A_05_FECB_REG_START                        0x0222ae00
+#define BCHP_DS_A_05_FECB_REG_END                          0x0222aebc
+#define BCHP_DS_A_05_FFT_REG_START                         0x0222b000
+#define BCHP_DS_A_05_FFT_REG_END                           0x0222b17c
+#define BCHP_DS_A_05_OI_REG_START                          0x0222b200
+#define BCHP_DS_A_05_OI_REG_END                            0x0222b23c
+#define BCHP_DS_A_05_IRQ_REG_START                         0x0222b300
+#define BCHP_DS_A_05_IRQ_REG_END                           0x0222b314
+#define BCHP_DS_A_06_ISW_MXR_REG_START                     0x0222c000
+#define BCHP_DS_A_06_ISW_MXR_REG_END                       0x0222c008
+#define BCHP_DS_A_06_ACI_AGF_REG_START                     0x0222c200
+#define BCHP_DS_A_06_ACI_AGF_REG_END                       0x0222c37c
+#define BCHP_DS_A_06_TRL_REG_START                         0x0222c400
+#define BCHP_DS_A_06_TRL_REG_END                           0x0222c6fc
+#define BCHP_DS_A_06_EQ_REG_START                          0x0222c800
+#define BCHP_DS_A_06_EQ_REG_END                            0x0222cbbc
+#define BCHP_DS_A_06_FECF_REG_START                        0x0222cc00
+#define BCHP_DS_A_06_FECF_REG_END                          0x0222cd7c
+#define BCHP_DS_A_06_FECB_REG_START                        0x0222ce00
+#define BCHP_DS_A_06_FECB_REG_END                          0x0222cebc
+#define BCHP_DS_A_06_FFT_REG_START                         0x0222d000
+#define BCHP_DS_A_06_FFT_REG_END                           0x0222d17c
+#define BCHP_DS_A_06_OI_REG_START                          0x0222d200
+#define BCHP_DS_A_06_OI_REG_END                            0x0222d23c
+#define BCHP_DS_A_06_IRQ_REG_START                         0x0222d300
+#define BCHP_DS_A_06_IRQ_REG_END                           0x0222d314
+#define BCHP_DS_A_07_ISW_MXR_REG_START                     0x0222e000
+#define BCHP_DS_A_07_ISW_MXR_REG_END                       0x0222e008
+#define BCHP_DS_A_07_ACI_AGF_REG_START                     0x0222e200
+#define BCHP_DS_A_07_ACI_AGF_REG_END                       0x0222e37c
+#define BCHP_DS_A_07_TRL_REG_START                         0x0222e400
+#define BCHP_DS_A_07_TRL_REG_END                           0x0222e6fc
+#define BCHP_DS_A_07_EQ_REG_START                          0x0222e800
+#define BCHP_DS_A_07_EQ_REG_END                            0x0222ebbc
+#define BCHP_DS_A_07_FECF_REG_START                        0x0222ec00
+#define BCHP_DS_A_07_FECF_REG_END                          0x0222ed7c
+#define BCHP_DS_A_07_FECB_REG_START                        0x0222ee00
+#define BCHP_DS_A_07_FECB_REG_END                          0x0222eebc
+#define BCHP_DS_A_07_FFT_REG_START                         0x0222f000
+#define BCHP_DS_A_07_FFT_REG_END                           0x0222f17c
+#define BCHP_DS_A_07_OI_REG_START                          0x0222f200
+#define BCHP_DS_A_07_OI_REG_END                            0x0222f23c
+#define BCHP_DS_A_07_IRQ_REG_START                         0x0222f300
+#define BCHP_DS_A_07_IRQ_REG_END                           0x0222f314
+#define BCHP_DS_A_08_ISW_MXR_REG_START                     0x02230000
+#define BCHP_DS_A_08_ISW_MXR_REG_END                       0x02230008
+#define BCHP_DS_A_08_ACI_AGF_REG_START                     0x02230200
+#define BCHP_DS_A_08_ACI_AGF_REG_END                       0x0223037c
+#define BCHP_DS_A_08_TRL_REG_START                         0x02230400
+#define BCHP_DS_A_08_TRL_REG_END                           0x022306fc
+#define BCHP_DS_A_08_EQ_REG_START                          0x02230800
+#define BCHP_DS_A_08_EQ_REG_END                            0x02230bbc
+#define BCHP_DS_A_08_FECF_REG_START                        0x02230c00
+#define BCHP_DS_A_08_FECF_REG_END                          0x02230d7c
+#define BCHP_DS_A_08_FECB_REG_START                        0x02230e00
+#define BCHP_DS_A_08_FECB_REG_END                          0x02230ebc
+#define BCHP_DS_A_08_FFT_REG_START                         0x02231000
+#define BCHP_DS_A_08_FFT_REG_END                           0x0223117c
+#define BCHP_DS_A_08_OI_REG_START                          0x02231200
+#define BCHP_DS_A_08_OI_REG_END                            0x0223123c
+#define BCHP_DS_A_08_IRQ_REG_START                         0x02231300
+#define BCHP_DS_A_08_IRQ_REG_END                           0x02231314
+#define BCHP_DS_A_09_ISW_MXR_REG_START                     0x02232000
+#define BCHP_DS_A_09_ISW_MXR_REG_END                       0x02232008
+#define BCHP_DS_A_09_ACI_AGF_REG_START                     0x02232200
+#define BCHP_DS_A_09_ACI_AGF_REG_END                       0x0223237c
+#define BCHP_DS_A_09_TRL_REG_START                         0x02232400
+#define BCHP_DS_A_09_TRL_REG_END                           0x022326fc
+#define BCHP_DS_A_09_EQ_REG_START                          0x02232800
+#define BCHP_DS_A_09_EQ_REG_END                            0x02232bbc
+#define BCHP_DS_A_09_FECF_REG_START                        0x02232c00
+#define BCHP_DS_A_09_FECF_REG_END                          0x02232d7c
+#define BCHP_DS_A_09_FECB_REG_START                        0x02232e00
+#define BCHP_DS_A_09_FECB_REG_END                          0x02232ebc
+#define BCHP_DS_A_09_FFT_REG_START                         0x02233000
+#define BCHP_DS_A_09_FFT_REG_END                           0x0223317c
+#define BCHP_DS_A_09_OI_REG_START                          0x02233200
+#define BCHP_DS_A_09_OI_REG_END                            0x0223323c
+#define BCHP_DS_A_09_IRQ_REG_START                         0x02233300
+#define BCHP_DS_A_09_IRQ_REG_END                           0x02233314
+#define BCHP_DS_A_10_ISW_MXR_REG_START                     0x02234000
+#define BCHP_DS_A_10_ISW_MXR_REG_END                       0x02234008
+#define BCHP_DS_A_10_ACI_AGF_REG_START                     0x02234200
+#define BCHP_DS_A_10_ACI_AGF_REG_END                       0x0223437c
+#define BCHP_DS_A_10_TRL_REG_START                         0x02234400
+#define BCHP_DS_A_10_TRL_REG_END                           0x022346fc
+#define BCHP_DS_A_10_EQ_REG_START                          0x02234800
+#define BCHP_DS_A_10_EQ_REG_END                            0x02234bbc
+#define BCHP_DS_A_10_FECF_REG_START                        0x02234c00
+#define BCHP_DS_A_10_FECF_REG_END                          0x02234d7c
+#define BCHP_DS_A_10_FECB_REG_START                        0x02234e00
+#define BCHP_DS_A_10_FECB_REG_END                          0x02234ebc
+#define BCHP_DS_A_10_FFT_REG_START                         0x02235000
+#define BCHP_DS_A_10_FFT_REG_END                           0x0223517c
+#define BCHP_DS_A_10_OI_REG_START                          0x02235200
+#define BCHP_DS_A_10_OI_REG_END                            0x0223523c
+#define BCHP_DS_A_10_IRQ_REG_START                         0x02235300
+#define BCHP_DS_A_10_IRQ_REG_END                           0x02235314
+#define BCHP_DS_A_11_ISW_MXR_REG_START                     0x02236000
+#define BCHP_DS_A_11_ISW_MXR_REG_END                       0x02236008
+#define BCHP_DS_A_11_ACI_AGF_REG_START                     0x02236200
+#define BCHP_DS_A_11_ACI_AGF_REG_END                       0x0223637c
+#define BCHP_DS_A_11_TRL_REG_START                         0x02236400
+#define BCHP_DS_A_11_TRL_REG_END                           0x022366fc
+#define BCHP_DS_A_11_EQ_REG_START                          0x02236800
+#define BCHP_DS_A_11_EQ_REG_END                            0x02236bbc
+#define BCHP_DS_A_11_FECF_REG_START                        0x02236c00
+#define BCHP_DS_A_11_FECF_REG_END                          0x02236d7c
+#define BCHP_DS_A_11_FECB_REG_START                        0x02236e00
+#define BCHP_DS_A_11_FECB_REG_END                          0x02236ebc
+#define BCHP_DS_A_11_FFT_REG_START                         0x02237000
+#define BCHP_DS_A_11_FFT_REG_END                           0x0223717c
+#define BCHP_DS_A_11_OI_REG_START                          0x02237200
+#define BCHP_DS_A_11_OI_REG_END                            0x0223723c
+#define BCHP_DS_A_11_IRQ_REG_START                         0x02237300
+#define BCHP_DS_A_11_IRQ_REG_END                           0x02237314
+#define BCHP_DS_A_12_ISW_MXR_REG_START                     0x02238000
+#define BCHP_DS_A_12_ISW_MXR_REG_END                       0x02238008
+#define BCHP_DS_A_12_ACI_AGF_REG_START                     0x02238200
+#define BCHP_DS_A_12_ACI_AGF_REG_END                       0x0223837c
+#define BCHP_DS_A_12_TRL_REG_START                         0x02238400
+#define BCHP_DS_A_12_TRL_REG_END                           0x022386fc
+#define BCHP_DS_A_12_EQ_REG_START                          0x02238800
+#define BCHP_DS_A_12_EQ_REG_END                            0x02238bbc
+#define BCHP_DS_A_12_FECF_REG_START                        0x02238c00
+#define BCHP_DS_A_12_FECF_REG_END                          0x02238d7c
+#define BCHP_DS_A_12_FECB_REG_START                        0x02238e00
+#define BCHP_DS_A_12_FECB_REG_END                          0x02238ebc
+#define BCHP_DS_A_12_FFT_REG_START                         0x02239000
+#define BCHP_DS_A_12_FFT_REG_END                           0x0223917c
+#define BCHP_DS_A_12_OI_REG_START                          0x02239200
+#define BCHP_DS_A_12_OI_REG_END                            0x0223923c
+#define BCHP_DS_A_12_IRQ_REG_START                         0x02239300
+#define BCHP_DS_A_12_IRQ_REG_END                           0x02239314
+#define BCHP_DS_A_13_ISW_MXR_REG_START                     0x0223a000
+#define BCHP_DS_A_13_ISW_MXR_REG_END                       0x0223a008
+#define BCHP_DS_A_13_ACI_AGF_REG_START                     0x0223a200
+#define BCHP_DS_A_13_ACI_AGF_REG_END                       0x0223a37c
+#define BCHP_DS_A_13_TRL_REG_START                         0x0223a400
+#define BCHP_DS_A_13_TRL_REG_END                           0x0223a6fc
+#define BCHP_DS_A_13_EQ_REG_START                          0x0223a800
+#define BCHP_DS_A_13_EQ_REG_END                            0x0223abbc
+#define BCHP_DS_A_13_FECF_REG_START                        0x0223ac00
+#define BCHP_DS_A_13_FECF_REG_END                          0x0223ad7c
+#define BCHP_DS_A_13_FECB_REG_START                        0x0223ae00
+#define BCHP_DS_A_13_FECB_REG_END                          0x0223aebc
+#define BCHP_DS_A_13_FFT_REG_START                         0x0223b000
+#define BCHP_DS_A_13_FFT_REG_END                           0x0223b17c
+#define BCHP_DS_A_13_OI_REG_START                          0x0223b200
+#define BCHP_DS_A_13_OI_REG_END                            0x0223b23c
+#define BCHP_DS_A_13_IRQ_REG_START                         0x0223b300
+#define BCHP_DS_A_13_IRQ_REG_END                           0x0223b314
+#define BCHP_DS_A_14_ISW_MXR_REG_START                     0x0223c000
+#define BCHP_DS_A_14_ISW_MXR_REG_END                       0x0223c008
+#define BCHP_DS_A_14_ACI_AGF_REG_START                     0x0223c200
+#define BCHP_DS_A_14_ACI_AGF_REG_END                       0x0223c37c
+#define BCHP_DS_A_14_TRL_REG_START                         0x0223c400
+#define BCHP_DS_A_14_TRL_REG_END                           0x0223c6fc
+#define BCHP_DS_A_14_EQ_REG_START                          0x0223c800
+#define BCHP_DS_A_14_EQ_REG_END                            0x0223cbbc
+#define BCHP_DS_A_14_FECF_REG_START                        0x0223cc00
+#define BCHP_DS_A_14_FECF_REG_END                          0x0223cd7c
+#define BCHP_DS_A_14_FECB_REG_START                        0x0223ce00
+#define BCHP_DS_A_14_FECB_REG_END                          0x0223cebc
+#define BCHP_DS_A_14_FFT_REG_START                         0x0223d000
+#define BCHP_DS_A_14_FFT_REG_END                           0x0223d17c
+#define BCHP_DS_A_14_OI_REG_START                          0x0223d200
+#define BCHP_DS_A_14_OI_REG_END                            0x0223d23c
+#define BCHP_DS_A_14_IRQ_REG_START                         0x0223d300
+#define BCHP_DS_A_14_IRQ_REG_END                           0x0223d314
+#define BCHP_DS_A_15_ISW_MXR_REG_START                     0x0223e000
+#define BCHP_DS_A_15_ISW_MXR_REG_END                       0x0223e008
+#define BCHP_DS_A_15_ACI_AGF_REG_START                     0x0223e200
+#define BCHP_DS_A_15_ACI_AGF_REG_END                       0x0223e37c
+#define BCHP_DS_A_15_TRL_REG_START                         0x0223e400
+#define BCHP_DS_A_15_TRL_REG_END                           0x0223e6fc
+#define BCHP_DS_A_15_EQ_REG_START                          0x0223e800
+#define BCHP_DS_A_15_EQ_REG_END                            0x0223ebbc
+#define BCHP_DS_A_15_FECF_REG_START                        0x0223ec00
+#define BCHP_DS_A_15_FECF_REG_END                          0x0223ed7c
+#define BCHP_DS_A_15_FECB_REG_START                        0x0223ee00
+#define BCHP_DS_A_15_FECB_REG_END                          0x0223eebc
+#define BCHP_DS_A_15_FFT_REG_START                         0x0223f000
+#define BCHP_DS_A_15_FFT_REG_END                           0x0223f17c
+#define BCHP_DS_A_15_OI_REG_START                          0x0223f200
+#define BCHP_DS_A_15_OI_REG_END                            0x0223f23c
+#define BCHP_DS_A_15_IRQ_REG_START                         0x0223f300
+#define BCHP_DS_A_15_IRQ_REG_END                           0x0223f314
+#define BCHP_DS_A_16_ISW_MXR_REG_START                     0x02240000
+#define BCHP_DS_A_16_ISW_MXR_REG_END                       0x02240008
+#define BCHP_DS_A_16_ACI_AGF_REG_START                     0x02240200
+#define BCHP_DS_A_16_ACI_AGF_REG_END                       0x0224037c
+#define BCHP_DS_A_16_TRL_REG_START                         0x02240400
+#define BCHP_DS_A_16_TRL_REG_END                           0x022406fc
+#define BCHP_DS_A_16_EQ_REG_START                          0x02240800
+#define BCHP_DS_A_16_EQ_REG_END                            0x02240bbc
+#define BCHP_DS_A_16_FECF_REG_START                        0x02240c00
+#define BCHP_DS_A_16_FECF_REG_END                          0x02240d7c
+#define BCHP_DS_A_16_FECB_REG_START                        0x02240e00
+#define BCHP_DS_A_16_FECB_REG_END                          0x02240ebc
+#define BCHP_DS_A_16_FFT_REG_START                         0x02241000
+#define BCHP_DS_A_16_FFT_REG_END                           0x0224117c
+#define BCHP_DS_A_16_OI_REG_START                          0x02241200
+#define BCHP_DS_A_16_OI_REG_END                            0x0224123c
+#define BCHP_DS_A_16_IRQ_REG_START                         0x02241300
+#define BCHP_DS_A_16_IRQ_REG_END                           0x02241314
+#define BCHP_DS_A_17_ISW_MXR_REG_START                     0x02242000
+#define BCHP_DS_A_17_ISW_MXR_REG_END                       0x02242008
+#define BCHP_DS_A_17_ACI_AGF_REG_START                     0x02242200
+#define BCHP_DS_A_17_ACI_AGF_REG_END                       0x0224237c
+#define BCHP_DS_A_17_TRL_REG_START                         0x02242400
+#define BCHP_DS_A_17_TRL_REG_END                           0x022426fc
+#define BCHP_DS_A_17_EQ_REG_START                          0x02242800
+#define BCHP_DS_A_17_EQ_REG_END                            0x02242bbc
+#define BCHP_DS_A_17_FECF_REG_START                        0x02242c00
+#define BCHP_DS_A_17_FECF_REG_END                          0x02242d7c
+#define BCHP_DS_A_17_FECB_REG_START                        0x02242e00
+#define BCHP_DS_A_17_FECB_REG_END                          0x02242ebc
+#define BCHP_DS_A_17_FFT_REG_START                         0x02243000
+#define BCHP_DS_A_17_FFT_REG_END                           0x0224317c
+#define BCHP_DS_A_17_OI_REG_START                          0x02243200
+#define BCHP_DS_A_17_OI_REG_END                            0x0224323c
+#define BCHP_DS_A_17_IRQ_REG_START                         0x02243300
+#define BCHP_DS_A_17_IRQ_REG_END                           0x02243314
+#define BCHP_DS_A_18_ISW_MXR_REG_START                     0x02244000
+#define BCHP_DS_A_18_ISW_MXR_REG_END                       0x02244008
+#define BCHP_DS_A_18_ACI_AGF_REG_START                     0x02244200
+#define BCHP_DS_A_18_ACI_AGF_REG_END                       0x0224437c
+#define BCHP_DS_A_18_TRL_REG_START                         0x02244400
+#define BCHP_DS_A_18_TRL_REG_END                           0x022446fc
+#define BCHP_DS_A_18_EQ_REG_START                          0x02244800
+#define BCHP_DS_A_18_EQ_REG_END                            0x02244bbc
+#define BCHP_DS_A_18_FECF_REG_START                        0x02244c00
+#define BCHP_DS_A_18_FECF_REG_END                          0x02244d7c
+#define BCHP_DS_A_18_FECB_REG_START                        0x02244e00
+#define BCHP_DS_A_18_FECB_REG_END                          0x02244ebc
+#define BCHP_DS_A_18_FFT_REG_START                         0x02245000
+#define BCHP_DS_A_18_FFT_REG_END                           0x0224517c
+#define BCHP_DS_A_18_OI_REG_START                          0x02245200
+#define BCHP_DS_A_18_OI_REG_END                            0x0224523c
+#define BCHP_DS_A_18_IRQ_REG_START                         0x02245300
+#define BCHP_DS_A_18_IRQ_REG_END                           0x02245314
+#define BCHP_DS_A_19_ISW_MXR_REG_START                     0x02246000
+#define BCHP_DS_A_19_ISW_MXR_REG_END                       0x02246008
+#define BCHP_DS_A_19_ACI_AGF_REG_START                     0x02246200
+#define BCHP_DS_A_19_ACI_AGF_REG_END                       0x0224637c
+#define BCHP_DS_A_19_TRL_REG_START                         0x02246400
+#define BCHP_DS_A_19_TRL_REG_END                           0x022466fc
+#define BCHP_DS_A_19_EQ_REG_START                          0x02246800
+#define BCHP_DS_A_19_EQ_REG_END                            0x02246bbc
+#define BCHP_DS_A_19_FECF_REG_START                        0x02246c00
+#define BCHP_DS_A_19_FECF_REG_END                          0x02246d7c
+#define BCHP_DS_A_19_FECB_REG_START                        0x02246e00
+#define BCHP_DS_A_19_FECB_REG_END                          0x02246ebc
+#define BCHP_DS_A_19_FFT_REG_START                         0x02247000
+#define BCHP_DS_A_19_FFT_REG_END                           0x0224717c
+#define BCHP_DS_A_19_OI_REG_START                          0x02247200
+#define BCHP_DS_A_19_OI_REG_END                            0x0224723c
+#define BCHP_DS_A_19_IRQ_REG_START                         0x02247300
+#define BCHP_DS_A_19_IRQ_REG_END                           0x02247314
+#define BCHP_DS_A_20_ISW_MXR_REG_START                     0x02248000
+#define BCHP_DS_A_20_ISW_MXR_REG_END                       0x02248008
+#define BCHP_DS_A_20_ACI_AGF_REG_START                     0x02248200
+#define BCHP_DS_A_20_ACI_AGF_REG_END                       0x0224837c
+#define BCHP_DS_A_20_TRL_REG_START                         0x02248400
+#define BCHP_DS_A_20_TRL_REG_END                           0x022486fc
+#define BCHP_DS_A_20_EQ_REG_START                          0x02248800
+#define BCHP_DS_A_20_EQ_REG_END                            0x02248bbc
+#define BCHP_DS_A_20_FECF_REG_START                        0x02248c00
+#define BCHP_DS_A_20_FECF_REG_END                          0x02248d7c
+#define BCHP_DS_A_20_FECB_REG_START                        0x02248e00
+#define BCHP_DS_A_20_FECB_REG_END                          0x02248ebc
+#define BCHP_DS_A_20_FFT_REG_START                         0x02249000
+#define BCHP_DS_A_20_FFT_REG_END                           0x0224917c
+#define BCHP_DS_A_20_OI_REG_START                          0x02249200
+#define BCHP_DS_A_20_OI_REG_END                            0x0224923c
+#define BCHP_DS_A_20_IRQ_REG_START                         0x02249300
+#define BCHP_DS_A_20_IRQ_REG_END                           0x02249314
+#define BCHP_DS_A_21_ISW_MXR_REG_START                     0x0224a000
+#define BCHP_DS_A_21_ISW_MXR_REG_END                       0x0224a008
+#define BCHP_DS_A_21_ACI_AGF_REG_START                     0x0224a200
+#define BCHP_DS_A_21_ACI_AGF_REG_END                       0x0224a37c
+#define BCHP_DS_A_21_TRL_REG_START                         0x0224a400
+#define BCHP_DS_A_21_TRL_REG_END                           0x0224a6fc
+#define BCHP_DS_A_21_EQ_REG_START                          0x0224a800
+#define BCHP_DS_A_21_EQ_REG_END                            0x0224abbc
+#define BCHP_DS_A_21_FECF_REG_START                        0x0224ac00
+#define BCHP_DS_A_21_FECF_REG_END                          0x0224ad7c
+#define BCHP_DS_A_21_FECB_REG_START                        0x0224ae00
+#define BCHP_DS_A_21_FECB_REG_END                          0x0224aebc
+#define BCHP_DS_A_21_FFT_REG_START                         0x0224b000
+#define BCHP_DS_A_21_FFT_REG_END                           0x0224b17c
+#define BCHP_DS_A_21_OI_REG_START                          0x0224b200
+#define BCHP_DS_A_21_OI_REG_END                            0x0224b23c
+#define BCHP_DS_A_21_IRQ_REG_START                         0x0224b300
+#define BCHP_DS_A_21_IRQ_REG_END                           0x0224b314
+#define BCHP_DS_A_22_ISW_MXR_REG_START                     0x0224c000
+#define BCHP_DS_A_22_ISW_MXR_REG_END                       0x0224c008
+#define BCHP_DS_A_22_ACI_AGF_REG_START                     0x0224c200
+#define BCHP_DS_A_22_ACI_AGF_REG_END                       0x0224c37c
+#define BCHP_DS_A_22_TRL_REG_START                         0x0224c400
+#define BCHP_DS_A_22_TRL_REG_END                           0x0224c6fc
+#define BCHP_DS_A_22_EQ_REG_START                          0x0224c800
+#define BCHP_DS_A_22_EQ_REG_END                            0x0224cbbc
+#define BCHP_DS_A_22_FECF_REG_START                        0x0224cc00
+#define BCHP_DS_A_22_FECF_REG_END                          0x0224cd7c
+#define BCHP_DS_A_22_FECB_REG_START                        0x0224ce00
+#define BCHP_DS_A_22_FECB_REG_END                          0x0224cebc
+#define BCHP_DS_A_22_FFT_REG_START                         0x0224d000
+#define BCHP_DS_A_22_FFT_REG_END                           0x0224d17c
+#define BCHP_DS_A_22_OI_REG_START                          0x0224d200
+#define BCHP_DS_A_22_OI_REG_END                            0x0224d23c
+#define BCHP_DS_A_22_IRQ_REG_START                         0x0224d300
+#define BCHP_DS_A_22_IRQ_REG_END                           0x0224d314
+#define BCHP_DS_A_23_ISW_MXR_REG_START                     0x0224e000
+#define BCHP_DS_A_23_ISW_MXR_REG_END                       0x0224e008
+#define BCHP_DS_A_23_ACI_AGF_REG_START                     0x0224e200
+#define BCHP_DS_A_23_ACI_AGF_REG_END                       0x0224e37c
+#define BCHP_DS_A_23_TRL_REG_START                         0x0224e400
+#define BCHP_DS_A_23_TRL_REG_END                           0x0224e6fc
+#define BCHP_DS_A_23_EQ_REG_START                          0x0224e800
+#define BCHP_DS_A_23_EQ_REG_END                            0x0224ebbc
+#define BCHP_DS_A_23_FECF_REG_START                        0x0224ec00
+#define BCHP_DS_A_23_FECF_REG_END                          0x0224ed7c
+#define BCHP_DS_A_23_FECB_REG_START                        0x0224ee00
+#define BCHP_DS_A_23_FECB_REG_END                          0x0224eebc
+#define BCHP_DS_A_23_FFT_REG_START                         0x0224f000
+#define BCHP_DS_A_23_FFT_REG_END                           0x0224f17c
+#define BCHP_DS_A_23_OI_REG_START                          0x0224f200
+#define BCHP_DS_A_23_OI_REG_END                            0x0224f23c
+#define BCHP_DS_A_23_IRQ_REG_START                         0x0224f300
+#define BCHP_DS_A_23_IRQ_REG_END                           0x0224f314
+#define BCHP_DS_A_24_ISW_MXR_REG_START                     0x02250000
+#define BCHP_DS_A_24_ISW_MXR_REG_END                       0x02250008
+#define BCHP_DS_A_24_ACI_AGF_REG_START                     0x02250200
+#define BCHP_DS_A_24_ACI_AGF_REG_END                       0x0225037c
+#define BCHP_DS_A_24_TRL_REG_START                         0x02250400
+#define BCHP_DS_A_24_TRL_REG_END                           0x022506fc
+#define BCHP_DS_A_24_EQ_REG_START                          0x02250800
+#define BCHP_DS_A_24_EQ_REG_END                            0x02250bbc
+#define BCHP_DS_A_24_FECF_REG_START                        0x02250c00
+#define BCHP_DS_A_24_FECF_REG_END                          0x02250d7c
+#define BCHP_DS_A_24_FECB_REG_START                        0x02250e00
+#define BCHP_DS_A_24_FECB_REG_END                          0x02250ebc
+#define BCHP_DS_A_24_FFT_REG_START                         0x02251000
+#define BCHP_DS_A_24_FFT_REG_END                           0x0225117c
+#define BCHP_DS_A_24_OI_REG_START                          0x02251200
+#define BCHP_DS_A_24_OI_REG_END                            0x0225123c
+#define BCHP_DS_A_24_IRQ_REG_START                         0x02251300
+#define BCHP_DS_A_24_IRQ_REG_END                           0x02251314
+#define BCHP_DS_A_25_ISW_MXR_REG_START                     0x02252000
+#define BCHP_DS_A_25_ISW_MXR_REG_END                       0x02252008
+#define BCHP_DS_A_25_ACI_AGF_REG_START                     0x02252200
+#define BCHP_DS_A_25_ACI_AGF_REG_END                       0x0225237c
+#define BCHP_DS_A_25_TRL_REG_START                         0x02252400
+#define BCHP_DS_A_25_TRL_REG_END                           0x022526fc
+#define BCHP_DS_A_25_EQ_REG_START                          0x02252800
+#define BCHP_DS_A_25_EQ_REG_END                            0x02252bbc
+#define BCHP_DS_A_25_FECF_REG_START                        0x02252c00
+#define BCHP_DS_A_25_FECF_REG_END                          0x02252d7c
+#define BCHP_DS_A_25_FECB_REG_START                        0x02252e00
+#define BCHP_DS_A_25_FECB_REG_END                          0x02252ebc
+#define BCHP_DS_A_25_FFT_REG_START                         0x02253000
+#define BCHP_DS_A_25_FFT_REG_END                           0x0225317c
+#define BCHP_DS_A_25_OI_REG_START                          0x02253200
+#define BCHP_DS_A_25_OI_REG_END                            0x0225323c
+#define BCHP_DS_A_25_IRQ_REG_START                         0x02253300
+#define BCHP_DS_A_25_IRQ_REG_END                           0x02253314
+#define BCHP_DS_A_26_ISW_MXR_REG_START                     0x02254000
+#define BCHP_DS_A_26_ISW_MXR_REG_END                       0x02254008
+#define BCHP_DS_A_26_ACI_AGF_REG_START                     0x02254200
+#define BCHP_DS_A_26_ACI_AGF_REG_END                       0x0225437c
+#define BCHP_DS_A_26_TRL_REG_START                         0x02254400
+#define BCHP_DS_A_26_TRL_REG_END                           0x022546fc
+#define BCHP_DS_A_26_EQ_REG_START                          0x02254800
+#define BCHP_DS_A_26_EQ_REG_END                            0x02254bbc
+#define BCHP_DS_A_26_FECF_REG_START                        0x02254c00
+#define BCHP_DS_A_26_FECF_REG_END                          0x02254d7c
+#define BCHP_DS_A_26_FECB_REG_START                        0x02254e00
+#define BCHP_DS_A_26_FECB_REG_END                          0x02254ebc
+#define BCHP_DS_A_26_FFT_REG_START                         0x02255000
+#define BCHP_DS_A_26_FFT_REG_END                           0x0225517c
+#define BCHP_DS_A_26_OI_REG_START                          0x02255200
+#define BCHP_DS_A_26_OI_REG_END                            0x0225523c
+#define BCHP_DS_A_26_IRQ_REG_START                         0x02255300
+#define BCHP_DS_A_26_IRQ_REG_END                           0x02255314
+#define BCHP_DS_A_27_ISW_MXR_REG_START                     0x02256000
+#define BCHP_DS_A_27_ISW_MXR_REG_END                       0x02256008
+#define BCHP_DS_A_27_ACI_AGF_REG_START                     0x02256200
+#define BCHP_DS_A_27_ACI_AGF_REG_END                       0x0225637c
+#define BCHP_DS_A_27_TRL_REG_START                         0x02256400
+#define BCHP_DS_A_27_TRL_REG_END                           0x022566fc
+#define BCHP_DS_A_27_EQ_REG_START                          0x02256800
+#define BCHP_DS_A_27_EQ_REG_END                            0x02256bbc
+#define BCHP_DS_A_27_FECF_REG_START                        0x02256c00
+#define BCHP_DS_A_27_FECF_REG_END                          0x02256d7c
+#define BCHP_DS_A_27_FECB_REG_START                        0x02256e00
+#define BCHP_DS_A_27_FECB_REG_END                          0x02256ebc
+#define BCHP_DS_A_27_FFT_REG_START                         0x02257000
+#define BCHP_DS_A_27_FFT_REG_END                           0x0225717c
+#define BCHP_DS_A_27_OI_REG_START                          0x02257200
+#define BCHP_DS_A_27_OI_REG_END                            0x0225723c
+#define BCHP_DS_A_27_IRQ_REG_START                         0x02257300
+#define BCHP_DS_A_27_IRQ_REG_END                           0x02257314
+#define BCHP_DS_A_28_ISW_MXR_REG_START                     0x02258000
+#define BCHP_DS_A_28_ISW_MXR_REG_END                       0x02258008
+#define BCHP_DS_A_28_ACI_AGF_REG_START                     0x02258200
+#define BCHP_DS_A_28_ACI_AGF_REG_END                       0x0225837c
+#define BCHP_DS_A_28_TRL_REG_START                         0x02258400
+#define BCHP_DS_A_28_TRL_REG_END                           0x022586fc
+#define BCHP_DS_A_28_EQ_REG_START                          0x02258800
+#define BCHP_DS_A_28_EQ_REG_END                            0x02258bbc
+#define BCHP_DS_A_28_FECF_REG_START                        0x02258c00
+#define BCHP_DS_A_28_FECF_REG_END                          0x02258d7c
+#define BCHP_DS_A_28_FECB_REG_START                        0x02258e00
+#define BCHP_DS_A_28_FECB_REG_END                          0x02258ebc
+#define BCHP_DS_A_28_FFT_REG_START                         0x02259000
+#define BCHP_DS_A_28_FFT_REG_END                           0x0225917c
+#define BCHP_DS_A_28_OI_REG_START                          0x02259200
+#define BCHP_DS_A_28_OI_REG_END                            0x0225923c
+#define BCHP_DS_A_28_IRQ_REG_START                         0x02259300
+#define BCHP_DS_A_28_IRQ_REG_END                           0x02259314
+#define BCHP_DS_A_29_ISW_MXR_REG_START                     0x0225a000
+#define BCHP_DS_A_29_ISW_MXR_REG_END                       0x0225a008
+#define BCHP_DS_A_29_ACI_AGF_REG_START                     0x0225a200
+#define BCHP_DS_A_29_ACI_AGF_REG_END                       0x0225a37c
+#define BCHP_DS_A_29_TRL_REG_START                         0x0225a400
+#define BCHP_DS_A_29_TRL_REG_END                           0x0225a6fc
+#define BCHP_DS_A_29_EQ_REG_START                          0x0225a800
+#define BCHP_DS_A_29_EQ_REG_END                            0x0225abbc
+#define BCHP_DS_A_29_FECF_REG_START                        0x0225ac00
+#define BCHP_DS_A_29_FECF_REG_END                          0x0225ad7c
+#define BCHP_DS_A_29_FECB_REG_START                        0x0225ae00
+#define BCHP_DS_A_29_FECB_REG_END                          0x0225aebc
+#define BCHP_DS_A_29_FFT_REG_START                         0x0225b000
+#define BCHP_DS_A_29_FFT_REG_END                           0x0225b17c
+#define BCHP_DS_A_29_OI_REG_START                          0x0225b200
+#define BCHP_DS_A_29_OI_REG_END                            0x0225b23c
+#define BCHP_DS_A_29_IRQ_REG_START                         0x0225b300
+#define BCHP_DS_A_29_IRQ_REG_END                           0x0225b314
+#define BCHP_DS_A_30_ISW_MXR_REG_START                     0x0225c000
+#define BCHP_DS_A_30_ISW_MXR_REG_END                       0x0225c008
+#define BCHP_DS_A_30_ACI_AGF_REG_START                     0x0225c200
+#define BCHP_DS_A_30_ACI_AGF_REG_END                       0x0225c37c
+#define BCHP_DS_A_30_TRL_REG_START                         0x0225c400
+#define BCHP_DS_A_30_TRL_REG_END                           0x0225c6fc
+#define BCHP_DS_A_30_EQ_REG_START                          0x0225c800
+#define BCHP_DS_A_30_EQ_REG_END                            0x0225cbbc
+#define BCHP_DS_A_30_FECF_REG_START                        0x0225cc00
+#define BCHP_DS_A_30_FECF_REG_END                          0x0225cd7c
+#define BCHP_DS_A_30_FECB_REG_START                        0x0225ce00
+#define BCHP_DS_A_30_FECB_REG_END                          0x0225cebc
+#define BCHP_DS_A_30_FFT_REG_START                         0x0225d000
+#define BCHP_DS_A_30_FFT_REG_END                           0x0225d17c
+#define BCHP_DS_A_30_OI_REG_START                          0x0225d200
+#define BCHP_DS_A_30_OI_REG_END                            0x0225d23c
+#define BCHP_DS_A_30_IRQ_REG_START                         0x0225d300
+#define BCHP_DS_A_30_IRQ_REG_END                           0x0225d314
+#define BCHP_DS_A_31_ISW_MXR_REG_START                     0x0225e000
+#define BCHP_DS_A_31_ISW_MXR_REG_END                       0x0225e008
+#define BCHP_DS_A_31_ACI_AGF_REG_START                     0x0225e200
+#define BCHP_DS_A_31_ACI_AGF_REG_END                       0x0225e37c
+#define BCHP_DS_A_31_TRL_REG_START                         0x0225e400
+#define BCHP_DS_A_31_TRL_REG_END                           0x0225e6fc
+#define BCHP_DS_A_31_EQ_REG_START                          0x0225e800
+#define BCHP_DS_A_31_EQ_REG_END                            0x0225ebbc
+#define BCHP_DS_A_31_FECF_REG_START                        0x0225ec00
+#define BCHP_DS_A_31_FECF_REG_END                          0x0225ed7c
+#define BCHP_DS_A_31_FECB_REG_START                        0x0225ee00
+#define BCHP_DS_A_31_FECB_REG_END                          0x0225eebc
+#define BCHP_DS_A_31_FFT_REG_START                         0x0225f000
+#define BCHP_DS_A_31_FFT_REG_END                           0x0225f17c
+#define BCHP_DS_A_31_OI_REG_START                          0x0225f200
+#define BCHP_DS_A_31_OI_REG_END                            0x0225f23c
+#define BCHP_DS_A_31_IRQ_REG_START                         0x0225f300
+#define BCHP_DS_A_31_IRQ_REG_END                           0x0225f314
+#define BCHP_DS_A_32_ISW_MXR_REG_START                     0x02260000
+#define BCHP_DS_A_32_ISW_MXR_REG_END                       0x02260008
+#define BCHP_DS_A_32_ACI_AGF_REG_START                     0x02260200
+#define BCHP_DS_A_32_ACI_AGF_REG_END                       0x0226037c
+#define BCHP_DS_A_32_TRL_REG_START                         0x02260400
+#define BCHP_DS_A_32_TRL_REG_END                           0x022606fc
+#define BCHP_DS_A_32_EQ_REG_START                          0x02260800
+#define BCHP_DS_A_32_EQ_REG_END                            0x02260bbc
+#define BCHP_DS_A_32_FECF_REG_START                        0x02260c00
+#define BCHP_DS_A_32_FECF_REG_END                          0x02260d7c
+#define BCHP_DS_A_32_FECB_REG_START                        0x02260e00
+#define BCHP_DS_A_32_FECB_REG_END                          0x02260ebc
+#define BCHP_DS_A_32_FFT_REG_START                         0x02261000
+#define BCHP_DS_A_32_FFT_REG_END                           0x0226117c
+#define BCHP_DS_A_32_OI_REG_START                          0x02261200
+#define BCHP_DS_A_32_OI_REG_END                            0x0226123c
+#define BCHP_DS_A_32_IRQ_REG_START                         0x02261300
+#define BCHP_DS_A_32_IRQ_REG_END                           0x02261314
+#define BCHP_CMD_AFEC_GLOBAL_A_REG_START                   0x022c0000
+#define BCHP_CMD_AFEC_GLOBAL_A_REG_END                     0x022c0010
+#define BCHP_CMD_AFEC_A_REG_START                          0x022c0100
+#define BCHP_CMD_AFEC_A_REG_END                            0x022c0158
+#define BCHP_CMD_AFEC_STATS_A_REG_START                    0x022c2000
+#define BCHP_CMD_AFEC_STATS_A_REG_END                      0x022c307c
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_A_REG_START             0x022c4000
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_A_REG_END               0x022c402c
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_A_REG_START             0x022c4400
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_A_REG_END               0x022c442c
+#define BCHP_CMD_AFEC_GLOBAL_B_REG_START                   0x022d0000
+#define BCHP_CMD_AFEC_GLOBAL_B_REG_END                     0x022d0010
+#define BCHP_CMD_AFEC_B_REG_START                          0x022d0100
+#define BCHP_CMD_AFEC_B_REG_END                            0x022d0158
+#define BCHP_CMD_AFEC_STATS_B_REG_START                    0x022d2000
+#define BCHP_CMD_AFEC_STATS_B_REG_END                      0x022d307c
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_B_REG_START             0x022d4000
+#define BCHP_CMD_AFEC_INTR_CTRL2_0_B_REG_END               0x022d402c
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_B_REG_START             0x022d4400
+#define BCHP_CMD_AFEC_INTR_CTRL2_1_B_REG_END               0x022d442c
+#define BCHP_AIF_WB_CAB_CORE_REG_START                     0x022e0000
+#define BCHP_AIF_WB_CAB_CORE_REG_END                       0x022e04c4
+#define BCHP_AIF_WB_CAB_CORE_INTR2_REG_START               0x022e0800
+#define BCHP_AIF_WB_CAB_CORE_INTR2_REG_END                 0x022e082c
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_REG_START               0x022e1000
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_REG_END                 0x022e1138
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_INTR2_REG_START         0x022e1800
+#define BCHP_AIF_MDAC_CAL_CAB_CORE_INTR2_REG_END           0x022e182c
+#define BCHP_AIF_WB_CAB_ANA_REG_START                      0x022e2000
+#define BCHP_AIF_WB_CAB_ANA_REG_END                        0x022e20a4
+#define BCHP_AIF_WB_CAB_DECFILT_REG_START                  0x022e3000
+#define BCHP_AIF_WB_CAB_DECFILT_REG_END                    0x022e302c
+#define BCHP_UDA_CORE_REG_START                            0x022e4000
+#define BCHP_UDA_CORE_REG_END                              0x022e4508
+#define BCHP_UDA_ANA_REG_START                             0x022e5000
+#define BCHP_UDA_ANA_REG_END                               0x022e5034
+#define BCHP_WOD_CPU0_PROG_MEM_A_REG_START                 0x02300000
+#define BCHP_WOD_CPU0_PROG_MEM_A_REG_END                   0x02307ffc
+#define BCHP_WOD_CPU0_DATA_MEM_A_REG_START                 0x02320000
+#define BCHP_WOD_CPU0_DATA_MEM_A_REG_END                   0x0232affc
+#define BCHP_WOD_CPU0_CORE_REGS_A_REG_START                0x02340000
+#define BCHP_WOD_CPU0_CORE_REGS_A_REG_END                  0x023400fc
+#define BCHP_WOD_CPU0_AUX_REGS_A_REG_START                 0x02342000
+#define BCHP_WOD_CPU0_AUX_REGS_A_REG_END                   0x02342a08
+#define BCHP_WOD_CPU0_CTRL_A_REG_START                     0x02344000
+#define BCHP_WOD_CPU0_CTRL_A_REG_END                       0x02344010
+#define BCHP_WOD_CPU0_L1_A_REG_START                       0x02344100
+#define BCHP_WOD_CPU0_L1_A_REG_END                         0x02344118
+#define BCHP_WOD_INTR_A_REG_START                          0x02346000
+#define BCHP_WOD_INTR_A_REG_END                            0x0234602c
+#define BCHP_WOD_INTR2_A_REG_START                         0x02346040
+#define BCHP_WOD_INTR2_A_REG_END                           0x0234606c
+#define BCHP_WOD_SEQ0_A_REG_START                          0x02346800
+#define BCHP_WOD_SEQ0_A_REG_END                            0x023468f4
+#define BCHP_WOD_SEQ1_A_REG_START                          0x02346900
+#define BCHP_WOD_SEQ1_A_REG_END                            0x023469f4
+#define BCHP_WOD_SEQ2_A_REG_START                          0x02346a00
+#define BCHP_WOD_SEQ2_A_REG_END                            0x02346af4
+#define BCHP_WOD_SEQ3_A_REG_START                          0x02346b00
+#define BCHP_WOD_SEQ3_A_REG_END                            0x02346bf4
+#define BCHP_WOD_MEM_CTRL_A_REG_START                      0x02350000
+#define BCHP_WOD_MEM_CTRL_A_REG_END                        0x02350094
+#define BCHP_WOD_MEM_PROC0_A_REG_START                     0x02350100
+#define BCHP_WOD_MEM_PROC0_A_REG_END                       0x02350124
+#define BCHP_WOD_MEM_PROC1_A_REG_START                     0x02350140
+#define BCHP_WOD_MEM_PROC1_A_REG_END                       0x02350164
+#define BCHP_WOD_MEM_PROC2_A_REG_START                     0x02350180
+#define BCHP_WOD_MEM_PROC2_A_REG_END                       0x023501a4
+#define BCHP_WOD_MEM_PROC3_A_REG_START                     0x023501c0
+#define BCHP_WOD_MEM_PROC3_A_REG_END                       0x023501e4
+#define BCHP_WOD_MEM_PROC4_A_REG_START                     0x02350200
+#define BCHP_WOD_MEM_PROC4_A_REG_END                       0x02350224
+#define BCHP_WOD_MEM_PROC5_A_REG_START                     0x02350240
+#define BCHP_WOD_MEM_PROC5_A_REG_END                       0x02350264
+#define BCHP_WOD_MEM_PROC6_A_REG_START                     0x02350280
+#define BCHP_WOD_MEM_PROC6_A_REG_END                       0x023502a4
+#define BCHP_WOD_MEM_PROC7_A_REG_START                     0x023502c0
+#define BCHP_WOD_MEM_PROC7_A_REG_END                       0x023502e4
+#define BCHP_WOD_MEM_PROC8_A_REG_START                     0x02350300
+#define BCHP_WOD_MEM_PROC8_A_REG_END                       0x02350324
+#define BCHP_WOD_MEM_PROC9_A_REG_START                     0x02350340
+#define BCHP_WOD_MEM_PROC9_A_REG_END                       0x02350364
+#define BCHP_WOD_MEM_PROC10_A_REG_START                    0x02350380
+#define BCHP_WOD_MEM_PROC10_A_REG_END                      0x023503a4
+#define BCHP_WOD_MEM_PROC11_A_REG_START                    0x023503c0
+#define BCHP_WOD_MEM_PROC11_A_REG_END                      0x023503e4
+#define BCHP_WOD_MEM_PROC12_A_REG_START                    0x02350400
+#define BCHP_WOD_MEM_PROC12_A_REG_END                      0x02350424
+#define BCHP_WOD_MEM_PROC13_A_REG_START                    0x02350440
+#define BCHP_WOD_MEM_PROC13_A_REG_END                      0x02350464
+#define BCHP_WOD_MEM_PROC14_A_REG_START                    0x02350480
+#define BCHP_WOD_MEM_PROC14_A_REG_END                      0x023504a4
+#define BCHP_WOD_MEM_PROC15_A_REG_START                    0x023504c0
+#define BCHP_WOD_MEM_PROC15_A_REG_END                      0x023504e4
+#define BCHP_WOD_GLB_A_REG_START                           0x02350800
+#define BCHP_WOD_GLB_A_REG_END                             0x023508ac
+#define BCHP_WOD_CHAN_FE_A_REG_START                       0x02351000
+#define BCHP_WOD_CHAN_FE_A_REG_END                         0x02351114
+#define BCHP_WOD_OFDM_A_REG_START                          0x02352000
+#define BCHP_WOD_OFDM_A_REG_END                            0x02352444
+#define BCHP_WOD_LOCAL_A_REG_START                         0x02353000
+#define BCHP_WOD_LOCAL_A_REG_END                           0x023530ec
+#define BCHP_WOD_INTR_LOC_A_A_REG_START                    0x02354000
+#define BCHP_WOD_INTR_LOC_A_A_REG_END                      0x0235402c
+#define BCHP_WOD_INTR_LOC_B_A_REG_START                    0x02354040
+#define BCHP_WOD_INTR_LOC_B_A_REG_END                      0x0235406c
+#define BCHP_WOD_INTR_LOC_A2_A_REG_START                   0x02354080
+#define BCHP_WOD_INTR_LOC_A2_A_REG_END                     0x023540ac
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_A_REG_START             0x02358000
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_A_REG_END               0x02358ffc
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_A_REG_START              0x02359000
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_A_REG_END                0x02359ffc
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_A_REG_START       0x0235a000
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_A_REG_END         0x0235a3fc
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_A_REG_START          0x0235a400
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_A_REG_END            0x0235a4fc
+#define BCHP_WOD_TABLE_PP_CP_INDEX_A_REG_START             0x0235a500
+#define BCHP_WOD_TABLE_PP_CP_INDEX_A_REG_END               0x0235a5fc
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_A_REG_START            0x0235a600
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_A_REG_END              0x0235a69c
+#define BCHP_WOD_TABLE_FAVG_COEF_A_REG_START               0x0235a6c0
+#define BCHP_WOD_TABLE_FAVG_COEF_A_REG_END                 0x0235a6dc
+#define BCHP_WOD_DMEM0_A_REG_START                         0x02360000
+#define BCHP_WOD_DMEM0_A_REG_END                           0x02367ffc
+#define BCHP_WOD_DMEM1_A_REG_START                         0x02368000
+#define BCHP_WOD_DMEM1_A_REG_END                           0x0236fffc
+#define BCHP_WOD_DMEM2_A_REG_START                         0x02370000
+#define BCHP_WOD_DMEM2_A_REG_END                           0x02377ffc
+#define BCHP_WOD_DMEM3_A_REG_START                         0x02378000
+#define BCHP_WOD_DMEM3_A_REG_END                           0x0237fffc
+#define BCHP_WOD_CPU0_PROG_MEM_B_REG_START                 0x02380000
+#define BCHP_WOD_CPU0_PROG_MEM_B_REG_END                   0x02387ffc
+#define BCHP_WOD_CPU0_DATA_MEM_B_REG_START                 0x023a0000
+#define BCHP_WOD_CPU0_DATA_MEM_B_REG_END                   0x023aaffc
+#define BCHP_WOD_CPU0_CORE_REGS_B_REG_START                0x023c0000
+#define BCHP_WOD_CPU0_CORE_REGS_B_REG_END                  0x023c00fc
+#define BCHP_WOD_CPU0_AUX_REGS_B_REG_START                 0x023c2000
+#define BCHP_WOD_CPU0_AUX_REGS_B_REG_END                   0x023c2a08
+#define BCHP_WOD_CPU0_CTRL_B_REG_START                     0x023c4000
+#define BCHP_WOD_CPU0_CTRL_B_REG_END                       0x023c4010
+#define BCHP_WOD_CPU0_L1_B_REG_START                       0x023c4100
+#define BCHP_WOD_CPU0_L1_B_REG_END                         0x023c4118
+#define BCHP_WOD_INTR_B_REG_START                          0x023c6000
+#define BCHP_WOD_INTR_B_REG_END                            0x023c602c
+#define BCHP_WOD_INTR2_B_REG_START                         0x023c6040
+#define BCHP_WOD_INTR2_B_REG_END                           0x023c606c
+#define BCHP_WOD_SEQ0_B_REG_START                          0x023c6800
+#define BCHP_WOD_SEQ0_B_REG_END                            0x023c68f4
+#define BCHP_WOD_SEQ1_B_REG_START                          0x023c6900
+#define BCHP_WOD_SEQ1_B_REG_END                            0x023c69f4
+#define BCHP_WOD_SEQ2_B_REG_START                          0x023c6a00
+#define BCHP_WOD_SEQ2_B_REG_END                            0x023c6af4
+#define BCHP_WOD_SEQ3_B_REG_START                          0x023c6b00
+#define BCHP_WOD_SEQ3_B_REG_END                            0x023c6bf4
+#define BCHP_WOD_MEM_CTRL_B_REG_START                      0x023d0000
+#define BCHP_WOD_MEM_CTRL_B_REG_END                        0x023d0094
+#define BCHP_WOD_MEM_PROC0_B_REG_START                     0x023d0100
+#define BCHP_WOD_MEM_PROC0_B_REG_END                       0x023d0124
+#define BCHP_WOD_MEM_PROC1_B_REG_START                     0x023d0140
+#define BCHP_WOD_MEM_PROC1_B_REG_END                       0x023d0164
+#define BCHP_WOD_MEM_PROC2_B_REG_START                     0x023d0180
+#define BCHP_WOD_MEM_PROC2_B_REG_END                       0x023d01a4
+#define BCHP_WOD_MEM_PROC3_B_REG_START                     0x023d01c0
+#define BCHP_WOD_MEM_PROC3_B_REG_END                       0x023d01e4
+#define BCHP_WOD_MEM_PROC4_B_REG_START                     0x023d0200
+#define BCHP_WOD_MEM_PROC4_B_REG_END                       0x023d0224
+#define BCHP_WOD_MEM_PROC5_B_REG_START                     0x023d0240
+#define BCHP_WOD_MEM_PROC5_B_REG_END                       0x023d0264
+#define BCHP_WOD_MEM_PROC6_B_REG_START                     0x023d0280
+#define BCHP_WOD_MEM_PROC6_B_REG_END                       0x023d02a4
+#define BCHP_WOD_MEM_PROC7_B_REG_START                     0x023d02c0
+#define BCHP_WOD_MEM_PROC7_B_REG_END                       0x023d02e4
+#define BCHP_WOD_MEM_PROC8_B_REG_START                     0x023d0300
+#define BCHP_WOD_MEM_PROC8_B_REG_END                       0x023d0324
+#define BCHP_WOD_MEM_PROC9_B_REG_START                     0x023d0340
+#define BCHP_WOD_MEM_PROC9_B_REG_END                       0x023d0364
+#define BCHP_WOD_MEM_PROC10_B_REG_START                    0x023d0380
+#define BCHP_WOD_MEM_PROC10_B_REG_END                      0x023d03a4
+#define BCHP_WOD_MEM_PROC11_B_REG_START                    0x023d03c0
+#define BCHP_WOD_MEM_PROC11_B_REG_END                      0x023d03e4
+#define BCHP_WOD_MEM_PROC12_B_REG_START                    0x023d0400
+#define BCHP_WOD_MEM_PROC12_B_REG_END                      0x023d0424
+#define BCHP_WOD_MEM_PROC13_B_REG_START                    0x023d0440
+#define BCHP_WOD_MEM_PROC13_B_REG_END                      0x023d0464
+#define BCHP_WOD_MEM_PROC14_B_REG_START                    0x023d0480
+#define BCHP_WOD_MEM_PROC14_B_REG_END                      0x023d04a4
+#define BCHP_WOD_MEM_PROC15_B_REG_START                    0x023d04c0
+#define BCHP_WOD_MEM_PROC15_B_REG_END                      0x023d04e4
+#define BCHP_WOD_GLB_B_REG_START                           0x023d0800
+#define BCHP_WOD_GLB_B_REG_END                             0x023d08ac
+#define BCHP_WOD_CHAN_FE_B_REG_START                       0x023d1000
+#define BCHP_WOD_CHAN_FE_B_REG_END                         0x023d1114
+#define BCHP_WOD_OFDM_B_REG_START                          0x023d2000
+#define BCHP_WOD_OFDM_B_REG_END                            0x023d2444
+#define BCHP_WOD_LOCAL_B_REG_START                         0x023d3000
+#define BCHP_WOD_LOCAL_B_REG_END                           0x023d30ec
+#define BCHP_WOD_INTR_LOC_A_B_REG_START                    0x023d4000
+#define BCHP_WOD_INTR_LOC_A_B_REG_END                      0x023d402c
+#define BCHP_WOD_INTR_LOC_B_B_REG_START                    0x023d4040
+#define BCHP_WOD_INTR_LOC_B_B_REG_END                      0x023d406c
+#define BCHP_WOD_INTR_LOC_A2_B_REG_START                   0x023d4080
+#define BCHP_WOD_INTR_LOC_A2_B_REG_END                     0x023d40ac
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_B_REG_START             0x023d8000
+#define BCHP_WOD_TABLE_FFT_WIN_TAP_B_REG_END               0x023d8ffc
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_B_REG_START              0x023d9000
+#define BCHP_WOD_TABLE_PP_ACQ_MEM_B_REG_END                0x023d9ffc
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_B_REG_START       0x023da000
+#define BCHP_WOD_TABLE_CTYPE_ACTIVE_CARR_B_REG_END         0x023da3fc
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_B_REG_START          0x023da400
+#define BCHP_WOD_TABLE_CTYPE_CP_INDEX_B_REG_END            0x023da4fc
+#define BCHP_WOD_TABLE_PP_CP_INDEX_B_REG_START             0x023da500
+#define BCHP_WOD_TABLE_PP_CP_INDEX_B_REG_END               0x023da5fc
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_B_REG_START            0x023da600
+#define BCHP_WOD_TABLE_GI_DFT_PHASE_B_REG_END              0x023da69c
+#define BCHP_WOD_TABLE_FAVG_COEF_B_REG_START               0x023da6c0
+#define BCHP_WOD_TABLE_FAVG_COEF_B_REG_END                 0x023da6dc
+#define BCHP_WOD_DMEM0_B_REG_START                         0x023e0000
+#define BCHP_WOD_DMEM0_B_REG_END                           0x023e7ffc
+#define BCHP_WOD_DMEM1_B_REG_START                         0x023e8000
+#define BCHP_WOD_DMEM1_B_REG_END                           0x023efffc
+#define BCHP_WOD_DMEM2_B_REG_START                         0x023f0000
+#define BCHP_WOD_DMEM2_B_REG_END                           0x023f7ffc
+#define BCHP_WOD_DMEM3_B_REG_START                         0x023f8000
+#define BCHP_WOD_DMEM3_B_REG_END                           0x023ffffc
+#define BCHP_BaseReserved_EMC_REG_START                    0x03600000
+#define BCHP_BaseReserved_EMC_REG_END                      0x03600000
+#define BCHP_Control_EMC_REG_START                         0x03601000
+#define BCHP_Control_EMC_REG_END                           0x036010fc
+#define BCHP_OutgoingMessageFIFO_EMC_REG_START             0x03601100
+#define BCHP_OutgoingMessageFIFO_EMC_REG_END               0x0360117c
+#define BCHP_IncomingMessageFIFO_EMC_REG_START             0x03601200
+#define BCHP_IncomingMessageFIFO_EMC_REG_END               0x0360127c
+#define BCHP_DMA0_EMC_REG_START                            0x03601300
+#define BCHP_DMA0_EMC_REG_END                              0x0360131c
+#define BCHP_DMA1_EMC_REG_START                            0x03601320
+#define BCHP_DMA1_EMC_REG_END                              0x0360133c
+#define BCHP_DMAHI0_EMC_REG_START                          0x03601340
+#define BCHP_DMAHI0_EMC_REG_END                            0x0360134c
+#define BCHP_DMAHI1_EMC_REG_START                          0x03601350
+#define BCHP_DMAHI1_EMC_REG_END                            0x0360135c
+#define BCHP_Token_EMC_REG_START                           0x03601400
+#define BCHP_Token_EMC_REG_END                             0x03601420
+#define BCHP_PerfPower_EMC_REG_START                       0x03601600
+#define BCHP_PerfPower_EMC_REG_END                         0x03601640
+#define BCHP_MessageID_EMC_REG_START                       0x03601700
+#define BCHP_MessageID_EMC_REG_END                         0x0360177c
+#define BCHP_HWCounters_EMC_REG_START                      0x03601900
+#define BCHP_HWCounters_EMC_REG_END                        0x03601944
+#define BCHP_DQM_0_31_EMC_REG_START                        0x03601c00
+#define BCHP_DQM_0_31_EMC_REG_END                          0x03601c48
+#define BCHP_DQM_32_63_EMC_REG_START                       0x03601d00
+#define BCHP_DQM_32_63_EMC_REG_END                         0x03601d48
+#define BCHP_QUEUE_TIMER_EMC_REG_START                     0x03602000
+#define BCHP_QUEUE_TIMER_EMC_REG_END                       0x036021fc
+#define BCHP_QUEUE_STATUS_0_31_EMC_REG_START               0x03602800
+#define BCHP_QUEUE_STATUS_0_31_EMC_REG_END                 0x0360287c
+#define BCHP_QUEUE_STATUS_32_63_EMC_REG_START              0x03602900
+#define BCHP_QUEUE_STATUS_32_63_EMC_REG_END                0x0360297c
+#define BCHP_QUEUE_MIB_0_31_EMC_REG_START                  0x03603000
+#define BCHP_QUEUE_MIB_0_31_EMC_REG_END                    0x0360317c
+#define BCHP_QUEUE_MIB_32_63_EMC_REG_START                 0x03603200
+#define BCHP_QUEUE_MIB_32_63_EMC_REG_END                   0x0360337c
+#define BCHP_QUEUE_0_CNTRL_EMC_REG_START                   0x03604000
+#define BCHP_QUEUE_0_CNTRL_EMC_REG_END                     0x0360400c
+#define BCHP_QUEUE_1_CNTRL_EMC_REG_START                   0x03604010
+#define BCHP_QUEUE_1_CNTRL_EMC_REG_END                     0x0360401c
+#define BCHP_QUEUE_2_CNTRL_EMC_REG_START                   0x03604020
+#define BCHP_QUEUE_2_CNTRL_EMC_REG_END                     0x0360402c
+#define BCHP_QUEUE_3_CNTRL_EMC_REG_START                   0x03604030
+#define BCHP_QUEUE_3_CNTRL_EMC_REG_END                     0x0360403c
+#define BCHP_QUEUE_4_CNTRL_EMC_REG_START                   0x03604040
+#define BCHP_QUEUE_4_CNTRL_EMC_REG_END                     0x0360404c
+#define BCHP_QUEUE_5_CNTRL_EMC_REG_START                   0x03604050
+#define BCHP_QUEUE_5_CNTRL_EMC_REG_END                     0x0360405c
+#define BCHP_QUEUE_6_CNTRL_EMC_REG_START                   0x03604060
+#define BCHP_QUEUE_6_CNTRL_EMC_REG_END                     0x0360406c
+#define BCHP_QUEUE_7_CNTRL_EMC_REG_START                   0x03604070
+#define BCHP_QUEUE_7_CNTRL_EMC_REG_END                     0x0360407c
+#define BCHP_QUEUE_8_CNTRL_EMC_REG_START                   0x03604080
+#define BCHP_QUEUE_8_CNTRL_EMC_REG_END                     0x0360408c
+#define BCHP_QUEUE_9_CNTRL_EMC_REG_START                   0x03604090
+#define BCHP_QUEUE_9_CNTRL_EMC_REG_END                     0x0360409c
+#define BCHP_QUEUE_10_CNTRL_EMC_REG_START                  0x036040a0
+#define BCHP_QUEUE_10_CNTRL_EMC_REG_END                    0x036040ac
+#define BCHP_QUEUE_11_CNTRL_EMC_REG_START                  0x036040b0
+#define BCHP_QUEUE_11_CNTRL_EMC_REG_END                    0x036040bc
+#define BCHP_QUEUE_12_CNTRL_EMC_REG_START                  0x036040c0
+#define BCHP_QUEUE_12_CNTRL_EMC_REG_END                    0x036040cc
+#define BCHP_QUEUE_13_CNTRL_EMC_REG_START                  0x036040d0
+#define BCHP_QUEUE_13_CNTRL_EMC_REG_END                    0x036040dc
+#define BCHP_QUEUE_14_CNTRL_EMC_REG_START                  0x036040e0
+#define BCHP_QUEUE_14_CNTRL_EMC_REG_END                    0x036040ec
+#define BCHP_QUEUE_15_CNTRL_EMC_REG_START                  0x036040f0
+#define BCHP_QUEUE_15_CNTRL_EMC_REG_END                    0x036040fc
+#define BCHP_QUEUE_16_CNTRL_EMC_REG_START                  0x03604100
+#define BCHP_QUEUE_16_CNTRL_EMC_REG_END                    0x0360410c
+#define BCHP_QUEUE_17_CNTRL_EMC_REG_START                  0x03604110
+#define BCHP_QUEUE_17_CNTRL_EMC_REG_END                    0x0360411c
+#define BCHP_QUEUE_18_CNTRL_EMC_REG_START                  0x03604120
+#define BCHP_QUEUE_18_CNTRL_EMC_REG_END                    0x0360412c
+#define BCHP_QUEUE_19_CNTRL_EMC_REG_START                  0x03604130
+#define BCHP_QUEUE_19_CNTRL_EMC_REG_END                    0x0360413c
+#define BCHP_QUEUE_20_CNTRL_EMC_REG_START                  0x03604140
+#define BCHP_QUEUE_20_CNTRL_EMC_REG_END                    0x0360414c
+#define BCHP_QUEUE_21_CNTRL_EMC_REG_START                  0x03604150
+#define BCHP_QUEUE_21_CNTRL_EMC_REG_END                    0x0360415c
+#define BCHP_QUEUE_22_CNTRL_EMC_REG_START                  0x03604160
+#define BCHP_QUEUE_22_CNTRL_EMC_REG_END                    0x0360416c
+#define BCHP_QUEUE_23_CNTRL_EMC_REG_START                  0x03604170
+#define BCHP_QUEUE_23_CNTRL_EMC_REG_END                    0x0360417c
+#define BCHP_QUEUE_24_CNTRL_EMC_REG_START                  0x03604180
+#define BCHP_QUEUE_24_CNTRL_EMC_REG_END                    0x0360418c
+#define BCHP_QUEUE_25_CNTRL_EMC_REG_START                  0x03604190
+#define BCHP_QUEUE_25_CNTRL_EMC_REG_END                    0x0360419c
+#define BCHP_QUEUE_26_CNTRL_EMC_REG_START                  0x036041a0
+#define BCHP_QUEUE_26_CNTRL_EMC_REG_END                    0x036041ac
+#define BCHP_QUEUE_27_CNTRL_EMC_REG_START                  0x036041b0
+#define BCHP_QUEUE_27_CNTRL_EMC_REG_END                    0x036041bc
+#define BCHP_QUEUE_28_CNTRL_EMC_REG_START                  0x036041c0
+#define BCHP_QUEUE_28_CNTRL_EMC_REG_END                    0x036041cc
+#define BCHP_QUEUE_29_CNTRL_EMC_REG_START                  0x036041d0
+#define BCHP_QUEUE_29_CNTRL_EMC_REG_END                    0x036041dc
+#define BCHP_QUEUE_30_CNTRL_EMC_REG_START                  0x036041e0
+#define BCHP_QUEUE_30_CNTRL_EMC_REG_END                    0x036041ec
+#define BCHP_QUEUE_31_CNTRL_EMC_REG_START                  0x036041f0
+#define BCHP_QUEUE_31_CNTRL_EMC_REG_END                    0x036041fc
+#define BCHP_QUEUE_32_CNTRL_EMC_REG_START                  0x03604200
+#define BCHP_QUEUE_32_CNTRL_EMC_REG_END                    0x0360420c
+#define BCHP_QUEUE_33_CNTRL_EMC_REG_START                  0x03604210
+#define BCHP_QUEUE_33_CNTRL_EMC_REG_END                    0x0360421c
+#define BCHP_QUEUE_34_CNTRL_EMC_REG_START                  0x03604220
+#define BCHP_QUEUE_34_CNTRL_EMC_REG_END                    0x0360422c
+#define BCHP_QUEUE_35_CNTRL_EMC_REG_START                  0x03604230
+#define BCHP_QUEUE_35_CNTRL_EMC_REG_END                    0x0360423c
+#define BCHP_QUEUE_36_CNTRL_EMC_REG_START                  0x03604240
+#define BCHP_QUEUE_36_CNTRL_EMC_REG_END                    0x0360424c
+#define BCHP_QUEUE_37_CNTRL_EMC_REG_START                  0x03604250
+#define BCHP_QUEUE_37_CNTRL_EMC_REG_END                    0x0360425c
+#define BCHP_QUEUE_38_CNTRL_EMC_REG_START                  0x03604260
+#define BCHP_QUEUE_38_CNTRL_EMC_REG_END                    0x0360426c
+#define BCHP_QUEUE_39_CNTRL_EMC_REG_START                  0x03604270
+#define BCHP_QUEUE_39_CNTRL_EMC_REG_END                    0x0360427c
+#define BCHP_QUEUE_40_CNTRL_EMC_REG_START                  0x03604280
+#define BCHP_QUEUE_40_CNTRL_EMC_REG_END                    0x0360428c
+#define BCHP_QUEUE_41_CNTRL_EMC_REG_START                  0x03604290
+#define BCHP_QUEUE_41_CNTRL_EMC_REG_END                    0x0360429c
+#define BCHP_QUEUE_42_CNTRL_EMC_REG_START                  0x036042a0
+#define BCHP_QUEUE_42_CNTRL_EMC_REG_END                    0x036042ac
+#define BCHP_QUEUE_43_CNTRL_EMC_REG_START                  0x036042b0
+#define BCHP_QUEUE_43_CNTRL_EMC_REG_END                    0x036042bc
+#define BCHP_QUEUE_44_CNTRL_EMC_REG_START                  0x036042c0
+#define BCHP_QUEUE_44_CNTRL_EMC_REG_END                    0x036042cc
+#define BCHP_QUEUE_45_CNTRL_EMC_REG_START                  0x036042d0
+#define BCHP_QUEUE_45_CNTRL_EMC_REG_END                    0x036042dc
+#define BCHP_QUEUE_46_CNTRL_EMC_REG_START                  0x036042e0
+#define BCHP_QUEUE_46_CNTRL_EMC_REG_END                    0x036042ec
+#define BCHP_QUEUE_47_CNTRL_EMC_REG_START                  0x036042f0
+#define BCHP_QUEUE_47_CNTRL_EMC_REG_END                    0x036042fc
+#define BCHP_QUEUE_48_CNTRL_EMC_REG_START                  0x03604300
+#define BCHP_QUEUE_48_CNTRL_EMC_REG_END                    0x0360430c
+#define BCHP_QUEUE_49_CNTRL_EMC_REG_START                  0x03604310
+#define BCHP_QUEUE_49_CNTRL_EMC_REG_END                    0x0360431c
+#define BCHP_QUEUE_50_CNTRL_EMC_REG_START                  0x03604320
+#define BCHP_QUEUE_50_CNTRL_EMC_REG_END                    0x0360432c
+#define BCHP_QUEUE_51_CNTRL_EMC_REG_START                  0x03604330
+#define BCHP_QUEUE_51_CNTRL_EMC_REG_END                    0x0360433c
+#define BCHP_QUEUE_52_CNTRL_EMC_REG_START                  0x03604340
+#define BCHP_QUEUE_52_CNTRL_EMC_REG_END                    0x0360434c
+#define BCHP_QUEUE_53_CNTRL_EMC_REG_START                  0x03604350
+#define BCHP_QUEUE_53_CNTRL_EMC_REG_END                    0x0360435c
+#define BCHP_QUEUE_54_CNTRL_EMC_REG_START                  0x03604360
+#define BCHP_QUEUE_54_CNTRL_EMC_REG_END                    0x0360436c
+#define BCHP_QUEUE_55_CNTRL_EMC_REG_START                  0x03604370
+#define BCHP_QUEUE_55_CNTRL_EMC_REG_END                    0x0360437c
+#define BCHP_QUEUE_56_CNTRL_EMC_REG_START                  0x03604380
+#define BCHP_QUEUE_56_CNTRL_EMC_REG_END                    0x0360438c
+#define BCHP_QUEUE_57_CNTRL_EMC_REG_START                  0x03604390
+#define BCHP_QUEUE_57_CNTRL_EMC_REG_END                    0x0360439c
+#define BCHP_QUEUE_58_CNTRL_EMC_REG_START                  0x036043a0
+#define BCHP_QUEUE_58_CNTRL_EMC_REG_END                    0x036043ac
+#define BCHP_QUEUE_59_CNTRL_EMC_REG_START                  0x036043b0
+#define BCHP_QUEUE_59_CNTRL_EMC_REG_END                    0x036043bc
+#define BCHP_QUEUE_60_CNTRL_EMC_REG_START                  0x036043c0
+#define BCHP_QUEUE_60_CNTRL_EMC_REG_END                    0x036043cc
+#define BCHP_QUEUE_61_CNTRL_EMC_REG_START                  0x036043d0
+#define BCHP_QUEUE_61_CNTRL_EMC_REG_END                    0x036043dc
+#define BCHP_QUEUE_62_CNTRL_EMC_REG_START                  0x036043e0
+#define BCHP_QUEUE_62_CNTRL_EMC_REG_END                    0x036043ec
+#define BCHP_QUEUE_63_CNTRL_EMC_REG_START                  0x036043f0
+#define BCHP_QUEUE_63_CNTRL_EMC_REG_END                    0x036043fc
+#define BCHP_QUEUE_0_DATA_EMC_REG_START                    0x03605000
+#define BCHP_QUEUE_0_DATA_EMC_REG_END                      0x0360500c
+#define BCHP_QUEUE_1_DATA_EMC_REG_START                    0x03605010
+#define BCHP_QUEUE_1_DATA_EMC_REG_END                      0x0360501c
+#define BCHP_QUEUE_2_DATA_EMC_REG_START                    0x03605020
+#define BCHP_QUEUE_2_DATA_EMC_REG_END                      0x0360502c
+#define BCHP_QUEUE_3_DATA_EMC_REG_START                    0x03605030
+#define BCHP_QUEUE_3_DATA_EMC_REG_END                      0x0360503c
+#define BCHP_QUEUE_4_DATA_EMC_REG_START                    0x03605040
+#define BCHP_QUEUE_4_DATA_EMC_REG_END                      0x0360504c
+#define BCHP_QUEUE_5_DATA_EMC_REG_START                    0x03605050
+#define BCHP_QUEUE_5_DATA_EMC_REG_END                      0x0360505c
+#define BCHP_QUEUE_6_DATA_EMC_REG_START                    0x03605060
+#define BCHP_QUEUE_6_DATA_EMC_REG_END                      0x0360506c
+#define BCHP_QUEUE_7_DATA_EMC_REG_START                    0x03605070
+#define BCHP_QUEUE_7_DATA_EMC_REG_END                      0x0360507c
+#define BCHP_QUEUE_8_DATA_EMC_REG_START                    0x03605080
+#define BCHP_QUEUE_8_DATA_EMC_REG_END                      0x0360508c
+#define BCHP_QUEUE_9_DATA_EMC_REG_START                    0x03605090
+#define BCHP_QUEUE_9_DATA_EMC_REG_END                      0x0360509c
+#define BCHP_QUEUE_10_DATA_EMC_REG_START                   0x036050a0
+#define BCHP_QUEUE_10_DATA_EMC_REG_END                     0x036050ac
+#define BCHP_QUEUE_11_DATA_EMC_REG_START                   0x036050b0
+#define BCHP_QUEUE_11_DATA_EMC_REG_END                     0x036050bc
+#define BCHP_QUEUE_12_DATA_EMC_REG_START                   0x036050c0
+#define BCHP_QUEUE_12_DATA_EMC_REG_END                     0x036050cc
+#define BCHP_QUEUE_13_DATA_EMC_REG_START                   0x036050d0
+#define BCHP_QUEUE_13_DATA_EMC_REG_END                     0x036050dc
+#define BCHP_QUEUE_14_DATA_EMC_REG_START                   0x036050e0
+#define BCHP_QUEUE_14_DATA_EMC_REG_END                     0x036050ec
+#define BCHP_QUEUE_15_DATA_EMC_REG_START                   0x036050f0
+#define BCHP_QUEUE_15_DATA_EMC_REG_END                     0x036050fc
+#define BCHP_QUEUE_16_DATA_EMC_REG_START                   0x03605100
+#define BCHP_QUEUE_16_DATA_EMC_REG_END                     0x0360510c
+#define BCHP_QUEUE_17_DATA_EMC_REG_START                   0x03605110
+#define BCHP_QUEUE_17_DATA_EMC_REG_END                     0x0360511c
+#define BCHP_QUEUE_18_DATA_EMC_REG_START                   0x03605120
+#define BCHP_QUEUE_18_DATA_EMC_REG_END                     0x0360512c
+#define BCHP_QUEUE_19_DATA_EMC_REG_START                   0x03605130
+#define BCHP_QUEUE_19_DATA_EMC_REG_END                     0x0360513c
+#define BCHP_QUEUE_20_DATA_EMC_REG_START                   0x03605140
+#define BCHP_QUEUE_20_DATA_EMC_REG_END                     0x0360514c
+#define BCHP_QUEUE_21_DATA_EMC_REG_START                   0x03605150
+#define BCHP_QUEUE_21_DATA_EMC_REG_END                     0x0360515c
+#define BCHP_QUEUE_22_DATA_EMC_REG_START                   0x03605160
+#define BCHP_QUEUE_22_DATA_EMC_REG_END                     0x0360516c
+#define BCHP_QUEUE_23_DATA_EMC_REG_START                   0x03605170
+#define BCHP_QUEUE_23_DATA_EMC_REG_END                     0x0360517c
+#define BCHP_QUEUE_24_DATA_EMC_REG_START                   0x03605180
+#define BCHP_QUEUE_24_DATA_EMC_REG_END                     0x0360518c
+#define BCHP_QUEUE_25_DATA_EMC_REG_START                   0x03605190
+#define BCHP_QUEUE_25_DATA_EMC_REG_END                     0x0360519c
+#define BCHP_QUEUE_26_DATA_EMC_REG_START                   0x036051a0
+#define BCHP_QUEUE_26_DATA_EMC_REG_END                     0x036051ac
+#define BCHP_QUEUE_27_DATA_EMC_REG_START                   0x036051b0
+#define BCHP_QUEUE_27_DATA_EMC_REG_END                     0x036051bc
+#define BCHP_QUEUE_28_DATA_EMC_REG_START                   0x036051c0
+#define BCHP_QUEUE_28_DATA_EMC_REG_END                     0x036051cc
+#define BCHP_QUEUE_29_DATA_EMC_REG_START                   0x036051d0
+#define BCHP_QUEUE_29_DATA_EMC_REG_END                     0x036051dc
+#define BCHP_QUEUE_30_DATA_EMC_REG_START                   0x036051e0
+#define BCHP_QUEUE_30_DATA_EMC_REG_END                     0x036051ec
+#define BCHP_QUEUE_31_DATA_EMC_REG_START                   0x036051f0
+#define BCHP_QUEUE_31_DATA_EMC_REG_END                     0x036051fc
+#define BCHP_QUEUE_32_DATA_EMC_REG_START                   0x03605200
+#define BCHP_QUEUE_32_DATA_EMC_REG_END                     0x0360520c
+#define BCHP_QUEUE_33_DATA_EMC_REG_START                   0x03605210
+#define BCHP_QUEUE_33_DATA_EMC_REG_END                     0x0360521c
+#define BCHP_QUEUE_34_DATA_EMC_REG_START                   0x03605220
+#define BCHP_QUEUE_34_DATA_EMC_REG_END                     0x0360522c
+#define BCHP_QUEUE_35_DATA_EMC_REG_START                   0x03605230
+#define BCHP_QUEUE_35_DATA_EMC_REG_END                     0x0360523c
+#define BCHP_QUEUE_36_DATA_EMC_REG_START                   0x03605240
+#define BCHP_QUEUE_36_DATA_EMC_REG_END                     0x0360524c
+#define BCHP_QUEUE_37_DATA_EMC_REG_START                   0x03605250
+#define BCHP_QUEUE_37_DATA_EMC_REG_END                     0x0360525c
+#define BCHP_QUEUE_38_DATA_EMC_REG_START                   0x03605260
+#define BCHP_QUEUE_38_DATA_EMC_REG_END                     0x0360526c
+#define BCHP_QUEUE_39_DATA_EMC_REG_START                   0x03605270
+#define BCHP_QUEUE_39_DATA_EMC_REG_END                     0x0360527c
+#define BCHP_QUEUE_40_DATA_EMC_REG_START                   0x03605280
+#define BCHP_QUEUE_40_DATA_EMC_REG_END                     0x0360528c
+#define BCHP_QUEUE_41_DATA_EMC_REG_START                   0x03605290
+#define BCHP_QUEUE_41_DATA_EMC_REG_END                     0x0360529c
+#define BCHP_QUEUE_42_DATA_EMC_REG_START                   0x036052a0
+#define BCHP_QUEUE_42_DATA_EMC_REG_END                     0x036052ac
+#define BCHP_QUEUE_43_DATA_EMC_REG_START                   0x036052b0
+#define BCHP_QUEUE_43_DATA_EMC_REG_END                     0x036052bc
+#define BCHP_QUEUE_44_DATA_EMC_REG_START                   0x036052c0
+#define BCHP_QUEUE_44_DATA_EMC_REG_END                     0x036052cc
+#define BCHP_QUEUE_45_DATA_EMC_REG_START                   0x036052d0
+#define BCHP_QUEUE_45_DATA_EMC_REG_END                     0x036052dc
+#define BCHP_QUEUE_46_DATA_EMC_REG_START                   0x036052e0
+#define BCHP_QUEUE_46_DATA_EMC_REG_END                     0x036052ec
+#define BCHP_QUEUE_47_DATA_EMC_REG_START                   0x036052f0
+#define BCHP_QUEUE_47_DATA_EMC_REG_END                     0x036052fc
+#define BCHP_QUEUE_48_DATA_EMC_REG_START                   0x03605300
+#define BCHP_QUEUE_48_DATA_EMC_REG_END                     0x0360530c
+#define BCHP_QUEUE_49_DATA_EMC_REG_START                   0x03605310
+#define BCHP_QUEUE_49_DATA_EMC_REG_END                     0x0360531c
+#define BCHP_QUEUE_50_DATA_EMC_REG_START                   0x03605320
+#define BCHP_QUEUE_50_DATA_EMC_REG_END                     0x0360532c
+#define BCHP_QUEUE_51_DATA_EMC_REG_START                   0x03605330
+#define BCHP_QUEUE_51_DATA_EMC_REG_END                     0x0360533c
+#define BCHP_QUEUE_52_DATA_EMC_REG_START                   0x03605340
+#define BCHP_QUEUE_52_DATA_EMC_REG_END                     0x0360534c
+#define BCHP_QUEUE_53_DATA_EMC_REG_START                   0x03605350
+#define BCHP_QUEUE_53_DATA_EMC_REG_END                     0x0360535c
+#define BCHP_QUEUE_54_DATA_EMC_REG_START                   0x03605360
+#define BCHP_QUEUE_54_DATA_EMC_REG_END                     0x0360536c
+#define BCHP_QUEUE_55_DATA_EMC_REG_START                   0x03605370
+#define BCHP_QUEUE_55_DATA_EMC_REG_END                     0x0360537c
+#define BCHP_QUEUE_56_DATA_EMC_REG_START                   0x03605380
+#define BCHP_QUEUE_56_DATA_EMC_REG_END                     0x0360538c
+#define BCHP_QUEUE_57_DATA_EMC_REG_START                   0x03605390
+#define BCHP_QUEUE_57_DATA_EMC_REG_END                     0x0360539c
+#define BCHP_QUEUE_58_DATA_EMC_REG_START                   0x036053a0
+#define BCHP_QUEUE_58_DATA_EMC_REG_END                     0x036053ac
+#define BCHP_QUEUE_59_DATA_EMC_REG_START                   0x036053b0
+#define BCHP_QUEUE_59_DATA_EMC_REG_END                     0x036053bc
+#define BCHP_QUEUE_60_DATA_EMC_REG_START                   0x036053c0
+#define BCHP_QUEUE_60_DATA_EMC_REG_END                     0x036053cc
+#define BCHP_QUEUE_61_DATA_EMC_REG_START                   0x036053d0
+#define BCHP_QUEUE_61_DATA_EMC_REG_END                     0x036053dc
+#define BCHP_QUEUE_62_DATA_EMC_REG_START                   0x036053e0
+#define BCHP_QUEUE_62_DATA_EMC_REG_END                     0x036053ec
+#define BCHP_QUEUE_63_DATA_EMC_REG_START                   0x036053f0
+#define BCHP_QUEUE_63_DATA_EMC_REG_END                     0x036053fc
+#define BCHP_OL_DQM_EMC_REG_START                          0x03606c00
+#define BCHP_OL_DQM_EMC_REG_END                            0x03606c5c
+#define BCHP_OL_QUEUE_STATUS_EMC_REG_START                 0x03607400
+#define BCHP_OL_QUEUE_STATUS_EMC_REG_END                   0x0360747c
+#define BCHP_OL_QUEUE_0_DEBUG_EMC_REG_START                0x03607c00
+#define BCHP_OL_QUEUE_0_DEBUG_EMC_REG_END                  0x03607c04
+#define BCHP_OL_QUEUE_1_DEBUG_EMC_REG_START                0x03607c08
+#define BCHP_OL_QUEUE_1_DEBUG_EMC_REG_END                  0x03607c0c
+#define BCHP_OL_QUEUE_2_DEBUG_EMC_REG_START                0x03607c10
+#define BCHP_OL_QUEUE_2_DEBUG_EMC_REG_END                  0x03607c14
+#define BCHP_OL_QUEUE_3_DEBUG_EMC_REG_START                0x03607c18
+#define BCHP_OL_QUEUE_3_DEBUG_EMC_REG_END                  0x03607c1c
+#define BCHP_OL_QUEUE_4_DEBUG_EMC_REG_START                0x03607c20
+#define BCHP_OL_QUEUE_4_DEBUG_EMC_REG_END                  0x03607c24
+#define BCHP_OL_QUEUE_5_DEBUG_EMC_REG_START                0x03607c28
+#define BCHP_OL_QUEUE_5_DEBUG_EMC_REG_END                  0x03607c2c
+#define BCHP_OL_QUEUE_6_DEBUG_EMC_REG_START                0x03607c30
+#define BCHP_OL_QUEUE_6_DEBUG_EMC_REG_END                  0x03607c34
+#define BCHP_OL_QUEUE_7_DEBUG_EMC_REG_START                0x03607c38
+#define BCHP_OL_QUEUE_7_DEBUG_EMC_REG_END                  0x03607c3c
+#define BCHP_OL_QUEUE_8_DEBUG_EMC_REG_START                0x03607c40
+#define BCHP_OL_QUEUE_8_DEBUG_EMC_REG_END                  0x03607c44
+#define BCHP_OL_QUEUE_9_DEBUG_EMC_REG_START                0x03607c48
+#define BCHP_OL_QUEUE_9_DEBUG_EMC_REG_END                  0x03607c4c
+#define BCHP_OL_QUEUE_10_DEBUG_EMC_REG_START               0x03607c50
+#define BCHP_OL_QUEUE_10_DEBUG_EMC_REG_END                 0x03607c54
+#define BCHP_OL_QUEUE_11_DEBUG_EMC_REG_START               0x03607c58
+#define BCHP_OL_QUEUE_11_DEBUG_EMC_REG_END                 0x03607c5c
+#define BCHP_OL_QUEUE_12_DEBUG_EMC_REG_START               0x03607c60
+#define BCHP_OL_QUEUE_12_DEBUG_EMC_REG_END                 0x03607c64
+#define BCHP_OL_QUEUE_13_DEBUG_EMC_REG_START               0x03607c68
+#define BCHP_OL_QUEUE_13_DEBUG_EMC_REG_END                 0x03607c6c
+#define BCHP_OL_QUEUE_14_DEBUG_EMC_REG_START               0x03607c70
+#define BCHP_OL_QUEUE_14_DEBUG_EMC_REG_END                 0x03607c74
+#define BCHP_OL_QUEUE_15_DEBUG_EMC_REG_START               0x03607c78
+#define BCHP_OL_QUEUE_15_DEBUG_EMC_REG_END                 0x03607c7c
+#define BCHP_OL_QUEUE_16_DEBUG_EMC_REG_START               0x03607c80
+#define BCHP_OL_QUEUE_16_DEBUG_EMC_REG_END                 0x03607c84
+#define BCHP_OL_QUEUE_17_DEBUG_EMC_REG_START               0x03607c88
+#define BCHP_OL_QUEUE_17_DEBUG_EMC_REG_END                 0x03607c8c
+#define BCHP_OL_QUEUE_18_DEBUG_EMC_REG_START               0x03607c90
+#define BCHP_OL_QUEUE_18_DEBUG_EMC_REG_END                 0x03607c94
+#define BCHP_OL_QUEUE_19_DEBUG_EMC_REG_START               0x03607c98
+#define BCHP_OL_QUEUE_19_DEBUG_EMC_REG_END                 0x03607c9c
+#define BCHP_OL_QUEUE_20_DEBUG_EMC_REG_START               0x03607ca0
+#define BCHP_OL_QUEUE_20_DEBUG_EMC_REG_END                 0x03607ca4
+#define BCHP_OL_QUEUE_21_DEBUG_EMC_REG_START               0x03607ca8
+#define BCHP_OL_QUEUE_21_DEBUG_EMC_REG_END                 0x03607cac
+#define BCHP_OL_QUEUE_22_DEBUG_EMC_REG_START               0x03607cb0
+#define BCHP_OL_QUEUE_22_DEBUG_EMC_REG_END                 0x03607cb4
+#define BCHP_OL_QUEUE_23_DEBUG_EMC_REG_START               0x03607cb8
+#define BCHP_OL_QUEUE_23_DEBUG_EMC_REG_END                 0x03607cbc
+#define BCHP_OL_QUEUE_24_DEBUG_EMC_REG_START               0x03607cc0
+#define BCHP_OL_QUEUE_24_DEBUG_EMC_REG_END                 0x03607cc4
+#define BCHP_OL_QUEUE_25_DEBUG_EMC_REG_START               0x03607cc8
+#define BCHP_OL_QUEUE_25_DEBUG_EMC_REG_END                 0x03607ccc
+#define BCHP_OL_QUEUE_26_DEBUG_EMC_REG_START               0x03607cd0
+#define BCHP_OL_QUEUE_26_DEBUG_EMC_REG_END                 0x03607cd4
+#define BCHP_OL_QUEUE_27_DEBUG_EMC_REG_START               0x03607cd8
+#define BCHP_OL_QUEUE_27_DEBUG_EMC_REG_END                 0x03607cdc
+#define BCHP_OL_QUEUE_28_DEBUG_EMC_REG_START               0x03607ce0
+#define BCHP_OL_QUEUE_28_DEBUG_EMC_REG_END                 0x03607ce4
+#define BCHP_OL_QUEUE_29_DEBUG_EMC_REG_START               0x03607ce8
+#define BCHP_OL_QUEUE_29_DEBUG_EMC_REG_END                 0x03607cec
+#define BCHP_OL_QUEUE_30_DEBUG_EMC_REG_START               0x03607cf0
+#define BCHP_OL_QUEUE_30_DEBUG_EMC_REG_END                 0x03607cf4
+#define BCHP_OL_QUEUE_31_DEBUG_EMC_REG_START               0x03607cf8
+#define BCHP_OL_QUEUE_31_DEBUG_EMC_REG_END                 0x03607cfc
+#define BCHP_OL_QUEUE_0_CNTRL_EMC_REG_START                0x03608000
+#define BCHP_OL_QUEUE_0_CNTRL_EMC_REG_END                  0x0360801c
+#define BCHP_OL_QUEUE_1_CNTRL_EMC_REG_START                0x03608020
+#define BCHP_OL_QUEUE_1_CNTRL_EMC_REG_END                  0x0360803c
+#define BCHP_OL_QUEUE_2_CNTRL_EMC_REG_START                0x03608040
+#define BCHP_OL_QUEUE_2_CNTRL_EMC_REG_END                  0x0360805c
+#define BCHP_OL_QUEUE_3_CNTRL_EMC_REG_START                0x03608060
+#define BCHP_OL_QUEUE_3_CNTRL_EMC_REG_END                  0x0360807c
+#define BCHP_OL_QUEUE_4_CNTRL_EMC_REG_START                0x03608080
+#define BCHP_OL_QUEUE_4_CNTRL_EMC_REG_END                  0x0360809c
+#define BCHP_OL_QUEUE_5_CNTRL_EMC_REG_START                0x036080a0
+#define BCHP_OL_QUEUE_5_CNTRL_EMC_REG_END                  0x036080bc
+#define BCHP_OL_QUEUE_6_CNTRL_EMC_REG_START                0x036080c0
+#define BCHP_OL_QUEUE_6_CNTRL_EMC_REG_END                  0x036080dc
+#define BCHP_OL_QUEUE_7_CNTRL_EMC_REG_START                0x036080e0
+#define BCHP_OL_QUEUE_7_CNTRL_EMC_REG_END                  0x036080fc
+#define BCHP_OL_QUEUE_8_CNTRL_EMC_REG_START                0x03608100
+#define BCHP_OL_QUEUE_8_CNTRL_EMC_REG_END                  0x0360811c
+#define BCHP_OL_QUEUE_9_CNTRL_EMC_REG_START                0x03608120
+#define BCHP_OL_QUEUE_9_CNTRL_EMC_REG_END                  0x0360813c
+#define BCHP_OL_QUEUE_10_CNTRL_EMC_REG_START               0x03608140
+#define BCHP_OL_QUEUE_10_CNTRL_EMC_REG_END                 0x0360815c
+#define BCHP_OL_QUEUE_11_CNTRL_EMC_REG_START               0x03608160
+#define BCHP_OL_QUEUE_11_CNTRL_EMC_REG_END                 0x0360817c
+#define BCHP_OL_QUEUE_12_CNTRL_EMC_REG_START               0x03608180
+#define BCHP_OL_QUEUE_12_CNTRL_EMC_REG_END                 0x0360819c
+#define BCHP_OL_QUEUE_13_CNTRL_EMC_REG_START               0x036081a0
+#define BCHP_OL_QUEUE_13_CNTRL_EMC_REG_END                 0x036081bc
+#define BCHP_OL_QUEUE_14_CNTRL_EMC_REG_START               0x036081c0
+#define BCHP_OL_QUEUE_14_CNTRL_EMC_REG_END                 0x036081dc
+#define BCHP_OL_QUEUE_15_CNTRL_EMC_REG_START               0x036081e0
+#define BCHP_OL_QUEUE_15_CNTRL_EMC_REG_END                 0x036081fc
+#define BCHP_OL_QUEUE_16_CNTRL_EMC_REG_START               0x03608200
+#define BCHP_OL_QUEUE_16_CNTRL_EMC_REG_END                 0x0360821c
+#define BCHP_OL_QUEUE_17_CNTRL_EMC_REG_START               0x03608220
+#define BCHP_OL_QUEUE_17_CNTRL_EMC_REG_END                 0x0360823c
+#define BCHP_OL_QUEUE_18_CNTRL_EMC_REG_START               0x03608240
+#define BCHP_OL_QUEUE_18_CNTRL_EMC_REG_END                 0x0360825c
+#define BCHP_OL_QUEUE_19_CNTRL_EMC_REG_START               0x03608260
+#define BCHP_OL_QUEUE_19_CNTRL_EMC_REG_END                 0x0360827c
+#define BCHP_OL_QUEUE_20_CNTRL_EMC_REG_START               0x03608280
+#define BCHP_OL_QUEUE_20_CNTRL_EMC_REG_END                 0x0360829c
+#define BCHP_OL_QUEUE_21_CNTRL_EMC_REG_START               0x036082a0
+#define BCHP_OL_QUEUE_21_CNTRL_EMC_REG_END                 0x036082bc
+#define BCHP_OL_QUEUE_22_CNTRL_EMC_REG_START               0x036082c0
+#define BCHP_OL_QUEUE_22_CNTRL_EMC_REG_END                 0x036082dc
+#define BCHP_OL_QUEUE_23_CNTRL_EMC_REG_START               0x036082e0
+#define BCHP_OL_QUEUE_23_CNTRL_EMC_REG_END                 0x036082fc
+#define BCHP_OL_QUEUE_24_CNTRL_EMC_REG_START               0x03608300
+#define BCHP_OL_QUEUE_24_CNTRL_EMC_REG_END                 0x0360831c
+#define BCHP_OL_QUEUE_25_CNTRL_EMC_REG_START               0x03608320
+#define BCHP_OL_QUEUE_25_CNTRL_EMC_REG_END                 0x0360833c
+#define BCHP_OL_QUEUE_26_CNTRL_EMC_REG_START               0x03608340
+#define BCHP_OL_QUEUE_26_CNTRL_EMC_REG_END                 0x0360835c
+#define BCHP_OL_QUEUE_27_CNTRL_EMC_REG_START               0x03608360
+#define BCHP_OL_QUEUE_27_CNTRL_EMC_REG_END                 0x0360837c
+#define BCHP_OL_QUEUE_28_CNTRL_EMC_REG_START               0x03608380
+#define BCHP_OL_QUEUE_28_CNTRL_EMC_REG_END                 0x0360839c
+#define BCHP_OL_QUEUE_29_CNTRL_EMC_REG_START               0x036083a0
+#define BCHP_OL_QUEUE_29_CNTRL_EMC_REG_END                 0x036083bc
+#define BCHP_OL_QUEUE_30_CNTRL_EMC_REG_START               0x036083c0
+#define BCHP_OL_QUEUE_30_CNTRL_EMC_REG_END                 0x036083dc
+#define BCHP_OL_QUEUE_31_CNTRL_EMC_REG_START               0x036083e0
+#define BCHP_OL_QUEUE_31_CNTRL_EMC_REG_END                 0x036083fc
+#define BCHP_OL_QUEUE_0_DATA_EMC_REG_START                 0x03609000
+#define BCHP_OL_QUEUE_0_DATA_EMC_REG_END                   0x0360901c
+#define BCHP_OL_QUEUE_1_DATA_EMC_REG_START                 0x03609020
+#define BCHP_OL_QUEUE_1_DATA_EMC_REG_END                   0x0360903c
+#define BCHP_OL_QUEUE_2_DATA_EMC_REG_START                 0x03609040
+#define BCHP_OL_QUEUE_2_DATA_EMC_REG_END                   0x0360905c
+#define BCHP_OL_QUEUE_3_DATA_EMC_REG_START                 0x03609060
+#define BCHP_OL_QUEUE_3_DATA_EMC_REG_END                   0x0360907c
+#define BCHP_OL_QUEUE_4_DATA_EMC_REG_START                 0x03609080
+#define BCHP_OL_QUEUE_4_DATA_EMC_REG_END                   0x0360909c
+#define BCHP_OL_QUEUE_5_DATA_EMC_REG_START                 0x036090a0
+#define BCHP_OL_QUEUE_5_DATA_EMC_REG_END                   0x036090bc
+#define BCHP_OL_QUEUE_6_DATA_EMC_REG_START                 0x036090c0
+#define BCHP_OL_QUEUE_6_DATA_EMC_REG_END                   0x036090dc
+#define BCHP_OL_QUEUE_7_DATA_EMC_REG_START                 0x036090e0
+#define BCHP_OL_QUEUE_7_DATA_EMC_REG_END                   0x036090fc
+#define BCHP_OL_QUEUE_8_DATA_EMC_REG_START                 0x03609100
+#define BCHP_OL_QUEUE_8_DATA_EMC_REG_END                   0x0360911c
+#define BCHP_OL_QUEUE_9_DATA_EMC_REG_START                 0x03609120
+#define BCHP_OL_QUEUE_9_DATA_EMC_REG_END                   0x0360913c
+#define BCHP_OL_QUEUE_10_DATA_EMC_REG_START                0x03609140
+#define BCHP_OL_QUEUE_10_DATA_EMC_REG_END                  0x0360915c
+#define BCHP_OL_QUEUE_11_DATA_EMC_REG_START                0x03609160
+#define BCHP_OL_QUEUE_11_DATA_EMC_REG_END                  0x0360917c
+#define BCHP_OL_QUEUE_12_DATA_EMC_REG_START                0x03609180
+#define BCHP_OL_QUEUE_12_DATA_EMC_REG_END                  0x0360919c
+#define BCHP_OL_QUEUE_13_DATA_EMC_REG_START                0x036091a0
+#define BCHP_OL_QUEUE_13_DATA_EMC_REG_END                  0x036091bc
+#define BCHP_OL_QUEUE_14_DATA_EMC_REG_START                0x036091c0
+#define BCHP_OL_QUEUE_14_DATA_EMC_REG_END                  0x036091dc
+#define BCHP_OL_QUEUE_15_DATA_EMC_REG_START                0x036091e0
+#define BCHP_OL_QUEUE_15_DATA_EMC_REG_END                  0x036091fc
+#define BCHP_OL_QUEUE_16_DATA_EMC_REG_START                0x03609200
+#define BCHP_OL_QUEUE_16_DATA_EMC_REG_END                  0x0360921c
+#define BCHP_OL_QUEUE_17_DATA_EMC_REG_START                0x03609220
+#define BCHP_OL_QUEUE_17_DATA_EMC_REG_END                  0x0360923c
+#define BCHP_OL_QUEUE_18_DATA_EMC_REG_START                0x03609240
+#define BCHP_OL_QUEUE_18_DATA_EMC_REG_END                  0x0360925c
+#define BCHP_OL_QUEUE_19_DATA_EMC_REG_START                0x03609260
+#define BCHP_OL_QUEUE_19_DATA_EMC_REG_END                  0x0360927c
+#define BCHP_OL_QUEUE_20_DATA_EMC_REG_START                0x03609280
+#define BCHP_OL_QUEUE_20_DATA_EMC_REG_END                  0x0360929c
+#define BCHP_OL_QUEUE_21_DATA_EMC_REG_START                0x036092a0
+#define BCHP_OL_QUEUE_21_DATA_EMC_REG_END                  0x036092bc
+#define BCHP_OL_QUEUE_22_DATA_EMC_REG_START                0x036092c0
+#define BCHP_OL_QUEUE_22_DATA_EMC_REG_END                  0x036092dc
+#define BCHP_OL_QUEUE_23_DATA_EMC_REG_START                0x036092e0
+#define BCHP_OL_QUEUE_23_DATA_EMC_REG_END                  0x036092fc
+#define BCHP_OL_QUEUE_24_DATA_EMC_REG_START                0x03609300
+#define BCHP_OL_QUEUE_24_DATA_EMC_REG_END                  0x0360931c
+#define BCHP_OL_QUEUE_25_DATA_EMC_REG_START                0x03609320
+#define BCHP_OL_QUEUE_25_DATA_EMC_REG_END                  0x0360933c
+#define BCHP_OL_QUEUE_26_DATA_EMC_REG_START                0x03609340
+#define BCHP_OL_QUEUE_26_DATA_EMC_REG_END                  0x0360935c
+#define BCHP_OL_QUEUE_27_DATA_EMC_REG_START                0x03609360
+#define BCHP_OL_QUEUE_27_DATA_EMC_REG_END                  0x0360937c
+#define BCHP_OL_QUEUE_28_DATA_EMC_REG_START                0x03609380
+#define BCHP_OL_QUEUE_28_DATA_EMC_REG_END                  0x0360939c
+#define BCHP_OL_QUEUE_29_DATA_EMC_REG_START                0x036093a0
+#define BCHP_OL_QUEUE_29_DATA_EMC_REG_END                  0x036093bc
+#define BCHP_OL_QUEUE_30_DATA_EMC_REG_START                0x036093c0
+#define BCHP_OL_QUEUE_30_DATA_EMC_REG_END                  0x036093dc
+#define BCHP_OL_QUEUE_31_DATA_EMC_REG_START                0x036093e0
+#define BCHP_OL_QUEUE_31_DATA_EMC_REG_END                  0x036093fc
+#define BCHP_OL_QUEUE_MIB_EMC_REG_START                    0x0360a000
+#define BCHP_OL_QUEUE_MIB_EMC_REG_END                      0x0360a17c
+#define BCHP_QueueSharedMem_EMC_REG_START                  0x03640000
+#define BCHP_QueueSharedMem_EMC_REG_END                    0x0364bffc
+#define BCHP_PacketSharedMemory_EMC_REG_START              0x03680000
+#define BCHP_PacketSharedMemory_EMC_REG_END                0x03680ffc
+#define BCHP_PLC_EMC_REG_START                             0x03700000
+#define BCHP_PLC_EMC_REG_END                               0x0370000c
+#define BCHP_DTR_EMC_REG_START                             0x03700100
+#define BCHP_DTR_EMC_REG_END                               0x03700114
+#define BCHP_MISC_EMC_REG_START                            0x03700200
+#define BCHP_MISC_EMC_REG_END                              0x03700204
+#define BCHP_CPU_COMM_REGS_CPUC_REG_START                  0x03800000
+#define BCHP_CPU_COMM_REGS_CPUC_REG_END                    0x0380007c
+#define BCHP_MBOX_CPUC_REG_START                           0x03800080
+#define BCHP_MBOX_CPUC_REG_END                             0x038000fc
+#define BCHP_HW_COUNTER_CPUC_REG_START                     0x03800100
+#define BCHP_HW_COUNTER_CPUC_REG_END                       0x03800188
+#define BCHP_TRACEBUFF_CPUC_REG_START                      0x03801000
+#define BCHP_TRACEBUFF_CPUC_REG_END                        0x03801028
+#define BCHP_Token_CPUC_REG_START                          0x03801400
+#define BCHP_Token_CPUC_REG_END                            0x03801420
+#define BCHP_RNR_WKUP_CPUC_REG_START                       0x03801800
+#define BCHP_RNR_WKUP_CPUC_REG_END                         0x03801984
+#define BCHP_DQM_CPUC_REG_START                            0x03801c00
+#define BCHP_DQM_CPUC_REG_END                              0x03801e20
+#define BCHP_QUEUE_TIMER_CPUC_REG_START                    0x03802000
+#define BCHP_QUEUE_TIMER_CPUC_REG_END                      0x038021fc
+#define BCHP_QUEUE_TIMER_96_CPUC_REG_START                 0x03802200
+#define BCHP_QUEUE_TIMER_96_CPUC_REG_END                   0x038022fc
+#define BCHP_OL_QUEUE_STATUS_CPUC_REG_START                0x03807400
+#define BCHP_OL_QUEUE_STATUS_CPUC_REG_END                  0x0380747c
+#define BCHP_OL_QUEUE_STATUS_64_CPUC_REG_START             0x03807480
+#define BCHP_OL_QUEUE_STATUS_64_CPUC_REG_END               0x038074fc
+#define BCHP_OL_QUEUE_STATUS_96_CPUC_REG_START             0x03807500
+#define BCHP_OL_QUEUE_STATUS_96_CPUC_REG_END               0x0380757c
+#define BCHP_OL_QUEUE_0_DEBUG_CPUC_REG_START               0x03807c00
+#define BCHP_OL_QUEUE_0_DEBUG_CPUC_REG_END                 0x03807c04
+#define BCHP_OL_QUEUE_1_DEBUG_CPUC_REG_START               0x03807c08
+#define BCHP_OL_QUEUE_1_DEBUG_CPUC_REG_END                 0x03807c0c
+#define BCHP_OL_QUEUE_2_DEBUG_CPUC_REG_START               0x03807c10
+#define BCHP_OL_QUEUE_2_DEBUG_CPUC_REG_END                 0x03807c14
+#define BCHP_OL_QUEUE_3_DEBUG_CPUC_REG_START               0x03807c18
+#define BCHP_OL_QUEUE_3_DEBUG_CPUC_REG_END                 0x03807c1c
+#define BCHP_OL_QUEUE_4_DEBUG_CPUC_REG_START               0x03807c20
+#define BCHP_OL_QUEUE_4_DEBUG_CPUC_REG_END                 0x03807c24
+#define BCHP_OL_QUEUE_5_DEBUG_CPUC_REG_START               0x03807c28
+#define BCHP_OL_QUEUE_5_DEBUG_CPUC_REG_END                 0x03807c2c
+#define BCHP_OL_QUEUE_6_DEBUG_CPUC_REG_START               0x03807c30
+#define BCHP_OL_QUEUE_6_DEBUG_CPUC_REG_END                 0x03807c34
+#define BCHP_OL_QUEUE_7_DEBUG_CPUC_REG_START               0x03807c38
+#define BCHP_OL_QUEUE_7_DEBUG_CPUC_REG_END                 0x03807c3c
+#define BCHP_OL_QUEUE_8_DEBUG_CPUC_REG_START               0x03807c40
+#define BCHP_OL_QUEUE_8_DEBUG_CPUC_REG_END                 0x03807c44
+#define BCHP_OL_QUEUE_9_DEBUG_CPUC_REG_START               0x03807c48
+#define BCHP_OL_QUEUE_9_DEBUG_CPUC_REG_END                 0x03807c4c
+#define BCHP_OL_QUEUE_10_DEBUG_CPUC_REG_START              0x03807c50
+#define BCHP_OL_QUEUE_10_DEBUG_CPUC_REG_END                0x03807c54
+#define BCHP_OL_QUEUE_11_DEBUG_CPUC_REG_START              0x03807c58
+#define BCHP_OL_QUEUE_11_DEBUG_CPUC_REG_END                0x03807c5c
+#define BCHP_OL_QUEUE_12_DEBUG_CPUC_REG_START              0x03807c60
+#define BCHP_OL_QUEUE_12_DEBUG_CPUC_REG_END                0x03807c64
+#define BCHP_OL_QUEUE_13_DEBUG_CPUC_REG_START              0x03807c68
+#define BCHP_OL_QUEUE_13_DEBUG_CPUC_REG_END                0x03807c6c
+#define BCHP_OL_QUEUE_14_DEBUG_CPUC_REG_START              0x03807c70
+#define BCHP_OL_QUEUE_14_DEBUG_CPUC_REG_END                0x03807c74
+#define BCHP_OL_QUEUE_15_DEBUG_CPUC_REG_START              0x03807c78
+#define BCHP_OL_QUEUE_15_DEBUG_CPUC_REG_END                0x03807c7c
+#define BCHP_OL_QUEUE_16_DEBUG_CPUC_REG_START              0x03807c80
+#define BCHP_OL_QUEUE_16_DEBUG_CPUC_REG_END                0x03807c84
+#define BCHP_OL_QUEUE_17_DEBUG_CPUC_REG_START              0x03807c88
+#define BCHP_OL_QUEUE_17_DEBUG_CPUC_REG_END                0x03807c8c
+#define BCHP_OL_QUEUE_18_DEBUG_CPUC_REG_START              0x03807c90
+#define BCHP_OL_QUEUE_18_DEBUG_CPUC_REG_END                0x03807c94
+#define BCHP_OL_QUEUE_19_DEBUG_CPUC_REG_START              0x03807c98
+#define BCHP_OL_QUEUE_19_DEBUG_CPUC_REG_END                0x03807c9c
+#define BCHP_OL_QUEUE_20_DEBUG_CPUC_REG_START              0x03807ca0
+#define BCHP_OL_QUEUE_20_DEBUG_CPUC_REG_END                0x03807ca4
+#define BCHP_OL_QUEUE_21_DEBUG_CPUC_REG_START              0x03807ca8
+#define BCHP_OL_QUEUE_21_DEBUG_CPUC_REG_END                0x03807cac
+#define BCHP_OL_QUEUE_22_DEBUG_CPUC_REG_START              0x03807cb0
+#define BCHP_OL_QUEUE_22_DEBUG_CPUC_REG_END                0x03807cb4
+#define BCHP_OL_QUEUE_23_DEBUG_CPUC_REG_START              0x03807cb8
+#define BCHP_OL_QUEUE_23_DEBUG_CPUC_REG_END                0x03807cbc
+#define BCHP_OL_QUEUE_24_DEBUG_CPUC_REG_START              0x03807cc0
+#define BCHP_OL_QUEUE_24_DEBUG_CPUC_REG_END                0x03807cc4
+#define BCHP_OL_QUEUE_25_DEBUG_CPUC_REG_START              0x03807cc8
+#define BCHP_OL_QUEUE_25_DEBUG_CPUC_REG_END                0x03807ccc
+#define BCHP_OL_QUEUE_26_DEBUG_CPUC_REG_START              0x03807cd0
+#define BCHP_OL_QUEUE_26_DEBUG_CPUC_REG_END                0x03807cd4
+#define BCHP_OL_QUEUE_27_DEBUG_CPUC_REG_START              0x03807cd8
+#define BCHP_OL_QUEUE_27_DEBUG_CPUC_REG_END                0x03807cdc
+#define BCHP_OL_QUEUE_28_DEBUG_CPUC_REG_START              0x03807ce0
+#define BCHP_OL_QUEUE_28_DEBUG_CPUC_REG_END                0x03807ce4
+#define BCHP_OL_QUEUE_29_DEBUG_CPUC_REG_START              0x03807ce8
+#define BCHP_OL_QUEUE_29_DEBUG_CPUC_REG_END                0x03807cec
+#define BCHP_OL_QUEUE_30_DEBUG_CPUC_REG_START              0x03807cf0
+#define BCHP_OL_QUEUE_30_DEBUG_CPUC_REG_END                0x03807cf4
+#define BCHP_OL_QUEUE_31_DEBUG_CPUC_REG_START              0x03807cf8
+#define BCHP_OL_QUEUE_31_DEBUG_CPUC_REG_END                0x03807cfc
+#define BCHP_OL_QUEUE_32_DEBUG_CPUC_REG_START              0x03807d00
+#define BCHP_OL_QUEUE_32_DEBUG_CPUC_REG_END                0x03807d04
+#define BCHP_OL_QUEUE_33_DEBUG_CPUC_REG_START              0x03807d08
+#define BCHP_OL_QUEUE_33_DEBUG_CPUC_REG_END                0x03807d0c
+#define BCHP_OL_QUEUE_34_DEBUG_CPUC_REG_START              0x03807d10
+#define BCHP_OL_QUEUE_34_DEBUG_CPUC_REG_END                0x03807d14
+#define BCHP_OL_QUEUE_35_DEBUG_CPUC_REG_START              0x03807d18
+#define BCHP_OL_QUEUE_35_DEBUG_CPUC_REG_END                0x03807d1c
+#define BCHP_OL_QUEUE_36_DEBUG_CPUC_REG_START              0x03807d20
+#define BCHP_OL_QUEUE_36_DEBUG_CPUC_REG_END                0x03807d24
+#define BCHP_OL_QUEUE_37_DEBUG_CPUC_REG_START              0x03807d28
+#define BCHP_OL_QUEUE_37_DEBUG_CPUC_REG_END                0x03807d2c
+#define BCHP_OL_QUEUE_38_DEBUG_CPUC_REG_START              0x03807d30
+#define BCHP_OL_QUEUE_38_DEBUG_CPUC_REG_END                0x03807d34
+#define BCHP_OL_QUEUE_39_DEBUG_CPUC_REG_START              0x03807d38
+#define BCHP_OL_QUEUE_39_DEBUG_CPUC_REG_END                0x03807d3c
+#define BCHP_OL_QUEUE_40_DEBUG_CPUC_REG_START              0x03807d40
+#define BCHP_OL_QUEUE_40_DEBUG_CPUC_REG_END                0x03807d44
+#define BCHP_OL_QUEUE_41_DEBUG_CPUC_REG_START              0x03807d48
+#define BCHP_OL_QUEUE_41_DEBUG_CPUC_REG_END                0x03807d4c
+#define BCHP_OL_QUEUE_42_DEBUG_CPUC_REG_START              0x03807d50
+#define BCHP_OL_QUEUE_42_DEBUG_CPUC_REG_END                0x03807d54
+#define BCHP_OL_QUEUE_43_DEBUG_CPUC_REG_START              0x03807d58
+#define BCHP_OL_QUEUE_43_DEBUG_CPUC_REG_END                0x03807d5c
+#define BCHP_OL_QUEUE_44_DEBUG_CPUC_REG_START              0x03807d60
+#define BCHP_OL_QUEUE_44_DEBUG_CPUC_REG_END                0x03807d64
+#define BCHP_OL_QUEUE_45_DEBUG_CPUC_REG_START              0x03807d68
+#define BCHP_OL_QUEUE_45_DEBUG_CPUC_REG_END                0x03807d6c
+#define BCHP_OL_QUEUE_46_DEBUG_CPUC_REG_START              0x03807d70
+#define BCHP_OL_QUEUE_46_DEBUG_CPUC_REG_END                0x03807d74
+#define BCHP_OL_QUEUE_47_DEBUG_CPUC_REG_START              0x03807d78
+#define BCHP_OL_QUEUE_47_DEBUG_CPUC_REG_END                0x03807d7c
+#define BCHP_OL_QUEUE_48_DEBUG_CPUC_REG_START              0x03807d80
+#define BCHP_OL_QUEUE_48_DEBUG_CPUC_REG_END                0x03807d84
+#define BCHP_OL_QUEUE_49_DEBUG_CPUC_REG_START              0x03807d88
+#define BCHP_OL_QUEUE_49_DEBUG_CPUC_REG_END                0x03807d8c
+#define BCHP_OL_QUEUE_50_DEBUG_CPUC_REG_START              0x03807d90
+#define BCHP_OL_QUEUE_50_DEBUG_CPUC_REG_END                0x03807d94
+#define BCHP_OL_QUEUE_51_DEBUG_CPUC_REG_START              0x03807d98
+#define BCHP_OL_QUEUE_51_DEBUG_CPUC_REG_END                0x03807d9c
+#define BCHP_OL_QUEUE_52_DEBUG_CPUC_REG_START              0x03807da0
+#define BCHP_OL_QUEUE_52_DEBUG_CPUC_REG_END                0x03807da4
+#define BCHP_OL_QUEUE_53_DEBUG_CPUC_REG_START              0x03807da8
+#define BCHP_OL_QUEUE_53_DEBUG_CPUC_REG_END                0x03807dac
+#define BCHP_OL_QUEUE_54_DEBUG_CPUC_REG_START              0x03807db0
+#define BCHP_OL_QUEUE_54_DEBUG_CPUC_REG_END                0x03807db4
+#define BCHP_OL_QUEUE_55_DEBUG_CPUC_REG_START              0x03807db8
+#define BCHP_OL_QUEUE_55_DEBUG_CPUC_REG_END                0x03807dbc
+#define BCHP_OL_QUEUE_56_DEBUG_CPUC_REG_START              0x03807dc0
+#define BCHP_OL_QUEUE_56_DEBUG_CPUC_REG_END                0x03807dc4
+#define BCHP_OL_QUEUE_57_DEBUG_CPUC_REG_START              0x03807dc8
+#define BCHP_OL_QUEUE_57_DEBUG_CPUC_REG_END                0x03807dcc
+#define BCHP_OL_QUEUE_58_DEBUG_CPUC_REG_START              0x03807dd0
+#define BCHP_OL_QUEUE_58_DEBUG_CPUC_REG_END                0x03807dd4
+#define BCHP_OL_QUEUE_59_DEBUG_CPUC_REG_START              0x03807dd8
+#define BCHP_OL_QUEUE_59_DEBUG_CPUC_REG_END                0x03807ddc
+#define BCHP_OL_QUEUE_60_DEBUG_CPUC_REG_START              0x03807de0
+#define BCHP_OL_QUEUE_60_DEBUG_CPUC_REG_END                0x03807de4
+#define BCHP_OL_QUEUE_61_DEBUG_CPUC_REG_START              0x03807de8
+#define BCHP_OL_QUEUE_61_DEBUG_CPUC_REG_END                0x03807dec
+#define BCHP_OL_QUEUE_62_DEBUG_CPUC_REG_START              0x03807df0
+#define BCHP_OL_QUEUE_62_DEBUG_CPUC_REG_END                0x03807df4
+#define BCHP_OL_QUEUE_63_DEBUG_CPUC_REG_START              0x03807df8
+#define BCHP_OL_QUEUE_63_DEBUG_CPUC_REG_END                0x03807dfc
+#define BCHP_OL_QUEUE_64_DEBUG_CPUC_REG_START              0x03807e00
+#define BCHP_OL_QUEUE_64_DEBUG_CPUC_REG_END                0x03807e04
+#define BCHP_OL_QUEUE_65_DEBUG_CPUC_REG_START              0x03807e08
+#define BCHP_OL_QUEUE_65_DEBUG_CPUC_REG_END                0x03807e0c
+#define BCHP_OL_QUEUE_66_DEBUG_CPUC_REG_START              0x03807e10
+#define BCHP_OL_QUEUE_66_DEBUG_CPUC_REG_END                0x03807e14
+#define BCHP_OL_QUEUE_67_DEBUG_CPUC_REG_START              0x03807e18
+#define BCHP_OL_QUEUE_67_DEBUG_CPUC_REG_END                0x03807e1c
+#define BCHP_OL_QUEUE_68_DEBUG_CPUC_REG_START              0x03807e20
+#define BCHP_OL_QUEUE_68_DEBUG_CPUC_REG_END                0x03807e24
+#define BCHP_OL_QUEUE_69_DEBUG_CPUC_REG_START              0x03807e28
+#define BCHP_OL_QUEUE_69_DEBUG_CPUC_REG_END                0x03807e2c
+#define BCHP_OL_QUEUE_70_DEBUG_CPUC_REG_START              0x03807e30
+#define BCHP_OL_QUEUE_70_DEBUG_CPUC_REG_END                0x03807e34
+#define BCHP_OL_QUEUE_71_DEBUG_CPUC_REG_START              0x03807e38
+#define BCHP_OL_QUEUE_71_DEBUG_CPUC_REG_END                0x03807e3c
+#define BCHP_OL_QUEUE_72_DEBUG_CPUC_REG_START              0x03807e40
+#define BCHP_OL_QUEUE_72_DEBUG_CPUC_REG_END                0x03807e44
+#define BCHP_OL_QUEUE_73_DEBUG_CPUC_REG_START              0x03807e48
+#define BCHP_OL_QUEUE_73_DEBUG_CPUC_REG_END                0x03807e4c
+#define BCHP_OL_QUEUE_74_DEBUG_CPUC_REG_START              0x03807e50
+#define BCHP_OL_QUEUE_74_DEBUG_CPUC_REG_END                0x03807e54
+#define BCHP_OL_QUEUE_75_DEBUG_CPUC_REG_START              0x03807e58
+#define BCHP_OL_QUEUE_75_DEBUG_CPUC_REG_END                0x03807e5c
+#define BCHP_OL_QUEUE_76_DEBUG_CPUC_REG_START              0x03807e60
+#define BCHP_OL_QUEUE_76_DEBUG_CPUC_REG_END                0x03807e64
+#define BCHP_OL_QUEUE_77_DEBUG_CPUC_REG_START              0x03807e68
+#define BCHP_OL_QUEUE_77_DEBUG_CPUC_REG_END                0x03807e6c
+#define BCHP_OL_QUEUE_78_DEBUG_CPUC_REG_START              0x03807e70
+#define BCHP_OL_QUEUE_78_DEBUG_CPUC_REG_END                0x03807e74
+#define BCHP_OL_QUEUE_79_DEBUG_CPUC_REG_START              0x03807e78
+#define BCHP_OL_QUEUE_79_DEBUG_CPUC_REG_END                0x03807e7c
+#define BCHP_OL_QUEUE_80_DEBUG_CPUC_REG_START              0x03807e80
+#define BCHP_OL_QUEUE_80_DEBUG_CPUC_REG_END                0x03807e84
+#define BCHP_OL_QUEUE_81_DEBUG_CPUC_REG_START              0x03807e88
+#define BCHP_OL_QUEUE_81_DEBUG_CPUC_REG_END                0x03807e8c
+#define BCHP_OL_QUEUE_82_DEBUG_CPUC_REG_START              0x03807e90
+#define BCHP_OL_QUEUE_82_DEBUG_CPUC_REG_END                0x03807e94
+#define BCHP_OL_QUEUE_83_DEBUG_CPUC_REG_START              0x03807e98
+#define BCHP_OL_QUEUE_83_DEBUG_CPUC_REG_END                0x03807e9c
+#define BCHP_OL_QUEUE_84_DEBUG_CPUC_REG_START              0x03807ea0
+#define BCHP_OL_QUEUE_84_DEBUG_CPUC_REG_END                0x03807ea4
+#define BCHP_OL_QUEUE_85_DEBUG_CPUC_REG_START              0x03807ea8
+#define BCHP_OL_QUEUE_85_DEBUG_CPUC_REG_END                0x03807eac
+#define BCHP_OL_QUEUE_86_DEBUG_CPUC_REG_START              0x03807eb0
+#define BCHP_OL_QUEUE_86_DEBUG_CPUC_REG_END                0x03807eb4
+#define BCHP_OL_QUEUE_87_DEBUG_CPUC_REG_START              0x03807eb8
+#define BCHP_OL_QUEUE_87_DEBUG_CPUC_REG_END                0x03807ebc
+#define BCHP_OL_QUEUE_88_DEBUG_CPUC_REG_START              0x03807ec0
+#define BCHP_OL_QUEUE_88_DEBUG_CPUC_REG_END                0x03807ec4
+#define BCHP_OL_QUEUE_89_DEBUG_CPUC_REG_START              0x03807ec8
+#define BCHP_OL_QUEUE_89_DEBUG_CPUC_REG_END                0x03807ecc
+#define BCHP_OL_QUEUE_90_DEBUG_CPUC_REG_START              0x03807ed0
+#define BCHP_OL_QUEUE_90_DEBUG_CPUC_REG_END                0x03807ed4
+#define BCHP_OL_QUEUE_91_DEBUG_CPUC_REG_START              0x03807ed8
+#define BCHP_OL_QUEUE_91_DEBUG_CPUC_REG_END                0x03807edc
+#define BCHP_OL_QUEUE_92_DEBUG_CPUC_REG_START              0x03807ee0
+#define BCHP_OL_QUEUE_92_DEBUG_CPUC_REG_END                0x03807ee4
+#define BCHP_OL_QUEUE_93_DEBUG_CPUC_REG_START              0x03807ee8
+#define BCHP_OL_QUEUE_93_DEBUG_CPUC_REG_END                0x03807eec
+#define BCHP_OL_QUEUE_94_DEBUG_CPUC_REG_START              0x03807ef0
+#define BCHP_OL_QUEUE_94_DEBUG_CPUC_REG_END                0x03807ef4
+#define BCHP_OL_QUEUE_95_DEBUG_CPUC_REG_START              0x03807ef8
+#define BCHP_OL_QUEUE_95_DEBUG_CPUC_REG_END                0x03807efc
+#define BCHP_OL_QUEUE_0_CNTRL_CPUC_REG_START               0x03808000
+#define BCHP_OL_QUEUE_0_CNTRL_CPUC_REG_END                 0x0380801c
+#define BCHP_OL_QUEUE_1_CNTRL_CPUC_REG_START               0x03808020
+#define BCHP_OL_QUEUE_1_CNTRL_CPUC_REG_END                 0x0380803c
+#define BCHP_OL_QUEUE_2_CNTRL_CPUC_REG_START               0x03808040
+#define BCHP_OL_QUEUE_2_CNTRL_CPUC_REG_END                 0x0380805c
+#define BCHP_OL_QUEUE_3_CNTRL_CPUC_REG_START               0x03808060
+#define BCHP_OL_QUEUE_3_CNTRL_CPUC_REG_END                 0x0380807c
+#define BCHP_OL_QUEUE_4_CNTRL_CPUC_REG_START               0x03808080
+#define BCHP_OL_QUEUE_4_CNTRL_CPUC_REG_END                 0x0380809c
+#define BCHP_OL_QUEUE_5_CNTRL_CPUC_REG_START               0x038080a0
+#define BCHP_OL_QUEUE_5_CNTRL_CPUC_REG_END                 0x038080bc
+#define BCHP_OL_QUEUE_6_CNTRL_CPUC_REG_START               0x038080c0
+#define BCHP_OL_QUEUE_6_CNTRL_CPUC_REG_END                 0x038080dc
+#define BCHP_OL_QUEUE_7_CNTRL_CPUC_REG_START               0x038080e0
+#define BCHP_OL_QUEUE_7_CNTRL_CPUC_REG_END                 0x038080fc
+#define BCHP_OL_QUEUE_8_CNTRL_CPUC_REG_START               0x03808100
+#define BCHP_OL_QUEUE_8_CNTRL_CPUC_REG_END                 0x0380811c
+#define BCHP_OL_QUEUE_9_CNTRL_CPUC_REG_START               0x03808120
+#define BCHP_OL_QUEUE_9_CNTRL_CPUC_REG_END                 0x0380813c
+#define BCHP_OL_QUEUE_10_CNTRL_CPUC_REG_START              0x03808140
+#define BCHP_OL_QUEUE_10_CNTRL_CPUC_REG_END                0x0380815c
+#define BCHP_OL_QUEUE_11_CNTRL_CPUC_REG_START              0x03808160
+#define BCHP_OL_QUEUE_11_CNTRL_CPUC_REG_END                0x0380817c
+#define BCHP_OL_QUEUE_12_CNTRL_CPUC_REG_START              0x03808180
+#define BCHP_OL_QUEUE_12_CNTRL_CPUC_REG_END                0x0380819c
+#define BCHP_OL_QUEUE_13_CNTRL_CPUC_REG_START              0x038081a0
+#define BCHP_OL_QUEUE_13_CNTRL_CPUC_REG_END                0x038081bc
+#define BCHP_OL_QUEUE_14_CNTRL_CPUC_REG_START              0x038081c0
+#define BCHP_OL_QUEUE_14_CNTRL_CPUC_REG_END                0x038081dc
+#define BCHP_OL_QUEUE_15_CNTRL_CPUC_REG_START              0x038081e0
+#define BCHP_OL_QUEUE_15_CNTRL_CPUC_REG_END                0x038081fc
+#define BCHP_OL_QUEUE_16_CNTRL_CPUC_REG_START              0x03808200
+#define BCHP_OL_QUEUE_16_CNTRL_CPUC_REG_END                0x0380821c
+#define BCHP_OL_QUEUE_17_CNTRL_CPUC_REG_START              0x03808220
+#define BCHP_OL_QUEUE_17_CNTRL_CPUC_REG_END                0x0380823c
+#define BCHP_OL_QUEUE_18_CNTRL_CPUC_REG_START              0x03808240
+#define BCHP_OL_QUEUE_18_CNTRL_CPUC_REG_END                0x0380825c
+#define BCHP_OL_QUEUE_19_CNTRL_CPUC_REG_START              0x03808260
+#define BCHP_OL_QUEUE_19_CNTRL_CPUC_REG_END                0x0380827c
+#define BCHP_OL_QUEUE_20_CNTRL_CPUC_REG_START              0x03808280
+#define BCHP_OL_QUEUE_20_CNTRL_CPUC_REG_END                0x0380829c
+#define BCHP_OL_QUEUE_21_CNTRL_CPUC_REG_START              0x038082a0
+#define BCHP_OL_QUEUE_21_CNTRL_CPUC_REG_END                0x038082bc
+#define BCHP_OL_QUEUE_22_CNTRL_CPUC_REG_START              0x038082c0
+#define BCHP_OL_QUEUE_22_CNTRL_CPUC_REG_END                0x038082dc
+#define BCHP_OL_QUEUE_23_CNTRL_CPUC_REG_START              0x038082e0
+#define BCHP_OL_QUEUE_23_CNTRL_CPUC_REG_END                0x038082fc
+#define BCHP_OL_QUEUE_24_CNTRL_CPUC_REG_START              0x03808300
+#define BCHP_OL_QUEUE_24_CNTRL_CPUC_REG_END                0x0380831c
+#define BCHP_OL_QUEUE_25_CNTRL_CPUC_REG_START              0x03808320
+#define BCHP_OL_QUEUE_25_CNTRL_CPUC_REG_END                0x0380833c
+#define BCHP_OL_QUEUE_26_CNTRL_CPUC_REG_START              0x03808340
+#define BCHP_OL_QUEUE_26_CNTRL_CPUC_REG_END                0x0380835c
+#define BCHP_OL_QUEUE_27_CNTRL_CPUC_REG_START              0x03808360
+#define BCHP_OL_QUEUE_27_CNTRL_CPUC_REG_END                0x0380837c
+#define BCHP_OL_QUEUE_28_CNTRL_CPUC_REG_START              0x03808380
+#define BCHP_OL_QUEUE_28_CNTRL_CPUC_REG_END                0x0380839c
+#define BCHP_OL_QUEUE_29_CNTRL_CPUC_REG_START              0x038083a0
+#define BCHP_OL_QUEUE_29_CNTRL_CPUC_REG_END                0x038083bc
+#define BCHP_OL_QUEUE_30_CNTRL_CPUC_REG_START              0x038083c0
+#define BCHP_OL_QUEUE_30_CNTRL_CPUC_REG_END                0x038083dc
+#define BCHP_OL_QUEUE_31_CNTRL_CPUC_REG_START              0x038083e0
+#define BCHP_OL_QUEUE_31_CNTRL_CPUC_REG_END                0x038083fc
+#define BCHP_OL_QUEUE_32_CNTRL_CPUC_REG_START              0x03808400
+#define BCHP_OL_QUEUE_32_CNTRL_CPUC_REG_END                0x0380841c
+#define BCHP_OL_QUEUE_33_CNTRL_CPUC_REG_START              0x03808420
+#define BCHP_OL_QUEUE_33_CNTRL_CPUC_REG_END                0x0380843c
+#define BCHP_OL_QUEUE_34_CNTRL_CPUC_REG_START              0x03808440
+#define BCHP_OL_QUEUE_34_CNTRL_CPUC_REG_END                0x0380845c
+#define BCHP_OL_QUEUE_35_CNTRL_CPUC_REG_START              0x03808460
+#define BCHP_OL_QUEUE_35_CNTRL_CPUC_REG_END                0x0380847c
+#define BCHP_OL_QUEUE_36_CNTRL_CPUC_REG_START              0x03808480
+#define BCHP_OL_QUEUE_36_CNTRL_CPUC_REG_END                0x0380849c
+#define BCHP_OL_QUEUE_37_CNTRL_CPUC_REG_START              0x038084a0
+#define BCHP_OL_QUEUE_37_CNTRL_CPUC_REG_END                0x038084bc
+#define BCHP_OL_QUEUE_38_CNTRL_CPUC_REG_START              0x038084c0
+#define BCHP_OL_QUEUE_38_CNTRL_CPUC_REG_END                0x038084dc
+#define BCHP_OL_QUEUE_39_CNTRL_CPUC_REG_START              0x038084e0
+#define BCHP_OL_QUEUE_39_CNTRL_CPUC_REG_END                0x038084fc
+#define BCHP_OL_QUEUE_40_CNTRL_CPUC_REG_START              0x03808500
+#define BCHP_OL_QUEUE_40_CNTRL_CPUC_REG_END                0x0380851c
+#define BCHP_OL_QUEUE_41_CNTRL_CPUC_REG_START              0x03808520
+#define BCHP_OL_QUEUE_41_CNTRL_CPUC_REG_END                0x0380853c
+#define BCHP_OL_QUEUE_42_CNTRL_CPUC_REG_START              0x03808540
+#define BCHP_OL_QUEUE_42_CNTRL_CPUC_REG_END                0x0380855c
+#define BCHP_OL_QUEUE_43_CNTRL_CPUC_REG_START              0x03808560
+#define BCHP_OL_QUEUE_43_CNTRL_CPUC_REG_END                0x0380857c
+#define BCHP_OL_QUEUE_44_CNTRL_CPUC_REG_START              0x03808580
+#define BCHP_OL_QUEUE_44_CNTRL_CPUC_REG_END                0x0380859c
+#define BCHP_OL_QUEUE_45_CNTRL_CPUC_REG_START              0x038085a0
+#define BCHP_OL_QUEUE_45_CNTRL_CPUC_REG_END                0x038085bc
+#define BCHP_OL_QUEUE_46_CNTRL_CPUC_REG_START              0x038085c0
+#define BCHP_OL_QUEUE_46_CNTRL_CPUC_REG_END                0x038085dc
+#define BCHP_OL_QUEUE_47_CNTRL_CPUC_REG_START              0x038085e0
+#define BCHP_OL_QUEUE_47_CNTRL_CPUC_REG_END                0x038085fc
+#define BCHP_OL_QUEUE_48_CNTRL_CPUC_REG_START              0x03808600
+#define BCHP_OL_QUEUE_48_CNTRL_CPUC_REG_END                0x0380861c
+#define BCHP_OL_QUEUE_49_CNTRL_CPUC_REG_START              0x03808620
+#define BCHP_OL_QUEUE_49_CNTRL_CPUC_REG_END                0x0380863c
+#define BCHP_OL_QUEUE_50_CNTRL_CPUC_REG_START              0x03808640
+#define BCHP_OL_QUEUE_50_CNTRL_CPUC_REG_END                0x0380865c
+#define BCHP_OL_QUEUE_51_CNTRL_CPUC_REG_START              0x03808660
+#define BCHP_OL_QUEUE_51_CNTRL_CPUC_REG_END                0x0380867c
+#define BCHP_OL_QUEUE_52_CNTRL_CPUC_REG_START              0x03808680
+#define BCHP_OL_QUEUE_52_CNTRL_CPUC_REG_END                0x0380869c
+#define BCHP_OL_QUEUE_53_CNTRL_CPUC_REG_START              0x038086a0
+#define BCHP_OL_QUEUE_53_CNTRL_CPUC_REG_END                0x038086bc
+#define BCHP_OL_QUEUE_54_CNTRL_CPUC_REG_START              0x038086c0
+#define BCHP_OL_QUEUE_54_CNTRL_CPUC_REG_END                0x038086dc
+#define BCHP_OL_QUEUE_55_CNTRL_CPUC_REG_START              0x038086e0
+#define BCHP_OL_QUEUE_55_CNTRL_CPUC_REG_END                0x038086fc
+#define BCHP_OL_QUEUE_56_CNTRL_CPUC_REG_START              0x03808700
+#define BCHP_OL_QUEUE_56_CNTRL_CPUC_REG_END                0x0380871c
+#define BCHP_OL_QUEUE_57_CNTRL_CPUC_REG_START              0x03808720
+#define BCHP_OL_QUEUE_57_CNTRL_CPUC_REG_END                0x0380873c
+#define BCHP_OL_QUEUE_58_CNTRL_CPUC_REG_START              0x03808740
+#define BCHP_OL_QUEUE_58_CNTRL_CPUC_REG_END                0x0380875c
+#define BCHP_OL_QUEUE_59_CNTRL_CPUC_REG_START              0x03808760
+#define BCHP_OL_QUEUE_59_CNTRL_CPUC_REG_END                0x0380877c
+#define BCHP_OL_QUEUE_60_CNTRL_CPUC_REG_START              0x03808780
+#define BCHP_OL_QUEUE_60_CNTRL_CPUC_REG_END                0x0380879c
+#define BCHP_OL_QUEUE_61_CNTRL_CPUC_REG_START              0x038087a0
+#define BCHP_OL_QUEUE_61_CNTRL_CPUC_REG_END                0x038087bc
+#define BCHP_OL_QUEUE_62_CNTRL_CPUC_REG_START              0x038087c0
+#define BCHP_OL_QUEUE_62_CNTRL_CPUC_REG_END                0x038087dc
+#define BCHP_OL_QUEUE_63_CNTRL_CPUC_REG_START              0x038087e0
+#define BCHP_OL_QUEUE_63_CNTRL_CPUC_REG_END                0x038087fc
+#define BCHP_OL_QUEUE_64_CNTRL_CPUC_REG_START              0x03808800
+#define BCHP_OL_QUEUE_64_CNTRL_CPUC_REG_END                0x0380881c
+#define BCHP_OL_QUEUE_65_CNTRL_CPUC_REG_START              0x03808820
+#define BCHP_OL_QUEUE_65_CNTRL_CPUC_REG_END                0x0380883c
+#define BCHP_OL_QUEUE_66_CNTRL_CPUC_REG_START              0x03808840
+#define BCHP_OL_QUEUE_66_CNTRL_CPUC_REG_END                0x0380885c
+#define BCHP_OL_QUEUE_67_CNTRL_CPUC_REG_START              0x03808860
+#define BCHP_OL_QUEUE_67_CNTRL_CPUC_REG_END                0x0380887c
+#define BCHP_OL_QUEUE_68_CNTRL_CPUC_REG_START              0x03808880
+#define BCHP_OL_QUEUE_68_CNTRL_CPUC_REG_END                0x0380889c
+#define BCHP_OL_QUEUE_69_CNTRL_CPUC_REG_START              0x038088a0
+#define BCHP_OL_QUEUE_69_CNTRL_CPUC_REG_END                0x038088bc
+#define BCHP_OL_QUEUE_70_CNTRL_CPUC_REG_START              0x038088c0
+#define BCHP_OL_QUEUE_70_CNTRL_CPUC_REG_END                0x038088dc
+#define BCHP_OL_QUEUE_71_CNTRL_CPUC_REG_START              0x038088e0
+#define BCHP_OL_QUEUE_71_CNTRL_CPUC_REG_END                0x038088fc
+#define BCHP_OL_QUEUE_72_CNTRL_CPUC_REG_START              0x03808900
+#define BCHP_OL_QUEUE_72_CNTRL_CPUC_REG_END                0x0380891c
+#define BCHP_OL_QUEUE_73_CNTRL_CPUC_REG_START              0x03808920
+#define BCHP_OL_QUEUE_73_CNTRL_CPUC_REG_END                0x0380893c
+#define BCHP_OL_QUEUE_74_CNTRL_CPUC_REG_START              0x03808940
+#define BCHP_OL_QUEUE_74_CNTRL_CPUC_REG_END                0x0380895c
+#define BCHP_OL_QUEUE_75_CNTRL_CPUC_REG_START              0x03808960
+#define BCHP_OL_QUEUE_75_CNTRL_CPUC_REG_END                0x0380897c
+#define BCHP_OL_QUEUE_76_CNTRL_CPUC_REG_START              0x03808980
+#define BCHP_OL_QUEUE_76_CNTRL_CPUC_REG_END                0x0380899c
+#define BCHP_OL_QUEUE_77_CNTRL_CPUC_REG_START              0x038089a0
+#define BCHP_OL_QUEUE_77_CNTRL_CPUC_REG_END                0x038089bc
+#define BCHP_OL_QUEUE_78_CNTRL_CPUC_REG_START              0x038089c0
+#define BCHP_OL_QUEUE_78_CNTRL_CPUC_REG_END                0x038089dc
+#define BCHP_OL_QUEUE_79_CNTRL_CPUC_REG_START              0x038089e0
+#define BCHP_OL_QUEUE_79_CNTRL_CPUC_REG_END                0x038089fc
+#define BCHP_OL_QUEUE_80_CNTRL_CPUC_REG_START              0x03808a00
+#define BCHP_OL_QUEUE_80_CNTRL_CPUC_REG_END                0x03808a1c
+#define BCHP_OL_QUEUE_81_CNTRL_CPUC_REG_START              0x03808a20
+#define BCHP_OL_QUEUE_81_CNTRL_CPUC_REG_END                0x03808a3c
+#define BCHP_OL_QUEUE_82_CNTRL_CPUC_REG_START              0x03808a40
+#define BCHP_OL_QUEUE_82_CNTRL_CPUC_REG_END                0x03808a5c
+#define BCHP_OL_QUEUE_83_CNTRL_CPUC_REG_START              0x03808a60
+#define BCHP_OL_QUEUE_83_CNTRL_CPUC_REG_END                0x03808a7c
+#define BCHP_OL_QUEUE_84_CNTRL_CPUC_REG_START              0x03808a80
+#define BCHP_OL_QUEUE_84_CNTRL_CPUC_REG_END                0x03808a9c
+#define BCHP_OL_QUEUE_85_CNTRL_CPUC_REG_START              0x03808aa0
+#define BCHP_OL_QUEUE_85_CNTRL_CPUC_REG_END                0x03808abc
+#define BCHP_OL_QUEUE_86_CNTRL_CPUC_REG_START              0x03808ac0
+#define BCHP_OL_QUEUE_86_CNTRL_CPUC_REG_END                0x03808adc
+#define BCHP_OL_QUEUE_87_CNTRL_CPUC_REG_START              0x03808ae0
+#define BCHP_OL_QUEUE_87_CNTRL_CPUC_REG_END                0x03808afc
+#define BCHP_OL_QUEUE_88_CNTRL_CPUC_REG_START              0x03808b00
+#define BCHP_OL_QUEUE_88_CNTRL_CPUC_REG_END                0x03808b1c
+#define BCHP_OL_QUEUE_89_CNTRL_CPUC_REG_START              0x03808b20
+#define BCHP_OL_QUEUE_89_CNTRL_CPUC_REG_END                0x03808b3c
+#define BCHP_OL_QUEUE_90_CNTRL_CPUC_REG_START              0x03808b40
+#define BCHP_OL_QUEUE_90_CNTRL_CPUC_REG_END                0x03808b5c
+#define BCHP_OL_QUEUE_91_CNTRL_CPUC_REG_START              0x03808b60
+#define BCHP_OL_QUEUE_91_CNTRL_CPUC_REG_END                0x03808b7c
+#define BCHP_OL_QUEUE_92_CNTRL_CPUC_REG_START              0x03808b80
+#define BCHP_OL_QUEUE_92_CNTRL_CPUC_REG_END                0x03808b9c
+#define BCHP_OL_QUEUE_93_CNTRL_CPUC_REG_START              0x03808ba0
+#define BCHP_OL_QUEUE_93_CNTRL_CPUC_REG_END                0x03808bbc
+#define BCHP_OL_QUEUE_94_CNTRL_CPUC_REG_START              0x03808bc0
+#define BCHP_OL_QUEUE_94_CNTRL_CPUC_REG_END                0x03808bdc
+#define BCHP_OL_QUEUE_95_CNTRL_CPUC_REG_START              0x03808be0
+#define BCHP_OL_QUEUE_95_CNTRL_CPUC_REG_END                0x03808bfc
+#define BCHP_OL_QUEUE_0_DATA_CPUC_REG_START                0x03809000
+#define BCHP_OL_QUEUE_0_DATA_CPUC_REG_END                  0x0380901c
+#define BCHP_OL_QUEUE_1_DATA_CPUC_REG_START                0x03809020
+#define BCHP_OL_QUEUE_1_DATA_CPUC_REG_END                  0x0380903c
+#define BCHP_OL_QUEUE_2_DATA_CPUC_REG_START                0x03809040
+#define BCHP_OL_QUEUE_2_DATA_CPUC_REG_END                  0x0380905c
+#define BCHP_OL_QUEUE_3_DATA_CPUC_REG_START                0x03809060
+#define BCHP_OL_QUEUE_3_DATA_CPUC_REG_END                  0x0380907c
+#define BCHP_OL_QUEUE_4_DATA_CPUC_REG_START                0x03809080
+#define BCHP_OL_QUEUE_4_DATA_CPUC_REG_END                  0x0380909c
+#define BCHP_OL_QUEUE_5_DATA_CPUC_REG_START                0x038090a0
+#define BCHP_OL_QUEUE_5_DATA_CPUC_REG_END                  0x038090bc
+#define BCHP_OL_QUEUE_6_DATA_CPUC_REG_START                0x038090c0
+#define BCHP_OL_QUEUE_6_DATA_CPUC_REG_END                  0x038090dc
+#define BCHP_OL_QUEUE_7_DATA_CPUC_REG_START                0x038090e0
+#define BCHP_OL_QUEUE_7_DATA_CPUC_REG_END                  0x038090fc
+#define BCHP_OL_QUEUE_8_DATA_CPUC_REG_START                0x03809100
+#define BCHP_OL_QUEUE_8_DATA_CPUC_REG_END                  0x0380911c
+#define BCHP_OL_QUEUE_9_DATA_CPUC_REG_START                0x03809120
+#define BCHP_OL_QUEUE_9_DATA_CPUC_REG_END                  0x0380913c
+#define BCHP_OL_QUEUE_10_DATA_CPUC_REG_START               0x03809140
+#define BCHP_OL_QUEUE_10_DATA_CPUC_REG_END                 0x0380915c
+#define BCHP_OL_QUEUE_11_DATA_CPUC_REG_START               0x03809160
+#define BCHP_OL_QUEUE_11_DATA_CPUC_REG_END                 0x0380917c
+#define BCHP_OL_QUEUE_12_DATA_CPUC_REG_START               0x03809180
+#define BCHP_OL_QUEUE_12_DATA_CPUC_REG_END                 0x0380919c
+#define BCHP_OL_QUEUE_13_DATA_CPUC_REG_START               0x038091a0
+#define BCHP_OL_QUEUE_13_DATA_CPUC_REG_END                 0x038091bc
+#define BCHP_OL_QUEUE_14_DATA_CPUC_REG_START               0x038091c0
+#define BCHP_OL_QUEUE_14_DATA_CPUC_REG_END                 0x038091dc
+#define BCHP_OL_QUEUE_15_DATA_CPUC_REG_START               0x038091e0
+#define BCHP_OL_QUEUE_15_DATA_CPUC_REG_END                 0x038091fc
+#define BCHP_OL_QUEUE_16_DATA_CPUC_REG_START               0x03809200
+#define BCHP_OL_QUEUE_16_DATA_CPUC_REG_END                 0x0380921c
+#define BCHP_OL_QUEUE_17_DATA_CPUC_REG_START               0x03809220
+#define BCHP_OL_QUEUE_17_DATA_CPUC_REG_END                 0x0380923c
+#define BCHP_OL_QUEUE_18_DATA_CPUC_REG_START               0x03809240
+#define BCHP_OL_QUEUE_18_DATA_CPUC_REG_END                 0x0380925c
+#define BCHP_OL_QUEUE_19_DATA_CPUC_REG_START               0x03809260
+#define BCHP_OL_QUEUE_19_DATA_CPUC_REG_END                 0x0380927c
+#define BCHP_OL_QUEUE_20_DATA_CPUC_REG_START               0x03809280
+#define BCHP_OL_QUEUE_20_DATA_CPUC_REG_END                 0x0380929c
+#define BCHP_OL_QUEUE_21_DATA_CPUC_REG_START               0x038092a0
+#define BCHP_OL_QUEUE_21_DATA_CPUC_REG_END                 0x038092bc
+#define BCHP_OL_QUEUE_22_DATA_CPUC_REG_START               0x038092c0
+#define BCHP_OL_QUEUE_22_DATA_CPUC_REG_END                 0x038092dc
+#define BCHP_OL_QUEUE_23_DATA_CPUC_REG_START               0x038092e0
+#define BCHP_OL_QUEUE_23_DATA_CPUC_REG_END                 0x038092fc
+#define BCHP_OL_QUEUE_24_DATA_CPUC_REG_START               0x03809300
+#define BCHP_OL_QUEUE_24_DATA_CPUC_REG_END                 0x0380931c
+#define BCHP_OL_QUEUE_25_DATA_CPUC_REG_START               0x03809320
+#define BCHP_OL_QUEUE_25_DATA_CPUC_REG_END                 0x0380933c
+#define BCHP_OL_QUEUE_26_DATA_CPUC_REG_START               0x03809340
+#define BCHP_OL_QUEUE_26_DATA_CPUC_REG_END                 0x0380935c
+#define BCHP_OL_QUEUE_27_DATA_CPUC_REG_START               0x03809360
+#define BCHP_OL_QUEUE_27_DATA_CPUC_REG_END                 0x0380937c
+#define BCHP_OL_QUEUE_28_DATA_CPUC_REG_START               0x03809380
+#define BCHP_OL_QUEUE_28_DATA_CPUC_REG_END                 0x0380939c
+#define BCHP_OL_QUEUE_29_DATA_CPUC_REG_START               0x038093a0
+#define BCHP_OL_QUEUE_29_DATA_CPUC_REG_END                 0x038093bc
+#define BCHP_OL_QUEUE_30_DATA_CPUC_REG_START               0x038093c0
+#define BCHP_OL_QUEUE_30_DATA_CPUC_REG_END                 0x038093dc
+#define BCHP_OL_QUEUE_31_DATA_CPUC_REG_START               0x038093e0
+#define BCHP_OL_QUEUE_31_DATA_CPUC_REG_END                 0x038093fc
+#define BCHP_OL_QUEUE_32_DATA_CPUC_REG_START               0x03809400
+#define BCHP_OL_QUEUE_32_DATA_CPUC_REG_END                 0x0380941c
+#define BCHP_OL_QUEUE_33_DATA_CPUC_REG_START               0x03809420
+#define BCHP_OL_QUEUE_33_DATA_CPUC_REG_END                 0x0380943c
+#define BCHP_OL_QUEUE_34_DATA_CPUC_REG_START               0x03809440
+#define BCHP_OL_QUEUE_34_DATA_CPUC_REG_END                 0x0380945c
+#define BCHP_OL_QUEUE_35_DATA_CPUC_REG_START               0x03809460
+#define BCHP_OL_QUEUE_35_DATA_CPUC_REG_END                 0x0380947c
+#define BCHP_OL_QUEUE_36_DATA_CPUC_REG_START               0x03809480
+#define BCHP_OL_QUEUE_36_DATA_CPUC_REG_END                 0x0380949c
+#define BCHP_OL_QUEUE_37_DATA_CPUC_REG_START               0x038094a0
+#define BCHP_OL_QUEUE_37_DATA_CPUC_REG_END                 0x038094bc
+#define BCHP_OL_QUEUE_38_DATA_CPUC_REG_START               0x038094c0
+#define BCHP_OL_QUEUE_38_DATA_CPUC_REG_END                 0x038094dc
+#define BCHP_OL_QUEUE_39_DATA_CPUC_REG_START               0x038094e0
+#define BCHP_OL_QUEUE_39_DATA_CPUC_REG_END                 0x038094fc
+#define BCHP_OL_QUEUE_40_DATA_CPUC_REG_START               0x03809500
+#define BCHP_OL_QUEUE_40_DATA_CPUC_REG_END                 0x0380951c
+#define BCHP_OL_QUEUE_41_DATA_CPUC_REG_START               0x03809520
+#define BCHP_OL_QUEUE_41_DATA_CPUC_REG_END                 0x0380953c
+#define BCHP_OL_QUEUE_42_DATA_CPUC_REG_START               0x03809540
+#define BCHP_OL_QUEUE_42_DATA_CPUC_REG_END                 0x0380955c
+#define BCHP_OL_QUEUE_43_DATA_CPUC_REG_START               0x03809560
+#define BCHP_OL_QUEUE_43_DATA_CPUC_REG_END                 0x0380957c
+#define BCHP_OL_QUEUE_44_DATA_CPUC_REG_START               0x03809580
+#define BCHP_OL_QUEUE_44_DATA_CPUC_REG_END                 0x0380959c
+#define BCHP_OL_QUEUE_45_DATA_CPUC_REG_START               0x038095a0
+#define BCHP_OL_QUEUE_45_DATA_CPUC_REG_END                 0x038095bc
+#define BCHP_OL_QUEUE_46_DATA_CPUC_REG_START               0x038095c0
+#define BCHP_OL_QUEUE_46_DATA_CPUC_REG_END                 0x038095dc
+#define BCHP_OL_QUEUE_47_DATA_CPUC_REG_START               0x038095e0
+#define BCHP_OL_QUEUE_47_DATA_CPUC_REG_END                 0x038095fc
+#define BCHP_OL_QUEUE_48_DATA_CPUC_REG_START               0x03809600
+#define BCHP_OL_QUEUE_48_DATA_CPUC_REG_END                 0x0380961c
+#define BCHP_OL_QUEUE_49_DATA_CPUC_REG_START               0x03809620
+#define BCHP_OL_QUEUE_49_DATA_CPUC_REG_END                 0x0380963c
+#define BCHP_OL_QUEUE_50_DATA_CPUC_REG_START               0x03809640
+#define BCHP_OL_QUEUE_50_DATA_CPUC_REG_END                 0x0380965c
+#define BCHP_OL_QUEUE_51_DATA_CPUC_REG_START               0x03809660
+#define BCHP_OL_QUEUE_51_DATA_CPUC_REG_END                 0x0380967c
+#define BCHP_OL_QUEUE_52_DATA_CPUC_REG_START               0x03809680
+#define BCHP_OL_QUEUE_52_DATA_CPUC_REG_END                 0x0380969c
+#define BCHP_OL_QUEUE_53_DATA_CPUC_REG_START               0x038096a0
+#define BCHP_OL_QUEUE_53_DATA_CPUC_REG_END                 0x038096bc
+#define BCHP_OL_QUEUE_54_DATA_CPUC_REG_START               0x038096c0
+#define BCHP_OL_QUEUE_54_DATA_CPUC_REG_END                 0x038096dc
+#define BCHP_OL_QUEUE_55_DATA_CPUC_REG_START               0x038096e0
+#define BCHP_OL_QUEUE_55_DATA_CPUC_REG_END                 0x038096fc
+#define BCHP_OL_QUEUE_56_DATA_CPUC_REG_START               0x03809700
+#define BCHP_OL_QUEUE_56_DATA_CPUC_REG_END                 0x0380971c
+#define BCHP_OL_QUEUE_57_DATA_CPUC_REG_START               0x03809720
+#define BCHP_OL_QUEUE_57_DATA_CPUC_REG_END                 0x0380973c
+#define BCHP_OL_QUEUE_58_DATA_CPUC_REG_START               0x03809740
+#define BCHP_OL_QUEUE_58_DATA_CPUC_REG_END                 0x0380975c
+#define BCHP_OL_QUEUE_59_DATA_CPUC_REG_START               0x03809760
+#define BCHP_OL_QUEUE_59_DATA_CPUC_REG_END                 0x0380977c
+#define BCHP_OL_QUEUE_60_DATA_CPUC_REG_START               0x03809780
+#define BCHP_OL_QUEUE_60_DATA_CPUC_REG_END                 0x0380979c
+#define BCHP_OL_QUEUE_61_DATA_CPUC_REG_START               0x038097a0
+#define BCHP_OL_QUEUE_61_DATA_CPUC_REG_END                 0x038097bc
+#define BCHP_OL_QUEUE_62_DATA_CPUC_REG_START               0x038097c0
+#define BCHP_OL_QUEUE_62_DATA_CPUC_REG_END                 0x038097dc
+#define BCHP_OL_QUEUE_63_DATA_CPUC_REG_START               0x038097e0
+#define BCHP_OL_QUEUE_63_DATA_CPUC_REG_END                 0x038097fc
+#define BCHP_OL_QUEUE_64_DATA_CPUC_REG_START               0x03809800
+#define BCHP_OL_QUEUE_64_DATA_CPUC_REG_END                 0x0380981c
+#define BCHP_OL_QUEUE_65_DATA_CPUC_REG_START               0x03809820
+#define BCHP_OL_QUEUE_65_DATA_CPUC_REG_END                 0x0380983c
+#define BCHP_OL_QUEUE_66_DATA_CPUC_REG_START               0x03809840
+#define BCHP_OL_QUEUE_66_DATA_CPUC_REG_END                 0x0380985c
+#define BCHP_OL_QUEUE_67_DATA_CPUC_REG_START               0x03809860
+#define BCHP_OL_QUEUE_67_DATA_CPUC_REG_END                 0x0380987c
+#define BCHP_OL_QUEUE_68_DATA_CPUC_REG_START               0x03809880
+#define BCHP_OL_QUEUE_68_DATA_CPUC_REG_END                 0x0380989c
+#define BCHP_OL_QUEUE_69_DATA_CPUC_REG_START               0x038098a0
+#define BCHP_OL_QUEUE_69_DATA_CPUC_REG_END                 0x038098bc
+#define BCHP_OL_QUEUE_70_DATA_CPUC_REG_START               0x038098c0
+#define BCHP_OL_QUEUE_70_DATA_CPUC_REG_END                 0x038098dc
+#define BCHP_OL_QUEUE_71_DATA_CPUC_REG_START               0x038098e0
+#define BCHP_OL_QUEUE_71_DATA_CPUC_REG_END                 0x038098fc
+#define BCHP_OL_QUEUE_72_DATA_CPUC_REG_START               0x03809900
+#define BCHP_OL_QUEUE_72_DATA_CPUC_REG_END                 0x0380991c
+#define BCHP_OL_QUEUE_73_DATA_CPUC_REG_START               0x03809920
+#define BCHP_OL_QUEUE_73_DATA_CPUC_REG_END                 0x0380993c
+#define BCHP_OL_QUEUE_74_DATA_CPUC_REG_START               0x03809940
+#define BCHP_OL_QUEUE_74_DATA_CPUC_REG_END                 0x0380995c
+#define BCHP_OL_QUEUE_75_DATA_CPUC_REG_START               0x03809960
+#define BCHP_OL_QUEUE_75_DATA_CPUC_REG_END                 0x0380997c
+#define BCHP_OL_QUEUE_76_DATA_CPUC_REG_START               0x03809980
+#define BCHP_OL_QUEUE_76_DATA_CPUC_REG_END                 0x0380999c
+#define BCHP_OL_QUEUE_77_DATA_CPUC_REG_START               0x038099a0
+#define BCHP_OL_QUEUE_77_DATA_CPUC_REG_END                 0x038099bc
+#define BCHP_OL_QUEUE_78_DATA_CPUC_REG_START               0x038099c0
+#define BCHP_OL_QUEUE_78_DATA_CPUC_REG_END                 0x038099dc
+#define BCHP_OL_QUEUE_79_DATA_CPUC_REG_START               0x038099e0
+#define BCHP_OL_QUEUE_79_DATA_CPUC_REG_END                 0x038099fc
+#define BCHP_OL_QUEUE_80_DATA_CPUC_REG_START               0x03809a00
+#define BCHP_OL_QUEUE_80_DATA_CPUC_REG_END                 0x03809a1c
+#define BCHP_OL_QUEUE_81_DATA_CPUC_REG_START               0x03809a20
+#define BCHP_OL_QUEUE_81_DATA_CPUC_REG_END                 0x03809a3c
+#define BCHP_OL_QUEUE_82_DATA_CPUC_REG_START               0x03809a40
+#define BCHP_OL_QUEUE_82_DATA_CPUC_REG_END                 0x03809a5c
+#define BCHP_OL_QUEUE_83_DATA_CPUC_REG_START               0x03809a60
+#define BCHP_OL_QUEUE_83_DATA_CPUC_REG_END                 0x03809a7c
+#define BCHP_OL_QUEUE_84_DATA_CPUC_REG_START               0x03809a80
+#define BCHP_OL_QUEUE_84_DATA_CPUC_REG_END                 0x03809a9c
+#define BCHP_OL_QUEUE_85_DATA_CPUC_REG_START               0x03809aa0
+#define BCHP_OL_QUEUE_85_DATA_CPUC_REG_END                 0x03809abc
+#define BCHP_OL_QUEUE_86_DATA_CPUC_REG_START               0x03809ac0
+#define BCHP_OL_QUEUE_86_DATA_CPUC_REG_END                 0x03809adc
+#define BCHP_OL_QUEUE_87_DATA_CPUC_REG_START               0x03809ae0
+#define BCHP_OL_QUEUE_87_DATA_CPUC_REG_END                 0x03809afc
+#define BCHP_OL_QUEUE_88_DATA_CPUC_REG_START               0x03809b00
+#define BCHP_OL_QUEUE_88_DATA_CPUC_REG_END                 0x03809b1c
+#define BCHP_OL_QUEUE_89_DATA_CPUC_REG_START               0x03809b20
+#define BCHP_OL_QUEUE_89_DATA_CPUC_REG_END                 0x03809b3c
+#define BCHP_OL_QUEUE_90_DATA_CPUC_REG_START               0x03809b40
+#define BCHP_OL_QUEUE_90_DATA_CPUC_REG_END                 0x03809b5c
+#define BCHP_OL_QUEUE_91_DATA_CPUC_REG_START               0x03809b60
+#define BCHP_OL_QUEUE_91_DATA_CPUC_REG_END                 0x03809b7c
+#define BCHP_OL_QUEUE_92_DATA_CPUC_REG_START               0x03809b80
+#define BCHP_OL_QUEUE_92_DATA_CPUC_REG_END                 0x03809b9c
+#define BCHP_OL_QUEUE_93_DATA_CPUC_REG_START               0x03809ba0
+#define BCHP_OL_QUEUE_93_DATA_CPUC_REG_END                 0x03809bbc
+#define BCHP_OL_QUEUE_94_DATA_CPUC_REG_START               0x03809bc0
+#define BCHP_OL_QUEUE_94_DATA_CPUC_REG_END                 0x03809bdc
+#define BCHP_OL_QUEUE_95_DATA_CPUC_REG_START               0x03809be0
+#define BCHP_OL_QUEUE_95_DATA_CPUC_REG_END                 0x03809bfc
+#define BCHP_OL_QUEUE_MIB_CPUC_REG_START                   0x0380a000
+#define BCHP_OL_QUEUE_MIB_CPUC_REG_END                     0x0380a17c
+#define BCHP_OL_QUEUE_MIB_64_CPUC_REG_START                0x0380a200
+#define BCHP_OL_QUEUE_MIB_64_CPUC_REG_END                  0x0380a37c
+#define BCHP_OL_QUEUE_MIB_96_CPUC_REG_START                0x0380a400
+#define BCHP_OL_QUEUE_MIB_96_CPUC_REG_END                  0x0380a57c
+#define BCHP_QueueSharedMem_CPUC_REG_START                 0x03840000
+#define BCHP_QueueSharedMem_CPUC_REG_END                   0x0384bffc
+#define BCHP_CM_TOP_CTRL_REG_START                         0x03880000
+#define BCHP_CM_TOP_CTRL_REG_END                           0x03880370
+#define BCHP_RG_TOP_CTRL_REG_START                         0x03881000
+#define BCHP_RG_TOP_CTRL_REG_END                           0x0388104c
+#define BCHP_UART_REG_START                                0x03881800
+#define BCHP_UART_REG_END                                  0x0388181c
+#define BCHP_CM_AON_CTRL_REG_START                         0x03882000
+#define BCHP_CM_AON_CTRL_REG_END                           0x03882008
+#define BCHP_PROD_OTP_GRB_UB_REG_START                     0x03890000
+#define BCHP_PROD_OTP_GRB_UB_REG_END                       0x0389000c
+#define BCHP_JTAG_OTP_UB_REG_START                         0x03890100
+#define BCHP_JTAG_OTP_UB_REG_END                           0x0389015c
+#define BCHP_RF4CE_CPU_PROG0_MEM_UB_REG_START              0x03900000
+#define BCHP_RF4CE_CPU_PROG0_MEM_UB_REG_END                0x0391fffc
+#define BCHP_RF4CE_CPU_PROG1_MEM_UB_REG_START              0x03920000
+#define BCHP_RF4CE_CPU_PROG1_MEM_UB_REG_END                0x0393fffc
+#define BCHP_RF4CE_CPU_DATA_MEM_UB_REG_START               0x03940000
+#define BCHP_RF4CE_CPU_DATA_MEM_UB_REG_END                 0x03947ffc
+#define BCHP_RF4CE_CPU_CORE_REGS_UB_REG_START              0x03950000
+#define BCHP_RF4CE_CPU_CORE_REGS_UB_REG_END                0x039500fc
+#define BCHP_RF4CE_CPU_AUX_REGS_UB_REG_START               0x03951000
+#define BCHP_RF4CE_CPU_AUX_REGS_UB_REG_END                 0x03951a08
+#define BCHP_RF4CE_CPU_UART_UB_REG_START                   0x03952000
+#define BCHP_RF4CE_CPU_UART_UB_REG_END                     0x03952ffc
+#define BCHP_RF4CE_CPU_WDG_UB_REG_START                    0x03953000
+#define BCHP_RF4CE_CPU_WDG_UB_REG_END                      0x03953ffc
+#define BCHP_RF4CE_CPU_CTRL_UB_REG_START                   0x03980000
+#define BCHP_RF4CE_CPU_CTRL_UB_REG_END                     0x0398008c
+#define BCHP_RF4CE_CPU_L2_UB_REG_START                     0x03980300
+#define BCHP_RF4CE_CPU_L2_UB_REG_END                       0x03980314
+#define BCHP_RF4CE_CPU_HOST_STB_L2_UB_REG_START            0x03980500
+#define BCHP_RF4CE_CPU_HOST_STB_L2_UB_REG_END              0x0398052c
+#define BCHP_RF4CE_CPU_HOST_CM_L2_UB_REG_START             0x03980800
+#define BCHP_RF4CE_CPU_HOST_CM_L2_UB_REG_END               0x0398082c
+#define BCHP_RF4CE_CPU_HOST_RG_L2_UB_REG_START             0x03980a00
+#define BCHP_RF4CE_CPU_HOST_RG_L2_UB_REG_END               0x03980a2c
+#define BCHP_TX_UB_REG_START                               0x039c0000
+#define BCHP_TX_UB_REG_END                                 0x039c0020
+#define BCHP_RX_UB_REG_START                               0x039d0000
+#define BCHP_RX_UB_REG_END                                 0x039d0254
+#define BCHP_RF_UB_REG_START                               0x039e0000
+#define BCHP_RF_UB_REG_END                                 0x039e00a4
+#define BCHP_VCOCAL_UB_REG_START                           0x039e0100
+#define BCHP_VCOCAL_UB_REG_END                             0x039e0174
+#define BCHP_KVCO_UB_REG_START                             0x039e0200
+#define BCHP_KVCO_UB_REG_END                               0x039e0224
+#define BCHP_PA_UB_REG_START                               0x039e0300
+#define BCHP_PA_UB_REG_END                                 0x039e0314
+#define BCHP_MAC_UB_REG_START                              0x039e0400
+#define BCHP_MAC_UB_REG_END                                0x039e0564
+#define BCHP_PWR_MGT_L2_UB_REG_START                       0x039e0600
+#define BCHP_PWR_MGT_L2_UB_REG_END                         0x039e0614
+#define BCHP_MISC_L2_UB_REG_START                          0x039e0700
+#define BCHP_MISC_L2_UB_REG_END                            0x039e0714
+#define BCHP_IQCAL_CCA_CCM_L2_UB_REG_START                 0x039e0800
+#define BCHP_IQCAL_CCA_CCM_L2_UB_REG_END                   0x039e0814
+#define BCHP_SYMCNT6_L2_UB_REG_START                       0x039e0900
+#define BCHP_SYMCNT6_L2_UB_REG_END                         0x039e0914
+#define BCHP_TX_DONE_L2_UB_REG_START                       0x039e0a00
+#define BCHP_TX_DONE_L2_UB_REG_END                         0x039e0a14
+#define BCHP_RX_DONE_L2_UB_REG_START                       0x039e0b00
+#define BCHP_RX_DONE_L2_UB_REG_END                         0x039e0b14
+#define BCHP_RX_START_L2_UB_REG_START                      0x039e0c00
+#define BCHP_RX_START_L2_UB_REG_END                        0x039e0c14
+#define BCHP_SYMCNT7_L2_UB_REG_START                       0x039e0d00
+#define BCHP_SYMCNT7_L2_UB_REG_END                         0x039e0d14
+#define BCHP_GCI_0_UB_REG_START                            0x039e1000
+#define BCHP_GCI_0_UB_REG_END                              0x039e120c
+#define BCHP_GCI_1_UB_REG_START                            0x039e1400
+#define BCHP_GCI_1_UB_REG_END                              0x039e1604
+#define BCHP_GCI_2_UB_REG_START                            0x039e1800
+#define BCHP_GCI_2_UB_REG_END                              0x039e1a04
+#define BCHP_FPM_CTRL_FPM_REG_START                        0x03a00000
+#define BCHP_FPM_CTRL_FPM_REG_END                          0x03a00154
+#define BCHP_FPM_POOL_FPM_REG_START                        0x03a00200
+#define BCHP_FPM_POOL_FPM_REG_END                          0x03a00224
+#define BCHP_FPM_POOL_0_FPM_REG_START                      0x03a00400
+#define BCHP_FPM_POOL_0_FPM_REG_END                        0x03a00424
+#define BCHP_FPM_POOL_1_FPM_REG_START                      0x03a00600
+#define BCHP_FPM_POOL_1_FPM_REG_END                        0x03a00624
+#define BCHP_FPM_SEARCH_0_FPM_REG_START                    0x03a04000
+#define BCHP_FPM_SEARCH_0_FPM_REG_END                      0x03a048b8
+#define BCHP_FPM_SEARCH_1_FPM_REG_START                    0x03a05000
+#define BCHP_FPM_SEARCH_1_FPM_REG_END                      0x03a058b8
+#define BCHP_FPM_MULTI_0_FPM_REG_START                     0x03a10000
+#define BCHP_FPM_MULTI_0_FPM_REG_END                       0x03a1fff8
+#define BCHP_FPM_MULTI_1_FPM_REG_START                     0x03a20000
+#define BCHP_FPM_MULTI_1_FPM_REG_END                       0x03a2fff8
+#define BCHP_REGS_FPM_REG_START                            0x03a30000
+#define BCHP_REGS_FPM_REG_END                              0x03a30130
+#define BCHP_FPM_COMPUTE_POOL_0_FPM_REG_START              0x03a50000
+#define BCHP_FPM_COMPUTE_POOL_0_FPM_REG_END                0x03a5ffff
+#define BCHP_FPM_COMPUTE_POOL_1_FPM_REG_START              0x03a60000
+#define BCHP_FPM_COMPUTE_POOL_1_FPM_REG_END                0x03a6ffff
+#define BCHP_GenInt_PER_REG_START                          0x03c00000
+#define BCHP_GenInt_PER_REG_END                            0x03c00048
+#define BCHP_IntSet0_PER_REG_START                         0x03c00100
+#define BCHP_IntSet0_PER_REG_END                           0x03c0018c
+#define BCHP_IntSet1_PER_REG_START                         0x03c00200
+#define BCHP_IntSet1_PER_REG_END                           0x03c0028c
+#define BCHP_IntSet2_PER_REG_START                         0x03c00300
+#define BCHP_IntSet2_PER_REG_END                           0x03c0038c
+#define BCHP_PERIPH_TIMER_PER_REG_START                    0x03c00400
+#define BCHP_PERIPH_TIMER_PER_REG_END                      0x03c00438
+#define BCHP_GPIO_PER_REG_START                            0x03c00500
+#define BCHP_GPIO_PER_REG_END                              0x03c00578
+#define BCHP_BROM_GEN_PER_REG_START                        0x03c00600
+#define BCHP_BROM_GEN_PER_REG_END                          0x03c00608
+#define BCHP_BROM_SEC1_PER_REG_START                       0x03c00620
+#define BCHP_BROM_SEC1_PER_REG_END                         0x03c00630
+#define BCHP_UART0_PER_REG_START                           0x03c00640
+#define BCHP_UART0_PER_REG_END                             0x03c00654
+#define BCHP_UART1_PER_REG_START                           0x03c00660
+#define BCHP_UART1_PER_REG_END                             0x03c00674
+#define BCHP_I2C_DUAL_CORE1_PER_REG_START                  0x03c00700
+#define BCHP_I2C_DUAL_CORE1_PER_REG_END                    0x03c00754
+#define BCHP_I2C_DUAL_CORE2_PER_REG_START                  0x03c00780
+#define BCHP_I2C_DUAL_CORE2_PER_REG_END                    0x03c007d4
+#define BCHP_LED_PER_REG_START                             0x03c009c0
+#define BCHP_LED_PER_REG_END                               0x03c009ec
+#define BCHP_DIAG_MEM_TOP_PER_REG_START                    0x03c00a00
+#define BCHP_DIAG_MEM_TOP_PER_REG_END                      0x03c00b00
+#define BCHP_GLOBALCNTRL_PER_REG_START                     0x03c01000
+#define BCHP_GLOBALCNTRL_PER_REG_END                       0x03c01018
+#define BCHP_PINGPONG_0_PER_REG_START                      0x03c01080
+#define BCHP_PINGPONG_0_PER_REG_END                        0x03c010bc
+#define BCHP_PINGPONG_1_PER_REG_START                      0x03c010c0
+#define BCHP_PINGPONG_1_PER_REG_END                        0x03c010fc
+#define BCHP_PROFILE_0_PER_REG_START                       0x03c01100
+#define BCHP_PROFILE_0_PER_REG_END                         0x03c0111c
+#define BCHP_PROFILE_1_PER_REG_START                       0x03c01120
+#define BCHP_PROFILE_1_PER_REG_END                         0x03c0113c
+#define BCHP_PROFILE_2_PER_REG_START                       0x03c01140
+#define BCHP_PROFILE_2_PER_REG_END                         0x03c0115c
+#define BCHP_PROFILE_3_PER_REG_START                       0x03c01160
+#define BCHP_PROFILE_3_PER_REG_END                         0x03c0117c
+#define BCHP_PROFILE_4_PER_REG_START                       0x03c01180
+#define BCHP_PROFILE_4_PER_REG_END                         0x03c0119c
+#define BCHP_PROFILE_5_PER_REG_START                       0x03c011a0
+#define BCHP_PROFILE_5_PER_REG_END                         0x03c011bc
+#define BCHP_PROFILE_6_PER_REG_START                       0x03c011c0
+#define BCHP_PROFILE_6_PER_REG_END                         0x03c011dc
+#define BCHP_PROFILE_7_PER_REG_START                       0x03c011e0
+#define BCHP_PROFILE_7_PER_REG_END                         0x03c011fc
+#define BCHP_FIFO_0_PER_REG_START                          0x03c01200
+#define BCHP_FIFO_0_PER_REG_END                            0x03c013ff
+#define BCHP_FIFO_1_PER_REG_START                          0x03c01400
+#define BCHP_FIFO_1_PER_REG_END                            0x03c015ff
+#define BCHP_PERIPH_MISC_PER_REG_START                     0x03c02600
+#define BCHP_PERIPH_MISC_PER_REG_END                       0x03c026d0
+#define BCHP_PMB_MASTER_PER_REG_START                      0x03c03000
+#define BCHP_PMB_MASTER_PER_REG_END                        0x03c0300c
+#define BCHP_DTP_CFGCTL_PER_REG_START                      0x03c03100
+#define BCHP_DTP_CFGCTL_PER_REG_END                        0x03c0310c
+#define BCHP_DTP_RESERVED_PER_REG_START                    0x03c03110
+#define BCHP_DTP_RESERVED_PER_REG_END                      0x03c0311c
+#define BCHP_DTP_SOFTRESET_PER_REG_START                   0x03c03120
+#define BCHP_DTP_SOFTRESET_PER_REG_END                     0x03c03120
+#define BCHP_DTP_ZONE0_PER_REG_START                       0x03c03140
+#define BCHP_DTP_ZONE0_PER_REG_END                         0x03c0314c
+#define BCHP_DTP_ZONE1_PER_REG_START                       0x03c03150
+#define BCHP_DTP_ZONE1_PER_REG_END                         0x03c0315c
+#define BCHP_DTP_ZONE2_PER_REG_START                       0x03c03160
+#define BCHP_DTP_ZONE2_PER_REG_END                         0x03c0316c
+#define BCHP_DFAP_CFGCTL_PER_REG_START                     0x03c07100
+#define BCHP_DFAP_CFGCTL_PER_REG_END                       0x03c0710c
+#define BCHP_DFAP_RESERVED_PER_REG_START                   0x03c07110
+#define BCHP_DFAP_RESERVED_PER_REG_END                     0x03c0711c
+#define BCHP_DFAP_SOFTRESET_PER_REG_START                  0x03c07120
+#define BCHP_DFAP_SOFTRESET_PER_REG_END                    0x03c07120
+#define BCHP_DFAP_ZONE0_PER_REG_START                      0x03c07140
+#define BCHP_DFAP_ZONE0_PER_REG_END                        0x03c0714c
+#define BCHP_DFAP_ZONE1_PER_REG_START                      0x03c07150
+#define BCHP_DFAP_ZONE1_PER_REG_END                        0x03c0715c
+#define BCHP_DFAP_ZONE2_PER_REG_START                      0x03c07160
+#define BCHP_DFAP_ZONE2_PER_REG_END                        0x03c0716c
+#define BCHP_D3DSMAC32_CFGCTL_PER_REG_START                0x03c0b100
+#define BCHP_D3DSMAC32_CFGCTL_PER_REG_END                  0x03c0b10c
+#define BCHP_D3DSMAC32_RESERVED_PER_REG_START              0x03c0b110
+#define BCHP_D3DSMAC32_RESERVED_PER_REG_END                0x03c0b11c
+#define BCHP_D3DSMAC32_SOFTRESET_PER_REG_START             0x03c0b120
+#define BCHP_D3DSMAC32_SOFTRESET_PER_REG_END               0x03c0b120
+#define BCHP_D3DSMAC32_ZONE0_PER_REG_START                 0x03c0b140
+#define BCHP_D3DSMAC32_ZONE0_PER_REG_END                   0x03c0b14c
+#define BCHP_D3DSMAC32_ZONE1_PER_REG_START                 0x03c0b150
+#define BCHP_D3DSMAC32_ZONE1_PER_REG_END                   0x03c0b15c
+#define BCHP_D3DSMAC32_ZONE2_PER_REG_START                 0x03c0b160
+#define BCHP_D3DSMAC32_ZONE2_PER_REG_END                   0x03c0b16c
+#define BCHP_D3DSMAC32_ZONE3_PER_REG_START                 0x03c0b170
+#define BCHP_D3DSMAC32_ZONE3_PER_REG_END                   0x03c0b17c
+#define BCHP_D3DSMAC32_ZONE4_PER_REG_START                 0x03c0b180
+#define BCHP_D3DSMAC32_ZONE4_PER_REG_END                   0x03c0b18c
+#define BCHP_D3DSMAC32_ZONE5_PER_REG_START                 0x03c0b190
+#define BCHP_D3DSMAC32_ZONE5_PER_REG_END                   0x03c0b19c
+#define BCHP_DSMACOFDA_CFGCTL_PER_REG_START                0x03c0f100
+#define BCHP_DSMACOFDA_CFGCTL_PER_REG_END                  0x03c0f10c
+#define BCHP_DSMACOFDA_RESERVED_PER_REG_START              0x03c0f110
+#define BCHP_DSMACOFDA_RESERVED_PER_REG_END                0x03c0f11c
+#define BCHP_DSMACOFDA_SOFTRESET_PER_REG_START             0x03c0f120
+#define BCHP_DSMACOFDA_SOFTRESET_PER_REG_END               0x03c0f120
+#define BCHP_DSMACOFDA_ZONE0_PER_REG_START                 0x03c0f140
+#define BCHP_DSMACOFDA_ZONE0_PER_REG_END                   0x03c0f14c
+#define BCHP_DSMACSFDB_CFGCTL_PER_REG_START                0x03c13100
+#define BCHP_DSMACSFDB_CFGCTL_PER_REG_END                  0x03c1310c
+#define BCHP_DSMACSFDB_RESERVED_PER_REG_START              0x03c13110
+#define BCHP_DSMACSFDB_RESERVED_PER_REG_END                0x03c1311c
+#define BCHP_DSMACSFDB_SOFTRESET_PER_REG_START             0x03c13120
+#define BCHP_DSMACSFDB_SOFTRESET_PER_REG_END               0x03c13120
+#define BCHP_DSMACSFDB_ZONE0_PER_REG_START                 0x03c13140
+#define BCHP_DSMACSFDB_ZONE0_PER_REG_END                   0x03c1314c
+#define BCHP_UTP_CFGCTL_PER_REG_START                      0x03c17100
+#define BCHP_UTP_CFGCTL_PER_REG_END                        0x03c1710c
+#define BCHP_UTP_RESERVED_PER_REG_START                    0x03c17110
+#define BCHP_UTP_RESERVED_PER_REG_END                      0x03c1711c
+#define BCHP_UTP_SOFTRESET_PER_REG_START                   0x03c17120
+#define BCHP_UTP_SOFTRESET_PER_REG_END                     0x03c17120
+#define BCHP_UTP_ZONE0_PER_REG_START                       0x03c17140
+#define BCHP_UTP_ZONE0_PER_REG_END                         0x03c1714c
+#define BCHP_UTP_ZONE1_PER_REG_START                       0x03c17150
+#define BCHP_UTP_ZONE1_PER_REG_END                         0x03c1715c
+#define BCHP_UTP_ZONE2_PER_REG_START                       0x03c17160
+#define BCHP_UTP_ZONE2_PER_REG_END                         0x03c1716c
+#define BCHP_UTP_ZONE3_PER_REG_START                       0x03c17170
+#define BCHP_UTP_ZONE3_PER_REG_END                         0x03c1717c
+#define BCHP_UTP_ZONE4_PER_REG_START                       0x03c17180
+#define BCHP_UTP_ZONE4_PER_REG_END                         0x03c1718c
+#define BCHP_PERIPH_CFGCTL_PER_REG_START                   0x03c1b100
+#define BCHP_PERIPH_CFGCTL_PER_REG_END                     0x03c1b10c
+#define BCHP_PERIPH_RESERVED_PER_REG_START                 0x03c1b110
+#define BCHP_PERIPH_RESERVED_PER_REG_END                   0x03c1b11c
+#define BCHP_PERIPH_SOFTRESET_PER_REG_START                0x03c1b120
+#define BCHP_PERIPH_SOFTRESET_PER_REG_END                  0x03c1b120
+#define BCHP_PERIPH_ZONE0_PER_REG_START                    0x03c1b140
+#define BCHP_PERIPH_ZONE0_PER_REG_END                      0x03c1b14c
+#define BCHP_PERIPH_ZONE1_PER_REG_START                    0x03c1b150
+#define BCHP_PERIPH_ZONE1_PER_REG_END                      0x03c1b15c
+#define BCHP_PERIPH_ZONE2_PER_REG_START                    0x03c1b160
+#define BCHP_PERIPH_ZONE2_PER_REG_END                      0x03c1b16c
+#define BCHP_FPM_CFGCTL_PER_REG_START                      0x03c1f100
+#define BCHP_FPM_CFGCTL_PER_REG_END                        0x03c1f10c
+#define BCHP_FPM_RESERVED_PER_REG_START                    0x03c1f110
+#define BCHP_FPM_RESERVED_PER_REG_END                      0x03c1f11c
+#define BCHP_FPM_SOFTRESET_PER_REG_START                   0x03c1f120
+#define BCHP_FPM_SOFTRESET_PER_REG_END                     0x03c1f120
+#define BCHP_FPM_ZONE0_PER_REG_START                       0x03c1f140
+#define BCHP_FPM_ZONE0_PER_REG_END                         0x03c1f14c
+#define BCHP_CPUC_CFGCTL_PER_REG_START                     0x03c23100
+#define BCHP_CPUC_CFGCTL_PER_REG_END                       0x03c2310c
+#define BCHP_CPUC_RESERVED_PER_REG_START                   0x03c23110
+#define BCHP_CPUC_RESERVED_PER_REG_END                     0x03c2311c
+#define BCHP_CPUC_SOFTRESET_PER_REG_START                  0x03c23120
+#define BCHP_CPUC_SOFTRESET_PER_REG_END                    0x03c23120
+#define BCHP_CPUC_ZONE0_PER_REG_START                      0x03c23140
+#define BCHP_CPUC_ZONE0_PER_REG_END                        0x03c2314c
+#define BCHP_APM_CFGCTL_PER_REG_START                      0x03c2b100
+#define BCHP_APM_CFGCTL_PER_REG_END                        0x03c2b10c
+#define BCHP_APM_RESERVED_PER_REG_START                    0x03c2b110
+#define BCHP_APM_RESERVED_PER_REG_END                      0x03c2b11c
+#define BCHP_APM_SOFTRESET_PER_REG_START                   0x03c2b120
+#define BCHP_APM_SOFTRESET_PER_REG_END                     0x03c2b120
+#define BCHP_APM_ZONE0_PER_REG_START                       0x03c2b140
+#define BCHP_APM_ZONE0_PER_REG_END                         0x03c2b14c
+#define BCHP_APM_ZONE1_PER_REG_START                       0x03c2b150
+#define BCHP_APM_ZONE1_PER_REG_END                         0x03c2b15c
+#define BCHP_APM_ZONE2_PER_REG_START                       0x03c2b160
+#define BCHP_APM_ZONE2_PER_REG_END                         0x03c2b16c
+#define BCHP_APM_ZONE3_PER_REG_START                       0x03c2b170
+#define BCHP_APM_ZONE3_PER_REG_END                         0x03c2b17c
+#define BCHP_APM_ZONE4_PER_REG_START                       0x03c2b180
+#define BCHP_APM_ZONE4_PER_REG_END                         0x03c2b18c
+#define BCHP_APM_ZONE5_PER_REG_START                       0x03c2b190
+#define BCHP_APM_ZONE5_PER_REG_END                         0x03c2b19c
+#define BCHP_UNIMAC_CFGCTL_PER_REG_START                   0x03c2f100
+#define BCHP_UNIMAC_CFGCTL_PER_REG_END                     0x03c2f10c
+#define BCHP_UNIMAC_RESERVED_PER_REG_START                 0x03c2f110
+#define BCHP_UNIMAC_RESERVED_PER_REG_END                   0x03c2f11c
+#define BCHP_UNIMAC_SOFTRESET_PER_REG_START                0x03c2f120
+#define BCHP_UNIMAC_SOFTRESET_PER_REG_END                  0x03c2f120
+#define BCHP_UNIMAC_ZONE0_PER_REG_START                    0x03c2f140
+#define BCHP_UNIMAC_ZONE0_PER_REG_END                      0x03c2f14c
+#define BCHP_USMAC_CFGCTL_PER_REG_START                    0x03c33100
+#define BCHP_USMAC_CFGCTL_PER_REG_END                      0x03c3310c
+#define BCHP_USMAC_RESERVED_PER_REG_START                  0x03c33110
+#define BCHP_USMAC_RESERVED_PER_REG_END                    0x03c3311c
+#define BCHP_USMAC_SOFTRESET_PER_REG_START                 0x03c33120
+#define BCHP_USMAC_SOFTRESET_PER_REG_END                   0x03c33120
+#define BCHP_USMAC_ZONE0_PER_REG_START                     0x03c33140
+#define BCHP_USMAC_ZONE0_PER_REG_END                       0x03c3314c
+#define BCHP_USMAC_ZONE1_PER_REG_START                     0x03c33150
+#define BCHP_USMAC_ZONE1_PER_REG_END                       0x03c3315c
+#define BCHP_USMAC_ZONE2_PER_REG_START                     0x03c33160
+#define BCHP_USMAC_ZONE2_PER_REG_END                       0x03c3316c
+#define BCHP_USMAC_ZONE3_PER_REG_START                     0x03c33170
+#define BCHP_USMAC_ZONE3_PER_REG_END                       0x03c3317c
+#define BCHP_USMAC_ZONE4_PER_REG_START                     0x03c33180
+#define BCHP_USMAC_ZONE4_PER_REG_END                       0x03c3318c
+#define BCHP_USMAC_ZONE5_PER_REG_START                     0x03c33190
+#define BCHP_USMAC_ZONE5_PER_REG_END                       0x03c3319c
+#define BCHP_USMAC_ZONE6_PER_REG_START                     0x03c331a0
+#define BCHP_USMAC_ZONE6_PER_REG_END                       0x03c331ac
+#define BCHP_USMAC_ZONE7_PER_REG_START                     0x03c331b0
+#define BCHP_USMAC_ZONE7_PER_REG_END                       0x03c331bc
+#define BCHP_USMAC_ZONE8_PER_REG_START                     0x03c331c0
+#define BCHP_USMAC_ZONE8_PER_REG_END                       0x03c331cc
+#define BCHP_USMAC_ZONE9_PER_REG_START                     0x03c331d0
+#define BCHP_USMAC_ZONE9_PER_REG_END                       0x03c331dc
+#define BCHP_USMAC_ZONE10_PER_REG_START                    0x03c331e0
+#define BCHP_USMAC_ZONE10_PER_REG_END                      0x03c331ec
+#define BCHP_USMAC_ZONE11_PER_REG_START                    0x03c331f0
+#define BCHP_USMAC_ZONE11_PER_REG_END                      0x03c331fc
+#define BCHP_USMAC_ZONE12_PER_REG_START                    0x03c33200
+#define BCHP_USMAC_ZONE12_PER_REG_END                      0x03c3320c
+#define BCHP_TC8X_CFGCTL_PER_REG_START                     0x03c37100
+#define BCHP_TC8X_CFGCTL_PER_REG_END                       0x03c3710c
+#define BCHP_TC8X_RESERVED_PER_REG_START                   0x03c37110
+#define BCHP_TC8X_RESERVED_PER_REG_END                     0x03c3711c
+#define BCHP_TC8X_SOFTRESET_PER_REG_START                  0x03c37120
+#define BCHP_TC8X_SOFTRESET_PER_REG_END                    0x03c37120
+#define BCHP_TC8X_ZONE0_PER_REG_START                      0x03c37140
+#define BCHP_TC8X_ZONE0_PER_REG_END                        0x03c3714c
+#define BCHP_TC8X_ZONE1_PER_REG_START                      0x03c37150
+#define BCHP_TC8X_ZONE1_PER_REG_END                        0x03c3715c
+#define BCHP_TC8X_ZONE2_PER_REG_START                      0x03c37160
+#define BCHP_TC8X_ZONE2_PER_REG_END                        0x03c3716c
+#define BCHP_TC8X_ZONE3_PER_REG_START                      0x03c37170
+#define BCHP_TC8X_ZONE3_PER_REG_END                        0x03c3717c
+#define BCHP_TC8X_ZONE4_PER_REG_START                      0x03c37180
+#define BCHP_TC8X_ZONE4_PER_REG_END                        0x03c3718c
+#define BCHP_TC8X_ZONE5_PER_REG_START                      0x03c37190
+#define BCHP_TC8X_ZONE5_PER_REG_END                        0x03c3719c
+#define BCHP_TC8X_ZONE6_PER_REG_START                      0x03c371a0
+#define BCHP_TC8X_ZONE6_PER_REG_END                        0x03c371ac
+#define BCHP_TC8X_ZONE7_PER_REG_START                      0x03c371b0
+#define BCHP_TC8X_ZONE7_PER_REG_END                        0x03c371bc
+#define BCHP_TC8X_ZONE8_PER_REG_START                      0x03c371c0
+#define BCHP_TC8X_ZONE8_PER_REG_END                        0x03c371cc
+#define BCHP_TCOFDM_CFGCTL_PER_REG_START                   0x03c3b100
+#define BCHP_TCOFDM_CFGCTL_PER_REG_END                     0x03c3b10c
+#define BCHP_TCOFDM_RESERVED_PER_REG_START                 0x03c3b110
+#define BCHP_TCOFDM_RESERVED_PER_REG_END                   0x03c3b11c
+#define BCHP_TCOFDM_SOFTRESET_PER_REG_START                0x03c3b120
+#define BCHP_TCOFDM_SOFTRESET_PER_REG_END                  0x03c3b120
+#define BCHP_TCOFDM_ZONE0_PER_REG_START                    0x03c3b140
+#define BCHP_TCOFDM_ZONE0_PER_REG_END                      0x03c3b14c
+#define BCHP_TCOFDM_ZONE1_PER_REG_START                    0x03c3b150
+#define BCHP_TCOFDM_ZONE1_PER_REG_END                      0x03c3b15c
+#define BCHP_TCOFDM_ZONE2_PER_REG_START                    0x03c3b160
+#define BCHP_TCOFDM_ZONE2_PER_REG_END                      0x03c3b16c
+#define BCHP_TCOFDM_ZONE3_PER_REG_START                    0x03c3b170
+#define BCHP_TCOFDM_ZONE3_PER_REG_END                      0x03c3b17c
+#define BCHP_TCOFDM_ZONE4_PER_REG_START                    0x03c3b180
+#define BCHP_TCOFDM_ZONE4_PER_REG_END                      0x03c3b18c
+#define BCHP_MIPS_CFGCTL_PER_REG_START                     0x03c43100
+#define BCHP_MIPS_CFGCTL_PER_REG_END                       0x03c4310c
+#define BCHP_MIPS_RESERVED_PER_REG_START                   0x03c43110
+#define BCHP_MIPS_RESERVED_PER_REG_END                     0x03c4311c
+#define BCHP_MIPS_SOFTRESET_PER_REG_START                  0x03c43120
+#define BCHP_MIPS_SOFTRESET_PER_REG_END                    0x03c43120
+#define BCHP_MIPS_ZONE0_PER_REG_START                      0x03c43140
+#define BCHP_MIPS_ZONE0_PER_REG_END                        0x03c4314c
+#define BCHP_USTOP_CFGCTL_PER_REG_START                    0x03c47100
+#define BCHP_USTOP_CFGCTL_PER_REG_END                      0x03c4710c
+#define BCHP_USTOP_RESERVED_PER_REG_START                  0x03c47110
+#define BCHP_USTOP_RESERVED_PER_REG_END                    0x03c4711c
+#define BCHP_USTOP_SOFTRESET_PER_REG_START                 0x03c47120
+#define BCHP_USTOP_SOFTRESET_PER_REG_END                   0x03c47120
+#define BCHP_USTOP_ZONE0_PER_REG_START                     0x03c47140
+#define BCHP_USTOP_ZONE0_PER_REG_END                       0x03c4714c
+#define BCHP_LEAP_CFGCTL_PER_REG_START                     0x03c4b100
+#define BCHP_LEAP_CFGCTL_PER_REG_END                       0x03c4b10c
+#define BCHP_LEAP_RESERVED_PER_REG_START                   0x03c4b110
+#define BCHP_LEAP_RESERVED_PER_REG_END                     0x03c4b11c
+#define BCHP_LEAP_SOFTRESET_PER_REG_START                  0x03c4b120
+#define BCHP_LEAP_SOFTRESET_PER_REG_END                    0x03c4b120
+#define BCHP_LEAP_ZONE0_PER_REG_START                      0x03c4b140
+#define BCHP_LEAP_ZONE0_PER_REG_END                        0x03c4b14c
+#define BCHP_EMC_CFGCTL_PER_REG_START                      0x03c4f100
+#define BCHP_EMC_CFGCTL_PER_REG_END                        0x03c4f10c
+#define BCHP_EMC_RESERVED_PER_REG_START                    0x03c4f110
+#define BCHP_EMC_RESERVED_PER_REG_END                      0x03c4f11c
+#define BCHP_EMC_SOFTRESET_PER_REG_START                   0x03c4f120
+#define BCHP_EMC_SOFTRESET_PER_REG_END                     0x03c4f120
+#define BCHP_EMC_ZONE0_PER_REG_START                       0x03c4f140
+#define BCHP_EMC_ZONE0_PER_REG_END                         0x03c4f14c
+#define BCHP_CNTLERRPORT_PERIPH_REG_START                  0x03e00000
+#define BCHP_CNTLERRPORT_PERIPH_REG_END                    0x03e000e4
+#define BCHP_REQA0_PERIPH_REG_START                        0x03e00400
+#define BCHP_REQA0_PERIPH_REG_END                          0x03e0048c
+#define BCHP_REPA0_PERIPH_REG_START                        0x03e00500
+#define BCHP_REPA0_PERIPH_REG_END                          0x03e0058c
+#define BCHP_REQA1_PERIPH_REG_START                        0x03e00600
+#define BCHP_REQA1_PERIPH_REG_END                          0x03e0068c
+#define BCHP_REPA1_PERIPH_REG_START                        0x03e00700
+#define BCHP_REPA1_PERIPH_REG_END                          0x03e0078c
+#define BCHP_REQB0_PERIPH_REG_START                        0x03e00800
+#define BCHP_REQB0_PERIPH_REG_END                          0x03e0088c
+#define BCHP_REPB0_PERIPH_REG_START                        0x03e00900
+#define BCHP_REPB0_PERIPH_REG_END                          0x03e0098c
+#define BCHP_REQB1_PERIPH_REG_START                        0x03e00a00
+#define BCHP_REQB1_PERIPH_REG_END                          0x03e00a8c
+#define BCHP_REPB1_PERIPH_REG_START                        0x03e00b00
+#define BCHP_REPB1_PERIPH_REG_END                          0x03e00b8c
+#define BCHP_REQC0_PERIPH_REG_START                        0x03e00c00
+#define BCHP_REQC0_PERIPH_REG_END                          0x03e00c8c
+#define BCHP_REPC0_PERIPH_REG_START                        0x03e00d00
+#define BCHP_REPC0_PERIPH_REG_END                          0x03e00d8c
+#define BCHP_REQC1_PERIPH_REG_START                        0x03e00e00
+#define BCHP_REQC1_PERIPH_REG_END                          0x03e00e8c
+#define BCHP_REPC1_PERIPH_REG_START                        0x03e00f00
+#define BCHP_REPC1_PERIPH_REG_END                          0x03e00f8c
+#define BCHP_SWITCH_CORE_REG_START                         0x04e00000
+#define BCHP_SWITCH_CORE_REG_END                           0x04e38110
+#define BCHP_SWITCH_REG_REG_START                          0x04e40000
+#define BCHP_SWITCH_REG_REG_END                            0x04e401b4
+#define BCHP_SWITCH_INDIR_RW_REG_START                     0x04e40300
+#define BCHP_SWITCH_INDIR_RW_REG_END                       0x04e40314
+#define BCHP_SWITCH_INTRL2_0_REG_START                     0x04e40340
+#define BCHP_SWITCH_INTRL2_0_REG_END                       0x04e4036c
+#define BCHP_SWITCH_INTRL2_1_REG_START                     0x04e40380
+#define BCHP_SWITCH_INTRL2_1_REG_END                       0x04e403ac
+#define BCHP_SWITCH_MDIO_REG_START                         0x04e403c0
+#define BCHP_SWITCH_MDIO_REG_END                           0x04e403c4
+#define BCHP_SWITCH_FCB_REG_START                          0x04e40400
+#define BCHP_SWITCH_FCB_REG_END                            0x04e40430
+#define BCHP_SWITCH_ACB_REG_START                          0x04e40600
+#define BCHP_SWITCH_ACB_REG_END                            0x04e40804
+#define BCHP_MEM_COMMON_1_REG_START                        0x05000000
+#define BCHP_MEM_COMMON_1_REG_END                          0x05000004
+#define BCHP_MEM_PRIVATE_1_REG_START                       0x05010000
+#define BCHP_MEM_PRIVATE_1_REG_END                         0x05010004
+#define BCHP_MEM_INST_MAIN_1_REG_START                     0x05020000
+#define BCHP_MEM_INST_MAIN_1_REG_END                       0x05020000
+#define BCHP_MEM_CNTXT_MAIN_1_REG_START                    0x05028000
+#define BCHP_MEM_CNTXT_MAIN_1_REG_END                      0x05028000
+#define BCHP_MEM_PRED_MAIN_1_REG_START                     0x0502c000
+#define BCHP_MEM_PRED_MAIN_1_REG_END                       0x0502c37e
+#define BCHP_MEM_INST_PICO_1_REG_START                     0x05030000
+#define BCHP_MEM_INST_PICO_1_REG_END                       0x05030000
+#define BCHP_MEM_CNTXT_PICO_1_REG_START                    0x05038000
+#define BCHP_MEM_CNTXT_PICO_1_REG_END                      0x05038000
+#define BCHP_MEM_PRED_PICO_1_REG_START                     0x0503c000
+#define BCHP_MEM_PRED_PICO_1_REG_END                       0x0503c1fe
+#define BCHP_MEM_COMMON_2_REG_START                        0x05040000
+#define BCHP_MEM_COMMON_2_REG_END                          0x05040004
+#define BCHP_MEM_PRIVATE_2_REG_START                       0x05050000
+#define BCHP_MEM_PRIVATE_2_REG_END                         0x05050004
+#define BCHP_MEM_INST_MAIN_2_REG_START                     0x05060000
+#define BCHP_MEM_INST_MAIN_2_REG_END                       0x05060000
+#define BCHP_MEM_CNTXT_MAIN_2_REG_START                    0x05068000
+#define BCHP_MEM_CNTXT_MAIN_2_REG_END                      0x05068000
+#define BCHP_MEM_PRED_MAIN_2_REG_START                     0x0506c000
+#define BCHP_MEM_PRED_MAIN_2_REG_END                       0x0506c37e
+#define BCHP_MEM_INST_PICO_2_REG_START                     0x05070000
+#define BCHP_MEM_INST_PICO_2_REG_END                       0x05070000
+#define BCHP_MEM_CNTXT_PICO_2_REG_START                    0x05078000
+#define BCHP_MEM_CNTXT_PICO_2_REG_END                      0x05078000
+#define BCHP_MEM_PRED_PICO_2_REG_START                     0x0507c000
+#define BCHP_MEM_PRED_PICO_2_REG_END                       0x0507c1fe
+#define BCHP_CFG_REGS_1_REG_START                          0x05099000
+#define BCHP_CFG_REGS_1_REG_END                            0x050991c8
+#define BCHP_DBG_REGS_1_REG_START                          0x050991d0
+#define BCHP_DBG_REGS_1_REG_END                            0x050992b8
+#define BCHP_CFG_REGS_2_REG_START                          0x0509a000
+#define BCHP_CFG_REGS_2_REG_END                            0x0509a1c8
+#define BCHP_DBG_REGS_2_REG_START                          0x0509a1d0
+#define BCHP_DBG_REGS_2_REG_END                            0x0509a2b8
+#define BCHP_MEM_ENTRY_REG_START                           0x050a0000
+#define BCHP_MEM_ENTRY_REG_END                             0x050a0000
+#define BCHP_CONFIGURATIONS_REG_START                      0x050c0000
+#define BCHP_CONFIGURATIONS_REG_END                        0x050c001c
+#define BCHP_PM_COUNTERS_REG_START                         0x050c0100
+#define BCHP_PM_COUNTERS_REG_END                           0x050c01fc
+#define BCHP_DEBUG_REG_START                               0x050c0200
+#define BCHP_DEBUG_REG_END                                 0x050c0208
+#define B0_BCHP_REGS_REG_START                             0x050c4000
+#define B0_BCHP_REGS_REG_END                               0x050c4130
+#define BCHP_REGS_REG_START                                0x050c8000
+#define BCHP_REGS_REG_END                                  0x050c81a8
+#define BCHP_LOOKUP_CONFIGURATION_REG_START                0x050d0000
+#define BCHP_LOOKUP_CONFIGURATION_REG_END                  0x050d0250
+#define BCHP_PARSER_CORE_CONFIGURATION_REG_START           0x050d0400
+#define BCHP_PARSER_CORE_CONFIGURATION_REG_END             0x050d0560
+#define BCHP_GENERAL_CONFIGURATION_REG_START               0x050d0800
+#define BCHP_GENERAL_CONFIGURATION_REG_END                 0x050d0ad0
+#define BCHP_CONFIG_DMA_REGS_1_REG_START                   0x050d1000
+#define BCHP_CONFIG_DMA_REGS_1_REG_END                     0x050d10a8
+#define BCHP_DEBUG_DMA_REGS_1_REG_START                    0x050d1100
+#define BCHP_DEBUG_DMA_REGS_1_REG_END                      0x050d1218
+#define BCHP_CONFIG_DMA_REGS_2_REG_START                   0x050d1800
+#define BCHP_CONFIG_DMA_REGS_2_REG_END                     0x050d18a8
+#define BCHP_DEBUG_DMA_REGS_2_REG_START                    0x050d1900
+#define BCHP_DEBUG_DMA_REGS_2_REG_END                      0x050d1a18
+#define BCHP_BRDG_REG_UBUS_MASTER_1_REG_START              0x050d2000
+#define BCHP_BRDG_REG_UBUS_MASTER_1_REG_END                0x050d2014
+#define BCHP_BRDG_REG_UBUS_MASTER_2_REG_START              0x050d2400
+#define BCHP_BRDG_REG_UBUS_MASTER_2_REG_END                0x050d2414
+#define BCHP_BRDG_REG_UBUS_MASTER_3_REG_START              0x050d2800
+#define BCHP_BRDG_REG_UBUS_MASTER_3_REG_END                0x050d2814
+#define B0_BCHP_BRDG_REG_REG_START                         0x050d2c00
+#define B0_BCHP_BRDG_REG_REG_END                           0x050d2c08
+#define BCHP_EGPHY_REG_START                               0x050d3000
+#define BCHP_EGPHY_REG_END                                 0x050d3014
+#define BCHP_BRDG_REG_REG_START                            0x050d3c00
+#define BCHP_BRDG_REG_REG_END                              0x050d3c14
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_0_REG_START         0x050d4000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_0_REG_END           0x050d464c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_1_REG_START         0x050d5000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_1_REG_END           0x050d564c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_2_REG_START         0x050d6000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_2_REG_END           0x050d664c
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_0Module_REG_START 0x050da000
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_0Module_REG_END 0x050da180
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_1Module_REG_START 0x050da400
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_1Module_REG_END 0x050da580
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_2Module_REG_START 0x050da800
+#define BCHP_UNIMAC_CONFIGURATION_UMAC_MIB_2Module_REG_END 0x050da980
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_1_REG_START            0x050db800
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_1_REG_END              0x050db820
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_2_REG_START            0x050dbc00
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_2_REG_END              0x050dbc20
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_3_REG_START            0x050dc000
+#define BCHP_UNIMAC_MISC_UNIMAC_TOP_3_REG_END              0x050dc020
+#define BCHP_GENERAL_CONFIGURATION_RX_1_REG_START          0x050de000
+#define BCHP_GENERAL_CONFIGURATION_RX_1_REG_END            0x050de094
+#define BCHP_PM_COUNTERS_RX_1_REG_START                    0x050de100
+#define BCHP_PM_COUNTERS_RX_1_REG_END                      0x050de144
+#define BCHP_DEBUG_RX_1_REG_START                          0x050de200
+#define BCHP_DEBUG_RX_1_REG_END                            0x050de2cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_1_REG_START           0x050de400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_1_REG_END             0x050de7fc
+#define BCHP_GENERAL_CONFIGURATION_RX_2_REG_START          0x050de800
+#define BCHP_GENERAL_CONFIGURATION_RX_2_REG_END            0x050de894
+#define BCHP_PM_COUNTERS_RX_2_REG_START                    0x050de900
+#define BCHP_PM_COUNTERS_RX_2_REG_END                      0x050de944
+#define BCHP_DEBUG_RX_2_REG_START                          0x050dea00
+#define BCHP_DEBUG_RX_2_REG_END                            0x050deacc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_2_REG_START           0x050dec00
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_2_REG_END             0x050deffc
+#define BCHP_GENERAL_CONFIGURATION_RX_3_REG_START          0x050df000
+#define BCHP_GENERAL_CONFIGURATION_RX_3_REG_END            0x050df094
+#define BCHP_PM_COUNTERS_RX_3_REG_START                    0x050df100
+#define BCHP_PM_COUNTERS_RX_3_REG_END                      0x050df144
+#define BCHP_DEBUG_RX_3_REG_START                          0x050df200
+#define BCHP_DEBUG_RX_3_REG_END                            0x050df2cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_3_REG_START           0x050df400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_3_REG_END             0x050df7fc
+#define BCHP_GENERAL_CONFIGURATION_RX_4_REG_START          0x050e1000
+#define BCHP_GENERAL_CONFIGURATION_RX_4_REG_END            0x050e1094
+#define BCHP_PM_COUNTERS_RX_4_REG_START                    0x050e1100
+#define BCHP_PM_COUNTERS_RX_4_REG_END                      0x050e1144
+#define BCHP_DEBUG_RX_4_REG_START                          0x050e1200
+#define BCHP_DEBUG_RX_4_REG_END                            0x050e12cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_4_REG_START           0x050e1400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_4_REG_END             0x050e17fc
+#define BCHP_GENERAL_CONFIGURATION_RX_5_REG_START          0x050e2000
+#define BCHP_GENERAL_CONFIGURATION_RX_5_REG_END            0x050e2094
+#define BCHP_PM_COUNTERS_RX_5_REG_START                    0x050e2100
+#define BCHP_PM_COUNTERS_RX_5_REG_END                      0x050e2144
+#define BCHP_DEBUG_RX_5_REG_START                          0x050e2200
+#define BCHP_DEBUG_RX_5_REG_END                            0x050e22cc
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_5_REG_START           0x050e2400
+#define BCHP_PER_FLOW_PM_COUNTERS_RX_5_REG_END             0x050e27fc
+#define BCHP_CONFIGURATIONS_TX_1_REG_START                 0x050e8000
+#define BCHP_CONFIGURATIONS_TX_1_REG_END                   0x050e8098
+#define BCHP_DEBUG_TX_1_REG_START                          0x050e8100
+#define BCHP_DEBUG_TX_1_REG_END                            0x050e81ec
+#define BCHP_PD_FIFO_TX_1_REG_START                        0x050e8200
+#define BCHP_PD_FIFO_TX_1_REG_END                          0x050e85fc
+#define BCHP_CONTEXT_TX_1_REG_START                        0x050e8600
+#define BCHP_CONTEXT_TX_1_REG_END                          0x050e869c
+#define BCHP_EPON_PD_FIFO_TX_1_REG_START                   0x050e8700
+#define BCHP_EPON_PD_FIFO_TX_1_REG_END                     0x050e8efc
+#define BCHP_EPON_CFG_TX_1_REG_START                       0x050e9000
+#define BCHP_EPON_CFG_TX_1_REG_END                         0x050e9054
+#define BCHP_EPON_DBG_TX_1_REG_START                       0x050e9100
+#define BCHP_EPON_DBG_TX_1_REG_END                         0x050e9204
+#define BCHP_EPON_STS_FIFO_TX_1_REG_START                  0x050e9700
+#define BCHP_EPON_STS_FIFO_TX_1_REG_END                    0x050e9efc
+#define BCHP_CONFIGURATIONS_TX_2_REG_START                 0x050ea000
+#define BCHP_CONFIGURATIONS_TX_2_REG_END                   0x050ea098
+#define BCHP_DEBUG_TX_2_REG_START                          0x050ea100
+#define BCHP_DEBUG_TX_2_REG_END                            0x050ea1ec
+#define BCHP_PD_FIFO_TX_2_REG_START                        0x050ea200
+#define BCHP_PD_FIFO_TX_2_REG_END                          0x050ea5fc
+#define BCHP_CONTEXT_TX_2_REG_START                        0x050ea600
+#define BCHP_CONTEXT_TX_2_REG_END                          0x050ea69c
+#define BCHP_EPON_PD_FIFO_TX_2_REG_START                   0x050ea700
+#define BCHP_EPON_PD_FIFO_TX_2_REG_END                     0x050eaefc
+#define BCHP_EPON_CFG_TX_2_REG_START                       0x050eb000
+#define BCHP_EPON_CFG_TX_2_REG_END                         0x050eb054
+#define BCHP_EPON_DBG_TX_2_REG_START                       0x050eb100
+#define BCHP_EPON_DBG_TX_2_REG_END                         0x050eb204
+#define BCHP_EPON_STS_FIFO_TX_2_REG_START                  0x050eb700
+#define BCHP_EPON_STS_FIFO_TX_2_REG_END                    0x050ebefc
+#define BCHP_CONFIGURATIONS_TX_3_REG_START                 0x050ec000
+#define BCHP_CONFIGURATIONS_TX_3_REG_END                   0x050ec098
+#define BCHP_DEBUG_TX_3_REG_START                          0x050ec100
+#define BCHP_DEBUG_TX_3_REG_END                            0x050ec1ec
+#define BCHP_PD_FIFO_TX_3_REG_START                        0x050ec200
+#define BCHP_PD_FIFO_TX_3_REG_END                          0x050ec5fc
+#define BCHP_CONTEXT_TX_3_REG_START                        0x050ec600
+#define BCHP_CONTEXT_TX_3_REG_END                          0x050ec69c
+#define BCHP_EPON_PD_FIFO_TX_3_REG_START                   0x050ec700
+#define BCHP_EPON_PD_FIFO_TX_3_REG_END                     0x050ecefc
+#define BCHP_EPON_CFG_TX_3_REG_START                       0x050ed000
+#define BCHP_EPON_CFG_TX_3_REG_END                         0x050ed054
+#define BCHP_EPON_DBG_TX_3_REG_START                       0x050ed100
+#define BCHP_EPON_DBG_TX_3_REG_END                         0x050ed204
+#define BCHP_EPON_STS_FIFO_TX_3_REG_START                  0x050ed700
+#define BCHP_EPON_STS_FIFO_TX_3_REG_END                    0x050edefc
+#define BCHP_CONFIGURATIONS_TX_4_REG_START                 0x050f4000
+#define BCHP_CONFIGURATIONS_TX_4_REG_END                   0x050f4098
+#define BCHP_DEBUG_TX_4_REG_START                          0x050f4100
+#define BCHP_DEBUG_TX_4_REG_END                            0x050f41ec
+#define BCHP_PD_FIFO_TX_4_REG_START                        0x050f4200
+#define BCHP_PD_FIFO_TX_4_REG_END                          0x050f45fc
+#define BCHP_CONTEXT_TX_4_REG_START                        0x050f4600
+#define BCHP_CONTEXT_TX_4_REG_END                          0x050f469c
+#define BCHP_EPON_PD_FIFO_TX_4_REG_START                   0x050f4700
+#define BCHP_EPON_PD_FIFO_TX_4_REG_END                     0x050f4efc
+#define BCHP_EPON_CFG_TX_4_REG_START                       0x050f5000
+#define BCHP_EPON_CFG_TX_4_REG_END                         0x050f5054
+#define BCHP_EPON_DBG_TX_4_REG_START                       0x050f5100
+#define BCHP_EPON_DBG_TX_4_REG_END                         0x050f5204
+#define BCHP_EPON_STS_FIFO_TX_4_REG_START                  0x050f5700
+#define BCHP_EPON_STS_FIFO_TX_4_REG_END                    0x050f5efc
+#define BCHP_CONFIGURATIONS_TX_5_REG_START                 0x050f6000
+#define BCHP_CONFIGURATIONS_TX_5_REG_END                   0x050f6098
+#define BCHP_DEBUG_TX_5_REG_START                          0x050f6100
+#define BCHP_DEBUG_TX_5_REG_END                            0x050f61ec
+#define BCHP_PD_FIFO_TX_5_REG_START                        0x050f6200
+#define BCHP_PD_FIFO_TX_5_REG_END                          0x050f65fc
+#define BCHP_CONTEXT_TX_5_REG_START                        0x050f6600
+#define BCHP_CONTEXT_TX_5_REG_END                          0x050f669c
+#define BCHP_EPON_PD_FIFO_TX_5_REG_START                   0x050f6700
+#define BCHP_EPON_PD_FIFO_TX_5_REG_END                     0x050f6efc
+#define BCHP_EPON_CFG_TX_5_REG_START                       0x050f7000
+#define BCHP_EPON_CFG_TX_5_REG_END                         0x050f7054
+#define BCHP_EPON_DBG_TX_5_REG_START                       0x050f7100
+#define BCHP_EPON_DBG_TX_5_REG_END                         0x050f7204
+#define BCHP_EPON_STS_FIFO_TX_5_REG_START                  0x050f7700
+#define BCHP_EPON_STS_FIFO_TX_5_REG_END                    0x050f7efc
+#define BCHP_NATCACHE_REG_START                            0x050fc000
+#define BCHP_NATCACHE_REG_END                              0x050fc2b0
+#define BCHP_NATCACHE_INDIR_RW_REG_START                   0x050fc400
+#define BCHP_NATCACHE_INDIR_RW_REG_END                     0x050fc45c
+#define BCHP_GisbWindow0_REG_START                         0x07c00000
+#define BCHP_GisbWindow0_REG_END                           0x07c7fffc
+#define BCHP_GisbWindow1_REG_START                         0x07c80000
+#define BCHP_GisbWindow1_REG_END                           0x07cffffc
+#define BCHP_GisbWindow2_REG_START                         0x07d00000
+#define BCHP_GisbWindow2_REG_END                           0x07d7fffc
+#define BCHP_GisbWindow3_REG_START                         0x07d80000
+#define BCHP_GisbWindow3_REG_END                           0x07dfeffc
+#define BCHP_U2G_REGS_REG_START                            0x07dff000
+#define BCHP_U2G_REGS_REG_END                              0x07dff048
+#define BCHP_CNTLERRPORT_G2U_REG_START                     0x07e00000
+#define BCHP_CNTLERRPORT_G2U_REG_END                       0x07e000e4
+#define BCHP_REQA0_G2U_REG_START                           0x07e00400
+#define BCHP_REQA0_G2U_REG_END                             0x07e0048c
+#define BCHP_REPA0_G2U_REG_START                           0x07e00500
+#define BCHP_REPA0_G2U_REG_END                             0x07e0058c
+#define BCHP_REQA1_G2U_REG_START                           0x07e00600
+#define BCHP_REQA1_G2U_REG_END                             0x07e0068c
+#define BCHP_REPA1_G2U_REG_START                           0x07e00700
+#define BCHP_REPA1_G2U_REG_END                             0x07e0078c
+#define BCHP_REQB0_G2U_REG_START                           0x07e00800
+#define BCHP_REQB0_G2U_REG_END                             0x07e0088c
+#define BCHP_REPB0_G2U_REG_START                           0x07e00900
+#define BCHP_REPB0_G2U_REG_END                             0x07e0098c
+#define BCHP_REQB1_G2U_REG_START                           0x07e00a00
+#define BCHP_REQB1_G2U_REG_END                             0x07e00a8c
+#define BCHP_REPB1_G2U_REG_START                           0x07e00b00
+#define BCHP_REPB1_G2U_REG_END                             0x07e00b8c
+#define BCHP_REQC0_G2U_REG_START                           0x07e00c00
+#define BCHP_REQC0_G2U_REG_END                             0x07e00c8c
+#define BCHP_REPC0_G2U_REG_START                           0x07e00d00
+#define BCHP_REPC0_G2U_REG_END                             0x07e00d8c
+#define BCHP_REQC1_G2U_REG_START                           0x07e00e00
+#define BCHP_REQC1_G2U_REG_END                             0x07e00e8c
+#define BCHP_REPC1_G2U_REG_START                           0x07e00f00
+#define BCHP_REPC1_G2U_REG_END                             0x07e00f8c
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x20300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x2030fffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x20310000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x203103fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x20310400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x20310450
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x20310460
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x20310470
+#define BCHP_SCPU_INTR1_REG_START                          0x20310480
+#define BCHP_SCPU_INTR1_REG_END                            0x20310498
+#define BCHP_INTERNAL_INTR2_REG_START                      0x203104c0
+#define BCHP_INTERNAL_INTR2_REG_END                        0x203104ec
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x20310500
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x2031052c
+#define BCHP_SCPU_HW_INTR2_REG_START                       0x20310540
+#define BCHP_SCPU_HW_INTR2_REG_END                         0x2031056c
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x20311000
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x2031102c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x20311040
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x2031106c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x20312000
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x20312008
+#define BCHP_SCPU_HDMI_CTRL_REG_START                      0x20312080
+#define BCHP_SCPU_HDMI_CTRL_REG_END                        0x20312084
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x20312100
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x20312114
+#define BCHP_SAGE_UART_REG_START                           0x20312200
+#define BCHP_SAGE_UART_REG_END                             0x2031221c
+#define BCHP_SCPU_PM_REG_START                             0x20312980
+#define BCHP_SCPU_PM_REG_END                               0x20312988
+#define BCHP_SCPU_TIMER_REG_START                          0x20312e80
+#define BCHP_SCPU_TIMER_REG_END                            0x20312ebc
+#define BCHP_BSP_CMDBUF_REG_START                          0x2032c800
+#define BCHP_BSP_CMDBUF_REG_END                            0x2032cffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x2032d000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x2032d0b0
+#define BCHP_BSP_PKL_REG_START                             0x2032d300
+#define BCHP_BSP_PKL_REG_END                               0x2032d37c
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x2032d800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x2032d82c
+#define BCHP_BSP_VISTA_GENACC_REG_START                    0x2032d900
+#define BCHP_BSP_VISTA_GENACC_REG_END                      0x2032d9fc
+#define BCHP_BSP_OTP_SCRATCH_REG_START                     0x2032e000
+#define BCHP_BSP_OTP_SCRATCH_REG_END                       0x2032fffc
+#define BCHP_SUN_GISB_ARB_REG_START                        0x20400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x204007fc
+#define BCHP_SUN_GR_REG_START                              0x20401000
+#define BCHP_SUN_GR_REG_END                                0x2040100c
+#define BCHP_SSP_RG_REG_START                              0x20401200
+#define BCHP_SSP_RG_REG_END                                0x2040120c
+#define BCHP_SUN_RG_REG_START                              0x20401400
+#define BCHP_SUN_RG_REG_END                                0x2040140c
+#define BCHP_RF4CE_GR_REG_START                            0x20401600
+#define BCHP_RF4CE_GR_REG_END                              0x2040160c
+#define BCHP_TPCAP_REG_START                               0x20401800
+#define BCHP_TPCAP_REG_END                                 0x2040189c
+#define BCHP_SUN_L2_REG_START                              0x20403000
+#define BCHP_SUN_L2_REG_END                                0x20403044
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x20404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x2040452c
+#define BCHP_BBSI_RG_REG_START                             0x20405c00
+#define BCHP_BBSI_RG_REG_END                               0x20405c0c
+#define BCHP_PWM_REG_START                                 0x20408000
+#define BCHP_PWM_REG_END                                   0x20408024
+#define BCHP_PWMB_REG_START                                0x20409000
+#define BCHP_PWMB_REG_END                                  0x20409024
+#define BCHP_GIO_REG_START                                 0x2040a000
+#define BCHP_GIO_REG_END                                   0x2040a09c
+#define BCHP_TIMER_REG_START                               0x2040a100
+#define BCHP_TIMER_REG_END                                 0x2040a13c
+#define BCHP_WATCHDOG_REG_START                            0x2040a200
+#define BCHP_WATCHDOG_REG_END                              0x2040a210
+#define BCHP_BSCA_REG_START                                0x2040a300
+#define BCHP_BSCA_REG_END                                  0x2040a354
+#define BCHP_BSCD_REG_START                                0x2040a400
+#define BCHP_BSCD_REG_END                                  0x2040a454
+#define BCHP_BSCE_REG_START                                0x2040a500
+#define BCHP_BSCE_REG_END                                  0x2040a554
+#define BCHP_IRQ0_REG_START                                0x2040a600
+#define BCHP_IRQ0_REG_END                                  0x2040a604
+#define BCHP_IRQ1_REG_START                                0x2040a640
+#define BCHP_IRQ1_REG_END                                  0x2040a644
+#define BCHP_PM_REG_START                                  0x2040a680
+#define BCHP_PM_REG_END                                    0x2040a688
+#define BCHP_UARTA_REG_START                               0x2040a900
+#define BCHP_UARTA_REG_END                                 0x2040a91c
+#define BCHP_UARTB_REG_START                               0x2040a940
+#define BCHP_UARTB_REG_END                                 0x2040a95c
+#define BCHP_UARTC_REG_START                               0x2040a980
+#define BCHP_UARTC_REG_END                                 0x2040a99c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x2040b100
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x2040b12c
+#define BCHP_UPG_UART_DMA_REG_START                        0x2040b400
+#define BCHP_UPG_UART_DMA_REG_END                          0x2040b430
+#define BCHP_AON_CTRL_REG_START                            0x20410000
+#define BCHP_AON_CTRL_REG_END                              0x204105fc
+#define BCHP_AON_L2_REG_START                              0x20410600
+#define BCHP_AON_L2_REG_END                                0x2041062c
+#define BCHP_AON_PM_L2_REG_START                           0x20410640
+#define BCHP_AON_PM_L2_REG_END                             0x2041066c
+#define BCHP_AON_PM_BBM_L2_REG_START                       0x20410680
+#define BCHP_AON_PM_BBM_L2_REG_END                         0x204106ac
+#define BCHP_AON_PIN_CTRL_REG_START                        0x20410700
+#define BCHP_AON_PIN_CTRL_REG_END                          0x20410714
+#define BCHP_CNTControlBase_REG_START                      0x20412000
+#define BCHP_CNTControlBase_REG_END                        0x20412ffc
+#define BCHP_CNTReadBase_REG_START                         0x20414000
+#define BCHP_CNTReadBase_REG_END                           0x20414ffc
+#define BCHP_MSPI_REG_START                                0x20416000
+#define BCHP_MSPI_REG_END                                  0x2041617c
+#define BCHP_GIO_AON_REG_START                             0x20417000
+#define BCHP_GIO_AON_REG_END                               0x2041703c
+#define BCHP_LDK_REG_START                                 0x20417100
+#define BCHP_LDK_REG_END                                   0x20417144
+#define BCHP_BSCB_REG_START                                0x20417180
+#define BCHP_BSCB_REG_END                                  0x204171d4
+#define BCHP_IRQ0_AON_REG_START                            0x20417200
+#define BCHP_IRQ0_AON_REG_END                              0x20417204
+#define BCHP_IRQ1_AON_REG_START                            0x20417240
+#define BCHP_IRQ1_AON_REG_END                              0x20417244
+#define BCHP_PM_AON_REG_START                              0x20417280
+#define BCHP_PM_AON_REG_END                                0x20417288
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x20417400
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x2041742c
+#define BCHP_WKTMR_REG_START                               0x20417480
+#define BCHP_WKTMR_REG_END                                 0x20417490
+#define BCHP_AVS_CPU_PROG_MEM_REG_START                    0x20420000
+#define BCHP_AVS_CPU_PROG_MEM_REG_END                      0x20422ffc
+#define BCHP_AVS_CPU_DATA_MEM_REG_START                    0x20424000
+#define BCHP_AVS_CPU_DATA_MEM_REG_END                      0x20424bfc
+#define BCHP_AVS_CPU_CORE_REGS_REG_START                   0x20428000
+#define BCHP_AVS_CPU_CORE_REGS_REG_END                     0x204280fc
+#define BCHP_AVS_CPU_AUX_REGS_REG_START                    0x2042a000
+#define BCHP_AVS_CPU_AUX_REGS_REG_END                      0x2042b058
+#define BCHP_AVS_UART_REG_START                            0x20430000
+#define BCHP_AVS_UART_REG_END                              0x20430ffc
+#define BCHP_AVS_CPU_L2_REG_START                          0x20431100
+#define BCHP_AVS_CPU_L2_REG_END                            0x2043112c
+#define BCHP_AVS_HOST_L2_REG_START                         0x20431200
+#define BCHP_AVS_HOST_L2_REG_END                           0x20431244
+#define BCHP_AVS_CPU_CTRL_REG_START                        0x20431300
+#define BCHP_AVS_CPU_CTRL_REG_END                          0x2043135c
+#define BCHP_AVS_BSTI_REG_START                            0x20431400
+#define BCHP_AVS_BSTI_REG_END                              0x20431404
+#define BCHP_AVS_TMON_REG_START                            0x20431500
+#define BCHP_AVS_TMON_REG_END                              0x20431524
+#define BCHP_AVS_TOP_CTRL_REG_START                        0x20431800
+#define BCHP_AVS_TOP_CTRL_REG_END                          0x204318a8
+#define BCHP_AVS_HW_MNTR_1_REG_START                       0x20432000
+#define BCHP_AVS_HW_MNTR_1_REG_END                         0x204320c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_START               0x20432100
+#define BCHP_AVS_PVT_MNTR_CONFIG_1_REG_END                 0x20432124
+#define BCHP_AVS_RO_REGISTERS_0_1_REG_START                0x20432200
+#define BCHP_AVS_RO_REGISTERS_0_1_REG_END                  0x204322e0
+#define BCHP_AVS_RO_REGISTERS_1_1_REG_START                0x20432800
+#define BCHP_AVS_RO_REGISTERS_1_1_REG_END                  0x20432808
+#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_START              0x20432d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_1_REG_END                0x20432dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_START              0x20432e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_1_REG_END                0x20432efc
+#define BCHP_AVS_HW_MNTR_2_REG_START                       0x20434000
+#define BCHP_AVS_HW_MNTR_2_REG_END                         0x204340c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_START               0x20434100
+#define BCHP_AVS_PVT_MNTR_CONFIG_2_REG_END                 0x20434124
+#define BCHP_AVS_RO_REGISTERS_0_2_REG_START                0x20434200
+#define BCHP_AVS_RO_REGISTERS_0_2_REG_END                  0x204342e0
+#define BCHP_AVS_RO_REGISTERS_1_2_REG_START                0x20434800
+#define BCHP_AVS_RO_REGISTERS_1_2_REG_END                  0x20434808
+#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_START              0x20434d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_2_REG_END                0x20434dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_START              0x20434e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_2_REG_END                0x20434efc
+#define BCHP_AVS_WDOG_REG_START                            0x20436000
+#define BCHP_AVS_WDOG_REG_END                              0x20436ffc
+#define BCHP_AVS_PMB_S_000_REG_START                       0x20438000
+#define BCHP_AVS_PMB_S_000_REG_END                         0x20438024
+#define BCHP_AVS_PMB_S_001_REG_START                       0x20438040
+#define BCHP_AVS_PMB_S_001_REG_END                         0x20438064
+#define BCHP_AVS_PMB_S_002_REG_START                       0x20438080
+#define BCHP_AVS_PMB_S_002_REG_END                         0x204380a4
+#define BCHP_AVS_PMB_S_003_REG_START                       0x204380c0
+#define BCHP_AVS_PMB_S_003_REG_END                         0x204380e4
+#define BCHP_AVS_PMB_S_004_REG_START                       0x20438100
+#define BCHP_AVS_PMB_S_004_REG_END                         0x20438124
+#define BCHP_AVS_PMB_S_005_REG_START                       0x20438140
+#define BCHP_AVS_PMB_S_005_REG_END                         0x20438164
+#define BCHP_AVS_PMB_S_006_REG_START                       0x20438180
+#define BCHP_AVS_PMB_S_006_REG_END                         0x204381a4
+#define BCHP_AVS_PMB_S_007_REG_START                       0x204381c0
+#define BCHP_AVS_PMB_S_007_REG_END                         0x204381e4
+#define BCHP_AVS_PMB_S_008_REG_START                       0x20438200
+#define BCHP_AVS_PMB_S_008_REG_END                         0x20438224
+#define BCHP_AVS_PMB_S_009_REG_START                       0x20438240
+#define BCHP_AVS_PMB_S_009_REG_END                         0x20438264
+#define BCHP_AVS_PMB_S_010_REG_START                       0x20438280
+#define BCHP_AVS_PMB_S_010_REG_END                         0x204382a4
+#define BCHP_AVS_PMB_S_011_REG_START                       0x204382c0
+#define BCHP_AVS_PMB_S_011_REG_END                         0x204382e4
+#define BCHP_AVS_PMB_S_012_REG_START                       0x20438300
+#define BCHP_AVS_PMB_S_012_REG_END                         0x20438324
+#define BCHP_AVS_PMB_S_013_REG_START                       0x20438340
+#define BCHP_AVS_PMB_S_013_REG_END                         0x20438364
+#define BCHP_AVS_PMB_S_014_REG_START                       0x20438380
+#define BCHP_AVS_PMB_S_014_REG_END                         0x204383a4
+#define BCHP_AVS_PMB_S_015_REG_START                       0x204383c0
+#define BCHP_AVS_PMB_S_015_REG_END                         0x204383e4
+#define BCHP_AVS_PMB_S_016_REG_START                       0x20438400
+#define BCHP_AVS_PMB_S_016_REG_END                         0x20438424
+#define BCHP_AVS_PMB_S_017_REG_START                       0x20438440
+#define BCHP_AVS_PMB_S_017_REG_END                         0x20438464
+#define BCHP_AVS_PMB_S_018_REG_START                       0x20438480
+#define BCHP_AVS_PMB_S_018_REG_END                         0x204384a4
+#define BCHP_AVS_PMB_S_019_REG_START                       0x204384c0
+#define BCHP_AVS_PMB_S_019_REG_END                         0x204384e4
+#define BCHP_AVS_PMB_S_020_REG_START                       0x20438500
+#define BCHP_AVS_PMB_S_020_REG_END                         0x20438524
+#define BCHP_AVS_PMB_S_021_REG_START                       0x20438540
+#define BCHP_AVS_PMB_S_021_REG_END                         0x20438564
+#define BCHP_AVS_PMB_S_022_REG_START                       0x20438580
+#define BCHP_AVS_PMB_S_022_REG_END                         0x204385a4
+#define BCHP_AVS_PMB_S_023_REG_START                       0x204385c0
+#define BCHP_AVS_PMB_S_023_REG_END                         0x204385e4
+#define BCHP_AVS_PMB_S_024_REG_START                       0x20438600
+#define BCHP_AVS_PMB_S_024_REG_END                         0x20438624
+#define BCHP_AVS_PMB_S_025_REG_START                       0x20438640
+#define BCHP_AVS_PMB_S_025_REG_END                         0x20438664
+#define BCHP_AVS_PMB_S_026_REG_START                       0x20438680
+#define BCHP_AVS_PMB_S_026_REG_END                         0x204386a4
+#define BCHP_AVS_PMB_S_027_REG_START                       0x204386c0
+#define BCHP_AVS_PMB_S_027_REG_END                         0x204386e4
+#define BCHP_AVS_PMB_S_028_REG_START                       0x20438700
+#define BCHP_AVS_PMB_S_028_REG_END                         0x20438724
+#define BCHP_AVS_PMB_S_029_REG_START                       0x20438740
+#define BCHP_AVS_PMB_S_029_REG_END                         0x20438764
+#define BCHP_AVS_PMB_S_030_REG_START                       0x20438780
+#define BCHP_AVS_PMB_S_030_REG_END                         0x204387a4
+#define BCHP_AVS_PMB_S_031_REG_START                       0x204387c0
+#define BCHP_AVS_PMB_S_031_REG_END                         0x204387e4
+#define BCHP_AVS_PMB_S_032_REG_START                       0x20438800
+#define BCHP_AVS_PMB_S_032_REG_END                         0x20438824
+#define BCHP_AVS_PMB_S_033_REG_START                       0x20438840
+#define BCHP_AVS_PMB_S_033_REG_END                         0x20438864
+#define BCHP_AVS_PMB_S_034_REG_START                       0x20438880
+#define BCHP_AVS_PMB_S_034_REG_END                         0x204388a4
+#define BCHP_AVS_PMB_REGISTERS_REG_START                   0x2043a000
+#define BCHP_AVS_PMB_REGISTERS_REG_END                     0x2043a008
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x20440000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x204407fc
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x20440800
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x20440804
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x20440900
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x2044097c
+#define BCHP_AVS_RANGE_BLOCKER_REG_START                   0x20440a00
+#define BCHP_AVS_RANGE_BLOCKER_REG_END                     0x20440a58
+#define BCHP_HIF_CONTINUATION_REG_START                    0x20450000
+#define BCHP_HIF_CONTINUATION_REG_END                      0x204500fc
+#define BCHP_WEBHIF_CONTINUATION_REG_START                 0x20450800
+#define BCHP_WEBHIF_CONTINUATION_REG_END                   0x20450814
+#define BCHP_CLKGEN_REG_START                              0x20480000
+#define BCHP_CLKGEN_REG_END                                0x204804b8
+#define BCHP_CLKGEN_GR_REG_START                           0x20483000
+#define BCHP_CLKGEN_GR_REG_END                             0x2048300c
+#define BCHP_SDIO_0_HOST_REG_START                         0x204a0000
+#define BCHP_SDIO_0_HOST_REG_END                           0x204a00fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x204a0100
+#define BCHP_SDIO_0_CFG_REG_END                            0x204a01fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x204a0200
+#define BCHP_SDIO_1_HOST_REG_END                           0x204a02fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x204a0300
+#define BCHP_SDIO_1_CFG_REG_END                            0x204a03fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x204a0400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x204a043c
+#define BCHP_EBI_REG_START                                 0x204a0800
+#define BCHP_EBI_REG_END                                   0x204a0bfc
+#define BCHP_HIF_INTR2_REG_START                           0x204a1000
+#define BCHP_HIF_INTR2_REG_END                             0x204a102c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x204a1500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x204a154c
+#define BCHP_HIF_RGR2_REG_START                            0x204a1700
+#define BCHP_HIF_RGR2_REG_END                              0x204a1710
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x204a1a00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x204a1a2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x204a2000
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x204a203c
+#define BCHP_WEBHIF_L1_MASK_REG_START                      0x204a2100
+#define BCHP_WEBHIF_L1_MASK_REG_END                        0x204a2110
+#define BCHP_HIF_CPUBIUARCH_REG_START                      0x204a2200
+#define BCHP_HIF_CPUBIUARCH_REG_END                        0x204a23fc
+#define BCHP_HIF_CPUBIUCTRL_REG_START                      0x204a2400
+#define BCHP_HIF_CPUBIUCTRL_REG_END                        0x204a27fc
+#define BCHP_NAND_REG_START                                0x204a2800
+#define BCHP_NAND_REG_END                                  0x204a2dfc
+#define BCHP_FLASH_DMA_REG_START                           0x204a3000
+#define BCHP_FLASH_DMA_REG_END                             0x204a3028
+#define BCHP_BSPI_REG_START                                0x204a3200
+#define BCHP_BSPI_REG_END                                  0x204a324c
+#define BCHP_BSPI_RAF_REG_START                            0x204a3300
+#define BCHP_BSPI_RAF_REG_END                              0x204a3320
+#define BCHP_HIF_MSPI_REG_START                            0x204a3400
+#define BCHP_HIF_MSPI_REG_END                              0x204a3584
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START          0x204a3600
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END            0x204a3604
+#define BCHP_IPI0_INTR2_REG_START                          0x204a4000
+#define BCHP_IPI0_INTR2_REG_END                            0x204a402c
+#define BCHP_IPI1_INTR2_REG_START                          0x204a4100
+#define BCHP_IPI1_INTR2_REG_END                            0x204a412c
+#define BCHP_BOOTSRAM_TM_REG_START                         0x204b0000
+#define BCHP_BOOTSRAM_TM_REG_END                           0x204bfffc
+#define BCHP_BOOTSRAM_SECURE_REG_START                     0x204c0000
+#define BCHP_BOOTSRAM_SECURE_REG_END                       0x204cfffc
+#define BCHP_ITCH0_REG_START                               0x204d0000
+#define BCHP_ITCH0_REG_END                                 0x204d0000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x204d0400
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x204d0400
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x204d0500
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x204d0500
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x204d0600
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x204d0600
+#define BCHP_NAND_SECURE_REG_START                         0x204d0800
+#define BCHP_NAND_SECURE_REG_END                           0x204d0800
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START       0x204d0c00
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END         0x204d0c00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START               0x204d0e00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END                 0x204d0ffc
+#define BCHP_HIF_CONTINUATION_SECURE_REG_START             0x204d1000
+#define BCHP_HIF_CONTINUATION_SECURE_REG_END               0x204d1004
+#define BCHP_ITCH1_REG_START                               0x204d1200
+#define BCHP_ITCH1_REG_END                                 0x204d1200
+#define BCHP_PROD_OTP_GRB_REG_START                        0x204e6000
+#define BCHP_PROD_OTP_GRB_REG_END                          0x204e600c
+#define BCHP_JTAG_OTP_REG_START                            0x204e6100
+#define BCHP_JTAG_OTP_REG_END                              0x204e615c
+#define BCHP_BOOTROM_REG_START                             0x20500000
+#define BCHP_BOOTROM_REG_END                               0x20503ffc
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_START              0x20a80200
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_END                0x20a80204
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_START              0x20a80300
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_END                0x20a80304
+#define BCHP_DEMOD_XPT_WAKEUP_REG_START                    0x20a81000
+#define BCHP_DEMOD_XPT_WAKEUP_REG_END                      0x20a81fbc
+#define BCHP_DEMOD_XPT_FE_REG_START                        0x20a82000
+#define BCHP_DEMOD_XPT_FE_REG_END                          0x20a837fc
+#define BCHP_SID_REG_START                                 0x20bc0100
+#define BCHP_SID_REG_END                                   0x20bc019c
+#define BCHP_SID_RLE_REG_START                             0x20bc0300
+#define BCHP_SID_RLE_REG_END                               0x20bc039c
+#define BCHP_SID_DQ_REG_START                              0x20bc0400
+#define BCHP_SID_DQ_REG_END                                0x20bc04bc
+#define BCHP_SID_STRM_REG_START                            0x20bc0800
+#define BCHP_SID_STRM_REG_END                              0x20bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x20bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x20bc0c40
+#define BCHP_SID_ARC_REG_START                             0x20bc0f00
+#define BCHP_SID_ARC_REG_END                               0x20bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x20bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x20bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x20bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x20bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x20bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x20bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x20bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x20bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x20bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x20bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x20bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x20bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x20bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x20bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x20bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x20bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x20bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x20bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x20bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x20bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x20bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x20bd5014
+#define BCHP_SID_GR_REG_START                              0x20be0000
+#define BCHP_SID_GR_REG_END                                0x20be000c
+#define BCHP_SID_L2_REG_START                              0x20be0100
+#define BCHP_SID_L2_REG_END                                0x20be012c
+#define BCHP_SICH_REG_START                                0x20be2000
+#define BCHP_SICH_REG_END                                  0x20be203c
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_START                 0x20e00000
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_END                   0x20e1fffc
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_START                 0x20e20000
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_END                   0x20e3fffc
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_START                  0x20e40000
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_END                    0x20e47ffc
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_START                 0x20e50000
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_END                   0x20e500fc
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_START                  0x20e51000
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_END                    0x20e51a08
+#define BCHP_RF4CE_CPU_UART_REG_START                      0x20e52000
+#define BCHP_RF4CE_CPU_UART_REG_END                        0x20e52ffc
+#define BCHP_RF4CE_CPU_WDG_REG_START                       0x20e53000
+#define BCHP_RF4CE_CPU_WDG_REG_END                         0x20e53ffc
+#define BCHP_RF4CE_CPU_CTRL_REG_START                      0x20e80000
+#define BCHP_RF4CE_CPU_CTRL_REG_END                        0x20e8008c
+#define BCHP_RF4CE_CPU_L2_REG_START                        0x20e80300
+#define BCHP_RF4CE_CPU_L2_REG_END                          0x20e80314
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_START               0x20e80500
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_END                 0x20e8052c
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_START                0x20e80800
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_END                  0x20e8082c
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_START                0x20e80a00
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_END                  0x20e80a2c
+#define BCHP_TX_REG_START                                  0x20ec0000
+#define BCHP_TX_REG_END                                    0x20ec0020
+#define BCHP_RX_REG_START                                  0x20ed0000
+#define BCHP_RX_REG_END                                    0x20ed0254
+#define BCHP_RF_REG_START                                  0x20ee0000
+#define BCHP_RF_REG_END                                    0x20ee00a4
+#define BCHP_VCOCAL_REG_START                              0x20ee0100
+#define BCHP_VCOCAL_REG_END                                0x20ee0174
+#define BCHP_KVCO_REG_START                                0x20ee0200
+#define BCHP_KVCO_REG_END                                  0x20ee0224
+#define BCHP_PA_REG_START                                  0x20ee0300
+#define BCHP_PA_REG_END                                    0x20ee0314
+#define BCHP_MAC_REG_START                                 0x20ee0400
+#define BCHP_MAC_REG_END                                   0x20ee0564
+#define BCHP_PWR_MGT_L2_REG_START                          0x20ee0600
+#define BCHP_PWR_MGT_L2_REG_END                            0x20ee0614
+#define BCHP_MISC_L2_REG_START                             0x20ee0700
+#define BCHP_MISC_L2_REG_END                               0x20ee0714
+#define BCHP_IQCAL_CCA_CCM_L2_REG_START                    0x20ee0800
+#define BCHP_IQCAL_CCA_CCM_L2_REG_END                      0x20ee0814
+#define BCHP_SYMCNT6_L2_REG_START                          0x20ee0900
+#define BCHP_SYMCNT6_L2_REG_END                            0x20ee0914
+#define BCHP_TX_DONE_L2_REG_START                          0x20ee0a00
+#define BCHP_TX_DONE_L2_REG_END                            0x20ee0a14
+#define BCHP_RX_DONE_L2_REG_START                          0x20ee0b00
+#define BCHP_RX_DONE_L2_REG_END                            0x20ee0b14
+#define BCHP_RX_START_L2_REG_START                         0x20ee0c00
+#define BCHP_RX_START_L2_REG_END                           0x20ee0c14
+#define BCHP_SYMCNT7_L2_REG_START                          0x20ee0d00
+#define BCHP_SYMCNT7_L2_REG_END                            0x20ee0d14
+#define BCHP_GCI_0_REG_START                               0x20ee1000
+#define BCHP_GCI_0_REG_END                                 0x20ee120c
+#define BCHP_GCI_1_REG_START                               0x20ee1400
+#define BCHP_GCI_1_REG_END                                 0x20ee1604
+#define BCHP_GCI_2_REG_START                               0x20ee1800
+#define BCHP_GCI_2_REG_END                                 0x20ee1a04
+#define BCHP_USB_CAPS_REG_START                            0x21000000
+#define BCHP_USB_CAPS_REG_END                              0x2100002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x21000100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x2100010c
+#define BCHP_USB_INTR2_REG_START                           0x21000180
+#define BCHP_USB_INTR2_REG_END                             0x210001ac
+#define BCHP_USB_CTRL_REG_START                            0x21000200
+#define BCHP_USB_CTRL_REG_END                              0x210002fc
+#define BCHP_USB_EHCI_REG_START                            0x21000300
+#define BCHP_USB_EHCI_REG_END                              0x210003a4
+#define BCHP_USB_OHCI_REG_START                            0x21000400
+#define BCHP_USB_OHCI_REG_END                              0x21000454
+#define BCHP_USB_AXI_MON_REG_START                         0x21000500
+#define BCHP_USB_AXI_MON_REG_END                           0x21000534
+#define BCHP_USB_XHCI_REG_START                            0x21001000
+#define BCHP_USB_XHCI_REG_END                              0x21001ffc
+#define BCHP_USB1_CAPS_REG_START                           0x21010000
+#define BCHP_USB1_CAPS_REG_END                             0x2101002c
+#define BCHP_USB1_INTR2_REG_START                          0x21010180
+#define BCHP_USB1_INTR2_REG_END                            0x210101ac
+#define BCHP_USB1_CTRL_REG_START                           0x21010200
+#define BCHP_USB1_CTRL_REG_END                             0x210102fc
+#define BCHP_USB1_EHCI_REG_START                           0x21010300
+#define BCHP_USB1_EHCI_REG_END                             0x210103a4
+#define BCHP_USB1_OHCI_REG_START                           0x21010400
+#define BCHP_USB1_OHCI_REG_END                             0x21010454
+#define BCHP_USB1_AXI_MON_REG_START                        0x21010500
+#define BCHP_USB1_AXI_MON_REG_END                          0x21010534
+#define BCHP_USB1_XHCI_REG_START                           0x21011000
+#define BCHP_USB1_XHCI_REG_END                             0x21011ffc
+#define BCHP_USB1_BDC_REG_START                            0x21012000
+#define BCHP_USB1_BDC_REG_END                              0x21012fc0
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START                 0x21080000
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END                   0x2108003c
+#define BCHP_PCIE_0_RC_CFG_PM_REG_START                    0x21080048
+#define BCHP_PCIE_0_RC_CFG_PM_REG_END                      0x2108004c
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START                  0x210800ac
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END                    0x210800e4
+#define BCHP_PCIE_0_RC_CFG_AER_REG_START                   0x21080100
+#define BCHP_PCIE_0_RC_CFG_AER_REG_END                     0x21080134
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START                0x21080180
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END                  0x210801a4
+#define BCHP_PCIE_0_RC_CFG_L1SUB_REG_START                 0x21080240
+#define BCHP_PCIE_0_RC_CFG_L1SUB_REG_END                   0x2108024c
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START                 0x21080404
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END                   0x21080418
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START                 0x21080428
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END                   0x21080630
+#define BCHP_PCIE_0_RC_TL_REG_START                        0x21080800
+#define BCHP_PCIE_0_RC_TL_REG_END                          0x21080a74
+#define BCHP_PCIE_0_RC_DL_REG_START                        0x21081000
+#define BCHP_PCIE_0_RC_DL_REG_END                          0x21081424
+#define BCHP_PCIE_0_RC_PL_REG_START                        0x21081800
+#define BCHP_PCIE_0_RC_PL_REG_END                          0x21081ffc
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START                 0x21082000
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END                   0x2108203c
+#define BCHP_PCIE_0_EP_CFG_PM_REG_START                    0x21082048
+#define BCHP_PCIE_0_EP_CFG_PM_REG_END                      0x2108204c
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_START                   0x21082050
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_END                     0x21082054
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_START                   0x21082058
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_END                     0x21082064
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START                  0x210820a0
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END                    0x210820a8
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START                  0x210820ac
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END                    0x210820e4
+#define BCHP_PCIE_0_EP_CFG_AER_REG_START                   0x21082100
+#define BCHP_PCIE_0_EP_CFG_AER_REG_END                     0x21082134
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_START                   0x2108213c
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_END                     0x21082144
+#define BCHP_PCIE_0_EP_CFG_PB_REG_START                    0x21082150
+#define BCHP_PCIE_0_EP_CFG_PB_REG_END                      0x2108215c
+#define BCHP_PCIE_0_EP_CFG_VC_REG_START                    0x21082160
+#define BCHP_PCIE_0_EP_CFG_VC_REG_END                      0x21082178
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START                0x21082180
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END                  0x210821a4
+#define BCHP_PCIE_0_EP_CFG_LTR_REG_START                   0x210821b0
+#define BCHP_PCIE_0_EP_CFG_LTR_REG_END                     0x210821b4
+#define BCHP_PCIE_0_EP_CFG_L1SUB_REG_START                 0x21082240
+#define BCHP_PCIE_0_EP_CFG_L1SUB_REG_END                   0x2108224c
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START                 0x21082404
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END                   0x21082418
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START                 0x21082428
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END                   0x21082630
+#define BCHP_PCIE_0_EP_TL_REG_START                        0x21082800
+#define BCHP_PCIE_0_EP_TL_REG_END                          0x21082a74
+#define BCHP_PCIE_0_EP_DL_REG_START                        0x21083000
+#define BCHP_PCIE_0_EP_DL_REG_END                          0x21083424
+#define BCHP_PCIE_0_EP_PL_REG_START                        0x21083800
+#define BCHP_PCIE_0_EP_PL_REG_END                          0x21083ffc
+#define BCHP_PCIE_0_MISC_REG_START                         0x21084000
+#define BCHP_PCIE_0_MISC_REG_END                           0x210840d0
+#define BCHP_PCIE_0_MISC_PERST_REG_START                   0x21084100
+#define BCHP_PCIE_0_MISC_PERST_REG_END                     0x21084104
+#define BCHP_PCIE_0_MISC_HARD_REG_START                    0x21084200
+#define BCHP_PCIE_0_MISC_HARD_REG_END                      0x21084204
+#define BCHP_PCIE_0_INTR2_REG_START                        0x21084300
+#define BCHP_PCIE_0_INTR2_REG_END                          0x2108432c
+#define BCHP_PCIE_0_DMA_REG_START                          0x21084400
+#define BCHP_PCIE_0_DMA_REG_END                            0x2108446c
+#define BCHP_PCIE_0_MSI_INTR2_REG_START                    0x21084500
+#define BCHP_PCIE_0_MSI_INTR2_REG_END                      0x2108452c
+#define BCHP_PCIE_0_EXT_CFG_REG_START                      0x21088000
+#define BCHP_PCIE_0_EXT_CFG_REG_END                        0x21089008
+#define BCHP_PCIE_0_RGR1_REG_START                         0x21089200
+#define BCHP_PCIE_0_RGR1_REG_END                           0x21089210
+#define BCHP_PCIE_0_RG_REG_START                           0x21089300
+#define BCHP_PCIE_0_RG_REG_END                             0x2108930c
+#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_START                 0x21090000
+#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_END                   0x2109003c
+#define BCHP_PCIE_1_RC_CFG_PM_REG_START                    0x21090048
+#define BCHP_PCIE_1_RC_CFG_PM_REG_END                      0x2109004c
+#define BCHP_PCIE_1_RC_CFG_PCIE_REG_START                  0x210900ac
+#define BCHP_PCIE_1_RC_CFG_PCIE_REG_END                    0x210900e4
+#define BCHP_PCIE_1_RC_CFG_AER_REG_START                   0x21090100
+#define BCHP_PCIE_1_RC_CFG_AER_REG_END                     0x21090134
+#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_START                0x21090180
+#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_END                  0x210901a4
+#define BCHP_PCIE_1_RC_CFG_L1SUB_REG_START                 0x21090240
+#define BCHP_PCIE_1_RC_CFG_L1SUB_REG_END                   0x2109024c
+#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_START                 0x21090404
+#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_END                   0x21090418
+#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_START                 0x21090428
+#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_END                   0x21090630
+#define BCHP_PCIE_1_RC_TL_REG_START                        0x21090800
+#define BCHP_PCIE_1_RC_TL_REG_END                          0x21090a74
+#define BCHP_PCIE_1_RC_DL_REG_START                        0x21091000
+#define BCHP_PCIE_1_RC_DL_REG_END                          0x21091424
+#define BCHP_PCIE_1_RC_PL_REG_START                        0x21091800
+#define BCHP_PCIE_1_RC_PL_REG_END                          0x21091ffc
+#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_START                 0x21092000
+#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_END                   0x2109203c
+#define BCHP_PCIE_1_EP_CFG_PM_REG_START                    0x21092048
+#define BCHP_PCIE_1_EP_CFG_PM_REG_END                      0x2109204c
+#define BCHP_PCIE_1_EP_CFG_VPD_REG_START                   0x21092050
+#define BCHP_PCIE_1_EP_CFG_VPD_REG_END                     0x21092054
+#define BCHP_PCIE_1_EP_CFG_MSI_REG_START                   0x21092058
+#define BCHP_PCIE_1_EP_CFG_MSI_REG_END                     0x21092064
+#define BCHP_PCIE_1_EP_CFG_MSIX_REG_START                  0x210920a0
+#define BCHP_PCIE_1_EP_CFG_MSIX_REG_END                    0x210920a8
+#define BCHP_PCIE_1_EP_CFG_PCIE_REG_START                  0x210920ac
+#define BCHP_PCIE_1_EP_CFG_PCIE_REG_END                    0x210920e4
+#define BCHP_PCIE_1_EP_CFG_AER_REG_START                   0x21092100
+#define BCHP_PCIE_1_EP_CFG_AER_REG_END                     0x21092134
+#define BCHP_PCIE_1_EP_CFG_DEV_REG_START                   0x2109213c
+#define BCHP_PCIE_1_EP_CFG_DEV_REG_END                     0x21092144
+#define BCHP_PCIE_1_EP_CFG_PB_REG_START                    0x21092150
+#define BCHP_PCIE_1_EP_CFG_PB_REG_END                      0x2109215c
+#define BCHP_PCIE_1_EP_CFG_VC_REG_START                    0x21092160
+#define BCHP_PCIE_1_EP_CFG_VC_REG_END                      0x21092178
+#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_START                0x21092180
+#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_END                  0x210921a4
+#define BCHP_PCIE_1_EP_CFG_LTR_REG_START                   0x210921b0
+#define BCHP_PCIE_1_EP_CFG_LTR_REG_END                     0x210921b4
+#define BCHP_PCIE_1_EP_CFG_L1SUB_REG_START                 0x21092240
+#define BCHP_PCIE_1_EP_CFG_L1SUB_REG_END                   0x2109224c
+#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_START                 0x21092404
+#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_END                   0x21092418
+#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_START                 0x21092428
+#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_END                   0x21092630
+#define BCHP_PCIE_1_EP_TL_REG_START                        0x21092800
+#define BCHP_PCIE_1_EP_TL_REG_END                          0x21092a74
+#define BCHP_PCIE_1_EP_DL_REG_START                        0x21093000
+#define BCHP_PCIE_1_EP_DL_REG_END                          0x21093424
+#define BCHP_PCIE_1_EP_PL_REG_START                        0x21093800
+#define BCHP_PCIE_1_EP_PL_REG_END                          0x21093ffc
+#define BCHP_PCIE_1_MISC_REG_START                         0x21094000
+#define BCHP_PCIE_1_MISC_REG_END                           0x210940d0
+#define BCHP_PCIE_1_MISC_PERST_REG_START                   0x21094100
+#define BCHP_PCIE_1_MISC_PERST_REG_END                     0x21094104
+#define BCHP_PCIE_1_MISC_HARD_REG_START                    0x21094200
+#define BCHP_PCIE_1_MISC_HARD_REG_END                      0x21094204
+#define BCHP_PCIE_1_INTR2_REG_START                        0x21094300
+#define BCHP_PCIE_1_INTR2_REG_END                          0x2109432c
+#define BCHP_PCIE_1_DMA_REG_START                          0x21094400
+#define BCHP_PCIE_1_DMA_REG_END                            0x2109446c
+#define BCHP_PCIE_1_MSI_INTR2_REG_START                    0x21094500
+#define BCHP_PCIE_1_MSI_INTR2_REG_END                      0x2109452c
+#define BCHP_PCIE_1_EXT_CFG_REG_START                      0x21098000
+#define BCHP_PCIE_1_EXT_CFG_REG_END                        0x21099008
+#define BCHP_PCIE_1_RGR1_REG_START                         0x21099200
+#define BCHP_PCIE_1_RGR1_REG_END                           0x21099210
+#define BCHP_PCIE_1_RG_REG_START                           0x21099300
+#define BCHP_PCIE_1_RG_REG_END                             0x2109930c
+#define BCHP_G2U_REGS_REG_START                            0x210a0000
+#define BCHP_G2U_REGS_REG_END                              0x210a0030
+#define BCHP_WEBHIF_RGR_REG_START                          0x210b0000
+#define BCHP_WEBHIF_RGR_REG_END                            0x210b0010
+#define BCHP_WEBHIF_INTR2_REG_START                        0x210b0100
+#define BCHP_WEBHIF_INTR2_REG_END                          0x210b012c
+#define BCHP_WEBHIF_CPU_INTR1_REG_START                    0x210b0600
+#define BCHP_WEBHIF_CPU_INTR1_REG_END                      0x210b064c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x210b0700
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x210b074c
+#define BCHP_WEBHIF_SCRATCH_REG_START                      0x210b0800
+#define BCHP_WEBHIF_SCRATCH_REG_END                        0x210b081c
+#define BCHP_WEBHIF_TIMER_REG_START                        0x210b0900
+#define BCHP_WEBHIF_TIMER_REG_END                          0x210b093c
+#define BCHP_WEBHIF_TOP_CTRL_REG_START                     0x210b0a00
+#define BCHP_WEBHIF_TOP_CTRL_REG_END                       0x210b0a00
+#define BCHP_RG_PM_REG_START                               0x210b0e00
+#define BCHP_RG_PM_REG_END                                 0x210b0e1c
+#define BCHP_PMBM_REG_START                                0x210b0f00
+#define BCHP_PMBM_REG_END                                  0x210b0f0c
+#define BCHP_WEBHIF_IPI0_INTR2_REG_START                   0x210b1000
+#define BCHP_WEBHIF_IPI0_INTR2_REG_END                     0x210b102c
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START               0x210b2000
+#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END                 0x210b202c
+#define BCHP_PCIE_2_RC_CFG_TYPE1_REG_START                 0x210c0000
+#define BCHP_PCIE_2_RC_CFG_TYPE1_REG_END                   0x210c003c
+#define BCHP_PCIE_2_RC_CFG_PM_REG_START                    0x210c0048
+#define BCHP_PCIE_2_RC_CFG_PM_REG_END                      0x210c004c
+#define BCHP_PCIE_2_RC_CFG_PCIE_REG_START                  0x210c00ac
+#define BCHP_PCIE_2_RC_CFG_PCIE_REG_END                    0x210c00e4
+#define BCHP_PCIE_2_RC_CFG_AER_REG_START                   0x210c0100
+#define BCHP_PCIE_2_RC_CFG_AER_REG_END                     0x210c0134
+#define BCHP_PCIE_2_RC_CFG_VENDOR_REG_START                0x210c0180
+#define BCHP_PCIE_2_RC_CFG_VENDOR_REG_END                  0x210c01a4
+#define BCHP_PCIE_2_RC_CFG_L1SUB_REG_START                 0x210c0240
+#define BCHP_PCIE_2_RC_CFG_L1SUB_REG_END                   0x210c024c
+#define BCHP_PCIE_2_RC_CFG_PRIV0_REG_START                 0x210c0404
+#define BCHP_PCIE_2_RC_CFG_PRIV0_REG_END                   0x210c0418
+#define BCHP_PCIE_2_RC_CFG_PRIV1_REG_START                 0x210c0428
+#define BCHP_PCIE_2_RC_CFG_PRIV1_REG_END                   0x210c0630
+#define BCHP_PCIE_2_RC_TL_REG_START                        0x210c0800
+#define BCHP_PCIE_2_RC_TL_REG_END                          0x210c0a74
+#define BCHP_PCIE_2_RC_DL_REG_START                        0x210c1000
+#define BCHP_PCIE_2_RC_DL_REG_END                          0x210c1424
+#define BCHP_PCIE_2_RC_PL_REG_START                        0x210c1800
+#define BCHP_PCIE_2_RC_PL_REG_END                          0x210c1ffc
+#define BCHP_PCIE_2_EP_CFG_TYPE0_REG_START                 0x210c2000
+#define BCHP_PCIE_2_EP_CFG_TYPE0_REG_END                   0x210c203c
+#define BCHP_PCIE_2_EP_CFG_PM_REG_START                    0x210c2048
+#define BCHP_PCIE_2_EP_CFG_PM_REG_END                      0x210c204c
+#define BCHP_PCIE_2_EP_CFG_VPD_REG_START                   0x210c2050
+#define BCHP_PCIE_2_EP_CFG_VPD_REG_END                     0x210c2054
+#define BCHP_PCIE_2_EP_CFG_MSI_REG_START                   0x210c2058
+#define BCHP_PCIE_2_EP_CFG_MSI_REG_END                     0x210c2064
+#define BCHP_PCIE_2_EP_CFG_MSIX_REG_START                  0x210c20a0
+#define BCHP_PCIE_2_EP_CFG_MSIX_REG_END                    0x210c20a8
+#define BCHP_PCIE_2_EP_CFG_PCIE_REG_START                  0x210c20ac
+#define BCHP_PCIE_2_EP_CFG_PCIE_REG_END                    0x210c20e4
+#define BCHP_PCIE_2_EP_CFG_AER_REG_START                   0x210c2100
+#define BCHP_PCIE_2_EP_CFG_AER_REG_END                     0x210c2134
+#define BCHP_PCIE_2_EP_CFG_DEV_REG_START                   0x210c213c
+#define BCHP_PCIE_2_EP_CFG_DEV_REG_END                     0x210c2144
+#define BCHP_PCIE_2_EP_CFG_PB_REG_START                    0x210c2150
+#define BCHP_PCIE_2_EP_CFG_PB_REG_END                      0x210c215c
+#define BCHP_PCIE_2_EP_CFG_VC_REG_START                    0x210c2160
+#define BCHP_PCIE_2_EP_CFG_VC_REG_END                      0x210c2178
+#define BCHP_PCIE_2_EP_CFG_VENDOR_REG_START                0x210c2180
+#define BCHP_PCIE_2_EP_CFG_VENDOR_REG_END                  0x210c21a4
+#define BCHP_PCIE_2_EP_CFG_LTR_REG_START                   0x210c21b0
+#define BCHP_PCIE_2_EP_CFG_LTR_REG_END                     0x210c21b4
+#define BCHP_PCIE_2_EP_CFG_L1SUB_REG_START                 0x210c2240
+#define BCHP_PCIE_2_EP_CFG_L1SUB_REG_END                   0x210c224c
+#define BCHP_PCIE_2_EP_CFG_PRIV0_REG_START                 0x210c2404
+#define BCHP_PCIE_2_EP_CFG_PRIV0_REG_END                   0x210c2418
+#define BCHP_PCIE_2_EP_CFG_PRIV1_REG_START                 0x210c2428
+#define BCHP_PCIE_2_EP_CFG_PRIV1_REG_END                   0x210c2630
+#define BCHP_PCIE_2_EP_TL_REG_START                        0x210c2800
+#define BCHP_PCIE_2_EP_TL_REG_END                          0x210c2a74
+#define BCHP_PCIE_2_EP_DL_REG_START                        0x210c3000
+#define BCHP_PCIE_2_EP_DL_REG_END                          0x210c3424
+#define BCHP_PCIE_2_EP_PL_REG_START                        0x210c3800
+#define BCHP_PCIE_2_EP_PL_REG_END                          0x210c3ffc
+#define BCHP_PCIE_2_MISC_REG_START                         0x210c4000
+#define BCHP_PCIE_2_MISC_REG_END                           0x210c40d0
+#define BCHP_PCIE_2_MISC_PERST_REG_START                   0x210c4100
+#define BCHP_PCIE_2_MISC_PERST_REG_END                     0x210c4104
+#define BCHP_PCIE_2_MISC_HARD_REG_START                    0x210c4200
+#define BCHP_PCIE_2_MISC_HARD_REG_END                      0x210c4204
+#define BCHP_PCIE_2_INTR2_REG_START                        0x210c4300
+#define BCHP_PCIE_2_INTR2_REG_END                          0x210c432c
+#define BCHP_PCIE_2_DMA_REG_START                          0x210c4400
+#define BCHP_PCIE_2_DMA_REG_END                            0x210c446c
+#define BCHP_PCIE_2_MSI_INTR2_REG_START                    0x210c4500
+#define BCHP_PCIE_2_MSI_INTR2_REG_END                      0x210c452c
+#define BCHP_PCIE_2_EXT_CFG_REG_START                      0x210c8000
+#define BCHP_PCIE_2_EXT_CFG_REG_END                        0x210c9008
+#define BCHP_PCIE_2_RGR1_REG_START                         0x210c9200
+#define BCHP_PCIE_2_RGR1_REG_END                           0x210c9210
+#define BCHP_PCIE_2_RG_REG_START                           0x210c9300
+#define BCHP_PCIE_2_RG_REG_END                             0x210c930c
+#define BCHP_DATA_MEM_REG_START                            0x21200000
+#define BCHP_DATA_MEM_REG_END                              0x212bfffc
+#define BCHP_CNTL_MEM_REG_START                            0x21300000
+#define BCHP_CNTL_MEM_REG_END                              0x21367ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x213c0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x213c0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x213c0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x213c0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x213c0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x213c0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x213c0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x213c0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x213c0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x213c0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x213c0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x213c0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x213c0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x213c0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x213c0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x213c0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x213c0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x213c0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x213c0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x213c0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x213c00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x213c00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x213c00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x213c00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x213c00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x213c00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x213c00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x213c00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x213c00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x213c00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x213c00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x213c00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x213c0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x213c0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x213c0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x213c0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x213c0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x213c0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x213c0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x213c0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x213c0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x213c0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x213c4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x213c4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x213c4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x213c4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x213c4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x213c4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x213c4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x213c4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x213c4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x213c4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x213c4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x213c4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x213c4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x213c4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x213c4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x213c4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x213c4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x213c4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x213c4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x213c4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x213c40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x213c40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x213c40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x213c40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x213c40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x213c40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x213c40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x213c40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x213c40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x213c40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x213c40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x213c40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x213c4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x213c4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x213c4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x213c4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x213c4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x213c4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x213c4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x213c4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x213c4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x213c4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x213c4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x213c4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x213c4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x213c4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x213c4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x213c4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x213c4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x213c4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x213c4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x213c4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x213c4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x213c4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x213c4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x213c4270
+#define BCHP_DMA_AHB_CMD_RES1_SCH0_REG_START               0x213c4400
+#define BCHP_DMA_AHB_CMD_RES1_SCH0_REG_END                 0x213c4400
+#define BCHP_DMA_AHB_CMD_RES1_SCH1_REG_START               0x213c4410
+#define BCHP_DMA_AHB_CMD_RES1_SCH1_REG_END                 0x213c4410
+#define BCHP_DMA_AHB_CMD_RES1_SCH2_REG_START               0x213c4420
+#define BCHP_DMA_AHB_CMD_RES1_SCH2_REG_END                 0x213c4420
+#define BCHP_DMA_AHB_CMD_RES1_SCH3_REG_START               0x213c4430
+#define BCHP_DMA_AHB_CMD_RES1_SCH3_REG_END                 0x213c4430
+#define BCHP_DMA_AHB_CMD_RES1_SCH4_REG_START               0x213c4440
+#define BCHP_DMA_AHB_CMD_RES1_SCH4_REG_END                 0x213c4440
+#define BCHP_DMA_AHB_CMD_RES1_SCH5_REG_START               0x213c4450
+#define BCHP_DMA_AHB_CMD_RES1_SCH5_REG_END                 0x213c4450
+#define BCHP_DMA_AHB_CMD_RES1_SCH6_REG_START               0x213c4460
+#define BCHP_DMA_AHB_CMD_RES1_SCH6_REG_END                 0x213c4460
+#define BCHP_DMA_AHB_CMD_RES1_SCH7_REG_START               0x213c4470
+#define BCHP_DMA_AHB_CMD_RES1_SCH7_REG_END                 0x213c4470
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x213c4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x213c4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x213c4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x213c4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x213c4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x213c4c00
+#define BCHP_DMA_AHB_CMD_CONF1_REG_START                   0x213c4e00
+#define BCHP_DMA_AHB_CMD_CONF1_REG_END                     0x213c4e00
+#define BCHP_MAC_AHB_REG_START                             0x213c5000
+#define BCHP_MAC_AHB_REG_END                               0x213c500c
+#define BCHP_LLM_AHB_REG_START                             0x213c8000
+#define BCHP_LLM_AHB_REG_END                               0x213c805c
+#define BCHP_PHY1_REG_START                                0x213d8000
+#define BCHP_PHY1_REG_END                                  0x213dc7fc
+#define BCHP_PHY_REG_START                                 0x213e0000
+#define BCHP_PHY_REG_END                                   0x213e47fc
+#define BCHP_ECL_REG_START                                 0x213e8000
+#define BCHP_ECL_REG_END                                   0x213ecb20
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x213ed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x213ed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x213ed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x213ed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x213ed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x213ed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x213ed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x213ed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x213ed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x213ed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x213ed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x213ed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x213ed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x213ed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x213ed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x213ed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x213ed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x213ed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x213ed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x213ed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x213ed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x213ed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x213ed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x213ed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x213ed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x213ed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x213ed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x213ed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x213ed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x213ed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x213ed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x213ed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x213ed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x213ed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x213ed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x213ed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x213ed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x213ed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x213ed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x213ed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x213ed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x213ed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x213ed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x213ed828
+#define BCHP_GMII_REG_START                                0x213edc00
+#define BCHP_GMII_REG_END                                  0x213edc58
+#define BCHP_MAC_APB_REG_START                             0x213f0000
+#define BCHP_MAC_APB_REG_END                               0x213f14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x213f4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x213f4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x213f4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x213f406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x213f4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x213f40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x213f40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x213f40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x213f4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x213f412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x213f4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x213f416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x213f4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x213f41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x213f41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x213f41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x213f4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x213f422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x213f4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x213f426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x213f4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x213f42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x213f42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x213f42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x213f4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x213f432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x213f4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x213f436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x213f4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x213f43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x213f43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x213f43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x213f4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x213f442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x213f4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x213f446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x213f4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x213f44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x213f44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x213f44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x213f4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x213f452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x213f4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x213f4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x213f4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x213f486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x213f4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x213f48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x213f48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x213f48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x213f4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x213f492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x213f4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x213f496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x213f4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x213f49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x213f49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x213f49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x213f4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x213f4a2c
+#define BCHP_DMA_IO2MEM_CH_PHY1_Global_REG_START           0x213f5000
+#define BCHP_DMA_IO2MEM_CH_PHY1_Global_REG_END             0x213f5014
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH0_REG_START        0x213f5040
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH0_REG_END          0x213f506c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH1_REG_START        0x213f5080
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH1_REG_END          0x213f50ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH2_REG_START        0x213f50c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH2_REG_END          0x213f50ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH3_REG_START        0x213f5100
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH3_REG_END          0x213f512c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH4_REG_START        0x213f5140
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH4_REG_END          0x213f516c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH5_REG_START        0x213f5180
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH5_REG_END          0x213f51ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH6_REG_START        0x213f51c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH6_REG_END          0x213f51ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH7_REG_START        0x213f5200
+#define BCHP_DMA_IO2MEM_SUBCH_PHY1_SUBCH7_REG_END          0x213f522c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x213f6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x213f6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x213f6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x213f6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x213f6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x213f6828
+#define BCHP_DMA_MEM2IO_CH_PHY1_CONFIG_REG_START           0x213f6c00
+#define BCHP_DMA_MEM2IO_CH_PHY1_CONFIG_REG_END             0x213f6c28
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x213f8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x213f8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x213f8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x213f8d84
+#define BCHP_LLM_APB_REG_START                             0x213fc000
+#define BCHP_LLM_APB_REG_END                               0x213fd00c
+#define BCHP_TRX_REG_START                                 0x213fe000
+#define BCHP_TRX_REG_END                                   0x213fe554
+#define BCHP_MOCA_TIMER_REG_START                          0x213fe800
+#define BCHP_MOCA_TIMER_REG_END                            0x213fe8ec
+#define BCHP_MOCA_GPIO_REG_START                           0x213fec00
+#define BCHP_MOCA_GPIO_REG_END                             0x213fec18
+#define BCHP_EXTRAS_REG_START                              0x213ff000
+#define BCHP_EXTRAS_REG_END                                0x213ff118
+#define BCHP_MOCA_BSC_REG_START                            0x213ff400
+#define BCHP_MOCA_BSC_REG_END                              0x213ff458
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x213ffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x213ffc14
+#define BCHP_AHB_M2M_DMA_REG_START                         0x213ffc20
+#define BCHP_AHB_M2M_DMA_REG_END                           0x213ffc2c
+#define BCHP_MOCA_L2_REG_START                             0x213ffc40
+#define BCHP_MOCA_L2_REG_END                               0x213ffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x213ffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x213ffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x213ffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x213ffd9c
+#define BCHP_MC_GLB_0_REG_START                            0x21500000
+#define BCHP_MC_GLB_0_REG_END                              0x21500010
+#define BCHP_MC_SRAM_REMAP_0_REG_START                     0x21500020
+#define BCHP_MC_SRAM_REMAP_0_REG_END                       0x21500034
+#define BCHP_MC_RBF_REORDER_0_0_REG_START                  0x21500040
+#define BCHP_MC_RBF_REORDER_0_0_REG_END                    0x2150007c
+#define BCHP_MC_INTR2_0_REG_START                          0x21500080
+#define BCHP_MC_INTR2_0_REG_END                            0x215000c4
+#define BCHP_MC_BPM_0_REG_START                            0x215000e0
+#define BCHP_MC_BPM_0_REG_END                              0x215000e4
+#define BCHP_MC_CHN_CFG_0_REG_START                        0x21500100
+#define BCHP_MC_CHN_CFG_0_REG_END                          0x21500140
+#define BCHP_MC_CHN_TIM_0_REG_START                        0x21500200
+#define BCHP_MC_CHN_TIM_0_REG_END                          0x21500258
+#define BCHP_MC_ARB_0_REG_START                            0x21500300
+#define BCHP_MC_ARB_0_REG_END                              0x215003bc
+#define BCHP_MC_UBUSIF_0_0_REG_START                       0x21500400
+#define BCHP_MC_UBUSIF_0_0_REG_END                         0x21500430
+#define BCHP_MC_UBUSIF_1_0_REG_START                       0x21500440
+#define BCHP_MC_UBUSIF_1_0_REG_END                         0x21500470
+#define BCHP_MC_MCPIF_0_0_REG_START                        0x21500500
+#define BCHP_MC_MCPIF_0_0_REG_END                          0x21500520
+#define BCHP_MC_EXACC_0_REG_START                          0x21500580
+#define BCHP_MC_EXACC_0_REG_END                            0x215005dc
+#define BCHP_MC_LMBIF_0_0_REG_START                        0x21500600
+#define BCHP_MC_LMBIF_0_0_REG_END                          0x2150060c
+#define BCHP_MC_EDIS_0_0_REG_START                         0x21500800
+#define BCHP_MC_EDIS_0_0_REG_END                           0x215008fc
+#define BCHP_MC_EDIS_1_0_REG_START                         0x21500900
+#define BCHP_MC_EDIS_1_0_REG_END                           0x215009fc
+#define BCHP_MC_STATS_0_REG_START                          0x21500a00
+#define BCHP_MC_STATS_0_REG_END                            0x21500abc
+#define BCHP_MC_CAP_0_REG_START                            0x21500b00
+#define BCHP_MC_CAP_0_REG_END                              0x21500b6c
+#define BCHP_MC_CORE_ATW_0_REG_START                       0x21500c00
+#define BCHP_MC_CORE_ATW_0_REG_END                         0x21500db8
+#define BCHP_MC_SEC_INTR2_0_REG_START                      0x21500e00
+#define BCHP_MC_SEC_INTR2_0_REG_END                        0x21500e14
+#define BCHP_MC_RGR_BRIDGE_0_REG_START                     0x21500e80
+#define BCHP_MC_RGR_BRIDGE_0_REG_END                       0x21500e90
+#define BCHP_MC_SCBARB_0_REG_START                         0x21501000
+#define BCHP_MC_SCBARB_0_REG_END                           0x215014f0
+#define BCHP_MC_SCRAM_CTRL_0_REG_START                     0x21501500
+#define BCHP_MC_SCRAM_CTRL_0_REG_END                       0x21501548
+#define BCHP_DSCRAM_KEYGEN_0_REG_START                     0x21501600
+#define BCHP_DSCRAM_KEYGEN_0_REG_END                       0x21501734
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_0_REG_START           0x21501800
+#define BCHP_MC_UBUS_NONSEC_ARCH_REG_0_REG_END             0x21501b5c
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_0_REG_START            0x21501c00
+#define BCHP_MC_SCB_NONSEC_ARCH_REG_0_REG_END              0x21501f5c
+#define BCHP_MC_MSA_0_REG_START                            0x21502000
+#define BCHP_MC_MSA_0_REG_END                              0x2150223c
+#define BCHP_PHY_CONTROL_REGS_0_REG_START                  0x21504000
+#define BCHP_PHY_CONTROL_REGS_0_REG_END                    0x21504218
+#define BCHP_PHY_BYTE_LANE_0_0_REG_START                   0x21504400
+#define BCHP_PHY_BYTE_LANE_0_0_REG_END                     0x21504518
+#define BCHP_PHY_BYTE_LANE_1_0_REG_START                   0x21504600
+#define BCHP_PHY_BYTE_LANE_1_0_REG_END                     0x21504718
+#define BCHP_PHY_BYTE_LANE_2_0_REG_START                   0x21504800
+#define BCHP_PHY_BYTE_LANE_2_0_REG_END                     0x21504918
+#define BCHP_PHY_BYTE_LANE_3_0_REG_START                   0x21504a00
+#define BCHP_PHY_BYTE_LANE_3_0_REG_END                     0x21504b18
+#define BCHP_PHY_ECC_LANE_0_REG_START                      0x21504c00
+#define BCHP_PHY_ECC_LANE_0_REG_END                        0x21504d18
+
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01ffffff
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffff00
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   8
+
+/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK            0x000000ff
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT           0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_ebi.h b/include/linux/brcmstb/3390b0/bchp_ebi.h
new file mode 100644
index 000000000000..ac0988d4db20
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_ebi.h
@@ -0,0 +1,1998 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:16 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_HI_0                    0x204a0800 /* [RW] Upper 8-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_BASE_0                       0x204a0804 /* [RW] Lower 32-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x204a0808 /* [RW] EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_HI_1                    0x204a080c /* [RW] Upper 8-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_BASE_1                       0x204a0810 /* [RW] Lower 32-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x204a0814 /* [RW] EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_HI_2                    0x204a0818 /* [RW] Upper 8-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_BASE_2                       0x204a081c /* [RW] Lower 32-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x204a0820 /* [RW] EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_HI_3                    0x204a0824 /* [RW] Upper 8-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_BASE_3                       0x204a0828 /* [RW] Lower 32-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x204a082c /* [RW] EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_HI_4                    0x204a0830 /* [RW] Upper 8-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_BASE_4                       0x204a0834 /* [RW] Lower 32-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x204a0838 /* [RW] EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_HI_5                    0x204a083c /* [RW] Upper 8-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_BASE_5                       0x204a0840 /* [RW] Lower 32-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x204a0844 /* [RW] EBI CS Config 5 Register */
+#define BCHP_EBI_CS_BASE_HI_6                    0x204a0848 /* [RW] Upper 8-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_BASE_6                       0x204a084c /* [RW] Lower 32-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_CONFIG_6                     0x204a0850 /* [RW] EBI CS Config 6 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x204a0860 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x204a0864 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x204a0868 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x204a086c /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x204a0870 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x204a0874 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_6                     0x204a0878 /* [RW] EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x204a0900 /* [RW] EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x204a0918 /* [RW] EBI CS Tristate Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x204a0920 /* [RW] SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x204a09f0 /* [RW] EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_6 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_6_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_6_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_6 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_6_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_6_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_6_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_6 - EBI CS Config 6 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_6_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_6_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_6_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_6_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_6_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_6_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_6_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_6_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_6_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_6 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_6_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_6_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_6_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_6_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_6_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffff80
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   7
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK             0x00000040
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT            6
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff8000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     15
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK                      0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT                     7
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x204a0a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_hif_intr2.h b/include/linux/brcmstb/3390b0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..c4a764b58350
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_hif_intr2.h
@@ -0,0 +1,1241 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:20 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x204a1000 /* [RO] CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x204a1004 /* [WO] CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x204a1008 /* [WO] CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x204a100c /* [RO] CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x204a1010 /* [WO] CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x204a1014 /* [WO] CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x204a1018 /* [RO] PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x204a101c /* [WO] PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x204a1020 /* [WO] PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x204a1024 /* [RO] PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x204a1028 /* [WO] PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x204a102c /* [WO] PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x000c0000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  18
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK                   0x00007fc0
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT                  6
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK                   0x00000004
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT                  2
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK               0x00000002
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT              1
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x000c0000
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     18
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK                      0x00007fc0
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT                     6
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK                      0x00000004
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT                     2
+
+/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK                  0x00000002
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT                 1
+#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x000c0000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   18
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK                    0x00007fc0
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT                   6
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK                    0x00000004
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT                   2
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT               1
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             18
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK              0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT             6
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK              0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT             2
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                18
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK                 0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT                6
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK                 0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT                2
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT            1
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x000c0000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              18
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK               0x00007fc0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT              6
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK               0x00000004
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT              2
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x000c0000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  18
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK                   0x00007fc0
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT                  6
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
+#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK                   0x00000004
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT                  2
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK               0x00000002
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT              1
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x000c0000
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     18
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK                      0x00007fc0
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT                     6
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
+#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK                      0x00000004
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT                     2
+
+/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK                  0x00000002
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT                 1
+#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x000c0000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   18
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK                    0x00007fc0
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT                   6
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
+#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK                    0x00000004
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT                   2
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT               1
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             18
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK              0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT             6
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK              0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT             2
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                18
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK                 0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT                6
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
+#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK                 0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT                2
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT            1
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x000c0000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              18
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK               0x00007fc0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT              6
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:02] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK               0x00000004
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT              2
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_hif_mspi.h b/include/linux/brcmstb/3390b0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..13f20263007c
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_hif_mspi.h
@@ -0,0 +1,1282 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:17 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x204a3400 /* [RW] SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x204a3404 /* [RW] SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x204a3408 /* [RW] SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x204a340c /* [RW] SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x204a3410 /* [RW] NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x204a3414 /* [RW] ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x204a3418 /* [RW] SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x204a3420 /* [RW] MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x204a3424 /* [RO] CPTQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR3                      0x204a3428 /* [RW] SPCR3 REGISTER */
+#define BCHP_HIF_MSPI_REVISION                   0x204a342c /* [RO] REVISION ID REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x204a3440 /* [RW] Most significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x204a3444 /* [RW] Least significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x204a3448 /* [RW] Most significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x204a344c /* [RW] Least significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x204a3450 /* [RW] Most significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x204a3454 /* [RW] Least significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x204a3458 /* [RW] Most significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x204a345c /* [RW] Least significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x204a3460 /* [RW] Most significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x204a3464 /* [RW] Least significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x204a3468 /* [RW] Most significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x204a346c /* [RW] Least significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x204a3470 /* [RW] Most significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x204a3474 /* [RW] Least significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x204a3478 /* [RW] Most significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x204a347c /* [RW] Least significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x204a3480 /* [RW] Most significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x204a3484 /* [RW] Least significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x204a3488 /* [RW] Most significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x204a348c /* [RW] Least significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x204a3490 /* [RW] Most significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x204a3494 /* [RW] Least significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x204a3498 /* [RW] Most significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x204a349c /* [RW] Least significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x204a34a0 /* [RW] Most significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x204a34a4 /* [RW] Least significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x204a34a8 /* [RW] Most significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x204a34ac /* [RW] Least significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x204a34b0 /* [RW] Most significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x204a34b4 /* [RW] Least significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x204a34b8 /* [RW] Most significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x204a34bc /* [RW] Least significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x204a34c0 /* [RW] Most significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x204a34c4 /* [RW] Least significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x204a34c8 /* [RW] Most significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x204a34cc /* [RW] Least significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x204a34d0 /* [RW] Most significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x204a34d4 /* [RW] Least significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x204a34d8 /* [RW] Most significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x204a34dc /* [RW] Least significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x204a34e0 /* [RW] Most significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x204a34e4 /* [RW] Least significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x204a34e8 /* [RW] Most significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x204a34ec /* [RW] Least significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x204a34f0 /* [RW] Most significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x204a34f4 /* [RW] Least significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x204a34f8 /* [RW] Most significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x204a34fc /* [RW] Least significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x204a3500 /* [RW] Most significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x204a3504 /* [RW] Least significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x204a3508 /* [RW] Most significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x204a350c /* [RW] Least significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x204a3510 /* [RW] Most significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x204a3514 /* [RW] Least significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x204a3518 /* [RW] Most significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x204a351c /* [RW] Least significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x204a3520 /* [RW] Most significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x204a3524 /* [RW] Least significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x204a3528 /* [RW] Most significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x204a352c /* [RW] Least significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x204a3530 /* [RW] Most significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x204a3534 /* [RW] Least significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x204a3538 /* [RW] Most significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x204a353c /* [RW] Least significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x204a3540 /* [RW] 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x204a3544 /* [RW] 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x204a3548 /* [RW] 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x204a354c /* [RW] 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x204a3550 /* [RW] 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x204a3554 /* [RW] 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x204a3558 /* [RW] 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x204a355c /* [RW] 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x204a3560 /* [RW] 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x204a3564 /* [RW] 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x204a3568 /* [RW] 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x204a356c /* [RW] 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x204a3570 /* [RW] 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x204a3574 /* [RW] 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x204a3578 /* [RW] 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x204a357c /* [RW] 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x204a3580 /* [RW] Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x204a3584 /* [RW] Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xfffffe00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    9
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000100
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              8
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* union - case data_reg_8 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK          0x000000c0
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT         6
+
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK               0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT              2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT            0x00000000
+
+/* union - case data_reg_32 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK              0x000000fc
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT             2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT           0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR3 - SPCR3 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
+#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK                         0xfffffc00
+#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT                        10
+
+/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
+#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK                            0x00000200
+#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT                           9
+#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK                     0x00000100
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT                    8
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT                  0x00000000
+
+/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK                         0x00000080
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT                        7
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT                      0x00000000
+
+/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK                        0x00000040
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT                       6
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT                     0x00000000
+
+/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
+#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK                          0x00000030
+#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT                         4
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK                          0x0000000c
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
+#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK                            0x00000002
+#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT                           1
+#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
+#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK                            0x00000001
+#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT                           0
+#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *REVISION - REVISION ID REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_REVISION_reserved0_MASK                      0xffffff00
+#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT                     8
+
+/* HIF_MSPI :: REVISION :: major [07:04] */
+#define BCHP_HIF_MSPI_REVISION_major_MASK                          0x000000f0
+#define BCHP_HIF_MSPI_REVISION_major_SHIFT                         4
+#define BCHP_HIF_MSPI_REVISION_major_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: REVISION :: minor [03:00] */
+#define BCHP_HIF_MSPI_REVISION_minor_MASK                          0x0000000f
+#define BCHP_HIF_MSPI_REVISION_minor_SHIFT                         0
+#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT                       0x00000005
+
+/***************************************************************************
+ *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/3390b0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..f61a7f7d38ee
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,557 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Wed Jun 10 03:09:32 2015
+ *                 Full Compile MD5 Checksum  e8bde4108283f67d401938287dbb6bde
+ *                     (minus title and desc)
+ *                 MD5 Checksum               56f0f944fbd407545cd964e7b4e7f7b0
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008008
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x204a1a00 /* [RO] CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x204a1a04 /* [WO] CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x204a1a08 /* [WO] CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x204a1a0c /* [RO] CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x204a1a10 /* [WO] CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x204a1a14 /* [WO] CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x204a1a18 /* [RO] PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x204a1a1c /* [WO] PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x204a1a20 /* [WO] PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x204a1a24 /* [RO] PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x204a1a28 /* [WO] PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x204a1a2c /* [WO] PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_irq0.h b/include/linux/brcmstb/3390b0/bchp_irq0.h
new file mode 100644
index 000000000000..288664132c75
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_irq0.h
@@ -0,0 +1,157 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:20 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x2040a600 /* [RW] Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x2040a604 /* [RW] Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xfffffc00
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: gio_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000200
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            9
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: iice_irqen [08:08] */
+#define BCHP_IRQ0_IRQEN_iice_irqen_MASK                            0x00000100
+#define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT                           8
+#define BCHP_IRQ0_IRQEN_iice_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [07:07] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x00000080
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           7
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x00000040
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           6
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000020
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             5
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00000004
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          2
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00000002
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          1
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00000001
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          0
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xfffffc00
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: gioirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000200
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             9
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: iiceirq [08:08] */
+#define BCHP_IRQ0_IRQSTAT_iiceirq_MASK                             0x00000100
+#define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT                            8
+#define BCHP_IRQ0_IRQSTAT_iiceirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [07:07] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x00000080
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            7
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x00000040
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            6
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000020
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              5
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uairq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00000004
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          2
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00000002
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          1
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00000001
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          0
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_nand.h b/include/linux/brcmstb/3390b0/bchp_nand.h
new file mode 100644
index 000000000000..9c3c51056c28
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_nand.h
@@ -0,0 +1,3748 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:18 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x204a2800 /* [RO] NAND Revision */
+#define BCHP_NAND_CMD_START                      0x204a2804 /* [RW] Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x204a2808 /* [RW] Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x204a280c /* [RW] Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x204a2810 /* [RW] Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x204a2814 /* [RO] Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x204a2818 /* [RW] Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x204a281c /* [RW] Nand Flash EBI CS XOR masking on CPU address Control */
+#define BCHP_NAND_LL_OP                          0x204a2820 /* [RW] Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x204a2824 /* [RW] Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x204a2828 /* [RW] Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x204a2850 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS0                 0x204a2854 /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS0                     0x204a2858 /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x204a285c /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x204a2860 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x204a2864 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS1                 0x204a2868 /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS1                     0x204a286c /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x204a2870 /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x204a2874 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x204a2878 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS2                 0x204a287c /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS2                     0x204a2880 /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x204a2884 /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x204a2888 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x204a288c /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS3                 0x204a2890 /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS3                     0x204a2894 /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x204a2898 /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x204a289c /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x204a28a0 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS4                 0x204a28a4 /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS4                     0x204a28a8 /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x204a28ac /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x204a28b0 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x204a28b4 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS5                 0x204a28b8 /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS5                     0x204a28bc /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x204a28c0 /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x204a28c4 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS6                0x204a28c8 /* [RW] Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS6                 0x204a28cc /* [RW] Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS6                     0x204a28d0 /* [RW] Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS6                   0x204a28d4 /* [RW] Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS6                   0x204a28d8 /* [RW] Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x204a28dc /* [RW] Correctable Error Reporting Threshold */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x204a28e0 /* [RW] Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x204a28e4 /* [RW] Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x204a28e8 /* [RW] Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x204a28ec /* [RW] Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x204a28f0 /* [RW] Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x204a28fc /* [RW] Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x204a2900 /* [RO] Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x204a2904 /* [RO] Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x204a2908 /* [RO] Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x204a290c /* [RO] ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x204a2910 /* [RO] ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x204a2914 /* [RO] ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x204a2918 /* [RO] ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x204a291c /* [RO] Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x204a2920 /* [RO] Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x204a2924 /* [RO] Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x204a2928 /* [RO] Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x204a292c /* [RO] Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x204a2930 /* [RO] Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x204a2934 /* [RO] Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x204a2938 /* [RO] Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x204a293c /* [RO] Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x204a2940 /* [RO] Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x204a2944 /* [RO] Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x204a2948 /* [RW] ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x204a294c /* [RO] ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x204a2950 /* [RW] Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x204a2994 /* [RO] Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x204a2998 /* [RO] Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x204a299c /* [RO] Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x204a2a00 /* [RO] Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x204a2a04 /* [RO] Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x204a2a08 /* [RO] Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x204a2a0c /* [RO] Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x204a2a10 /* [RO] Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x204a2a14 /* [RO] Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x204a2a18 /* [RO] Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x204a2a1c /* [RO] Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x204a2a20 /* [RO] Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x204a2a24 /* [RO] Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x204a2a28 /* [RO] Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x204a2a2c /* [RO] Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x204a2a30 /* [RO] Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x204a2a34 /* [RO] Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x204a2a38 /* [RO] Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x204a2a3c /* [RO] Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x204a2a80 /* [RW] Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x204a2a84 /* [RW] Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x204a2a88 /* [RW] Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x204a2a8c /* [RW] Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x204a2a90 /* [RW] Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x204a2a94 /* [RW] Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x204a2a98 /* [RW] Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x204a2a9c /* [RW] Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x204a2aa0 /* [RW] Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x204a2aa4 /* [RW] Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x204a2aa8 /* [RW] Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x204a2aac /* [RW] Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x204a2ab0 /* [RW] Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x204a2ab4 /* [RW] Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x204a2ab8 /* [RW] Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x204a2abc /* [RW] Nand Flash Spare Area Write Bytes 60-63 */
+#define BCHP_NAND_DDR_TIMING                     0x204a2ac0 /* [RW] Nand Flash DDR TIMING */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL             0x204a2ac4 /* [RW] Nand Flash Calibration Control for Master DLL */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD          0x204a2ac8 /* [RW] Nand Flash Calibration Period */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT            0x204a2acc /* [RO] Nand Flash Calibration Status for Master DLL */
+#define BCHP_NAND_DDR_NCDL_MODE                  0x204a2ad0 /* [RW] Nand Flash NCDL mode for Slave DLLs */
+#define BCHP_NAND_DDR_NCDL_OFFSET                0x204a2ad4 /* [RW] Nand Flash NCDL offset for Slave DLLs */
+#define BCHP_NAND_DDR_PHY_CTL                    0x204a2ad8 /* [RW] Nand Flash DDR PHY CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_CTL               0x204a2adc /* [RW] Nand Flash DDR PHY BIST CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_STAT              0x204a2ae0 /* [RO] Nand Flash DDR PHY BIST STATUS */
+#define BCHP_NAND_DDR_DIAG_STAT0                 0x204a2ae4 /* [RO] Nand Flash DDR DIAG STATUS0 */
+#define BCHP_NAND_DDR_DIAG_STAT1                 0x204a2ae8 /* [RO] Nand Flash DDR DIAG STATUS1 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: reserved0 [31:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0xffff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000007
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000001
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:05] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5
+
+/* NAND :: CMD_START :: OPCODE [04:00] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK                      0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT                     29
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT                   0x00000001
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK                0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT               31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT             0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK               0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT              7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK               0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT              6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK               0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT              5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK               0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT              4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK               0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT              3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK               0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT              2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK               0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT              1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK               0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT              0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS0 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS0 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS0 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS0 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS0 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS0_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS0_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS0_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS0_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS1 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS1 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS1 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS1 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS1 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS1_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS1_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS1_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS1_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS2 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS2 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS2 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS2 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS2 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS2_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS2_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS2_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS2_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS3 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS3 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS3 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS3 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS3 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS3_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS3_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS3_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS3_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS4 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS4 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS4 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS4 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS4 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS4_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS4_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS4_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS4_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS5 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS5 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS5 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS5 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS5 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS5_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS5_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS5_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS5_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS6 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS6 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS6 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS6 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS6 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS6 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS6 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS6_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS6 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS6_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS6_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS6_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS6_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS6 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS6_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS6_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS6_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS6_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS6_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS6_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS6_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS6 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS6 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS6 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS6_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS6_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS6_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS6_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS6_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS6_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xfffff000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          12
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *DDR_TIMING - Nand Flash DDR TIMING
+ ***************************************************************************/
+/* NAND :: DDR_TIMING :: reserved0 [31:28] */
+#define BCHP_NAND_DDR_TIMING_reserved0_MASK                        0xf0000000
+#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT                       28
+
+/* NAND :: DDR_TIMING :: tCCS [27:24] */
+#define BCHP_NAND_DDR_TIMING_tCCS_MASK                             0x0f000000
+#define BCHP_NAND_DDR_TIMING_tCCS_SHIFT                            24
+#define BCHP_NAND_DDR_TIMING_tCCS_DEFAULT                          0x00000008
+
+/* NAND :: DDR_TIMING :: tCAD [23:20] */
+#define BCHP_NAND_DDR_TIMING_tCAD_MASK                             0x00f00000
+#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT                            20
+#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT                          0x00000004
+
+/* NAND :: DDR_TIMING :: reserved1 [19:17] */
+#define BCHP_NAND_DDR_TIMING_reserved1_MASK                        0x000e0000
+#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT                       17
+
+/* NAND :: DDR_TIMING :: tWHR [16:12] */
+#define BCHP_NAND_DDR_TIMING_tWHR_MASK                             0x0001f000
+#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT                            12
+#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT                          0x00000014
+
+/* NAND :: DDR_TIMING :: tCS [11:08] */
+#define BCHP_NAND_DDR_TIMING_tCS_MASK                              0x00000f00
+#define BCHP_NAND_DDR_TIMING_tCS_SHIFT                             8
+#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT                           0x00000002
+
+/* NAND :: DDR_TIMING :: tWB [07:04] */
+#define BCHP_NAND_DDR_TIMING_tWB_MASK                              0x000000f0
+#define BCHP_NAND_DDR_TIMING_tWB_SHIFT                             4
+#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT                           0x0000000f
+
+/* NAND :: DDR_TIMING :: tADL [03:00] */
+#define BCHP_NAND_DDR_TIMING_tADL_MASK                             0x0000000f
+#define BCHP_NAND_DDR_TIMING_tADL_SHIFT                            0
+#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT                          0x00000007
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK                0xfffffff0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT               4
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK           0x00000008
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT          3
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT        0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK             0x00000004
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT            2
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT          0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK               0x00000002
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT              1
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT            0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK                 0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT                0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK             0xfff00000
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT            20
+
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK          0x000fffff
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT         0
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK               0xffff0000
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT              16
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK              0x0000ff00
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT             8
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT           0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK               0x000000fe
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT              1
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK              0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT             0
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT           0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK                     0xffffffe0
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT                    5
+
+/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK                        0x00000010
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT                       4
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT                     0x00000000
+
+/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK                     0x0000000e
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT                    1
+
+/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK                        0x00000001
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT                       0
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK                   0xfe000000
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT                  25
+
+/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK                  0x01ff0000
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT                 16
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT               0x00000000
+
+/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK                   0x0000fe00
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT                  9
+
+/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK                  0x000001ff
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT                 0
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT               0x00000000
+
+/***************************************************************************
+ *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK                       0xfffffffc
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT                      2
+
+/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK                        0x00000002
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT                       1
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT                     0x00000000
+
+/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK                       0x00000001
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT                      0
+
+/***************************************************************************
+ *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK                  0xffffffe0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT                 5
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK                   0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT                  4
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT                0x00000000
+
+/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK                  0x0000000e
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT                 1
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT                0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK                 0xffffff80
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT                7
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK          0x00000040
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT         6
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK          0x00000020
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT         5
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK          0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT         4
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK          0x00000008
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT         3
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK               0x00000004
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT              2
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK               0x00000002
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT              1
+
+/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT                0
+
+/***************************************************************************
+ *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x204a2c00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/3390b0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..31bb241393e6
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,814 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:19 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD0/EMMC0) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x204a0100 /* [RW] SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x204a0104 /* [RW] SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x204a0108 /* [RW] SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE         0x204a010c /* [RW] SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x204a0110 /* [RW] SDIO CAPABILITIES override Register[31:0] */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x204a0114 /* [RW] SDIO CAPABILITIES override Register[63:32] */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x204a0118 /* [RW] SDIO PRESET_INIT/PRESET_DS override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x204a011c /* [RW] SDIO PRESET_HS/PRESET_SDR12 override Register */
+#define BCHP_SDIO_0_CFG_PRESET3                  0x204a0120 /* [RW] SDIO PRESET_SDR25/PRESET_SDR50 override Register */
+#define BCHP_SDIO_0_CFG_PRESET4                  0x204a0124 /* [RW] SDIO PRESET_SDR104/PRESET_DDR50 override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x204a0128 /* [RW] SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x204a012c /* [RW] SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x204a0130 /* [RW] SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x204a0134 /* [RW] SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x204a0138 /* [RW] SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x204a013c /* [RW] SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY            0x204a0140 /* [RO] Debug TAP delay setting register */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS  0x204a0144 /* [RO] Debug A2S Bridge Status */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x204a0148 /* [RO] Debug register to read AHB req start address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR   0x204a014c /* [RO] Debug register to read AHB req end address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x204a0150 /* [RW] Disable Client Init */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL               0x204a0154 /* [RW] SD Pin Select */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT              0x204a0158 /* [RW] Max Current Override */
+#define BCHP_SDIO_0_CFG_VERSION                  0x204a01f0 /* [RO] SDIO VERSION Register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x204a01fc /* [RW] SDIO Scratch Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK             0x0ffc0000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT            18
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK        0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT       17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK             0x000003fc
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT            2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK          0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT         0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT       0x00000003
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000003
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK            0xfffffffe
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT           1
+
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK     0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT    0
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0xc0000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK                     0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT                    29
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK                0x10000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT               28
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK                    0x08000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT                   27
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK                 0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT                26
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK                 0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT                25
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK               0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT              23
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK                         0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT                        22
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT                      0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK                   0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT                  21
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK                    0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT                   20
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK                        0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT                       19
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK               0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT              18
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK                0x00030000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT               16
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK                0x0000ff00
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT               8
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK                 0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT                7
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK                    0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT                   6
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK             0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0xfc000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   26
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK               0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT              25
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    24
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x00ff0000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    16
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK                0x0000c000
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT               14
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK                   0x00002000
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT                  13
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK                    0x00001000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT                   12
+
+/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK                  0x00000f00
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT                 8
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK                    0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT                   7
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK                     0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT                    6
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK                     0x00000020
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT                    5
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK                     0x00000010
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT                    4
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT                   3
+
+/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK                        0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT                       2
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK                       0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT                      1
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT                    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK                        0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT                       0
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK                   0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT                  16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT                  0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK                  0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT                 0
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT               0x00000003
+
+/***************************************************************************
+ *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK                 0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT                0
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT              0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:05] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffe0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     5
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000001f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xffffffc0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     6
+
+/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT                  0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT                0x00000020
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *DEBUG_TAP_DLY - Debug TAP delay setting register
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK               0xfffff000
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT              12
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK      0x00000f00
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT     8
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK               0x00000080
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT              7
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK      0x0000007f
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT     0
+
+/***************************************************************************
+ *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK     0x60000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT    29
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK  0x10000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK     0x0e000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT    25
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK     0x0000ff80
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT    7
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK     0x00000070
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT    4
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK     0x00000008
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT    3
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK     0x00000007
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT    0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK   0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT  0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK       0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT      0
+
+/***************************************************************************
+ *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK   0xfffffffe
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT  1
+
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SD_PIN_SEL - SD Pin Select
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK                    0x00000003
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT                   0
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MAX_CURRENT - Max Current Override
+ ***************************************************************************/
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK                  0x80000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT                 31
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK                 0x7f000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT                24
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK             0x00ff0000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT            16
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK             0x0000ff00
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT            8
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK             0x000000ff
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT            0
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK                     0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT                    24
+
+/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK                      0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT                     16
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT                   0x00000003
+
+/* SDIO_0_CFG :: VERSION :: IP_VERSION [15:00] */
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_MASK                    0x0000ffff
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_SHIFT                   0
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_DEFAULT                 0x00001170
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/3390b0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..e47e4d0239b8
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7157 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Wed Jun 10 03:09:41 2015
+ *                 Full Compile MD5 Checksum  e8bde4108283f67d401938287dbb6bde
+ *                     (minus title and desc)
+ *                 MD5 Checksum               56f0f944fbd407545cd964e7b4e7f7b0
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008008
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x20404000 /* [RO] Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x20404004 /* [RO] Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x20404008 /* [RO] BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x2040401c /* [RO] Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x20404020 /* [RO] Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x20404024 /* [RO] Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x20404028 /* [RW] OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x2040402c /* [RW] OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x20404030 /* [RO] OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x20404034 /* [RO] OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x20404038 /* [RW] Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x2040403c /* [RW] Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x20404040 /* [RW] Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x20404044 /* [RW] Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x20404048 /* [RW] Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x2040404c /* [RW] Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x20404050 /* [RW] Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x20404054 /* [RW] Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x20404058 /* [RW] Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x2040405c /* [RW] Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x20404060 /* [RW] Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x20404064 /* [RW] Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x20404068 /* [RW] Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x2040406c /* [RW] Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x20404070 /* [RW] Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x20404074 /* [RW] Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x20404078 /* [RW] General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x2040407c /* [RW] General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x20404080 /* [RW] General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x20404084 /* [RW] General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x20404088 /* [RW] General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x2040408c /* [RW] General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x20404090 /* [RW] General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x20404094 /* [RW] General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x20404098 /* [RO] General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x2040409c /* [RO] General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x204040a0 /* [RO] General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x204040a4 /* [RW] General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x204040a8 /* [RW] General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x204040ac /* [RW] General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x204040b0 /* [RW] General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x204040b4 /* [RW] General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x204040b8 /* [RW] General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3       0x204040bc /* [RO] General status register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4       0x204040c0 /* [RO] General status register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x20404100 /* [RW] Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x20404104 /* [RW] Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x20404108 /* [RW] Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x2040410c /* [RW] Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x20404110 /* [RW] Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x20404114 /* [RW] Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x20404118 /* [RW] Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x2040411c /* [RW] Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x20404120 /* [RW] Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x20404124 /* [RW] Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x20404128 /* [RW] Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x2040412c /* [RW] Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x20404130 /* [RW] Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x20404134 /* [RW] Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x20404138 /* [RW] Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x2040413c /* [RW] Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x20404140 /* [RW] Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x20404144 /* [RW] Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x20404148 /* [RW] Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x2040414c /* [RW] Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x20404150 /* [RW] Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x20404154 /* [RW] Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x20404158 /* [RW] Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x2040415c /* [RW] Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x20404160 /* [RW] Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x20404164 /* [RW] Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x20404168 /* [RW] Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x20404300 /* [RW] Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x20404304 /* [RW] Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x20404308 /* [RW] Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x2040430c /* [RW] Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x20404310 /* [RO] Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x20404314 /* [RO] Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x20404318 /* [WO] Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x2040431c /* [WO] Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x20404320 /* [RO] Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x20404324 /* [RO] Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x20404328 /* [RO] Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x2040432c /* [RO] Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x20404330 /* [WO] Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x20404334 /* [WO] Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x20404338 /* [RO] Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x2040433c /* [RO] Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x20404340 /* [RO] Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x20404344 /* [RO] Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x20404348 /* [RW] Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x2040434c /* [RW] One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x20404350 /* [RW] One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x20404354 /* [RW] One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x20404358 /* [RW] One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x2040435c /* [RW] One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x20404360 /* [RW] One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE    0x20404364 /* [RW] Router software init 0 mask */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE    0x20404368 /* [RW] Router software init 0 mask */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x2040436c /* [RW] Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x20404370 /* [RW] Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x20404380 /* [RW] Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x20404384 /* [RO] Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x20404388 /* [RW] Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x2040438c /* [RO] Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x20404390 /* [RW] Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x20404394 /* [RW] EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x20404398 /* [RW] EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x204043a0 /* [RW] VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x204043a4 /* [RO] VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0      0x204043a8 /* [RW] UART Router select 0 */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1      0x204043ac /* [RW] UART Router select 1 */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x20404400 /* [RW] Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x20404420 /* [RO] SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x20404424 /* [RW] SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x20404514 /* [RW] Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x20404518 /* [RW] Test configuration */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL 0x20404520 /* [RW] Power Cycle Control */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY  0x20404524 /* [RW] Power Cycle Delay */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6         0x20404528 /* [RW] General control register 6 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7         0x2040452c /* [RW] General control register 7 */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x33900010
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x33900010
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffff8000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            15
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [14:14] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [13:09] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x00003e00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_1 [08:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_MASK          0x000001e0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_SHIFT         5
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_MASK          0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_2_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_MASK          0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_SHIFT         3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_3_DEFAULT       0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie0_rc_ep [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie0_rc_ep_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie1_rc_ep [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie1_rc_ep_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie2_rc_ep [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie2_rc_ep_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie2_rc_ep_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie2_rc_ep_DEFAULT  0x00000001
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_rsvd_0 [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_MASK          0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_rsvd_0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT   0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_6 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_5 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_4 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p0_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uda_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uda_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uda_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uda_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rdp_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rdp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_p1_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_p1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0x001ffe00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_d31ofdmb_dis [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdmb_dis_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_bonded_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_bonded_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_bonded_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_bonded_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gphy_trim_dac [15:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_MASK 0x0000f000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gphy_trim_dac_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rgmii_1_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rgmii_1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_d31ofdma_dis [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_d31ofdma_dis_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_mtsif_enc_ctrl_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mtsif_enc_ctrl_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie2_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie2_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie2_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_memc0_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_memc0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_eaglet_disable [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_eaglet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie0_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_gisb_to_ubus_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_gisb_to_ubus_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_20_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_20_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_6 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_6_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_6_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_5 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_4 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p0_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p0_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uda_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uda_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uda_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rdp_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rdp_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rdp_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_p1_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_p1_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0x001ffe00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_d31ofdmb_dis [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdmb_dis_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdmb_dis_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_bonded_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_bonded_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_bonded_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gphy_trim_dac [15:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_MASK 0x0000f000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gphy_trim_dac_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rgmii_1_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rgmii_1_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_d31ofdma_dis [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdma_dis_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_d31ofdma_dis_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_mtsif_enc_ctrl_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mtsif_enc_ctrl_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mtsif_enc_ctrl_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie2_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie2_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie2_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_memc0_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_memc0_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_memc0_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_eaglet_disable [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_eaglet_disable_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_eaglet_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie0_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie0_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_gisb_to_ubus_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_gisb_to_ubus_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_20_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_20_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_pin_sel [04:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_MASK        0x00000018
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio1_pin_sel [02:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_MASK        0x00000006
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: core0_sw_init_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_core0_sw_init_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_3_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: disable_rg_wd_reset [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_rg_wd_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: disable_host_wd_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_disable_host_wd_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT    1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT   1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffffc0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   6
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_amp_en [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_gmii [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_modehv [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xe0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   29
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_060 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_060_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_059 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_058 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [20:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x001f0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xffffffe0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   5
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_018 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_018_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_017 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_017_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_016 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_016_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_015 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_015_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_014 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_014_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_STATUS_3 - General status register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_4 - General status register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK          0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK          0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT       0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_000 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_RGMII1_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_EXT_IRQB_6       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_TP_IN_00         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_000_PM_GPIO_000      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_clk [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_EMMC1_CLK       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_clk_PM_EMMC1_CLK    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: emmc1_cmd [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_EMMC1_CMD       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_emmc1_cmd_PM_EMMC1_CMD    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_nand_dqs [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_MASK         0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_EBI_NAND_DQS 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_nand_dqs_PM_EBI_NAND_DQS 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_waitb [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_waitb_PM_EBI_WAITB    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs2b [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_EBI_CS2B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs2b_ALT_TP_IN_10     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs1b [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_EBI_CS1B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs1b_ALT_TP_IN_09     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_cs0b [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_EBI_CS0B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_cs0b_ALT_TP_IN_08     1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_008 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_RGMII1_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_UART_RXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_TP_IN_08         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_008_PM_GPIO_008      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_007 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_MII_RXEN_RGMII1_RXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_EXT_IRQB_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_TP_IN_07         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_007_PM_GPIO_007      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_006 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_RGMII1_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_TP_IN_06         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_006_PM_GPIO_006      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_005 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_RGMII1_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_TP_IN_05         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_005_PM_GPIO_005      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_004 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_RGMII1_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_TP_IN_04         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_004_PM_GPIO_004      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_003 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_RGMII1_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_TP_IN_03         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_PM_GPIO_003      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_002 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_RGMII1_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PWM_2            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_TP_IN_02         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_PM_GPIO_002      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_001 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MII_TXEN_RGMII1_TXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_TP_IN_01         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_PM_GPIO_001      3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_016 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_EBI_ADDR_04      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_TP_IN_12         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_016_PM_GPIO_016      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_015 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_EBI_ADDR_08      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_015_ALT_TP_OUT_11    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_014 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_EBI_ADDR_09      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_014_ALT_TP_OUT_10    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_013 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_RGMII1_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_UART_TXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_ALT_TP_OUT_09    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_012 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_RGMII1_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_UART_RXD_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_EXT_IRQB_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_TP_IN_09         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_PM_GPIO_012      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_011 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_RGMII1_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_UART_RTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_ALT_TP_IN_31     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_010 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_RGMII1_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_UART_CTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_EXT_IRQB_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_TP_IN_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_PM_GPIO_010      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_009 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_RGMII1_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_UART_TXD_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_TP_OUT_00        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_PM_GPIO_009      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_024 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_GPIO_024         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_SDIO1_DAT1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_LED_LD_13        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_HCPU_TRACE_RXD   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_MTSIF_TX1_DATA5  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_TP_IN_19         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_024_PM_GPIO_024      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_023 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_GPIO_023         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SDIO1_DAT0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_LED_LD_12        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_HCPU_TRACE_DATA3 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MTSIF_TX1_DATA4  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_TP_IN_18         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_PM_GPIO_023      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_022 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_GPIO_022         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SDIO1_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_LED_LD_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_HCPU_TRACE_DATA2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MTSIF_TX1_DATA3  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_PM_GPIO_022      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_021 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_GPIO_021         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SDIO1_PWR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_LED_LD_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_HCPU_TRACE_DATA1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MTSIF_TX1_DATA2  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_TP_IN_17         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_PM_GPIO_021      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_020 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SDIO1_WPROT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_LED_LD_9         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_HCPU_TRACE_DATA0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MTSIF_TX1_DATA1  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_TP_IN_16         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_PM_GPIO_020      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_019 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SDIO1_CMD        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_LED_LD_8         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_HCPU_TRACE_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MTSIF_TX1_DATA0  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_TP_IN_15         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_PM_GPIO_019      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_018 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_EBI_ADDR_05      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_TP_IN_14         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_PM_GPIO_018      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_017 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_EBI_ADDR_07      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_TP_IN_13         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_PM_GPIO_017      3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_032 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_GPIO_032         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_EBI_ADDR_14      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SPI_S_SS0B       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SW_SPI_S_SS0B    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_TP_IN_25         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_PM_GPIO_032      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_031 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_GPIO_031         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_TXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_UART_RTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_TP_OUT_07        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_PM_GPIO_031      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_030 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_GPIO_030         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_RXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_UART_CTS_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_TP_IN_23         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_PM_GPIO_030      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_029 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_GPIO_029         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_EXT_IRQB_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_TP_IN_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_PM_GPIO_029      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_028 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_GPIO_028         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SDIO1_LED        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_EXT_IRQB_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MTSIF_TX1_CLK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_TP_IN_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_PM_GPIO_028      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_027 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_GPIO_027         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SDIO1_PRES       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MTSIF_TX1_SYNC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_PM_GPIO_027      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_026 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_GPIO_026         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SDIO1_DAT3       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_LED_LD_15        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MTSIF_TX1_DATA7  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_ALT_TP_IN_12     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_PM_GPIO_026      5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_025 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_GPIO_025         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SDIO1_DAT2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_LED_LD_14        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MTSIF_TX1_DATA6  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_TP_IN_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_PM_GPIO_025      5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_040 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_GPIO_040         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_UART_TXD_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_TP_OUT_27        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_PM_GPIO_040      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_039 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_GPIO_039         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_UART_RXD_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_TP_IN_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_PM_GPIO_039      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_038 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_GPIO_038         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_DEMOD_MTSIF_ATS_RST 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_TP_IN_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_PM_GPIO_038      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_037 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_GPIO_037         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_EBI_ADDR_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_ALT_TP_OUT_14    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_036 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_GPIO_036         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_EBI_ADDR_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_ALT_TP_OUT_13    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_035 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_GPIO_035         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SW_SPI_S_MOSI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_PM_GPIO_035      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_034 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_GPIO_034         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_EBI_ADDR_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SW_SPI_S_SCK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_TP_IN_26         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_PM_GPIO_034      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_033 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_GPIO_033         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_EBI_ADDR_15      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SPI_S_MISO       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_SW_SPI_S_MISO    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_033_ALT_TP_OUT_12    4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_048 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_GPIO_048         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_EBI_ADDR_13      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_PM_GPIO_048      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_047 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_GPIO_047         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_EBI_ADDR_15      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_PM_GPIO_047      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_046 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_GPIO_046         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_EBI_ADDR_14      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_TP_IN_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_PM_GPIO_046      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_045 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_GPIO_045         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_DEMOD_MTSIF_ATS_INC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_PM_GPIO_045      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_044 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_GPIO_044         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_UART_TXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_PM_GPIO_044      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_043 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_GPIO_043         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_UART_RXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_TP_IN_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_043_PM_GPIO_043      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_042 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_GPIO_042         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_UART_TXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_042_PM_GPIO_042      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_041 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_GPIO_041         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_UART_RXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_TP_IN_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_041_PM_GPIO_041      3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_056 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_GPIO_056         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_EBI_ADDR_23      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_TP_OUT_19        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_PM_GPIO_056      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_055 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_GPIO_055         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_MTSIF_TX0_DATA3  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_EBI_ADDR_22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_TP_OUT_18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_PM_GPIO_055      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_054 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_GPIO_054         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_MTSIF_TX0_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_EBI_ADDR_21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_TP_OUT_17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_PM_GPIO_054      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_053 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_GPIO_053         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_MTSIF_TX0_SYNC   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_EBI_ADDR_20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_TP_OUT_16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_053_PM_GPIO_053      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_052 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_GPIO_052         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_MTSIF_TX0_DATA0  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_EBI_ADDR_19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_052_PM_GPIO_052      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_051 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_GPIO_051         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_MTSIF_TX0_DATA6  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_EBI_ADDR_18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_051_PM_GPIO_051      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_050 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_GPIO_050         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_MTSIF_TX0_DATA1  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_EBI_ADDR_17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_050_ALT_TP_OUT_15    3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_049 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_GPIO_049         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_MTSIF_TX0_DATA7  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_EBI_ADDR_16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_049_PM_GPIO_049      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_064 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_GPIO_064         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_SDIO0_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PWM_2            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_ALT_TP_IN_11     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_064_PM_GPIO_064      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_063 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_GPIO_063         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_SDIO0_PWR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_063_PM_GPIO_063      2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_062 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_GPIO_062         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_SDIO0_WPROT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_TP_OUT_25        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_062_PM_GPIO_062      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_061 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_GPIO_061         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_SDIO0_CMD        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_TP_OUT_24        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_061_PM_GPIO_061      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_060 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_GPIO_060         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_EBI_ADDR_06      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_UART_CTS_2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_TP_OUT_23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_060_PM_GPIO_060      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_059 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_GPIO_059         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_MTSIF_TX0_DATA4  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_EBI_ADDR_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_TP_OUT_22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_059_PM_GPIO_059      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_058 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_GPIO_058         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_MTSIF_TX0_DATA2  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_EBI_ADDR_25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_TP_OUT_21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_058_PM_GPIO_058      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_057 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_GPIO_057         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_MTSIF_TX0_DATA5  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_EBI_ADDR_24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_TP_OUT_20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_057_PM_GPIO_057      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_072 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_GPIO_072        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_SPI_M_MOSI      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_072_PM_GPIO_072     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_071 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_SPI_M_SCK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_071_PM_GPIO_071     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_070 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_SDIO0_LED       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_EXT_IRQB_4      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_070_PM_GPIO_070     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_069 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_SDIO0_PRES      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_CTS_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_EXT_IRQB_3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_UART_TXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_TP_OUT_30       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_069_PM_GPIO_069     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_068 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_SDIO0_DAT3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RTS_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_EXT_IRQB_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_UART_RXD_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_TP_OUT_29       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_068_PM_GPIO_068     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_067 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_SDIO0_DAT2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_UART_TXD_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_EXT_IRQB_1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_067_PM_GPIO_067     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_066 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_SDIO0_DAT1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_UART_RXD_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_EXT_IRQB_0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_TP_IN_31        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_066_PM_GPIO_066     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_065 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_SDIO0_DAT0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_TP_OUT_26       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_065_PM_GPIO_065     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_080 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_GPIO_080        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_MII_IRQ         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_ALT_TP_IN_19    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_080_PM_GPIO_080     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_079 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_GPIO_079        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_TEST_THP        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PWM_1           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_UART_CTS_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_ALT_TP_IN_18    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_079_PM_GPIO_079     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_078 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_GPIO_078        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PWM_2           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_ALT_TP_IN_17    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_078_PM_GPIO_078     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_077 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_GPIO_077        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_ALT_TP_IN_16    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_077_PM_GPIO_077     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_076 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_GPIO_076        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_SPI_M_SS2B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_ALT_TP_IN_15    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_076_PM_GPIO_076     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_075 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_GPIO_075        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_SPI_M_SS1B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_ALT_TP_IN_14    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_075_PM_GPIO_075     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_074 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_GPIO_074        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_SPI_M_SS0B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_ALT_TP_IN_13    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_074_PM_GPIO_074     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_073 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_GPIO_073        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_SPI_M_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_073_PM_GPIO_073     2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_088 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_GPIO_088        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_EBI_ADDR_10     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PWM_1           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_MODEHV_D        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_ALT_TP_IN_26    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_088_PM_GPIO_088     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_087 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_GPIO_087        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_EBI_ADDR_03     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PWM_0           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_MODEHV_A        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_ALT_TP_IN_25    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_087_PM_GPIO_087     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_086 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_GPIO_086        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_EXT_IRQB_5      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_SDIO1_VOLT      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_RGMII1_RX_OK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_ALT_TP_IN_24    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_086_PM_GPIO_086     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_085 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_GPIO_085        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_SDIO0_VOLT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_RGMII1_START_STOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_ALT_TP_IN_23    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_085_PM_GPIO_085     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_084 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_GPIO_084        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_084_MII_TX_ERR      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_083 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_GPIO_083        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_MII_RX_ERR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_UART_RTS_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_ALT_TP_IN_22    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_083_PM_GPIO_083     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_082 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_GPIO_082        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_UART_RXD_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_ALT_TP_IN_21    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_082_PM_GPIO_082     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_081 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_GPIO_081        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_UART_TXD_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PWM_3           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_ALT_TP_IN_20    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_081_PM_GPIO_081     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_096 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_GPIO_096        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_SPI_M_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_ZIG_SECI_2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_096_PM_GPIO_096     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_095 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_GPIO_095        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_095_SPI_M_MOSI      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_094 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_GPIO_094        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_SPI_M_SCK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_ZIG_SECI_0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_094_PM_GPIO_094     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_093 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_GPIO_093        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_SW_LED_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_TP_IN_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_093_PM_GPIO_093     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_092 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_GPIO_092        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_SW_LED_DATA     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_ALT_TP_IN_30    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_092_PM_GPIO_092     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_091 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_GPIO_091        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_EBI_RWB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_ALT_TP_IN_29    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_091_PM_GPIO_091     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_090 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_GPIO_090        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_EBI_CS3B        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PWM_3           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_ALT_TP_IN_28    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_090_PM_GPIO_090     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_089 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_GPIO_089        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_EBI_ADDR_11     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_MODEHV_F        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_ALT_TP_IN_27    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_089_PM_GPIO_089     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_01 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_BSC_M4_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MOCA_BSC_SDA    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_00 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_BSC_M4_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MOCA_BSC_SCL    2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_102 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_SDIO1_CLK_IN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_102_PM_GPIO_102     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_101 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_SDIO0_CLK_IN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_101_PM_GPIO_101     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_100 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PWM_0           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_100_PM_GPIO_100     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_099 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_GPIO_099        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_SPI_M_SS2B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PWM_2           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_099_PM_GPIO_099     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_098 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_GPIO_098        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_SPI_M_SS1B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_ZIG_SECI_1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_098_PM_GPIO_098     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_097 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_GPIO_097        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_SPI_M_SS0B      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_097_ZIG_SECO        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: byp_hs_stb_clk [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_BYP_HS_STB_CLK 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_byp_hs_stb_clk_CLK_OUT0  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M3_SCL      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_tsb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_rdb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_we1b_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_we0b_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs2b_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs1b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_cs0b_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_rstb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie0_clkreqb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie0_rstb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie0_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_clk_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_clk_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc1_cmd_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc1_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_wpb_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_MASK  0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_holdb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK  0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_dqs_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_dqs_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_waitb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_waitb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_wpb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_nand_rbb_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_dsb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_007_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_006_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_005_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_004_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_003_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_002_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_001_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_000_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [13:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x00003fc0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie2_clkreqb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie2_rstb_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie2_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: pcie1_clkreqb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_pcie1_clkreqb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_022_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_021_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_020_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_019_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_018_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_017_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_016_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [15:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x0000fc00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_012_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_012_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK        0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_010_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_009_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_008_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_008_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_035_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_034_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_032_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_031_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_030_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_029_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_028_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_028_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_027_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_026_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_025_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_025_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_024_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_023_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_023_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_052_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_051_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_049_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_048_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_047_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_046_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_045_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_044_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_043_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_042_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_041_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_040_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_039_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_038_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_038_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_067_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_066_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_065_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_064_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_063_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_062_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_061_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_060_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_059_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_058_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_057_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_056_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_055_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_054_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_053_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_053_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_082_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_081_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_081_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_080_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_079_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_078_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_078_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_077_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_077_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_076_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_076_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_075_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_075_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_074_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_074_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_073_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_073_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_072_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_072_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_071_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_070_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_069_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_068_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_068_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_096_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_096_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_094_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_093_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_092_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved2 [17:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved2_MASK        0x0003c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved2_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_089_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_088_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_088_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_087_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_087_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_086_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_085_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_085_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved3 [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved3_MASK        0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved3_SHIFT       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_083_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_083_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved1 [25:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_MASK        0x03fffc00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_102_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_101_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_100_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_099_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_099_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_098_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_098_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffff8000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       15
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_500_514p28_clk [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_500_514p28_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_hs_stb_clk [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_hs_stb_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_073 [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_073_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_072 [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_072_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_071 [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_071_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_063 [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_063_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_039 [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_035 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_035_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_027 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_027_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_wpb [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_wpb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sf_holdb [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sf_holdb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_dqs [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_dqs_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_waitb [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_waitb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_dsb [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_dsb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_tsb [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_tsb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffff000
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      12
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: local_sw_master_reset_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_local_sw_master_reset_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          2
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: local_master_reset [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_local_master_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0x80000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            31
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [30:30] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 30
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [29:29] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 29
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [28:28] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 28
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [27:27] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 27
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [26:26] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT     26
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_cpu_ejtag_reset [25:25] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_MASK    0x02000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_cpu_ejtag_reset_SHIFT   25
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_cpu_ejtag_reset [24:24] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_MASK    0x01000000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_cpu_ejtag_reset_SHIFT   24
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: host_cpu_ejtag_reset [23:23] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_MASK  0x00800000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_cpu_ejtag_reset_SHIFT 23
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: powerloss_reset [22:22] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_powerloss_reset_SHIFT      22
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overvoltage_1_reset [21:21] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overvoltage_1_reset_SHIFT 21
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_1_reset [20:20] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_1_reset_SHIFT 20
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_undervoltage_0_reset [19:19] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_undervoltage_0_reset_SHIFT 19
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [18:18] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT  18
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [17:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK  0x00020000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK  0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_overtemp_reset [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_overtemp_reset_SHIFT    15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_software_master_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_software_master_reset_SHIFT 12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: local_software_master_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_local_software_master_reset_SHIFT 11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_2_hot_boot_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_2_hot_boot_reset_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_2_hot_boot_reset_SHIFT 9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: rg_watchdog_timer_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_rg_watchdog_timer_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cm_watchdog_timer_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cm_watchdog_timer_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: host_watchdog_timer_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_host_watchdog_timer_reset_SHIFT 4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_SHIFT  31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_MASK   0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_SHIFT  29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_MASK       0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_SHIFT      26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb_all_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK          0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT         22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_MASK   0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_SHIFT  15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_SHIFT  14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_MASK   0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_SHIFT  10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_MASK    0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_SHIFT   9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rg_cpu_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb_all_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK        0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT       22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rg_cpu_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_MASK    0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_SHIFT   26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb_all_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT      22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_16_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_15_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_14_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_10_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_9_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_8_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rg_cpu_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK  0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb_all_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_start_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rg_cpu_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_u2g_sw_init_MASK           0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_u2g_sw_init_SHIFT          11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_u2g_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_MASK   0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_SHIFT  10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK         0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT        7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_u2g_sw_init_MASK         0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_u2g_sw_init_SHIFT        11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_u2g_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT  9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK       0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK       0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT      7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffc000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         14
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_u2g_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_u2g_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_u2g_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_4_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffc000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_u2g_sw_init_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_u2g_sw_init_SHIFT  11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_u2g_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_u2g_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffc000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_u2g_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_u2g_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gisb_bridge_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_start_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rg_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_u2g_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_u2g_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_u2g_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rg_cpu_start_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_start_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rg_cpu_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rg_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffc000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 14
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: u2g_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_u2g_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_u2g_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_u2g_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gisb_bridge_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gisb_bridge_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RG_SW_INIT_0_ENABLE - Router software init 0 mask
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_MASK    0x10000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_SHIFT   28
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: gphy_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_MASK    0x08000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_SHIFT   27
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb_all_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb_all_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_MASK    0x02000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_MASK    0x01000000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_SHIFT   24
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: switch_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_MASK  0x00800000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_switch_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: pcie2_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie2_sw_init_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie2_sw_init_SHIFT  7
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie2_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: pcie1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_MASK   0x00000020
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_SHIFT  5
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_pcie0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_cpu_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_0_ENABLE :: rg_sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_0_ENABLE_rg_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RG_SW_INIT_1_ENABLE - Router software init 0 mask
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_reserved0_MASK       0xffffc000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_reserved0_SHIFT      14
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: spare1_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: spare0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RG_SW_INIT_1_ENABLE :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RG_SW_INIT_1_ENABLE_not_used_sw_init_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_US_TOP  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_CAB_TOP 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_LEAP    19
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1   36
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE    44
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_WOD_RCVRA 48
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_WOD_RCVRB 49
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CMD_AFECA 60
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CMD_AFECB 61
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffffe0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           5
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [04:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000001f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_HOST_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MEMC0_CPU 16
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_HOST_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MEMC0_CPU 4
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xff800000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               23
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xffffffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             5
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UART_ROUTER_SEL_0 - UART Router select 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK    0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK    0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU    3
+
+/***************************************************************************
+ *UART_ROUTER_SEL_1 - UART Router select 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK   0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU   3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK   0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU   3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU    3
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU    3
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x20404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x20404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xfffc0000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        18
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STB_POWER_CYCLE_CONTROL - Power Cycle Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_CONTROL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_reserved0_MASK   0xfffffffe
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_reserved0_SHIFT  1
+
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_CONTROL :: power_cycle_stb [00:00] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_CONTROL_power_cycle_stb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STB_POWER_CYCLE_DELAY - Power Cycle Delay
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_DELAY :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_reserved0_MASK     0xff000000
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_reserved0_SHIFT    24
+
+/* SUN_TOP_CTRL :: STB_POWER_CYCLE_DELAY :: prog_delay [23:00] */
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_MASK    0x00ffffff
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_STB_POWER_CYCLE_DELAY_prog_delay_DEFAULT 0x00001518
+
+/***************************************************************************
+ *GENERAL_CTRL_6 - General control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK            0xfffffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT           1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_7 - General control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_switch_acb.h b/include/linux/brcmstb/3390b0/bchp_switch_acb.h
new file mode 100644
index 000000000000..6391d86f3d4f
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_switch_acb.h
@@ -0,0 +1,4439 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:13 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_ACB_H__
+#define BCHP_SWITCH_ACB_H__
+
+/***************************************************************************
+ *SWITCH_ACB
+ ***************************************************************************/
+#define BCHP_SWITCH_ACB_ACB_CONTROL              0x04e40600 /* [RW] ACB Control Register */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION 0x04e40604 /* [RW] ACB XON Threshold Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION 0x04e40608 /* [RW] ACB Queue 0 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION 0x04e4060c /* [RW] ACB Queue 1 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION 0x04e40610 /* [RW] ACB Queue 2 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION 0x04e40614 /* [RW] ACB Queue 3 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION 0x04e40618 /* [RW] ACB Queue 4 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION 0x04e4061c /* [RW] ACB Queue 5 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION 0x04e40620 /* [RW] ACB Queue 6 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION 0x04e40624 /* [RW] ACB Queue 7 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION 0x04e40628 /* [RW] ACB Queue 8 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION 0x04e4062c /* [RW] ACB Queue 9 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION 0x04e40630 /* [RW] ACB Queue 10 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION 0x04e40634 /* [RW] ACB Queue 11 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION 0x04e40638 /* [RW] ACB Queue 12 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION 0x04e4063c /* [RW] ACB Queue 13 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION 0x04e40640 /* [RW] ACB Queue 14 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION 0x04e40644 /* [RW] ACB Queue 15 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION 0x04e40648 /* [RW] ACB Queue 16 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION 0x04e4064c /* [RW] ACB Queue 17 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION 0x04e40650 /* [RW] ACB Queue 18 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION 0x04e40654 /* [RW] ACB Queue 19 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION 0x04e40658 /* [RW] ACB Queue 20 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION 0x04e4065c /* [RW] ACB Queue 21 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION 0x04e40660 /* [RW] ACB Queue 22 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION 0x04e40664 /* [RW] ACB Queue 23 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION 0x04e40668 /* [RW] ACB Queue 24 Configuration Register6 */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION 0x04e4066c /* [RW] ACB Queue 25 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION 0x04e40670 /* [RW] ACB Queue 26 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION 0x04e40674 /* [RW] ACB Queue 27 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION 0x04e40678 /* [RW] ACB Queue 28 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION 0x04e4067c /* [RW] ACB Queue 29 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION 0x04e40680 /* [RW] ACB Queue 30 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION 0x04e40684 /* [RW] ACB Queue 31 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION 0x04e40688 /* [RW] ACB Queue 32 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION 0x04e4068c /* [RW] ACB Queue 33 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION 0x04e40690 /* [RW] ACB Queue 34 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION 0x04e40694 /* [RW] ACB Queue 35 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION 0x04e40698 /* [RW] ACB Queue 36 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION 0x04e4069c /* [RW] ACB Queue 37 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION 0x04e406a0 /* [RW] ACB Queue 38 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION 0x04e406a4 /* [RW] ACB Queue 39 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION 0x04e406a8 /* [RW] ACB Queue 40 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION 0x04e406ac /* [RW] ACB Queue 41 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION 0x04e406b0 /* [RW] ACB Queue 42 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION 0x04e406b4 /* [RW] ACB Queue 43 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION 0x04e406b8 /* [RW] ACB Queue 44 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION 0x04e406bc /* [RW] ACB Queue 45 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION 0x04e406c0 /* [RW] ACB Queue 46 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION 0x04e406c4 /* [RW] ACB Queue 47 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION 0x04e406c8 /* [RW] ACB Queue 48 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION 0x04e406cc /* [RW] ACB Queue 49 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION 0x04e406d0 /* [RW] ACB Queue 50 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION 0x04e406d4 /* [RW] ACB Queue 51 Configuration Register6 */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION 0x04e406d8 /* [RW] ACB Queue 52 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION 0x04e406dc /* [RW] ACB Queue 53 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION 0x04e406e0 /* [RW] ACB Queue 54 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION 0x04e406e4 /* [RW] ACB Queue 55 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION 0x04e406e8 /* [RW] ACB Queue 56 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION 0x04e406ec /* [RW] ACB Queue 57 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION 0x04e406f0 /* [RW] ACB Queue 58 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION 0x04e406f4 /* [RW] ACB Queue 59 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION 0x04e406f8 /* [RW] ACB Queue 60 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION 0x04e406fc /* [RW] ACB Queue 61 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION 0x04e40700 /* [RW] ACB Queue 62 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION 0x04e40704 /* [RW] ACB Queue 63 Configuration Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT 0x04e40708 /* [RW] ACB Queue 0 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT 0x04e4070c /* [RW] ACB Queue 1 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT 0x04e40710 /* [RW] ACB Queue 2 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT 0x04e40714 /* [RW] ACB Queue 3 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT 0x04e40718 /* [RW] ACB Queue 4 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT 0x04e4071c /* [RW] ACB Queue 5 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT 0x04e40720 /* [RW] ACB Queue 6 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT 0x04e40724 /* [RW] ACB Queue 7 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT 0x04e40728 /* [RW] ACB Queue 8 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT 0x04e4072c /* [RW] ACB Queue 9 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT 0x04e40730 /* [RW] ACB Queue 10 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT 0x04e40734 /* [RW] ACB Queue 11 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT 0x04e40738 /* [RW] ACB Queue 12 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT 0x04e4073c /* [RW] ACB Queue 13 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT 0x04e40740 /* [RW] ACB Queue 14 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT 0x04e40744 /* [RW] ACB Queue 15 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT 0x04e40748 /* [RW] ACB Queue 16 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT 0x04e4074c /* [RW] ACB Queue 17 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT 0x04e40750 /* [RW] ACB Queue 18 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT 0x04e40754 /* [RW] ACB Queue 19 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT 0x04e40758 /* [RW] ACB Queue 20 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT 0x04e4075c /* [RW] ACB Queue 21 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT 0x04e40760 /* [RW] ACB Queue 22 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT 0x04e40764 /* [RW] ACB Queue 23 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT 0x04e40768 /* [RW] ACB Queue 24 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT 0x04e4076c /* [RW] ACB Queue 25 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT 0x04e40770 /* [RW] ACB Queue 26 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT 0x04e40774 /* [RW] ACB Queue 27 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT 0x04e40778 /* [RW] ACB Queue 28 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT 0x04e4077c /* [RW] ACB Queue 29 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT 0x04e40780 /* [RW] ACB Queue 30 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT 0x04e40784 /* [RW] ACB Queue 31 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT 0x04e40788 /* [RW] ACB Queue 32 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT 0x04e4078c /* [RW] ACB Queue 33 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT 0x04e40790 /* [RW] ACB Queue 34 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT 0x04e40794 /* [RW] ACB Queue 35 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT 0x04e40798 /* [RW] ACB Queue 36 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT 0x04e4079c /* [RW] ACB Queue 37 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT 0x04e407a0 /* [RW] ACB Queue 38 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT 0x04e407a4 /* [RW] ACB Queue 39 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT 0x04e407a8 /* [RW] ACB Queue 40 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT 0x04e407ac /* [RW] ACB Queue 41 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT 0x04e407b0 /* [RW] ACB Queue 42 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT 0x04e407b4 /* [RW] ACB Queue 43 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT 0x04e407b8 /* [RW] ACB Queue 44 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT 0x04e407bc /* [RW] ACB Queue 45 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT 0x04e407c0 /* [RW] ACB Queue 46 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT 0x04e407c4 /* [RW] ACB Queue 47 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT 0x04e407c8 /* [RW] ACB Queue 48 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT 0x04e407cc /* [RW] ACB Queue 49 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT 0x04e407d0 /* [RW] ACB Queue 50 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT 0x04e407d4 /* [RW] ACB Queue 51 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT 0x04e407d8 /* [RW] ACB Queue 52 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT 0x04e407dc /* [RW] ACB Queue 53 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT 0x04e407e0 /* [RW] ACB Queue 54 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT 0x04e407e4 /* [RW] ACB Queue 55 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT 0x04e407e8 /* [RW] ACB Queue 56 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT 0x04e407ec /* [RW] ACB Queue 57 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT 0x04e407f0 /* [RW] ACB Queue 58 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT 0x04e407f4 /* [RW] ACB Queue 59 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT 0x04e407f8 /* [RW] ACB Queue 60 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT 0x04e407fc /* [RW] ACB Queue 61 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT 0x04e40800 /* [RW] ACB Queue 62 Packets In Flight Register */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT 0x04e40804 /* [RW] ACB Queue 63 Packets In Flight Register */
+
+/***************************************************************************
+ *ACB_CONTROL - ACB Control Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_CONTROL :: reserved0 [31:13] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_MASK                 0xffffe000
+#define BCHP_SWITCH_ACB_ACB_CONTROL_reserved0_SHIFT                13
+
+/* SWITCH_ACB :: ACB_CONTROL :: eop_delay [12:05] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_MASK                 0x00001fe0
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_SHIFT                5
+#define BCHP_SWITCH_ACB_ACB_CONTROL_eop_delay_DEFAULT              0x00000032
+
+/* SWITCH_ACB :: ACB_CONTROL :: flush [04:02] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_MASK                     0x0000001c
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_SHIFT                    2
+#define BCHP_SWITCH_ACB_ACB_CONTROL_flush_DEFAULT                  0x00000000
+
+/* SWITCH_ACB :: ACB_CONTROL :: acb_algorithm [01:01] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_MASK             0x00000002
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_SHIFT            1
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_algorithm_DEFAULT          0x00000000
+
+/* SWITCH_ACB :: ACB_CONTROL :: acb_en [00:00] */
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_MASK                    0x00000001
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_SHIFT                   0
+#define BCHP_SWITCH_ACB_ACB_CONTROL_acb_en_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ACB_XON_THRESHOLD_CONFIGURATION - ACB XON Threshold Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: reserved0 [31:22] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_MASK 0xffc00000
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_reserved0_SHIFT 22
+
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: total_xon_hyst [21:11] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_MASK 0x003ff800
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_SHIFT 11
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_total_xon_hyst_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_XON_THRESHOLD_CONFIGURATION :: queue_xon_hyst [10:00] */
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_XON_THRESHOLD_CONFIGURATION_queue_xon_hyst_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_0_CONFIGURATION - ACB Queue 0 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_0_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: input_is_acb_queue_0_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_input_is_acb_queue_0_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_0_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_1_CONFIGURATION - ACB Queue 1 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_1_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: input_is_acb_queue_1_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_input_is_acb_queue_1_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_1_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_2_CONFIGURATION - ACB Queue 2 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_2_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: input_is_acb_queue_2_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_input_is_acb_queue_2_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_2_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_3_CONFIGURATION - ACB Queue 3 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_3_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: input_is_acb_queue_3_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_input_is_acb_queue_3_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_3_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_4_CONFIGURATION - ACB Queue 4 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_4_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: input_is_acb_queue_4_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_input_is_acb_queue_4_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_4_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_5_CONFIGURATION - ACB Queue 5 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_5_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: input_is_acb_queue_5_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_input_is_acb_queue_5_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_5_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_6_CONFIGURATION - ACB Queue 6 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_6_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: input_is_acb_queue_6_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_input_is_acb_queue_6_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_6_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_7_CONFIGURATION - ACB Queue 7 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_7_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: input_is_acb_queue_7_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_input_is_acb_queue_7_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_7_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_8_CONFIGURATION - ACB Queue 8 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_8_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: input_is_acb_queue_8_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_input_is_acb_queue_8_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_8_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_9_CONFIGURATION - ACB Queue 9 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_9_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: input_is_acb_queue_9_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_input_is_acb_queue_9_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_MASK      0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_SHIFT     11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xon_en_DEFAULT   0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_9_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_10_CONFIGURATION - ACB Queue 10 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_10_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: input_is_acb_queue_10_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_input_is_acb_queue_10_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_10_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_11_CONFIGURATION - ACB Queue 11 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_11_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: input_is_acb_queue_11_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_input_is_acb_queue_11_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_11_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_12_CONFIGURATION - ACB Queue 12 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_12_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: input_is_acb_queue_12_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_input_is_acb_queue_12_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_12_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_13_CONFIGURATION - ACB Queue 13 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_13_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: input_is_acb_queue_13_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_input_is_acb_queue_13_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_13_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_14_CONFIGURATION - ACB Queue 14 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_14_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: input_is_acb_queue_14_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_input_is_acb_queue_14_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_14_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_15_CONFIGURATION - ACB Queue 15 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_15_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: input_is_acb_queue_15_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_input_is_acb_queue_15_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_15_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_16_CONFIGURATION - ACB Queue 16 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_16_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: input_is_acb_queue_16_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_input_is_acb_queue_16_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_16_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_17_CONFIGURATION - ACB Queue 17 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_17_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: input_is_acb_queue_17_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_input_is_acb_queue_17_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_17_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_18_CONFIGURATION - ACB Queue 18 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_18_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: input_is_acb_queue_18_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_input_is_acb_queue_18_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_18_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_19_CONFIGURATION - ACB Queue 19 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_19_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: input_is_acb_queue_19_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_input_is_acb_queue_19_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_19_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_20_CONFIGURATION - ACB Queue 20 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_20_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: input_is_acb_queue_20_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_input_is_acb_queue_20_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_20_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_21_CONFIGURATION - ACB Queue 21 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_21_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: input_is_acb_queue_21_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_input_is_acb_queue_21_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_21_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_22_CONFIGURATION - ACB Queue 22 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_22_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: input_is_acb_queue_22_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_input_is_acb_queue_22_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_22_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_23_CONFIGURATION - ACB Queue 23 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_23_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: input_is_acb_queue_23_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_input_is_acb_queue_23_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_23_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_24_CONFIGURATION - ACB Queue 24 Configuration Register6
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_24_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: input_is_acb_queue_24_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_input_is_acb_queue_24_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_24_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_25_CONFIGURATION - ACB Queue 25 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_25_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: input_is_acb_queue_25_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_input_is_acb_queue_25_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_25_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_26_CONFIGURATION - ACB Queue 26 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_26_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: input_is_acb_queue_26_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_input_is_acb_queue_26_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_26_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_27_CONFIGURATION - ACB Queue 27 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_27_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: input_is_acb_queue_27_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_input_is_acb_queue_27_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_27_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_28_CONFIGURATION - ACB Queue 28 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_28_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: input_is_acb_queue_28_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_input_is_acb_queue_28_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_28_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_29_CONFIGURATION - ACB Queue 29 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_29_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: input_is_acb_queue_29_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_input_is_acb_queue_29_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_29_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_30_CONFIGURATION - ACB Queue 30 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_30_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: input_is_acb_queue_30_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_input_is_acb_queue_30_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_30_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_31_CONFIGURATION - ACB Queue 31 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_31_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: input_is_acb_queue_31_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_input_is_acb_queue_31_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_31_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_32_CONFIGURATION - ACB Queue 32 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_32_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: input_is_acb_queue_32_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_input_is_acb_queue_32_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_32_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_33_CONFIGURATION - ACB Queue 33 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_33_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: input_is_acb_queue_33_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_input_is_acb_queue_33_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_33_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_34_CONFIGURATION - ACB Queue 34 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_34_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: input_is_acb_queue_34_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_input_is_acb_queue_34_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_34_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_35_CONFIGURATION - ACB Queue 35 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_35_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: input_is_acb_queue_35_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_input_is_acb_queue_35_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_35_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_36_CONFIGURATION - ACB Queue 36 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_36_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: input_is_acb_queue_36_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_input_is_acb_queue_36_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_36_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_37_CONFIGURATION - ACB Queue 37 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_37_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: input_is_acb_queue_37_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_input_is_acb_queue_37_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_37_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_38_CONFIGURATION - ACB Queue 38 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_38_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: input_is_acb_queue_38_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_input_is_acb_queue_38_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_38_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_39_CONFIGURATION - ACB Queue 39 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_39_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: input_is_acb_queue_39_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_input_is_acb_queue_39_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_39_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_40_CONFIGURATION - ACB Queue 40 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_40_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: input_is_acb_queue_40_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_input_is_acb_queue_40_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_40_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_41_CONFIGURATION - ACB Queue 41 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_41_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: input_is_acb_queue_41_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_input_is_acb_queue_41_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_41_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_42_CONFIGURATION - ACB Queue 42 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_42_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: input_is_acb_queue_42_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_input_is_acb_queue_42_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_42_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_43_CONFIGURATION - ACB Queue 43 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_43_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: input_is_acb_queue_43_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_input_is_acb_queue_43_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_43_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_44_CONFIGURATION - ACB Queue 44 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_44_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: input_is_acb_queue_44_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_input_is_acb_queue_44_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_44_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_45_CONFIGURATION - ACB Queue 45 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_45_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: input_is_acb_queue_45_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_input_is_acb_queue_45_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_45_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_46_CONFIGURATION - ACB Queue 46 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_46_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: input_is_acb_queue_46_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_input_is_acb_queue_46_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_46_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_47_CONFIGURATION - ACB Queue 47 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_47_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: input_is_acb_queue_47_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_input_is_acb_queue_47_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_47_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_48_CONFIGURATION - ACB Queue 48 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_48_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: input_is_acb_queue_48_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_input_is_acb_queue_48_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_48_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_49_CONFIGURATION - ACB Queue 49 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_49_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: input_is_acb_queue_49_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_input_is_acb_queue_49_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_49_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_50_CONFIGURATION - ACB Queue 50 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_50_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: input_is_acb_queue_50_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_input_is_acb_queue_50_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_50_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_51_CONFIGURATION - ACB Queue 51 Configuration Register6
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_51_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: input_is_acb_queue_51_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_input_is_acb_queue_51_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_51_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_52_CONFIGURATION - ACB Queue 52 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_52_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: input_is_acb_queue_52_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_input_is_acb_queue_52_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_52_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_53_CONFIGURATION - ACB Queue 53 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_53_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: input_is_acb_queue_53_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_input_is_acb_queue_53_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_53_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_54_CONFIGURATION - ACB Queue 54 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_54_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: input_is_acb_queue_54_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_input_is_acb_queue_54_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_54_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_55_CONFIGURATION - ACB Queue 55 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_55_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: input_is_acb_queue_55_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_input_is_acb_queue_55_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_55_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_56_CONFIGURATION - ACB Queue 56 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_56_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: input_is_acb_queue_56_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_input_is_acb_queue_56_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_56_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_57_CONFIGURATION - ACB Queue 57 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_57_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: input_is_acb_queue_57_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_input_is_acb_queue_57_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_57_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_58_CONFIGURATION - ACB Queue 58 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_58_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: input_is_acb_queue_58_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_input_is_acb_queue_58_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_58_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_59_CONFIGURATION - ACB Queue 59 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_59_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: input_is_acb_queue_59_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_input_is_acb_queue_59_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_59_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_60_CONFIGURATION - ACB Queue 60 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_60_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: input_is_acb_queue_60_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_input_is_acb_queue_60_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_60_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_61_CONFIGURATION - ACB Queue 61 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_61_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: input_is_acb_queue_61_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_input_is_acb_queue_61_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_61_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_62_CONFIGURATION - ACB Queue 62 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_62_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: input_is_acb_queue_62_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_input_is_acb_queue_62_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_62_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_63_CONFIGURATION - ACB Queue 63 Configuration Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: pessimistic_mode_en [31:31] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_MASK 0x80000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_SHIFT 31
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_DEFAULT 0x00000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_GISB 1
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_pessimistic_mode_en_PORT 0
+
+/* union - case input_is_gisb [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_gisb :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_acb_queue_63_configuration [30:25] */
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: input_is_acb_queue_63_configuration :: pktlen [30:25] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_MASK 0x7e000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_SHIFT 25
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_input_is_acb_queue_63_configuration_pktlen_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xon_en [24:24] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_MASK 0x01000000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_SHIFT 24
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xon_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_en [23:23] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_MASK 0x00800000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_SHIFT 23
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_en_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: total_xoff_threshold [22:12] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_MASK 0x007ff000
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_SHIFT 12
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_total_xoff_threshold_DEFAULT 0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xon_en [11:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_MASK     0x00000800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_SHIFT    11
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xon_en_DEFAULT  0x00000000
+
+/* SWITCH_ACB :: ACB_QUEUE_63_CONFIGURATION :: xoff_threshold [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_CONFIGURATION_xoff_threshold_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_0_PACKETS_IN_FLIGHT - ACB Queue 0 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_0_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: input_is_acb_queue_0_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_acb_queue_0_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_0_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_0_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_1_PACKETS_IN_FLIGHT - ACB Queue 1 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_1_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: input_is_acb_queue_1_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_acb_queue_1_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_1_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_1_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_2_PACKETS_IN_FLIGHT - ACB Queue 2 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_2_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: input_is_acb_queue_2_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_acb_queue_2_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_2_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_2_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_3_PACKETS_IN_FLIGHT - ACB Queue 3 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_3_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: input_is_acb_queue_3_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_acb_queue_3_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_3_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_3_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_4_PACKETS_IN_FLIGHT - ACB Queue 4 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_4_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: input_is_acb_queue_4_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_acb_queue_4_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_4_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_4_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_5_PACKETS_IN_FLIGHT - ACB Queue 5 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_5_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: input_is_acb_queue_5_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_acb_queue_5_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_5_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_5_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_6_PACKETS_IN_FLIGHT - ACB Queue 6 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_6_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: input_is_acb_queue_6_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_acb_queue_6_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_6_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_6_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_7_PACKETS_IN_FLIGHT - ACB Queue 7 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_7_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: input_is_acb_queue_7_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_acb_queue_7_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_7_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_7_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_8_PACKETS_IN_FLIGHT - ACB Queue 8 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_8_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: input_is_acb_queue_8_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_acb_queue_8_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_8_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_8_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_9_PACKETS_IN_FLIGHT - ACB Queue 9 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_9_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: input_is_acb_queue_9_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_acb_queue_9_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_9_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_9_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_10_PACKETS_IN_FLIGHT - ACB Queue 10 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_10_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: input_is_acb_queue_10_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_acb_queue_10_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_10_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_10_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_11_PACKETS_IN_FLIGHT - ACB Queue 11 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_11_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: input_is_acb_queue_11_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_acb_queue_11_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_11_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_11_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_12_PACKETS_IN_FLIGHT - ACB Queue 12 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_13_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: input_is_acb_queue_13_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_12_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_12_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_13_PACKETS_IN_FLIGHT - ACB Queue 13 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_13_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: input_is_acb_queue_13_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_acb_queue_13_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_13_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_13_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_14_PACKETS_IN_FLIGHT - ACB Queue 14 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_14_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: input_is_acb_queue_14_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_acb_queue_14_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_14_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_14_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_15_PACKETS_IN_FLIGHT - ACB Queue 15 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_15_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: input_is_acb_queue_15_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_acb_queue_15_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_15_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_15_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_16_PACKETS_IN_FLIGHT - ACB Queue 16 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_16_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: input_is_acb_queue_16_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_acb_queue_16_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_16_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_16_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_17_PACKETS_IN_FLIGHT - ACB Queue 17 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_17_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: input_is_acb_queue_17_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_acb_queue_17_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_17_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_17_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_18_PACKETS_IN_FLIGHT - ACB Queue 18 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_18_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: input_is_acb_queue_18_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_acb_queue_18_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_18_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_18_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_19_PACKETS_IN_FLIGHT - ACB Queue 19 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_19_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: input_is_acb_queue_19_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_acb_queue_19_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_19_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_19_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_20_PACKETS_IN_FLIGHT - ACB Queue 20 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_20_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: input_is_acb_queue_20_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_acb_queue_20_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_20_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_20_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_21_PACKETS_IN_FLIGHT - ACB Queue 21 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_21_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: input_is_acb_queue_21_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_acb_queue_21_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_21_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_21_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_22_PACKETS_IN_FLIGHT - ACB Queue 22 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_22_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: input_is_acb_queue_22_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_acb_queue_22_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_22_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_22_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_23_PACKETS_IN_FLIGHT - ACB Queue 23 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_23_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: input_is_acb_queue_23_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_acb_queue_23_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_23_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_23_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_24_PACKETS_IN_FLIGHT - ACB Queue 24 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_24_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: input_is_acb_queue_24_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_acb_queue_24_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_24_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_24_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_25_PACKETS_IN_FLIGHT - ACB Queue 25 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_25_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: input_is_acb_queue_25_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_acb_queue_25_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_25_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_25_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_26_PACKETS_IN_FLIGHT - ACB Queue 26 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_26_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: input_is_acb_queue_26_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_acb_queue_26_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_26_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_26_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_27_PACKETS_IN_FLIGHT - ACB Queue 27 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_27_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: input_is_acb_queue_27_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_acb_queue_27_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_27_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_27_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_28_PACKETS_IN_FLIGHT - ACB Queue 28 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_28_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: input_is_acb_queue_28_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_acb_queue_28_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_28_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_28_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_29_PACKETS_IN_FLIGHT - ACB Queue 29 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_29_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: input_is_acb_queue_29_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_acb_queue_29_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_29_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_29_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_30_PACKETS_IN_FLIGHT - ACB Queue 30 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_30_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: input_is_acb_queue_30_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_acb_queue_30_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_30_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_30_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_31_PACKETS_IN_FLIGHT - ACB Queue 31 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_31_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: input_is_acb_queue_31_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_acb_queue_31_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_31_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_31_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_32_PACKETS_IN_FLIGHT - ACB Queue 32 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_32_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: input_is_acb_queue_32_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_acb_queue_32_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_32_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_32_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_33_PACKETS_IN_FLIGHT - ACB Queue 33 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_33_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: input_is_acb_queue_33_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_acb_queue_33_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_33_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_33_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_34_PACKETS_IN_FLIGHT - ACB Queue 34 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_34_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: input_is_acb_queue_34_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_acb_queue_34_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_34_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_34_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_35_PACKETS_IN_FLIGHT - ACB Queue 35 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_35_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: input_is_acb_queue_35_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_acb_queue_35_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_35_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_35_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_36_PACKETS_IN_FLIGHT - ACB Queue 36 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_36_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: input_is_acb_queue_36_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_acb_queue_36_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_36_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_36_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_37_PACKETS_IN_FLIGHT - ACB Queue 37 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_37_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: input_is_acb_queue_37_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_acb_queue_37_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_37_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_37_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_38_PACKETS_IN_FLIGHT - ACB Queue 38 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_38_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: input_is_acb_queue_38_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_acb_queue_38_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_38_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_38_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_39_PACKETS_IN_FLIGHT - ACB Queue 39 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_39_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: input_is_acb_queue_39_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_acb_queue_39_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_39_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_39_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_40_PACKETS_IN_FLIGHT - ACB Queue 40 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_40_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: input_is_acb_queue_40_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_acb_queue_40_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_40_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_40_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_41_PACKETS_IN_FLIGHT - ACB Queue 41 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_41_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: input_is_acb_queue_41_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_acb_queue_41_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_41_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_41_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_42_PACKETS_IN_FLIGHT - ACB Queue 42 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_42_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: input_is_acb_queue_42_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_acb_queue_42_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_42_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_42_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_43_PACKETS_IN_FLIGHT - ACB Queue 43 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_43_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: input_is_acb_queue_43_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_acb_queue_43_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_43_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_43_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_44_PACKETS_IN_FLIGHT - ACB Queue 44 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_44_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: input_is_acb_queue_44_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_acb_queue_44_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_44_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_44_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_45_PACKETS_IN_FLIGHT - ACB Queue 45 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_45_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: input_is_acb_queue_45_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_acb_queue_45_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_45_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_45_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_46_PACKETS_IN_FLIGHT - ACB Queue 46 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_46_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: input_is_acb_queue_46_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_acb_queue_46_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_46_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_46_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_47_PACKETS_IN_FLIGHT - ACB Queue 47 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_47_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: input_is_acb_queue_47_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_acb_queue_47_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_47_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_47_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_48_PACKETS_IN_FLIGHT - ACB Queue 48 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_48_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: input_is_acb_queue_48_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_acb_queue_48_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_48_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_48_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_49_PACKETS_IN_FLIGHT - ACB Queue 49 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_49_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: input_is_acb_queue_49_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_acb_queue_49_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_49_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_49_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_50_PACKETS_IN_FLIGHT - ACB Queue 50 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_50_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: input_is_acb_queue_50_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_acb_queue_50_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_50_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_50_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_51_PACKETS_IN_FLIGHT - ACB Queue 51 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_51_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: input_is_acb_queue_51_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_acb_queue_51_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_51_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_51_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_52_PACKETS_IN_FLIGHT - ACB Queue 52 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_52_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: input_is_acb_queue_52_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_acb_queue_52_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_52_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_52_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_53_PACKETS_IN_FLIGHT - ACB Queue 53 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_53_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: input_is_acb_queue_53_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_acb_queue_53_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_53_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_53_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_54_PACKETS_IN_FLIGHT - ACB Queue 54 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_54_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: input_is_acb_queue_54_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_acb_queue_54_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_54_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_54_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_55_PACKETS_IN_FLIGHT - ACB Queue 55 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_55_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: input_is_acb_queue_55_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_acb_queue_55_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_55_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_55_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_56_PACKETS_IN_FLIGHT - ACB Queue 56 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_56_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: input_is_acb_queue_56_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_acb_queue_56_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_56_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_56_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_57_PACKETS_IN_FLIGHT - ACB Queue 57 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_57_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: input_is_acb_queue_57_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_acb_queue_57_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_57_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_57_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_58_PACKETS_IN_FLIGHT - ACB Queue 58 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_58_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: input_is_acb_queue_58_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_acb_queue_58_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_58_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_58_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_59_PACKETS_IN_FLIGHT - ACB Queue 59 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_59_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: input_is_acb_queue_59_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_acb_queue_59_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_59_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_59_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_60_PACKETS_IN_FLIGHT - ACB Queue 60 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_60_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: input_is_acb_queue_60_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_acb_queue_60_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_60_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_60_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_61_PACKETS_IN_FLIGHT - ACB Queue 61 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_61_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: input_is_acb_queue_61_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_acb_queue_61_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_61_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_61_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_62_PACKETS_IN_FLIGHT - ACB Queue 62 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_62_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: input_is_acb_queue_62_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_acb_queue_62_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_62_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_62_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ACB_QUEUE_63_PACKETS_IN_FLIGHT - ACB Queue 63 Packets In Flight Register
+ ***************************************************************************/
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: reserved0 [31:11] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_reserved0_MASK 0xfffff800
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_reserved0_SHIFT 11
+
+/* union - case input_is_acb_queue_63_packets_in_flight [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: input_is_acb_queue_63_packets_in_flight :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_acb_queue_63_packets_in_flight_pktlen_DEFAULT 0x00000000
+
+/* union - case input_is_gisb [10:00] */
+/* SWITCH_ACB :: ACB_QUEUE_63_PACKETS_IN_FLIGHT :: input_is_gisb :: pktlen [10:00] */
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_MASK 0x000007ff
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_SHIFT 0
+#define BCHP_SWITCH_ACB_ACB_QUEUE_63_PACKETS_IN_FLIGHT_input_is_gisb_pktlen_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_ACB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_switch_core.h b/include/linux/brcmstb/3390b0/bchp_switch_core.h
new file mode 100644
index 000000000000..d04b2bbe8bbc
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_switch_core.h
@@ -0,0 +1,31837 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Wed Jun 10 03:09:37 2015
+ *                 Full Compile MD5 Checksum  e8bde4108283f67d401938287dbb6bde
+ *                     (minus title and desc)
+ *                 MD5 Checksum               56f0f944fbd407545cd964e7b4e7f7b0
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008008
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_CORE_H__
+#define BCHP_SWITCH_CORE_H__
+
+/***************************************************************************
+ *SWITCH_CORE
+ ***************************************************************************/
+#define BCHP_SWITCH_CORE_G_PCTL_P0               0x04e00000 /* [RW] Port 0 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_P1               0x04e00004 /* [RW] Port 1 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_P2               0x04e00008 /* [RW] Port 2 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_P3               0x04e0000c /* [RW] Port 3 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_P4               0x04e00010 /* [RW] Port 4 Control Register */
+#define BCHP_SWITCH_CORE_G_PCTL_P5               0x04e00014 /* [RW] Port 5 Control Register */
+#define BCHP_SWITCH_CORE_CTL_P7                  0x04e0001c /* [RW] Port 7 Control Register */
+#define BCHP_SWITCH_CORE_CTL_IMP                 0x04e00020 /* [RW] IMP Port(Port 8) Control Register */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL           0x04e00028 /* [RW] RX Global Control register(Not2Release) */
+#define BCHP_SWITCH_CORE_SWMODE                  0x04e0002c /* [RW] Switch Mode Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP        0x04e00038 /* [RW] IMP Port(Port 8) States Override Register */
+#define BCHP_SWITCH_CORE_DEBUG_REG               0x04e00078 /* [RW] Debug Control Register(Not2Release) */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG           0x04e0007c /* [RW] Removed Pins Debug Register(Not2Release) */
+#define BCHP_SWITCH_CORE_NEW_CTRL                0x04e00084 /* [RW] New Control Register */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL             0x04e00088 /* [RW] Switch Control Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL           0x04e00090 /* [RW] Protected Port Select Register */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL            0x04e00098 /* [RW] WAN Port select Register */
+#define BCHP_SWITCH_CORE_PAUSE_CAP               0x04e000a0 /* [RW] PAUSE Capability Register */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL          0x04e000bc /* [RW] Reserved Multicast Register */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE          0x04e000c4 /* [RW] TxQ Flush Mode Control Register(Not2Release) */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP            0x04e000c8 /* [RW] Unicast Lookup Failed Forward Map Register */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP            0x04e000d0 /* [RW] Multicast Lookup Failed Forward Map Register */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP        0x04e000d8 /* [RW] IPMC Forward Map Register */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS           0x04e000e0 /* [RW] Pause pass Through for RX Register */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS           0x04e000e8 /* [RW] Pause pass Through for TX Register */
+#define BCHP_SWITCH_CORE_DIS_LEARN               0x04e000f0 /* [RW] Disable Learning Register */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL             0x04e000f8 /* [RW] Software Learning Control */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1          0x04e00100 /* [RW] Low Power Expansion I Register */
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE        0x04e00150 /* [RW] Spare Register (Not2Release) */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0    0x04e00160 /* [RW] Port 0 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1    0x04e00164 /* [RW] Port 1 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2    0x04e00168 /* [RW] Port 2 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3    0x04e0016c /* [RW] Port 3 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4    0x04e00170 /* [RW] Port 4 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5    0x04e00174 /* [RW] Port 5 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7    0x04e0017c /* [RW] Port 7 GMII Port States Override Register */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL          0x04e001e4 /* [RW] Watch Dog Control Register */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1          0x04e001e8 /* [RO] Watch Dog Report 1 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2          0x04e001f0 /* [RO] Watch Dog Report 2 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3          0x04e001f8 /* [RO] Watch Dog Report 3 Register(Not2Release) */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL          0x04e00200 /* [RW] Pause Frame Detection Control Register */
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR           0x04e00204 /* [RW] PAUSE Frame DA Address */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL           0x04e00220 /* [RW] Fast Ageing Control Register */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT           0x04e00224 /* [RW] Fast Ageing Port Control Register */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID            0x04e00228 /* [RW] Fast Ageing VID Control Register */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL          0x04e00378 /* [RW] LOW Power Control Register */
+#define BCHP_SWITCH_CORE_TCAM_CTRL               0x04e003a0 /* [RW] TCAM Control Register */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS         0x04e003a8 /* [RO] TCAM Checksum Status Register */
+#define BCHP_SWITCH_CORE_LNKSTS                  0x04e00400 /* [RO] Link Status Summary Register */
+#define BCHP_SWITCH_CORE_LNKSTSCHG               0x04e00408 /* [RO] Link Status Change Register */
+#define BCHP_SWITCH_CORE_SPDSTS                  0x04e00410 /* [RO] Port Speed Summary Register */
+#define BCHP_SWITCH_CORE_DUPSTS                  0x04e00420 /* [RO] Duplex status Summary Register */
+#define BCHP_SWITCH_CORE_PAUSESTS                0x04e00428 /* [RO] Pause Status Summary Register */
+#define BCHP_SWITCH_CORE_SRCADRCHG               0x04e00438 /* [RO] Source Address Change Register */
+#define BCHP_SWITCH_CORE_LSA_PORT_P0             0x04e00440 /* [RO] Port 0 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P1             0x04e00458 /* [RO] Port 1 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P2             0x04e00470 /* [RO] Port 2 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P3             0x04e00488 /* [RO] Port 3 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P4             0x04e004a0 /* [RO] Port 4 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P5             0x04e004b8 /* [RO] Port 5 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P7             0x04e004e8 /* [RO] Port 7 Last Source Address */
+#define BCHP_SWITCH_CORE_LSA_PORT_P8             0x04e00500 /* [RO] Port 8 Last Source Address */
+#define BCHP_SWITCH_CORE_BIST_STS0               0x04e00518 /* [RO] BIST Status Register 0 */
+#define BCHP_SWITCH_CORE_BIST_STS1               0x04e00530 /* [RO] BIST Status Register 1 */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0             0x04e00540 /* [RO] PBPTRFIFO Status Register 0(Not2Release) */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1             0x04e00558 /* [RO] PBPTRFIFO Status Register 1(Not2Release) */
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS        0x04e005c0 /* [RO] Strap Pin Status Register */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE 0x04e00600 /* [RO] Direct Input Control Value Register */
+#define BCHP_SWITCH_CORE_RESET_STATUS            0x04e00640 /* [RO] Reset Status Register */
+#define BCHP_SWITCH_CORE_ENG_DET_STS             0x04e00648 /* [RO] PHY Energy Detect Status Register */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG         0x04e0064c /* [RO] PHY Energy Detect Status Change Register */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0        0x04e00680 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1        0x04e00690 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_GMNGCFG                 0x04e00800 /* [RW] Global Management Configuration Register */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID             0x04e00804 /* [RO] IMP/IMP0 Port ID Register */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID             0x04e00808 /* [RO] IMP1 Port ID Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL           0x04e0080c /* [RW] BRCM Header Control Register */
+#define BCHP_SWITCH_CORE_SPTAGT                  0x04e00818 /* [RW] Aging Time Control Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2          0x04e00828 /* [RW] BRCM Header Control 2 Register */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL          0x04e00830 /* [RW] IPG Shrink Control Register */
+#define BCHP_SWITCH_CORE_MIRCAPCTL               0x04e00840 /* [RW] Mirror Capture Control Register */
+#define BCHP_SWITCH_CORE_IGMIRCTL                0x04e00848 /* [RW] Ingress Mirror Control Register */
+#define BCHP_SWITCH_CORE_IGMIRDIV                0x04e00850 /* [RW] Ingress Mirror Divider Register */
+#define BCHP_SWITCH_CORE_IGMIRMAC                0x04e00858 /* [RW] Ingress Mirror Mac Address Register */
+#define BCHP_SWITCH_CORE_EGMIRCTL                0x04e00870 /* [RW] Egress Mirror Control Register */
+#define BCHP_SWITCH_CORE_EGMIRDIV                0x04e00878 /* [RW] Egress Mirror Divider Register */
+#define BCHP_SWITCH_CORE_EGMIRMAC                0x04e00880 /* [RW] Egress Mirror MAC Address Register */
+#define BCHP_SWITCH_CORE_MODEL_ID                0x04e008c0 /* [RO] Model ID Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CHIP_REVID              0x04e00900 /* [RO] Chip Version ID Register */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL            0x04e00940 /* [RW] High Level Protocol Control Register */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN          0x04e00950 /* [RW] Reset MIB Counter Enable Register */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA        0x04e00960 /* [RW] IPG Shrink 2G Workaround Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS         0x04e00980 /* [RW] Broadcom Header RX Disable Register */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS         0x04e00988 /* [RW] Broadcom Header TX Disable Register */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0      0x04e009c0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1      0x04e009d0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_INT_STS                 0x04e00c00 /* [RW] External Host Raw Interrupt Status Register */
+#define BCHP_SWITCH_CORE_INT_EN                  0x04e00c20 /* [RW] External Host Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP         0x04e00c40 /* [RW] IMP Port(port 8) Sleep Timer Register */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER       0x04e00c48 /* [RW] Port 7 Sleep Timer Register */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER         0x04e00c50 /* [RW] WAN Port Sleep Timer Register */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS          0x04e00c60 /* [RO] Port Sleep Status Register */
+#define BCHP_SWITCH_CORE_INT_TRIGGER             0x04e00c80 /* [RW] Interrupt Trigger Register */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN         0x04e00c90 /* [RW] Link Status Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN          0x04e00ca0 /* [RW] Energy Detection Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN      0x04e00ca8 /* [RW] LPI Status Change Interrupt Enable Register */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS     0x04e00d80 /* [RW] Memory ECC Double-Error-Detection Interrupt Status (Not2Release) */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN      0x04e00d88 /* [RW] Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS    0x04e00d90 /* [RW] Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS    0x04e00d98 /* [RW] Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS    0x04e00da0 /* [RW] Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL           0x04e00dc0 /* [RW] Probe Bus Control Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL         0x04e00dd0 /* [RW] MDC Extend Clock Control Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN  0x04e00e00 /* [RW] PPPoE Session Packet Parsing Enable Register */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0     0x04e00e40 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1     0x04e00e50 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_GARLCFG                 0x04e01000 /* [RW] Global ARL Configuration Register */
+#define BCHP_SWITCH_CORE_BPDU_MCADDR             0x04e01010 /* [RW] BPDU Multicast Address Register */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL          0x04e01038 /* [RW] Multiport Control Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0         0x04e01040 /* [RW] Multiport Address 0 Register (Default for TS) */
+#define BCHP_SWITCH_CORE_MPORTVEC0               0x04e01060 /* [RW] Multiport Vector 0 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1         0x04e01080 /* [RW] Multiport Address 1 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC1               0x04e010a0 /* [RW] Multiport Vector 1 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2         0x04e010c0 /* [RW] Multiport Address 2 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC2               0x04e010e0 /* [RW] Multiport Vector 2 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3         0x04e01100 /* [RW] Multiport Address 3 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC3               0x04e01120 /* [RW] Multiport Vector 3 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4         0x04e01140 /* [RW] Multiport Address 4 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC4               0x04e01160 /* [RW] Multiport Vector 4 Register */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5         0x04e01180 /* [RW] Multiport Address 5 Register */
+#define BCHP_SWITCH_CORE_MPORTVEC5               0x04e011a0 /* [RW] Multiport Vector 5 Register */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR       0x04e011c0 /* [RW] ARL Bin Full Counter Register */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD        0x04e011d0 /* [RW] ARL Biin Full Forward Enable Register */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0       0x04e01200 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1       0x04e01210 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL              0x04e01400 /* [RW] ARL Read/Write Control Register */
+#define BCHP_SWITCH_CORE_ARLA_MAC                0x04e01408 /* [RW] MAC Address Index Register */
+#define BCHP_SWITCH_CORE_ARLA_VID                0x04e01420 /* [RW] VID Index Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0      0x04e01440 /* [RW] ARL MAC/VID Entry 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0         0x04e01460 /* [RW] ARL FWD Entry 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1      0x04e01480 /* [RW] ARL MAC/VID Entry 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1         0x04e014a0 /* [RW] ARL FWD Entry 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2      0x04e014c0 /* [RW] ARL MAC/VID Entry 2 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2         0x04e014e0 /* [RW] ARL FWD Entry 2 Register */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3      0x04e01500 /* [RW] ARL MAC/VID Entry 3 Register */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3         0x04e01520 /* [RW] ARL FWD Entry 3 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL           0x04e01540 /* [RW] ARL Search Control Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR           0x04e01544 /* [RO] ARL Search Address Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID 0x04e01580 /* [RO] ARL Search MAC/VID Result 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0        0x04e015a0 /* [RO] ARL Search Result 0 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID 0x04e015c0 /* [RO] ARL Search MAC/VID Result 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1        0x04e015e0 /* [RO] ARL Search Result 1 Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL        0x04e01600 /* [RW] VTBL Read/Write/Clear Control Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR          0x04e01604 /* [RW] VTBL Address Index Register */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY         0x04e0160c /* [RW] VTBL Entry Register */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0      0x04e01640 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1      0x04e01650 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MEM_CTRL                0x04e02000 /* [RW] Memory Debug Control Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_ADDR                0x04e02004 /* [RW] Memory Debug Address Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0      0x04e02020 /* [RW] Memory Debug Data 0_0 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1      0x04e02040 /* [RW] Memory Debug Data 0_1 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0      0x04e02048 /* [RW] Memory Debug Data 1_0 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1      0x04e02068 /* [RW] Memory Debug Data 1_1 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR            0x04e02080 /* [RW] Frame Memory Address Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0           0x04e020c0 /* [RW] Frame Memory Data 1st Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1           0x04e020e0 /* [RW] Frame Memory Data 2st Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2           0x04e02100 /* [RW] Frame Memory Data 3st Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3           0x04e02120 /* [RW] Frame Memory Data 4th Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0           0x04e02140 /* [RO] Buffer Tag Memory Register 0Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1           0x04e02160 /* [RO] Buffer Tag Memory Register 1Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR            0x04e02180 /* [RW] Buffer Control Memory Address Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA            0x04e02188 /* [RO] Buffer Control Memory Data Register Not2Release */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL     0x04e021c0 /* [RW] PRS_FIFO Debug Control Register(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA     0x04e021c4 /* [RO] PRS_FIFO Debug Data Register(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0          0x04e022a0 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1          0x04e022b0 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL           0x04e022c0 /* [RW] Memory Misc Control Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0          0x04e022d0 /* [RW] Memory Test Control 0 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1          0x04e022e0 /* [RW] Memory Test Control 1 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2          0x04e022f0 /* [RW] Memory Test Control 2 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3          0x04e02300 /* [RW] Memory Test Control 3 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4          0x04e02310 /* [RW] Memory Test Control 4 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5          0x04e02320 /* [RW] Memory Test Control 5 Register Not2Release */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL        0x04e02380 /* [RW] Memory PSM_VDD Pin Control registerNot2Release */
+#define BCHP_SWITCH_CORE_PORT0_DEBUG             0x04e02400 /* [RO] PORT0 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT1_DEBUG             0x04e02440 /* [RO] PORT1 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT2_DEBUG             0x04e02480 /* [RO] PORT2 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT3_DEBUG             0x04e024c0 /* [RO] PORT3 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT4_DEBUG             0x04e02500 /* [RO] PORT4 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT5_DEBUG             0x04e02540 /* [RO] PORT5 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT6_DEBUG             0x04e02580 /* [RO] PORT6 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT7_DEBUG             0x04e025c0 /* [RO] PORT7 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_PORT8_DEBUG             0x04e02600 /* [RO] PORT8 DEBUGNot2Release */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL            0x04e02800 /* [RW] Flowcon Diagnosis Control Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE            0x04e02808 /* [RW] Flow Control Mode Selection Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT            0x04e0280c /* [RW] Flow Control Port Selection Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN         0x04e02810 /* [RW] OOB Pause Signal Enable Register (Release2Customer)Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX          0x04e02840 /* [RW] MAX Quantum Pause Time Register Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN          0x04e02848 /* [RW] MIN Quantum Pause Time Register Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD    0x04e02850 /* [RW] Quantum Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD 0x04e02858 /* [RW] Quantum Pause Update Period Register Not2Release */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT      0x04e02860 /* [RW] Default Quantum Pause Time Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL      0x04e02868 /* [RW] Multicast Drop Control Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL      0x04e02870 /* [RW] Pause/Drop Control Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF    0x04e02878 /* [RW] TXQ Pause Off Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF            0x04e02880 /* [RW] RX-Based Run-Off Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD           0x04e02888 /* [RW] RX-Based Reserved Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD          0x04e02890 /* [RW] RX-Based Hysteresis Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR           0x04e02898 /* [RW] RX-Based Maximum Buffer Remap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG       0x04e028a0 /* [RW] Flow Control Spare Zero Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG        0x04e028a8 /* [RW] Flow Control Spare One Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0            0x04e028c0 /* [RO] Monitored TXQ 0 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1            0x04e028c8 /* [RO] Monitored TXQ 1 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2            0x04e028d0 /* [RO] Monitored TXQ 2 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3            0x04e028d8 /* [RO] Monitored TXQ 3 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4            0x04e028e0 /* [RO] Monitored TXQ 4 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5            0x04e028e8 /* [RO] Monitored TXQ 5 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6            0x04e028f0 /* [RO] Monitored TXQ 6 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7            0x04e028f8 /* [RO] Monitored TXQ 7 Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0           0x04e02900 /* [RO] Peak TXQ 0 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1           0x04e02908 /* [RO] Peak TXQ 1 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2           0x04e02910 /* [RO] Peak TXQ 2 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3           0x04e02918 /* [RO] Peak TXQ 3 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4           0x04e02920 /* [RO] Peak TXQ 4 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5           0x04e02928 /* [RO] Peak TXQ 5 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6           0x04e02930 /* [RO] Peak TXQ 6 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7           0x04e02938 /* [RO] Peak TXQ 7 Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED      0x04e02940 /* [RO] Peak Total Used Count Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED           0x04e02948 /* [RO] Total Used Count Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT          0x04e02950 /* [RO] Peak RX Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP         0x04e02958 /* [RO] PHY Link Information Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP         0x04e02960 /* [RO] Giga Speed Information Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0      0x04e02980 /* [RO] Port 0 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1      0x04e02988 /* [RO] Port 1 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2      0x04e02990 /* [RO] Port 2 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3      0x04e02998 /* [RO] Port 3 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4      0x04e029a0 /* [RO] Port 4 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5      0x04e029a8 /* [RO] Port 5 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7      0x04e029b8 /* [RO] Port 7 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8      0x04e029c0 /* [RO] Port 8 Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS            0x04e029e0 /* [RO] Pause History Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS 0x04e029e8 /* [RO] TX Quantum Pause History Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS         0x04e029f0 /* [RO] RX Based Pause History Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS        0x04e029f8 /* [RO] RX Buffer Error History Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0  0x04e02a00 /* [RO] Port 0 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1  0x04e02a08 /* [RO] Port 1 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2  0x04e02a10 /* [RO] Port 2 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3  0x04e02a18 /* [RO] Port 3 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4  0x04e02a20 /* [RO] Port 4 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5  0x04e02a28 /* [RO] Port 5 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7  0x04e02a38 /* [RO] Port 7 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8  0x04e02a40 /* [RO] Port 8 TXQ Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0 0x04e02a68 /* [RO] Port 0 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1 0x04e02a70 /* [RO] Port 1 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2 0x04e02a78 /* [RO] Port 2 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3 0x04e02a80 /* [RO] Port 3 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4 0x04e02a88 /* [RO] Port 4 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5 0x04e02a90 /* [RO] Port 5 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7 0x04e02aa0 /* [RO] Port 7 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8 0x04e02aa8 /* [RO] Port 8 Total Congested PortMap Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0   0x04e02c00 /* [RW] LAN Port Queue 0 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1   0x04e02c08 /* [RW] LAN Port Queue 1 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2   0x04e02c10 /* [RW] LAN Port Queue 2 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3   0x04e02c18 /* [RW] LAN Port Queue 3 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4   0x04e02c20 /* [RW] LAN Port Queue 4 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5   0x04e02c28 /* [RW] LAN Port Queue 5 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6   0x04e02c30 /* [RW] LAN Port Queue 6 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7   0x04e02c38 /* [RW] LAN Port Queue 7 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0  0x04e02c40 /* [RW] LAN Port Queue 0 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1  0x04e02c48 /* [RW] LAN Port Queue 1 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2  0x04e02c50 /* [RW] LAN Port Queue 2 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3  0x04e02c58 /* [RW] LAN Port Queue 3 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4  0x04e02c60 /* [RW] LAN Port Queue 4 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5  0x04e02c68 /* [RW] LAN Port Queue 5 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6  0x04e02c70 /* [RW] LAN Port Queue 6 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7  0x04e02c78 /* [RW] LAN Port Queue 7 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0 0x04e02c80 /* [RW] LAN Port Queue 0 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1 0x04e02c88 /* [RW] LAN Port Queue 1 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2 0x04e02c90 /* [RW] LAN Port Queue 2 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3 0x04e02c98 /* [RW] LAN Port Queue 3 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4 0x04e02ca0 /* [RW] LAN Port Queue 4 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5 0x04e02ca8 /* [RW] LAN Port Queue 5 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6 0x04e02cb0 /* [RW] LAN Port Queue 6 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7 0x04e02cb8 /* [RW] LAN Port Queue 7 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0  0x04e02cc0 /* [RW] LAN Port Queue 0 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1  0x04e02cc8 /* [RW] LAN Port Queue 1 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2  0x04e02cd0 /* [RW] LAN Port Queue 2 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3  0x04e02cd8 /* [RW] LAN Port Queue 3 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4  0x04e02ce0 /* [RW] LAN Port Queue 4 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5  0x04e02ce8 /* [RW] LAN Port Queue 5 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6  0x04e02cf0 /* [RW] LAN Port Queue 6 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7  0x04e02cf8 /* [RW] LAN Port Queue 7 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0 0x04e02d00 /* [RW] LAN Port Queue 0 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1 0x04e02d08 /* [RW] LAN Port Queue 1 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2 0x04e02d10 /* [RW] LAN Port Queue 2 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3 0x04e02d18 /* [RW] LAN Port Queue 3 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4 0x04e02d20 /* [RW] LAN Port Queue 4 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5 0x04e02d28 /* [RW] LAN Port Queue 5 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6 0x04e02d30 /* [RW] LAN Port Queue 6 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7 0x04e02d38 /* [RW] LAN Port Queue 7 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0 0x04e02d40 /* [RW] LAN Port Queue 0 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1 0x04e02d48 /* [RW] LAN Port Queue 1 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2 0x04e02d50 /* [RW] LAN Port Queue 2 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3 0x04e02d58 /* [RW] LAN Port Queue 3 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4 0x04e02d60 /* [RW] LAN Port Queue 4 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5 0x04e02d68 /* [RW] LAN Port Queue 5 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6 0x04e02d70 /* [RW] LAN Port Queue 6 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7 0x04e02d78 /* [RW] LAN Port Queue 7 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0 0x04e02d80 /* [RW] LAN Port Queue 0 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1 0x04e02d88 /* [RW] LAN Port Queue 1 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2 0x04e02d90 /* [RW] LAN Port Queue 2 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3 0x04e02d98 /* [RW] LAN Port Queue 3 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4 0x04e02da0 /* [RW] LAN Port Queue 4 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5 0x04e02da8 /* [RW] LAN Port Queue 5 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6 0x04e02db0 /* [RW] LAN Port Queue 6 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7 0x04e02db8 /* [RW] LAN Port Queue 7 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX            0x04e03000 /* [RO] P0 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX            0x04e03010 /* [RO] P1 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX            0x04e03020 /* [RO] P2 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX            0x04e03030 /* [RO] P3 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX            0x04e03040 /* [RO] P4 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX            0x04e03050 /* [RO] P5 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX            0x04e03060 /* [RO] P6 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_DEBUG_MUX_P7            0x04e03070 /* [RO] P7 DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_DEBUG_MUX_IMP           0x04e03080 /* [RO] IMP DEBUG MUXNot2Release */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0         0x04e03090 /* [RO] CFP DEBUG BUS 0Not2Release */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1         0x04e030a0 /* [RO] CFP DEBUG BUS 1Not2Release */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0            0x04e030b0 /* [RO] WRED DEBUG 0Not2Release */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1            0x04e030c0 /* [RO] WRED DEBUG 1Not2Release */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0        0x04e030d0 /* [RO] TOP MISC DEBUG 0Not2Release */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1        0x04e030e0 /* [RO] TOP MISC DEBUG 1Not2Release */
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON          0x04e030f0 /* [RO] DIAGREG BUFCONNot2Release */
+#define BCHP_SWITCH_CORE_TESTBUS_P1588           0x04e03100 /* [RO] TESTBUS P1588Not2Release */
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS       0x04e03110 /* [RO] FLOWCON DEBUG BUSNot2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0  0x04e03400 /* [RW] IMP0 Port(Port 8) Queue 0 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1  0x04e03408 /* [RW] IMP0 Port(Port 8) Queue 1 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2  0x04e03410 /* [RW] IMP0 Port(Port 8) Queue 2 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3  0x04e03418 /* [RW] IMP0 Port(Port 8) Queue 3 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4  0x04e03420 /* [RW] IMP0 Port(Port 8) Queue 4 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5  0x04e03428 /* [RW] IMP0 Port(Port 8) Queue 5 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6  0x04e03430 /* [RW] IMP0 Port(Port 8) Queue 6 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7  0x04e03438 /* [RW] IMP0 Port(Port 8) Queue 7 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0 0x04e03440 /* [RW] IMP0 Port(Port 8) Queue 0 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1 0x04e03448 /* [RW] IMP0 Port(Port 8) Queue 1 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2 0x04e03450 /* [RW] IMP0 Port(Port 8) Queue 2 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3 0x04e03458 /* [RW] IMP0 Port(Port 8) Queue 3 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4 0x04e03460 /* [RW] IMP0 Port(Port 8) Queue 4 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5 0x04e03468 /* [RW] IMP0 Port(Port 8) Queue 5 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6 0x04e03470 /* [RW] IMP0 Port(Port 8) Queue 6 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7 0x04e03478 /* [RW] IMP0 Port(Port 8) Queue 7 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0 0x04e03480 /* [RW] IMP0 Port(Port 8) Queue 0 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1 0x04e03488 /* [RW] IMP0 Port(Port 8) Queue 1 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2 0x04e03490 /* [RW] IMP0 Port(Port 8) Queue 2 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3 0x04e03498 /* [RW] IMP0 Port(Port 8) Queue 3 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4 0x04e034a0 /* [RW] IMP0 Port(Port 8) Queue 4 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5 0x04e034a8 /* [RW] IMP0 Port(Port 8) Queue 5 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6 0x04e034b0 /* [RW] IMP0 Port(Port 8) Queue 6 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7 0x04e034b8 /* [RW] IMP0 Port(Port 8) Queue 7 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0 0x04e034c0 /* [RW] IMP0 Port(Port 8) Queue 0 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1 0x04e034c8 /* [RW] IMP0 Port(Port 8) Queue 1 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2 0x04e034d0 /* [RW] IMP0 Port(Port 8) Queue 2 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3 0x04e034d8 /* [RW] IMP0 Port(Port 8) Queue 3 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4 0x04e034e0 /* [RW] IMP0 Port(Port 8) Queue 4 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5 0x04e034e8 /* [RW] IMP0 Port(Port 8) Queue 5 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6 0x04e034f0 /* [RW] IMP0 Port(Port 8) Queue 6 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7 0x04e034f8 /* [RW] IMP0 Port(Port 8) Queue 7 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0 0x04e03500 /* [RW] IMP0 Port(Port 8) Queue 0 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1 0x04e03508 /* [RW] IMP0 Port(Port 8) Queue 1 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2 0x04e03510 /* [RW] IMP0 Port(Port 8) Queue 2 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3 0x04e03518 /* [RW] IMP0 Port(Port 8) Queue 3 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4 0x04e03520 /* [RW] IMP0 Port(Port 8) Queue 4 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5 0x04e03528 /* [RW] IMP0 Port(Port 8) Queue 5 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6 0x04e03530 /* [RW] IMP0 Port(Port 8) Queue 6 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7 0x04e03538 /* [RW] IMP0 Port(Port 8) Queue 7 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0 0x04e03540 /* [RW] IMP0 Port(Port 8) Queue 0 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1 0x04e03548 /* [RW] IMP0 Port(Port 8) Queue 1 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2 0x04e03550 /* [RW] IMP0 Port(Port 8) Queue 2 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3 0x04e03558 /* [RW] IMP0 Port(Port 8) Queue 3 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4 0x04e03560 /* [RW] IMP0 Port(Port 8) Queue 4 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5 0x04e03568 /* [RW] IMP0 Port(Port 8) Queue 5 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6 0x04e03570 /* [RW] IMP0 Port(Port 8) Queue 6 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7 0x04e03578 /* [RW] IMP0 Port(Port 8) Queue 7 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0 0x04e03580 /* [RW] IMP0 Port(Port 8) Queue 0 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1 0x04e03588 /* [RW] IMP0 Port(Port 8) Queue 1 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2 0x04e03590 /* [RW] IMP0 Port(Port 8) Queue 2 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3 0x04e03598 /* [RW] IMP0 Port(Port 8) Queue 3 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4 0x04e035a0 /* [RW] IMP0 Port(Port 8) Queue 4 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5 0x04e035a8 /* [RW] IMP0 Port(Port 8) Queue 5 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6 0x04e035b0 /* [RW] IMP0 Port(Port 8) Queue 6 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7 0x04e035b8 /* [RW] IMP0 Port(Port 8) Queue 7 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0      0x04e035c0 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1      0x04e035c8 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0 0x04e03800 /* [RW] WAN/IMP1 Port Queue 0 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1 0x04e03808 /* [RW] WAN/IMP1 Port Queue 1 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2 0x04e03810 /* [RW] WAN/IMP1 Port Queue 2 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3 0x04e03818 /* [RW] WAN/IMP1 Port Queue 3 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4 0x04e03820 /* [RW] WAN/IMP1 Port Queue 4 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5 0x04e03828 /* [RW] WAN/IMP1 Port Queue 5 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6 0x04e03830 /* [RW] WAN/IMP1 Port Queue 6 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7 0x04e03838 /* [RW] WAN/IMP1 Port Queue 7 Reserved Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0 0x04e03840 /* [RW] WAN/IMP1 Port Queue 0 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1 0x04e03848 /* [RW] WAN/IMP1 Port Queue 1 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2 0x04e03850 /* [RW] WAN/IMP1 Port Queue 2 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3 0x04e03858 /* [RW] WAN/IMP1 Port Queue 3 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4 0x04e03860 /* [RW] WAN/IMP1 Port Queue 4 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5 0x04e03868 /* [RW] WAN/IMP1 Port Queue 5 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6 0x04e03870 /* [RW] WAN/IMP1 Port Queue 6 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7 0x04e03878 /* [RW] WAN/IMP1 Port Queue 7 Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 0x04e03880 /* [RW] WAN/IMP1 Port Queue 0 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 0x04e03888 /* [RW] WAN/IMP1 Port Queue 1 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 0x04e03890 /* [RW] WAN/IMP1 Port Queue 2 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 0x04e03898 /* [RW] WAN/IMP1 Port Queue 3 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 0x04e038a0 /* [RW] WAN/IMP1 Port Queue 4 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 0x04e038a8 /* [RW] WAN/IMP1 Port Queue 5 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 0x04e038b0 /* [RW] WAN/IMP1 Port Queue 6 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 0x04e038b8 /* [RW] WAN/IMP1 Port Queue 7 Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0 0x04e038c0 /* [RW] WAN/IMP1 Port Queue 0 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1 0x04e038c8 /* [RW] WAN/IMP1 Port Queue 1 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2 0x04e038d0 /* [RW] WAN/IMP1 Port Queue 2 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3 0x04e038d8 /* [RW] WAN/IMP1 Port Queue 3 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4 0x04e038e0 /* [RW] WAN/IMP1 Port Queue 4 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5 0x04e038e8 /* [RW] WAN/IMP1 Port Queue 5 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6 0x04e038f0 /* [RW] WAN/IMP1 Port Queue 6 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7 0x04e038f8 /* [RW] WAN/IMP1 Port Queue 7 DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0 0x04e03900 /* [RW] WAN/IMP1 Port Queue 0 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1 0x04e03908 /* [RW] WAN/IMP1 Port Queue 1 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2 0x04e03910 /* [RW] WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3 0x04e03918 /* [RW] WAN/IMP1 Port Queue 3 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4 0x04e03920 /* [RW] WAN/IMP1 Port Queue 4 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5 0x04e03928 /* [RW] WAN/IMP1 Port Queue 5 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6 0x04e03930 /* [RW] WAN/IMP1 Port Queue 6 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7 0x04e03938 /* [RW] WAN/IMP1 Port Queue 7 Total Hysteresis Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 0x04e03940 /* [RW] WAN/IMP1 Port Queue 0 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 0x04e03948 /* [RW] WAN/IMP1 Port Queue 1 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 0x04e03950 /* [RW] WAN/IMP1 Port Queue 2 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 0x04e03958 /* [RW] WAN/IMP1 Port Queue 3 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 0x04e03960 /* [RW] WAN/IMP1 Port Queue 4 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 0x04e03968 /* [RW] WAN/IMP1 Port Queue 5 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 0x04e03970 /* [RW] WAN/IMP1 Port Queue 6 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 0x04e03978 /* [RW] WAN/IMP1 Port Queue 7 Total Pause Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0 0x04e03980 /* [RW] WAN/IMP1 Port Queue 0 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1 0x04e03988 /* [RW] WAN/IMP1 Port Queue 1 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2 0x04e03990 /* [RW] WAN/IMP1 Port Queue 2 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3 0x04e03998 /* [RW] WAN/IMP1 Port Queue 3 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4 0x04e039a0 /* [RW] WAN/IMP1 Port Queue 4 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5 0x04e039a8 /* [RW] WAN/IMP1 Port Queue 5 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6 0x04e039b0 /* [RW] WAN/IMP1 Port Queue 6 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7 0x04e039b8 /* [RW] WAN/IMP1 Port Queue 7 Total DROP Threshold Register Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0  0x04e039c0 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1  0x04e039c8 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL            0x04e03c00 /* [RW] Temperature Monitor Control Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU           0x04e03c08 /* [RW] Temperature Monitor Result Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU      0x04e03c10 /* [RW] Peak Temperature Monitor Result Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL            0x04e03c18 /* [RW] Temperature Monitor Calibration Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL       0x04e03c20 /* [RW] Temperature Monitor Special Control Registers(Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TxOctets_P0             0x04e08000 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P0           0x04e08020 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0             0x04e08030 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0      0x04e08040 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0      0x04e08050 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0        0x04e08060 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P0         0x04e08070 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0    0x04e08080 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0  0x04e08090 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0   0x04e080a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P0      0x04e080b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0 0x04e080c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0        0x04e080d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P0          0x04e080e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0             0x04e080f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0             0x04e08100 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0             0x04e08110 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0             0x04e08120 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0             0x04e08130 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P0             0x04e08140 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0      0x04e08160 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P0          0x04e08170 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0       0x04e08180 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0  0x04e08190 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0 0x04e081a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0 0x04e081b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0 0x04e081c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0 0x04e081d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0       0x04e081e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P0            0x04e081f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0    0x04e08200 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0          0x04e08210 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0         0x04e08220 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P0           0x04e08240 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0        0x04e08250 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0      0x04e08260 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0      0x04e08270 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P0          0x04e08280 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P0          0x04e08290 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0           0x04e082a0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P0           0x04e082b0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0      0x04e082c0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0     0x04e082d0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0        0x04e082e0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0     0x04e082f0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P0            0x04e08300 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0             0x04e08320 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0             0x04e08330 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0       0x04e08340 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0  0x04e08350 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0 0x04e08360 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0 0x04e08370 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0 0x04e08380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0 0x04e08390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P1             0x04e08400 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P1           0x04e08420 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1             0x04e08430 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1      0x04e08440 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1      0x04e08450 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1        0x04e08460 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P1         0x04e08470 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1    0x04e08480 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1  0x04e08490 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1   0x04e084a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P1      0x04e084b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1 0x04e084c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1        0x04e084d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P1          0x04e084e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1             0x04e084f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1             0x04e08500 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1             0x04e08510 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1             0x04e08520 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1             0x04e08530 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P1             0x04e08540 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1      0x04e08560 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P1          0x04e08570 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1       0x04e08580 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1  0x04e08590 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1 0x04e085a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1 0x04e085b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1 0x04e085c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1 0x04e085d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1       0x04e085e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P1            0x04e085f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1    0x04e08600 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1          0x04e08610 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1         0x04e08620 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P1           0x04e08640 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1        0x04e08650 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1      0x04e08660 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1      0x04e08670 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P1          0x04e08680 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P1          0x04e08690 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1           0x04e086a0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P1           0x04e086b0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1      0x04e086c0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1     0x04e086d0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1        0x04e086e0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1     0x04e086f0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P1            0x04e08700 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1             0x04e08720 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1             0x04e08730 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1       0x04e08740 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1  0x04e08750 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1 0x04e08760 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1 0x04e08770 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1 0x04e08780 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1 0x04e08790 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P2             0x04e08800 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P2           0x04e08820 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2             0x04e08830 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2      0x04e08840 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2      0x04e08850 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2        0x04e08860 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P2         0x04e08870 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2    0x04e08880 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2  0x04e08890 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2   0x04e088a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P2      0x04e088b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2 0x04e088c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2        0x04e088d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P2          0x04e088e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2             0x04e088f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2             0x04e08900 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2             0x04e08910 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2             0x04e08920 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2             0x04e08930 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P2             0x04e08940 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2      0x04e08960 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P2          0x04e08970 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2       0x04e08980 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2  0x04e08990 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2 0x04e089a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2 0x04e089b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2 0x04e089c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2 0x04e089d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2       0x04e089e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P2            0x04e089f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2    0x04e08a00 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2          0x04e08a10 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2         0x04e08a20 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P2           0x04e08a40 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2        0x04e08a50 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2      0x04e08a60 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2      0x04e08a70 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P2          0x04e08a80 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P2          0x04e08a90 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2           0x04e08aa0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P2           0x04e08ab0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2      0x04e08ac0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2     0x04e08ad0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2        0x04e08ae0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2     0x04e08af0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P2            0x04e08b00 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2             0x04e08b20 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2             0x04e08b30 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2       0x04e08b40 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2  0x04e08b50 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2 0x04e08b60 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2 0x04e08b70 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2 0x04e08b80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2 0x04e08b90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P3             0x04e08c00 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P3           0x04e08c20 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3             0x04e08c30 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3      0x04e08c40 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3      0x04e08c50 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3        0x04e08c60 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P3         0x04e08c70 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3    0x04e08c80 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3  0x04e08c90 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3   0x04e08ca0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P3      0x04e08cb0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3 0x04e08cc0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3        0x04e08cd0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P3          0x04e08ce0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3             0x04e08cf0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3             0x04e08d00 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3             0x04e08d10 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3             0x04e08d20 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3             0x04e08d30 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P3             0x04e08d40 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3      0x04e08d60 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P3          0x04e08d70 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3       0x04e08d80 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3  0x04e08d90 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3 0x04e08da0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3 0x04e08db0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3 0x04e08dc0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3 0x04e08dd0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3       0x04e08de0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P3            0x04e08df0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3    0x04e08e00 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3          0x04e08e10 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3         0x04e08e20 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P3           0x04e08e40 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3        0x04e08e50 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3      0x04e08e60 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3      0x04e08e70 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P3          0x04e08e80 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P3          0x04e08e90 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3           0x04e08ea0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P3           0x04e08eb0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3      0x04e08ec0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3     0x04e08ed0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3        0x04e08ee0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3     0x04e08ef0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P3            0x04e08f00 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3             0x04e08f20 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3             0x04e08f30 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3       0x04e08f40 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3  0x04e08f50 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3 0x04e08f60 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3 0x04e08f70 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3 0x04e08f80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3 0x04e08f90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P4             0x04e09000 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P4           0x04e09020 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4             0x04e09030 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4      0x04e09040 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4      0x04e09050 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4        0x04e09060 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P4         0x04e09070 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4    0x04e09080 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4  0x04e09090 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4   0x04e090a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P4      0x04e090b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4 0x04e090c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4        0x04e090d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P4          0x04e090e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4             0x04e090f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4             0x04e09100 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4             0x04e09110 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4             0x04e09120 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4             0x04e09130 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P4             0x04e09140 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4      0x04e09160 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P4          0x04e09170 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4       0x04e09180 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4  0x04e09190 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4 0x04e091a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4 0x04e091b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4 0x04e091c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4 0x04e091d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4       0x04e091e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P4            0x04e091f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4    0x04e09200 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4          0x04e09210 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4         0x04e09220 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P4           0x04e09240 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4        0x04e09250 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4      0x04e09260 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4      0x04e09270 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P4          0x04e09280 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P4          0x04e09290 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4           0x04e092a0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P4           0x04e092b0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4      0x04e092c0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4     0x04e092d0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4        0x04e092e0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4     0x04e092f0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P4            0x04e09300 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4             0x04e09320 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4             0x04e09330 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4       0x04e09340 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4  0x04e09350 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4 0x04e09360 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4 0x04e09370 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4 0x04e09380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4 0x04e09390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P5             0x04e09400 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P5           0x04e09420 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5             0x04e09430 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5      0x04e09440 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5      0x04e09450 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5        0x04e09460 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P5         0x04e09470 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5    0x04e09480 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5  0x04e09490 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5   0x04e094a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P5      0x04e094b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5 0x04e094c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5        0x04e094d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P5          0x04e094e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5             0x04e094f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5             0x04e09500 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5             0x04e09510 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5             0x04e09520 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5             0x04e09530 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P5             0x04e09540 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5      0x04e09560 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P5          0x04e09570 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5       0x04e09580 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5  0x04e09590 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5 0x04e095a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5 0x04e095b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5 0x04e095c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5 0x04e095d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5       0x04e095e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P5            0x04e095f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5    0x04e09600 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5          0x04e09610 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5         0x04e09620 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P5           0x04e09640 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5        0x04e09650 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5      0x04e09660 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5      0x04e09670 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P5          0x04e09680 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P5          0x04e09690 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5           0x04e096a0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P5           0x04e096b0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5      0x04e096c0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5     0x04e096d0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5        0x04e096e0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5     0x04e096f0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P5            0x04e09700 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5             0x04e09720 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5             0x04e09730 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5       0x04e09740 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5  0x04e09750 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5 0x04e09760 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5 0x04e09770 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5 0x04e09780 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5 0x04e09790 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_P7             0x04e09c00 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_P7           0x04e09c20 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7             0x04e09c30 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7      0x04e09c40 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7      0x04e09c50 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7        0x04e09c60 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_P7         0x04e09c70 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7    0x04e09c80 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7  0x04e09c90 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7   0x04e09ca0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_P7      0x04e09cb0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7 0x04e09cc0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7        0x04e09cd0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_P7          0x04e09ce0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7             0x04e09cf0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7             0x04e09d00 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7             0x04e09d10 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7             0x04e09d20 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7             0x04e09d30 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_P7             0x04e09d40 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7      0x04e09d60 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_P7          0x04e09d70 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7       0x04e09d80 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7  0x04e09d90 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7 0x04e09da0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7 0x04e09db0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7 0x04e09dc0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7 0x04e09dd0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7       0x04e09de0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_P7            0x04e09df0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7    0x04e09e00 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7          0x04e09e10 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7         0x04e09e20 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_P7           0x04e09e40 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7        0x04e09e50 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7      0x04e09e60 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7      0x04e09e70 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_P7          0x04e09e80 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_P7          0x04e09e90 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7           0x04e09ea0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_P7           0x04e09eb0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7      0x04e09ec0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7     0x04e09ed0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7        0x04e09ee0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7     0x04e09ef0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_P7            0x04e09f00 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7             0x04e09f20 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7             0x04e09f30 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7       0x04e09f40 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7  0x04e09f50 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7 0x04e09f60 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7 0x04e09f70 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7 0x04e09f80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7 0x04e09f90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxOctets_IMP            0x04e0a000 /* [RW] Tx Octets */
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP          0x04e0a020 /* [RW] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP            0x04e0a030 /* [RW] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP     0x04e0a040 /* [RW] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP     0x04e0a050 /* [RW] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP       0x04e0a060 /* [RW] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_TxCollisions_IMP        0x04e0a070 /* [RW] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP   0x04e0a080 /* [RW] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP 0x04e0a090 /* [RW] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP  0x04e0a0a0 /* [RW] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP     0x04e0a0b0 /* [RW] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP 0x04e0a0c0 /* [RW] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP       0x04e0a0d0 /* [RW] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP         0x04e0a0e0 /* [RW] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP            0x04e0a0f0 /* [RW] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP            0x04e0a100 /* [RW] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP            0x04e0a110 /* [RW] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP            0x04e0a120 /* [RW] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP            0x04e0a130 /* [RW] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_RxOctets_IMP            0x04e0a140 /* [RW] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP     0x04e0a160 /* [RW] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP         0x04e0a170 /* [RW] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP      0x04e0a180 /* [RW] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP 0x04e0a190 /* [RW] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP 0x04e0a1a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP 0x04e0a1b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP 0x04e0a1c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP 0x04e0a1d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP      0x04e0a1e0 /* [RW] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_RxJabbers_IMP           0x04e0a1f0 /* [RW] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP   0x04e0a200 /* [RW] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP         0x04e0a210 /* [RW] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP        0x04e0a220 /* [RW] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP          0x04e0a240 /* [RW] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP       0x04e0a250 /* [RW] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP     0x04e0a260 /* [RW] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP     0x04e0a270 /* [RW] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP         0x04e0a280 /* [RW] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_RxFragments_IMP         0x04e0a290 /* [RW] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP          0x04e0a2a0 /* [RW] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP          0x04e0a2b0 /* [RW] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP     0x04e0a2c0 /* [RW] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP    0x04e0a2d0 /* [RW] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP       0x04e0a2e0 /* [RW] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP    0x04e0a2f0 /* [RW] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_RxDiscard_IMP           0x04e0a300 /* [RW] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP            0x04e0a320 /* [RW] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP            0x04e0a330 /* [RW] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP      0x04e0a340 /* [RW] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP 0x04e0a350 /* [RW] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP 0x04e0a360 /* [RW] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP 0x04e0a370 /* [RW] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP 0x04e0a380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP 0x04e0a390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL         0x04e0c000 /* [RW] QOS Global Control Register */
+#define BCHP_SWITCH_CORE_QOS_1P_EN               0x04e0c010 /* [RW] QoS 802.1P Enable Register */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV         0x04e0c018 /* [RW] QOS DiffServ Enable Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0          0x04e0c040 /* [RW] Port 0 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1          0x04e0c050 /* [RW] Port 1 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2          0x04e0c060 /* [RW] Port 2 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3          0x04e0c070 /* [RW] Port 3 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4          0x04e0c080 /* [RW] Port 4 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5          0x04e0c090 /* [RW] Port 5 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7          0x04e0c0a0 /* [RW] Port 7 PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP         0x04e0c0b0 /* [RW] Port 8 (IMP) PCP to TC Map for DEI 0 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0          0x04e0c0c0 /* [RW] DiffServ Priority Map 0 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1          0x04e0c0d8 /* [RW] DiffServ Priority Map 1 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2          0x04e0c0f0 /* [RW] DiffServ Priority Map 2 Register */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3          0x04e0c108 /* [RW] DiffServ Priority Map 3 Register */
+#define BCHP_SWITCH_CORE_PID2TC                  0x04e0c120 /* [RW] Port ID to TC Map Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0         0x04e0c140 /* [RW] Port 0 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1         0x04e0c148 /* [RW] Port 1 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2         0x04e0c150 /* [RW] Port 2 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3         0x04e0c158 /* [RW] Port 3 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4         0x04e0c160 /* [RW] Port 4 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5         0x04e0c168 /* [RW] Port 5 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7         0x04e0c178 /* [RW] Port 7 TC Select Table Register */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP        0x04e0c180 /* [RW] Port 8 TC Select Table Register */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP             0x04e0c190 /* [RW] CPU to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0           0x04e0c1c0 /* [RW] Port 0 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1           0x04e0c1d0 /* [RW] Port 1 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2           0x04e0c1e0 /* [RW] Port 2 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3           0x04e0c1f0 /* [RW] Port 3 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4           0x04e0c200 /* [RW] Port 4 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5           0x04e0c210 /* [RW] Port 5 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7           0x04e0c230 /* [RW] Port 7 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP          0x04e0c240 /* [RW] Port 8 TC to COS Mapping Register */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0          0x04e0c2a0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1          0x04e0c2b0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0          0x04e0c2c0 /* [RW] Port 0 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1          0x04e0c2d0 /* [RW] Port 1 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2          0x04e0c2e0 /* [RW] Port 2 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3          0x04e0c2f0 /* [RW] Port 3 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4          0x04e0c300 /* [RW] Port 4 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5          0x04e0c310 /* [RW] Port 5 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7          0x04e0c320 /* [RW] Port 7 PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP         0x04e0c330 /* [RW] Port 8 (IMP) PCP to TC Map for DEI 1 Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0             0x04e0c400 /* [RW] PORT 0 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1             0x04e0c408 /* [RW] PORT 1 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2             0x04e0c410 /* [RW] PORT 2 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3             0x04e0c418 /* [RW] PORT 3 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4             0x04e0c420 /* [RW] PORT 4 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5             0x04e0c428 /* [RW] PORT 5 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7             0x04e0c438 /* [RW] PORT 7 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP            0x04e0c440 /* [RW] PORT 8 VLAN Control Register */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0         0x04e0c480 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1         0x04e0c490 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL           0x04e0c800 /* [RW] MAC Trunk Control Register */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL            0x04e0c808 /* [RW] IMP0 Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0          0x04e0c840 /* [RW] Trunk 0 Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1          0x04e0c848 /* [RW] Trunk 1 Group Control Register */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0        0x04e0c880 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1        0x04e0c890 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0              0x04e0d000 /* [RW] 802.1Q VLAN Control 0 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1              0x04e0d004 /* [RW] 802.1Q VLAN Control 1 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2              0x04e0d008 /* [RW] 802.1Q VLAN Control 2 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3              0x04e0d00c /* [RW] 802.1Q VLAN Control 3 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4              0x04e0d014 /* [RW] 802.1Q VLAN Control 4 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5              0x04e0d018 /* [RW] 802.1Q VLAN Control 5 Registers */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6              0x04e0d01c /* [RW] 802.1Q VLAN Control 6 Registers */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL 0x04e0d028 /* [RW] VLAN Multiport Address Control Register */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0       0x04e0d040 /* [RW] Port 0 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1       0x04e0d048 /* [RW] Port 1 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2       0x04e0d050 /* [RW] Port 2 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3       0x04e0d058 /* [RW] Port 3 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4       0x04e0d060 /* [RW] Port 4 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5       0x04e0d068 /* [RW] Port 5 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7       0x04e0d078 /* [RW] Port 7 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP      0x04e0d080 /* [RW] Port 8 802.1Q Default Tag Registers */
+#define BCHP_SWITCH_CORE_DTAG_TPID               0x04e0d0c0 /* [RW] Double Tagging TPID Registers */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP         0x04e0d0c8 /* [RW] ISP Port Selection Portmap Registers */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS  0x04e0d100 /* [RW] Egress VID Remarking Table Access Register */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA 0x04e0d110 /* [RW] Egress VID Remarking Table Data Register */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN        0x04e0d140 /* [RW] Join All VLAN Enable Register */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL       0x04e0d148 /* [RW] Port IVL or SVL Control Register */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0     0x04e0d180 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1     0x04e0d190 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_DOS_CTRL                0x04e0d800 /* [RW] DoS Control RegisterRegister */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ      0x04e0d810 /* [RW] Minimum TCP Header Size Register */
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG     0x04e0d820 /* [RW] Maximum ICMPv4 Size Register */
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG     0x04e0d830 /* [RW] Maximum ICMPv6 Size Register */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG         0x04e0d840 /* [RW] DoS Disable Learn Register */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0          0x04e0d880 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1          0x04e0d890 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK         0x04e10004 /* [RW] Jumbo Frame Port Mask Registers */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE      0x04e10014 /* [RW] Jumbo MIB Good Frame Max Size Registers */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0   0x04e10040 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1   0x04e10050 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON            0x04e10400 /* [RW] Common Ingress rate Control Configuration Registers */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD    0x04e10410 /* [RW] Ingress Rate Control Virtual Zero Threshold Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD           0x04e10418 /* [RW] Ingress Rate Control Alarm Threshold Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0      0x04e10440 /* [RW] Port 0 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1      0x04e10450 /* [RW] Port 1 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2      0x04e10460 /* [RW] Port 2 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3      0x04e10470 /* [RW] Port 3 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4      0x04e10480 /* [RW] Port 4 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5      0x04e10490 /* [RW] Port 5 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7      0x04e104b0 /* [RW] Port 7 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP     0x04e104c0 /* [RW] Port 8 Receive Rate Control Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0    0x04e104d0 /* [RW] Port 0 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1    0x04e104d8 /* [RW] Port 1 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2    0x04e104e0 /* [RW] Port 2 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3    0x04e104e8 /* [RW] Port 3 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4    0x04e104f0 /* [RW] Port 4 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5    0x04e104f8 /* [RW] Port 5 Receive Rate Control 1 Registers */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7    0x04e10508 /* [RW] Port 7 Receive Rate Control 1 Register */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP   0x04e1050c /* [RW] Port 8 Receive Rate Control 1 Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0   0x04e10540 /* [RO] Port 0 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1   0x04e10550 /* [RO] Port 1 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2   0x04e10560 /* [RO] Port 2 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3   0x04e10570 /* [RO] Port 3 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4   0x04e10580 /* [RO] Port 4 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5   0x04e10590 /* [RO] Port 5 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7   0x04e105b0 /* [RO] P7 Suppressed Packet DropCounter Register */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP  0x04e105c0 /* [RO] Port 8 Suppressed Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0  0x04e10740 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1  0x04e10750 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON             0x04e10800 /* [RW] EAP Global Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL     0x04e10804 /* [RW] EAP Multiport Address Control Register */
+#define BCHP_SWITCH_CORE_EAP_DIP0                0x04e10808 /* [RW] EAP Destination IP Registers */
+#define BCHP_SWITCH_CORE_EAP_DIP1                0x04e10828 /* [RW] EAP Destination IP Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P0              0x04e10880 /* [RW] Port 0 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P1              0x04e108a0 /* [RW] Port 1 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P2              0x04e108c0 /* [RW] Port 2 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P3              0x04e108e0 /* [RW] Port 3 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P4              0x04e10900 /* [RW] Port 4 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P5              0x04e10920 /* [RW] Port 5 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_P7              0x04e10960 /* [RW] Port 7 EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP             0x04e10980 /* [RW] IMP EAP Configuration Registers */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0    0x04e109c0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1    0x04e109d0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MST_CON                 0x04e10c00 /* [RW] MST Control Registers */
+#define BCHP_SWITCH_CORE_MST_AGE                 0x04e10c08 /* [RW] MST Ageing Control Register */
+#define BCHP_SWITCH_CORE_MST_TAB0                0x04e10c40 /* [RW] MST Table 0 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB1                0x04e10c50 /* [RW] MST Table 1 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB2                0x04e10c60 /* [RW] MST Table 2 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB3                0x04e10c70 /* [RW] MST Table 3 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB4                0x04e10c80 /* [RW] MST Table 4 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB5                0x04e10c90 /* [RW] MST Table 5 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB6                0x04e10ca0 /* [RW] MST Table 6 Enable Registers */
+#define BCHP_SWITCH_CORE_MST_TAB7                0x04e10cb0 /* [RW] MST Table 7 Enable Registers */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL 0x04e10d40 /* [RW] STP Multiport Address Bypass Control Register */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0    0x04e10d80 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1    0x04e10d90 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE         0x04e11400 /* [RW] SA Limit Enable Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST         0x04e11408 /* [RW] SA Learned Counters Reset Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST   0x04e11410 /* [RW] SA Over Limit Counters Reset Register */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL      0x04e11440 /* [RW] Total SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0         0x04e11448 /* [RW] Port 0 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1         0x04e11450 /* [RW] Port 1 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2         0x04e11458 /* [RW] Port 2 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3         0x04e11460 /* [RW] Port 3 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4         0x04e11468 /* [RW] Port 4 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5         0x04e11470 /* [RW] Port 5 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7         0x04e11480 /* [RW] Port 7 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8         0x04e11488 /* [RW] Port 8 SA Limit Control Register */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR       0x04e114c0 /* [RW] Total SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0          0x04e114c8 /* [RW] Port 0 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1          0x04e114d0 /* [RW] Port 1 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2          0x04e114d8 /* [RW] Port 2 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3          0x04e114e0 /* [RW] Port 3 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4          0x04e114e8 /* [RW] Port 4 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5          0x04e114f0 /* [RW] Port 5 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7          0x04e11500 /* [RW] Port 7 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8          0x04e11508 /* [RW] Port 8 SA Learned Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0    0x04e11540 /* [RW] Port 0 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1    0x04e11550 /* [RW] Port 1 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2    0x04e11560 /* [RW] Port 2 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3    0x04e11570 /* [RW] Port 3 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4    0x04e11580 /* [RW] Port 4 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5    0x04e11590 /* [RW] Port 5 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7    0x04e115b0 /* [RW] Port 7 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8    0x04e115c0 /* [RW] Port 8 SA Over Limit Counter Register */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT 0x04e115d0 /* [RW] SA Over Limit Actions Config Register */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0    0x04e11600 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1    0x04e11610 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0          0x04e11800 /* [RW] Port 0 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1          0x04e11804 /* [RW] Port 1 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2          0x04e11808 /* [RW] Port 2 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3          0x04e1180c /* [RW] Port 3 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4          0x04e11810 /* [RW] Port 4 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5          0x04e11814 /* [RW] Port 5 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7          0x04e1181c /* [RW] Port 7 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP         0x04e11820 /* [RW] Port 8 QOS Priority Control Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0           0x04e11840 /* [RW] Port 0 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1           0x04e11860 /* [RW] Port 1 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2           0x04e11880 /* [RW] Port 2 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3           0x04e118a0 /* [RW] Port 3 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4           0x04e118c0 /* [RW] Port 4 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5           0x04e118e0 /* [RW] Port 5 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7           0x04e11920 /* [RW] Port 7 QOS Weight Register */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP          0x04e11940 /* [RW] Port 8 QOS Weight Register */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0         0x04e11980 /* [RO] Port 0 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1         0x04e11988 /* [RO] Port 1 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2         0x04e11990 /* [RO] Port 2 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3         0x04e11998 /* [RO] Port 3 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4         0x04e119a0 /* [RO] Port 4 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5         0x04e119a8 /* [RO] Port 5 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7         0x04e119c0 /* [RO] Port 7 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY         0x04e119c8 /* [RO] Port 8 WDRR Weight-Scaling Penalty Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0    0x04e11a00 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1    0x04e11a10 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 0x04e11c00 /* [RW] Port 0 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 0x04e11c10 /* [RW] Port 1 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 0x04e11c20 /* [RW] Port 2 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 0x04e11c30 /* [RW] Port 3 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 0x04e11c40 /* [RW] Port 4 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 0x04e11c50 /* [RW] Port 5 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 0x04e11c70 /* [RW] Port 7 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP 0x04e11c80 /* [RW] Port 8 Byte-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 0x04e11cc0 /* [RW] Port 0 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 0x04e11cd0 /* [RW] Port 1 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 0x04e11ce0 /* [RW] Port 2 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 0x04e11cf0 /* [RW] Port 3 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 0x04e11d00 /* [RW] Port 4 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 0x04e11d10 /* [RW] Port 5 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 0x04e11d30 /* [RW] Port 7 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP 0x04e11d40 /* [RW] Port 8 Byte-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0      0x04e11d80 /* [RO] Port 0 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1      0x04e11d90 /* [RO] Port 1 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2      0x04e11da0 /* [RO] Port 2 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3      0x04e11db0 /* [RO] Port 3 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4      0x04e11dc0 /* [RO] Port 4 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5      0x04e11dd0 /* [RO] Port 5 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7      0x04e11df0 /* [RO] Port 7 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP     0x04e11e00 /* [RO] Port 8 PORT Shaper Status Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 0x04e11e40 /* [RW] Port 0 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 0x04e11e50 /* [RW] Port 1 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 0x04e11e60 /* [RW] Port 2 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 0x04e11e70 /* [RW] Port 3 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 0x04e11e80 /* [RW] Port 4 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 0x04e11e90 /* [RW] Port 5 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 0x04e11eb0 /* [RW] Port 7 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP 0x04e11ec0 /* [RW] Port 8 Packet-Based, Port Shaper Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0 0x04e11ee0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1 0x04e11ef0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 0x04e11f00 /* [RW] Port 0 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 0x04e11f10 /* [RW] Port 1 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 0x04e11f20 /* [RW] Port 2 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 0x04e11f30 /* [RW] Port 3 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 0x04e11f40 /* [RW] Port 4 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 0x04e11f50 /* [RW] Port 5 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 0x04e11f70 /* [RW] Port 7 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP 0x04e11f80 /* [RW] Port 8 Packet-Based, Port Shaper Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE 0x04e11f90 /* [RW] Port Shaper AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE      0x04e11f98 /* [RW] Port Shaper Enable Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT 0x04e11fa0 /* [RW] Port Shaper Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING    0x04e11fa8 /* [RW] Port Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_IFG_BYTES               0x04e11fb8 /* [RW] IFG Correction Control Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0   0x04e12000 /* [RW] Port 0 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1   0x04e12010 /* [RW] Port 1 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2   0x04e12020 /* [RW] Port 2 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3   0x04e12030 /* [RW] Port 3 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4   0x04e12040 /* [RW] Port 4 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5   0x04e12050 /* [RW] Port 5 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7   0x04e12070 /* [RW] Port 7 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP  0x04e12080 /* [RW] Port 8 Byte-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0   0x04e120c0 /* [RW] Port 0 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1   0x04e120d0 /* [RW] Port 1 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2   0x04e120e0 /* [RW] Port 2 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3   0x04e120f0 /* [RW] Port 3 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4   0x04e12100 /* [RW] Port 4 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5   0x04e12110 /* [RW] Port 5 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7   0x04e12130 /* [RW] Port 7 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP  0x04e12140 /* [RW] Port 8 Byte-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0    0x04e12180 /* [RO] Port 0 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1    0x04e12190 /* [RO] Port 1 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2    0x04e121a0 /* [RO] Port 2 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3    0x04e121b0 /* [RO] Port 3 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4    0x04e121c0 /* [RO] Port 4 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5    0x04e121d0 /* [RO] Port 5 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7    0x04e121f0 /* [RO] Port 7 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP   0x04e12200 /* [RO] Port 8 Queue 0 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0 0x04e12240 /* [RW] Port 0 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1 0x04e12250 /* [RW] Port 1 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2 0x04e12260 /* [RW] Port 2 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3 0x04e12270 /* [RW] Port 3 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4 0x04e12280 /* [RW] Port 4 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5 0x04e12290 /* [RW] Port 5 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7 0x04e122b0 /* [RW] Port 7 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP 0x04e122c0 /* [RW] Port 8 Packet-based Queue 0 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 0x04e122e0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 0x04e122f0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0 0x04e12300 /* [RW] Port 0 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1 0x04e12310 /* [RW] Port 1 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2 0x04e12320 /* [RW] Port 2 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3 0x04e12330 /* [RW] Port 3 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4 0x04e12340 /* [RW] Port 4 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5 0x04e12350 /* [RW] Port 5 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7 0x04e12370 /* [RW] Port 7 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP 0x04e12380 /* [RW] Port 8 Packet-based Queue 0 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE 0x04e12390 /* [RW] Queue 0 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE    0x04e12398 /* [RW] Queue 0 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT 0x04e123a0 /* [RW] Queue 0 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING  0x04e123a8 /* [RW] Queue 0 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0   0x04e12400 /* [RW] Port 0 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1   0x04e12410 /* [RW] Port 1 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2   0x04e12420 /* [RW] Port 2 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3   0x04e12430 /* [RW] Port 3 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4   0x04e12440 /* [RW] Port 4 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5   0x04e12450 /* [RW] Port 5 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7   0x04e12470 /* [RW] Port 7 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP  0x04e12480 /* [RW] Port 8 Byte-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0   0x04e124c0 /* [RW] Port 0 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1   0x04e124d0 /* [RW] Port 1 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2   0x04e124e0 /* [RW] Port 2 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3   0x04e124f0 /* [RW] Port 3 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4   0x04e12500 /* [RW] Port 4 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5   0x04e12510 /* [RW] Port 5 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7   0x04e12530 /* [RW] Port 7 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP  0x04e12540 /* [RW] Port 8 Byte-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0    0x04e12580 /* [RO] Port 0 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1    0x04e12590 /* [RO] Port 1 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2    0x04e125a0 /* [RO] Port 2 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3    0x04e125b0 /* [RO] Port 3 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4    0x04e125c0 /* [RO] Port 4 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5    0x04e125d0 /* [RO] Port 5 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7    0x04e125f0 /* [RO] Port 7 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP   0x04e12600 /* [RO] Port 8 Queue 1 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0 0x04e12640 /* [RW] Port 0 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1 0x04e12650 /* [RW] Port 1 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2 0x04e12660 /* [RW] Port 2 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3 0x04e12670 /* [RW] Port 3 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4 0x04e12680 /* [RW] Port 4 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5 0x04e12690 /* [RW] Port 5 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7 0x04e126b0 /* [RW] Port 7 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP 0x04e126c0 /* [RW] Port 8 Packet-based Queue 1 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 0x04e126e0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 0x04e126f0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0 0x04e12700 /* [RW] Port 0 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1 0x04e12710 /* [RW] Port 1 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2 0x04e12720 /* [RW] Port 2 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3 0x04e12730 /* [RW] Port 3 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4 0x04e12740 /* [RW] Port 4 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5 0x04e12750 /* [RW] Port 5 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7 0x04e12770 /* [RW] Port 7 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP 0x04e12780 /* [RW] Port 8 Packet-based Queue 1 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE 0x04e12790 /* [RW] Queue 1 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE    0x04e12798 /* [RW] Queue 1 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT 0x04e127a0 /* [RW] Queue 1 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING  0x04e127a8 /* [RW] Queue 1 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0   0x04e12800 /* [RW] Port 0 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1   0x04e12810 /* [RW] Port 1 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2   0x04e12820 /* [RW] Port 2 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3   0x04e12830 /* [RW] Port 3 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4   0x04e12840 /* [RW] Port 4 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5   0x04e12850 /* [RW] Port 5 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7   0x04e12870 /* [RW] Port 7 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP  0x04e12880 /* [RW] Port 8 Byte-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0   0x04e128c0 /* [RW] Port 0 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1   0x04e128d0 /* [RW] Port 1 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2   0x04e128e0 /* [RW] Port 2 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3   0x04e128f0 /* [RW] Port 3 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4   0x04e12900 /* [RW] Port 4 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5   0x04e12910 /* [RW] Port 5 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7   0x04e12930 /* [RW] Port 7 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP  0x04e12940 /* [RW] Port 8 Byte-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0    0x04e12980 /* [RO] Port 0 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1    0x04e12990 /* [RO] Port 1 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2    0x04e129a0 /* [RO] Port 2 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3    0x04e129b0 /* [RO] Port 3 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4    0x04e129c0 /* [RO] Port 4 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5    0x04e129d0 /* [RO] Port 5 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7    0x04e129f0 /* [RO] Port 7 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP   0x04e12a00 /* [RO] Port 8 Queue 2 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0 0x04e12a40 /* [RW] Port 0 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1 0x04e12a50 /* [RW] Port 1 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2 0x04e12a60 /* [RW] Port 2 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3 0x04e12a70 /* [RW] Port 3 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4 0x04e12a80 /* [RW] Port 4 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5 0x04e12a90 /* [RW] Port 5 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7 0x04e12ab0 /* [RW] Port 7 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP 0x04e12ac0 /* [RW] Port 8 Packet-based Queue 2 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 0x04e12ae0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 0x04e12af0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0 0x04e12b00 /* [RW] Port 0 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1 0x04e12b10 /* [RW] Port 1 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2 0x04e12b20 /* [RW] Port 2 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3 0x04e12b30 /* [RW] Port 3 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4 0x04e12b40 /* [RW] Port 4 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5 0x04e12b50 /* [RW] Port 5 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7 0x04e12b70 /* [RW] Port 7 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP 0x04e12b80 /* [RW] Port 8 Packet-based Queue 2 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE 0x04e12b90 /* [RW] Queue 2 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE    0x04e12b98 /* [RW] Queue 2 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT 0x04e12ba0 /* [RW] Queue 2 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING  0x04e12ba8 /* [RW] Queue 2 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0   0x04e12c00 /* [RW] Port 0 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1   0x04e12c10 /* [RW] Port 1 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2   0x04e12c20 /* [RW] Port 2 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3   0x04e12c30 /* [RW] Port 3 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4   0x04e12c40 /* [RW] Port 4 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5   0x04e12c50 /* [RW] Port 5 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7   0x04e12c70 /* [RW] Port 7 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP  0x04e12c80 /* [RW] Port 8 Byte-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0   0x04e12cc0 /* [RW] Port 0 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1   0x04e12cd0 /* [RW] Port 1 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2   0x04e12ce0 /* [RW] Port 2 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3   0x04e12cf0 /* [RW] Port 3 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4   0x04e12d00 /* [RW] Port 4 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5   0x04e12d10 /* [RW] Port 5 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7   0x04e12d30 /* [RW] Port 7 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP  0x04e12d40 /* [RW] Port 8 Byte-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0    0x04e12d80 /* [RO] Port 0 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1    0x04e12d90 /* [RO] Port 1 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2    0x04e12da0 /* [RO] Port 2 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3    0x04e12db0 /* [RO] Port 3 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4    0x04e12dc0 /* [RO] Port 4 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5    0x04e12dd0 /* [RO] Port 5 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7    0x04e12df0 /* [RO] Port 7 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP   0x04e12e00 /* [RO] Port 8 Queue 3 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0 0x04e12e40 /* [RW] Port 0 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1 0x04e12e50 /* [RW] Port 1 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2 0x04e12e60 /* [RW] Port 2 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3 0x04e12e70 /* [RW] Port 3 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4 0x04e12e80 /* [RW] Port 4 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5 0x04e12e90 /* [RW] Port 5 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7 0x04e12eb0 /* [RW] Port 7 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP 0x04e12ec0 /* [RW] Port 8 Packet-based Queue 3 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 0x04e12ee0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 0x04e12ef0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0 0x04e12f00 /* [RW] Port 0 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1 0x04e12f10 /* [RW] Port 1 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2 0x04e12f20 /* [RW] Port 2 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3 0x04e12f30 /* [RW] Port 3 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4 0x04e12f40 /* [RW] Port 4 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5 0x04e12f50 /* [RW] Port 5 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7 0x04e12f70 /* [RW] Port 7 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP 0x04e12f80 /* [RW] Port 8 Packet-based Queue 3 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE 0x04e12f90 /* [RW] Queue 3 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE    0x04e12f98 /* [RW] Queue 3 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT 0x04e12fa0 /* [RW] Queue 3 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING  0x04e12fa8 /* [RW] Queue 3 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0   0x04e13000 /* [RW] Port 0 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1   0x04e13010 /* [RW] Port 1 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2   0x04e13020 /* [RW] Port 2 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3   0x04e13030 /* [RW] Port 3 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4   0x04e13040 /* [RW] Port 4 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5   0x04e13050 /* [RW] Port 5 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7   0x04e13070 /* [RW] Port 7 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP  0x04e13080 /* [RW] Port 8 Byte-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0   0x04e130c0 /* [RW] Port 0 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1   0x04e130d0 /* [RW] Port 1 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2   0x04e130e0 /* [RW] Port 2 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3   0x04e130f0 /* [RW] Port 3 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4   0x04e13100 /* [RW] Port 4 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5   0x04e13110 /* [RW] Port 5 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7   0x04e13130 /* [RW] Port 7 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP  0x04e13140 /* [RW] Port 8 Byte-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0    0x04e13180 /* [RO] Port 0 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1    0x04e13190 /* [RO] Port 1 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2    0x04e131a0 /* [RO] Port 2 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3    0x04e131b0 /* [RO] Port 3 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4    0x04e131c0 /* [RO] Port 4 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5    0x04e131d0 /* [RO] Port 5 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7    0x04e131f0 /* [RO] Port 7 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP   0x04e13200 /* [RO] Port 8 Queue 4 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0 0x04e13240 /* [RW] Port 0 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1 0x04e13250 /* [RW] Port 1 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2 0x04e13260 /* [RW] Port 2 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3 0x04e13270 /* [RW] Port 3 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4 0x04e13280 /* [RW] Port 4 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5 0x04e13290 /* [RW] Port 5 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7 0x04e132b0 /* [RW] Port 7 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP 0x04e132c0 /* [RW] Port 8 Packet-based Queue 4 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 0x04e132e0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 0x04e132f0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0 0x04e13300 /* [RW] Port 0 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1 0x04e13310 /* [RW] Port 1 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2 0x04e13320 /* [RW] Port 2 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3 0x04e13330 /* [RW] Port 3 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4 0x04e13340 /* [RW] Port 4 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5 0x04e13350 /* [RW] Port 5 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7 0x04e13370 /* [RW] Port 7 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP 0x04e13380 /* [RW] Port 8 Packet-based Queue 4 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE 0x04e13390 /* [RW] Queue 4 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE    0x04e13398 /* [RW] Queue 4 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT 0x04e133a0 /* [RW] Queue 4 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING  0x04e133a8 /* [RW] Queue 4 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0   0x04e13400 /* [RW] Port 0 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1   0x04e13410 /* [RW] Port 1 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2   0x04e13420 /* [RW] Port 2 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3   0x04e13430 /* [RW] Port 3 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4   0x04e13440 /* [RW] Port 4 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5   0x04e13450 /* [RW] Port 5 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7   0x04e13470 /* [RW] Port 7 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP  0x04e13480 /* [RW] Port 8 Byte-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0   0x04e134c0 /* [RW] Port 0 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1   0x04e134d0 /* [RW] Port 1 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2   0x04e134e0 /* [RW] Port 2 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3   0x04e134f0 /* [RW] Port 3 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4   0x04e13500 /* [RW] Port 4 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5   0x04e13510 /* [RW] Port 5 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7   0x04e13530 /* [RW] Port 7 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP  0x04e13540 /* [RW] Port 8 Byte-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0    0x04e13580 /* [RO] Port 0 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1    0x04e13590 /* [RO] Port 1 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2    0x04e135a0 /* [RO] Port 2 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3    0x04e135b0 /* [RO] Port 3 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4    0x04e135c0 /* [RO] Port 4 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5    0x04e135d0 /* [RO] Port 5 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7    0x04e135f0 /* [RO] Port 7 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP   0x04e13600 /* [RO] Port 8 Queue 5 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0 0x04e13640 /* [RW] Port 0 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1 0x04e13650 /* [RW] Port 1 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2 0x04e13660 /* [RW] Port 2 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3 0x04e13670 /* [RW] Port 3 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4 0x04e13680 /* [RW] Port 4 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5 0x04e13690 /* [RW] Port 5 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7 0x04e136b0 /* [RW] Port 7 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP 0x04e136c0 /* [RW] Port 8 Packet-based Queue 5 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 0x04e136e0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 0x04e136f0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0 0x04e13700 /* [RW] Port 0 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1 0x04e13710 /* [RW] Port 1 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2 0x04e13720 /* [RW] Port 2 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3 0x04e13730 /* [RW] Port 3 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4 0x04e13740 /* [RW] Port 4 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5 0x04e13750 /* [RW] Port 5 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7 0x04e13770 /* [RW] Port 7 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP 0x04e13780 /* [RW] Port 8 Packet-based Queue 5 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE 0x04e13790 /* [RW] Queue 5 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE    0x04e13798 /* [RW] Queue 5 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT 0x04e137a0 /* [RW] Queue 5 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING  0x04e137a8 /* [RW] Queue 5 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0   0x04e13800 /* [RW] Port 0 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1   0x04e13810 /* [RW] Port 1 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2   0x04e13820 /* [RW] Port 2 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3   0x04e13830 /* [RW] Port 3 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4   0x04e13840 /* [RW] Port 4 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5   0x04e13850 /* [RW] Port 5 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7   0x04e13870 /* [RW] Port 7 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP  0x04e13880 /* [RW] Port 8 Byte-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0   0x04e138c0 /* [RW] Port 0 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1   0x04e138d0 /* [RW] Port 1 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2   0x04e138e0 /* [RW] Port 2 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3   0x04e138f0 /* [RW] Port 3 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4   0x04e13900 /* [RW] Port 4 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5   0x04e13910 /* [RW] Port 5 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7   0x04e13930 /* [RW] Port 7 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP  0x04e13940 /* [RW] Port 8 Byte-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0    0x04e13980 /* [RO] Port 0 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1    0x04e13990 /* [RO] Port 1 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2    0x04e139a0 /* [RO] Port 2 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3    0x04e139b0 /* [RO] Port 3 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4    0x04e139c0 /* [RO] Port 4 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5    0x04e139d0 /* [RO] Port 5 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7    0x04e139f0 /* [RO] Port 7 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP   0x04e13a00 /* [RO] Port 8 Queue 6 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0 0x04e13a40 /* [RW] Port 0 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1 0x04e13a50 /* [RW] Port 1 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2 0x04e13a60 /* [RW] Port 2 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3 0x04e13a70 /* [RW] Port 3 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4 0x04e13a80 /* [RW] Port 4 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5 0x04e13a90 /* [RW] Port 5 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7 0x04e13ab0 /* [RW] Port 7 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP 0x04e13ac0 /* [RW] Port 8 Packet-based Queue 6 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 0x04e13ae0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 0x04e13af0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0 0x04e13b00 /* [RW] Port 0 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1 0x04e13b10 /* [RW] Port 1 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2 0x04e13b20 /* [RW] Port 2 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3 0x04e13b30 /* [RW] Port 3 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4 0x04e13b40 /* [RW] Port 4 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5 0x04e13b50 /* [RW] Port 5 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7 0x04e13b70 /* [RW] Port 7 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP 0x04e13b80 /* [RW] Port 8 Packet-based Queue 6 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE 0x04e13b90 /* [RW] Queue 6 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE    0x04e13b98 /* [RW] Queue 6 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT 0x04e13ba0 /* [RW] Queue 6 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING  0x04e13ba8 /* [RW] Queue 6 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0   0x04e13c00 /* [RW] Port 0 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1   0x04e13c10 /* [RW] Port 1 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2   0x04e13c20 /* [RW] Port 2 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3   0x04e13c30 /* [RW] Port 3 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4   0x04e13c40 /* [RW] Port 4 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5   0x04e13c50 /* [RW] Port 5 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7   0x04e13c70 /* [RW] Port 7 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP  0x04e13c80 /* [RW] Port 8 Byte-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0   0x04e13cc0 /* [RW] Port 0 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1   0x04e13cd0 /* [RW] Port 1 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2   0x04e13ce0 /* [RW] Port 2 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3   0x04e13cf0 /* [RW] Port 3 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4   0x04e13d00 /* [RW] Port 4 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5   0x04e13d10 /* [RW] Port 5 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7   0x04e13d30 /* [RW] Port 7 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP  0x04e13d40 /* [RW] Port 8 Byte-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0    0x04e13d80 /* [RO] Port 0 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1    0x04e13d90 /* [RO] Port 1 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2    0x04e13da0 /* [RO] Port 2 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3    0x04e13db0 /* [RO] Port 3 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4    0x04e13dc0 /* [RO] Port 4 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5    0x04e13dd0 /* [RO] Port 5 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7    0x04e13df0 /* [RO] Port 7 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP   0x04e13e00 /* [RO] Port 8 Queue 7 Shaper Status Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0 0x04e13e40 /* [RW] Port 0 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1 0x04e13e50 /* [RW] Port 1 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2 0x04e13e60 /* [RW] Port 2 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3 0x04e13e70 /* [RW] Port 3 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4 0x04e13e80 /* [RW] Port 4 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5 0x04e13e90 /* [RW] Port 5 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7 0x04e13eb0 /* [RW] Port 7 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP 0x04e13ec0 /* [RW] Port 8 Packet-based Queue 7 Shaping Rate Configure Register */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 0x04e13ee0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 0x04e13ef0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0 0x04e13f00 /* [RW] Port 0 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1 0x04e13f10 /* [RW] Port 1 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2 0x04e13f20 /* [RW] Port 2 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3 0x04e13f30 /* [RW] Port 3 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4 0x04e13f40 /* [RW] Port 4 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5 0x04e13f50 /* [RW] Port 5 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7 0x04e13f70 /* [RW] Port 7 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP 0x04e13f80 /* [RW] Port 8 Packet-based Queue 7 Burst Size Configure Register */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE 0x04e13f90 /* [RW] Queue 7 AVB Shaping Mode Control Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE    0x04e13f98 /* [RW] Queue 7 Shaper Enable Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT 0x04e13fa0 /* [RW] Queue 7 Bucket Count Select Register */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING  0x04e13fa8 /* [RW] Queue 7 Shaper Blocking Control Register */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL        0x04e1c000 /* [RW] MIB Snapshot Control Register */
+#define BCHP_SWITCH_CORE_S_TxOctets              0x04e1c400 /* [RO] Tx Octets */
+#define BCHP_SWITCH_CORE_S_TxDropPkts            0x04e1c420 /* [RO] Tx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0              0x04e1c430 /* [RO] Tx Q0 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts       0x04e1c440 /* [RO] Tx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts       0x04e1c450 /* [RO] Tx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts         0x04e1c460 /* [RO] Tx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxCollisions          0x04e1c470 /* [RO] Tx Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxSingleCollision     0x04e1c480 /* [RO] Tx Single Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision   0x04e1c490 /* [RO] Tx Multiple collsion Counter */
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit    0x04e1c4a0 /* [RO] Tx Deferred Transmit Counter */
+#define BCHP_SWITCH_CORE_S_TxLateCollision       0x04e1c4b0 /* [RO] Tx Late Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision  0x04e1c4c0 /* [RO] Tx Excessive Collision Counter */
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc         0x04e1c4d0 /* [RO] Tx Fram IN Disc Counter */
+#define BCHP_SWITCH_CORE_S_TxPausePkts           0x04e1c4e0 /* [RO] Tx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1              0x04e1c4f0 /* [RO] Tx Q1 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2              0x04e1c500 /* [RO] Tx Q2 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3              0x04e1c510 /* [RO] Tx Q3 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4              0x04e1c520 /* [RO] Tx Q4 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5              0x04e1c530 /* [RO] Tx Q5 Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxOctets              0x04e1c540 /* [RO] Rx Packet Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts       0x04e1c560 /* [RO] Rx Under Size Packet Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPausePkts           0x04e1c570 /* [RO] Rx Pause Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets        0x04e1c580 /* [RO] Rx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets   0x04e1c590 /* [RO] Rx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets  0x04e1c5a0 /* [RO] Rx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets  0x04e1c5b0 /* [RO] Rx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets 0x04e1c5c0 /* [RO] Rx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets 0x04e1c5d0 /* [RO] Rx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_RxOversizePkts        0x04e1c5e0 /* [RO] Rx Over Size Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxJabbers             0x04e1c5f0 /* [RO] Rx Jabber Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors     0x04e1c600 /* [RO] Rx Alignment Error Counter */
+#define BCHP_SWITCH_CORE_S_RxFCSErrors           0x04e1c610 /* [RO] Rx FCS Error Counter */
+#define BCHP_SWITCH_CORE_S_RxGoodOctets          0x04e1c620 /* [RO] Rx Good Packet Octet Counter */
+#define BCHP_SWITCH_CORE_S_RxDropPkts            0x04e1c640 /* [RO] Rx Drop Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts         0x04e1c650 /* [RO] Rx Unicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts       0x04e1c660 /* [RO] Rx Multicast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts       0x04e1c670 /* [RO] Rx Broadcast Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxSAChanges           0x04e1c680 /* [RO] Rx SA Change Counter */
+#define BCHP_SWITCH_CORE_S_RxFragments           0x04e1c690 /* [RO] Rx Fragment Counter */
+#define BCHP_SWITCH_CORE_S_RxJumboPkt            0x04e1c6a0 /* [RO] Jumbo Packet Counter */
+#define BCHP_SWITCH_CORE_S_RxSymblErr            0x04e1c6b0 /* [RO] Rx Symbol Error Counter */
+#define BCHP_SWITCH_CORE_S_InRangeErrCount       0x04e1c6c0 /* [RO] InRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount      0x04e1c6d0 /* [RO] OutRangeErrCount Counter */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT         0x04e1c6e0 /* [RO] EEE Low-Power Idle Event Registers */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION      0x04e1c6f0 /* [RO] EEE Low-Power Idle Duration Registers */
+#define BCHP_SWITCH_CORE_S_RxDiscard             0x04e1c700 /* [RO] Rx Discard Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6              0x04e1c720 /* [RO] Tx Q6 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7              0x04e1c730 /* [RO] Tx Q7 Packet Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets        0x04e1c740 /* [RO] Tx 64 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets   0x04e1c750 /* [RO] Tx 65 to 127 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets  0x04e1c760 /* [RO] Tx 128 to 255 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets  0x04e1c770 /* [RO] Tx 256 to 511 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets 0x04e1c780 /* [RO] Tx 512 to 1023 Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets 0x04e1c790 /* [RO] Tx 1024 to MaxPkt Bytes Octets Counter */
+#define BCHP_SWITCH_CORE_LPDET_CFG               0x04e1c800 /* [RW] Loop Detection Configuration RegistersNot2Release */
+#define BCHP_SWITCH_CORE_DF_TIMER                0x04e1c808 /* [RW] Discovery Frame Timer RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LED_PORTMAP             0x04e1c80c /* [RO] LED Waming Portmap RegistersNot2Release */
+#define BCHP_SWITCH_CORE_MODULE_ID0              0x04e1c814 /* [RO] Module ID 0 RegistersNot2Release */
+#define BCHP_SWITCH_CORE_MODULE_ID1              0x04e1c82c /* [RO] Module ID 1 RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LPDET_SA                0x04e1c844 /* [RW] Loop Detect Frame SA RegistersNot2Release */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0        0x04e1c880 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1        0x04e1c890 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_BPM_CTRL                0x04e1cc00 /* [RW] BPM Power Switching Control Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL        0x04e1cc04 /* [RW] BPM Power Switching SW Override Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG        0x04e1cc08 /* [RW] PSM_VDD Timing Parameter Configuration Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG         0x04e1cc10 /* [RW] PSM_VDD Switching Threshold Configuration Register Not2Release */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL      0x04e1cc20 /* [RW] BUFCON Row Status Valid Mask SW Override Control Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_STS                 0x04e1cc30 /* [RO] BPM Status Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL        0x04e1cc40 /* [RW] BPM PDA Switching SW Override Control Register Not2Release */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG         0x04e1cc48 /* [RW] BPM PDA Switching Timeout Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG      0x04e1cc50 /* [RW] BPM PDA Switching Setup Time Register Not2Release */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG       0x04e1cc58 /* [RW] BPM PDA Switching Hold Time Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0          0x04e1cc60 /* [RO] Packet Buffer Block 0 Valid Buffer Count Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1          0x04e1cc68 /* [RO] Packet Buffer Block 1 Valid Buffer Count Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2          0x04e1cc70 /* [RO] Packet Buffer Block 2 Valid Buffer Count Register Not2Release */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG            0x04e1cc78 /* [RW] Recycling Check Pulse Period Counter Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL     0x04e1cc80 /* [RW] PBB Powerdown Monitor Control Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0         0x04e1cca0 /* [RO] PBB Powerdown Time Monitor 0 Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1         0x04e1ccc0 /* [RO] PBB Powerdown Time Monitor 1 Register Not2Release */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2         0x04e1cce0 /* [RO] PBB Powerdown Time Monitor 2 Register Not2Release */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0          0x04e1cd80 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1          0x04e1cd90 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0             0x04e24400 /* [RW] Traffic Remarking Control 0 Register */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1             0x04e24410 /* [RW] Traffic Remarking Control 1 Register */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2             0x04e24420 /* [RW] Traffic Remarking Control 2 Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0 0x04e24440 /* [RW] Port 0 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1 0x04e24460 /* [RW] Port 1 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2 0x04e24480 /* [RW] Port 2 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3 0x04e244a0 /* [RW] Port 3 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4 0x04e244c0 /* [RW] Port 4 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5 0x04e244e0 /* [RW] Port 5 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7 0x04e24520 /* [RW] Port 7 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP 0x04e24540 /* [RW] Port 8 Egress TC to PCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0 0x04e24580 /* [RW] Port 0 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1 0x04e245a0 /* [RW] Port 1 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2 0x04e245c0 /* [RW] Port 2 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3 0x04e245e0 /* [RW] Port 3 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4 0x04e24600 /* [RW] Port 4 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5 0x04e24620 /* [RW] Port 5 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7 0x04e24660 /* [RW] Port 7 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP 0x04e24680 /* [RW] Port 8 Egress TC to CPCP mapping Register */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0        0x04e246c0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1        0x04e246d0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL             0x04e24800 /* [RW] EEE Enable Control Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT          0x04e24808 /* [RO] EEE Low Power Assert Status Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE        0x04e24810 /* [RO] EEE Low Power Indicate Status Registers */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL      0x04e24818 /* [RO] EEE Receiving Idle Symbols Status Registers */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE 0x04e24820 /* [RW] EEE LPI Symbol Transmit Disable Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER      0x04e24830 /* [RW] EEE Pipeline Delay Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0    0x04e24840 /* [RW] EEE Port 0 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1    0x04e24850 /* [RW] EEE Port 1 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2    0x04e24860 /* [RW] EEE Port 2 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3    0x04e24870 /* [RW] EEE Port 3 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4    0x04e24880 /* [RW] EEE Port 4 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5    0x04e24890 /* [RW] EEE Port 5 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7    0x04e248b0 /* [RW] EEE Port 7 Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP   0x04e248c0 /* [RW] EEE Port 8(IMP) Sleep Delay Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0    0x04e248d0 /* [RW] EEE Port 0 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1    0x04e248e0 /* [RW] EEE Port 1 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2    0x04e248f0 /* [RW] EEE Port 2 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3    0x04e24900 /* [RW] EEE Port 3 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4    0x04e24910 /* [RW] EEE Port 4 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5    0x04e24920 /* [RW] EEE Port 5 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7    0x04e24940 /* [RW] EEE Port 7 Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP   0x04e24950 /* [RW] EEE Port 8(IMP) Sleep Delay Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0   0x04e24960 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1   0x04e24970 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2   0x04e24980 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3   0x04e24990 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4   0x04e249a0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5   0x04e249b0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7   0x04e249d0 /* [RW] EEE Port 7 Minimum Low-Power Duration Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP  0x04e249e0 /* [RW] EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0   0x04e249f0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1   0x04e24a00 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2   0x04e24a10 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3   0x04e24a20 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4   0x04e24a30 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5   0x04e24a40 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7   0x04e24a60 /* [RW] EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP  0x04e24a70 /* [RW] EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0     0x04e24a80 /* [RW] EEE Port 0 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1     0x04e24a88 /* [RW] EEE Port 1 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2     0x04e24a90 /* [RW] EEE Port 2 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3     0x04e24a98 /* [RW] EEE Port 3 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4     0x04e24aa0 /* [RW] EEE Port 4 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5     0x04e24aa8 /* [RW] EEE Port 5 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7     0x04e24ab8 /* [RW] EEE Port 7 Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8     0x04e24ac0 /* [RW] EEE Port 8(IMP) Wake Transition Timer - 1G Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0     0x04e24ac8 /* [RW] EEE Port 0 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1     0x04e24ad0 /* [RW] EEE Port 1 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2     0x04e24ad8 /* [RW] EEE Port 2 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3     0x04e24ae0 /* [RW] EEE Port 3 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4     0x04e24ae8 /* [RW] EEE Port 4 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5     0x04e24af0 /* [RW] EEE Port 5 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7     0x04e24b00 /* [RW] EEE Port 7 Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP    0x04e24b08 /* [RW] EEE Port 8(IMP) Wake Transition Timer - 100M Registers */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH         0x04e24b10 /* [RW] EEE Global Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0       0x04e24b18 /* [RW] EEE TXQ 0 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1       0x04e24b20 /* [RW] EEE TXQ 1 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2       0x04e24b28 /* [RW] EEE TXQ 2 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3       0x04e24b30 /* [RW] EEE TXQ 3 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4       0x04e24b38 /* [RW] EEE TXQ 4 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5       0x04e24b40 /* [RW] EEE TXQ 5 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL            0x04e24b48 /* [RW] EEE PHY Control Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6       0x04e24b4c /* [RW] EEE TXQ 6 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7       0x04e24b54 /* [RW] EEE TXQ 7 Congestion Threshold Registers */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0      0x04e24b6c /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1      0x04e24b80 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_DEBUG               0x04e24b9c /* [RW] EEE Debug Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER      0x04e24ba0 /* [RW] EEE Link Delay Timer Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_EEE_STATE               0x04e24bb0 /* [RO] EEE Control Policy State Registers(Not2Release) */
+#define BCHP_SWITCH_CORE_RED_CONTROL             0x04e25400 /* [RW] RED Control Register */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE    0x04e25408 /* [RW] RED Table Configuration Register */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS       0x04e25410 /* [RW] RED Egress Bypass Register */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL         0x04e25418 /* [RW] RED AQD Control Register */
+#define BCHP_SWITCH_CORE_RED_EXPONENT            0x04e25420 /* [RW] RED AQD Weighted Factor Register */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB     0x04e25428 /* [RW] RED Drop Add to MIB Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT     0x04e25440 /* [RW] Default RED profile Register */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0         0x04e25450 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1         0x04e25460 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_RED_PROFILE0            0x04e25480 /* [RW] RED profile 0 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE1            0x04e25490 /* [RW] RED profile 1 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE2            0x04e254a0 /* [RW] RED profile 2 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE3            0x04e254b0 /* [RW] RED profile 3 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE4            0x04e254c0 /* [RW] RED profile 4 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE5            0x04e254d0 /* [RW] RED profile 5 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE6            0x04e254e0 /* [RW] RED profile 6 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE7            0x04e254f0 /* [RW] RED profile 7 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE8            0x04e25500 /* [RW] RED profile 8 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE9            0x04e25510 /* [RW] RED profile 9 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE10           0x04e25520 /* [RW] RED profile 10 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE11           0x04e25530 /* [RW] RED profile 11 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE12           0x04e25540 /* [RW] RED profile 12 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE13           0x04e25550 /* [RW] RED profile 13 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE14           0x04e25560 /* [RW] RED profile 14 Register */
+#define BCHP_SWITCH_CORE_RED_PROFILE15           0x04e25570 /* [RW] RED profile 15 Register */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST       0x04e255b0 /* [RW] RED Drop Counter Reset Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0    0x04e255c0 /* [RO] PORT 0 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1    0x04e255d0 /* [RO] PORT 1 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2    0x04e255e0 /* [RO] PORT 2 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3    0x04e255f0 /* [RO] PORT 3 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4    0x04e25600 /* [RO] PORT 4 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5    0x04e25610 /* [RO] PORT 5 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7    0x04e25630 /* [RO] PORT 7 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP   0x04e25640 /* [RO] PORT 8 RED Packet Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0   0x04e25680 /* [RO] PORT 0 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1   0x04e256a0 /* [RO] PORT 1 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2   0x04e256c0 /* [RO] PORT 2 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3   0x04e256e0 /* [RO] PORT 3 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4   0x04e25700 /* [RO] PORT 4 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5   0x04e25720 /* [RO] PORT 5 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7   0x04e25760 /* [RO] PORT 7 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP  0x04e25780 /* [RO] PORT 8 RED Byte Drop Counter Register */
+#define BCHP_SWITCH_CORE_CFP_ACC                 0x04e28000 /* [RW] CFP Access Registers */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL   0x04e28010 /* [RW] CFP RATE METER Global Control Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA0               0x04e28040 /* [RW] CFP TCAM Data 0 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA1               0x04e28050 /* [RW] CFP TCAM Data 1 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA2               0x04e28060 /* [RW] CFP TCAM Data 2 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA3               0x04e28070 /* [RW] CFP TCAM Data 3 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA4               0x04e28080 /* [RW] CFP TCAM Data 4 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA5               0x04e28090 /* [RW] CFP TCAM Data 5 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA6               0x04e280a0 /* [RW] CFP TCAM Data 6 Registers */
+#define BCHP_SWITCH_CORE_CFP_DATA7               0x04e280b0 /* [RW] CFP TCAM Data 7 Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK0               0x04e280c0 /* [RW] CFP TCAM Mask 0  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK1               0x04e280d0 /* [RW] CFP TCAM Mask 1  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK2               0x04e280e0 /* [RW] CFP TCAM Mask 2  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK3               0x04e280f0 /* [RW] CFP TCAM Mask 3  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK4               0x04e28100 /* [RW] CFP TCAM Mask 4  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK5               0x04e28110 /* [RW] CFP TCAM Mask 5  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK6               0x04e28120 /* [RW] CFP TCAM Mask 6  Registers */
+#define BCHP_SWITCH_CORE_CFP_MASK7               0x04e28130 /* [RW] CFP TCAM Mask 7  Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0           0x04e28140 /* [RW] CFP Action/Policy Data 0 Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1           0x04e28150 /* [RW] CFP Action/Policy Data 1 Registers */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2           0x04e28160 /* [RW] CFP Action/Policy Data 2 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER0             0x04e28180 /* [RW] CFP RATE METER DATA 0 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER1             0x04e28190 /* [RW] CFP RATE METER DATA 1 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER2             0x04e281a0 /* [RW] CFP RATE METER DATA 2 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER3             0x04e281b0 /* [RW] CFP RATE METER DATA 3 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER4             0x04e281c0 /* [RW] CFP RATE METER DATA 4 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER5             0x04e281d0 /* [RW] CFP RATE METER DATA 5 Registers */
+#define BCHP_SWITCH_CORE_RATE_METER6             0x04e281e0 /* [RW] CFP RATE METER DATA 6 Registers */
+#define BCHP_SWITCH_CORE_TC2COLOR                0x04e281f0 /* [RW] TC to COLOR Mapping Registers */
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR         0x04e28200 /* [RW] Policer Green color statistic counter */
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR        0x04e28210 /* [RW] Policer Yellow color statistic counter */
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR           0x04e28220 /* [RW] Policer RED color statistic counter */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL       0x04e28280 /* [RW] TCAM BIST Control Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS        0x04e28290 /* [RO] TCAM BIST Status Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS 0x04e282a0 /* [RO] TCAM Test Compare Status Registers (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0          0x04e282c0 /* [RW] Spare 0 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1          0x04e282d0 /* [RW] Spare 1 Register (Not2Release) */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG             0x04e28400 /* [RW] CFP Control Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0           0x04e28440 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1           0x04e28444 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2           0x04e28448 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3           0x04e2844c /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4           0x04e28450 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5           0x04e28454 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6           0x04e28458 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7           0x04e2845c /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8           0x04e28460 /* [RW] UDFs of slice 0 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0           0x04e28480 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1           0x04e28484 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2           0x04e28488 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3           0x04e2848c /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4           0x04e28490 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5           0x04e28494 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6           0x04e28498 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7           0x04e2849c /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8           0x04e284a0 /* [RW] UDFs of slice 1 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0           0x04e284c0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1           0x04e284c4 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2           0x04e284c8 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3           0x04e284cc /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4           0x04e284d0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5           0x04e284d4 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6           0x04e284d8 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7           0x04e284dc /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8           0x04e284e0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0           0x04e28500 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1           0x04e28504 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2           0x04e28508 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3           0x04e2850c /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4           0x04e28510 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5           0x04e28514 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6           0x04e28518 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7           0x04e2851c /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8           0x04e28520 /* [RW] UDFs of slice 0 for IPv6 packet Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0           0x04e28540 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1           0x04e28544 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2           0x04e28548 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3           0x04e2854c /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4           0x04e28550 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5           0x04e28554 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6           0x04e28558 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7           0x04e2855c /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8           0x04e28560 /* [RW] UDFs of slice 1 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0           0x04e28580 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1           0x04e28584 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2           0x04e28588 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3           0x04e2858c /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4           0x04e28590 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5           0x04e28594 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6           0x04e28598 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7           0x04e2859c /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8           0x04e285a0 /* [RW] UDFs of slice 2 for IPv6 Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0           0x04e285c0 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1           0x04e285c4 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2           0x04e285c8 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3           0x04e285cc /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4           0x04e285d0 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5           0x04e285d4 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6           0x04e285d8 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7           0x04e285dc /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8           0x04e285e0 /* [RW] UDFs of slice 0 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0           0x04e28600 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1           0x04e28604 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2           0x04e28608 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3           0x04e2860c /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4           0x04e28610 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5           0x04e28614 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6           0x04e28618 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7           0x04e2861c /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8           0x04e28620 /* [RW] UDFs of slice 1 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0           0x04e28640 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1           0x04e28644 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2           0x04e28648 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3           0x04e2864c /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4           0x04e28650 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5           0x04e28654 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6           0x04e28658 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7           0x04e2865c /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8           0x04e28660 /* [RW] UDFs of slice 2 for none-IP Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0          0x04e28680 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1          0x04e28684 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2          0x04e28688 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3          0x04e2868c /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4          0x04e28690 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5          0x04e28694 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6          0x04e28698 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7          0x04e2869c /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8          0x04e286a0 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9          0x04e286a4 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10         0x04e286a8 /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11         0x04e286ac /* [RW] UDFs for IPv6 Chain Rule Registers */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG             0x04e38000 /* [RW] CPU OTP Control RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG            0x04e38010 /* [RW] CPU OTP Address RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_STS_REG             0x04e38018 /* [RO] CPU OTP Status RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_WR_DATA             0x04e38020 /* [RW] CPU OTP Write Data RegistersNot2Release */
+#define BCHP_SWITCH_CORE_OTP_RD_DATA             0x04e38030 /* [RO] CPU OTP Read Data RegistersNot2Release */
+#define BCHP_SWITCH_CORE_IO_SR_CTL               0x04e38080 /* [RW] I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0              0x04e38090 /* [RW] I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2              0x04e380b0 /* [RW] I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL          0x04e380c0 /* [RW] GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0         0x04e380d0 /* [RW] GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1         0x04e380e0 /* [RW] GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0      0x04e38100 /* [RW] Spare 0 Register (Not2Release)Not2Release */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1      0x04e38110 /* [RW] Spare 1 Register (Not2Release)Not2Release */
+
+/***************************************************************************
+ *G_PCTL_P0 - Port 0 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P0_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P0_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P0 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P0 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P0 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P0 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *G_PCTL_P1 - Port 1 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P1_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P1_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P1 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P1 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P1 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P1 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *G_PCTL_P2 - Port 2 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P2_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P2_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P2 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P2 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P2 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P2 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *G_PCTL_P3 - Port 3 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P3_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P3_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P3 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P3 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P3 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P3 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *G_PCTL_P4 - Port 4 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P4_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P4_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P4 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P4 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P4 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P4 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *G_PCTL_P5 - Port 5 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: G_PCTL_P5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_G_PCTL_P5_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_G_PCTL_P5_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: G_PCTL_P5 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_MASK              0x000000e0
+#define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_SHIFT             5
+#define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: G_PCTL_P5 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_MASK                0x0000001c
+#define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P5 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_MASK                     0x00000002
+#define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_SHIFT                    1
+#define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: G_PCTL_P5 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_MASK                     0x00000001
+#define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_SHIFT                    0
+#define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CTL_P7 - Port 7 Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CTL_P7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_CTL_P7_reserved_for_padding0_MASK         0xffffff00
+#define BCHP_SWITCH_CORE_CTL_P7_reserved_for_padding0_SHIFT        8
+
+/* SWITCH_CORE :: CTL_P7 :: G_MISTP_STATE [07:05] */
+#define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_MASK                 0x000000e0
+#define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_SHIFT                5
+#define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_DEFAULT              0x00000001
+
+/* SWITCH_CORE :: CTL_P7 :: SWITCH_RESV [04:02] */
+#define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_MASK                   0x0000001c
+#define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_SHIFT                  2
+#define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CTL_P7 :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_MASK                        0x00000002
+#define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_SHIFT                       1
+#define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_DEFAULT                     0x00000000
+
+/* SWITCH_CORE :: CTL_P7 :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_MASK                        0x00000001
+#define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_SHIFT                       0
+#define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTL_IMP - IMP Port(Port 8) Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CTL_IMP :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_CTL_IMP_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_CTL_IMP_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: CTL_IMP :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_MASK                  0x000000e0
+#define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_SHIFT                 5
+#define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: CTL_IMP :: RX_UCST_EN [04:04] */
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_MASK                   0x00000010
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_SHIFT                  4
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CTL_IMP :: RX_MCST_EN [03:03] */
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_MASK                   0x00000008
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_SHIFT                  3
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CTL_IMP :: RX_BCST_EN [02:02] */
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_MASK                   0x00000004
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_SHIFT                  2
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CTL_IMP :: TX_DIS [01:01] */
+#define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_MASK                       0x00000002
+#define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_SHIFT                      1
+#define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: CTL_IMP :: RX_DIS [00:00] */
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_SHIFT                      0
+#define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RX_GLOBAL_CTL - RX Global Control register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: SWITCH_RESV [07:07] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_MASK            0x00000080
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_SHIFT           7
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_RX_MASK [06:06] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_MASK            0x00000040
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_SHIFT           6
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_ECC_CHK [05:05] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_MASK            0x00000020
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_SHIFT           5
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_CRC_CHK [04:04] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_MASK            0x00000010
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_SHIFT           4
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RX_GLOBAL_CTL :: FMOK_LATENCY_CNT [03:00] */
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *SWMODE - Switch Mode Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SWMODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_MASK         0xffffff00
+#define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_SHIFT        8
+
+/* SWITCH_CORE :: SWMODE :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_MASK                   0x000000e0
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_SHIFT                  5
+#define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SWMODE :: NOBLKCD [04:04] */
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_MASK                       0x00000010
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_SHIFT                      4
+#define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: SWMODE :: FAST_TXDESC_RERURN [03:03] */
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_SHIFT           3
+#define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWMODE :: RTRY_LMT_DIS [02:02] */
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_MASK                  0x00000004
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_SHIFT                 2
+#define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_DEFAULT               0x00000001
+
+/* SWITCH_CORE :: SWMODE :: SW_FWDG_EN [01:01] */
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_MASK                    0x00000002
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_SHIFT                   1
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: SWMODE :: SW_FWDG_MODE [00:00] */
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_SHIFT                 0
+#define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_DEFAULT               0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_IMP - IMP Port(Port 8) States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: MII_SW_OR [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_MASK           0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_SHIFT          7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: GMII_SPEED_UP_2G [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_MASK    0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_SHIFT   6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_MASK         0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_SHIFT        5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_MASK         0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_SHIFT        4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_MASK               0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_SHIFT              2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_DEFAULT            0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_MASK          0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_SHIFT         1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_IMP :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_MASK            0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_SHIFT           0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DEBUG_REG - Debug Control Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DEBUG_REG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: DEBUG_REG :: PROBE_SOC_DMU_CLK [07:07] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_MASK          0x00000080
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_SHIFT         7
+#define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: DEBUG_REG :: DEBUG_SEL [06:01] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_MASK                  0x0000007e
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_SHIFT                 1
+#define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: DEBUG_REG :: EN_DEBUG [00:00] */
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_MASK                   0x00000001
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_SHIFT                  0
+#define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RM_PINS_DEBUG - Removed Pins Debug Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: RM_PINS_DEBUG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_MASK            0x000000f8
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_SHIFT           3
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: DIS_IMP_PIN [02:02] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_MASK            0x00000004
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_SHIFT           2
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: ENFDXFLOW_PIN [01:01] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_MASK          0x00000002
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_SHIFT         1
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: RM_PINS_DEBUG :: ENHDXFLOW_PIN [00:00] */
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_MASK          0x00000001
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_SHIFT         0
+#define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_DEFAULT       0x00000001
+
+/***************************************************************************
+ *NEW_CTRL - New Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: NEW_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: NEW_CTRL :: MC_FWD_EN [07:07] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_MASK                   0x00000080
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_SHIFT                  7
+#define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: UC_FWD_EN [06:06] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_MASK                   0x00000040
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_SHIFT                  6
+#define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: EN_AUTO_PD_WAR [05:05] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_MASK              0x00000020
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_SHIFT             5
+#define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: OVERRIDE_AUTO_PD_WAR [04:04] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_MASK        0x00000010
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_SHIFT       4
+#define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: CABLE_DIAG_LEN [03:03] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_MASK              0x00000008
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_SHIFT             3
+#define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: INRANGEERR_DISCARD [02:02] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_MASK          0x00000004
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_SHIFT         2
+#define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: OUTRANGEERR_DISCARD [01:01] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_MASK         0x00000002
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_SHIFT        1
+#define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: NEW_CTRL :: IP_MC [00:00] */
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_SHIFT                      0
+#define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_DEFAULT                    0x00000001
+
+/***************************************************************************
+ *SWITCH_CTRL - Switch Control Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SWITCH_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_1 [15:07] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_MASK            0x0000ff80
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_SHIFT           7
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII_DUMB_FWDG_EN [06:06] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_MASK         0x00000040
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_SHIFT        6
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_0 [05:04] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_MASK            0x00000030
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_SHIFT           4
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: GPHY_PLLBYPASS [03:03] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_MASK           0x00000008
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_SHIFT          3
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII3_VOL_SEL [02:02] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_MASK             0x00000004
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_SHIFT            2
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII2_VOL_SEL [01:01] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_MASK             0x00000002
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_SHIFT            1
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_DEFAULT          0x00000001
+
+/* SWITCH_CORE :: SWITCH_CTRL :: MII1_VOL_SEL [00:00] */
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_MASK             0x00000001
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_SHIFT            0
+#define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PROTECTED_SEL - Protected Port Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PROTECTED_SEL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PROTECTED_SEL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: PROTECTED_SEL :: PORT_SEL [08:00] */
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_SHIFT              0
+#define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *WAN_PORT_SEL - WAN Port select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WAN_PORT_SEL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_1 [15:10] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_MASK           0x0000fc00
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_SHIFT          10
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: EN_MAN2WAN [09:09] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_MASK              0x00000200
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_SHIFT             9
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_0 [08:08] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_MASK           0x00000100
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_SHIFT          8
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WAN_PORT_SEL :: WAN_SELECT [07:00] */
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_MASK              0x000000ff
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_SHIFT             0
+#define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PAUSE_CAP - PAUSE Capability Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV_1 [31:24] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_MASK              0xff000000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_SHIFT             24
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: EN_OVERRIDE [23:23] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_MASK                0x00800000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_SHIFT               23
+#define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV [22:18] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_MASK                0x007c0000
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_SHIFT               18
+#define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: RX_PAUSE_CAP [17:09] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_MASK               0x0003fe00
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_SHIFT              9
+#define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: PAUSE_CAP :: TX_PAUSE_CAP [08:00] */
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_SHIFT              0
+#define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RSV_MCAST_CTRL - Reserved Multicast Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_RES_MUL_LEARN [07:07] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_MASK      0x00000080
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_SHIFT     7
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: SWITCH_RESV [06:05] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_MASK           0x00000060
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_SHIFT          5
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_4 [04:04] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_MASK              0x00000010
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_SHIFT             4
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_3 [03:03] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_MASK              0x00000008
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_SHIFT             3
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_2 [02:02] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_MASK              0x00000004
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_SHIFT             2
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_1 [01:01] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_MASK              0x00000002
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_SHIFT             1
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_0 [00:00] */
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_MASK              0x00000001
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_SHIFT             0
+#define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TXQ_FLUSH_MODE - TxQ Flush Mode Control Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_NEW_BOFF_SEED [07:07] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_MASK      0x00000080
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_SHIFT     7
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LATECOl65_DROP [06:06] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_MASK     0x00000040
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_SHIFT    6
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_ECOL_TXFM_MASK [05:05] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_MASK     0x00000020
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_SHIFT    5
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_TXFM_MASK [04:04] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_MASK     0x00000010
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_SHIFT    4
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_RELOAD_ERR_PATH [03:03] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_MASK    0x00000008
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_SHIFT   3
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_FLUSH [02:02] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_MASK         0x00000004
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_SHIFT        2
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: DIS_NEW_TXDIS [01:01] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_MASK         0x00000002
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_SHIFT        1
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TXQ_FLUSH_MODE :: BYPASS_FASTTXDSC_PATH [00:00] */
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_MASK 0x00000001
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_SHIFT 0
+#define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ULF_DROP_MAP - Unicast Lookup Failed Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ULF_DROP_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: ULF_DROP_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ULF_DROP_MAP :: UNI_LOOKUP_FAIL_FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MLF_DROP_MAP - Multicast Lookup Failed Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MLF_DROP_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MLF_DROP_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: MLF_DROP_MAP :: MUL_LOOKUP_FAIL_FRW_MAP [08:00] */
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MLF_IPMC_FWD_MAP - IPMC Forward Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: MLF_IPMC_FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_SHIFT   0
+#define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RX_PAUSE_PASS - Pause pass Through for RX Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_SHIFT         9
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_0 [08:08] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_MASK          0x00000100
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_SHIFT         8
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RX_PAUSE_PASS :: RX_PAUSE_PASS [07:00] */
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_MASK          0x000000ff
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_SHIFT         0
+#define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TX_PAUSE_PASS - Pause pass Through for TX Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TX_PAUSE_PASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TX_PAUSE_PASS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TX_PAUSE_PASS :: TX_PAUSE_PASS [08:00] */
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_SHIFT         0
+#define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DIS_LEARN - Disable Learning Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DIS_LEARN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: DIS_LEARN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DIS_LEARN :: DIS_LEARN [08:00] */
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_SHIFT                 0
+#define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *SFT_LRN_CTL - Software Learning Control
+ ***************************************************************************/
+/* SWITCH_CORE :: SFT_LRN_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: SFT_LRN_CTL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: SFT_LRN_CTL :: SW_LEARN_CNTL [08:00] */
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_SHIFT           0
+#define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *LOW_POWER_EXP1 - Low Power Expansion I Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_MASK         0xfe000000
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_SHIFT        25
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_MACCLK_PORT [24:16] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_MASK     0x01ff0000
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_SHIFT    16
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_SHIFT        9
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_SYSCLK_PORT [08:00] */
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_MASK     0x000001ff
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_SHIFT    0
+#define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CTLREG_REG_SPARE - Spare Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_REG_SPARE :: CTLREG_REG_SPARE [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_SHIFT   0
+#define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P0 - Port 0 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_MASK   0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_SHIFT  7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_DEFAULT     0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P1 - Port 1 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_MASK   0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_SHIFT  7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_DEFAULT     0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P2 - Port 2 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_MASK   0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_SHIFT  7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_DEFAULT     0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P3 - Port 3 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_MASK   0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_SHIFT  7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_DEFAULT     0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P4 - Port 4 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_MASK   0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_SHIFT  7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_DEFAULT     0x00000001
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P5 - Port 5 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: GMII_SPEED_UP_2G [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *STS_OVERRIDE_GMII_P7 - Port 7 GMII Port States Override Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: GMII_SPEED_UP_2G [07:07] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_MASK 0x00000080
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_SHIFT 7
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: SW_OVERRIDE [06:06] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_MASK     0x00000040
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_SHIFT    6
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: TXFLOW_CNTL [05:05] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_MASK     0x00000020
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_SHIFT    5
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: RXFLOW_CNTL [04:04] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_MASK     0x00000010
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_SHIFT    4
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: SPEED [03:02] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_SHIFT          2
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_DEFAULT        0x00000002
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: DUPLX_MODE [01:01] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_MASK      0x00000002
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_SHIFT     1
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: LINK_STS [00:00] */
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_MASK        0x00000001
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_SHIFT       0
+#define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_CTRL - Watch Dog Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: SOFTWARE_RESET [07:07] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_MASK        0x00000080
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_SHIFT       7
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_CHIP_RST [06:06] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_MASK           0x00000040
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_SHIFT          6
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: SWITCH_RESV [05:05] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_MASK           0x00000020
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_SHIFT          5
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_SW_RESET [04:04] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_MASK           0x00000010
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_SHIFT          4
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_AUTO_RST [03:03] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_MASK           0x00000008
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_SHIFT          3
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RELOAD_EEPROM [02:02] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_MASK      0x00000004
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_SHIFT     2
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_REGFILE [01:01] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_MASK        0x00000002
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_SHIFT       1
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_SWITCH [00:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_MASK         0x00000001
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_SHIFT        0
+#define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_DEFAULT      0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT1 - Watch Dog Report 1 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT1 :: TX_PORT_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_SHIFT 0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT2 - Watch Dog Report 2 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT2 :: RX_PORT_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_SHIFT 0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WATCH_DOG_RPT3 - Watch Dog Report 3 Register(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: WATCH_DOG_RPT3 :: ARL_HUNG_INDICATOR [08:00] */
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_SHIFT   0
+#define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_FRM_CTRL - Pause Frame Detection Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_2 [07:03] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_MASK         0x000000f8
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_SHIFT        3
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_1 [02:01] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_MASK         0x00000006
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_SHIFT        1
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PAUSE_FRM_CTRL :: PAUSE_IGNORE_DA [00:00] */
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_MASK       0x00000001
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_SHIFT      0
+#define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PAUSE_ST_ADDR - PAUSE Frame DA Address
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_ST_ADDR :: PAUSE_ST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_MASK          0x000000000000
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_SHIFT         0
+#define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_DEFAULT       0x0180c2000001
+
+/***************************************************************************
+ *FAST_AGE_CTRL - Fast Ageing Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: FAST_AGE_STR_DONE [07:07] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_MASK      0x00000080
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_SHIFT     7
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_MASK            0x00000040
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_SHIFT           6
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_MCAST [05:05] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_MASK           0x00000020
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_SHIFT          5
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_SPT [04:04] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_MASK             0x00000010
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_SHIFT            4
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_VLAN [03:03] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_SHIFT           3
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_PORT [02:02] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_MASK            0x00000004
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_SHIFT           2
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_DYNAMIC [01:01] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_MASK         0x00000002
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_SHIFT        1
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_DEFAULT      0x00000001
+
+/* SWITCH_CORE :: FAST_AGE_CTRL :: EN_FAST_AGE_STATIC [00:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_MASK     0x00000001
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_SHIFT    0
+#define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_DEFAULT  0x00000000
+
+/***************************************************************************
+ *FAST_AGE_PORT - Fast Ageing Port Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_PORT :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: FAST_AGE_PORT :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_MASK            0x000000f0
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_SHIFT           4
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_PORT :: AGE_PORT [03:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_MASK               0x0000000f
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_SHIFT              0
+#define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *FAST_AGE_VID - Fast Ageing VID Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: FAST_AGE_VID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FAST_AGE_VID :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_MASK             0x0000f000
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_SHIFT            12
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FAST_AGE_VID :: AGE_VID [11:00] */
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_MASK                 0x00000fff
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_SHIFT                0
+#define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_DEFAULT              0x00000000
+
+/***************************************************************************
+ *LOW_POWER_CTRL - LOW Power Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LOW_POWER_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P8 [15:15] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_MASK              0x00008000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_SHIFT             15
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_1 [14:13] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_MASK         0x00006000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_SHIFT        13
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P5 [12:12] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_MASK              0x00001000
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_SHIFT             12
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P4 [11:11] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_MASK              0x00000800
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_SHIFT             11
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_0 [10:07] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_MASK         0x00000780
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_SHIFT        7
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_SYS [06:06] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_MASK             0x00000040
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_SHIFT            6
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: TIMER_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_MASK         0x00000020
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_SHIFT        5
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: EN_LOW_POWER [04:04] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_MASK          0x00000010
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_SHIFT         4
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: LOW_POWER_CTRL :: LOW_POWER_DIVIDER [03:00] */
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_MASK     0x0000000f
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_SHIFT    0
+#define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_DEFAULT  0x00000000
+
+/***************************************************************************
+ *TCAM_CTRL - TCAM Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: TCAM_CTRL :: EN_TCAM_CHKSUM [07:07] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_MASK             0x00000080
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_SHIFT            7
+#define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TCAM_CTRL :: SWITCH_RESV [06:00] */
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_MASK                0x0000007f
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_SHIFT               0
+#define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TCAM_CHKSUM_STS - TCAM Checksum Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ERR [15:15] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_MASK  0x00008000
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_SHIFT 15
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: SWITCH_RESV [14:08] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_MASK          0x00007f00
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_SHIFT         8
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ADDR [07:00] */
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_SHIFT 0
+#define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LNKSTS - Link Status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LNKSTS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_SHIFT        16
+
+/* SWITCH_CORE :: LNKSTS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_MASK                   0x0000fe00
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_SHIFT                  9
+#define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LNKSTS :: LNK_STS [08:00] */
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_MASK                       0x000001ff
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_SHIFT                      0
+#define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *LNKSTSCHG - Link Status Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LNKSTSCHG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: LNKSTSCHG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: LNKSTSCHG :: LNK_STS_CHG [08:00] */
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_MASK                0x000001ff
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_SHIFT               0
+#define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_DEFAULT             0x000001ff
+
+/***************************************************************************
+ *SPDSTS - Port Speed Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPDSTS :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_MASK                   0xfffc0000
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_SHIFT                  18
+#define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SPDSTS :: PORT_SPD [17:00] */
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_MASK                      0x0003ffff
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_SHIFT                     0
+#define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_DEFAULT                   0x0002aaaa
+
+/***************************************************************************
+ *DUPSTS - Duplex status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DUPSTS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_SHIFT        16
+
+/* SWITCH_CORE :: DUPSTS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_MASK                   0x0000fe00
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_SHIFT                  9
+#define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: DUPSTS :: DUP_STS [08:00] */
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_MASK                       0x000001ff
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_SHIFT                      0
+#define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_DEFAULT                    0x000001ff
+
+/***************************************************************************
+ *PAUSESTS - Pause Status Summary Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSESTS :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_MASK                 0xfffc0000
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_SHIFT                18
+#define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: PAUSESTS :: PAUSE_STS [17:00] */
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_MASK                   0x0003ffff
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_SHIFT                  0
+#define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_DEFAULT                0x00024120
+
+/***************************************************************************
+ *SRCADRCHG - Source Address Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SRCADRCHG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: SRCADRCHG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: SRCADRCHG :: SRC_ADDR_CHANGE [08:00] */
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_SHIFT           0
+#define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *LSA_PORT_P0 - Port 0 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P0 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P1 - Port 1 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P1 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P2 - Port 2 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P2 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P3 - Port 3 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P3 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P4 - Port 4 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P4 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P5 - Port 5 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P5 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P7 - Port 7 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P7 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *LSA_PORT_P8 - Port 8 Last Source Address
+ ***************************************************************************/
+/* SWITCH_CORE :: LSA_PORT_P8 :: LST_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_SHIFT                0
+#define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *BIST_STS0 - BIST Status Register 0
+ ***************************************************************************/
+/* SWITCH_CORE :: BIST_STS0 :: BIST_STS0 [47:00] */
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_MASK                  0x000000000000
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_SHIFT                 0
+#define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_DEFAULT               0x000000000000
+
+/***************************************************************************
+ *BIST_STS1 - BIST Status Register 1
+ ***************************************************************************/
+/* SWITCH_CORE :: BIST_STS1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: BIST_STS1 :: BIST_STS1 [15:00] */
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_MASK                  0x0000ffff
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_SHIFT                 0
+#define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PBPTRFIFO_0 - PBPTRFIFO Status Register 0(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P5 [47:40] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_MASK             0xff0000000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_SHIFT            40
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P4 [39:32] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_MASK             0x00ff00000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_SHIFT            32
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P3 [31:24] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_MASK             0x0000ff000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_SHIFT            24
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P2 [23:16] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_MASK             0x000000ff0000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_SHIFT            16
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P1 [15:08] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_MASK             0x00000000ff00
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_SHIFT            8
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_DEFAULT          0x000000000002
+
+/* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P0 [07:00] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_MASK             0x0000000000ff
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_SHIFT            0
+#define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_DEFAULT          0x000000000002
+
+/***************************************************************************
+ *PBPTRFIFO_1 - PBPTRFIFO Status Register 1(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_1 [31:24] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_MASK            0xff000000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_SHIFT           24
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P8 [23:16] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_MASK             0x00ff0000
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_SHIFT            16
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P7 [15:08] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_MASK             0x0000ff00
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_SHIFT            8
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_0 [07:00] */
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_SHIFT           0
+#define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_PIN_STATUS - Strap Pin Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: STRAP_PIN_STATUS :: STRAP_VALUE_VECTOR [31:00] */
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_SHIFT 0
+#define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_DEFAULT 0x000003f8
+
+/***************************************************************************
+ *DIRECT_INPUT_CTRL_VALUE - Direct Input Control Value Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: SWITCH_RESV [31:02] */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_MASK  0xfffffffc
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_SHIFT 2
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: DIRECT_INPUT_CTRL_VALUE [01:00] */
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_MASK 0x00000003
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_SHIFT 0
+#define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_STATUS - Reset Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RESET_STATUS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_1 [15:11] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_SHIFT          11
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SOC_BOOT_DN [10:10] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_MASK             0x00000400
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_SHIFT            10
+#define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SW_CORE_RST_STS [09:09] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_MASK         0x00000200
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_SHIFT        9
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SW_REG_RST_STS [08:08] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_MASK          0x00000100
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_SHIFT         8
+#define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_0 [07:06] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_SHIFT          6
+#define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SD_RST_STS [05:05] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_MASK              0x00000020
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_SHIFT             5
+#define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: SPHY_RST_STS [04:04] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_MASK            0x00000010
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_SHIFT           4
+#define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RESET_STATUS :: QPHY_RST_STS [03:00] */
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_MASK            0x0000000f
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_SHIFT           0
+#define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ENG_DET_STS - PHY Energy Detect Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_STS :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: ENG_DET_STS :: ENG_DET_STS [07:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_MASK              0x000000ff
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_SHIFT             0
+#define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *ENG_DET_STS_CHG - PHY Energy Detect Status Change Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_STS_CHG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ENG_DET_STS_CHG :: ENG_DET_STS_CHG [07:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_SHIFT     0
+#define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_DEFAULT   0x00000000
+
+/***************************************************************************
+ *STREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: STREG_REG_SPARE0 :: STREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: STREG_REG_SPARE1 :: STREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GMNGCFG - Global Management Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: GMNGCFG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: GMNGCFG :: FRM_MNGP [07:06] */
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_MASK                     0x000000c0
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_SHIFT                    6
+#define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: SWITCH_RESV [05:02] */
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_MASK                  0x0000003c
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_SHIFT                 2
+#define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: RXBPDU_EN [01:01] */
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_MASK                    0x00000002
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_SHIFT                   1
+#define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: GMNGCFG :: RST_MIB_CNT [00:00] */
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IMP0_PRT_ID - IMP/IMP0 Port ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP0_PRT_ID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: IMP0_PRT_ID :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_MASK              0x000000f0
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_SHIFT             4
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: IMP0_PRT_ID :: IMP0_PRT_ID [03:00] */
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_SHIFT             0
+#define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_DEFAULT           0x00000008
+
+/***************************************************************************
+ *IMP1_PRT_ID - IMP1 Port ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP1_PRT_ID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: IMP1_PRT_ID :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_MASK              0x000000f0
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_SHIFT             4
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: IMP1_PRT_ID :: IMP1_PRT_ID [03:00] */
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_SHIFT             0
+#define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_DEFAULT           0x00000005
+
+/***************************************************************************
+ *BRCM_HDR_CTRL - BRCM Header Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_MASK            0x000000f8
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_SHIFT           3
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL :: BRCM_HDR_EN [02:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_MASK            0x00000007
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_SHIFT           0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_DEFAULT         0x00000001
+
+/***************************************************************************
+ *SPTAGT - Aging Time Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPTAGT :: SWITCH_RESV [31:21] */
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_MASK                   0xffe00000
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_SHIFT                  21
+#define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: SPTAGT :: AGE_CHANGE_EN [20:20] */
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_MASK                 0x00100000
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_SHIFT                20
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: SPTAGT :: AGE_TIME [19:00] */
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_MASK                      0x000fffff
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_SHIFT                     0
+#define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_DEFAULT                   0x0000012c
+
+/***************************************************************************
+ *BRCM_HDR_CTRL2 - BRCM Header Control 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_SHIFT        9
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_0 [08:05] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_MASK         0x000001e0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_SHIFT        5
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_CTRL2 :: BRCM_HDR_EN [04:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_MASK           0x0000001f
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *IPG_SHRNK_CTRL - IPG Shrink Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IPG_SHRNK_CTRL :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_MASK           0xfffc0000
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_SHIFT          18
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: IPG_SHRNK_CTRL :: IPG_SHKCTRL [17:00] */
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_MASK           0x0003ffff
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_SHIFT          0
+#define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MIRCAPCTL - Mirror Capture Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MIRCAPCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: MIRCAPCTL :: MIR_EN [15:15] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_MASK                     0x00008000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_SHIFT                    15
+#define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: BLK_NOT_MIR [14:14] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_MASK                0x00004000
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_SHIFT               14
+#define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_1 [13:06] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_MASK              0x00003fc0
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_SHIFT             6
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_0 [05:04] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_MASK              0x00000030
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_SHIFT             4
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: MIRCAPCTL :: SMIR_CAP_PORT [03:00] */
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_MASK              0x0000000f
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_SHIFT             0
+#define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *IGMIRCTL - Ingress Mirror Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_FLTR [15:14] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_MASK                 0x0000c000
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_SHIFT                14
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_DIV_EN [13:13] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_MASK                   0x00002000
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_SHIFT                  13
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: SWITCH_RESV [12:09] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_MASK                 0x00001e00
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_SHIFT                9
+#define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRCTL :: IN_MIR_MSK [08:00] */
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IGMIRDIV - Ingress Mirror Divider Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRDIV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: IGMIRDIV :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_MASK                 0x0000fc00
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_SHIFT                10
+#define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: IGMIRDIV :: IN_MIR_DIV [09:00] */
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_MASK                  0x000003ff
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_DEFAULT               0x00000000
+
+/***************************************************************************
+ *IGMIRMAC - Ingress Mirror Mac Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IGMIRMAC :: IN_MIR_MAC [47:00] */
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_MASK                  0x000000000000
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_SHIFT                 0
+#define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_DEFAULT               0x000000000000
+
+/***************************************************************************
+ *EGMIRCTL - Egress Mirror Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRCTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_FLTR [15:14] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_MASK                0x0000c000
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_SHIFT               14
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_DIV_EN [13:13] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_MASK                  0x00002000
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_SHIFT                 13
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: SWITCH_RESV [12:09] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_MASK                 0x00001e00
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_SHIFT                9
+#define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_MSK [08:00] */
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_MASK                 0x000001ff
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_DEFAULT              0x00000000
+
+/***************************************************************************
+ *EGMIRDIV - Egress Mirror Divider Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRDIV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: EGMIRDIV :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_MASK                 0x0000fc00
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_SHIFT                10
+#define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EGMIRDIV :: OUT_MIR_DIV [09:00] */
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_MASK                 0x000003ff
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_DEFAULT              0x00000000
+
+/***************************************************************************
+ *EGMIRMAC - Egress Mirror MAC Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGMIRMAC :: OUT_MIR_MAC [47:00] */
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_MASK                 0x000000000000
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_SHIFT                0
+#define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_DEFAULT              0x000000000000
+
+/***************************************************************************
+ *MODEL_ID - Model ID Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MODEL_ID :: MODELID [31:00] */
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_SHIFT                    0
+#define BCHP_SWITCH_CORE_MODEL_ID_MODELID_DEFAULT                  0x00053012
+
+/***************************************************************************
+ *CHIP_REVID - Chip Version ID Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CHIP_REVID :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: CHIP_REVID :: REVID [07:00] */
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_MASK                     0x000000ff
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_SHIFT                    0
+#define BCHP_SWITCH_CORE_CHIP_REVID_REVID_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *HL_PRTC_CTRL - High Level Protocol Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_1 [31:19] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_MASK           0xfff80000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_SHIFT          19
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_FWD_MODE [18:18] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_MASK        0x00040000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_SHIFT       18
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_EN [17:17] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_MASK              0x00020000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_SHIFT             17
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_FWD_MODE [16:16] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_MASK    0x00010000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_SHIFT   16
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_EN [15:15] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_MASK          0x00008000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_SHIFT         15
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_FWD_MODE [14:14] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_MASK       0x00004000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_SHIFT      14
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_EN [13:13] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_MASK             0x00002000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_SHIFT            13
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_FWD_MODE [12:12] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_MASK       0x00001000
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_SHIFT      12
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_EN [11:11] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_MASK             0x00000800
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_SHIFT            11
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_FWD_MODE [10:10] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_MASK    0x00000400
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_SHIFT   10
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_EN [09:09] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_MASK          0x00000200
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_SHIFT         9
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_DIP_EN [08:08] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_MASK             0x00000100
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_SHIFT            8
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_0 [07:06] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_SHIFT          6
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPv6_FWD_MODE [05:05] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_MASK         0x00000020
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_SHIFT        5
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV6_EN [04:04] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_MASK               0x00000010
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_SHIFT              4
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV4_EN [03:03] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_MASK               0x00000008
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_SHIFT              3
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: DHCP_EN [02:02] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_SHIFT                2
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: RARP_EN [01:01] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_SHIFT                1
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: HL_PRTC_CTRL :: ARP_EN [00:00] */
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_SHIFT                 0
+#define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RST_MIB_CNT_EN - Reset MIB Counter Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RST_MIB_CNT_EN :: RST_MIB_CNT_EN [08:00] */
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_MASK        0x000001ff
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_SHIFT       0
+#define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_DEFAULT     0x000001ff
+
+/***************************************************************************
+ *IPG_SHRINK_2G_WA - IPG Shrink 2G Workaround Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: IPG_SHRINK_2G_WA :: VLD2_COND_DIS [08:00] */
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_MASK       0x000001ff
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_SHIFT      0
+#define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *BRCM_HDR_RX_DIS - Broadcom Header RX Disable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_RX_DIS :: RX_DIS [08:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_SHIFT              0
+#define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *BRCM_HDR_TX_DIS - Broadcom Header TX Disable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BRCM_HDR_TX_DIS :: TX_DIS [08:00] */
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_SHIFT              0
+#define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MNGMODE_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MNGMODE_REG_SPARE0 :: MNGMODE_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MNGMODE_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MNGMODE_REG_SPARE1 :: MNGMODE_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INT_STS - External Host Raw Interrupt Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_STS :: INT_STS [31:00] */
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_MASK                      0xffffffff
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_SHIFT                     0
+#define BCHP_SWITCH_CORE_INT_STS_INT_STS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *INT_EN - External Host Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_EN :: INT_EN [31:00] */
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_MASK                        0xffffffff
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_SHIFT                       0
+#define BCHP_SWITCH_CORE_INT_EN_INT_EN_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *SLEEP_TIMER_IMP - IMP Port(port 8) Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SLEEP_TIMER_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SLEEP_TIMER_IMP :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_MASK          0x0000e000
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SLEEP_TIMER_IMP :: IMP_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_MASK      0x00001fff
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_SHIFT     0
+#define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT7_SLEEP_TIMER - Port 7 Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_MASK        0x0000e000
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_SHIFT       13
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PORT7_SLEEP_TIMER :: PORT7_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_MASK  0x00001fff
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WAN_SLEEP_TIMER - WAN Port Sleep Timer Register
+ ***************************************************************************/
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_MASK          0x0000e000
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: WAN_SLEEP_TIMER :: WAN_SLEEP_TIMER [12:00] */
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_MASK      0x00001fff
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_SHIFT     0
+#define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT_SLEEP_STS - Port Sleep Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SLEEP_STS :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: SWITCH_RESV [07:03] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_MASK           0x000000f8
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_SHIFT          3
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: PORT7_SLEEP_STS [02:02] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_MASK       0x00000004
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_SHIFT      2
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: WAN_PORT_SLEEP_STS [01:01] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_MASK    0x00000002
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_SHIFT   1
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SLEEP_STS :: IMP_PORT_SLEEP_STS [00:00] */
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_MASK    0x00000001
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_SHIFT   0
+#define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INT_TRIGGER - Interrupt Trigger Register
+ ***************************************************************************/
+/* SWITCH_CORE :: INT_TRIGGER :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_MASK              0xfffffff8
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_SHIFT             3
+#define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: INT_CPU_DOORBELL [02:02] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_MASK         0x00000004
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_SHIFT        2
+#define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_DOORBELL [01:01] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_MASK         0x00000002
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_SHIFT        1
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_INT [00:00] */
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_MASK              0x00000001
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_SHIFT             0
+#define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *LINK_STS_INT_EN - Link Status Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LINK_STS_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LINK_STS_INT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: LINK_STS_INT_EN :: LINK_STS_INT_EN [08:00] */
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_SHIFT     0
+#define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_DEFAULT   0x000001ff
+
+/***************************************************************************
+ *ENG_DET_INT_EN - Energy Detection Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ENG_DET_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_1 [15:09] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_SHIFT        9
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_0 [08:05] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_MASK         0x000001e0
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_SHIFT        5
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ENG_DET_INT_EN :: ENG_DET_INT_EN [04:00] */
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_MASK        0x0000001f
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_SHIFT       0
+#define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LPI_STS_CHG_INT_EN - LPI Status Change Interrupt Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: LPI_STS_CHG_INT_EN [08:00] */
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *MEM_ECC_ERR_INT_STS - Memory ECC Double-Error-Detection Interrupt Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_MASK      0x0000f800
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_SHIFT     11
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TXQ_ECC_DED_INT_STS [10:10] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_MASK 0x00000400
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_SHIFT 10
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: MIB_ECC_DED_INT_STS [09:09] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_MASK 0x00000200
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_SHIFT 9
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: EVT_ECC_DED_INT_STS [08:08] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_MASK 0x00000100
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_SHIFT 8
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: STS_ECC_DED_INT_STS [07:07] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_MASK 0x00000080
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_SHIFT 7
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ACTRAT_ECC_DED_INT_STS [06:06] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_MASK 0x00000040
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_SHIFT 6
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TCS_ECC_DED_INT_STS [05:05] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_MASK 0x00000020
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_SHIFT 5
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: FM_ECC_DED_INT_STS [04:04] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_SHIFT 4
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: BT_ECC_DED_INT_STS [03:03] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_MASK 0x00000008
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_SHIFT 3
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: VL_ECC_DED_INT_STS [02:02] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_MASK 0x00000004
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_SHIFT 2
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_SCON_ECC_DED_INT_STS [01:01] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_MASK 0x00000002
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_SHIFT 1
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_ATMU_ECC_DED_INT_STS [00:00] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_MASK 0x00000001
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEM_ECC_ERR_INT_EN - Memory ECC Double-Error-Detection Interrupt Enable (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TXQ_ECC_DED_INT_EN [10:10] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_MASK 0x00000400
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_SHIFT 10
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: MIB_ECC_DED_INT_EN [09:09] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_MASK 0x00000200
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_SHIFT 9
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: EVT_ECC_DED_INT_EN [08:08] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_MASK 0x00000100
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_SHIFT 8
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: STS_ECC_DED_INT_EN [07:07] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_MASK 0x00000080
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ACTRAT_ECC_DED_INT_EN [06:06] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_MASK 0x00000040
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_SHIFT 6
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TCS_ECC_DED_INT_EN [05:05] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_MASK 0x00000020
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_SHIFT 5
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: FM_ECC_DED_INT_EN [04:04] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: BT_ECC_DED_INT_EN [03:03] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_MASK 0x00000008
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_SHIFT 3
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: VL_ECC_DED_INT_EN [02:02] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_MASK 0x00000004
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_SCON_ECC_DED_INT_EN [01:01] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_MASK 0x00000002
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_SHIFT 1
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_ATMU_ECC_DED_INT_EN [00:00] */
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_MASK 0x00000001
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PORT_EVT_ECC_ERR_STS - Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: EVT_ECC_ERR_STS [08:00] */
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_MIB_ECC_ERR_STS - Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fc00
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_SHIFT    10
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: MIB_ECC_ERR_STS [09:00] */
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_MASK 0x000003ff
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_TXQ_ECC_ERR_STS - Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: TXQ_ECC_ERR_STS [08:00] */
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PROBE_BUS_CTL - Probe Bus Control Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_DEBUG_CTL [31:24] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_MASK        0xff000000
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_SHIFT       24
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_CLK_SEL [23:16] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_MASK          0x00ff0000
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_SHIFT         16
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_DEBUG_SEL [15:08] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_MASK     0x0000ff00
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_SHIFT    8
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_PROBE_SEL [07:00] */
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_MASK     0x000000ff
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_SHIFT    0
+#define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MDC_EXTEND_CTRL - MDC Extend Clock Control Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_MASK          0x000000fe
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_SHIFT         1
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MDC_EXTEND_CTRL :: EXTENDED_MDC_EN [00:00] */
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_MASK      0x00000001
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_SHIFT     0
+#define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PPPOE_SESSION_PARSE_EN - PPPoE Session Packet Parsing Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: SWITCH_RESV [31:25] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_MASK   0xfe000000
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_SHIFT  25
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_PARSE_EN [24:16] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_MASK 0x01ff0000
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_SHIFT 16
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_ETYPE [15:00] */
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_SHIFT 0
+#define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_DEFAULT 0x00008864
+
+/***************************************************************************
+ *CTLREG_1_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_1_REG_SPARE0 :: CTLREG_1_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CTLREG_1_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CTLREG_1_REG_SPARE1 :: CTLREG_1_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GARLCFG - Global ARL Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: GARLCFG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_1 [07:03] */
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_MASK                0x000000f8
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_SHIFT               3
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: GARLCFG :: AGE_ACC [02:02] */
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_MASK                      0x00000004
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_SHIFT                     2
+#define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_0 [01:01] */
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_MASK                0x00000002
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_SHIFT               1
+#define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_DEFAULT             0x00000001
+
+/* SWITCH_CORE :: GARLCFG :: HASH_DISABLE [00:00] */
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_SHIFT                0
+#define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *BPDU_MCADDR - BPDU Multicast Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BPDU_MCADDR :: BPDU_MC_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_MASK             0x000000000000
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_SHIFT            0
+#define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_DEFAULT          0x0180c2000000
+
+/***************************************************************************
+ *MULTI_PORT_CTL - Multiport Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTI_PORT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT0_TS_EN [15:15] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_MASK          0x00008000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_SHIFT         15
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_DA_HIT_EN [14:14] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_MASK       0x00004000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_SHIFT      14
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: SWITCH_RESV [13:12] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_MASK           0x00003000
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_SHIFT          12
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL5 [11:10] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_MASK           0x00000c00
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_SHIFT          10
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL4 [09:08] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_MASK           0x00000300
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_SHIFT          8
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL3 [07:06] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_MASK           0x000000c0
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_SHIFT          6
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL2 [05:04] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_MASK           0x00000030
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_SHIFT          4
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL1 [03:02] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_MASK           0x0000000c
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_SHIFT          2
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL0 [01:00] */
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_MASK           0x00000003
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR0 - Multiport Address 0 Register (Default for TS)
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC0 - Multiport Vector 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC0 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC0 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR1 - Multiport Address 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC1 - Multiport Vector 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC1 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC1 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR2 - Multiport Address 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC2 - Multiport Vector 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC2 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC2 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR3 - Multiport Address 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC3 - Multiport Vector 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC3 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC3 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR4 - Multiport Address 4 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC4 - Multiport Vector 4 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC4 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC4 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *MULTIPORT_ADDR5 - Multiport Address 5 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_E_TYPE [63:48] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_MASK         0xffff000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_SHIFT        48
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_DEFAULT      0x0000000000000000
+
+/* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_ADDR [47:00] */
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_SHIFT          0
+#define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MPORTVEC5 - Multiport Vector 5 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MPORTVEC5 :: SWITCH_RESV [31:09] */
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_MASK                0xfffffe00
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MPORTVEC5 :: PORT_VCTR [08:00] */
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_SHIFT                 0
+#define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_DEFAULT               0x00000000
+
+/***************************************************************************
+ *ARL_BIN_FULL_CNTR - ARL Bin Full Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARL_BIN_FULL_CNTR :: ARL_BIN_FUL_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_SHIFT  0
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARL_BIN_FULL_FWD - ARL Biin Full Forward Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: Reserved [15:01] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_MASK            0x0000fffe
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_SHIFT           1
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARL_BIN_FULL_FWD :: ARL_BIN_FULL_FWD_EN [00:00] */
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_MASK 0x00000001
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLCTL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLCTL_REG_SPARE0 :: ARLCTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLCTL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLCTL_REG_SPARE1 :: ARLCTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLA_RWCTL - ARL Read/Write Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_RWCTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: ARLA_RWCTL :: ARL_STRTDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_MASK                0x00000080
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_SHIFT               7
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: IVL_SVL_SELECT [06:06] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_MASK            0x00000040
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_SHIFT           6
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: SWITCH_RESV [05:01] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_MASK               0x0000003e
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_SHIFT              1
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ARLA_RWCTL :: ARL_RW [00:00] */
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_SHIFT                   0
+#define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ARLA_MAC - MAC Address Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MAC :: MAC_ADDR_INDX [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_MASK               0x000000000000
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_DEFAULT            0x000000000000
+
+/***************************************************************************
+ *ARLA_VID - VID Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_RSRV0 [15:12] */
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_MASK           0x0000f000
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_SHIFT          12
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_INDX [11:00] */
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_MASK            0x00000fff
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY0 - ARL MAC/VID Entry 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY0 - ARL FWD Entry 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY1 - ARL MAC/VID Entry 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY1 - ARL FWD Entry 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY2 - ARL MAC/VID Entry 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY2 - ARL FWD Entry 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_MACVID_ENTRY3 - ARL MAC/VID Entry 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_MASK       0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_SHIFT      60
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_DEFAULT    0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: VID [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_MASK               0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_SHIFT              48
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: ARL_MACADDR [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_MASK       0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_DEFAULT    0x0000000000000000
+
+/***************************************************************************
+ *ARLA_FWD_ENTRY3 - ARL FWD Entry 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_MASK          0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_SHIFT         17
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_VALID [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_MASK            0x00010000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_SHIFT           16
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_STATIC [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_MASK           0x00008000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_SHIFT          15
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_AGE [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_MASK              0x00004000
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_SHIFT             14
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_PRI [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_MASK              0x00003800
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_SHIFT             11
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_CON [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_MASK              0x00000600
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_SHIFT             9
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: PORTID [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_SHIFT              0
+#define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_CTL - ARL Search Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_STDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_MASK         0x00000080
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_SHIFT        7
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: SWITCH_RESV [06:01] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_MASK            0x0000007e
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_SHIFT           1
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_VLID [00:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_MASK         0x00000001
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_SHIFT        0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_DEFAULT      0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_ADR - ARL Search Address Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADR_VALID [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_MASK    0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_SHIFT   15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADDRESS [14:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_MASK      0x00007fff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_SHIFT     0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_DEFAULT   0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_0_MACVID - ARL Search MAC/VID Result 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_MASK  0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_SHIFT 60
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_RSLT_VID_0 [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_MASK 0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_SHIFT 48
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_MACADDR_0 [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_0 - ARL Search Result 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_MASK         0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_SHIFT        17
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_VLID_0 [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_MASK 0x00010000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_SHIFT 16
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_STATIC_0 [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_MASK 0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_SHIFT 15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_AGE_0 [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_MASK 0x00004000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_SHIFT 14
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_PRI_0 [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_MASK 0x00003800
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_SHIFT 11
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARL_CON_0 [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_MASK           0x00000600
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_SHIFT          9
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: PORTID_0 [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_1_MACVID - ARL Search MAC/VID Result 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: SWITCH_RESV [63:60] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_MASK  0xf000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_SHIFT 60
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_RSLT_VID_1 [59:48] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_MASK 0x0fff000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_SHIFT 48
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_MACADDR_1 [47:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *ARLA_SRCH_RSLT_1 - ARL Search Result 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: SWITCH_RESV [31:17] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_MASK         0xfffe0000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_SHIFT        17
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_VLID_1 [16:16] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_MASK 0x00010000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_SHIFT 16
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_STATIC_1 [15:15] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_MASK 0x00008000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_SHIFT 15
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_AGE_1 [14:14] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_MASK 0x00004000
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_SHIFT 14
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_PRI_1 [13:11] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_MASK 0x00003800
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_SHIFT 11
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARL_CON_1 [10:09] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_MASK           0x00000600
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_SHIFT          9
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: PORTID_1 [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_SHIFT           0
+#define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_DEFAULT         0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_RWCTRL - VTBL Read/Write/Clear Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_STDN [07:07] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_MASK      0x00000080
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_SHIFT     7
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: SWITCH_RESV [06:02] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_MASK         0x0000007c
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_SHIFT        2
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_RW_CLR [01:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_MASK    0x00000003
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_SHIFT   0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_ADDR - VTBL Address Index Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_MASK           0x0000f000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_SHIFT          12
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ADDR :: VTBL_ADDR_INDEX [11:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_MASK       0x00000fff
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_SHIFT      0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_DEFAULT    0x00000000
+
+/***************************************************************************
+ *ARLA_VTBL_ENTRY - VTBL Entry Register
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: SWITCH_RESV [31:22] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_MASK          0xffc00000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_SHIFT         22
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MODE [21:21] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_MASK             0x00200000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_SHIFT            21
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: MSPT_INDEX [20:18] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_MASK           0x001c0000
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_SHIFT          18
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: UNTAG_MAP [17:09] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_MASK            0x0003fe00
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_SHIFT           9
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MAP [08:00] */
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_SHIFT             0
+#define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_DEFAULT           0x00000000
+
+/***************************************************************************
+ *ARLACCS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLACCS_REG_SPARE0 :: ARLACCS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARLACCS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: ARLACCS_REG_SPARE1 :: ARLACCS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEM_CTRL - Memory Debug Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: MEM_CTRL :: MEM_TYPE [07:06] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_MASK                    0x000000c0
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_SHIFT                   6
+#define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_1 [05:04] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_MASK               0x00000030
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_SHIFT              4
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_MASK               0x0000000f
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_ADDR - Memory Debug Address Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_STDN [15:15] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_MASK                    0x00008000
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_SHIFT                   15
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_RW [14:14] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_MASK                      0x00004000
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_SHIFT                     14
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: MEM_ADDR :: MEM_ADR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_MASK                     0x00003fff
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_SHIFT                    0
+#define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_0_0 - Memory Debug Data 0_0 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_0 :: MEM_DAT [63:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_0_1 - Memory Debug Data 0_1 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: MEM_DAT [15:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_1_0 - Memory Debug Data 1_0 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_0 :: MEM_DAT [63:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *MEM_DEBUG_DATA_1_1 - Memory Debug Data 1_1 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: MEM_DAT [15:00] */
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_SHIFT          0
+#define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MEM_FRM_ADDR - Frame Memory Address Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_STDN [15:15] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_MASK                0x00008000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_SHIFT               15
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_RW [14:14] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_MASK                  0x00004000
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_SHIFT                 14
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_ADR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_MASK                 0x00003fff
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_FRM_DATA0 - Frame Memory Data 1st Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA0 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA1 - Frame Memory Data 2st Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA1 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA2 - Frame Memory Data 3st Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA2 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_FRM_DATA3 - Frame Memory Data 4th Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_FRM_DATA3 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_BTM_DATA0 - Buffer Tag Memory Register 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BTM_DATA0 :: MEM_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *MEM_BTM_DATA1 - Buffer Tag Memory Register 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BTM_DATA1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MEM_BTM_DATA1 :: MEM_DATA [15:00] */
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_MASK               0x0000ffff
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_BFC_ADDR - Buffer Control Memory Address Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BFC_ADDR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: MEM_REQ [15:15] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_MASK                 0x00008000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_SHIFT                15
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: RW_CTRL [14:14] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_MASK                 0x00004000
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_SHIFT                14
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_BFC_ADDR :: BFC_ADDR [13:00] */
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_MASK                0x00003fff
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_BFC_DATA - Buffer Control Memory Data Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_BFC_DATA :: BFC_DATA [63:00] */
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *PRS_FIFO_DEBUG_CTRL - PRS_FIFO Debug Control Register(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_MASK      0x000000f0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_SHIFT     4
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: PRS_FIFO_DBG_CTRL [03:00] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_SHIFT 0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PRS_FIFO_DEBUG_DATA - PRS_FIFO Debug Data Register(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PRS_FIFO_DEBUG_DATA :: PRS_FIFO_DBG_DATA [63:00] */
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_SHIFT 0
+#define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *MEM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_REG_SPARE0 :: MEM_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MEM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_REG_SPARE1 :: MEM_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MEM_MISC_CTRL - Memory Misc Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_MISC_CTRL :: SWITCH_RESV [31:05] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_MASK            0xffffffe0
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_SHIFT           5
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: TXQ_DCM [04:04] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_MASK                0x00000010
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_SHIFT               4
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: PB_DCM [03:03] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_SHIFT                3
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: BT_DCM [02:02] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_SHIFT                2
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: ARL_DCM [01:01] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_MASK                0x00000002
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_SHIFT               1
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_MISC_CTRL :: CK_AON [00:00] */
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_DEFAULT              0x00000001
+
+/***************************************************************************
+ *MEM_TEST_CTRL0 - Memory Test Control 0 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: VL_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_MASK                 0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_SHIFT                20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL0 :: ARL_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_MASK                0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL1 - Memory Test Control 1 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: ACTRAT_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_MASK             0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_SHIFT            20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL1 :: BT_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_MASK                 0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL2 - Memory Test Control 2 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: STS_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_MASK                0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_SHIFT               20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL2 :: PB_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_MASK                 0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_SHIFT                0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL3 - Memory Test Control 3 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_1 [31:30] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_MASK         0xc0000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_SHIFT        30
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: EVT_TM [29:20] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_MASK                0x3ff00000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_SHIFT               20
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_0 [19:17] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_MASK         0x000e0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_SHIFT        17
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL3 :: TXQ_TM [16:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_MASK                0x0001ffff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL4 - Memory Test Control 4 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_1 [31:26] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_MASK         0xfc000000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_SHIFT        26
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_CHKSUM_TM [25:16] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_MASK        0x03ff0000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_SHIFT       16
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_0 [15:14] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_MASK         0x0000c000
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_SHIFT        14
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_TM [13:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_MASK               0x00003fff
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_SHIFT              0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_DEFAULT            0x00000000
+
+/***************************************************************************
+ *MEM_TEST_CTRL5 - Memory Test Control 5 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_TEST_CTRL5 :: SWITCH_RESV [31:06] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_MASK           0xffffffc0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: MEM_TEST_CTRL5 :: MIB_TM [05:00] */
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_MASK                0x0000003f
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_SHIFT               0
+#define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MEM_PSM_VDD_CTRL - Memory PSM_VDD Pin Control registerNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: SWITCH_RESV [31:22] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_MASK         0xffc00000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_SHIFT        22
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: STS_PSM_VDD [21:20] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_MASK         0x00300000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_SHIFT        20
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: ACTRAT_PSM_VDD [19:18] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_MASK      0x000c0000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_SHIFT     18
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: IMP_TXQ_PSM_VDD [17:16] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_MASK     0x00030000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_SHIFT    16
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P7_TXQ_PSM_VDD [15:14] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_MASK      0x0000c000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_SHIFT     14
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P6_TXQ_PSM_VDD [13:12] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_MASK      0x00003000
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_SHIFT     12
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P5_TXQ_PSM_VDD [11:10] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_MASK      0x00000c00
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_SHIFT     10
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P4_TXQ_PSM_VDD [09:08] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_MASK      0x00000300
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_SHIFT     8
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P3_TXQ_PSM_VDD [07:06] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_MASK      0x000000c0
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_SHIFT     6
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P2_TXQ_PSM_VDD [05:04] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_MASK      0x00000030
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_SHIFT     4
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P1_TXQ_PSM_VDD [03:02] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_SHIFT     2
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P0_TXQ_PSM_VDD [01:00] */
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_MASK      0x00000003
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_SHIFT     0
+#define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PORT0_DEBUG - PORT0 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT0_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT1_DEBUG - PORT1 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT1_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT2_DEBUG - PORT2 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT2_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT3_DEBUG - PORT3 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT3_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT4_DEBUG - PORT4 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT4_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT5_DEBUG - PORT5 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT5_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT6_DEBUG - PORT6 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT6_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT7_DEBUG - PORT7 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT7_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PORT8_DEBUG - PORT8 DEBUGNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT8_DEBUG :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *FC_DIAG_CTRL - Flowcon Diagnosis Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_DIAG_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_DIAG_CTRL :: SWITCH_RESV [15:04] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_MASK             0x0000fff0
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_DIAG_CTRL :: DIAG_FLOWCON_PORT [03:00] */
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_CTRL_MODE - Flow Control Mode Selection Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CTRL_MODE :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: FC_CTRL_MODE :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_MASK             0x000000fe
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_SHIFT            1
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_CTRL_MODE :: FC_MODE [00:00] */
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_MASK                 0x00000001
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_SHIFT                0
+#define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FC_CTRL_PORT - Flow Control Port Selection Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CTRL_PORT :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: FC_CTRL_PORT :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_MASK             0x000000f0
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_CTRL_PORT :: FC_PORT_SEL [03:00] */
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_MASK             0x0000000f
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_SHIFT            0
+#define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FC_OOB_PAUSE_EN - OOB Pause Signal Enable Register (Release2Customer)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_OOB_PAUSE_EN :: OOB_PAUSE_EN [08:00] */
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PAUSE_TIME_MAX - MAX Quantum Pause Time Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_MAX :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_MAX :: PAUSE_TIME_MAX [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_MASK        0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_SHIFT       0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_DEFAULT     0x00008000
+
+/***************************************************************************
+ *PAUSE_TIME_MIN - MIN Quantum Pause Time Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_MIN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_MIN :: PAUSE_TIME_MIN [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_MASK        0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_SHIFT       0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_DEFAULT     0x00000400
+
+/***************************************************************************
+ *PAUSE_TIME_RESET_THD - Quantum Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_MASK     0x0000f800
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_SHIFT    11
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: PAUSE_TIME_RESET_THD [10:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_DEFAULT 0x00000100
+
+/***************************************************************************
+ *PAUSE_TIME_UPDATE_PERIOD - Quantum Pause Update Period Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: PAUSE_TIME_UPDATE_PERIOD [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_DEFAULT 0x00001000
+
+/***************************************************************************
+ *PAUSE_TIME_DEFAULT - Default Quantum Pause Time Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: PAUSE_TIME_DEFAULT [15:00] */
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_SHIFT 0
+#define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_DEFAULT 0x00001000
+
+/***************************************************************************
+ *FC_MCAST_DROP_CTRL - Multicast Drop Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: MCAST_PARTIAL_DROP_EN [08:00] */
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *FC_PAUSE_DROP_CTRL - Pause/Drop Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: QUEUE_BASED_PAUSE_EN [12:12] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_MASK 0x00001000
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_SHIFT 12
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TOTAL_PAUSE_EN [11:11] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_MASK 0x00000800
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TXQ_PAUSE_EN [10:10] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_MASK 0x00000400
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_SHIFT 10
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TOTAL_PAUSE_EN [09:09] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_MASK 0x00000200
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_SHIFT 9
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TXQ_PAUSE_EN [08:08] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_MASK 0x00000100
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_SHIFT 8
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_PAUSE_EN [07:07] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_MASK 0x00000080
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_PAUSE_EN [06:06] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_MASK   0x00000040
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_SHIFT  6
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_DROP_EN [05:05] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_MASK        0x00000020
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_SHIFT       5
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_DROP_EN [04:04] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_MASK  0x00000010
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_DROP_EN [03:03] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_MASK    0x00000008
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_SHIFT   3
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_BASED_CTRL_EN [02:02] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_MASK  0x00000004
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_QUANTUM_CTRL_EN [01:01] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_MASK 0x00000002
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_SHIFT 1
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_BASED_CTRL_EN [00:00] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_MASK  0x00000001
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FC_TXQ_THD_PAUSE_OFF - TXQ Pause Off Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_MASK     0x0000f800
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_SHIFT    11
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: TXQ_THD_PAUSE_OFF [10:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_DEFAULT 0x00000008
+
+/***************************************************************************
+ *FC_RX_RUNOFF - RX-Based Run-Off Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_RUNOFF :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_RX_RUNOFF :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_RX_RUNOFF :: RX_RUN_OFF_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_DEFAULT       0x00000013
+
+/***************************************************************************
+ *FC_RX_RSV_THD - RX-Based Reserved Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_RSV_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_RSV_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_RX_RSV_THD :: RX_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_DEFAULT          0x0000000a
+
+/***************************************************************************
+ *FC_RX_HYST_THD - RX-Based Hysteresis Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_HYST_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_HYST_THD :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_SHIFT          11
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FC_RX_HYST_THD :: RX_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_DEFAULT        0x00000014
+
+/***************************************************************************
+ *FC_RX_MAX_PTR - RX-Based Maximum Buffer Remap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: EN_REMAP [15:15] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_MASK               0x00008000
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_SHIFT              15
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: SWITCH_RESV [14:11] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_MASK            0x00007800
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_RX_MAX_PTR :: MAXBUF_REMAP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_DEFAULT    0x000001ea
+
+/***************************************************************************
+ *FC_SPARE_ZERO_REG - Flow Control Spare Zero Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_SPARE_ZERO_REG :: SPARE_ZERO [15:00] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_MASK         0x0000ffff
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_SPARE_ONE_REG - Flow Control Spare One Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_SPARE_ONE_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_SPARE_ONE_REG :: SPARE_ONE [15:00] */
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_MASK           0x0000ffff
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_DEFAULT        0x0000ffff
+
+/***************************************************************************
+ *FC_MON_TX_Q0 - Monitored TXQ 0 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q0 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q1 - Monitored TXQ 1 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q1 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q2 - Monitored TXQ 2 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q2 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q3 - Monitored TXQ 3 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q3 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q4 - Monitored TXQ 4 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q4 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q5 - Monitored TXQ 5 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q5 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q6 - Monitored TXQ 6 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q6 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_MON_TX_Q7 - Monitored TXQ 7 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_MON_TX_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_MON_TX_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_MASK             0x0000f800
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_SHIFT            11
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_MON_TX_Q7 :: MONITORED_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_MASK       0x000007ff
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q0 - Peak TXQ 0 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q0 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q1 - Peak TXQ 1 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q1 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q2 - Peak TXQ 2 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q2 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q3 - Peak TXQ 3 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q3 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q4 - Peak TXQ 4 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q4 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q5 - Peak TXQ 5 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q5 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q6 - Peak TXQ 6 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q6 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TX_Q7 - Peak TXQ 7 Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TX_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TX_Q7 :: PEAK_TXQ_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_MASK           0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *FC_PEAK_TOTAL_USED - Peak Total Used Count Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: PEAK_TOTAL_USE_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_USED - Total Used Count Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_USED :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_USED :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_MASK            0x0000f800
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_SHIFT           11
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: FC_TOTAL_USED :: TOTAL_USE_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_SHIFT         0
+#define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *FC_PEAK_RX_CNT - Peak RX Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_MASK           0x0000f800
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_SHIFT          11
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: FC_PEAK_RX_CNT :: PEAK_RXBUF_CNT [10:00] */
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *FC_LINK_PORTMAP - PHY Link Information Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_LINK_PORTMAP :: LINK_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_GIGA_PORTMAP - Giga Speed Information Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_GIGA_PORTMAP :: GIGA_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P0 - Port 0 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P0 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P1 - Port 1 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P1 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P2 - Port 2 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P2 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P3 - Port 3 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P3 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P4 - Port 4 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P4 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P5 - Port 5 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P5 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P7 - Port 7 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_CONG_PORTMAP_P8 - Port 8 Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_MASK   0x0000ffff
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_PAUSE_HIS - Pause History Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: FC_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: FC_PAUSE_HIS :: PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_SHIFT              0
+#define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *FC_TX_QUANTUM_PAUSE_HIS - TX Quantum Pause History Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: TX_QUANTUM_PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_RX_PAUSE_HIS - RX Based Pause History Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: FC_RX_PAUSE_HIS :: RX_PAUSE_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_MASK         0x000001ff
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_SHIFT        0
+#define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *FC_RXBUF_ERR_HIS - RX Buffer Error History Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: RXBUF_ERR_HIS [08:00] */
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_MASK       0x000001ff
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_SHIFT      0
+#define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P0 - Port 0 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P0 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P1 - Port 1 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P1 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P2 - Port 2 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P2 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P3 - Port 3 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P3 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P4 - Port 4 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P4 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P5 - Port 5 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P5 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P7 - Port 7 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TXQ_CONG_PORTMAP_P8 - Port 8 TXQ Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: TXQ_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P0 - Port 0 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P0 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P1 - Port 1 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P1 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P2 - Port 2 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P2 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P3 - Port 3 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P3 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P4 - Port 4 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P4 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P5 - Port 5 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P5 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P7 - Port 7 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_TOTAL_CONG_PORTMAP_P8 - Port 8 Total Congested PortMap Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: TOTAL_CONGEST_PORTMAP [15:00] */
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q0 - LAN Port Queue 0 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q1 - LAN Port Queue 1 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q2 - LAN Port Queue 2 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q3 - LAN Port Queue 3 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q4 - LAN Port Queue 4 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q5 - LAN Port Queue 5 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q6 - LAN Port Queue 6 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_RSV_Q7 - LAN Port Queue 7 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK    0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT   11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK    0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT   0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q0 - LAN Port Queue 0 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x0000004b
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q1 - LAN Port Queue 1 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x0000004f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q2 - LAN Port Queue 2 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x00000053
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q3 - LAN Port Queue 3 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x00000057
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q4 - LAN Port Queue 4 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x0000005b
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q5 - LAN Port Queue 5 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x0000005f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q6 - LAN Port Queue 6 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x00000063
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_HYST_Q7 - LAN Port Queue 7 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q0 - LAN Port Queue 0 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x00000097
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q1 - LAN Port Queue 1 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x0000009f
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q2 - LAN Port Queue 2 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000a7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q3 - LAN Port Queue 3 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000af
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q4 - LAN Port Queue 4 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000b7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q5 - LAN Port Queue 5 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000bf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q6 - LAN Port Queue 6 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000c7
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_PAUSE_Q7 - LAN Port Queue 7 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q0 - LAN Port Queue 0 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q1 - LAN Port Queue 1 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q2 - LAN Port Queue 2 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q3 - LAN Port Queue 3 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q4 - LAN Port Queue 4 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q5 - LAN Port Queue 5 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q6 - LAN Port Queue 6 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_LAN_TXQ_THD_DROP_Q7 - LAN Port Queue 7 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK  0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q0 - LAN Port Queue 0 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q1 - LAN Port Queue 1 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q2 - LAN Port Queue 2 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q3 - LAN Port Queue 3 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q4 - LAN Port Queue 4 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q5 - LAN Port Queue 5 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q6 - LAN Port Queue 6 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_HYST_Q7 - LAN Port Queue 7 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x0000038f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q0 - LAN Port Queue 0 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x0000040f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q1 - LAN Port Queue 1 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x00000417
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q2 - LAN Port Queue 2 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x0000041f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q3 - LAN Port Queue 3 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x00000427
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q4 - LAN Port Queue 4 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x0000042f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q5 - LAN Port Queue 5 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x00000437
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q6 - LAN Port Queue 6 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_PAUSE_Q7 - LAN Port Queue 7 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q0 - LAN Port Queue 0 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x0000058f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q1 - LAN Port Queue 1 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x00000597
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q2 - LAN Port Queue 2 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x0000059f
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q3 - LAN Port Queue 3 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005a7
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q4 - LAN Port Queue 4 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005af
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q5 - LAN Port Queue 5 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005b7
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q6 - LAN Port Queue 6 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005bf
+
+/***************************************************************************
+ *FC_LAN_TOTAL_THD_DROP_Q7 - LAN Port Queue 7 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *P0_DEBUG_MUX - P0 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P0_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P1_DEBUG_MUX - P1 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P1_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P2_DEBUG_MUX - P2 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P2_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P3_DEBUG_MUX - P3 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P3_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P4_DEBUG_MUX - P4 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P4_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P5_DEBUG_MUX - P5 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P5_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *P6_DEBUG_MUX - P6 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: P6_DEBUG_MUX :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *DEBUG_MUX_P7 - P7 DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DEBUG_MUX_P7 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *DEBUG_MUX_IMP - IMP DEBUG MUXNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DEBUG_MUX_IMP :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_SHIFT           0
+#define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CFP_DEBUG_BUS_0 - CFP DEBUG BUS 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DEBUG_BUS_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_SHIFT         0
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_DEFAULT       0x00000021
+
+/***************************************************************************
+ *CFP_DEBUG_BUS_1 - CFP DEBUG BUS 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DEBUG_BUS_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_SHIFT         0
+#define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_DEFAULT       0x00000000
+
+/***************************************************************************
+ *WRED_DEBUG_0 - WRED DEBUG 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_DEBUG_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *WRED_DEBUG_1 - WRED DEBUG 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_DEBUG_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_SHIFT            0
+#define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TOP_MISC_DEBUG_0 - TOP MISC DEBUG 0Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TOP_MISC_DEBUG_0 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_SHIFT        0
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_DEFAULT      0x00000002
+
+/***************************************************************************
+ *TOP_MISC_DEBUG_1 - TOP MISC DEBUG 1Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TOP_MISC_DEBUG_1 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_SHIFT        0
+#define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_DEFAULT      0x00000000
+
+/***************************************************************************
+ *DIAGREG_BUFCON - DIAGREG BUFCONNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DIAGREG_BUFCON :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_SHIFT          0
+#define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_DEFAULT        0x0000fffc
+
+/***************************************************************************
+ *TESTBUS_P1588 - TESTBUS P1588Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TESTBUS_P1588 :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_SHIFT           0
+#define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_DEFAULT         0x00000000
+
+/***************************************************************************
+ *FLOWCON_DEBUG_BUS - FLOWCON DEBUG BUSNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FLOWCON_DEBUG_BUS :: SWITCH_RESV [31:00] */
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_SHIFT       0
+#define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_DEFAULT     0x00000000
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q0 - IMP0 Port(Port 8) Queue 0 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q1 - IMP0 Port(Port 8) Queue 1 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q2 - IMP0 Port(Port 8) Queue 2 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q3 - IMP0 Port(Port 8) Queue 3 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q4 - IMP0 Port(Port 8) Queue 4 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q5 - IMP0 Port(Port 8) Queue 5 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q6 - IMP0 Port(Port 8) Queue 6 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_RSV_Q7 - IMP0 Port(Port 8) Queue 7 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK   0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT  11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK   0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT  0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q0 - IMP0 Port(Port 8) Queue 0 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x00000063
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q1 - IMP0 Port(Port 8) Queue 1 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q2 - IMP0 Port(Port 8) Queue 2 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x0000006b
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q3 - IMP0 Port(Port 8) Queue 3 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x0000006f
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q4 - IMP0 Port(Port 8) Queue 4 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x00000073
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q5 - IMP0 Port(Port 8) Queue 5 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x00000077
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q6 - IMP0 Port(Port 8) Queue 6 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x0000007b
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_HYST_Q7 - IMP0 Port(Port 8) Queue 7 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x0000007f
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q0 - IMP0 Port(Port 8) Queue 0 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x000000c7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q1 - IMP0 Port(Port 8) Queue 1 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q2 - IMP0 Port(Port 8) Queue 2 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000d7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q3 - IMP0 Port(Port 8) Queue 3 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000df
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q4 - IMP0 Port(Port 8) Queue 4 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000e7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q5 - IMP0 Port(Port 8) Queue 5 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000ef
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q6 - IMP0 Port(Port 8) Queue 6 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000f7
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_PAUSE_Q7 - IMP0 Port(Port 8) Queue 7 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x000000ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q0 - IMP0 Port(Port 8) Queue 0 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q1 - IMP0 Port(Port 8) Queue 1 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q2 - IMP0 Port(Port 8) Queue 2 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q3 - IMP0 Port(Port 8) Queue 3 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q4 - IMP0 Port(Port 8) Queue 4 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q5 - IMP0 Port(Port 8) Queue 5 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q6 - IMP0 Port(Port 8) Queue 6 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TXQ_THD_DROP_Q7 - IMP0 Port(Port 8) Queue 7 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK  0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q0 - IMP0 Port(Port 8) Queue 0 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q1 - IMP0 Port(Port 8) Queue 1 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q2 - IMP0 Port(Port 8) Queue 2 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q3 - IMP0 Port(Port 8) Queue 3 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q4 - IMP0 Port(Port 8) Queue 4 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q5 - IMP0 Port(Port 8) Queue 5 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q6 - IMP0 Port(Port 8) Queue 6 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_HYST_Q7 - IMP0 Port(Port 8) Queue 7 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x000003bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q0 - IMP0 Port(Port 8) Queue 0 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x0000043f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q1 - IMP0 Port(Port 8) Queue 1 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q2 - IMP0 Port(Port 8) Queue 2 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q3 - IMP0 Port(Port 8) Queue 3 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x00000457
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q4 - IMP0 Port(Port 8) Queue 4 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q5 - IMP0 Port(Port 8) Queue 5 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x00000467
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q6 - IMP0 Port(Port 8) Queue 6 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_PAUSE_Q7 - IMP0 Port(Port 8) Queue 7 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x00000477
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q0 - IMP0 Port(Port 8) Queue 0 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x000005bf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q1 - IMP0 Port(Port 8) Queue 1 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q2 - IMP0 Port(Port 8) Queue 2 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q3 - IMP0 Port(Port 8) Queue 3 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005d7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q4 - IMP0 Port(Port 8) Queue 4 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005df
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q5 - IMP0 Port(Port 8) Queue 5 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005e7
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q6 - IMP0 Port(Port 8) Queue 6 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005ef
+
+/***************************************************************************
+ *FC_IMP0_TOTAL_THD_DROP_Q7 - IMP0 Port(Port 8) Queue 7 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005f7
+
+/***************************************************************************
+ *FC_IMP0_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: FC_IMP0_REG_SPARE0 [15:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_IMP0_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: FC_IMP0_REG_SPARE1 [15:00] */
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q0 - WAN/IMP1 Port Queue 0 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q1 - WAN/IMP1 Port Queue 1 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q2 - WAN/IMP1 Port Queue 2 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q3 - WAN/IMP1 Port Queue 3 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q4 - WAN/IMP1 Port Queue 4 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q5 - WAN/IMP1 Port Queue 5 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q6 - WAN/IMP1 Port Queue 6 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_RSV_Q7 - WAN/IMP1 Port Queue 7 Reserved Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q0 - WAN/IMP1 Port Queue 0 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x00000067
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q1 - WAN/IMP1 Port Queue 1 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x0000006b
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q2 - WAN/IMP1 Port Queue 2 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x0000006f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q3 - WAN/IMP1 Port Queue 3 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x00000073
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q4 - WAN/IMP1 Port Queue 4 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x00000077
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q5 - WAN/IMP1 Port Queue 5 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x0000007b
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q6 - WAN/IMP1 Port Queue 6 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x0000007f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_HYST_Q7 - WAN/IMP1 Port Queue 7 Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x00000083
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 - WAN/IMP1 Port Queue 0 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x000000cf
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 - WAN/IMP1 Port Queue 1 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x000000d7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 - WAN/IMP1 Port Queue 2 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000df
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 - WAN/IMP1 Port Queue 3 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000e7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 - WAN/IMP1 Port Queue 4 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000ef
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 - WAN/IMP1 Port Queue 5 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000f7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 - WAN/IMP1 Port Queue 6 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 - WAN/IMP1 Port Queue 7 Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x00000107
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q0 - WAN/IMP1 Port Queue 0 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q1 - WAN/IMP1 Port Queue 1 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q2 - WAN/IMP1 Port Queue 2 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q3 - WAN/IMP1 Port Queue 3 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q4 - WAN/IMP1 Port Queue 4 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q5 - WAN/IMP1 Port Queue 5 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q6 - WAN/IMP1 Port Queue 6 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TXQ_THD_DROP_Q7 - WAN/IMP1 Port Queue 7 DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q0 - WAN/IMP1 Port Queue 0 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q1 - WAN/IMP1 Port Queue 1 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q2 - WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q3 - WAN/IMP1 Port Queue 3 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q4 - WAN/IMP1 Port Queue 4 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q5 - WAN/IMP1 Port Queue 5 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q6 - WAN/IMP1 Port Queue 6 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_HYST_Q7 - WAN/IMP1 Port Queue 7 Total Hysteresis Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x000003c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 - WAN/IMP1 Port Queue 0 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x00000447
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 - WAN/IMP1 Port Queue 1 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x0000044f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 - WAN/IMP1 Port Queue 2 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x00000457
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 - WAN/IMP1 Port Queue 3 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x0000045f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 - WAN/IMP1 Port Queue 4 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x00000467
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 - WAN/IMP1 Port Queue 5 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x0000046f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 - WAN/IMP1 Port Queue 6 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x00000477
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 - WAN/IMP1 Port Queue 7 Total Pause Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x0000047f
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q0 - WAN/IMP1 Port Queue 0 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x000005c7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q1 - WAN/IMP1 Port Queue 1 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x000005cf
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q2 - WAN/IMP1 Port Queue 2 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x000005d7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q3 - WAN/IMP1 Port Queue 3 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005df
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q4 - WAN/IMP1 Port Queue 4 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005e7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q5 - WAN/IMP1 Port Queue 5 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005ef
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q6 - WAN/IMP1 Port Queue 6 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005f7
+
+/***************************************************************************
+ *FC_WAN_IMP1_TOTAL_THD_DROP_Q7 - WAN/IMP1 Port Queue 7 Total DROP Threshold Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005ff
+
+/***************************************************************************
+ *FC_WAN_IMP1_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: FC_WAN_IMP1_REG_SPARE0 [15:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FC_WAN_IMP1_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: FC_WAN_IMP1_REG_SPARE1 [15:00] */
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEMP_MON_CTL - Temperature Monitor Control Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: TEMP_MON_CTL :: BIAS_ADJUST [07:01] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_MASK             0x000000fe
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_SHIFT            1
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_CTL :: ADC_TEST_EN [00:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_MASK             0x00000001
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_SHIFT            0
+#define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_DEFAULT          0x00000001
+
+/***************************************************************************
+ *TEMP_MON_RESU - Temperature Monitor Result Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TEMP_MON_RESU :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_SHIFT           9
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_RESU :: TEMP_DATA [08:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_DEFAULT           0x000001ff
+
+/***************************************************************************
+ *PEAK_TEMP_MON_RESU - Peak Temperature Monitor Result Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: PEAK_TEMP_DATA [08:00] */
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_SHIFT   0
+#define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *TEMP_MON_CAL - Temperature Monitor Calibration Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_CAL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: TEMP_MON_CAL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_CAL :: TEMP_DATA_25C [08:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_SHIFT          0
+#define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_DEFAULT        0x0000015a
+
+/***************************************************************************
+ *TEMP_MON_SPEC_CTL - Temperature Monitor Special Control Registers(Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_MASK        0x000000fe
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_SHIFT       1
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: TEMP_PWRDN [00:00] */
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_MASK         0x00000001
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_SHIFT        0
+#define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxOctets_P0 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P0 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P0 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P0 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P0 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P0 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P0 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P0 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P0 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P0 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P0 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P0 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P0 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P0 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P0 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P0 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P0 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P0 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P0 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P0 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P0 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P0 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P0 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P0 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P0 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P0 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P0 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P0 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P0 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P0 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P0 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P0 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P0 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P0 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P0 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P0 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P0 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P0 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P0 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P0 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P0 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P0 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P0 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P0 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P0 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P0 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P0 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P0 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P0 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P0 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P0 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P0 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P0 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P0 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P0 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P1 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P1 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P1 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P1 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P1 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P1 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P1 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P1 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P1 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P1 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P1 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P1 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P1 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P1 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P1 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P1 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P1 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P1 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P1 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P1 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P1 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P1 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P1 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P1 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P1 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P1 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P1 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P1 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P1 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P1 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P1 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P1 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P1 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P1 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P1 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P1 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P1 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P1 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P1 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P1 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P1 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P1 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P1 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P1 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P1 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P1 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P1 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P1 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P1 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P1 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P1 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P1 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P1 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P1 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P1 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P2 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P2 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P2 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P2 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P2 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P2 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P2 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P2 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P2 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P2 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P2 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P2 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P2 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P2 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P2 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P2 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P2 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P2 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P2 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P2 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P2 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P2 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P2 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P2 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P2 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P2 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P2 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P2 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P2 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P2 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P2 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P2 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P2 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P2 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P2 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P2 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P2 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P2 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P2 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P2 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P2 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P2 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P2 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P2 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P2 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P2 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P2 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P2 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P2 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P2 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P2 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P2 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P2 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P2 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P2 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P3 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P3 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P3 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P3 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P3 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P3 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P3 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P3 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P3 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P3 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P3 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P3 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P3 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P3 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P3 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P3 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P3 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P3 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P3 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P3 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P3 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P3 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P3 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P3 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P3 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P3 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P3 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P3 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P3 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P3 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P3 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P3 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P3 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P3 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P3 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P3 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P3 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P3 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P3 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P3 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P3 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P3 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P3 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P3 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P3 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P3 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P3 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P3 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P3 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P3 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P3 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P3 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P3 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P3 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P3 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P4 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P4 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P4 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P4 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P4 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P4 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P4 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P4 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P4 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P4 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P4 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P4 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P4 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P4 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P4 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P4 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P4 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P4 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P4 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P4 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P4 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P4 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P4 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P4 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P4 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P4 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P4 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P4 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P4 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P4 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P4 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P4 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P4 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P4 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P4 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P4 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P4 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P4 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P4 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P4 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P4 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P4 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P4 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P4 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P4 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P4 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P4 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P4 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P4 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P4 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P4 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P4 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P4 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P4 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P4 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P5 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P5 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P5 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P5 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P5 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P5 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P5 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P5 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P5 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P5 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P5 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P5 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P5 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P5 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P5 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P5 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P5 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P5 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P5 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P5 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P5 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P5 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P5 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P5 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P5 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P5 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P5 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P5 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P5 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P5 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P5 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P5 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P5 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P5 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P5 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P5 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P5 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P5 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P5 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P5 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P5 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P5 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P5 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P5 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P5 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P5 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P5 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P5 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P5 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P5 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P5 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P5 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P5 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P5 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P5 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_P7 - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_P7 - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_P7 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_P7 - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_P7 - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_P7 - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxCollisions_P7 - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_P7 - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_P7 - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_P7 - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxLateCollision_P7 - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_P7 - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_P7 - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxPausePkts_P7 - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_P7 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_P7 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_P7 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_P7 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_P7 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *RxOctets_P7 - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_MASK                    0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_DEFAULT                 0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_P7 - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPausePkts_P7 - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_P7 - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_P7 - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_P7 - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_P7 - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_P7 - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_P7 - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_P7 - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxJabbers_P7 - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_P7 - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_P7 - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_P7 - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_P7 :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_P7 - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_P7 - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_P7 - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_P7 - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxSAChanges_P7 - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxFragments_P7 - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_P7 - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxSymblErr_P7 - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_P7 - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_P7 - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_P7 - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_P7 - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxDiscard_P7 - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_P7 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_P7 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_P7 - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_P7 - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_P7 - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_P7 - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_P7 - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_P7 - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_SHIFT   0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TxOctets_IMP - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: TxOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_MASK                   0x0000000000000000
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_DEFAULT                0x0000000000000000
+
+/***************************************************************************
+ *TxDropPkts_IMP - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDropPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *TxQPKTQ0_IMP - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ0_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxBroadcastPkts_IMP - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxBroadcastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxMulticastPkts_IMP - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMulticastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxUnicastPkts_IMP - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxUnicastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxCollisions_IMP - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxCollisions_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TxSingleCollision_IMP - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxSingleCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TxMultipleCollision_IMP - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxMultipleCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxDeferredTransmit_IMP - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxDeferredTransmit_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *TxLateCollision_IMP - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxLateCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TxExcessiveCollision_IMP - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxExcessiveCollision_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxFrameInDisc_IMP - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxFrameInDisc_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TxPausePkts_IMP - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPausePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *TxQPKTQ1_IMP - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ1_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ2_IMP - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ2_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ3_IMP - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ3_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ4_IMP - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ4_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ5_IMP - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ5_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *RxOctets_IMP - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_MASK                   0x0000000000000000
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_DEFAULT                0x0000000000000000
+
+/***************************************************************************
+ *RxUndersizePkts_IMP - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUndersizePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxPausePkts_IMP - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPausePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxPkts64Octets_IMP - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts64Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxPkts65to127Octets_IMP - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts65to127Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RxPkts128to255Octets_IMP - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts128to255Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts256to511Octets_IMP - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts256to511Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RxPkts512to1023Octets_IMP - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts512to1023Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_SHIFT     0
+#define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RxPkts1024toMaxPktOctets_IMP - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT  0
+#define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RxOversizePkts_IMP - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxOversizePkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RxJabbers_IMP - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJabbers_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RxAlignmentErrors_IMP - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxAlignmentErrors_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *RxFCSErrors_IMP - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFCSErrors_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxGoodOctets_IMP - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxGoodOctets_IMP :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *RxDropPkts_IMP - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDropPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxUnicastPkts_IMP - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxUnicastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RxMulticastPkts_IMP - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxMulticastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxBroadcastPkts_IMP - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxBroadcastPkts_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RxSAChanges_IMP - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSAChanges_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxFragments_IMP - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxFragments_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RxJumboPkt_IMP - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxJumboPkt_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *RxSymblErr_IMP - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxSymblErr_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *InRangeErrCount_IMP - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: InRangeErrCount_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *OutRangeErrCount_IMP - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: OutRangeErrCount_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *EEE_LPI_EVENT_IMP - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_EVENT_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *EEE_LPI_DURATION_IMP - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_DURATION_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RxDiscard_IMP - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: RxDiscard_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *TxQPKTQ6_IMP - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ6_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxQPKTQ7_IMP - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxQPKTQ7_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TxPkts64Octets_IMP - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts64Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TxPkts65to127Octets_IMP - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts65to127Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TxPkts128to255Octets_IMP - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts128to255Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts256to511Octets_IMP - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts256to511Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_MASK       0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_SHIFT      0
+#define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TxPkts512to1023Octets_IMP - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts512to1023Octets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_SHIFT     0
+#define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TxPkts1024toMaxPktOctets_IMP - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: TxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT  0
+#define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QOS_GLOBAL_CTRL - QOS Global Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P8_AGGREGATION_MODE [07:07] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_MASK  0x00000080
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_1 [06:05] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_MASK        0x00000060
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_SHIFT       5
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P5_AGGREGATION_MODE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_MASK  0x00000010
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_MASK        0x0000000f
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *QOS_1P_EN - QoS 802.1P Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_1P_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: QOS_1P_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: QOS_1P_EN :: QOS_1P_EN [08:00] */
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_SHIFT                 0
+#define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_DEFAULT               0x00000000
+
+/***************************************************************************
+ *QOS_EN_DIFFSERV - QOS DiffServ Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: QOS_EN_DIFFSERV :: QOS_EN_DIFFSERV [08:00] */
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_DEFAULT   0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P0 - Port 0 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P1 - Port 1 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P2 - Port 2 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P3 - Port 3 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P4 - Port 4 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P5 - Port 5 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_P7 - Port 7 PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI0_IMP - Port 8 (IMP) PCP to TC Map for DEI 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_MASK          0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_SHIFT         24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_MASK       0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_SHIFT      21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_DEFAULT    0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_MASK       0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_SHIFT      18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_DEFAULT    0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_MASK       0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_SHIFT      15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_DEFAULT    0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_MASK       0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_SHIFT      12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_DEFAULT    0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_MASK       0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_SHIFT      9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_DEFAULT    0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_MASK       0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_SHIFT      6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_DEFAULT    0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_MASK       0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_SHIFT      3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_MASK       0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_SHIFT      0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_DEFAULT    0x00000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP0 - DiffServ Priority Map 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP1 - DiffServ Priority Map 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP2 - DiffServ Priority Map 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *QOS_DIFF_DSCP3 - DiffServ Priority Map 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111111 [47:45] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_MASK       0xe00000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_SHIFT      45
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111110 [44:42] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_MASK       0x1c0000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_SHIFT      42
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111101 [41:39] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_MASK       0x038000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_SHIFT      39
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111100 [38:36] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_MASK       0x007000000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_SHIFT      36
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111011 [35:33] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_MASK       0x000e00000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_SHIFT      33
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111010 [32:30] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_MASK       0x0001c0000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_SHIFT      30
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111001 [29:27] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_MASK       0x000038000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_SHIFT      27
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111000 [26:24] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_MASK       0x000007000000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_SHIFT      24
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110111 [23:21] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_MASK       0x000000e00000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_SHIFT      21
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110110 [20:18] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_MASK       0x0000001c0000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_SHIFT      18
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110101 [17:15] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_MASK       0x000000038000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_SHIFT      15
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110100 [14:12] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_MASK       0x000000007000
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_SHIFT      12
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110011 [11:09] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_MASK       0x000000000e00
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_SHIFT      9
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110010 [08:06] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_MASK       0x0000000001c0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_SHIFT      6
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110001 [05:03] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_MASK       0x000000000038
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_SHIFT      3
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_DEFAULT    0x000000000000
+
+/* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110000 [02:00] */
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_MASK       0x000000000007
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_SHIFT      0
+#define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_DEFAULT    0x000000000000
+
+/***************************************************************************
+ *PID2TC - Port ID to TC Map Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PID2TC :: SWITCH_RESV [31:27] */
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_MASK                   0xf8000000
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_SHIFT                  27
+#define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: PID2TC :: PID2TC [26:00] */
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_MASK                        0x07ffffff
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_SHIFT                       0
+#define BCHP_SWITCH_CORE_PID2TC_PID2TC_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P0 - Port 0 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P1 - Port 1 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P2 - Port 2 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P3 - Port 3 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P4 - Port 4 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P5 - Port 5 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_P7 - Port 7 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_MASK             0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_SHIFT            14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_MASK             0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_SHIFT            12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_MASK             0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_SHIFT            10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_MASK             0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_SHIFT            8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_MASK             0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_SHIFT            6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_MASK             0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_SHIFT            4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_SHIFT            2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_SHIFT            0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TC_SEL_TABLE_IMP - Port 8 TC Select Table Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_7 [15:14] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_MASK            0x0000c000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_SHIFT           14
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_6 [13:12] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_MASK            0x00003000
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_SHIFT           12
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_5 [11:10] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_MASK            0x00000c00
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_SHIFT           10
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_4 [09:08] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_MASK            0x00000300
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_SHIFT           8
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_3 [07:06] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_MASK            0x000000c0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_SHIFT           6
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_2 [05:04] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_MASK            0x00000030
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_SHIFT           4
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_1 [03:02] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_MASK            0x0000000c
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_SHIFT           2
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_0 [01:00] */
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_MASK            0x00000003
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_SHIFT           0
+#define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU2COS_MAP - CPU to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: CPU2COS_MAP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_MASK              0xfffc0000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_SHIFT             18
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: EXCPT_PRCS [17:15] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_MASK               0x00038000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_SHIFT              15
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_SNOOP [14:12] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_MASK               0x00007000
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_SHIFT              12
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: PRTC_TRMNT [11:09] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_MASK               0x00000e00
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_SHIFT              9
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: SW_FLD [08:06] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_MASK                   0x000001c0
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_SHIFT                  6
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: SA_LRN [05:03] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_MASK                   0x00000038
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_SHIFT                  3
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CPU2COS_MAP :: MIRROR [02:00] */
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_MASK                   0x00000007
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_SHIFT                  0
+#define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P0 - Port 0 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P1 - Port 1 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P2 - Port 2 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P3 - Port 3 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P4 - Port 4 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P5 - Port 5 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_P7 - Port 7 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_MASK      0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_SHIFT     24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_MASK          0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_SHIFT         21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_MASK          0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_SHIFT         18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_MASK          0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_SHIFT         15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_MASK          0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_SHIFT         12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_MASK          0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_MASK          0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_SHIFT         6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_MASK          0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_SHIFT         3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_MASK          0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_SHIFT         0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TC2COS_MAP_IMP - Port 8 TC to COS Mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: BCAST_DLF_DROP_TC [31:24] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_MASK     0xff000000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_SHIFT    24
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT111_TO_QID [23:21] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_MASK         0x00e00000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_SHIFT        21
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT110_TO_QID [20:18] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_MASK         0x001c0000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_SHIFT        18
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT101_TO_QID [17:15] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_MASK         0x00038000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_SHIFT        15
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT100_TO_QID [14:12] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_MASK         0x00007000
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_SHIFT        12
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT011_TO_QID [11:09] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_MASK         0x00000e00
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_SHIFT        9
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT010_TO_QID [08:06] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_MASK         0x000001c0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_SHIFT        6
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT001_TO_QID [05:03] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_MASK         0x00000038
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_SHIFT        3
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT000_TO_QID [02:00] */
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_MASK         0x00000007
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_SHIFT        0
+#define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_DEFAULT      0x00000000
+
+/***************************************************************************
+ *QOS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_REG_SPARE0 :: QOS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *QOS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_REG_SPARE1 :: QOS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P0 - Port 0 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P1 - Port 1 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P2 - Port 2 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P3 - Port 3 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P4 - Port 4 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P5 - Port 5 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_P7 - Port 7 PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_MASK           0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_SHIFT          24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_MASK        0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_SHIFT       21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_DEFAULT     0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_MASK        0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_SHIFT       18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_DEFAULT     0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_MASK        0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_SHIFT       15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_DEFAULT     0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_MASK        0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_SHIFT       12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_DEFAULT     0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_MASK        0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_SHIFT       9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_DEFAULT     0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_MASK        0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_SHIFT       6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_DEFAULT     0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_MASK        0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_SHIFT       3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_DEFAULT     0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_MASK        0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_SHIFT       0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCP2TC_DEI1_IMP - Port 8 (IMP) PCP to TC Map for DEI 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: SWITCH_RESV [31:24] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_MASK          0xff000000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_SHIFT         24
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG111_PRI_MAP [23:21] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_MASK       0x00e00000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_SHIFT      21
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_DEFAULT    0x00000007
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG110_PRI_MAP [20:18] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_MASK       0x001c0000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_SHIFT      18
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_DEFAULT    0x00000006
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG101_PRI_MAP [17:15] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_MASK       0x00038000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_SHIFT      15
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_DEFAULT    0x00000005
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG100_PRI_MAP [14:12] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_MASK       0x00007000
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_SHIFT      12
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_DEFAULT    0x00000004
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG011_PRI_MAP [11:09] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_MASK       0x00000e00
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_SHIFT      9
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_DEFAULT    0x00000003
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG010_PRI_MAP [08:06] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_MASK       0x000001c0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_SHIFT      6
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_DEFAULT    0x00000002
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG001_PRI_MAP [05:03] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_MASK       0x00000038
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_SHIFT      3
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG000_PRI_MAP [02:00] */
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_MASK       0x00000007
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_SHIFT      0
+#define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_DEFAULT    0x00000000
+
+/***************************************************************************
+ *VLAN_CTL_P0 - PORT 0 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P0 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P0 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P1 - PORT 1 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P1 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P2 - PORT 2 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P2 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P2 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P3 - PORT 3 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P3 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P4 - PORT 4 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P4 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P4 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P5 - PORT 5 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P5 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P5 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_P7 - PORT 7 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: VLAN_CTL_P7 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_P7 :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_MASK           0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_DEFAULT        0x000001ff
+
+/***************************************************************************
+ *VLAN_CTL_IMP - PORT 8 VLAN Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTL_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: VLAN_CTL_IMP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTL_IMP :: PORT_EGRESS_EN [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_SHIFT         0
+#define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_DEFAULT       0x000001ff
+
+/***************************************************************************
+ *VLAN_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_REG_SPARE0 :: VLAN_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_SHIFT     0
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *VLAN_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_REG_SPARE1 :: VLAN_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_SHIFT     0
+#define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MAC_TRUNK_CTL - MAC Trunk Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_1 [07:04] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_MASK          0x000000f0
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_SHIFT         4
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: EN_TRUNK_LOCAL [03:03] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_MASK         0x00000008
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_SHIFT        3
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_0 [02:02] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_MASK          0x00000004
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_SHIFT         2
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: MAC_TRUNK_CTL :: HASH_SEL [01:00] */
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_MASK               0x00000003
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_SHIFT              0
+#define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *IMP0_GRP_CTL - IMP0 Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IMP0_GRP_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: IMP0_GRP_CTL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_MASK             0x0000fe00
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_SHIFT            9
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: IMP0_GRP_CTL :: IMP0_GRP_CTL [08:00] */
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_SHIFT           0
+#define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_DEFAULT         0x00000100
+
+/***************************************************************************
+ *TRUNK_GRP_CTL0 - Trunk 0 Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_GRP_CTL0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL0 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL0 :: EN_TRUNK_GRP [08:00] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_SHIFT         0
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TRUNK_GRP_CTL1 - Trunk 1 Group Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_GRP_CTL1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL1 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: TRUNK_GRP_CTL1 :: EN_TRUNK_GRP [08:00] */
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_SHIFT         0
+#define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_DEFAULT       0x00000000
+
+/***************************************************************************
+ *TRUNK_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_REG_SPARE0 :: TRUNK_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRUNK_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRUNK_REG_SPARE1 :: TRUNK_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL0 - 802.1Q VLAN Control 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_EN [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_MASK                   0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_SHIFT                  7
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_LEARN_MODE [06:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_MASK           0x00000060
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_SHIFT          5
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_DEFAULT        0x00000003
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_1 [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_MASK             0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_SHIFT            4
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1Q_VID [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_MASK             0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_SHIFT            3
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_0 [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_MASK             0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_SHIFT            2
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_OUTER [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_MASK       0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_SHIFT      1
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_INNER [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_MASK       0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_SHIFT      0
+#define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_DEFAULT    0x00000001
+
+/***************************************************************************
+ *VLAN_CTRL1 - 802.1Q VLAN Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_3 [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_MASK             0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_SHIFT            7
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_UNTAG [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_MASK      0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_SHIFT     6
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_FWDMAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_MASK     0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_SHIFT    5
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_2 [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_MASK             0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_SHIFT            4
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_UNTAG [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_MASK        0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_SHIFT       3
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_FWDMAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_MASK       0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_SHIFT      2
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_1 [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_MASK             0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_DEFAULT          0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_0 [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_MASK             0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL2 - 802.1Q VLAN Control 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_MASK               0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_SHIFT              7
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_UNTAG_MAP [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_MASK    0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_SHIFT   6
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_V_FWDMAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_MASK     0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_SHIFT    5
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_2 [04:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_MASK             0x00000018
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_SHIFT            3
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_DEFAULT          0x00000002
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: EN_MIIM_BYPASS_V_FWDMAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_MASK   0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_SHIFT  2
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_0 [01:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_MASK             0x00000003
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL3 - 802.1Q VLAN Control 3 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_MASK     0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_SHIFT    16
+
+/* SWITCH_CORE :: VLAN_CTRL3 :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_MASK               0x0000fe00
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_SHIFT              9
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL3 :: EN_DROP_NON1Q [08:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_MASK             0x000001ff
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL4 - 802.1Q VLAN Control 4 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: INGR_VID_CHK [07:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_MASK              0x000000c0
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_SHIFT             6
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_DEFAULT           0x00000003
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GVRP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_MASK           0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_SHIFT          5
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GMRP [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_MASK           0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_SHIFT          4
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: EN_DOUBLE_TAG [03:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_MASK             0x0000000c
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_SHIFT            2
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: RESV_MCAST_FLOOD [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_MASK          0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_SHIFT         1
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL4 :: SWITCH_RESV_1 [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_MASK             0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_SHIFT            0
+#define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL5 - 802.1Q VLAN Control 5 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_2 [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_MASK             0x00000080
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_SHIFT            7
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: PRESV_NON1Q [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_MASK               0x00000040
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_SHIFT              6
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_1 [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_MASK             0x00000020
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_SHIFT            5
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EGRESS_DIR_FRM_BYPASS_TRUNK_EN [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: DROP_VTABLE_MISS [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_MASK          0x00000008
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_SHIFT         3
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EN_VID_FFF_FWD [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_MASK            0x00000004
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_SHIFT           2
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_0 [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_MASK             0x00000002
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL5 :: EN_CPU_RX_BYP_INNER_CRCCHK [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_MASK 0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_SHIFT 0
+#define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VLAN_CTRL6 - 802.1Q VLAN Control 6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_CTRL6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_MASK     0xffffff00
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_SHIFT    8
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_1 [07:05] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_MASK             0x000000e0
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_SHIFT            5
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: DIS_ARL_BUST_LMT [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_MASK          0x00000010
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_SHIFT         4
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_0 [03:01] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_MASK             0x0000000e
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_SHIFT            1
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: VLAN_CTRL6 :: STRICT_SFD_DETECT [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_MASK         0x00000001
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_SHIFT        0
+#define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *VLAN_MULTI_PORT_ADDR_CTL - VLAN Multiport Address Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: SWITCH_RESV [15:12] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_MASK 0x0000f000
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_SHIFT 12
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_UTG_MAP [11:11] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_MASK 0x00000800
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_SHIFT 11
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_V_FWD_MAP [10:10] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_MASK 0x00000400
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_SHIFT 10
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_UTG_MAP [09:09] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_MASK 0x00000200
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_SHIFT 9
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_V_FWD_MAP [08:08] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_MASK 0x00000100
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_SHIFT 8
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_UTG_MAP [07:07] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_MASK 0x00000080
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_SHIFT 7
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_V_FWD_MAP [06:06] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_MASK 0x00000040
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_SHIFT 6
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_UTG_MAP [05:05] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_MASK 0x00000020
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_SHIFT 5
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_V_FWD_MAP [04:04] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_MASK 0x00000010
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_SHIFT 4
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_UTG_MAP [03:03] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_MASK 0x00000008
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_SHIFT 3
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_V_FWD_MAP [02:02] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_MASK 0x00000004
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_SHIFT 2
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_UTG_MAP [01:01] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_MASK 0x00000002
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_SHIFT 1
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_V_FWD_MAP [00:00] */
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_MASK 0x00000001
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_SHIFT 0
+#define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P0 - Port 0 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P1 - Port 1 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P2 - Port 2 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P3 - Port 3 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P4 - Port 4 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P5 - Port 5 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_P7 - Port 7 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_MASK                0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_SHIFT               13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_MASK                0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_SHIFT               12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_MASK                0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_SHIFT               0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_DEFAULT             0x00000001
+
+/***************************************************************************
+ *DEFAULT_1Q_TAG_IMP - Port 8 802.1Q Default Tag Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: PRI [15:13] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_MASK               0x0000e000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_SHIFT              13
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: CFI [12:12] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_MASK               0x00001000
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_SHIFT              12
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: VID [11:00] */
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_MASK               0x00000fff
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_SHIFT              0
+#define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_DEFAULT            0x00000001
+
+/***************************************************************************
+ *DTAG_TPID - Double Tagging TPID Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: DTAG_TPID :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: DTAG_TPID :: ISP_TPID [15:00] */
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_MASK                   0x0000ffff
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_SHIFT                  0
+#define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_DEFAULT                0x000088a8
+
+/***************************************************************************
+ *ISP_SEL_PORTMAP - ISP Port Selection Portmap Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: ISP_SEL_PORTMAP :: ISP_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_SHIFT         0
+#define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_DEFAULT       0x00000000
+
+/***************************************************************************
+ *EGRESS_VID_RMK_TBL_ACS - Egress VID Remarking Table Access Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: GLOBAL_WR_EN [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_MASK  0x80000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV1 [30:16] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_MASK  0x7fff0000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: TBL_ADDR [15:08] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_MASK      0x0000ff00
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_SHIFT     8
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: EGRESS_PORT [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_MASK   0x000000f0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_SHIFT  4
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV2 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_MASK  0x00000008
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: RESET_EVT [02:02] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_MASK     0x00000004
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_SHIFT    2
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: OP [01:01] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_MASK            0x00000002
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_SHIFT           1
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: START_DONE [00:00] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_MASK    0x00000001
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_SHIFT   0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_VID_RMK_TBL_DATA - Egress VID Remarking Table Data Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV1 [31:30] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_MASK 0xc0000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_SHIFT 30
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_OP [29:28] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_MASK     0x30000000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_SHIFT    28
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_VID [27:16] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_MASK    0x0fff0000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_SHIFT   16
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV2 [15:14] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_MASK 0x0000c000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_SHIFT 14
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_OP [13:12] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_MASK     0x00003000
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_SHIFT    12
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_VID [11:00] */
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_MASK    0x00000fff
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_SHIFT   0
+#define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *JOIN_ALL_VLAN_EN - Join All VLAN Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: JOIN_ALL_VLAN_EN [08:00] */
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_SHIFT   0
+#define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_IVL_SVL_CTRL - Port IVL or SVL Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_EN [15:15] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_MASK    0x00008000
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_SHIFT   15
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: SWITCH_RESV [14:09] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_MASK        0x00007e00
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_SEL [08:00] */
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_MASK   0x000001ff
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM8021Q_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BCM8021Q_REG_SPARE0 :: BCM8021Q_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM8021Q_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BCM8021Q_REG_SPARE1 :: BCM8021Q_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DOS_CTRL - DoS Control RegisterRegister
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_1 [31:14] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_MASK               0xffffc000
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_SHIFT              14
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_LONG_PING_DROP_EN [13:13] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_MASK    0x00002000
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_SHIFT   13
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_LONG_PING_DROP_EN [12:12] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_MASK    0x00001000
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_SHIFT   12
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV6_FRAGMENT_DROP_EN [11:11] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_MASK     0x00000800
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_SHIFT    11
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: ICMPV4_FRAGMENT_DROP_EN [10:10] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_MASK     0x00000400
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_SHIFT    10
+#define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_FRAG_ERR_DROP_EN [09:09] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_MASK        0x00000200
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_SHIFT       9
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SHORT_HDR_DROP_EN [08:08] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_MASK       0x00000100
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_SHIFT      8
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SYN_ERR_DROP_EN [07:07] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_MASK         0x00000080
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_SHIFT        7
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_SYNFIN_SCAN_DROP_EN [06:06] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_MASK     0x00000040
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_SHIFT    6
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_XMASS_SCAN_DROP_EN [05:05] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_MASK      0x00000020
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_SHIFT     5
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_NULL_SCAN_DROP_EN [04:04] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_MASK       0x00000010
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_SHIFT      4
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: UDP_BLAT_DROP_EN [03:03] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_MASK            0x00000008
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_SHIFT           3
+#define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: TCP_BLAT_DROP_EN [02:02] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_MASK            0x00000004
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_SHIFT           2
+#define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: IP_LAND_DROP_EN [01:01] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_MASK             0x00000002
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_SHIFT            1
+#define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_0 [00:00] */
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_MASK               0x00000001
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_SHIFT              0
+#define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_DEFAULT            0x00000001
+
+/***************************************************************************
+ *MINIMUM_TCP_HDR_SZ - Minimum TCP Header Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: MIN_TCP_HDR_SZ [07:00] */
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_MASK    0x000000ff
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_SHIFT   0
+#define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MAX_ICMPV4_SIZE_REG - Maximum ICMPv4 Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAX_ICMPV4_SIZE_REG :: MAX_ICMPV4_SIZE [31:00] */
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_SHIFT 0
+#define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_DEFAULT 0x00000200
+
+/***************************************************************************
+ *MAX_ICMPV6_SIZE_REG - Maximum ICMPv6 Size Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MAX_ICMPV6_SIZE_REG :: MAX_ICMPV6_SIZE [31:00] */
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_MASK  0xffffffff
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_SHIFT 0
+#define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_DEFAULT 0x00000200
+
+/***************************************************************************
+ *DOS_DIS_LRN_REG - DoS Disable Learn Register
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_MASK          0x000000fe
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_SHIFT         1
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: DOS_DIS_LRN_REG :: DOS_DIS_LRN [00:00] */
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_MASK          0x00000001
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_SHIFT         0
+#define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DOS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_REG_SPARE0 :: DOS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DOS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: DOS_REG_SPARE1 :: DOS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *JUMBO_PORT_MASK - Jumbo Frame Port Mask Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_MASK        0xfe000000
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_SHIFT       25
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: EN_10_100_JUMBO [24:24] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_MASK      0x01000000
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_SHIFT     24
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_0 [23:09] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_MASK        0x00fffe00
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_SHIFT       9
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: JUMBO_PORT_MASK :: JUMBO_FM_PORT_MASK [08:00] */
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_MASK   0x000001ff
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_SHIFT  0
+#define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MIB_GD_FM_MAX_SIZE - Jumbo MIB Good Frame Max Size Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: SWITCH_RESV [15:14] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_MASK       0x0000c000
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_SHIFT      14
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: MAX_SIZE [13:00] */
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_MASK          0x00003fff
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_SHIFT         0
+#define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_DEFAULT       0x000007d0
+
+/***************************************************************************
+ *JUMBO_CTRL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE0 :: JUMBO_CTRL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *JUMBO_CTRL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE1 :: JUMBO_CTRL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *COMM_IRC_CON - Common Ingress rate Control Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_2 [31:18] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_MASK           0xfffc0000
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_SHIFT          18
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE1 [17:17] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_MASK              0x00020000
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_SHIFT             17
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_1 [16:09] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_MASK           0x0001fe00
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_SHIFT          9
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE0 [08:08] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_MASK              0x00000100
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_SHIFT             8
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_0 [07:00] */
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_MASK           0x000000ff
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_SHIFT          0
+#define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *IRC_VIRTUAL_ZERO_THD - Ingress Rate Control Virtual Zero Threshold Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: IRC_VIRTUAL_ZERO_THD [15:00] */
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_SHIFT 0
+#define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_DEFAULT 0x00002fff
+
+/***************************************************************************
+ *IRC_ALARM_THD - Ingress Rate Control Alarm Threshold Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IRC_ALARM_THD :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_MASK  0xffff0000
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: IRC_ALARM_THD :: IRC_ALARM_THD [15:00] */
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_MASK          0x0000ffff
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_DEFAULT       0x00000bff
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P0 - Port 0 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P1 - Port 1 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P2 - Port 2 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P3 - Port 3 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P4 - Port 4 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P5 - Port 5 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_P7 - Port 7 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_MASK     0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_SHIFT    31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_MASK      0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_SHIFT     30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_MASK      0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_SHIFT     29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_DEFAULT   0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_MASK     0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_SHIFT    24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_MASK        0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_SHIFT       23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_MASK        0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_SHIFT       22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_MASK      0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_SHIFT     19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_MASK   0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_SHIFT  11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_MASK      0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_SHIFT     8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_MASK   0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_IMP - Port 8 Receive Rate Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_1 [31:31] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_MASK    0x80000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_SHIFT   31
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE1 [30:30] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_MASK     0x40000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_SHIFT    30
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_DEFAULT  0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE0 [29:29] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_MASK     0x20000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_SHIFT    29
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_DEFAULT  0x00000001
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_0 [28:24] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_MASK    0x1f000000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_SHIFT   24
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET1 [23:23] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_MASK       0x00800000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_SHIFT      23
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET0 [22:22] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_MASK       0x00400000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_SHIFT      22
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_SIZE [21:19] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_MASK     0x00380000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_SHIFT    19
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_REF_CNT [18:11] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_MASK  0x0007f800
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_SHIFT 11
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_DEFAULT 0x00000010
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_SIZE [10:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_MASK     0x00000700
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_SHIFT    8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_REF_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_MASK  0x000000ff
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P0 - Port 0 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P1 - Port 1 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P2 - Port 2 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P3 - Port 3 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P4 - Port 4 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P5 - Port 5 Receive Rate Control 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_P7 - Port 7 Receive Rate Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_MASK      0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_SHIFT     15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_MASK        0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_SHIFT       8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_MASK      0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_SHIFT     7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_MASK        0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_SHIFT       0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BC_SUP_RATECTRL_1_IMP - Port 8 Receive Rate Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES1 [15:15] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_MASK     0x00008000
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_SHIFT    15
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK1 [14:08] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_MASK       0x00007f00
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_SHIFT      8
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES0 [07:07] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_MASK     0x00000080
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_SHIFT    7
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK0 [06:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_MASK       0x0000007f
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_SHIFT      0
+#define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_DEFAULT    0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P0 - Port 0 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P0 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P1 - Port 1 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P1 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P2 - Port 2 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P2 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P3 - Port 3 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P3 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P4 - Port 4 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P4 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P5 - Port 5 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P5 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_P7 - P7 Suppressed Packet DropCounter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P7 :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_SHIFT   0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUP_PKTDROP_CNT_IMP - Port 8 Suppressed Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_IMP :: PK_DROP_CNT [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_SHIFT  0
+#define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUPPRESS_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE0 :: BC_SUPPRESS_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BC_SUPPRESS_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE1 :: BC_SUPPRESS_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EAP_GLO_CON - EAP Global Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_GLO_CON :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_MASK    0xffffff00
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_SHIFT   8
+
+/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV_0 [07:07] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_MASK            0x00000080
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_SHIFT           7
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_RARP [06:06] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_MASK                  0x00000040
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_SHIFT                 6
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_BPDU [05:05] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_MASK                  0x00000020
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_SHIFT                 5
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_RMC [04:04] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_MASK                   0x00000010
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_SHIFT                  4
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_DHCP [03:03] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_MASK                  0x00000008
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_SHIFT                 3
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_ARP [02:02] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_MASK                   0x00000004
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_SHIFT                  2
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: EN_2_DIP [01:01] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_MASK                 0x00000002
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_SHIFT                1
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV [00:00] */
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_MASK              0x00000001
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_SHIFT             0
+#define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_DEFAULT           0x00000000
+
+/***************************************************************************
+ *EAP_MULTI_ADDR_CTRL - EAP Multiport Address Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: SWITCH_RESV [07:06] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_MASK      0x000000c0
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_SHIFT     6
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT5 [05:05] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_MASK        0x00000020
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_SHIFT       5
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT4 [04:04] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_MASK        0x00000010
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_SHIFT       4
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT3 [03:03] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_MASK        0x00000008
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_SHIFT       3
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT2 [02:02] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_MASK        0x00000004
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_SHIFT       2
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT1 [01:01] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_MASK        0x00000002
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_SHIFT       1
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT0 [00:00] */
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_MASK        0x00000001
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_SHIFT       0
+#define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *EAP_DIP0 - EAP Destination IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_DIP0 :: DIP_SUB_REG [63:32] */
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_MASK                 0xffffffff00000000
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_SHIFT                32
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_DEFAULT              0x0000000000000000
+
+/* SWITCH_CORE :: EAP_DIP0 :: DIP_MASK_REG [31:00] */
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_MASK                0x00000000ffffffff
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_DIP1 - EAP Destination IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_DIP1 :: DIP_SUB_REG [63:32] */
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_MASK                 0xffffffff00000000
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_SHIFT                32
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_DEFAULT              0x0000000000000000
+
+/* SWITCH_CORE :: EAP_DIP1 :: DIP_MASK_REG [31:00] */
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_MASK                0x00000000ffffffff
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P0 - Port 0 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P0 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P0 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P0 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P0 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P0 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P1 - Port 1 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P1 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P1 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P1 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P1 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P1 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P2 - Port 2 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P2 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P2 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P2 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P2 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P2 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P3 - Port 3 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P3 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P3 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P3 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P3 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P3 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P4 - Port 4 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P4 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P4 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P4 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P4 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P4 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P5 - Port 5 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P5 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P5 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P5 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P5 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P5 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_P7 - Port 7 EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_P7 :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_MASK               0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_SHIFT              53
+#define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_DEFAULT            0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P7 :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_MASK                  0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_SHIFT                 51
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_DEFAULT               0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P7 :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_MASK              0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_SHIFT             49
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P7 :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_MASK             0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_SHIFT            48
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_P7 :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_MASK                0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_SHIFT               0
+#define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_DEFAULT             0x0000000000000000
+
+/***************************************************************************
+ *EAP_CON_IMP - IMP EAP Configuration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EAP_CON_IMP :: SWITCH_RESV [63:53] */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_MASK              0xffe0000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_SHIFT             53
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_DEFAULT           0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_IMP :: EAP_MODE [52:51] */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_MASK                 0x0018000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_SHIFT                51
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_DEFAULT              0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_IMP :: EAP_BLK_MODE [50:49] */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_MASK             0x0006000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_SHIFT            49
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_DEFAULT          0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_IMP :: EAP_EN_UNI_DA [48:48] */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_MASK            0x0001000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_SHIFT           48
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_DEFAULT         0x0000000000000000
+
+/* SWITCH_CORE :: EAP_CON_IMP :: EAP_UNI_DA [47:00] */
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_MASK               0x0000000000000000
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_SHIFT              0
+#define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_DEFAULT            0x0000000000000000
+
+/***************************************************************************
+ *IEEE8021X_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021X_REG_SPARE0 :: IEEE8021X_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021X_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021X_REG_SPARE1 :: IEEE8021X_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MST_CON - MST Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_CON :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_MASK        0xffffff00
+#define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_SHIFT       8
+
+/* SWITCH_CORE :: MST_CON :: SWITCH_RESV [07:01] */
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_MASK                  0x000000fe
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_SHIFT                 1
+#define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MST_CON :: EN_802_1S [00:00] */
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_AGE - MST Ageing Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_AGE :: SWITCH_RESV [31:08] */
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_MASK                  0xffffff00
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_SHIFT                 8
+#define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: MST_AGE :: AGE_EN_PRT [07:00] */
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_MASK                   0x000000ff
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_SHIFT                  0
+#define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *MST_TAB0 - MST Table 0 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB0 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB0 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB1 - MST Table 1 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB1 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB1 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB2 - MST Table 2 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB2 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB2 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB3 - MST Table 3 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB3 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB3 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB4 - MST Table 4 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB4 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB4 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB5 - MST Table 5 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB5 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB5 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB6 - MST Table 6 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB6 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB6 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MST_TAB7 - MST Table 7 Enable Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: MST_TAB7 :: MST_TAB_RSRV [31:27] */
+#define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_SHIFT               27
+#define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_MASK               0x07000000
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_SHIFT              24
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA7 [23:21] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_MASK                    0x00e00000
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_SHIFT                   21
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SWITCH_RESV_0 [20:18] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_MASK               0x001c0000
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_SHIFT              18
+#define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA5 [17:15] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_MASK                    0x00038000
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_SHIFT                   15
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA4 [14:12] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_MASK                    0x00007000
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_SHIFT                   12
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA3 [11:09] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_MASK                    0x00000e00
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_SHIFT                   9
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA2 [08:06] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_MASK                    0x000001c0
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_SHIFT                   6
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA1 [05:03] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_MASK                    0x00000038
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_SHIFT                   3
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: MST_TAB7 :: SPT_STA0 [02:00] */
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_MASK                    0x00000007
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_SHIFT                   0
+#define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SPT_MULTI_ADDR_BPS_CTRL - STP Multiport Address Bypass Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: SWITCH_RESV [15:06] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_MASK  0x0000ffc0
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_SHIFT 6
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT5_BYPASS_SPT [05:05] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_MASK 0x00000020
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_SHIFT 5
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT4_BYPASS_SPT [04:04] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_MASK 0x00000010
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_SHIFT 4
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT3_BYPASS_SPT [03:03] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_MASK 0x00000008
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_SHIFT 3
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT2_BYPASS_SPT [02:02] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_MASK 0x00000004
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_SHIFT 2
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT1_BYPASS_SPT [01:01] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_MASK 0x00000002
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_SHIFT 1
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT0_BYPASS_SPT [00:00] */
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_MASK 0x00000001
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_SHIFT 0
+#define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021S_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021S_REG_SPARE0 :: IEEE8021S_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IEEE8021S_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: IEEE8021S_REG_SPARE1 :: IEEE8021S_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_LIMIT_ENABLE - SA Limit Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_MASK          0x0000fe00
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_ENABLE :: SA_LIMIT_EN [08:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_MASK          0x000001ff
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_SHIFT         0
+#define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_RST - SA Learned Counters Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: TOTAL_SA_LRN_CNTR_RST [15:15] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_MASK 0x00008000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_SHIFT 15
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: SWITCH_RESV [14:09] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_MASK          0x00007e00
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_SHIFT         9
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_RST :: PORT_SA_LRN_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_RST - SA Over Limit Counters Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_MASK    0x0000fe00
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_SHIFT   9
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: PORT_SA_OVER_LIMIT_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TOTAL_SA_LIMIT_CTL - Total SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_MASK       0x0000e000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_SHIFT      13
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: TOTAL_SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_SHIFT 0
+#define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_DEFAULT 0x00001000
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P0 - Port 0 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P1 - Port 1 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P2 - Port 2 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P3 - Port 3 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P4 - Port 4 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P5 - Port 5 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P7 - Port 7 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *SA_LIMIT_CTL_P8 - Port 8 SA Limit Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: OVER_LIMIT_ACTIONS [15:14] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_MASK   0x0000c000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_SHIFT  14
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: SWITCH_RESV [13:13] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_MASK          0x00002000
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_SHIFT         13
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: SA_LRN_CNT_LIM [12:00] */
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_MASK       0x00001fff
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_SHIFT      0
+#define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_DEFAULT    0x00000400
+
+/***************************************************************************
+ *TOTAL_SA_LRN_CNTR - Total SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_MASK        0x0000e000
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_SHIFT       13
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: TOTAL_SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_MASK 0x00001fff
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_SHIFT 0
+#define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P0 - Port 0 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P0 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P0 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P1 - Port 1 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P1 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P1 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P2 - Port 2 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P2 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P2 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P3 - Port 3 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P3 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P3 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P4 - Port 4 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P4 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P4 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P5 - Port 5 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P5 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P5 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P7 - Port 7 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P7 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P7 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_LRN_CNTR_P8 - Port 8 SA Learned Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_LRN_CNTR_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P8 :: SWITCH_RESV [15:13] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_MASK           0x0000e000
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_SHIFT          13
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: SA_LRN_CNTR_P8 :: SA_LRN_CNT_NO [12:00] */
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_MASK         0x00001fff
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_SHIFT        0
+#define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P0 - Port 0 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P0 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P1 - Port 1 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P1 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P2 - Port 2 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P2 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P3 - Port 3 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P3 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P4 - Port 4 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P4 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P5 - Port 5 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P5 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P7 - Port 7 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P7 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVERLIMIT_CNTR_P8 - Port 8 SA Over Limit Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P8 :: SA_OVER_LIMIT_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SA_OVER_LIMIT_COPY_REDIRECT - SA Over Limit Actions Config Register
+ ***************************************************************************/
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: SWITCH_RESV [15:04] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_MASK 0x0000fff0
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_SHIFT 4
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: COPY_REDIRECT_PORT_ID [03:00] */
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_SHIFT 0
+#define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MAC_LIMIT_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE0 :: MAC_LIMIT_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MAC_LIMIT_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: MAC_LIMIT_REG_SPARE1 :: MAC_LIMIT_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P0 - Port 0 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P0 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P1 - Port 1 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P1 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P2 - Port 2 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P2 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P3 - Port 3 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P3 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P4 - Port 4 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P4 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P5 - Port 5 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P5 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_P7 - Port 7 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_MASK           0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_SHIFT          6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_MASK      0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_SHIFT     3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_P7 :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_MASK      0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_SHIFT     0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QOS_PRI_CTL_IMP - Port 8 QOS Priority Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: TXQ_EMPTY_STATUS_SELECT [07:07] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_SHIFT 7
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: SWITCH_RESV [06:06] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_MASK          0x00000040
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_SHIFT         6
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: WDRR_GRANULARITY [03:03] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_MASK     0x00000008
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_SHIFT    3
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QOS_PRI_CTL_IMP :: SCHEDULER_SELECT [02:00] */
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_MASK     0x00000007
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_SHIFT    0
+#define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QOS_WEIGHT_P0 - Port 0 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P1 - Port 1 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P2 - Port 2 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P3 - Port 3 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P4 - Port 4 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P5 - Port 5 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_P7 - Port 7 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_MASK              0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_SHIFT             56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_MASK              0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_SHIFT             48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_MASK              0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_SHIFT             40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_MASK              0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_SHIFT             32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_MASK              0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_SHIFT             24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_MASK              0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_SHIFT             16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_MASK              0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_SHIFT             8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_DEFAULT           0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_MASK              0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_SHIFT             0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_DEFAULT           0x0000000000000001
+
+/***************************************************************************
+ *QOS_WEIGHT_IMP - Port 8 QOS Weight Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q7_WEIGHT [63:56] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_MASK             0xff00000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_SHIFT            56
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q6_WEIGHT [55:48] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_MASK             0x00ff000000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_SHIFT            48
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q5_WEIGHT [47:40] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_MASK             0x0000ff0000000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_SHIFT            40
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q4_WEIGHT [39:32] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_MASK             0x000000ff00000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_SHIFT            32
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q3_WEIGHT [31:24] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_MASK             0x00000000ff000000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_SHIFT            24
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q2_WEIGHT [23:16] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_MASK             0x0000000000ff0000
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_SHIFT            16
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q1_WEIGHT [15:08] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_MASK             0x000000000000ff00
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_SHIFT            8
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_DEFAULT          0x0000000000000001
+
+/* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q0_WEIGHT [07:00] */
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_MASK             0x00000000000000ff
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_SHIFT            0
+#define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_DEFAULT          0x0000000000000001
+
+/***************************************************************************
+ *WDRR_PENALTY_P0 - Port 0 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P0 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P0 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P1 - Port 1 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P1 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P1 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P2 - Port 2 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P2 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P2 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P3 - Port 3 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P3 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P3 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P4 - Port 4 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P4 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P4 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P5 - Port 5 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P5 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P5 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WDRR_PENALTY_P7 - Port 7 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WDRR_PENALTY_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: WDRR_PENALTY_P7 :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: WDRR_PENALTY_P7 :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *P8_WDRR_PENALTY - Port 8 WDRR Weight-Scaling Penalty Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0
+#define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCHEDULER_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SCHEDULER_REG_SPARE0 :: SCHEDULER_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCHEDULER_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: SCHEDULER_REG_SPARE1 :: SCHEDULER_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 - Port 0 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 - Port 1 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 - Port 2 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 - Port 3 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 - Port 4 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 - Port 5 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 - Port 7 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP - Port 8 Byte-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 - Port 0 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 - Port 1 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 - Port 2 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 - Port 3 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 - Port 4 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 - Port 5 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 - Port 7 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP - Port 8 Byte-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P0 - Port 0 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P1 - Port 1 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P2 - Port 2 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P3 - Port 3 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P4 - Port 4 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P5 - Port 5 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_P7 - Port 7 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK   0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT  31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_MASK       0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_SHIFT      29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_MASK        0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_SHIFT       0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_STS_IMP - Port 8 PORT Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK  0x80000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_MASK      0x60000000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_SHIFT     29
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_MASK       0x1fffffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_SHIFT      0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 - Port 0 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 - Port 1 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 - Port 2 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 - Port 3 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 - Port 4 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 - Port 5 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 - Port 7 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP - Port 8 Packet-Based, Port Shaper Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_CTLREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE0 :: EGRESS_SHAPER_CTLREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_CTLREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE1 :: EGRESS_SHAPER_CTLREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 - Port 0 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 - Port 1 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 - Port 2 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 - Port 3 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 - Port 4 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 - Port 5 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 - Port 7 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP - Port 8 Packet-Based, Port Shaper Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_AVB_SHAPING_MODE - Port Shaper AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: PORT_SHAPER_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_ENABLE - Port Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_ENABLE :: PORT_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BUCKET_COUNT_SELECT - Port Shaper Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: PORT_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PORT_SHAPER_BLOCKING - Port Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: PORT_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IFG_BYTES - IFG Correction Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: IFG_BYTES :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: IFG_BYTES :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_MASK                0x0000fe00
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_SHIFT               9
+#define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: IFG_BYTES :: IFG_BYTES [08:00] */
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_MASK                  0x000001ff
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_SHIFT                 0
+#define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_DEFAULT               0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P0 - Port 0 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P1 - Port 1 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P2 - Port 2 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P3 - Port 3 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P4 - Port 4 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P5 - Port 5 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_P7 - Port 7 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_REFRESH_IMP - Port 8 Byte-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P0 - Port 0 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P1 - Port 1 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P2 - Port 2 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P3 - Port 3 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P4 - Port 4 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P5 - Port 5 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_P7 - Port 7 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_STS_IMP - Port 8 Queue 0 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 0 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 0 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_AVB_SHAPING_MODE - Queue 0 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: QUEUE0_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_ENABLE - Queue 0 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: QUEUE0_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_BUCKET_COUNT_SELECT - Queue 0 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE0_SHAPER_BLOCKING - Queue 0 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: QUEUE0_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P0 - Port 0 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P1 - Port 1 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P2 - Port 2 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P3 - Port 3 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P4 - Port 4 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P5 - Port 5 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_P7 - Port 7 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_REFRESH_IMP - Port 8 Byte-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P0 - Port 0 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P1 - Port 1 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P2 - Port 2 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P3 - Port 3 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P4 - Port 4 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P5 - Port 5 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_P7 - Port 7 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_STS_IMP - Port 8 Queue 1 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 1 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 1 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_AVB_SHAPING_MODE - Queue 1 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: QUEUE1_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_ENABLE - Queue 1 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: QUEUE1_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_BUCKET_COUNT_SELECT - Queue 1 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE1_SHAPER_BLOCKING - Queue 1 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: QUEUE1_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P0 - Port 0 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P1 - Port 1 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P2 - Port 2 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P3 - Port 3 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P4 - Port 4 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P5 - Port 5 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_P7 - Port 7 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_REFRESH_IMP - Port 8 Byte-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P0 - Port 0 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P1 - Port 1 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P2 - Port 2 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P3 - Port 3 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P4 - Port 4 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P5 - Port 5 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_P7 - Port 7 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_STS_IMP - Port 8 Queue 2 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 2 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 2 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_AVB_SHAPING_MODE - Queue 2 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: QUEUE2_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_ENABLE - Queue 2 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: QUEUE2_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_BUCKET_COUNT_SELECT - Queue 2 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE2_SHAPER_BLOCKING - Queue 2 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: QUEUE2_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P0 - Port 0 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P1 - Port 1 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P2 - Port 2 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P3 - Port 3 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P4 - Port 4 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P5 - Port 5 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_P7 - Port 7 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_REFRESH_IMP - Port 8 Byte-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P0 - Port 0 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P1 - Port 1 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P2 - Port 2 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P3 - Port 3 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P4 - Port 4 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P5 - Port 5 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_P7 - Port 7 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_STS_IMP - Port 8 Queue 3 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 3 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 3 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_AVB_SHAPING_MODE - Queue 3 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: QUEUE3_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_ENABLE - Queue 3 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: QUEUE3_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_BUCKET_COUNT_SELECT - Queue 3 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE3_SHAPER_BLOCKING - Queue 3 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: QUEUE3_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P0 - Port 0 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P1 - Port 1 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P2 - Port 2 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P3 - Port 3 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P4 - Port 4 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P5 - Port 5 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_P7 - Port 7 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_REFRESH_IMP - Port 8 Byte-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P0 - Port 0 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P1 - Port 1 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P2 - Port 2 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P3 - Port 3 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P4 - Port 4 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P5 - Port 5 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_P7 - Port 7 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_STS_IMP - Port 8 Queue 4 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 4 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 4 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_AVB_SHAPING_MODE - Queue 4 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: QUEUE4_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_ENABLE - Queue 4 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: QUEUE4_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_BUCKET_COUNT_SELECT - Queue 4 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE4_SHAPER_BLOCKING - Queue 4 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: QUEUE4_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P0 - Port 0 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P1 - Port 1 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P2 - Port 2 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P3 - Port 3 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P4 - Port 4 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P5 - Port 5 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_P7 - Port 7 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_REFRESH_IMP - Port 8 Byte-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P0 - Port 0 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P1 - Port 1 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P2 - Port 2 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P3 - Port 3 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P4 - Port 4 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P5 - Port 5 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_P7 - Port 7 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_STS_IMP - Port 8 Queue 5 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 5 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 5 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_AVB_SHAPING_MODE - Queue 5 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: QUEUE5_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_ENABLE - Queue 5 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: QUEUE5_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_BUCKET_COUNT_SELECT - Queue 5 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE5_SHAPER_BLOCKING - Queue 5 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: QUEUE5_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P0 - Port 0 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P1 - Port 1 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P2 - Port 2 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P3 - Port 3 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P4 - Port 4 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P5 - Port 5 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_P7 - Port 7 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_REFRESH_IMP - Port 8 Byte-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P0 - Port 0 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P1 - Port 1 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P2 - Port 2 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P3 - Port 3 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P4 - Port 4 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P5 - Port 5 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_P7 - Port 7 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_STS_IMP - Port 8 Queue 6 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 6 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 6 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_AVB_SHAPING_MODE - Queue 6 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: QUEUE6_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_ENABLE - Queue 6 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: QUEUE6_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_BUCKET_COUNT_SELECT - Queue 6 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE6_SHAPER_BLOCKING - Queue 6 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: QUEUE6_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P0 - Port 0 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P1 - Port 1 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P2 - Port 2 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P3 - Port 3 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P4 - Port 4 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P5 - Port 5 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_P7 - Port 7 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_REFRESH_IMP - Port 8 Byte-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_MASK    0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT   18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_MASK    0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT   0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_MASK   0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT  18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK   0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT  0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P0 - Port 0 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P1 - Port 1 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P2 - Port 2 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P3 - Port 3 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P4 - Port 4 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P5 - Port 5 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_P7 - Port 7 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_MASK     0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_SHIFT    29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_MASK      0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_STS_IMP - Port 8 Queue 7 Shaper Status Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_MASK    0x60000000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_SHIFT   29
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_MASK     0x1fffffff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_SHIFT    0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 7 Shaping Rate Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 7 Burst Size Configure Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_AVB_SHAPING_MODE - Queue 7 AVB Shaping Mode Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_MASK  0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: QUEUE7_AVB_SHAPING_MODE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_ENABLE - Queue 7 Shaper Enable Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_MASK     0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_SHIFT    9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: QUEUE7_SHAPER_ENABLE [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_BUCKET_COUNT_SELECT - Queue 7 Bucket Count Select Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *QUEUE7_SHAPER_BLOCKING - Queue 7 Shaper Blocking Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_MASK   0x0000fe00
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_SHIFT  9
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: QUEUE7_SHAPER_BLOCKING [08:00] */
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_SHIFT 0
+#define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MIB_SNAPSHOT_CTL - MIB Snapshot Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_STDONE [07:07] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_MASK     0x00000080
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_SHIFT    7
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_MIRROR [06:06] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_MASK     0x00000040
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_SHIFT    6
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SWITCH_RESV [05:05] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_MASK         0x00000020
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_SHIFT        5
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: RST_MIB_SNAPSHOT_CNT_EN [04:04] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_MASK 0x00000010
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_SHIFT 4
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_PORT [03:00] */
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_MASK       0x0000000f
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_SHIFT      0
+#define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *S_TxOctets - Tx Octets
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_MASK                     0x0000000000000000
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxOctets_COUNT_DEFAULT                  0x0000000000000000
+
+/***************************************************************************
+ *S_TxDropPkts - Tx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxDropPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ0 - Tx Q0 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ0 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxBroadcastPkts - Tx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxBroadcastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxMulticastPkts - Tx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxMulticastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxUnicastPkts - Tx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxUnicastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_TxCollisions - Tx Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxCollisions :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_MASK                 0xffffffff
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *S_TxSingleCollision - Tx Single Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxSingleCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *S_TxMultipleCollision - Tx Multiple collsion Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxMultipleCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_TxDeferredTransmit - Tx Deferred Transmit Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxDeferredTransmit :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_SHIFT          0
+#define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *S_TxLateCollision - Tx Late Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxLateCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_TxExcessiveCollision - Tx Excessive Collision Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxExcessiveCollision :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxFrameInDisc - Tx Fram IN Disc Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxFrameInDisc :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_TxPausePkts - Tx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPausePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ1 - Tx Q1 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ1 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ2 - Tx Q2 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ2 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ3 - Tx Q3 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ3 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ4 - Tx Q4 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ4 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ5 - Tx Q5 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ5 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_RxOctets - Rx Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_MASK                     0x0000000000000000
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_RxOctets_COUNT_DEFAULT                  0x0000000000000000
+
+/***************************************************************************
+ *S_RxUndersizePkts - Rx Under Size Packet Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxUndersizePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxPausePkts - Rx Pause Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPausePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxPkts64Octets - Rx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts64Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_RxPkts65to127Octets - Rx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts65to127Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_RxPkts128to255Octets - Rx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts128to255Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_RxPkts256to511Octets - Rx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts256to511Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_RxPkts512to1023Octets - Rx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts512to1023Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *S_RxPkts1024toMaxPktOctets - Rx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxPkts1024toMaxPktOctets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_MASK     0xffffffff
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_SHIFT    0
+#define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *S_RxOversizePkts - Rx Over Size Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxOversizePkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_RxJabbers - Rx Jabber Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxJabbers :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *S_RxAlignmentErrors - Rx Alignment Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxAlignmentErrors :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_MASK            0xffffffff
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_SHIFT           0
+#define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *S_RxFCSErrors - Rx FCS Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxFCSErrors :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxGoodOctets - Rx Good Packet Octet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxGoodOctets :: COUNT [63:00] */
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_MASK                 0x0000000000000000
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_SHIFT                0
+#define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_DEFAULT              0x0000000000000000
+
+/***************************************************************************
+ *S_RxDropPkts - Rx Drop Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxDropPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_RxUnicastPkts - Rx Unicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxUnicastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_RxMulticastPkts - Rx Multicast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxMulticastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxBroadcastPkts - Rx Broadcast Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxBroadcastPkts :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_RxSAChanges - Rx SA Change Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxSAChanges :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxFragments - Rx Fragment Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxFragments :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_SHIFT                 0
+#define BCHP_SWITCH_CORE_S_RxFragments_COUNT_DEFAULT               0x00000000
+
+/***************************************************************************
+ *S_RxJumboPkt - Jumbo Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxJumboPkt :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_RxSymblErr - Rx Symbol Error Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxSymblErr :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_MASK                   0xffffffff
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_SHIFT                  0
+#define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *S_InRangeErrCount - InRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_InRangeErrCount :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_SHIFT             0
+#define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *S_OutRangeErrCount - OutRangeErrCount Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_OutRangeErrCount :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *S_EEE_LPI_EVENT - EEE Low-Power Idle Event Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: S_EEE_LPI_EVENT :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_MASK                0xffffffff
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_SHIFT               0
+#define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *S_EEE_LPI_DURATION - EEE Low-Power Idle Duration Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: S_EEE_LPI_DURATION :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_MASK             0xffffffff
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_SHIFT            0
+#define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *S_RxDiscard - Rx Discard Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_RxDiscard :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_MASK                    0xffffffff
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_SHIFT                   0
+#define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ6 - Tx Q6 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ6 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxQPKTQ7 - Tx Q7 Packet Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxQPKTQ7 :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_MASK                     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_SHIFT                    0
+#define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *S_TxPkts64Octets - Tx 64 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts64Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_SHIFT              0
+#define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *S_TxPkts65to127Octets - Tx 65 to 127 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts65to127Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_MASK          0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_SHIFT         0
+#define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_DEFAULT       0x00000000
+
+/***************************************************************************
+ *S_TxPkts128to255Octets - Tx 128 to 255 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts128to255Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxPkts256to511Octets - Tx 256 to 511 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts256to511Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_SHIFT        0
+#define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *S_TxPkts512to1023Octets - Tx 512 to 1023 Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts512to1023Octets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_SHIFT       0
+#define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *S_TxPkts1024toMaxPktOctets - Tx 1024 to MaxPkt Bytes Octets Counter
+ ***************************************************************************/
+/* SWITCH_CORE :: S_TxPkts1024toMaxPktOctets :: COUNT [31:00] */
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_MASK     0xffffffff
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_SHIFT    0
+#define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *LPDET_CFG - Loop Detection Configuration RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_MASK      0xffff0000
+#define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_SHIFT     16
+
+/* SWITCH_CORE :: LPDET_CFG :: SWITCH_RESV [15:15] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_MASK                0x00008000
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_SHIFT               15
+#define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL2 [14:14] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_MASK                   0x00004000
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_SHIFT                  14
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: EN_TXPASS [13:13] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_MASK                  0x00002000
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_SHIFT                 13
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: EN_LPDET [12:12] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_MASK                   0x00001000
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_SHIFT                  12
+#define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: LOOP_IMP_SEL [11:11] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_MASK               0x00000800
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_SHIFT              11
+#define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: LPDET_CFG :: LED_RST_CTL [10:03] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_MASK                0x000007f8
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_SHIFT               3
+#define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_DEFAULT             0x00000004
+
+/* SWITCH_CORE :: LPDET_CFG :: OV_PAUSE_ON [02:02] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_MASK                0x00000004
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_SHIFT               2
+#define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_DEFAULT             0x00000001
+
+/* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL [01:00] */
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_MASK                    0x00000003
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_SHIFT                   0
+#define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_DEFAULT                 0x00000001
+
+/***************************************************************************
+ *DF_TIMER - Discovery Frame Timer RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: DF_TIMER :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: DF_TIMER :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_MASK                 0x000000f0
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_SHIFT                4
+#define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: DF_TIMER :: DF_TIME [03:00] */
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_MASK                     0x0000000f
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_SHIFT                    0
+#define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *LED_PORTMAP - LED Waming Portmap RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LED_PORTMAP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: LED_PORTMAP :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: LED_PORTMAP :: LED_WARNING_PORTMAP [08:00] */
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_MASK      0x000001ff
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_SHIFT     0
+#define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MODULE_ID0 - Module ID 0 RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MODULE_ID0 :: MID_SA [47:00] */
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_MASK                    0x000000000000
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_SHIFT                   0
+#define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_DEFAULT                 0x000000000000
+
+/***************************************************************************
+ *MODULE_ID1 - Module ID 1 RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: MODULE_ID1 :: MID_AVAIL [47:47] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_MASK                 0x800000000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_SHIFT                47
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_DEFAULT              0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: SWITCH_RESV [46:40] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_MASK               0x7f0000000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_SHIFT              40
+#define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_DEFAULT            0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: MID_PORTNUM [39:32] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_MASK               0x00ff00000000
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_SHIFT              32
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_DEFAULT            0x000000000000
+
+/* SWITCH_CORE :: MODULE_ID1 :: MID_CRC [31:00] */
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_MASK                   0x0000ffffffff
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_SHIFT                  0
+#define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_DEFAULT                0x000000000000
+
+/***************************************************************************
+ *LPDET_SA - Loop Detect Frame SA RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_SA :: LPDET_SA [47:00] */
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_MASK                    0x000000000000
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_SHIFT                   0
+#define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_DEFAULT                 0x0180c2000001
+
+/***************************************************************************
+ *LPDET_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_REG_SPARE0 :: LPDET_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LPDET_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: LPDET_REG_SPARE1 :: LPDET_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BPM_CTRL - BPM Power Switching Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_MASK       0xffffff00
+#define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_SHIFT      8
+
+/* SWITCH_CORE :: BPM_CTRL :: SWITCH_RESV [07:05] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_MASK                 0x000000e0
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_SHIFT                5
+#define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: RX_PORT_KEEP2PAGE [04:04] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_MASK           0x00000010
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_SHIFT          4
+#define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PDA_CHG_OPT [03:03] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_SHIFT                3
+#define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: BFCFIFO_RECYCLE_EN [02:02] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_MASK          0x00000004
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_SHIFT         2
+#define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PTR_RECYCLE_EN [01:01] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_MASK              0x00000002
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_SHIFT             1
+#define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: BPM_CTRL :: PSM_SW_EN [00:00] */
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_MASK                   0x00000001
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_SHIFT                  0
+#define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_DEFAULT                0x00000000
+
+/***************************************************************************
+ *BPM_PSM_OVR_CTRL - BPM Power Switching SW Override Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE_EN [07:07] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_MASK  0x00000080
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_SHIFT 7
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: SWITCH_RESV [06:03] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_MASK         0x00000078
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_SHIFT        3
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE [02:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_MASK     0x00000007
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_SHIFT    0
+#define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *BPM_PSM_TIME_CFG - PSM_VDD Timing Parameter Configuration Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: DPSM_CNT [15:08] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_MASK            0x0000ff00
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_SHIFT           8
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_DEFAULT         0x00000017
+
+/* SWITCH_CORE :: BPM_PSM_TIME_CFG :: MPSM_CNT [07:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_SHIFT           0
+#define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_DEFAULT         0x00000002
+
+/***************************************************************************
+ *BPM_PSM_THD_CFG - PSM_VDD Switching Threshold Configuration Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_1 [31:28] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_MASK        0xf0000000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_SHIFT       28
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_ON_THD [27:16] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_MASK           0x0fff0000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_SHIFT          16
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_DEFAULT        0x00000027
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_0 [15:12] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_MASK        0x0000f000
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_SHIFT       12
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_OFF_THD [11:00] */
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_MASK          0x00000fff
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_SHIFT         0
+#define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_DEFAULT       0x00000050
+
+/***************************************************************************
+ *ROW_VMASK_OVR_CTRL - BUFCON Row Status Valid Mask SW Override Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_EN [15:15] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_MASK       0x00008000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_SHIFT      15
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: SWITCH_RESV [14:12] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_MASK       0x00007000
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_SHIFT      12
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_VAL [11:00] */
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_MASK      0x00000fff
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_SHIFT     0
+#define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_DEFAULT   0x00000fff
+
+/***************************************************************************
+ *BPM_STS - BPM Status Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_STS :: PBB_PWR_STS [31:29] */
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_MASK                  0xe0000000
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_SHIFT                 29
+#define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_DEFAULT               0x00000007
+
+/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_1 [28:28] */
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_MASK                0x10000000
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_SHIFT               28
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: ROW_USE_STS [27:16] */
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_MASK                  0x0fff0000
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_SHIFT                 16
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_DEFAULT               0x00000001
+
+/* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_0 [15:14] */
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_MASK                0x0000c000
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_SHIFT               14
+#define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: CUR_PBB [13:12] */
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_MASK                      0x00003000
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_SHIFT                     12
+#define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: BPM_STS :: ROW_VMASK [11:00] */
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_MASK                    0x00000fff
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_SHIFT                   0
+#define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_DEFAULT                 0x00000fff
+
+/***************************************************************************
+ *BPM_PDA_OVR_CTRL - BPM PDA Switching SW Override Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_EN [15:15] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_MASK         0x00008000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_SHIFT        15
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_DONE [14:14] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_MASK       0x00004000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_SHIFT      14
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: SWITCH_RESV [13:12] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_MASK         0x00003000
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_SHIFT        12
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_VAL [11:00] */
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_MASK        0x00000fff
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PDA_TIMEOUT_CFG - BPM PDA Switching Timeout Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_TIMEOUT_CFG :: PDA_TIMEOUT_CNT [15:00] */
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_MASK      0x0000ffff
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_SHIFT     0
+#define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_DEFAULT   0x00000100
+
+/***************************************************************************
+ *PDA_SETUP_TIME_CFG - BPM PDA Switching Setup Time Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_MASK       0x0000f800
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_SHIFT      11
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SETUP_TIME [10:00] */
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_SHIFT       0
+#define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_DEFAULT     0x00000001
+
+/***************************************************************************
+ *PDA_HOLD_TIME_CFG - BPM PDA Switching Hold Time Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: HOLD_TIME [10:00] */
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_SHIFT         0
+#define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_DEFAULT       0x00000001
+
+/***************************************************************************
+ *PBB_VBUFCNT_P0 - Packet Buffer Block 0 Valid Buffer Count Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P0 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_MASK           0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_SHIFT          10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P0 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_MASK         0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_SHIFT        0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_DEFAULT      0x00000200
+
+/***************************************************************************
+ *PBB_VBUFCNT_P1 - Packet Buffer Block 1 Valid Buffer Count Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P1 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_MASK           0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_SHIFT          10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P1 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_MASK         0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_SHIFT        0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_DEFAULT      0x00000200
+
+/***************************************************************************
+ *PBB_VBUFCNT_P2 - Packet Buffer Block 2 Valid Buffer Count Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_VBUFCNT_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P2 :: SWITCH_RESV [15:10] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_MASK           0x0000fc00
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_SHIFT          10
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: PBB_VBUFCNT_P2 :: VALID_BUF_CNT [09:00] */
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_MASK         0x000003ff
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_SHIFT        0
+#define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_DEFAULT      0x00000200
+
+/***************************************************************************
+ *RCY_TIME_CFG - Recycling Check Pulse Period Counter Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: RCY_TIME_CFG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RCY_TIME_CFG :: CHK_TIME [15:00] */
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_MASK                0x0000ffff
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_SHIFT               0
+#define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_DEFAULT             0x00000020
+
+/***************************************************************************
+ *PBB_PWRDWN_MON_CTRL - PBB Powerdown Monitor Control Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_PERIOD [15:08] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_MASK       0x0000ff00
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_SHIFT      8
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_DEFAULT    0x00000001
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_TIME_UNIT [07:03] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_MASK    0x000000f8
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_SHIFT   3
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_DEFAULT 0x00000001
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_DONE [02:02] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_MASK         0x00000004
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_SHIFT        2
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_CLR [01:01] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_MASK          0x00000002
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_SHIFT         1
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_EN [00:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_MASK           0x00000001
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_SHIFT          0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON0 - PBB Powerdown Time Monitor 0 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON0 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON1 - PBB Powerdown Time Monitor 1 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON1 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *PBB_PWRDWN_MON2 - PBB Powerdown Time Monitor 2 Register Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: PBB_PWRDWN_MON2 :: PWRDWN_CNT [63:00] */
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_MASK           0x0000000000000000
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_SHIFT          0
+#define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_DEFAULT        0x0000000000000000
+
+/***************************************************************************
+ *BPM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_REG_SPARE0 :: BPM_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *BPM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: BPM_REG_SPARE1 :: BPM_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *TRREG_CTRL0 - Traffic Remarking Control 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: PCP_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_MASK               0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_SHIFT              16
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL0 :: CFI_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_SHIFT              0
+#define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TRREG_CTRL1 - Traffic Remarking Control 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: DEI_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_MASK               0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_SHIFT              16
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: PPPOE_DSCP_RMK_EN [15:15] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_MASK        0x00008000
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_SHIFT       15
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_0 [14:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_MASK            0x00007e00
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL1 :: DSCP_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_MASK              0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_SHIFT             0
+#define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_DEFAULT           0x000001ff
+
+/***************************************************************************
+ *TRREG_CTRL2 - Traffic Remarking Control 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_1 [31:25] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_MASK            0xfe000000
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_SHIFT           25
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: C_PCP_RMK_EN [24:16] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_MASK             0x01ff0000
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_SHIFT            16
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_0 [15:09] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_MASK            0x0000fe00
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_SHIFT           9
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TRREG_CTRL2 :: S_PCP_RMK_EN [08:00] */
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_MASK             0x000001ff
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_SHIFT            0
+#define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_DEFAULT          0x00000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P0 - Port 0 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P1 - Port 1 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P2 - Port 2 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P3 - Port 3 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P4 - Port 4 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P5 - Port 5 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_P7 - Port 7 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2PCP_MAP_IMP - Port 8 Egress TC to PCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC7 [63:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC6 [59:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC5 [55:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC4 [51:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC3 [47:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC2 [43:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC1 [39:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC0 [35:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC7 [31:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC6 [27:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC5 [23:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC4 [19:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC3 [15:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC2 [11:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC1 [07:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC0 [03:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P0 - Port 0 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P1 - Port 1 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P2 - Port 2 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P3 - Port 3 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P4 - Port 4 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P5 - Port 5 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_P7 - Port 7 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *EGRESS_PKT_TC2CPCP_MAP_IMP - Port 8 Egress TC to CPCP mapping Register
+ ***************************************************************************/
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_15 [63:63] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_MASK 0x8000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_SHIFT 63
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC7 [62:60] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_SHIFT 60
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_14 [59:59] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_MASK 0x0800000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_SHIFT 59
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC6 [58:56] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_SHIFT 56
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_13 [55:55] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_MASK 0x0080000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_SHIFT 55
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC5 [54:52] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_SHIFT 52
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_12 [51:51] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_MASK 0x0008000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_SHIFT 51
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC4 [50:48] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_SHIFT 48
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_11 [47:47] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_MASK 0x0000800000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_SHIFT 47
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC3 [46:44] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_SHIFT 44
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_10 [43:43] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_MASK 0x0000080000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_SHIFT 43
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC2 [42:40] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_SHIFT 40
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_9 [39:39] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_MASK 0x0000008000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_SHIFT 39
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC1 [38:36] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_SHIFT 36
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_8 [35:35] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_MASK 0x0000000800000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_SHIFT 35
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC0 [34:32] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_SHIFT 32
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_7 [31:31] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_MASK 0x0000000080000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_SHIFT 31
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC7 [30:28] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_SHIFT 28
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_6 [27:27] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_MASK 0x0000000008000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_SHIFT 27
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC6 [26:24] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_SHIFT 24
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_5 [23:23] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_MASK 0x0000000000800000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_SHIFT 23
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC5 [22:20] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_SHIFT 20
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_4 [19:19] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_MASK 0x0000000000080000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_SHIFT 19
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC4 [18:16] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_SHIFT 16
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_3 [15:15] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_MASK 0x0000000000008000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_SHIFT 15
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC3 [14:12] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_SHIFT 12
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_2 [11:11] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_MASK 0x0000000000000800
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_SHIFT 11
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC2 [10:08] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_SHIFT 8
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_1 [07:07] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_MASK 0x0000000000000080
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_SHIFT 7
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC1 [06:04] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_SHIFT 4
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_0 [03:03] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_MASK 0x0000000000000008
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_SHIFT 3
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_DEFAULT 0x0000000000000000
+
+/* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC0 [02:00] */
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_SHIFT 0
+#define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *TRREG_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_REG_SPARE0 :: TRREG_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_SHIFT   0
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TRREG_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TRREG_REG_SPARE1 :: TRREG_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_SHIFT   0
+#define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_EN_CTRL - EEE Enable Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_EN_CTRL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: EEE_EN_CTRL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: EEE_EN_CTRL :: EN_EEE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_MASK                   0x000001ff
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_SHIFT                  0
+#define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_DEFAULT                0x00000000
+
+/***************************************************************************
+ *EEE_LPI_ASSERT - EEE Low Power Assert Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_MASK           0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_SHIFT          9
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_ASSERT :: LPI_ASSERT [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_MASK            0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_SHIFT           0
+#define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *EEE_LPI_INDICATE - EEE Low Power Indicate Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_MASK         0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_SHIFT        9
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_INDICATE :: LPI_INDICATE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_MASK        0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *EEE_RX_IDLE_SYMBOL - EEE Receiving Idle Symbols Status Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_MASK       0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_SHIFT      9
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: RX_IDLE_SYMBOL [08:00] */
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_MASK    0x000001ff
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_LPI_SYMBOL_TX_DISABLE - EEE LPI Symbol Transmit Disable Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_MASK 0x0000fe00
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_SHIFT 9
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: EEE_LPI_SYMBOL_TX_DISABLE [08:00] */
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_PIPELINE_TIMER - EEE Pipeline Delay Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_PIPELINE_TIMER :: PIPELINE_TIMER [31:00] */
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_DEFAULT 0x00000020
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P0 - EEE Port 0 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P0 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P1 - EEE Port 1 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P1 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P2 - EEE Port 2 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P2 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P3 - EEE Port 3 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P3 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P4 - EEE Port 4 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P4 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P5 - EEE Port 5 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P5 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_P7 - EEE Port 7 Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P7 :: SLEEP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_G_IMP - EEE Port 8(IMP) Sleep Delay Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_G_IMP :: SLEEP_TIMER_G_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_DEFAULT 0x00000190
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P0 - EEE Port 0 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P0 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P1 - EEE Port 1 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P1 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P2 - EEE Port 2 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P2 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P3 - EEE Port 3 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P3 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P4 - EEE Port 4 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P4 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P5 - EEE Port 5 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P5 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_P7 - EEE Port 7 Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P7 :: SLEEP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_MASK   0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_SHIFT  0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_SLEEP_TIMER_H_IMP - EEE Port 8(IMP) Sleep Delay Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_SLEEP_TIMER_H_IMP :: SLEEP_TIMER_H_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_DEFAULT 0x00000fa0
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P0 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P0 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P1 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P1 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P2 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P2 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P3 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P3 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P4 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P4 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P5 - EEE Port Minimum Low-Power Duration Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P5 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_P7 - EEE Port 7 Minimum Low-Power Duration Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P7 :: MIN_LP_TIMER_G [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_G_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_IMP :: MIN_LP_TIMER_G_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_DEFAULT 0x00000032
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P0 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P0 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P1 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P1 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P2 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P2 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P3 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P3 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P4 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P4 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P5 - EEE Port Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P5 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_P7 - EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P7 :: MIN_LP_TIMER_H [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_MIN_LP_TIMER_H_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_IMP :: MIN_LP_TIMER_H_IMP [31:00] */
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_DEFAULT 0x000001f4
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P0 - EEE Port 0 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P0 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P1 - EEE Port 1 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P1 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P2 - EEE Port 2 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P2 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P3 - EEE Port 3 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P3 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P4 - EEE Port 4 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P4 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P5 - EEE Port 5 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P5 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P7 - EEE Port 7 Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: WAKE_TIMER_G [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_DEFAULT  0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_G_P8 - EEE Port 8(IMP) Wake Transition Timer - 1G Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P8 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_G_P8 :: WAKE_TIMER_G_IMP [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_DEFAULT 0x00000011
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P0 - EEE Port 0 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P0 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P1 - EEE Port 1 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P1 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P2 - EEE Port 2 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P2 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P3 - EEE Port 3 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P3 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P4 - EEE Port 4 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P4 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P5 - EEE Port 5 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P5 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_P7 - EEE Port 7 Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: WAKE_TIMER_H [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_MASK     0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_SHIFT    0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_DEFAULT  0x00000024
+
+/***************************************************************************
+ *EEE_WAKE_TIMER_H_IMP - EEE Port 8(IMP) Wake Transition Timer - 100M Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: WAKE_TIMER_H_IMP [15:00] */
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_MASK 0x0000ffff
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_DEFAULT 0x00000024
+
+/***************************************************************************
+ *EEE_GLB_CONG_TH - EEE Global Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_MASK          0x0000f800
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_SHIFT         11
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: EEE_GLB_CONG_TH :: GLB_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_MASK          0x000007ff
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_SHIFT         0
+#define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_DEFAULT       0x00000300
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q0 - EEE TXQ 0 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_DEFAULT     0x00000050
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q1 - EEE TXQ 1 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_DEFAULT     0x00000050
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q2 - EEE TXQ 2 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_DEFAULT     0x00000050
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q3 - EEE TXQ 3 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_DEFAULT     0x00000050
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q4 - EEE TXQ 4 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_DEFAULT     0x00000050
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q5 - EEE TXQ 5 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_DEFAULT     0x00000001
+
+/***************************************************************************
+ *EEE_PHY_CTRL - EEE PHY Control Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_PHY_CTRL :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_MASK   0xffffff00
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_SHIFT  8
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: SWITCH_RESV [07:04] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_MASK             0x000000f0
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_SHIFT            4
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_100BASE_TX [03:03] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_MASK          0x00000008
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_SHIFT         3
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_DEFAULT       0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_1000BASE_TX [02:02] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_MASK         0x00000004
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_SHIFT        2
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_DEFAULT      0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_PHY_LPI [01:01] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_MASK              0x00000002
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_SHIFT             1
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_DEFAULT           0x00000001
+
+/* SWITCH_CORE :: EEE_PHY_CTRL :: EN_BIAS_10BTE [00:00] */
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_MASK           0x00000001
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_SHIFT          0
+#define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_DEFAULT        0x00000000
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q6 - EEE TXQ 6 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_DEFAULT     0x00000001
+
+/***************************************************************************
+ *EEE_TX_CONG_TH_Q7 - EEE TXQ 7 Congestion Threshold Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_MASK        0x0000f800
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_SHIFT       11
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: TXQ_CONG_TH [10:00] */
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_MASK        0x000007ff
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_SHIFT       0
+#define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_DEFAULT     0x00000001
+
+/***************************************************************************
+ *EEE_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_CTL_REG_SPARE0 :: EEE_CTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_CTL_REG_SPARE1 :: EEE_CTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EEE_DEBUG - EEE Debug Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_DEBUG :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_MASK      0xffffff00
+#define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_SHIFT     8
+
+/* SWITCH_CORE :: EEE_DEBUG :: SWITCH_RESV [07:02] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_MASK                0x000000fc
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_SHIFT               2
+#define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EEE_DEBUG :: DIS_EXIT_LPI_FLOW_CON_TX [01:01] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_MASK   0x00000002
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_SHIFT  1
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: EEE_DEBUG :: DIS_EMPTY_FLOW_CON [00:00] */
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_MASK         0x00000001
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_SHIFT        0
+#define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_DEFAULT      0x00000000
+
+/***************************************************************************
+ *EEE_LINK_DLY_TIMER - EEE Link Delay Timer Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_LINK_DLY_TIMER :: LINK_DLY_TIMER [31:00] */
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_MASK    0xffffffff
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_SHIFT   0
+#define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_DEFAULT 0x000f4240
+
+/***************************************************************************
+ *EEE_STATE - EEE Control Policy State Registers(Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: EEE_STATE :: SWITCH_RESV [31:27] */
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_MASK                0xf8000000
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_SHIFT               27
+#define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: EEE_STATE :: EEE_STATE [26:00] */
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_MASK                  0x07ffffff
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_SHIFT                 0
+#define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RED_CONTROL - RED Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_CONTROL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: RED_CONTROL :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RED_CONTROL :: RED_EN [08:00] */
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_MASK                   0x000001ff
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_SHIFT                  0
+#define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TC2RED_PROFILE_TABLE - RED Table Configuration Register
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_WR_RD [15:15] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_MASK 0x00008000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_SHIFT 15
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: SWITCH_RESV [14:13] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_MASK     0x00006000
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_SHIFT    13
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_ADDR [12:04] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_MASK 0x00001ff0
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_SHIFT 4
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_DATA [03:00] */
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_SHIFT 0
+#define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_EGRESS_BYPASS - RED Egress Bypass Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_MASK        0x0000fe00
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_EGRESS_BYPASS :: RED_EGRESS_BYPASS [08:00] */
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_DEFAULT 0x00000080
+
+/***************************************************************************
+ *RED_AQD_CONTROL - RED AQD Control Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_AQD_CONTROL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_2 [15:12] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_MASK        0x0000f000
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_SHIFT       12
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_PERIOD [11:08] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_MASK           0x00000f00
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_SHIFT          8
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_DEFAULT        0x00000008
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_1 [07:06] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_MASK        0x000000c0
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_SHIFT       6
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_RST [05:05] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_MASK              0x00000020
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_SHIFT             5
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: RED_FAST_CORR [04:04] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_MASK        0x00000010
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_SHIFT       4
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_0 [03:00] */
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_MASK        0x0000000f
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_SHIFT       0
+#define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RED_EXPONENT - RED AQD Weighted Factor Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_EXPONENT :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: RED_EXPONENT :: SWITCH_RESV [15:08] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_MASK             0x0000ff00
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_SHIFT            8
+#define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_EXPONENT :: RED_EXPONENT [07:00] */
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_MASK            0x000000ff
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_DEFAULT         0x00000005
+
+/***************************************************************************
+ *RED_DROP_ADD_TO_MIB - RED Drop Add to MIB Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_MASK      0x0000fe00
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_SHIFT     9
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: RED_DROP_ADD_TO_MIB [08:00] */
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_MASK 0x000001ff
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *RED_PROFILE_DEFAULT - Default RED profile Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: SWITCH_RESV [31:04] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_MASK      0xfffffff0
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_SHIFT     4
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE_DEFAULT :: RED_PROFILE_DEFAULT [03:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_MASK 0x0000000f
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WRED_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_REG_SPARE0 :: WRED_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_SHIFT     0
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *WRED_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: WRED_REG_SPARE1 :: WRED_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_MASK      0xffffffff
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_SHIFT     0
+#define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RED_PROFILE0 - RED profile 0 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE0 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE0 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE0 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE0 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE1 - RED profile 1 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE1 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE1 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE1 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE1 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE2 - RED profile 2 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE2 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE2 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE2 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE2 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE3 - RED profile 3 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE3 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE3 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE3 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE3 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE4 - RED profile 4 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE4 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE4 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE4 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE4 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE5 - RED profile 5 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE5 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE5 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE5 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE5 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE6 - RED profile 6 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE6 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE6 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE6 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE6 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE7 - RED profile 7 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE7 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE7 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE7 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE7 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE8 - RED profile 8 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE8 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE8 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE8 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE8 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE9 - RED profile 9 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE9 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_MASK             0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_SHIFT            26
+#define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE9 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_MASK           0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_SHIFT          22
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE9 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_MASK             0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_SHIFT            11
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE9 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_MASK             0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_SHIFT            0
+#define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RED_PROFILE10 - RED profile 10 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE10 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE10 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE10 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE10 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_PROFILE11 - RED profile 11 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE11 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE11 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE11 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE11 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_PROFILE12 - RED profile 12 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE12 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE12 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE12 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE12 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_PROFILE13 - RED profile 13 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE13 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE13 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE13 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE13 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_PROFILE14 - RED profile 14 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE14 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE14 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE14 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE14 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_PROFILE15 - RED profile 15 Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PROFILE15 :: SWITCH_RESV [31:26] */
+#define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_SHIFT           26
+#define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE15 :: RED_DROP_PROB [25:22] */
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_MASK          0x03c00000
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_SHIFT         22
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE15 :: RED_MAX_THD [21:11] */
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_MASK            0x003ff800
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_SHIFT           11
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: RED_PROFILE15 :: RED_MIN_THD [10:00] */
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_MASK            0x000007ff
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_SHIFT           0
+#define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_DEFAULT         0x00000000
+
+/***************************************************************************
+ *RED_DROP_CNTR_RST - RED Drop Counter Reset Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_MASK        0x0000fe00
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_SHIFT       9
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: RED_DROP_CNTR_RST :: RED_DROP_CNTR_RST [08:00] */
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_MASK  0x000001ff
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P0 - PORT 0 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P0 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P1 - PORT 1 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P1 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P2 - PORT 2 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P2 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P3 - PORT 3 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P3 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P4 - PORT 4 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P4 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P5 - PORT 5 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P5 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_P7 - PORT 7 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_P7 :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_PKT_DROP_CNTR_IMP - PORT 8 RED Packet Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_PKT_DROP_CNTR_IMP :: RED_PKT_DROP_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P0 - PORT 0 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P0 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P1 - PORT 1 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P1 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P2 - PORT 2 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P2 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P3 - PORT 3 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P3 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P4 - PORT 4 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P4 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P5 - PORT 5 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P5 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_P7 - PORT 7 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P7 :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *RED_BYTE_DROP_CNTR_IMP - PORT 8 RED Byte Drop Counter Register
+ ***************************************************************************/
+/* SWITCH_CORE :: RED_BYTE_DROP_CNTR_IMP :: RED_BYTE_DROP_CNTR [63:00] */
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_SHIFT 0
+#define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000
+
+/***************************************************************************
+ *CFP_ACC - CFP Access Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_ACC :: RD_STS [31:28] */
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_MASK                       0xf0000000
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_SHIFT                      28
+#define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SERCH_STS [27:27] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_MASK                    0x08000000
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_SHIFT                   27
+#define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_DEFAULT                 0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_1 [26:24] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_MASK                0x07000000
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_SHIFT               24
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: XCESS_ADDR [23:16] */
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_MASK                   0x00ff0000
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_SHIFT                  16
+#define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: TCAM_RST [15:15] */
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_MASK                     0x00008000
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_SHIFT                    15
+#define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_DEFAULT                  0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: RAM_SEL [14:10] */
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_MASK                      0x00007c00
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_SHIFT                     10
+#define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_DEFAULT                   0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_0 [09:06] */
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_MASK                0x000003c0
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_SHIFT               6
+#define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: KEY_0_1_RAW_ENC [05:05] */
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_MASK              0x00000020
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_SHIFT             5
+#define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: CFP_RAM_CLEAR [04:04] */
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_MASK                0x00000010
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_SHIFT               4
+#define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: OP_SEL [03:01] */
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_MASK                       0x0000000e
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_SHIFT                      1
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: CFP_ACC :: OP_STR_DONE [00:00] */
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_MASK                  0x00000001
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *RATE_METER_GLOBAL_CTL - CFP RATE METER Global Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_SHIFT 16
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: SWITCH_RESV [15:03] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_MASK    0x0000fff8
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_SHIFT   3
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: RATE_REFRESH_EN [02:02] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_MASK 0x00000004
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_SHIFT 2
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: PKT_LEN_CORR [01:00] */
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_MASK   0x00000003
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_SHIFT  0
+#define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CFP_DATA0 - CFP TCAM Data 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA0 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA1 - CFP TCAM Data 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA1 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA2 - CFP TCAM Data 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA2 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA3 - CFP TCAM Data 3 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA3 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA4 - CFP TCAM Data 4 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA4 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA5 - CFP TCAM Data 5 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA5 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA6 - CFP TCAM Data 6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA6 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_DATA7 - CFP TCAM Data 7 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_DATA7 :: TCAM_DATA [31:00] */
+#define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK0 - CFP TCAM Mask 0  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK0 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK1 - CFP TCAM Mask 1  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK1 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK2 - CFP TCAM Mask 2  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK2 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK3 - CFP TCAM Mask 3  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK3 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK4 - CFP TCAM Mask 4  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK4 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK5 - CFP TCAM Mask 5  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK5 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK6 - CFP TCAM Mask 6  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK6 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *CFP_MASK7 - CFP TCAM Mask 7  Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_MASK7 :: TCAM_MASK [31:00] */
+#define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_MASK                  0xffffffff
+#define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_SHIFT                 0
+#define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_DEFAULT               0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA0 - CFP Action/Policy Data 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_DSCP_IB [31:26] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_MASK            0xfc000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_SHIFT           26
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_FWRD_MAP_IB [25:24] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_MASK     0x03000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_SHIFT    24
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: DST_MAP_IB [23:14] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_MASK             0x00ffc000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_SHIFT            14
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_TC [13:13] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_MASK              0x00002000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_SHIFT             13
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_TC [12:10] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_MASK                 0x00001c00
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_SHIFT                10
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: LOOP_BK_EN [09:09] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_MASK             0x00000200
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_SHIFT            9
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: REASON_CODE [08:03] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_MASK            0x000001f8
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_SHIFT           3
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: STP_BYP [02:02] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_MASK                0x00000004
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_SHIFT               2
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: EAP_BYP [01:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_MASK                0x00000002
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_SHIFT               1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA0 :: VLAN_BYP [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_MASK               0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_SHIFT              0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA1 - CFP Action/Policy Data 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA1 :: RED_DEFAULT [31:31] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_MASK            0x80000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_SHIFT           31
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_COLOR [30:29] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_MASK              0x60000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_SHIFT             29
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_COLOR [28:28] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_MASK           0x10000000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_SHIFT          28
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHAIN_ID [27:20] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_MASK               0x0ff00000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_SHIFT              20
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_OB [19:19] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_MASK         0x00080000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_SHIFT        19
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_DSCP_OB [18:13] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_MASK            0x0007e000
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_SHIFT           13
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_FWRD_MAP_OB [12:11] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_MASK     0x00001800
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_SHIFT    11
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: DST_MAP_OB [10:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_MASK             0x000007fe
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_SHIFT            1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_IB [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_MASK         0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_SHIFT        0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_DEFAULT      0x00000000
+
+/***************************************************************************
+ *ACT_POL_DATA2 - CFP Action/Policy Data 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: ACT_POL_DATA2 :: SWITCH_RESV [31:08] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_MASK            0xffffff00
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_SHIFT           8
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: DEI_RMK_DISABLE [07:07] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_MASK        0x00000080
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_SHIFT       7
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_DEFAULT     0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: CPCP_RMK_DISABLE [06:06] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_MASK       0x00000040
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_SHIFT      6
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: SPCP_RMK_DISABLE [05:05] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_MASK       0x00000020
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_SHIFT      5
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: NEW_TC_O [04:02] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_MASK               0x0000001c
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_SHIFT              2
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: CHANGE_TC_O [01:01] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_MASK            0x00000002
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_SHIFT           1
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: ACT_POL_DATA2 :: MAC_LIMIT_BYPASS [00:00] */
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_MASK       0x00000001
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_SHIFT      0
+#define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RATE_METER0 - CFP RATE METER DATA 0 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER0 :: SWITCH_RESV [31:05] */
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_MASK              0xffffffe0
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_SHIFT             5
+#define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: POLICER_MODE [04:03] */
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_MASK             0x00000018
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_SHIFT            3
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: CF [02:02] */
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_MASK                       0x00000004
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_SHIFT                      2
+#define BCHP_SWITCH_CORE_RATE_METER0_CF_DEFAULT                    0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: POLICER_ACTION [01:01] */
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_MASK           0x00000002
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_SHIFT          1
+#define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: RATE_METER0 :: CM [00:00] */
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_MASK                       0x00000001
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_SHIFT                      0
+#define BCHP_SWITCH_CORE_RATE_METER0_CM_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *RATE_METER1 - CFP RATE METER DATA 1 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER1 :: SWITCH_RESV [31:23] */
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_MASK              0xff800000
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_SHIFT             23
+#define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER1 :: EIR_TK_BKT [22:00] */
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_MASK               0x007fffff
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_SHIFT              0
+#define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RATE_METER2 - CFP RATE METER DATA 2 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER2 :: SWITCH_RESV [31:20] */
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_MASK              0xfff00000
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_SHIFT             20
+#define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER2 :: EIR_BKT_SIZE [19:00] */
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_MASK             0x000fffff
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_SHIFT            0
+#define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RATE_METER3 - CFP RATE METER DATA 3 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER3 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_MASK              0xfff80000
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_SHIFT             19
+#define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER3 :: EIR_REF_CNT [18:00] */
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_MASK              0x0007ffff
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *RATE_METER4 - CFP RATE METER DATA 4 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER4 :: SWITCH_RESV [31:23] */
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_MASK              0xff800000
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_SHIFT             23
+#define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER4 :: CIR_TK_BKT [22:00] */
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_MASK               0x007fffff
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_SHIFT              0
+#define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *RATE_METER5 - CFP RATE METER DATA 5 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER5 :: SWITCH_RESV [31:20] */
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_MASK              0xfff00000
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_SHIFT             20
+#define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER5 :: CIR_BKT_SIZE [19:00] */
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_MASK             0x000fffff
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_SHIFT            0
+#define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RATE_METER6 - CFP RATE METER DATA 6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: RATE_METER6 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_MASK              0xfff80000
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_SHIFT             19
+#define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: RATE_METER6 :: CIR_REF_CNT [18:00] */
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_MASK              0x0007ffff
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_SHIFT             0
+#define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *TC2COLOR - TC to COLOR Mapping Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: TC2COLOR :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_MASK       0xffff0000
+#define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_SHIFT      16
+
+/* SWITCH_CORE :: TC2COLOR :: SWITCH_RESV [15:11] */
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_MASK                 0x0000f800
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_SHIFT                11
+#define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_COLOR [10:09] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_MASK          0x00000600
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_SHIFT         9
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_DEI [08:08] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_MASK            0x00000100
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_SHIFT           8
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_TC [07:05] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_MASK             0x000000e0
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_SHIFT            5
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_ING_PORT [04:01] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_MASK       0x0000001e
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_SHIFT      1
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_DEFAULT    0x00000000
+
+/* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_RW [00:00] */
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_MASK             0x00000001
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_SHIFT            0
+#define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_GREEN_CNTR - Policer Green color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_GREEN_CNTR :: GREEN_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_MASK           0xffffffff
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_SHIFT          0
+#define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *STAT_YELLOW_CNTR - Policer Yellow color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_YELLOW_CNTR :: YELLOW_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_MASK         0xffffffff
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_SHIFT        0
+#define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_RED_CNTR - Policer RED color statistic counter
+ ***************************************************************************/
+/* SWITCH_CORE :: STAT_RED_CNTR :: RED_CNTR [31:00] */
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_MASK               0xffffffff
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_SHIFT              0
+#define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *TCAM_BIST_CONTROL - TCAM BIST Control Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_DONE [31:31] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_MASK     0x80000000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_SHIFT    31
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_1 [30:17] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_MASK      0x7ffe0000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_SHIFT     17
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_TEST_COMPARE [16:16] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_MASK  0x00010000
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_SHIFT 16
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_SKIP_ERR_CNT [15:08] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_STATUS_SEL [07:04] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_SHIFT 4
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_0 [03:02] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_MASK      0x0000000c
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_SHIFT     2
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_DEFAULT   0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_SEL [01:01] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_MASK           0x00000002
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_SHIFT          1
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_EN [00:00] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_MASK       0x00000001
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_SHIFT      0
+#define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TCAM_BIST_STATUS - TCAM BIST Status Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_BIST_STATUS :: SWITCH_RESV [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_MASK         0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_SHIFT        16
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: TCAM_BIST_STATUS :: TCAM_BIST_STATUS [15:00] */
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK    0x0000ffff
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT   0
+#define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TCAM_TEST_COMPARE_STATUS - TCAM Test Compare Status Registers (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_1 [31:16] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_MASK 0xffff0000
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_SHIFT 16
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT [15:15] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_MASK    0x00008000
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_SHIFT   15
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_0 [14:07] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_MASK 0x00007f80
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_SHIFT 7
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000
+
+/* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT_ADDR [06:00] */
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_MASK 0x0000007f
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_SHIFT 0
+#define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CFP_REG_SPARE0 - Spare 0 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_REG_SPARE0 :: CFP_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_SHIFT       0
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CFP_REG_SPARE1 - Spare 1 Register (Not2Release)
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_REG_SPARE1 :: CFP_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_MASK        0xffffffff
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_SHIFT       0
+#define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CFP_CTL_REG - CFP Control Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: CFP_CTL_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: CFP_CTL_REG :: SWITCH_RESV [15:09] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_MASK              0x0000fe00
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_SHIFT             9
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: CFP_CTL_REG :: CFP_EN_MAP [08:00] */
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_MASK               0x000001ff
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_SHIFT              0
+#define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_DEFAULT            0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_0 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_0 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_1 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_1 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_2 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_2 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_3 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_3 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_4 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_4 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_5 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_5 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_6 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_6 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_7 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_7 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_A_0_8_8 - UDFs of slice 0 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_A_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_A_0_8_8 :: CFG_UDF_0_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_0 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_0 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_1 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_1 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_2 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_2 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_3 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_3 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_4 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_4 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_5 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_5 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_6 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_6 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_7 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_7 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_A_0_8_8 - UDFs of slice 1 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_A_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_A_0_8_8 :: CFG_UDF_1_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_0 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_0 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_1 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_1 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_2 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_2 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_3 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_3 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_4 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_4 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_5 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_5 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_6 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_6 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_7 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_7 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_A_0_8_8 - UDFs of slice 2 for IPv4 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_A_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_A_0_8_8 :: CFG_UDF_2_A_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_0 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_0 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_1 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_1 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_2 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_2 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_3 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_3 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_4 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_4 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_5 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_5 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_6 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_6 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_7 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_7 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_B_0_8_8 - UDFs of slice 0 for IPv6 packet Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_B_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_B_0_8_8 :: CFG_UDF_0_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_0 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_0 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_1 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_1 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_2 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_2 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_3 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_3 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_4 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_4 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_5 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_5 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_6 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_6 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_7 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_7 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_B_0_8_8 - UDFs of slice 1 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_B_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_B_0_8_8 :: CFG_UDF_1_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_0 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_0 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_1 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_1 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_2 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_2 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_3 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_3 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_4 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_4 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_5 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_5 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_6 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_6 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_7 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_7 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_B_0_8_8 - UDFs of slice 2 for IPv6 Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_B_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_B_0_8_8 :: CFG_UDF_2_B_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_0 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_0 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_1 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_1 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_2 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_2 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_3 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_3 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_4 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_4 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_5 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_5 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_6 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_6 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_7 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_7 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_C_0_8_8 - UDFs of slice 0 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_C_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_C_0_8_8 :: CFG_UDF_0_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_0 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_0 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_1 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_1 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_2 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_2 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_3 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_3 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_4 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_4 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_5 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_5 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_6 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_6 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_7 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_7 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_1_C_0_8_8 - UDFs of slice 1 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_1_C_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_1_C_0_8_8 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_0 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_0 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_1 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_1 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_2 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_2 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_3 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_3 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_4 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_4 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_5 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_5 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_6 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_6 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_7 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_7 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_2_C_0_8_8 - UDFs of slice 2 for none-IP Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_2_C_0_8_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_reserved_for_padding0_MASK  0xffffff00
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_2_C_0_8_8 :: CFG_UDF_1_C_0_8 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_MASK        0x000000ff
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_SHIFT       0
+#define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_DEFAULT     0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_0 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_0 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_0 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_1 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_1 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_1 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_2 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_2 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_2 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_3 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_3 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_3 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_4 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_4 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_4 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_5 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_5 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_5 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_6 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_6 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_6 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_7 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_7 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_7 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_8 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_8 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_8 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_9 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_9 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_9 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_MASK      0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_SHIFT     0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_DEFAULT   0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_10 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_10 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_10 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_MASK     0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_SHIFT    0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_DEFAULT  0x00000000
+
+/***************************************************************************
+ *UDF_0_D_0_11_11 - UDFs for IPv6 Chain Rule Registers
+ ***************************************************************************/
+/* SWITCH_CORE :: UDF_0_D_0_11_11 :: reserved_for_padding0 [31:08] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_reserved_for_padding0_MASK 0xffffff00
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_reserved_for_padding0_SHIFT 8
+
+/* SWITCH_CORE :: UDF_0_D_0_11_11 :: CFG_UDF_0_D_0_11 [07:00] */
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_MASK     0x000000ff
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_SHIFT    0
+#define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_DEFAULT  0x00000000
+
+/***************************************************************************
+ *OTP_CTL_REG - CPU OTP Control RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG :: BYPASS_OTP_CLK [31:31] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_MASK           0x80000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_SHIFT          31
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: SWITCH_RESV [30:29] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_MASK              0x60000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_SHIFT             29
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: CPU_DEBUG_SEL [28:25] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_MASK            0x1e000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_SHIFT           25
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_DEFAULT         0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: BURST_STAT_SEL [24:24] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_MASK           0x01000000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_SHIFT          24
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: ACCESS_MODE [23:22] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_MASK              0x00c00000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_SHIFT             22
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: OTP_PROG_EN [21:21] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_MASK              0x00200000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_SHIFT             21
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: OTP_DEBUG_MODE [20:20] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_MASK           0x00100000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_SHIFT          20
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_CONTINUE_ON_FAIL [19:19] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_MASK     0x00080000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_SHIFT    19
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_DEFAULT  0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_TIME_MARGIN [18:16] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_MASK          0x00070000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_SHIFT         16
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_SADBYP [15:15] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_MASK               0x00008000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_SHIFT              15
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: UNUSED [14:14] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_MASK                   0x00004000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_SHIFT                  14
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_DEFAULT                0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PBYP [13:13] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_MASK                 0x00002000
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_SHIFT                13
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PCOUNT [12:10] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_MASK               0x00001c00
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_SHIFT              10
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_VSEL [09:06] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_MASK                 0x000003c0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_SHIFT                6
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: WRP_PROG_SEL [05:05] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_MASK             0x00000020
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_SHIFT            5
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: COMMAND [04:01] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_MASK                  0x0000001e
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_SHIFT                 1
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_DEFAULT               0x00000000
+
+/* SWITCH_CORE :: OTP_CTL_REG :: START [00:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_MASK                    0x00000001
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_SHIFT                   0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_START_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *OTP_ADDR_REG - CPU OTP Address RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_ADDR_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_MASK   0xffff0000
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_SHIFT  16
+
+/* SWITCH_CORE :: OTP_ADDR_REG :: CPU_ADDR [15:00] */
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_MASK                0x0000ffff
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_SHIFT               0
+#define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_DEFAULT             0x00000000
+
+/***************************************************************************
+ *OTP_STS_REG - CPU OTP Status RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_STS_REG :: reserved_for_padding0 [31:16] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_MASK    0xffff0000
+#define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_SHIFT   16
+
+/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_0 [15:12] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_MASK                 0x0000f000
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_SHIFT                12
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: CONTROL_ERR [11:11] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_MASK              0x00000800
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_SHIFT             11
+#define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_DEFAULT           0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_ERROR [10:10] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_MASK                0x00000400
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_SHIFT               10
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INVALID_COMMAND [09:09] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_MASK          0x00000200
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_SHIFT         9
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: UNUSED_1 [08:08] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_MASK                 0x00000100
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_SHIFT                8
+#define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INIT_WAIT_DONE [07:07] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_MASK           0x00000080
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_SHIFT          7
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_DEFAULT        0x00000001
+
+/* SWITCH_CORE :: OTP_STS_REG :: PROG_BLOCKED [06:06] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_MASK             0x00000040
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_SHIFT            6
+#define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_DEFAULT          0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: INVALID_PROG_REQ [05:05] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_MASK         0x00000020
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_SHIFT        5
+#define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_DEFAULT      0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_FAIL [04:04] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_MASK                 0x00000010
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_SHIFT                4
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_BUSY [03:03] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_MASK                 0x00000008
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_SHIFT                3
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_DOUT [02:02] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_MASK                 0x00000004
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_SHIFT                2
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_DEFAULT              0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: WRP_DATA_READY [01:01] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_MASK           0x00000002
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_SHIFT          1
+#define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: OTP_STS_REG :: COMMAND_DONE [00:00] */
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_MASK             0x00000001
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_SHIFT            0
+#define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *OTP_WR_DATA - CPU OTP Write Data RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_WR_DATA :: CPU_WR_DATA [31:00] */
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *OTP_RD_DATA - CPU OTP Read Data RegistersNot2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_RD_DATA :: CPU_RD_DATA [31:00] */
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_MASK              0xffffffff
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_SHIFT             0
+#define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_DEFAULT           0x00000000
+
+/***************************************************************************
+ *IO_SR_CTL - I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_SR_CTL :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_MASK                0xfff80000
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_SHIFT               19
+#define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_DEFAULT             0x00000000
+
+/* SWITCH_CORE :: IO_SR_CTL :: IO_SR_CTL [18:00] */
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_MASK                  0x0007ffff
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_SHIFT                 0
+#define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_DEFAULT               0x00000600
+
+/***************************************************************************
+ *IO_DS_SEL0 - I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_DS_SEL0 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_MASK               0xfff80000
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_SHIFT              19
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: IO_DS_SEL0 :: IO_DS_SEL0 [18:00] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_MASK                0x0007ffff
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_SHIFT               0
+#define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_DEFAULT             0x0007ffff
+
+/***************************************************************************
+ *IO_DS_SEL2 - I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: IO_DS_SEL2 :: SWITCH_RESV [31:19] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_MASK               0xfff80000
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_SHIFT              19
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_DEFAULT            0x00000000
+
+/* SWITCH_CORE :: IO_DS_SEL2 :: IO_DS_SEL2 [18:00] */
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_MASK                0x0007ffff
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_SHIFT               0
+#define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_DEFAULT             0x0007ffff
+
+/***************************************************************************
+ *GMII_IO_SR_CTL - GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_SR_CTL :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_MASK           0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_SHIFT          3
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_DEFAULT        0x00000000
+
+/* SWITCH_CORE :: GMII_IO_SR_CTL :: GMII_IO_SR_CTL [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_MASK        0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_SHIFT       0
+#define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GMII_IO_DS_SEL0 - GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_MASK          0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_SHIFT         3
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: GMII_IO_DS_SEL0 :: GMII_IO_DS_SEL0 [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_MASK      0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_SHIFT     0
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_DEFAULT   0x00000007
+
+/***************************************************************************
+ *GMII_IO_DS_SEL1 - GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: SWITCH_RESV [31:03] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_MASK          0xfffffff8
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_SHIFT         3
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_DEFAULT       0x00000000
+
+/* SWITCH_CORE :: GMII_IO_DS_SEL1 :: GMII_IO_DS_SEL1 [02:00] */
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_MASK      0x00000007
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_SHIFT     0
+#define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_DEFAULT   0x00000007
+
+/***************************************************************************
+ *OTP_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG_SPARE0 :: OTP_CTL_REG_SPARE0 [31:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_SHIFT 0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release
+ ***************************************************************************/
+/* SWITCH_CORE :: OTP_CTL_REG_SPARE1 :: OTP_CTL_REG_SPARE1 [31:00] */
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_MASK 0xffffffff
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_SHIFT 0
+#define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_CORE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_switch_fcb.h b/include/linux/brcmstb/3390b0/bchp_switch_fcb.h
new file mode 100644
index 000000000000..cbe2b9aff6b6
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_switch_fcb.h
@@ -0,0 +1,415 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:19 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_FCB_H__
+#define BCHP_SWITCH_FCB_H__
+
+/***************************************************************************
+ *SWITCH_FCB
+ ***************************************************************************/
+#define BCHP_SWITCH_FCB_FCB_CONTROL              0x04e40400 /* [RW] Tx Pause Enable Register */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL 0x04e40404 /* [RW] P8 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT       0x04e40408 /* [RW] P8 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL 0x04e4040c /* [RW] P5 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT       0x04e40410 /* [RW] P5 Release Timeout Register */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT 0x04e40414 /* [RW] P5 Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL 0x04e40418 /* [RW] P4 Failover Release Control Register */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT       0x04e4041c /* [RW] P4 Release Timeout Register */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT 0x04e40420 /* [RW] P4 Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL 0x04e40424 /* [RW] LAN Failover Release Control Register */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT      0x04e40428 /* [RW] LAN Release Timeout Register */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT 0x04e4042c /* [RW] LAN Release Delay Timeout Register */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL 0x04e40430 /* [RW] FCB Pause Override Control Register */
+
+/***************************************************************************
+ *FCB_CONTROL - Tx Pause Enable Register
+ ***************************************************************************/
+/* SWITCH_FCB :: FCB_CONTROL :: reserved0 [31:10] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_MASK                 0xfffffc00
+#define BCHP_SWITCH_FCB_FCB_CONTROL_reserved0_SHIFT                10
+
+/* SWITCH_FCB :: FCB_CONTROL :: fcb_en [09:09] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_MASK                    0x00000200
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_SHIFT                   9
+#define BCHP_SWITCH_FCB_FCB_CONTROL_fcb_en_DEFAULT                 0x00000000
+
+/* SWITCH_FCB :: FCB_CONTROL :: failover_dis [08:00] */
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_MASK              0x000001ff
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_SHIFT             0
+#define BCHP_SWITCH_FCB_FCB_CONTROL_failover_dis_DEFAULT           0x00000000
+
+/***************************************************************************
+ *P8_FAILOVER_RELEASE_CONTROL - P8 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P8_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P8_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P8_RELEASE_TIMEOUT - P8 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P8_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P8_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P5_FAILOVER_RELEASE_CONTROL - P5 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P5_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P5_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P5_RELEASE_TIMEOUT - P5 Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P5_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P5_RELEASE_DELAY_TIMEOUT - P5 Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_MASK    0xfffffe00
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT   9
+
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P5_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_P5_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *P4_FAILOVER_RELEASE_CONTROL - P4 Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: P4_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_P4_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *P4_RELEASE_TIMEOUT - P4 Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_MASK          0xfffe0000
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_reserved0_SHIFT         17
+
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_MASK   0x00010000
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_SHIFT  16
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_MASK    0x0000ffff
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_SHIFT   0
+#define BCHP_SWITCH_FCB_P4_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *P4_RELEASE_DELAY_TIMEOUT - P4 Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_MASK    0xfffffe00
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT   9
+
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: P4_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_P4_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *LAN_FAILOVER_RELEASE_CONTROL - LAN Failover Release Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: reserved0 [31:24] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_reserved0_SHIFT 24
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: queue_release_mask [23:16] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_MASK 0x00ff0000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_SHIFT 16
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_queue_release_mask_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q7_release_state [15:14] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_MASK 0x0000c000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_SHIFT 14
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q7_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q6_release_state [13:12] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_MASK 0x00003000
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_SHIFT 12
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q6_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q5_release_state [11:10] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_MASK 0x00000c00
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_SHIFT 10
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q5_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q4_release_state [09:08] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_MASK 0x00000300
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_SHIFT 8
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q4_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q3_release_state [07:06] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_MASK 0x000000c0
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_SHIFT 6
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q3_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q2_release_state [05:04] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_MASK 0x00000030
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_SHIFT 4
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q2_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q1_release_state [03:02] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_MASK 0x0000000c
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_SHIFT 2
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q1_release_state_DEFAULT 0x00000001
+
+/* SWITCH_FCB :: LAN_FAILOVER_RELEASE_CONTROL :: Q0_release_state [01:00] */
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_MASK 0x00000003
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_SHIFT 0
+#define BCHP_SWITCH_FCB_LAN_FAILOVER_RELEASE_CONTROL_Q0_release_state_DEFAULT 0x00000001
+
+/***************************************************************************
+ *LAN_RELEASE_TIMEOUT - LAN Release Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_MASK         0xfffe0000
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_reserved0_SHIFT        17
+
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timer_en [16:16] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_MASK  0x00010000
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_SHIFT 16
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_RELEASE_TIMEOUT :: release_timeout [15:00] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_MASK   0x0000ffff
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_SHIFT  0
+#define BCHP_SWITCH_FCB_LAN_RELEASE_TIMEOUT_release_timeout_DEFAULT 0x000001ff
+
+/***************************************************************************
+ *LAN_RELEASE_DELAY_TIMEOUT - LAN Release Delay Timeout Register
+ ***************************************************************************/
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: reserved0 [31:09] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_MASK   0xfffffe00
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_reserved0_SHIFT  9
+
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timer_en [08:08] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_MASK 0x00000100
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_SHIFT 8
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timer_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: LAN_RELEASE_DELAY_TIMEOUT :: release_timeout [07:00] */
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_MASK 0x000000ff
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_SHIFT 0
+#define BCHP_SWITCH_FCB_LAN_RELEASE_DELAY_TIMEOUT_release_timeout_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *FCB_PAUSE_OVERRIDE_CONTROL - FCB Pause Override Control Register
+ ***************************************************************************/
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: reserved0 [31:18] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_reserved0_MASK  0xfffc0000
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_reserved0_SHIFT 18
+
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: tx_pause_ovrd_en [17:09] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_MASK 0x0003fe00
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_SHIFT 9
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_en_DEFAULT 0x00000000
+
+/* SWITCH_FCB :: FCB_PAUSE_OVERRIDE_CONTROL :: tx_pause_ovrd [08:00] */
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_MASK 0x000001ff
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_SHIFT 0
+#define BCHP_SWITCH_FCB_FCB_PAUSE_OVERRIDE_CONTROL_tx_pause_ovrd_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_FCB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_switch_reg.h b/include/linux/brcmstb/3390b0/bchp_switch_reg.h
new file mode 100644
index 000000000000..dbb9334b4154
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_switch_reg.h
@@ -0,0 +1,1478 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:12 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SWITCH_REG_H__
+#define BCHP_SWITCH_REG_H__
+
+/***************************************************************************
+ *SWITCH_REG
+ ***************************************************************************/
+#define BCHP_SWITCH_REG_SWITCH_CNTRL             0x04e40000 /* [RW] Switch Control Register */
+#define BCHP_SWITCH_REG_SWITCH_STATUS            0x04e40004 /* [RO] Switch Status Register */
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG       0x04e40008 /* [RW] Direct Data Write Register */
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG        0x04e4000c /* [RO] Direct Data Read Register */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT 0x04e40010 /* [RW] LED Serial Refresh Time Unit Register */
+#define BCHP_SWITCH_REG_SWITCH_REVISION          0x04e40018 /* [RO] SWITCH Revision Control Register */
+#define BCHP_SWITCH_REG_PHY_REVISION             0x04e4001c /* [RO] PHY Revision Control Register */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL           0x04e40020 /* [RW] PHY Test Control Register */
+#define BCHP_SWITCH_REG_QPHY_CNTRL               0x04e40024 /* [RW] Quad GPHY Control Register */
+#define BCHP_SWITCH_REG_QPHY_STATUS              0x04e40028 /* [RO] Quad GPHY Status Register */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL     0x04e40088 /* [RW] LED port Blink Rate Control Register */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL         0x04e4008c /* [RW] LED Serial Control Register */
+#define BCHP_SWITCH_REG_LED_0_CNTRL              0x04e40090 /* [RW] LED port 0 Control Register */
+#define BCHP_SWITCH_REG_LED_1_CNTRL              0x04e40094 /* [RW] LED port 1 Control Register */
+#define BCHP_SWITCH_REG_LED_2_CNTRL              0x04e40098 /* [RW] LED port 2 Control Register */
+#define BCHP_SWITCH_REG_LED_3_CNTRL              0x04e4009c /* [RW] LED port 3 Control Register */
+#define BCHP_SWITCH_REG_LED_4_CNTRL              0x04e400a0 /* [RW] LED port 4 Control Register */
+#define BCHP_SWITCH_REG_LED_5_CNTRL              0x04e400a4 /* [RW] LED port 5 Control Register */
+#define BCHP_SWITCH_REG_LED_7_CNTRL              0x04e400a8 /* [RW] LED port 7 Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL            0x04e400b0 /* [RW] RGMII port 9 Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS        0x04e400b4 /* [RW] RGMII port 9 InBand Status Register */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL 0x04e400b8 /* [RW] RGMII port 9 RX Clock Delay Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL           0x04e400bc /* [RW] RGMII port 10 Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS       0x04e400c0 /* [RW] RGMII port 10 InBand Status Register */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL 0x04e400c4 /* [RW] RGMII port 10 RX Clock Delay Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL     0x04e40150 /* [RW] RGMII port 9 ATE RX Control Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS    0x04e40154 /* [RO] RGMII port 9 ATE RX Status Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0   0x04e40158 /* [RW] RGMII port 9 ATE TX Control 0 Register */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1   0x04e4015c /* [RW] RGMII port 9 ATE TX Control 1 Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL    0x04e40160 /* [RW] RGMII port 10 ATE RX Control Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS   0x04e40164 /* [RO] RGMII port 10 ATE RX Status Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0  0x04e40168 /* [RW] RGMII port 10 ATE TX Control 0 Register */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1  0x04e4016c /* [RW] RGMII port 10 ATE TX Control 1 Register */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL      0x04e401a8 /* [RW] Aggregate LED Control Register */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL 0x04e401ac /* [RW] Aggregate LED Blink Rate Control Register */
+#define BCHP_SWITCH_REG_SPARE_CNTRL              0x04e401b0 /* [RW] Spare Control Register */
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL    0x04e401b4 /* [RW] Switch PHY Interrupt Control Register */
+
+/***************************************************************************
+ *SWITCH_CNTRL - Switch Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_CNTRL :: reserved0 [31:15] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_MASK                0xffff8000
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_SHIFT               15
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p4_hs_sel [14:14] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_MASK                0x00004000
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_SHIFT               14
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p4_hs_sel_DEFAULT             0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: sw_pseudo_phy_addr [13:09] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_MASK       0x00003e00
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_SHIFT      9
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_pseudo_phy_addr_DEFAULT    0x0000001d
+
+/* SWITCH_REG :: SWITCH_CNTRL :: sw_mdio_en [08:08] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_MASK               0x00000100
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_SHIFT              8
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_sw_mdio_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p5_2_5g_en [07:07] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_MASK               0x00000080
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_SHIFT              7
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p5_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p7_2_5g_en [06:06] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_MASK               0x00000040
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_SHIFT              6
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p7_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: p8_2_5g_en [05:05] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_MASK               0x00000020
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_SHIFT              5
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_p8_2_5g_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: moca_bp_en [04:04] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_MASK               0x00000010
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_SHIFT              4
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_moca_bp_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_CNTRL :: pda_mux_sel [03:03] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_MASK              0x00000008
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_SHIFT             3
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_mux_sel_DEFAULT           0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: pda_chain_en [02:02] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_MASK             0x00000004
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_SHIFT            2
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_pda_chain_en_DEFAULT          0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: spi_dis [01:01] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_MASK                  0x00000002
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_SHIFT                 1
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_spi_dis_DEFAULT               0x00000001
+
+/* SWITCH_REG :: SWITCH_CNTRL :: mdio_master_sel [00:00] */
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_MASK          0x00000001
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_SHIFT         0
+#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SWITCH_STATUS - Switch Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_STATUS :: reserved0 [31:01] */
+#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_SHIFT              1
+
+/* SWITCH_REG :: SWITCH_STATUS :: sw_init_done [00:00] */
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_MASK            0x00000001
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_SHIFT           0
+#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DIR_DATA_WRITE_REG - Direct Data Write Register
+ ***************************************************************************/
+/* SWITCH_REG :: DIR_DATA_WRITE_REG :: write_data [31:00] */
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_MASK         0xffffffff
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_SHIFT        0
+#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_DEFAULT      0x00000000
+
+/***************************************************************************
+ *DIR_DATA_READ_REG - Direct Data Read Register
+ ***************************************************************************/
+/* SWITCH_REG :: DIR_DATA_READ_REG :: read_data [31:00] */
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_MASK           0xffffffff
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_SHIFT          0
+#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_SERIAL_REFRESH_TIME_UNIT - LED Serial Refresh Time Unit Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_MASK 0xff000000
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_SHIFT 24
+
+/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: refresh_time_unit [23:00] */
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_MASK 0x00ffffff
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_SHIFT 0
+#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_DEFAULT 0x0001e847
+
+/***************************************************************************
+ *SWITCH_REVISION - SWITCH Revision Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_REVISION :: SF2_rev [31:16] */
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_MASK               0xffff0000
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_SHIFT              16
+#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_DEFAULT            0x00000000
+
+/* SWITCH_REG :: SWITCH_REVISION :: switch_top_rev [15:00] */
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_MASK        0x0000ffff
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_SHIFT       0
+#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PHY_REVISION - PHY Revision Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: PHY_REVISION :: quad_phy_rev [31:16] */
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_MASK             0xffff0000
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_SHIFT            16
+#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_DEFAULT          0x00000000
+
+/* SWITCH_REG :: PHY_REVISION :: single_phy_rev [15:00] */
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_MASK           0x0000ffff
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_SHIFT          0
+#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PHY_TEST_CNTRL - PHY Test Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: PHY_TEST_CNTRL :: reserved0 [31:06] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_MASK              0xffffffc0
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_SHIFT             6
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_sel [05:03] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_MASK                0x00000038
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_SHIFT               3
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_DEFAULT             0x00000000
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_mode [02:01] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_MASK          0x00000006
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_SHIFT         1
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_en [00:00] */
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_MASK            0x00000001
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_SHIFT           0
+#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_DEFAULT         0x00000000
+
+/***************************************************************************
+ *QPHY_CNTRL - Quad GPHY Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: QPHY_CNTRL :: reserved0 [31:17] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_MASK                  0xfffe0000
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_SHIFT                 17
+
+/* SWITCH_REG :: QPHY_CNTRL :: phy_phyad [16:12] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_MASK                  0x0001f000
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_SHIFT                 12
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_DEFAULT               0x00000001
+
+/* SWITCH_REG :: QPHY_CNTRL :: reserved1 [11:09] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_MASK                  0x00000e00
+#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_SHIFT                 9
+
+/* SWITCH_REG :: QPHY_CNTRL :: phy_reset [08:08] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_MASK                  0x00000100
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_SHIFT                 8
+#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_DEFAULT               0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: ck25_dis [07:07] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_MASK                   0x00000080
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_SHIFT                  7
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_DEFAULT                0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: iddq_global_pwr [06:06] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_MASK            0x00000040
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_SHIFT           6
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_DEFAULT         0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: force_dll_en [05:05] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_MASK               0x00000020
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_SHIFT              5
+#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_DEFAULT            0x00000000
+
+/* SWITCH_REG :: QPHY_CNTRL :: ext_pwr_down [04:01] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_MASK               0x0000001e
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_SHIFT              1
+#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_DEFAULT            0x0000000f
+
+/* SWITCH_REG :: QPHY_CNTRL :: iddq_bias [00:00] */
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_MASK                  0x00000001
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_SHIFT                 0
+#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_DEFAULT               0x00000001
+
+/***************************************************************************
+ *QPHY_STATUS - Quad GPHY Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: QPHY_STATUS :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_MASK                 0xffff0000
+#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_SHIFT                16
+
+/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_en [15:15] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_MASK      0x00008000
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_SHIFT     15
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_en_DEFAULT   0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: mac_gphy_cfg_test_mode [14:13] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_MASK    0x00006000
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_SHIFT   13
+#define BCHP_SWITCH_REG_QPHY_STATUS_mac_gphy_cfg_test_mode_DEFAULT 0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: lock_recovery_clk [12:09] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_MASK         0x00001e00
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_SHIFT        9
+#define BCHP_SWITCH_REG_QPHY_STATUS_lock_recovery_clk_DEFAULT      0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: pll_lock [08:08] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_MASK                  0x00000100
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_SHIFT                 8
+#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_DEFAULT               0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: energy_det_apd [07:04] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_MASK            0x000000f0
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_SHIFT           4
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_DEFAULT         0x00000000
+
+/* SWITCH_REG :: QPHY_STATUS :: energy_det_masked [03:00] */
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_MASK         0x0000000f
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_SHIFT        0
+#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_DEFAULT      0x00000000
+
+/***************************************************************************
+ *LED_BLINK_RATE_CNTRL - LED port Blink Rate Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_MASK      0xffff0000
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT     16
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT   0x00000320
+
+/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_MASK     0x0000ffff
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT    0
+#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT  0x00000320
+
+/***************************************************************************
+ *LED_SERIAL_CNTRL - LED Serial Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_MASK            0xffff0000
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_SHIFT           16
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: port_en [15:08] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_MASK              0x0000ff00
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_SHIFT             8
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: smode [07:07] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_MASK                0x00000080
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_SHIFT               7
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_DEFAULT             0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_frequency [06:06] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_MASK   0x00000040
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_SHIFT  6
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_pol [05:05] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_MASK         0x00000020
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_SHIFT        5
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_DEFAULT      0x00000000
+
+/* SWITCH_REG :: LED_SERIAL_CNTRL :: refresh_period [04:00] */
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_MASK       0x0000001f
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_SHIFT      0
+#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_DEFAULT    0x00000004
+
+/***************************************************************************
+ *LED_0_CNTRL - LED port 0 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_0_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_0_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_0_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_0_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_0_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_1_CNTRL - LED port 1 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_1_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_1_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_1_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_1_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_1_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_2_CNTRL - LED port 2 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_2_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_2_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_2_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_2_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_2_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_3_CNTRL - LED port 3 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_3_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_3_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_3_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_3_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_3_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_4_CNTRL - LED port 4 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_4_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_4_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_4_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_4_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_4_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_4_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_4_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_4_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_4_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_4_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_4_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_4_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_4_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_4_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_5_CNTRL - LED port 5 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_5_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_5_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_5_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_5_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_5_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_5_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_5_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_5_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_5_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_5_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_5_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_5_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_5_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_5_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *LED_7_CNTRL - LED port 7 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: LED_7_CNTRL :: reserved0 [31:28] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_MASK                 0xf0000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_SHIFT                28
+
+/* SWITCH_REG :: LED_7_CNTRL :: act_led_pol_sel [27:27] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_MASK           0x08000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_SHIFT          27
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_src_sel [24:24] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_MASK            0x01000000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_SHIFT           24
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: act_led_act_sel [23:22] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_MASK           0x00c00000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_SHIFT          22
+#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_sel [21:20] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_SHIFT      20
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_sel [19:18] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_SHIFT      18
+#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: tx_en_en [17:17] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_MASK                  0x00020000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_SHIFT                 17
+#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: rx_dv_en [16:16] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_MASK                  0x00010000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_SHIFT                 16
+#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_DEFAULT               0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_1000m_encode [15:14] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_MASK          0x0000c000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_SHIFT         14
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_DEFAULT       0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_100m_encode [13:12] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_MASK           0x00003000
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_SHIFT          12
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_DEFAULT        0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_10m_encode [11:10] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_MASK            0x00000c00
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_SHIFT           10
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_DEFAULT         0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: sel_no_link_encode [09:08] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_MASK        0x00000300
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_SHIFT       8
+#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: 1000m_encode [07:06] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_MASK              0x000000c0
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_SHIFT             6
+#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_DEFAULT           0x00000000
+
+/* SWITCH_REG :: LED_7_CNTRL :: 100m_encode [05:04] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_MASK               0x00000030
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_SHIFT              4
+#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_DEFAULT            0x00000001
+
+/* SWITCH_REG :: LED_7_CNTRL :: 10m_encode [03:02] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_MASK                0x0000000c
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_SHIFT               2
+#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_DEFAULT             0x00000002
+
+/* SWITCH_REG :: LED_7_CNTRL :: no_link_encode [01:00] */
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_MASK            0x00000003
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_SHIFT           0
+#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_DEFAULT         0x00000003
+
+/***************************************************************************
+ *RGMII_9_CNTRL - RGMII port 9 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_CNTRL :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_MASK               0xffff0000
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_SHIFT              16
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: col_crs_mask [15:15] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_MASK            0x00008000
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_SHIFT           15
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_col_crs_mask_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rx_err_mask [14:14] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_MASK             0x00004000
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_SHIFT            14
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_err_mask_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: lpi_count [13:09] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_MASK               0x00003e00
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_SHIFT              9
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_lpi_count_DEFAULT            0x0000000f
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: tx_clk_stop_en [08:08] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_MASK          0x00000100
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_SHIFT         8
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_clk_stop_en_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: tx_pause_en [07:07] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_MASK             0x00000080
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_SHIFT            7
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rx_pause_en [06:06] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_MASK             0x00000040
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_SHIFT            6
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rvmii_ref_sel [05:05] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_MASK           0x00000020
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_SHIFT          5
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: port_mode [04:02] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_MASK               0x0000001c
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_SHIFT              2
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_DEFAULT            0x00000003
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: id_mode_dis [01:01] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_MASK             0x00000002
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_SHIFT            1
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_DEFAULT          0x00000000
+
+/* SWITCH_REG :: RGMII_9_CNTRL :: rgmii_mode_en [00:00] */
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_MASK           0x00000001
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_SHIFT          0
+#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_DEFAULT        0x00000000
+
+/***************************************************************************
+ *RGMII_9_IB_STATUS - RGMII port 9 InBand Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: reserved0 [31:05] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_MASK           0xffffffe0
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_SHIFT          5
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: ib_status_ovrd [04:04] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_MASK      0x00000010
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_SHIFT     4
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_ib_status_ovrd_DEFAULT   0x00000000
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: link_decode [03:03] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_MASK         0x00000008
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_SHIFT        3
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_DEFAULT      0x00000000
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: duplex_decode [02:02] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_MASK       0x00000004
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_SHIFT      2
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_DEFAULT    0x00000000
+
+/* SWITCH_REG :: RGMII_9_IB_STATUS :: speed_decode [01:00] */
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_MASK        0x00000003
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_SHIFT       0
+#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_DEFAULT     0x00000000
+
+/***************************************************************************
+ *RGMII_9_RX_CLOCK_DELAY_CNTRL - RGMII port 9 RX Clock Delay Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK  0x00000040
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_MASK   0x00000020
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT  5
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_MASK     0x00000010
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT    4
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_MASK     0x0000000c
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_SHIFT    2
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT  0x00000002
+
+/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_MASK     0x00000003
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT    0
+#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RGMII_10_CNTRL - RGMII port 10 Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_CNTRL :: reserved0 [31:16] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_MASK              0xffff0000
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_reserved0_SHIFT             16
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: col_crs_mask [15:15] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_MASK           0x00008000
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_SHIFT          15
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_col_crs_mask_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rx_err_mask [14:14] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_MASK            0x00004000
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_SHIFT           14
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_err_mask_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: lpi_count [13:09] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_MASK              0x00003e00
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_SHIFT             9
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_lpi_count_DEFAULT           0x0000000f
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: tx_clk_stop_en [08:08] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_MASK         0x00000100
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_SHIFT        8
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_clk_stop_en_DEFAULT      0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: tx_pause_en [07:07] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_MASK            0x00000080
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_SHIFT           7
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_tx_pause_en_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rx_pause_en [06:06] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_MASK            0x00000040
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_SHIFT           6
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rx_pause_en_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rvmii_ref_sel [05:05] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_MASK          0x00000020
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_SHIFT         5
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rvmii_ref_sel_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: port_mode [04:02] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_MASK              0x0000001c
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_SHIFT             2
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_port_mode_DEFAULT           0x00000003
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: id_mode_dis [01:01] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_MASK            0x00000002
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_SHIFT           1
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_id_mode_dis_DEFAULT         0x00000000
+
+/* SWITCH_REG :: RGMII_10_CNTRL :: rgmii_mode_en [00:00] */
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_MASK          0x00000001
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_SHIFT         0
+#define BCHP_SWITCH_REG_RGMII_10_CNTRL_rgmii_mode_en_DEFAULT       0x00000000
+
+/***************************************************************************
+ *RGMII_10_IB_STATUS - RGMII port 10 InBand Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: reserved0 [31:05] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_reserved0_SHIFT         5
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: ib_status_ovrd [04:04] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_MASK     0x00000010
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_SHIFT    4
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_ib_status_ovrd_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: link_decode [03:03] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_MASK        0x00000008
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_SHIFT       3
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_link_decode_DEFAULT     0x00000000
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: duplex_decode [02:02] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_MASK      0x00000004
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_SHIFT     2
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_duplex_decode_DEFAULT   0x00000000
+
+/* SWITCH_REG :: RGMII_10_IB_STATUS :: speed_decode [01:00] */
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_MASK       0x00000003
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_SHIFT      0
+#define BCHP_SWITCH_REG_RGMII_10_IB_STATUS_speed_decode_DEFAULT    0x00000000
+
+/***************************************************************************
+ *RGMII_10_RX_CLOCK_DELAY_CNTRL - RGMII port 10 RX Clock Delay Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK 0x00000040
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_MASK  0x00000020
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT 5
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_MASK    0x00000010
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT   4
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_MASK    0x0000000c
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_SHIFT   2
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT 0x00000002
+
+/* SWITCH_REG :: RGMII_10_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_MASK    0x00000003
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT   0
+#define BCHP_SWITCH_REG_RGMII_10_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_RX_CNTRL - RGMII port 9 ATE RX Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_MASK        0xff000000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_reserved0_SHIFT       24
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: ate_en [23:23] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_MASK           0x00800000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_SHIFT          23
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_ate_en_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: good_count [22:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_MASK       0x007c0000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_SHIFT      18
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_good_count_DEFAULT    0x00000004
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_MASK  0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_CNTRL :: expected_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_MASK  0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_RX_STATUS - RGMII port 9 ATE RX Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: reserved0 [31:19] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_MASK       0xfff80000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_reserved0_SHIFT      19
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: rx_ok [18:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_MASK           0x00040000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_SHIFT          18
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_rx_ok_DEFAULT        0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_RX_STATUS :: received_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_TX_CNTRL_0 - RGMII port 9 ATE TX Control 0 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_MASK      0xfffffffc
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_reserved0_SHIFT     2
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop [01:01] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_MASK     0x00000002
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_SHIFT    1
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_9_ATE_TX_CNTRL_1 - RGMII port 9 ATE TX Control 1 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_MASK      0xfffc0000
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_reserved0_SHIFT     18
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_MASK      0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_SHIFT     9
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_1_DEFAULT   0x00000000
+
+/* SWITCH_REG :: RGMII_9_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_MASK      0x000001ff
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_SHIFT     0
+#define BCHP_SWITCH_REG_RGMII_9_ATE_TX_CNTRL_1_tx_data_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_RX_CNTRL - RGMII port 10 ATE RX Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: reserved0 [31:24] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_MASK       0xff000000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_reserved0_SHIFT      24
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: ate_en [23:23] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_MASK          0x00800000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_SHIFT         23
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_ate_en_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: good_count [22:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_MASK      0x007c0000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_SHIFT     18
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_good_count_DEFAULT   0x00000004
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_CNTRL :: expected_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_CNTRL_expected_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_RX_STATUS - RGMII port 10 ATE RX Status Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: reserved0 [31:19] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_MASK      0xfff80000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_reserved0_SHIFT     19
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: rx_ok [18:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_MASK          0x00040000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_SHIFT         18
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_rx_ok_DEFAULT       0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_MASK 0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_SHIFT 9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_1_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_RX_STATUS :: received_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_MASK 0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_RX_STATUS_received_data_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_TX_CNTRL_0 - RGMII port 10 ATE TX Control 0 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: reserved0 [31:02] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_MASK     0xfffffffc
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_reserved0_SHIFT    2
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop [01:01] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_MASK    0x00000002
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_SHIFT   1
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_DEFAULT 0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_0 :: start_stop_ovrd [00:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_MASK 0x00000001
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_SHIFT 0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_0_start_stop_ovrd_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RGMII_10_ATE_TX_CNTRL_1 - RGMII port 10 ATE TX Control 1 Register
+ ***************************************************************************/
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: reserved0 [31:18] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_MASK     0xfffc0000
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_reserved0_SHIFT    18
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_1 [17:09] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_MASK     0x0003fe00
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_SHIFT    9
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_1_DEFAULT  0x00000000
+
+/* SWITCH_REG :: RGMII_10_ATE_TX_CNTRL_1 :: tx_data_0 [08:00] */
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_MASK     0x000001ff
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_SHIFT    0
+#define BCHP_SWITCH_REG_RGMII_10_ATE_TX_CNTRL_1_tx_data_0_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AGGREGATE_LED_CNTRL - Aggregate LED Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: reserved0 [31:14] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_MASK         0xffffc000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_reserved0_SHIFT        14
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: lnk_pol_sel [13:13] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_MASK       0x00002000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_SHIFT      13
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_lnk_pol_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_pol_sel [12:12] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_MASK       0x00001000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_SHIFT      12
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_pol_sel_DEFAULT    0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: act_sel [11:11] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_MASK           0x00000800
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_SHIFT          11
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_act_sel_DEFAULT        0x00000000
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_tx_en_en [10:10] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_MASK       0x00000400
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_SHIFT      10
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_tx_en_en_DEFAULT    0x00000001
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: p8_rx_dv_en [09:09] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_MASK       0x00000200
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_SHIFT      9
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_p8_rx_dv_en_DEFAULT    0x00000001
+
+/* SWITCH_REG :: AGGREGATE_LED_CNTRL :: port_en [08:00] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_MASK           0x000001ff
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_SHIFT          0
+#define BCHP_SWITCH_REG_AGGREGATE_LED_CNTRL_port_en_DEFAULT        0x00000000
+
+/***************************************************************************
+ *AGGREGATE_LED_BLINK_RATE_CNTRL - Aggregate LED Blink Rate Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_MASK 0xffff0000
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT 16
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT 0x00000320
+
+/* SWITCH_REG :: AGGREGATE_LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_MASK 0x0000ffff
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT 0
+#define BCHP_SWITCH_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT 0x00000320
+
+/***************************************************************************
+ *SPARE_CNTRL - Spare Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SPARE_CNTRL :: spare_reg [31:00] */
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_MASK                 0xffffffff
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_SHIFT                0
+#define BCHP_SWITCH_REG_SPARE_CNTRL_spare_reg_DEFAULT              0x00000000
+
+/***************************************************************************
+ *SWITCH_PHY_INTR_CNTRL - Switch PHY Interrupt Control Register
+ ***************************************************************************/
+/* SWITCH_REG :: SWITCH_PHY_INTR_CNTRL :: reserved0 [31:08] */
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_reserved0_MASK       0xffffff00
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_reserved0_SHIFT      8
+
+/* SWITCH_REG :: SWITCH_PHY_INTR_CNTRL :: phy_intr_pol_inv [07:00] */
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_MASK 0x000000ff
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_SHIFT 0
+#define BCHP_SWITCH_REG_SWITCH_PHY_INTR_CNTRL_phy_intr_pol_inv_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SWITCH_REG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/3390b0/bchp_usb_ctrl.h b/include/linux/brcmstb/3390b0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..1a35934affcd
--- /dev/null
+++ b/include/linux/brcmstb/3390b0/bchp_usb_ctrl.h
@@ -0,0 +1,1661 @@
+/****************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *     All Rights Reserved
+ *     Confidential Property of Broadcom Corporation
+ *
+ *
+ * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
+ * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
+ * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on               Mon May  4 10:42:15 2015
+ *                 Full Compile MD5 Checksum  3fa71b7874a727210919dce012235db9
+ *                     (minus title and desc)
+ *                 MD5 Checksum               354cf45b714a5565197034df92d073c7
+ *
+ * Compiled with:  RDB Utility                combo_header.pl
+ *                 RDB.pm                     15517
+ *                 unknown                    unknown
+ *                 Perl Interpreter           5.008005
+ *                 Operating System           linux
+ *
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x21000200 /* [RW] Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x21000204 /* [RW] PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x21000208 /* [RW] Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x2100020c /* [RW] Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x21000210 /* [RW] Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x21000214 /* [RW] MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x21000218 /* [RO] MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x2100021c /* [RW] Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x21000220 /* [RW] Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x21000224 /* [RW] Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x21000228 /* [RO] Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x2100022c /* [RW] UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x21000230 /* [RW] UTMI Control 2 Register */
+#define BCHP_USB_CTRL_USB_PM                     0x21000234 /* [RW] Power Management Register */
+#define BCHP_USB_CTRL_USB_PM_STATUS              0x21000238 /* [RW] usb20 Power Management Status Register */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT              0x2100023c /* [RW] OHCI ADDRESS Extension */
+#define BCHP_USB_CTRL_PLL_LDO_CTL                0x21000240 /* [RW] 28NM USBPHY LDO Control */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS            0x21000244 /* [RW] 28NM USBPHY PLLBIAS Control */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL            0x21000248 /* [RW] 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_AFE_USBIO_TST              0x2100024c /* [RW] 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC              0x21000250 /* [RW] PLL Feedback Divider Control Register */
+#define BCHP_USB_CTRL_TP_DIAG                    0x21000254 /* [RW] diagnostic for tp bus */
+#define BCHP_USB_CTRL_SPARE3                     0x21000258 /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE4                     0x2100025c /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_USB30_CTL1                 0x21000260 /* [RW] USB30 CONTROL Register 1 */
+#define BCHP_USB_CTRL_USB30_CTL2                 0x21000264 /* [RW] USB30 CONTROL Register 2 */
+#define BCHP_USB_CTRL_USB30_CTL3                 0x21000268 /* [RW] USB30 CONTROL Register 3 */
+#define BCHP_USB_CTRL_USB30_CTL4                 0x2100026c /* [RW] USB30 CONTROL Register 4 */
+#define BCHP_USB_CTRL_USB30_PCTL                 0x21000270 /* [RW] USB30 PORT CONTROL Register */
+#define BCHP_USB_CTRL_USB30_CTL5                 0x21000274 /* [RW] USB30 CONTROL Register 5 */
+#define BCHP_USB_CTRL_SPARE5                     0x21000278 /* [RW] Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE6                     0x2100027c /* [RW] Spare2 Register for future use */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1            0x21000290 /* [RW] USB DEVICE  CONTROL Register 1 */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE            0x210002a0 /* [RW] SCB0 base start and end address */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE            0x210002a4 /* [RW] SCB1 base start and end address */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE            0x210002a8 /* [RW] SCB2 base start and end address */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE            0x210002ac /* [RW] SCB0 extn start and end address */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE            0x210002b0 /* [RW] SCB1 extn start and end address */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE            0x210002b4 /* [RW] SCB2 extn start and end address */
+#define BCHP_USB_CTRL_USB20_ID                   0x210002f0 /* [RO] USB REVID */
+#define BCHP_USB_CTRL_USB30_ID                   0x210002f4 /* [RO] USB REVID */
+#define BCHP_USB_CTRL_BDC_COREID                 0x210002f8 /* [RO] USB REVID */
+#define BCHP_USB_CTRL_USB_REVID                  0x210002fc /* [RO] USB REVID */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK                       0xc0000000
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT                      30
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0x30000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK                   0x08000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT                  27
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK                     0x04000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT                    26
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: strap_ipp_sel [25:25] */
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_MASK                     0x02000000
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_SHIFT                    25
+#define BCHP_USB_CTRL_SETUP_strap_ipp_sel_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:20] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01f00000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      20
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK                    0x00080000
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT                   19
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                   0x00040000
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                  18
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK                   0x00020000
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT                  17
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT                0x00000001
+
+/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00010000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 16
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: scb2_en [15:15] */
+#define BCHP_USB_CTRL_SETUP_scb2_en_MASK                           0x00008000
+#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT                          15
+#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT                        0x00000000
+
+/* USB_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb0_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb0_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00001000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  12
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: setup_spare1 [11:10] */
+#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK                      0x00000c00
+#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT                     10
+#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_CTL_SPARE1 [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_CTL_SPARE1_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000004
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x0000f000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000020
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000001
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000001
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:19] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ff80000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      19
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: ohci_memreq_disable [18:18] */
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_MASK             0x00040000
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_SHIFT            18
+#define BCHP_USB_CTRL_OBRIDGE_ohci_memreq_disable_DEFAULT          0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0x7c000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: MDIO2_SPARE [31:16] */
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_MASK                       0xffff0000
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_SHIFT                      16
+#define BCHP_USB_CTRL_MDIO2_MDIO2_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0xf0000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              28
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK          0x08000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT         27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK               0x01800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT              23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK            0x00600000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT           21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK                0x00080000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT               19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK            0x00040000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT           18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK            0x00020000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT           17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK                  0x00010000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                 16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT               0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: PHY_TPOUT_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_PHY_TPOUT_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0             0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1             1
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2             2
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3             3
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4             4
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5             5
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6             6
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7             7
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8             8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9             9
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10            10
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11            11
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12            12
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13            13
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14            14
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15            15
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17            17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18            18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19            19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23            23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24            24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25            25
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffc00
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                10
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK              0x00000200
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT             9
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [08:07] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK                0x00000180
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT               7
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK                  0x00000040
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT                 6
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT                5
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK                0x00000010
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT               4
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x0000000f
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK              0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT             21
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK                 0x80000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT                31
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK                 0x40000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT                30
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT                29
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0x1fffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK           0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT          27
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK              0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT             26
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK       0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT      25
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK        0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT       24
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT     0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host                  0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device                1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG                   2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10                  3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK              0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT             11
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT           0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK                 0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT                10
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK          0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT         9
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT       0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK           0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT          8
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host                     0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device                   1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG                      2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10                     3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB_PM - Power Management Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM :: USB_PWRDN [31:31] */
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK                        0x80000000
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_SHIFT                       31
+#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_DEFAULT                     0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE2 [30:28] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_MASK                    0x70000000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_SHIFT                   28
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE2_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_p1 [27:27] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_MASK                      0x08000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_SHIFT                     27
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_p0 [26:26] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_MASK                      0x04000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_SHIFT                     26
+#define BCHP_USB_CTRL_USB_PM_bond_dis_p0_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_usb30 [25:25] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_MASK                   0x02000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_SHIFT                  25
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_PM :: bond_dis_usb30_p1 [24:24] */
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_MASK                0x01000000
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_SHIFT               24
+#define BCHP_USB_CTRL_USB_PM_bond_dis_usb30_p1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: xdc_soft_resetb [23:23] */
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK                  0x00800000
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT                 23
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_soft_resetb [22:22] */
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK                  0x00400000
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT                 22
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [21:21] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT                21
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [20:20] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK                 0x00100000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT                20
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [19:16] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK                    0x000f0000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT                   16
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK            0x00008000
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT           15
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK            0x00004000
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT           14
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK                     0x00003fe0
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT                    5
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK                       0x00000010
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT                      4
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK                0x00000008
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT               3
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK                0x00000004
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT               2
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK                      0x00000002
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT                     1
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK                       0x00000001
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT                      0
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *USB_PM_STATUS - usb20 Power Management Status Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK               0xffff0000
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT              16
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK                 0x0000ffff
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT                0
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *OHCI_ADDR_EXT - OHCI ADDRESS Extension
+ ***************************************************************************/
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK           0xffffff00
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT          8
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK             0x000000ff
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT            0
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_LDO_CTL - 28NM USBPHY LDO Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK            0xffff0000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT           16
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT         0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK                0x0000f000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT               12
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK                0x00000f00
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT               8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK               0x000000f8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT              3
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK            0x00000004
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT           2
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT         0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK             0x00000002
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT            1
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT          0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK              0x00000001
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT             0
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK           0xfffc0000
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT          18
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK    0x0003ffff
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT   0
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK        0xfffe0000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT       17
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT     0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK             0x0001f000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT            12
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT          0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK     0x0000000f
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT    0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK           0x80000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT          31
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT        0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK                   0x40000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT                  30
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT                0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK       0x3fff0000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT      16
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT    0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK          0x0000ff00
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT         8
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT       0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK          0x000000ff
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT         0
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK      0xfff00000
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT     20
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT   0x00000000
+
+/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK             0x000fffff
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT            0
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TP_DIAG - diagnostic for tp bus
+ ***************************************************************************/
+/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK                    0xffffffff
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT                   0
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SPARE3 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE4 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB30_CTL1 - USB30 CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:23] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK            0xff800000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT           23
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_rxelectidle_sel [22:22] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_MASK        0x00400000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_SHIFT       22
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_rxelectidle_sel_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT      21
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK            0x00100000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT           20
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK                  0x00080000
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT                 19
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK                   0x00040000
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT                  18
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK                    0x00020000
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT                   17
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK                  0x00010000
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT                 16
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK            0x0000ff80
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT           7
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK          0x00000040
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT         6
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT                5
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK           0x00000010
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK          0x0000000e
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT         1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT       0x00000004
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk    0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL          1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N     2
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk   4
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK          0x00000001
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT         0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *USB30_CTL2 - USB30 CONTROL Register 2
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK            0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT         0x00000020
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK          0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT         16
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK          0x0000ff00
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT         8
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK            0x000000f8
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT           3
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK          0x00000004
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT         2
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_CTL3 - USB30 CONTROL Register 3
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK     0x20000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT    29
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK        0x1f000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT       24
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT     0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK        0x00f00000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT       20
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT     0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK           0x00080000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT          19
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK     0x00040000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT    18
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK         0x00020000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT        17
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT      0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK            0x00010000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK            0x0000c000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT           14
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK        0x00002000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT       13
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK           0x00001f00
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT          8
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT        0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK           0x000000f0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT        0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK              0x00000008
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT             3
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK        0x00000004
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT       2
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK            0x00000002
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT           1
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK               0x00000001
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT            0x00000001
+
+/***************************************************************************
+ *USB30_CTL4 - USB30 CONTROL Register 4
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL4 :: phy3_phystatus_override [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_MASK      0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_SHIFT     30
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_phystatus_override_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: phy3_rxstatus_override [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_MASK       0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_SHIFT      24
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_rxstatus_override_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK            0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_PCTL - USB30 PORT CONTROL Register
+ ***************************************************************************/
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK             0xe0000000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT            29
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK           0x10000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT          28
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT      21
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK       0x00100000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT      20
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK                 0x000c0000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT                18
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK      0x00010000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT     16
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK           0x00008000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT          15
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK             0x00006000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT            13
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK              0x00001000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT             12
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT           0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK    0x00000100
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT   8
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK    0x00000080
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT   7
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK    0x00000040
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT   6
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK          0x00000020
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT         5
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK          0x00000010
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT         4
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK                    0x0000000c
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT                   2
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK         0x00000001
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT        0
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT      0x00000000
+
+/***************************************************************************
+ *USB30_CTL5 - USB30 CONTROL Register 5
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK                   0xffffffff
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT                  0
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPARE5 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE6 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB_DEVICE_CTL1 - USB DEVICE  CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare3 [31:20] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_MASK  0xfff00000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_SHIFT 20
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare3_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_spd [19:17] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_MASK      0x000e0000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_SHIFT     17
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_spd_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_ndr [16:16] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_MASK      0x00010000
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_SHIFT     16
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_ndr_DEFAULT   0x00000001
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare2 [15:11] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_MASK  0x0000f800
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_SHIFT 11
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare2_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_vdd_retention [10:10] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_MASK 0x00000400
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_SHIFT 10
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_vdd_retention_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_rmt_wkup [09:09] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_MASK     0x00000200
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_SHIFT    9
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_rmt_wkup_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_stp_buspwr [08:08] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_MASK   0x00000100
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_SHIFT  8
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_stp_buspwr_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usb_device_ctl1_spare1 [07:04] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_MASK  0x000000f0
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_SHIFT 4
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usb_device_ctl1_spare1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: device_pullup_dis [03:03] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_MASK       0x00000008
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_SHIFT      3
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_device_pullup_dis_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: usbphy_host_override [02:02] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_MASK    0x00000004
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_SHIFT   2
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_usbphy_host_override_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB_DEVICE_CTL1 :: port_mode [01:00] */
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB_DEVICE_CTL1_port_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCB0_BASE_RANGE - SCB0 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT   0x00000007
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCB1_BASE_RANGE - SCB1 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB2_BASE_RANGE - SCB2 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT   0x0000000f
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *SCB0_EXTN_RANGE - SCB0 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT   0x0000001b
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010
+
+/***************************************************************************
+ *SCB1_EXTN_RANGE - SCB1 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT   0x0000003b
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030
+
+/***************************************************************************
+ *SCB2_EXTN_RANGE - SCB2 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT   0x000000cb
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0
+
+/***************************************************************************
+ *USB20_ID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB20_ID :: USB20PHY_ID [31:16] */
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_MASK                    0xffff0000
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_SHIFT                   16
+#define BCHP_USB_CTRL_USB20_ID_USB20PHY_ID_DEFAULT                 0x0000d034
+
+/* USB_CTRL :: USB20_ID :: SYNOPSYS_CORE_ID [15:00] */
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_SHIFT              0
+#define BCHP_USB_CTRL_USB20_ID_SYNOPSYS_CORE_ID_DEFAULT            0x0000298a
+
+/***************************************************************************
+ *USB30_ID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB30_ID :: USB30PHY_ID [31:16] */
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_MASK                    0xffff0000
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_SHIFT                   16
+#define BCHP_USB_CTRL_USB30_ID_USB30PHY_ID_DEFAULT                 0x0000c000
+
+/* USB_CTRL :: USB30_ID :: XHC_CORE_ID [15:00] */
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_MASK                    0x0000ffff
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_SHIFT                   0
+#define BCHP_USB_CTRL_USB30_ID_XHC_CORE_ID_DEFAULT                 0x00000200
+
+/***************************************************************************
+ *BDC_COREID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: BDC_COREID :: BDC3_COREID [31:16] */
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_SHIFT                 16
+#define BCHP_USB_CTRL_BDC_COREID_BDC3_COREID_DEFAULT               0x0000c000
+
+/* USB_CTRL :: BDC_COREID :: BDC2_COREID [15:00] */
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_MASK                  0x0000ffff
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_SHIFT                 0
+#define BCHP_USB_CTRL_BDC_COREID_BDC2_COREID_DEFAULT               0x00000200
+
+/***************************************************************************
+ *USB_REVID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK                     0xffffffff
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT                    0
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT                  0x00000001
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7228a0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..2cdd98028cec
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_aon_ctrl.h
@@ -0,0 +1,1577 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_hys_en [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_MASK     0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_SHIFT    0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_DEFAULT  0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7228a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..f36f9c363865
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,650 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7228a0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..32eec4f3760e
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1106 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_bspi.h b/include/linux/brcmstb/7228a0/bchp_bspi.h
new file mode 100644
index 000000000000..da3aa7cf4028
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_bspi.h
@@ -0,0 +1,445 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_bspi_raf.h b/include/linux/brcmstb/7228a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..e4c37b1b67df
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_bspi_raf.h
@@ -0,0 +1,162 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_clkgen.h b/include/linux/brcmstb/7228a0/bchp_clkgen.h
new file mode 100644
index 000000000000..53d5ab4ae0c8
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_clkgen.h
@@ -0,0 +1,4691 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420088 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042009c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a4 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200e8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004200fc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420100 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420104 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420114 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420118 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042011c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420120 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042012c /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420168 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x0042016c /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420170 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x00420174 /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420178 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x0042017c /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420180 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420184 /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420188 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x0042018c /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420190 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x00420194 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x00420198 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x0042019c /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a0 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201ac /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b0 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201ec /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201f0 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x004201f4 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201fc /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420200 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420204 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420208 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x0042020c /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420210 /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420214 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420218 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0042021c /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420220 /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420224 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420228 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x0042022c /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420230 /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420234 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420238 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x0042023c /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x00420240 /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420244 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420248 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0042024c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x00420250 /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420254 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420258 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x0042025c /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x00420260 /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420264 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420268 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x0042026c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420274 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420278 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042027c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420280 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420284 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420288 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042028c /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x00420290 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420294 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420298 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x0042029c /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202a0 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202a4 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202a8 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202ac /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202b0 /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202b4 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202b8 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202bc /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202c0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Sata3 memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202c8 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL         0x004202cc /* Sata3 top PLL Ref Sel */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202d0 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202d4 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202d8 /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202dc /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202e0 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202e4 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202e8 /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202ec /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202f0 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202f4 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202f8 /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x00420300 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x00420304 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420308 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420310 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420314 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420318 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042031c /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420320 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420324 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420328 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042032c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420330 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420334 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420338 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x0042033c /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420340 /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420344 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420348 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420354 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420358 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x0042035c /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420360 /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420364 /* Vec aio top power switch memory b */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 0x00420368 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x0042036c /* spi clock control */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000032
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      0x00000001
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:08] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 8
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_WAIT_COUNT [07:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_MASK 0x000000fc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_SHIFT 2
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_DEFAULT 0x0000000f
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     0x00000001
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_USE_PROG_CLK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_FUNC_30_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_PLLREF_SEL - Sata3 top PLL Ref Sel
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_SHIFT           1
+
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: SATA_TOP_PLLREF_SEL [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_MASK  0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BSPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_common.h b/include/linux/brcmstb/7228a0/bchp_common.h
new file mode 100644
index 000000000000..cb04b17c5b6b
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_common.h
@@ -0,0 +1,1990 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:48 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7228_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00b01010 /* RFM_GRB is last */
+#define BCHP_REGISTER_SIZE                                 0x002c0404 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_VP6_DCP_0_REG_START                    0x00000620
+#define BCHP_DECODE_VP6_DCP_0_REG_END                      0x0000062c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060090
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410408
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042036c
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042349c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x00680080
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00dc
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_CWC_REG_START                             0x00700600
+#define BCHP_SDS_CWC_REG_END                               0x00700694
+#define BCHP_SDS_MISC_REG_START                            0x00700700
+#define BCHP_SDS_MISC_REG_END                              0x00700798
+#define BCHP_SDS_DSEC_REG_START                            0x00700800
+#define BCHP_SDS_DSEC_REG_END                              0x007008c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700900
+#define BCHP_SDS_TUNER_REG_END                             0x007009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x00702060
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a38000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a38000
+#define BCHP_RFM_SYSCLK_REG_START                          0x00b00000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00b00118
+#define BCHP_RFM_CLK27_REG_START                           0x00b00000
+#define BCHP_RFM_CLK27_REG_END                             0x00b00470
+#define BCHP_RFM_L2_REG_START                              0x00b00c00
+#define BCHP_RFM_L2_REG_END                                0x00b00c2c
+#define BCHP_RFM_GRB_REG_START                             0x00b01000
+#define BCHP_RFM_GRB_REG_END                               0x00b0100c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7228a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..63cab083096a
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1538 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 physical interface control registers
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000006
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7228a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..7c34c0689f01
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3333 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 word lane #0 control registers
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_ebi.h b/include/linux/brcmstb/7228a0/bchp_ebi.h
new file mode 100644
index 000000000000..2c99723f6bcd
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_ebi.h
@@ -0,0 +1,1471 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7228a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..2b8501ca97b9
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2018 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_hif_intr2.h b/include/linux/brcmstb/7228a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..c8c4e4a12994
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_hif_intr2.h
@@ -0,0 +1,974 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_hif_mspi.h b/include/linux/brcmstb/7228a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..66e0fd0e92f8
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_hif_mspi.h
@@ -0,0 +1,1213 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7228a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..4b0d7239a462
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,566 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7228a0/bchp_hif_top_ctrl.h
new file mode 100644
index 000000000000..b218783efc9a
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,529 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_irq0.h b/include/linux/brcmstb/7228a0/bchp_irq0.h
new file mode 100644
index 000000000000..41d9c1b10e79
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_irq0.h
@@ -0,0 +1,216 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_irq1.h b/include/linux/brcmstb/7228a0/bchp_irq1.h
new file mode 100644
index 000000000000..9fbdbb1e038a
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_irq1.h
@@ -0,0 +1,216 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ1 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ1_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ1 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ1_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ1_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ1_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ1_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ1_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ1_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ1_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ1_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ1 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ1_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ1 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ1_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ1_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ1 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ1_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ1_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ1 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ1_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ1_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ1_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ1_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ1 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ1 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ1_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ1_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ1_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ1_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ1_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ1_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ1_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ1_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ1 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ1_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ1 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ1_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ1_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ1 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ1_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ1_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ1 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ1_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ1_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ1_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ1_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7228a0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..15588aa78379
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_mem_dma_0.h
@@ -0,0 +1,156 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7228a0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..1c2ab9301eaf
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2664 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_misb_bridge.h b/include/linux/brcmstb/7228a0/bchp_misb_bridge.h
new file mode 100644
index 000000000000..4917ab3bdba1
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_misb_bridge.h
@@ -0,0 +1,89 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0x00000000
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 0x00000001
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_nand.h b/include/linux/brcmstb/7228a0/bchp_nand.h
new file mode 100644
index 000000000000..193172279da8
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_nand.h
@@ -0,0 +1,2259 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7228a0/bchp_sata_top_ctrl.h
new file mode 100644
index 000000000000..5b0efcb3b605
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_sata_top_ctrl.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7228a0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..f1e4c54119e0
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,637 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00410138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000032
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000028
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a9
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7228a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..8cd0617f6846
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6200 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404164 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x72280000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x72280000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000007
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_RSVD_MPOD_M_SDI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_RSVD_MPOD_M_SDO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_RSVD_MPOD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_RSVD_MPOD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xffc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_timer.h b/include/linux/brcmstb/7228a0/bchp_timer.h
new file mode 100644
index 000000000000..4a5620d23a41
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_timer.h
@@ -0,0 +1,326 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_uarta.h b/include/linux/brcmstb/7228a0/bchp_uarta.h
new file mode 100644
index 000000000000..e46364e54d9c
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_uarta.h
@@ -0,0 +1,393 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_uartb.h b/include/linux/brcmstb/7228a0/bchp_uartb.h
new file mode 100644
index 000000000000..ab9735d5405d
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_uartb.h
@@ -0,0 +1,393 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:57 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTB :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTB_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_RBR_reserved0_SHIFT                             8
+
+/* UARTB :: RBR :: RBR [07:00] */
+#define BCHP_UARTB_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTB_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTB_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTB :: THR :: reserved0 [31:08] */
+#define BCHP_UARTB_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_THR_reserved0_SHIFT                             8
+
+/* UARTB :: THR :: THR [07:00] */
+#define BCHP_UARTB_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTB_THR_THR_SHIFT                                   0
+#define BCHP_UARTB_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTB :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTB_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLH_reserved0_SHIFT                             8
+
+/* UARTB :: DLH :: DLH [07:00] */
+#define BCHP_UARTB_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTB_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTB_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTB :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTB_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLL_reserved0_SHIFT                             8
+
+/* UARTB :: DLL :: DLL [07:00] */
+#define BCHP_UARTB_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTB_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTB_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTB :: IER :: reserved0 [31:08] */
+#define BCHP_UARTB_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IER_reserved0_SHIFT                             8
+
+/* UARTB :: IER :: PTIME [07:07] */
+#define BCHP_UARTB_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTB_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTB_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: reserved1 [06:04] */
+#define BCHP_UARTB_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTB_IER_reserved1_SHIFT                             4
+
+/* UARTB :: IER :: EDSSI [03:03] */
+#define BCHP_UARTB_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTB_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTB_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ELSI [02:02] */
+#define BCHP_UARTB_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTB_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTB_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTB :: IER :: ETBEI [01:01] */
+#define BCHP_UARTB_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTB_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTB_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ERBFI [00:00] */
+#define BCHP_UARTB_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTB_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTB_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTB :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTB_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IIR_reserved0_SHIFT                             8
+
+/* UARTB :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTB_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTB_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTB_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTB :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTB_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTB_IIR_reserved1_SHIFT                             4
+
+/* UARTB :: IIR :: IID [03:00] */
+#define BCHP_UARTB_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTB_IIR_IID_SHIFT                                   0
+#define BCHP_UARTB_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTB :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTB_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_FCR_reserved0_SHIFT                             8
+
+/* UARTB :: FCR :: RT [07:06] */
+#define BCHP_UARTB_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTB_FCR_RT_SHIFT                                    6
+#define BCHP_UARTB_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTB :: FCR :: TET [05:04] */
+#define BCHP_UARTB_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTB_FCR_TET_SHIFT                                   4
+#define BCHP_UARTB_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTB :: FCR :: DMAM [03:03] */
+#define BCHP_UARTB_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTB_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTB_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTB :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTB_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTB_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTB_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTB_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTB_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTB_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTB_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTB_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTB_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTB :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTB_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LCR_reserved0_SHIFT                             8
+
+/* UARTB :: LCR :: DLAB [07:07] */
+#define BCHP_UARTB_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTB_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTB_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: BC [06:06] */
+#define BCHP_UARTB_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTB_LCR_BC_SHIFT                                    6
+#define BCHP_UARTB_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTB :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTB_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTB_LCR_reserved1_SHIFT                             5
+
+/* UARTB :: LCR :: EPS [04:04] */
+#define BCHP_UARTB_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTB_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTB_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: PEN [03:03] */
+#define BCHP_UARTB_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTB_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTB_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: STOP [02:02] */
+#define BCHP_UARTB_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTB_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTB_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: DLS [01:00] */
+#define BCHP_UARTB_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTB_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTB_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTB :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTB_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTB_MCR_reserved0_SHIFT                             7
+
+/* UARTB :: MCR :: SIRE [06:06] */
+#define BCHP_UARTB_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTB_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTB_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: AFCE [05:05] */
+#define BCHP_UARTB_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTB_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTB_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: LB [04:04] */
+#define BCHP_UARTB_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTB_MCR_LB_SHIFT                                    4
+#define BCHP_UARTB_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTB :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTB_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTB_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTB_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTB_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTB_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTB_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: RTS [01:01] */
+#define BCHP_UARTB_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTB_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTB_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MCR :: DTR [00:00] */
+#define BCHP_UARTB_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTB_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTB_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTB :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTB_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LSR_reserved0_SHIFT                             8
+
+/* UARTB :: LSR :: RFE [07:07] */
+#define BCHP_UARTB_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTB_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTB_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTB :: LSR :: TEMT [06:06] */
+#define BCHP_UARTB_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTB_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTB_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: THRE [05:05] */
+#define BCHP_UARTB_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTB_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTB_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: BI [04:04] */
+#define BCHP_UARTB_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTB_LSR_BI_SHIFT                                    4
+#define BCHP_UARTB_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: FE [03:03] */
+#define BCHP_UARTB_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTB_LSR_FE_SHIFT                                    3
+#define BCHP_UARTB_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: PE [02:02] */
+#define BCHP_UARTB_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTB_LSR_PE_SHIFT                                    2
+#define BCHP_UARTB_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: OE [01:01] */
+#define BCHP_UARTB_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTB_LSR_OE_SHIFT                                    1
+#define BCHP_UARTB_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: DR [00:00] */
+#define BCHP_UARTB_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTB_LSR_DR_SHIFT                                    0
+#define BCHP_UARTB_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTB :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTB_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_MSR_reserved0_SHIFT                             8
+
+/* UARTB :: MSR :: DCD [07:07] */
+#define BCHP_UARTB_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTB_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTB_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: RI [06:06] */
+#define BCHP_UARTB_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTB_MSR_RI_SHIFT                                    6
+#define BCHP_UARTB_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTB :: MSR :: DSR [05:05] */
+#define BCHP_UARTB_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTB_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTB_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: CTS [04:04] */
+#define BCHP_UARTB_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTB_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTB_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: DDCD [03:03] */
+#define BCHP_UARTB_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTB_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTB_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: TERI [02:02] */
+#define BCHP_UARTB_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTB_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTB_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DDSR [01:01] */
+#define BCHP_UARTB_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTB_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTB_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DCTS [00:00] */
+#define BCHP_UARTB_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTB_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTB_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTB :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTB_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_SCR_reserved0_SHIFT                             8
+
+/* UARTB :: SCR :: SCR [07:00] */
+#define BCHP_UARTB_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTB_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTB_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_uartc.h b/include/linux/brcmstb/7228a0/bchp_uartc.h
new file mode 100644
index 000000000000..4264ad2b0767
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_uartc.h
@@ -0,0 +1,393 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTC :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTC_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_RBR_reserved0_SHIFT                             8
+
+/* UARTC :: RBR :: RBR [07:00] */
+#define BCHP_UARTC_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTC_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTC_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTC :: THR :: reserved0 [31:08] */
+#define BCHP_UARTC_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_THR_reserved0_SHIFT                             8
+
+/* UARTC :: THR :: THR [07:00] */
+#define BCHP_UARTC_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTC_THR_THR_SHIFT                                   0
+#define BCHP_UARTC_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTC :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTC_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLH_reserved0_SHIFT                             8
+
+/* UARTC :: DLH :: DLH [07:00] */
+#define BCHP_UARTC_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTC_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTC_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTC :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTC_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLL_reserved0_SHIFT                             8
+
+/* UARTC :: DLL :: DLL [07:00] */
+#define BCHP_UARTC_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTC_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTC_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTC :: IER :: reserved0 [31:08] */
+#define BCHP_UARTC_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IER_reserved0_SHIFT                             8
+
+/* UARTC :: IER :: PTIME [07:07] */
+#define BCHP_UARTC_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTC_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTC_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: reserved1 [06:04] */
+#define BCHP_UARTC_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTC_IER_reserved1_SHIFT                             4
+
+/* UARTC :: IER :: EDSSI [03:03] */
+#define BCHP_UARTC_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTC_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTC_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ELSI [02:02] */
+#define BCHP_UARTC_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTC_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTC_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTC :: IER :: ETBEI [01:01] */
+#define BCHP_UARTC_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTC_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTC_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ERBFI [00:00] */
+#define BCHP_UARTC_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTC_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTC_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTC :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTC_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IIR_reserved0_SHIFT                             8
+
+/* UARTC :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTC_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTC_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTC_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTC :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTC_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTC_IIR_reserved1_SHIFT                             4
+
+/* UARTC :: IIR :: IID [03:00] */
+#define BCHP_UARTC_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTC_IIR_IID_SHIFT                                   0
+#define BCHP_UARTC_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTC :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTC_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_FCR_reserved0_SHIFT                             8
+
+/* UARTC :: FCR :: RT [07:06] */
+#define BCHP_UARTC_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTC_FCR_RT_SHIFT                                    6
+#define BCHP_UARTC_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTC :: FCR :: TET [05:04] */
+#define BCHP_UARTC_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTC_FCR_TET_SHIFT                                   4
+#define BCHP_UARTC_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTC :: FCR :: DMAM [03:03] */
+#define BCHP_UARTC_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTC_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTC_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTC :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTC_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTC_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTC_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTC_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTC_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTC_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTC_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTC_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTC_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTC :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTC_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LCR_reserved0_SHIFT                             8
+
+/* UARTC :: LCR :: DLAB [07:07] */
+#define BCHP_UARTC_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTC_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTC_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: BC [06:06] */
+#define BCHP_UARTC_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTC_LCR_BC_SHIFT                                    6
+#define BCHP_UARTC_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTC :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTC_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTC_LCR_reserved1_SHIFT                             5
+
+/* UARTC :: LCR :: EPS [04:04] */
+#define BCHP_UARTC_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTC_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTC_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: PEN [03:03] */
+#define BCHP_UARTC_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTC_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTC_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: STOP [02:02] */
+#define BCHP_UARTC_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTC_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTC_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: DLS [01:00] */
+#define BCHP_UARTC_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTC_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTC_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTC :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTC_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTC_MCR_reserved0_SHIFT                             7
+
+/* UARTC :: MCR :: SIRE [06:06] */
+#define BCHP_UARTC_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTC_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTC_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: AFCE [05:05] */
+#define BCHP_UARTC_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTC_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTC_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: LB [04:04] */
+#define BCHP_UARTC_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTC_MCR_LB_SHIFT                                    4
+#define BCHP_UARTC_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTC :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTC_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTC_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTC_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTC_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTC_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTC_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: RTS [01:01] */
+#define BCHP_UARTC_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTC_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTC_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MCR :: DTR [00:00] */
+#define BCHP_UARTC_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTC_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTC_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTC :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTC_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LSR_reserved0_SHIFT                             8
+
+/* UARTC :: LSR :: RFE [07:07] */
+#define BCHP_UARTC_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTC_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTC_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTC :: LSR :: TEMT [06:06] */
+#define BCHP_UARTC_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTC_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTC_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: THRE [05:05] */
+#define BCHP_UARTC_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTC_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTC_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: BI [04:04] */
+#define BCHP_UARTC_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTC_LSR_BI_SHIFT                                    4
+#define BCHP_UARTC_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: FE [03:03] */
+#define BCHP_UARTC_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTC_LSR_FE_SHIFT                                    3
+#define BCHP_UARTC_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: PE [02:02] */
+#define BCHP_UARTC_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTC_LSR_PE_SHIFT                                    2
+#define BCHP_UARTC_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: OE [01:01] */
+#define BCHP_UARTC_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTC_LSR_OE_SHIFT                                    1
+#define BCHP_UARTC_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: DR [00:00] */
+#define BCHP_UARTC_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTC_LSR_DR_SHIFT                                    0
+#define BCHP_UARTC_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTC :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTC_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_MSR_reserved0_SHIFT                             8
+
+/* UARTC :: MSR :: DCD [07:07] */
+#define BCHP_UARTC_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTC_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTC_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: RI [06:06] */
+#define BCHP_UARTC_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTC_MSR_RI_SHIFT                                    6
+#define BCHP_UARTC_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTC :: MSR :: DSR [05:05] */
+#define BCHP_UARTC_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTC_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTC_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: CTS [04:04] */
+#define BCHP_UARTC_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTC_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTC_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: DDCD [03:03] */
+#define BCHP_UARTC_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTC_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTC_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: TERI [02:02] */
+#define BCHP_UARTC_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTC_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTC_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DDSR [01:01] */
+#define BCHP_UARTC_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTC_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTC_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DCTS [00:00] */
+#define BCHP_UARTC_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTC_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTC_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTC :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTC_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_SCR_reserved0_SHIFT                             8
+
+/* UARTC :: SCR :: SCR [07:00] */
+#define BCHP_UARTC_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTC_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTC_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7228a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..7f02f4acde94
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_usb_ctrl.h
@@ -0,0 +1,654 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:56 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/bchp_wktmr.h b/include/linux/brcmstb/7228a0/bchp_wktmr.h
new file mode 100644
index 000000000000..e10b67605d2f
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/bchp_wktmr.h
@@ -0,0 +1,107 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 16 11:12:55 2014
+ *                 Full Compile MD5 Checksum 74317a30eab2c0396bb2d7c2dd9c02f7
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              2e09daa633013a10114c0860c809d8eb
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7228a0/brcmirq.h b/include/linux/brcmstb/7228a0/brcmirq.h
new file mode 100644
index 000000000000..c06ad9d970b2
--- /dev/null
+++ b/include/linux/brcmstb/7228a0/brcmirq.h
@@ -0,0 +1,39 @@
+/*
+ * 7228a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_SATA		87
+#define BRCM_IRQ_SDIO0		83
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..646204f34a22
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:21:19 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:12p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      2
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..7c95d2a21632
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,613 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:04:25 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:12p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00408518 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PWM0          5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDIO0_WPROT   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_HD_DVI0_16    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDIO0_CMD     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_HD_DVI0_17    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_INT        6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_LINK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET0_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AUD_FS_CLK1   7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET1_LINK    8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_30     9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_21     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_VO0_656_0     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SC1_AUX1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_HD_DVI0_8     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_VO0_656_CLK   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SC1_VPP       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_HD_DVI0_9     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_IN_12      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_15     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_14     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_HD_DVI0_12    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_OUT_20     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_HD_DVI0_13    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_HD_DVI0_14    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_IR_INT        6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_HD_DVI0_15    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M_SCL    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_21     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_VO0_656_7     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AUD_FS_CLK1   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_HD_DVI0_1     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_20      9
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 10
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_VO0_656_6     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_HD_DVI0_2     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_19      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_VO0_656_5     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_HD_DVI0_3     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_18      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_VO0_656_4     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_HD_DVI0_4     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_17      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_VO0_656_3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_HD_DVI0_5     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_16      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_VO0_656_2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_HD_DVI0_6     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_VO0_656_1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SC1_AUX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_HD_DVI0_7     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M_SDA    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_22     2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_09_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [11:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00000fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fc00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       22
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..b558ac803f55
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_aon_pm_l2.h
@@ -0,0 +1,918 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Thu Oct 27 10:23:30 2011
+ *                 MD5 Checksum         1dc065bf3d1dc88383610b02195770fc
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffffe000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  13
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET1_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          10
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       9
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       8
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffffe000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     13
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET1_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          9
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          8
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       7
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffffe000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   13
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        9
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        8
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     7
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             13
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET1_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              11
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                13
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET1_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 11
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffffe000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              13
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               11
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffffe000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  13
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET1_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          10
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       9
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       8
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffffe000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     13
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET1_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          9
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          8
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       7
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffffe000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   13
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        9
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        8
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     7
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             13
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET1_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              11
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                13
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET1_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 11
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffffe000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              13
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET1 [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               11
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_bspi.h b/include/linux/brcmstb/7231b0/bchp_bspi.h
new file mode 100644
index 000000000000..6c7f78f5b6ae
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:16:23 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 4:28p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_bspi_raf.h b/include/linux/brcmstb/7231b0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..1c84a7daf433
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:26:50 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 4:29p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_clkgen.h b/include/linux/brcmstb/7231b0/bchp_clkgen.h
new file mode 100644
index 000000000000..ad17037b0ae6
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_clkgen.h
@@ -0,0 +1,4512 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:04:59 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:14p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x00420058 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x0042005c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00420060 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x00420064 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00420068 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x0042006c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00420070 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x00420074 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00420078 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x0042007c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00420080 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x00420084 /* Test Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420088 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0042009c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x004200a0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x004200a4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x004200a8 /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x004200b0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x004200b4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x004200b8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x004200bc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x004200c0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x004200c4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x004200c8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x004200cc /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x004200d0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200d4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200d8 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200dc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200e0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200e4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200e8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200ec /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200f0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200f4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200f8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200fc /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00420100 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x00420104 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00420108 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x0042010c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00420110 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00420114 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00420118 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x0042011c /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420120 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00420124 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x00420128 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x0042012c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420130 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420134 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420138 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x0042013c /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420140 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420144 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420168 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x0042016c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420170 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x00420174 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420178 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x0042017c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420180 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00420184 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420188 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x0042018c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420190 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420194 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420198 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x0042019c /* Status */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE 0x004201a0 /* Disable ANA_QDAC40G_M7FC's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x004201a4 /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x004201a8 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x004201ac /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x004201b0 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE         0x004201b4 /* Bvn top clock enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x004201b8 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x004201bc /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE 0x004201ec /* Disable DUAL_GENET_TOP_DUAL_RGMII's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE 0x004201f0 /* Dual genet top dual rgmii clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT 0x004201f4 /* Dual genet top dual rgmii clock select */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dual genet top dual rgmii memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK 0x004201fc /* Dual genet top dual rgmii observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY 0x00420200 /* Dual genet top dual rgmii power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x00420204 /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x00420208 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x0042020c /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x00420210 /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420214 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x00420218 /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC   0x0042021c /* Graphics clock enable m2mc */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D    0x00420220 /* Graphics clock enable v3d */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC 0x00420224 /* Graphics memory standby enable m2mc */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D 0x00420228 /* Graphics memory standby enable v3d */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x0042022c /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC 0x00420230 /* Graphics power switch memory m2mc */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D 0x00420234 /* Graphics power switch memory v3d */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x00420238 /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x0042023c /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO        0x00420240 /* Hif clock enable sdio */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID         0x00420244 /* Hif clock enable sid */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420248 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO 0x0042024c /* Hif memory standby enable sdio */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID 0x00420250 /* Hif memory standby enable sid */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420254 /* Hif power switch memory */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO 0x00420258 /* Hif power switch memory sdio */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID  0x0042025c /* Hif power switch memory sid */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420260 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE       0x00420264 /* Memsys 32 clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE 0x00420268 /* Memsys 32 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK      0x0042026c /* Memsys 32 observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY 0x00420270 /* Memsys 32 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS             0x00420274 /* Memsys 32 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420278 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x0042027c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x00420280 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420284 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420288 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042028c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420290 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x00420294 /* PLL_AVD Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00420298 /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x0042029c /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x004202a0 /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x004202a4 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x004202a8 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x004202ac /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004202b0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004202b4 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x004202b8 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x004202bc /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x004202c0 /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202c8 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202cc /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202d0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202d4 /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT       0x004202d8 /* Sata3 top clock select */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202dc /* Sata3 top memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202e0 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202e4 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA   0x004202e8 /* Sectop clock enable m2mdma */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK         0x004202ec /* Sectop observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x004202f0 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x004202f4 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE        0x004202f8 /* Svd0 top clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Svd0 top memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY 0x00420300 /* Svd0 top power switch memory */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE 0x00420304 /* Sys aon memory standby enable */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x00420308 /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY  0x0042030c /* Sys aon power switch memory */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420310 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420314 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420318 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042031c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x00420320 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE           0x00420324 /* Disable USB0's clocks */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE            0x00420328 /* Usb0 clock enable */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE   0x0042032c /* Usb0 memory standby enable */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK           0x00420330 /* Usb0 observe clock */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY     0x00420334 /* Usb0 power switch memory */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE           0x00420338 /* Disable USB1's clocks */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE            0x0042033c /* Usb1 clock enable */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE   0x00420340 /* Usb1 memory standby enable */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK           0x00420344 /* Usb1 observe clock */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY     0x00420348 /* Usb1 power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO 0x00420354 /* Vec aio top clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC 0x00420358 /* Vec aio top clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO 0x0042035c /* Vec aio top memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC 0x00420360 /* Vec aio top memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x00420364 /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO 0x00420368 /* Vec aio top power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC 0x0042036c /* Vec aio top power switch memory vec */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               135
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 4
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              88
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 26
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 96
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 54
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              96
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *ANA_QDAC40G_M7FC_CLOCK_DISABLE - Disable ANA_QDAC40G_M7FC's clocks
+ ***************************************************************************/
+/* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: ANA_QDAC40G_M7FC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_CLOCK_ENABLE - Bvn top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET_25_PHY_LVCLOCK [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET_25_PHY_LVCLOCK_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE - Dual genet top dual rgmii clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: reserved0 [31:16] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_reserved0_SHIFT 16
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT - Dual genet top dual rgmii clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE - Dual genet top dual rgmii memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE :: GENET0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_MEMORY_STANDBY_ENABLE_GENET0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK - Dual genet top dual rgmii observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK :: GENET_BROADCAST_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_OBSERVE_CLOCK_GENET_BROADCAST_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY - Dual genet top dual rgmii power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY :: GENET0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_POWER_SWITCH_MEMORY_GENET0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: VEC_IF_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE_M2MC - Graphics clock enable m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_reserved0_SHIFT     2
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_SCB_CLOCK_ENABLE_M2MC [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_M2MC :: M2MC_CORE_CLOCK_ENABLE_M2MC [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE_V3D - Graphics clock enable v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_reserved0_SHIFT      2
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_SCB_CLOCK_ENABLE_V3D [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_SCB_CLOCK_ENABLE_V3D_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE_V3D :: V3D_CORE_CLOCK_ENABLE_V3D [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D_V3D_CORE_CLOCK_ENABLE_V3D_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC - Graphics memory standby enable m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC :: M2MC_MEMORY_STANDBY_ENABLE_M2MC [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE_V3D - Graphics memory standby enable v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE_V3D :: V3D_MEMORY_STANDBY_ENABLE_V3D [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D_V3D_MEMORY_STANDBY_ENABLE_V3D_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY_M2MC - Graphics power switch memory m2mc
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_M2MC :: GFX_POWER_SWITCH_MEMORY_M2MC [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC_GFX_POWER_SWITCH_MEMORY_M2MC_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY_V3D - Graphics power switch memory v3d
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY_V3D :: GFX_POWER_SWITCH_MEMORY_V3D [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D_GFX_POWER_SWITCH_MEMORY_V3D_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  1
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE_SDIO - Hif clock enable sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_reserved0_SHIFT          2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_SCB_CLOCK_ENABLE_SDIO [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_DEFAULT 1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SDIO :: SDIO_216_CLOCK_ENABLE_SDIO [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_DEFAULT 1
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE_SID - Hif clock enable sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_reserved0_SHIFT           2
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: SID_SCB_CLOCK_ENABLE_SID [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_SHIFT 1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_SCB_CLOCK_ENABLE_SID_DEFAULT 1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE_SID :: SID_216_CLOCK_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID_SID_216_CLOCK_ENABLE_SID_DEFAULT 1
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE_SDIO - Hif memory standby enable sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SDIO :: SDIO_MEMORY_STANDBY_ENABLE_SDIO [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_DEFAULT 0
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE_SID - Hif memory standby enable sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SID :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_reserved0_SHIFT  1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE_SID :: SID_MEMORY_STANDBY_ENABLE_SID [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_SID_SID_MEMORY_STANDBY_ENABLE_SID_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY_SDIO - Hif power switch memory sdio
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SDIO :: SDIO_POWER_SWITCH_MEMORY_SDIO [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY_SID - Hif power switch memory sid
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SID :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_reserved0_SHIFT    2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY_SID :: SID_POWER_SWITCH_MEMORY_SID [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_SID_SID_POWER_SWITCH_MEMORY_SID_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_CLOCK_ENABLE - Memsys 32 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: DDR_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_CLOCK_ENABLE :: DDR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_MEMORY_STANDBY_ENABLE - Memsys 32 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_MEMORY_STANDBY_ENABLE :: DDR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_OBSERVE_CLOCK - Memsys 32 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_reserved0_SHIFT        1
+
+/* CLKGEN :: MEMSYS_32_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_POWER_SWITCH_MEMORY - Memsys 32 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_32_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_STATUS - Memsys 32 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_32_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 31
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    1
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_LV_CLK_30 [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_LV_CLK_30_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_SELECT - Sata3 top clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_reserved0_SHIFT         1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_CLOCK_ENABLE_M2MDMA - Sectop clock enable m2mdma
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT     1
+
+/* CLKGEN :: SECTOP_CLOCK_ENABLE_M2MDMA :: M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA_M2M_DMA_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_OBSERVE_CLOCK - Sectop observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_reserved0_SHIFT           1
+
+/* CLKGEN :: SECTOP_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SVD0_TOP_CLOCK_ENABLE - Svd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SVD0_TOP_MEMORY_STANDBY_ENABLE - Svd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD0_TOP_POWER_SWITCH_MEMORY - Svd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_MEMORY_STANDBY_ENABLE - Sys aon memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: SYS_AON_MEMORY_STANDBY_ENABLE :: AON_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_MEMORY_STANDBY_ENABLE_AON_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_POWER_SWITCH_MEMORY - Sys aon power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: SYS_AON_POWER_SWITCH_MEMORY :: AON_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_POWER_SWITCH_MEMORY_AON_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         4
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         1
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *USB0_CLOCK_DISABLE - Disable USB0's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: USB0_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_CLOCK_ENABLE - Usb0 clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_reserved0_SHIFT              2
+
+/* CLKGEN :: USB0_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_USB0_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB0_MEMORY_STANDBY_ENABLE - Usb0 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: USB0_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB0_OBSERVE_CLOCK - Usb0 observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_reserved0_SHIFT             1
+
+/* CLKGEN :: USB0_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_POWER_SWITCH_MEMORY - Usb0 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_reserved0_SHIFT       2
+
+/* CLKGEN :: USB0_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_CLOCK_DISABLE - Disable USB1's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_reserved0_SHIFT             2
+
+/* CLKGEN :: USB1_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_CLOCK_ENABLE - Usb1 clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_reserved0_SHIFT              2
+
+/* CLKGEN :: USB1_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK   0x00000002
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT  1
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK   0x00000001
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT  0
+#define BCHP_CLKGEN_USB1_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_MEMORY_STANDBY_ENABLE - Usb1 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: USB1_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB1_OBSERVE_CLOCK - Usb1 observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_OBSERVE_CLOCK :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_reserved0_SHIFT             1
+
+/* CLKGEN :: USB1_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_POWER_SWITCH_MEMORY - Usb1 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_reserved0_SHIFT       2
+
+/* CLKGEN :: USB1_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      2
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       3
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_AIO_ALTERNATE2_216_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE_AIO - Vec aio top clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_SHIFT   2
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE_VEC - Vec aio top clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: reserved0 [31:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_MASK    0xfffffff0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_SHIFT   4
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_DAC_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_DAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO - Vec aio top memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC - Vec aio top memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      2
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO - Vec aio top power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC - Vec aio top power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_common.h b/include/linux/brcmstb/7231b0/bchp_common.h
new file mode 100644
index 000000000000..86ea1f1075cf
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_common.h
@@ -0,0 +1,2192 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:00:52 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7231_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a3f004 /* XPT_SECURE_BUS_IF is last */
+#define BCHP_REGISTER_SIZE                                 0x0028fc01 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00070000
+#define BCHP_ILS_REGS_0_REG_END                            0x0007007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00070100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0007010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00070180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00070180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00070200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0007038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00080400
+#define BCHP_SVD_RGR_0_REG_END                             0x00080410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00100000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0010007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00100100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00100200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0010027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00100300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0010031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00100320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0010033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00100340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0010035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00100400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0010045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00100500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0010057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00100600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0010060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00100700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0010071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00100720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0010073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00100740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0010075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00100b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00100bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00100c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00100dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00100e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00100efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00100f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00100f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00100f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00100ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00101800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x001018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00101a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x001021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00102400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x001027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00103000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x001031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0010cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0010ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00140800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00140ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00141000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0014107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00144000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00144ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00145000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00145ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00146000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00147ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00148000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0014fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00151000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0015107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00151800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x001518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00151a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x001521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00154000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00154ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00155000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00155ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00156000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00157ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00158000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0015fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00160000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00160084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00162000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0016203c
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_PWMB_REG_START                                0x004065c0
+#define BCHP_PWMB_REG_END                                  0x004065e4
+#define BCHP_GIO_REG_START                                 0x00406600
+#define BCHP_GIO_REG_END                                   0x0040669c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_MCIF_REG_START                                0x00406d00
+#define BCHP_MCIF_REG_END                                  0x00406d20
+#define BCHP_MCIF_INTR2_REG_START                          0x00406d40
+#define BCHP_MCIF_INTR2_REG_END                            0x00406d6c
+#define BCHP_TMON_REG_START                                0x00406d80
+#define BCHP_TMON_REG_END                                  0x00406dd0
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406e00
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406e2c
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00408518
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410408
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042036c
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042347c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00440000
+#define BCHP_GENET_1_SYS_REG_END                           0x0044000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00440040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0044004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00440080
+#define BCHP_GENET_1_EXT_REG_END                           0x00440098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00440200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0044022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00440240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0044026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00440300
+#define BCHP_GENET_1_RBUF_REG_END                          0x004403ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00440600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00440628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00440800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00440ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00441000
+#define BCHP_GENET_1_HFB_REG_END                           0x00442010
+#define BCHP_GENET_1_RDMA_REG_START                        0x00443000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00443cb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00444000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00444c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_V3D_CTL_REG_START                             0x00451000
+#define BCHP_V3D_CTL_REG_END                               0x00451040
+#define BCHP_V3D_CLE_REG_START                             0x00451100
+#define BCHP_V3D_CLE_REG_END                               0x00451138
+#define BCHP_V3D_PTB_REG_START                             0x00451300
+#define BCHP_V3D_PTB_REG_END                               0x00451310
+#define BCHP_V3D_QPS_REG_START                             0x00451400
+#define BCHP_V3D_QPS_REG_END                               0x0045143c
+#define BCHP_V3D_VPM_REG_START                             0x00451500
+#define BCHP_V3D_VPM_REG_END                               0x00451504
+#define BCHP_V3D_PCTR_REG_START                            0x00451600
+#define BCHP_V3D_PCTR_REG_END                              0x004516fc
+#define BCHP_V3D_GCA_REG_START                             0x00451a00
+#define BCHP_V3D_GCA_REG_END                               0x00451a54
+#define BCHP_V3D_DBG_REG_START                             0x00451e00
+#define BCHP_V3D_DBG_REG_END                               0x00451f20
+#define BCHP_GFX_L2_REG_START                              0x00453000
+#define BCHP_GFX_L2_REG_END                                0x0045302c
+#define BCHP_GFX_GR_REG_START                              0x00454000
+#define BCHP_GFX_GR_REG_END                                0x0045400c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_OTG_REG_START                             0x00482000
+#define BCHP_USB_OTG_REG_END                               0x00482e00
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_USB1_OTG_REG_START                            0x00492000
+#define BCHP_USB1_OTG_REG_END                              0x00492e00
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_SID_REG_START                                 0x00540100
+#define BCHP_SID_REG_END                                   0x0054019c
+#define BCHP_SID_RLE_REG_START                             0x00540300
+#define BCHP_SID_RLE_REG_END                               0x0054039c
+#define BCHP_SID_DQ_REG_START                              0x00540400
+#define BCHP_SID_DQ_REG_END                                0x005404bc
+#define BCHP_SID_STRM_REG_START                            0x00540800
+#define BCHP_SID_STRM_REG_END                              0x0054087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00540c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00540c40
+#define BCHP_SID_ARC_REG_START                             0x00540f00
+#define BCHP_SID_ARC_REG_END                               0x00540f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00541800
+#define BCHP_SID_ARCDMA_REG_END                            0x00541840
+#define BCHP_SID_DMARAM_REG_START                          0x00541a00
+#define BCHP_SID_DMARAM_REG_END                            0x00541bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00542b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00542b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00542b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00542b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00543000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x005437fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00543900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x005439fc
+#define BCHP_SID_SYMB_REG_START                            0x00543a00
+#define BCHP_SID_SYMB_REG_END                              0x00543a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00543a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00543a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00548000
+#define BCHP_SID_BIGRAM_REG_END                            0x0054fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00551000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00551010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00555000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00555014
+#define BCHP_SID_GR_REG_START                              0x00560000
+#define BCHP_SID_GR_REG_END                                0x0056000c
+#define BCHP_SICH_REG_START                                0x00561000
+#define BCHP_SICH_REG_END                                  0x0056103c
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220bc
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222bc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_LBOX_1_REG_START                              0x00625200
+#define BCHP_LBOX_1_REG_END                                0x00625270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x00643420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068009c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x00685000
+#define BCHP_ITU656_DTG_0_REG_END                          0x00685154
+#define BCHP_ITU656_CSC_0_REG_START                        0x00685200
+#define BCHP_ITU656_CSC_0_REG_END                          0x00685230
+#define BCHP_ITU656_DVF_0_REG_START                        0x00685300
+#define BCHP_ITU656_DVF_0_REG_END                          0x00685314
+#define BCHP_ITU656_0_REG_START                            0x00685400
+#define BCHP_ITU656_0_REG_END                              0x00685420
+#define BCHP_VEC_CFG_REG_START                             0x00685600
+#define BCHP_VEC_CFG_REG_END                               0x00685708
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685a00
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x00685a2c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685b00
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685b18
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685c00
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685c08
+#define BCHP_DVP_TVG_0_REG_START                           0x00685d00
+#define BCHP_DVP_TVG_0_REG_END                             0x00685d88
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686074
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00687000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00687054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00687100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0068710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00687200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00687228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00687300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00687380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00687400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0068748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00687500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00687524
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00d4
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_HD_DVI_0_REG_START                            0x006a8000
+#define BCHP_HD_DVI_0_REG_END                              0x006a81fc
+#define BCHP_BVN_RGR_REG_START                             0x006ac000
+#define BCHP_BVN_RGR_REG_END                               0x006ac010
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001a0
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00208
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a053fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a07000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a07074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a07080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a07100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a07174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a07180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a071f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a07400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a07404
+#define BCHP_XPT_PSUB_REG_START                            0x00a07a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a07ac8
+#define BCHP_XPT_MPOD_REG_START                            0x00a07c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a07c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a07d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a07d08
+#define BCHP_XPT_RMX1_REG_START                            0x00a07e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a07e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00a08000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00a0805c
+#define BCHP_XPT_PB0_REG_START                             0x00a08100
+#define BCHP_XPT_PB0_REG_END                               0x00a08174
+#define BCHP_XPT_PB1_REG_START                             0x00a08180
+#define BCHP_XPT_PB1_REG_END                               0x00a081f4
+#define BCHP_XPT_PB2_REG_START                             0x00a08200
+#define BCHP_XPT_PB2_REG_END                               0x00a08274
+#define BCHP_XPT_PB3_REG_START                             0x00a08280
+#define BCHP_XPT_PB3_REG_END                               0x00a082f4
+#define BCHP_XPT_PB4_REG_START                             0x00a08300
+#define BCHP_XPT_PB4_REG_END                               0x00a08374
+#define BCHP_XPT_PB5_REG_START                             0x00a08380
+#define BCHP_XPT_PB5_REG_END                               0x00a083f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a0c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a12050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a15000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a15b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a16000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a17ccc
+#define BCHP_XPT_MSG_REG_START                             0x00a18000
+#define BCHP_XPT_MSG_REG_END                               0x00a1e014
+#define BCHP_XPT_RAVE_REG_START                            0x00a20000
+#define BCHP_XPT_RAVE_REG_END                              0x00a2bcfc
+#define BCHP_XPT_XPU_REG_START                             0x00a30000
+#define BCHP_XPT_XPU_REG_END                               0x00a347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a3f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a3f000
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved0 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..1d0c0b9cfa41
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:05:34 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..9a0ea8f08707
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:05:58 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 000000000000..8c0f9b905949
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:08:18 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:15p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_ebi.h b/include/linux/brcmstb/7231b0/bchp_ebi.h
new file mode 100644
index 000000000000..ab42d3cccff1
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:15:44 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:04p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00410828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00410854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..74610c0e9323
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:18 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:32p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK     0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT    22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 000000000000..b5422a12039e
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:20:13 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:33p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00411600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00411604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00411608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00411610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00411614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00411618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00411620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00411624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00411628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_intr2.h b/include/linux/brcmstb/7231b0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..d496a467c325
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:22:43 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:34p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_mspi.h b/include/linux/brcmstb/7231b0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..5a6fd9b3c478
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:24:34 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:35p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..f9e6822a6bf5
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:55 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 5:39p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h
new file mode 100644
index 000000000000..ae9c838374de
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_hif_top_ctrl.h
@@ -0,0 +1,530 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:11:47 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:19p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_UnSupport          3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SDIO_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_MASK             0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_SHIFT            0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SDIO_TP_SEL_DEFAULT          0
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_irq0.h b/include/linux/brcmstb/7231b0/bchp_irq0.h
new file mode 100644
index 000000000000..6a133b381038
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:45 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 6:11p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_irq1.h b/include/linux/brcmstb/7231b0/bchp_irq1.h
new file mode 100644
index 000000000000..aa14c59dc023
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:36:55 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..e2514da71434
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:18:31 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:22p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..194f0280f8a2
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:36:03 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:22p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_nand.h b/include/linux/brcmstb/7231b0/bchp_nand.h
new file mode 100644
index 000000000000..a54345dd5913
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:57 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 6:33p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00412910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00412914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00412918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h
new file mode 100644
index 000000000000..2113ed2ae2b8
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:14:27 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:26p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           1
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..73d5931cabe0
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Jun 22 16:17:51 2011
+ *                 MD5 Checksum         f1fe9dd101680af6476d6b0b4e1d855e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   6/22/11 10:26p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..6d809d288348
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6822 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 18:42:10 2011
+ *                 MD5 Checksum         2fa181eb09c8005dabf78dab1495aac5
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   8/9/11 5:02p pntruong
+ * SW7231-196: Synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404174 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1915813904
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1915813904
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:09] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffffe00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            9
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [08:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000001e0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_cs_swap [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_DEFAULT  0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_MASK          0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_SHIFT         1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare4 [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare4_DEFAULT       0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_jtag_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_jtag_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb3_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb3_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb2_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_5 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_5_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_4 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_4_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_jtag_0 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_jtag_0_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_jtag_0_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb3_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb3_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb3_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb2_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb2_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_pwrflt_4_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_4_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_pwrflt_3_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_pwrflt_3_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_pwrflt_2_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_2_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_pwrflt_1_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_pwrflt_1_disable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: mtsif_hys_en [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfff00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   20
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_069 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_068 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_066 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_065 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_064 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_063 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_062 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_061 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_060 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_059 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_058 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_055 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_054 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_053 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_052 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_051 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_050 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_049 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_048 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_047 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_07 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_PM_GPIO_07        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_06 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_PM_GPIO_06        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_05 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_PM_GPIO_05        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_04 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_PM_GPIO_04        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_PM_GPIO_03        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_15 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_14 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_14_PM_GPIO_14        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_13 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_13_PM_GPIO_13        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_12 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_12_PM_GPIO_12        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_11 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_PM_GPIO_11        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_25 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_TP_IN_25          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_25_PM_GPIO_25        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_24 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_24_PM_GPIO_24        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_23 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_23_PM_GPIO_23        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_22 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_TP_IN_24          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_21 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_20 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_20_PM_GPIO_20        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_19 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_19_PM_GPIO_19        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_33 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_32 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_TP_OUT_00         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_32_PM_GPIO_32        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_31 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_TP_IN_31          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_31_PM_GPIO_31        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_30 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_TP_IN_30          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_30_PM_GPIO_30        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_29 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_TP_IN_29          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_29_PM_GPIO_29        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_28          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_27          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_26          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_41 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_TP_OUT_01         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_41_PM_GPIO_41        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_40 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_40_PM_GPIO_40        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_39 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_39_PM_GPIO_39        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_38 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_38_PM_GPIO_38        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_37 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_37_PM_GPIO_37        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_49 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_48 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_47 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_46 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_45 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_TP_OUT_05         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_45_PM_GPIO_45        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_04         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_03         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_02         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_57 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_57_PM_GPIO_57        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_56 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_55 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_54 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_53 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_53_PM_GPIO_53        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_65 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_65_PM_GPIO_65        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_64 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_64_PM_GPIO_64        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_63 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_63_PM_GPIO_63        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_62 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_62_PM_GPIO_62        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_61 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_61_PM_GPIO_61        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_73 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_MPOD_M_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_72 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_MPOD_M_SDO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_71 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_MPOD_SCLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_70 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_MPOD_SCTL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_70_PM_GPIO_70        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_69 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_69_PM_GPIO_69        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_81 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_GPIO_81           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_SC0_RST           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_TP_OUT_08         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_81_PM_GPIO_81        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_80 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_GPIO_80           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_SC0_CLK           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_80_PM_GPIO_80        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_79 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_GPIO_79           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_SC0_VCC           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_TEST_THP          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_TP_OUT_06         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_79_PM_GPIO_79        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_78 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_GPIO_78           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_RMX0_PAUSE        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_I2S_LR0_IN        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_P1_INTR_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_78_PM_GPIO_78        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_77 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_GPIO_77           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_RMX0_VALID        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_SPI_M_SS1B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_77_PM_GPIO_77        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_CLK_OBSRV3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RO_OBSRV          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_89 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PKT1_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PPKT_I_SYNC      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_MTSIF0_SYNC      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_TP_OUT_16        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_88 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PKT1_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PPKT_I_VALID     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_MTSIF0_DATA0     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_TP_IN_11         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_88_PM_GPIO_88       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_87 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PKT1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PPKT_I_CLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_MTSIF0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_TP_IN_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_87_PM_GPIO_87       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_86 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_POD_EBI_DSB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_I2S_LR0_OUT      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_TP_OUT_13        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_86_PM_GPIO_86       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_85 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_POD_EBI_WE0B     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_I2S_DATA0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_TP_OUT_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_85_PM_GPIO_85       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_POD_EBI_RDB      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_CLK0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_11        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_97 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_I2S_LR0_OUT      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_ALT_TP_IN_1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_96 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_I2S_DATA0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_ALT_TP_OUT_1     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_95 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_GPIO_95          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_I2S_CLK0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_ALT_TP_IN_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_95_PM_GPIO_95       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_94 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_POD_EBI_RDB      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_ALT_TP_OUT_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_94_PM_GPIO_94       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_93 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_ALT_TP_IN_2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_93_PM_GPIO_93       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_OUT_2     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PKT1_ERROR       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PKT3_DATA        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MTSIF0_DATA1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_TP_OUT_18        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PKT1_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PKT3_CLK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PPKT_I_ERROR     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_TP_OUT_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_106 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_GPIO_106        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_TP_OUT_27       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_PM_GPIO_106     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_105 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_UART_CTS2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_CODEC_FSYNCB    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_MTSIF0_DATA5    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_TP_OUT_26       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_104 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT2_VALID      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT3_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_IR_OUT          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_UART_RX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_CODEC_SDI       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SPI_M_MISO      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MTSIF_ATS_RST   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_TP_OUT_25       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PM_GPIO_104     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_103 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PKT2_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_CODEC_MCLK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SPI_M_SCK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MTSIF0_DATA4    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_TP_OUT_24       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_102 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PKT2_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_HD_DVI0_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SATA_MDCLK      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_UART_RTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_CODEC_SDO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SPI_M_SS0B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MTSIF0_DATA3    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_TP_OUT_23       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PM_GPIO_102     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PKT2_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_HD_DVI0_10      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SATA_MDIO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_UART_TX2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_CODEC_SCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SPI_M_MOSI      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MTSIF0_DATA2    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_22       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_114 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET0_ACTIVITY  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_CLK_OBSRV       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_CLK_27M         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET1_ACTIVITY  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_ENET1_LINK      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_TP_OUT_29       9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_114_PM_GPIO_114     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_113 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_USB1_PWRFLT_4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_RMX1_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_113_PM_GPIO_113     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_112 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_USB1_PWRFLT_3   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_RMX1_PAUSE      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_P1_INTR_1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_PM_GPIO_112     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_111 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SDIO0_VCTL      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_PM_GPIO_111     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_TP_OUT_31       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_USB1_PWRON_4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_USB1_PWRON_3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_OUT_28       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_126 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_GPIO_126        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_SDIO0_DAT0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_I2S_DATA0_OUT   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_VO0_656_3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_PPKT_I_DATA_3   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_126_PM_GPIO_126     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_125 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_GPIO_125        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_SDIO0_CLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_I2S_CLK0_OUT    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_VO0_656_2       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_PPKT_I_DATA_2   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_125_PM_GPIO_125     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_SDIO0_PWR0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_VO0_656_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PPKT_I_DATA_1   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_124_PM_GPIO_124     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_SDIO0_WPROT     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_VO0_656_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PPKT_I_DATA_0   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_123_PM_GPIO_123     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_SDIO0_CMD       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_VO0_656_CLK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_122_PM_GPIO_122     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PKT4_SYNC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR0_OUT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EXT_IRQ2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_HD_DVI0_11      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MTSIF0_DATA7    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_I2S_LR1_OUT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_IN_09        9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PKT4_DATA       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA0_OUT   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EXT_IRQ1        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_HD_DVI0_20      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MTSIF0_DATA6    7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_I2S_DATA1_OUT   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_19       9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PKT4_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK0_OUT    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EXT_IRQ0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_HD_DVI0_21      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MTSIF_ATS_INC   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_I2S_CLK1_OUT    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_IN_23        9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     10
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_134 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_GPIO_134        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_MII_RX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_HD_DVI0_22      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_134_PM_GPIO_134     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_133 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_GPIO_133        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_POD_EBI_WE0B    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_PKT4_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_HD_DVI0_23      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_133_PM_GPIO_133     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_132 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_GPIO_132        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_MII_RX_DV       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_HD_DVI0_24      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_132_PM_GPIO_132     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_131 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_GPIO_131        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_SDIO0_LED       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_VEC_HSYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_131_PM_GPIO_131     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_130 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_GPIO_130        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_SDIO0_PRES      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_I2S_LR0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_VO0_656_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PPKT_I_DATA_7   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_130_PM_GPIO_130     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_129 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_GPIO_129        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_SDIO0_DAT3      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_I2S_DATA0_IN    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_VO0_656_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PPKT_I_DATA_6   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_129_PM_GPIO_129     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_128 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_GPIO_128        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_SDIO0_DAT2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_I2S_CLK0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_VO0_656_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PPKT_I_DATA_5   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_128_PM_GPIO_128     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_127 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_GPIO_127        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_SDIO0_DAT1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_I2S_LR0_OUT     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_VO0_656_4       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PPKT_I_DATA_4   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_127_PM_GPIO_127     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_142 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_GPIO_142        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_MII_RXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_SC1_PRES        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_HD_DVI0_DE      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_142_PM_GPIO_142     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_141 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_GPIO_141        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_MII_RXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_HD_DVI0_VS      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_141_PM_GPIO_141     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_140 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_GPIO_140        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_MII_RXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_HD_DVI0_HS      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_140_PM_GPIO_140     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_139 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_GPIO_139        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_MII_RXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_SPI_M_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_139_PM_GPIO_139     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_138 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_GPIO_138        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_MII_TX_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_SPI_M_MISO      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_HD_DVI0_CLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_138_PM_GPIO_138     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_137 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_GPIO_137        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_MII_MDIO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_137_PM_GPIO_137     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_136 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_GPIO_136        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_POD_EBI_RDB     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PKT4_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_HD_DVI0_18      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_136_PM_GPIO_136     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_135 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_GPIO_135        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_POD_EBI_DSB     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PKT4_DATA       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_HD_DVI0_19      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_135_PM_GPIO_135     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_02_BSC_M1_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_149 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_GPIO_149        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_MII_MDC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_SPI_M_SCK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_149_PM_GPIO_149     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_148 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_GPIO_148        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_POD2CHIP_MCLKI  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_HD_DVI0_25      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_148_PM_GPIO_148     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_147 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_GPIO_147        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_MII_TX_EN       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_SPI_M_MOSI      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_147_PM_GPIO_147     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_146 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_GPIO_146        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_MII_TXD_00      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_SC1_IO          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_HD_DVI0_26      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_146_PM_GPIO_146     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_145 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_GPIO_145        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_MII_TXD_01      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_SC1_RST         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_HD_DVI0_27      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_145_PM_GPIO_145     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_144 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_GPIO_144        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_MII_TXD_02      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_SC1_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_HD_DVI0_28      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_144_PM_GPIO_144     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_143 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_GPIO_143        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_MII_TXD_03      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_SC1_VCC         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_HD_DVI0_29      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_143_PM_GPIO_143     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xfffff000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          12
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_BSC_M2_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_05_EXT_IRQ1        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_04_BSC_M2_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sgpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sgpio_03_BSC_M1_SDA      1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_11_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_10_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_09_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_08_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_28_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_27_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_26_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_25_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_24_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_23_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_43_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_42_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_41_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_40_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_58_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_57_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_56_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_55_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_73_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_72_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_71_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_70_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_88_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_87_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_86_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_85_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_104_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_103_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_102_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_101_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_95_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_95_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_123_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_122_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_118_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_117_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_106_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_106_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_138_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_138_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_137_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_137_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_136_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_136_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_135_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_135_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_134_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_134_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_133_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_133_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_132_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_132_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_131_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_131_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_130_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_130_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_129_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_129_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_128_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_128_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_127_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_127_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_126_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_126_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_125_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_125_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_149_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_149_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_148_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_148_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_147_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_147_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_146_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_146_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_145_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_145_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_144_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_144_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_143_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_143_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_142_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_142_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_141_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_141_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_140_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_140_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_139_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_139_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_111 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_111_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_20 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_20_DEFAULT 1
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffffc
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffffc
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_timer.h b/include/linux/brcmstb/7231b0/bchp_timer.h
new file mode 100644
index 000000000000..1987416f1ef5
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:13:07 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:21p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uarta.h b/include/linux/brcmstb/7231b0/bchp_uarta.h
new file mode 100644
index 000000000000..f0e1936e12af
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:25:46 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:23p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uartb.h b/include/linux/brcmstb/7231b0/bchp_uartb.h
new file mode 100644
index 000000000000..537b74f4afb9
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:38:55 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_uartc.h b/include/linux/brcmstb/7231b0/bchp_uartc.h
new file mode 100644
index 000000000000..63240a75cdd3
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon May 17 03:30:38 2010
+ *                 MD5 Checksum         48de0819069cffb1a27afe66f66cd920
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h
new file mode 100644
index 000000000000..1f203179f580
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Aug 24 17:42:44 2010
+ *                 MD5 Checksum         39761c6e4b9d69cf41e7412c1f6df022
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/a0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   8/25/10 2:00p albertl
+ * HW7231-39: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..6db4b5794569
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_usb_ctrl.h
@@ -0,0 +1,675 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:18:38 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 7:27p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7c000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/bchp_wktmr.h b/include/linux/brcmstb/7231b0/bchp_wktmr.h
new file mode 100644
index 000000000000..a05d081dd58e
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:13:12 2011
+ *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/13/11 3:03p albertl
+ * SW7231-123: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7231b0/brcmirq.h b/include/linux/brcmstb/7231b0/brcmirq.h
new file mode 100644
index 000000000000..b2d71bb4ae9a
--- /dev/null
+++ b/include/linux/brcmstb/7231b0/brcmirq.h
@@ -0,0 +1,48 @@
+/*
+ * 7231b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_GENET_1_A	27
+#define BRCM_IRQ_GENET_1_B	28
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_MOCA		36
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SATA		41
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7250b0/bchp_bspi.h b/include/linux/brcmstb/7250b0/bchp_bspi.h
new file mode 100644
index 000000000000..13c7cda907ab
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_bspi.h
@@ -0,0 +1,445 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:49 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00443200 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00443204 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00443208 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0044320c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00443210 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00443214 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00443218 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0044321c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00443220 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00443224 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00443228 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0044322c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00443230 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00443234 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00443238 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0044323c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00443240 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00443244 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00443248 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0044324c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000002
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000e00
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000001
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_bspi_raf.h b/include/linux/brcmstb/7250b0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..8f764170a38a
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_bspi_raf.h
@@ -0,0 +1,162 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:51 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00443300 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00443304 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00443308 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0044330c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00443310 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00443314 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00443318 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0044331c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00443320 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_common.h b/include/linux/brcmstb/7250b0/bchp_common.h
new file mode 100644
index 000000000000..95ed1f24cf42
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_common.h
@@ -0,0 +1,3975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:34 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7250_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0xf0000000
+#define BCHP_REGISTER_START                                0x00100000 /* HEVD_OL_CPU_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x01273400 /* DEMOD_XPT_FE is last */
+#define BCHP_REGISTER_SIZE                                 0x0045cd00 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_START                  0x00100000
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_END                    0x00100108
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_START                   0x00100400
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_END                     0x00100440
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START                 0x00100800
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END                   0x00100ffc
+#define BCHP_HEVD_OL_SINT_0_REG_START                      0x00101000
+#define BCHP_HEVD_OL_SINT_0_REG_END                        0x00101028
+#define BCHP_HEVD_OL_LDST_0_REG_START                      0x00108000
+#define BCHP_HEVD_OL_LDST_0_REG_END                        0x0010fffc
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00110b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00110bfc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00112400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x001127fc
+#define BCHP_HEVD_CABAC_0_REG_START                        0x00113000
+#define BCHP_HEVD_CABAC_0_REG_END                          0x0011307c
+#define BCHP_HEVD_OL_CTL_0_REG_START                       0x00114000
+#define BCHP_HEVD_OL_CTL_0_REG_END                         0x001151fc
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00120100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x001201fc
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00120300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0012031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00120320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0012033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00120340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0012035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00120400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0012045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00120500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0012057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00120600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0012060c
+#define BCHP_DECODE_VP6_DCP_0_REG_START                    0x00120620
+#define BCHP_DECODE_VP6_DCP_0_REG_END                      0x0012062c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00120700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0012071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00120720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0012073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00120740
+#define BCHP_DECODE_MB_0_REG_END                           0x0012075c
+#define BCHP_DECODE_SINT_0_REG_START                       0x00120c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00120dfc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00123000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x001231fc
+#define BCHP_HEVD_BE_GLOBAL_0_REG_START                    0x00124000
+#define BCHP_HEVD_BE_GLOBAL_0_REG_END                      0x00124030
+#define BCHP_HEVD_IXFORM_0_REG_START                       0x00124100
+#define BCHP_HEVD_IXFORM_0_REG_END                         0x001241fc
+#define BCHP_HEVD_MCOMP_0_REG_START                        0x00124200
+#define BCHP_HEVD_MCOMP_0_REG_END                          0x001242fc
+#define BCHP_HEVD_SPRED_0_REG_START                        0x00124300
+#define BCHP_HEVD_SPRED_0_REG_END                          0x001243f0
+#define BCHP_HEVD_FILTER_0_REG_START                       0x00124400
+#define BCHP_HEVD_FILTER_0_REG_END                         0x001244fc
+#define BCHP_HEVD_OUTPUT_0_REG_START                       0x00124500
+#define BCHP_HEVD_OUTPUT_0_REG_END                         0x001245fc
+#define BCHP_HEVD_MARKER_0_REG_START                       0x00124f00
+#define BCHP_HEVD_MARKER_0_REG_END                         0x00124f7c
+#define BCHP_HEVD_FE_CTRL_0_REG_START                      0x00125000
+#define BCHP_HEVD_FE_CTRL_0_REG_END                        0x0012507c
+#define BCHP_HEVD_STRM_IN_0_REG_START                      0x00125100
+#define BCHP_HEVD_STRM_IN_0_REG_END                        0x00125118
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START                  0x00125200
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END                    0x00125230
+#define BCHP_HEVD_VECGEN_0_REG_START                       0x00125400
+#define BCHP_HEVD_VECGEN_0_REG_END                         0x0012568c
+#define BCHP_DCD_PIPE_CTL_0_REG_START                      0x00126000
+#define BCHP_DCD_PIPE_CTL_0_REG_END                        0x00126404
+#define BCHP_HEVD_PCACHE_0_REG_START                       0x00126800
+#define BCHP_HEVD_PCACHE_0_REG_END                         0x00126838
+#define BCHP_HEVD_PFRI_0_REG_START                         0x00126a00
+#define BCHP_HEVD_PFRI_0_REG_END                           0x00126b58
+#define BCHP_RVC_0_REG_START                               0x00126c00
+#define BCHP_RVC_0_REG_END                                 0x00126c20
+#define BCHP_ILS_REGS_0_REG_START                          0x00127000
+#define BCHP_ILS_REGS_0_REG_END                            0x001270fc
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00127100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0012710c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00127180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00127184
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00127200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0012738c
+#define BCHP_ILB_REGS_0_REG_START                          0x00127400
+#define BCHP_ILB_REGS_0_REG_END                            0x00127410
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00128100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001281fc
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00128300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0012831c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00128320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0012833c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00128400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0012845c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00128500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0012857c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00128700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0012871c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00128720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0012873c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00128740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0012875c
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00128c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00128dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00128e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00128efc
+#define BCHP_BLD_BL_CPU_REGS_0_REG_START                   0x0012c000
+#define BCHP_BLD_BL_CPU_REGS_0_REG_END                     0x0012c108
+#define BCHP_BLD_BL_CPU_DMA_0_REG_START                    0x0012c400
+#define BCHP_BLD_BL_CPU_DMA_0_REG_END                      0x0012c440
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START                  0x0012c800
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END                    0x0012cffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x0012d000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x0012d090
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_START                  0x00130000
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_END                    0x00130108
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_START                   0x00130400
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_END                     0x00130440
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START                 0x00130800
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END                   0x00130ffc
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START                 0x00131000
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END                   0x0013100c
+#define BCHP_HEVD_IL_LDST_0_REG_START                      0x00134000
+#define BCHP_HEVD_IL_LDST_0_REG_END                        0x00137ffc
+#define BCHP_DECODE_MAIN_2_0_REG_START                     0x00140100
+#define BCHP_DECODE_MAIN_2_0_REG_END                       0x001401fc
+#define BCHP_DECODE_MCOM_2_0_REG_START                     0x00140300
+#define BCHP_DECODE_MCOM_2_0_REG_END                       0x0014031c
+#define BCHP_DECODE_SPRE_2_0_REG_START                     0x00140320
+#define BCHP_DECODE_SPRE_2_0_REG_END                       0x0014033c
+#define BCHP_DECODE_WPRD_2_0_REG_START                     0x00140340
+#define BCHP_DECODE_WPRD_2_0_REG_END                       0x0014035c
+#define BCHP_DECODE_DQNT_2_0_REG_START                     0x00140400
+#define BCHP_DECODE_DQNT_2_0_REG_END                       0x0014045c
+#define BCHP_DECODE_DQNT_8X8_2_0_REG_START                 0x00140500
+#define BCHP_DECODE_DQNT_8X8_2_0_REG_END                   0x0014057c
+#define BCHP_DECODE_VP8_XFRM_2_0_REG_START                 0x00140600
+#define BCHP_DECODE_VP8_XFRM_2_0_REG_END                   0x0014060c
+#define BCHP_DECODE_VP6_DCP_2_0_REG_START                  0x00140620
+#define BCHP_DECODE_VP6_DCP_2_0_REG_END                    0x0014062c
+#define BCHP_DECODE_XFRM_2_0_REG_START                     0x00140700
+#define BCHP_DECODE_XFRM_2_0_REG_END                       0x0014071c
+#define BCHP_DECODE_DBLK_2_0_REG_START                     0x00140720
+#define BCHP_DECODE_DBLK_2_0_REG_END                       0x0014073c
+#define BCHP_DECODE_MB_2_0_REG_START                       0x00140740
+#define BCHP_DECODE_MB_2_0_REG_END                         0x0014075c
+#define BCHP_DECODE_SINT_2_0_REG_START                     0x00140c00
+#define BCHP_DECODE_SINT_2_0_REG_END                       0x00140dfc
+#define BCHP_DECODE_WPTBL_2_0_REG_START                    0x00143000
+#define BCHP_DECODE_WPTBL_2_0_REG_END                      0x001431fc
+#define BCHP_HEVD_BE_GLOBAL_2_0_REG_START                  0x00144000
+#define BCHP_HEVD_BE_GLOBAL_2_0_REG_END                    0x00144030
+#define BCHP_HEVD_IXFORM_2_0_REG_START                     0x00144100
+#define BCHP_HEVD_IXFORM_2_0_REG_END                       0x001441fc
+#define BCHP_HEVD_MCOMP_2_0_REG_START                      0x00144200
+#define BCHP_HEVD_MCOMP_2_0_REG_END                        0x001442fc
+#define BCHP_HEVD_SPRED_2_0_REG_START                      0x00144300
+#define BCHP_HEVD_SPRED_2_0_REG_END                        0x001443f0
+#define BCHP_HEVD_FILTER_2_0_REG_START                     0x00144400
+#define BCHP_HEVD_FILTER_2_0_REG_END                       0x001444fc
+#define BCHP_HEVD_OUTPUT_2_0_REG_START                     0x00144500
+#define BCHP_HEVD_OUTPUT_2_0_REG_END                       0x001445fc
+#define BCHP_HEVD_MARKER_2_0_REG_START                     0x00144f00
+#define BCHP_HEVD_MARKER_2_0_REG_END                       0x00144f7c
+#define BCHP_HEVD_FE_CTRL_2_0_REG_START                    0x00145000
+#define BCHP_HEVD_FE_CTRL_2_0_REG_END                      0x0014507c
+#define BCHP_HEVD_STRM_IN_2_0_REG_START                    0x00145100
+#define BCHP_HEVD_STRM_IN_2_0_REG_END                      0x00145118
+#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_START                0x00145200
+#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_END                  0x00145230
+#define BCHP_HEVD_VECGEN_2_0_REG_START                     0x00145400
+#define BCHP_HEVD_VECGEN_2_0_REG_END                       0x0014568c
+#define BCHP_DCD_PIPE_CTL_2_0_REG_START                    0x00146000
+#define BCHP_DCD_PIPE_CTL_2_0_REG_END                      0x00146404
+#define BCHP_HEVD_PCACHE_2_0_REG_START                     0x00146800
+#define BCHP_HEVD_PCACHE_2_0_REG_END                       0x00146838
+#define BCHP_HEVD_PFRI_2_0_REG_START                       0x00146a00
+#define BCHP_HEVD_PFRI_2_0_REG_END                         0x00146b58
+#define BCHP_RVC_2_0_REG_START                             0x00146c00
+#define BCHP_RVC_2_0_REG_END                               0x00146c20
+#define BCHP_ILS_REGS_2_0_REG_START                        0x00147000
+#define BCHP_ILS_REGS_2_0_REG_END                          0x001470fc
+#define BCHP_ILS_SCALE_ADDR_2_0_REG_START                  0x00147100
+#define BCHP_ILS_SCALE_ADDR_2_0_REG_END                    0x0014710c
+#define BCHP_ILS_SPSCALE_FILL_2_0_REG_START                0x00147180
+#define BCHP_ILS_SPSCALE_FILL_2_0_REG_END                  0x00147184
+#define BCHP_ILS_MVSCALE_2_0_REG_START                     0x00147200
+#define BCHP_ILS_MVSCALE_2_0_REG_END                       0x0014738c
+#define BCHP_ILB_REGS_2_0_REG_START                        0x00147400
+#define BCHP_ILB_REGS_2_0_REG_END                          0x00147410
+#define BCHP_BLD_DECODE_MAIN_2_0_REG_START                 0x00148100
+#define BCHP_BLD_DECODE_MAIN_2_0_REG_END                   0x001481fc
+#define BCHP_BLD_DECODE_MCOM_2_0_REG_START                 0x00148300
+#define BCHP_BLD_DECODE_MCOM_2_0_REG_END                   0x0014831c
+#define BCHP_BLD_DECODE_SPRE_2_0_REG_START                 0x00148320
+#define BCHP_BLD_DECODE_SPRE_2_0_REG_END                   0x0014833c
+#define BCHP_BLD_DECODE_DQNT_2_0_REG_START                 0x00148400
+#define BCHP_BLD_DECODE_DQNT_2_0_REG_END                   0x0014845c
+#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_START             0x00148500
+#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_END               0x0014857c
+#define BCHP_BLD_DECODE_XFRM_2_0_REG_START                 0x00148700
+#define BCHP_BLD_DECODE_XFRM_2_0_REG_END                   0x0014871c
+#define BCHP_BLD_DECODE_DBLK_2_0_REG_START                 0x00148720
+#define BCHP_BLD_DECODE_DBLK_2_0_REG_END                   0x0014873c
+#define BCHP_BLD_DECODE_MB_2_0_REG_START                   0x00148740
+#define BCHP_BLD_DECODE_MB_2_0_REG_END                     0x0014875c
+#define BCHP_BLD_DECODE_SINT_2_0_REG_START                 0x00148c00
+#define BCHP_BLD_DECODE_SINT_2_0_REG_END                   0x00148dfc
+#define BCHP_BLD_DECODE_RVC_2_0_REG_START                  0x00148e00
+#define BCHP_BLD_DECODE_RVC_2_0_REG_END                    0x00148efc
+#define BCHP_BLD_BL_CPU_REGS_2_0_REG_START                 0x0014c000
+#define BCHP_BLD_BL_CPU_REGS_2_0_REG_END                   0x0014c108
+#define BCHP_BLD_BL_CPU_DMA_2_0_REG_START                  0x0014c400
+#define BCHP_BLD_BL_CPU_DMA_2_0_REG_END                    0x0014c440
+#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_START                0x0014c800
+#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_END                  0x0014cffc
+#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_START              0x0014d000
+#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_END                0x0014d090
+#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_START                0x00150000
+#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_END                  0x00150108
+#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_START                 0x00150400
+#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_END                   0x00150440
+#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_START               0x00150800
+#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_END                 0x00150ffc
+#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_START               0x00151000
+#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_END                 0x0015100c
+#define BCHP_HEVD_IL_LDST_2_0_REG_START                    0x00154000
+#define BCHP_HEVD_IL_LDST_2_0_REG_END                      0x00157ffc
+#define BCHP_HVD_INTR2_0_REG_START                         0x00180000
+#define BCHP_HVD_INTR2_0_REG_END                           0x0018002c
+#define BCHP_HVD_RGR_0_REG_START                           0x00180400
+#define BCHP_HVD_RGR_0_REG_END                             0x00180410
+#define BCHP_VICH_0_REG_START                              0x001a0000
+#define BCHP_VICH_0_REG_END                                0x001a008b
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x00300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x0030fffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x00310000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x003103fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x00310400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x00310450
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x00310460
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x00310470
+#define BCHP_SCPU_INTR1_REG_START                          0x00310480
+#define BCHP_SCPU_INTR1_REG_END                            0x00310498
+#define BCHP_INTERNAL_INTR2_REG_START                      0x003104c0
+#define BCHP_INTERNAL_INTR2_REG_END                        0x003104ec
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x00310500
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x0031052c
+#define BCHP_SCPU_HW_INTR2_REG_START                       0x00310540
+#define BCHP_SCPU_HW_INTR2_REG_END                         0x0031056c
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x00311000
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x0031102c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x00311040
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x0031106c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x00312000
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x00312008
+#define BCHP_SCPU_HDMI_CTRL_REG_START                      0x00312080
+#define BCHP_SCPU_HDMI_CTRL_REG_END                        0x00312084
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x00312100
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x00312114
+#define BCHP_SAGE_UART_REG_START                           0x00312200
+#define BCHP_SAGE_UART_REG_END                             0x0031221c
+#define BCHP_SCPU_PM_REG_START                             0x00312980
+#define BCHP_SCPU_PM_REG_END                               0x00312988
+#define BCHP_SCPU_TIMER_REG_START                          0x00312e80
+#define BCHP_SCPU_TIMER_REG_END                            0x00312ebc
+#define BCHP_BSP_CMDBUF_REG_START                          0x0032c800
+#define BCHP_BSP_CMDBUF_REG_END                            0x0032cffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032d000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032d0b0
+#define BCHP_BSP_PKL_REG_START                             0x0032d300
+#define BCHP_BSP_PKL_REG_END                               0x0032d37c
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032d800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032d82c
+#define BCHP_BSP_VISTA_GENACC_REG_START                    0x0032d900
+#define BCHP_BSP_VISTA_GENACC_REG_END                      0x0032d9fc
+#define BCHP_BSP_OTP_SCRATCH_REG_START                     0x0032e000
+#define BCHP_BSP_OTP_SCRATCH_REG_END                       0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0037fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00380000
+#define BCHP_SECTOP_GRB_REG_END                            0x0038000c
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START             0x00380080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END               0x003800ac
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START             0x00380100
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END               0x0038012c
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START             0x00380180
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END               0x003801ac
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00380200
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x003802c8
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004007fc
+#define BCHP_SUN_GR_REG_START                              0x00401000
+#define BCHP_SUN_GR_REG_END                                0x0040100c
+#define BCHP_SSP_RG_REG_START                              0x00401200
+#define BCHP_SSP_RG_REG_END                                0x0040120c
+#define BCHP_SUN_RG_REG_START                              0x00401400
+#define BCHP_SUN_RG_REG_END                                0x0040140c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x00403044
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404520
+#define BCHP_BBSI_RG_REG_START                             0x00405c00
+#define BCHP_BBSI_RG_REG_END                               0x00405c0c
+#define BCHP_MPM_TOP_GR_REG_START                          0x00406000
+#define BCHP_MPM_TOP_GR_REG_END                            0x0040600c
+#define BCHP_PWM_REG_START                                 0x00408000
+#define BCHP_PWM_REG_END                                   0x00408024
+#define BCHP_PWMB_REG_START                                0x00409000
+#define BCHP_PWMB_REG_END                                  0x00409024
+#define BCHP_IRB_REG_START                                 0x0040a000
+#define BCHP_IRB_REG_END                                   0x0040a138
+#define BCHP_BSCA_REG_START                                0x0040a180
+#define BCHP_BSCA_REG_END                                  0x0040a1d4
+#define BCHP_GIO_REG_START                                 0x0040a200
+#define BCHP_GIO_REG_END                                   0x0040a29c
+#define BCHP_TIMER_REG_START                               0x0040a300
+#define BCHP_TIMER_REG_END                                 0x0040a33c
+#define BCHP_PM_REG_START                                  0x0040a340
+#define BCHP_PM_REG_END                                    0x0040a348
+#define BCHP_IRQ0_REG_START                                0x0040a380
+#define BCHP_IRQ0_REG_END                                  0x0040a384
+#define BCHP_IRQ1_REG_START                                0x0040a3c0
+#define BCHP_IRQ1_REG_END                                  0x0040a3c4
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x0040a800
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x0040a82c
+#define BCHP_SCA_REG_START                                 0x0040b000
+#define BCHP_SCA_REG_END                                   0x0040b0bc
+#define BCHP_SCB_REG_START                                 0x0040b100
+#define BCHP_SCB_REG_END                                   0x0040b1bc
+#define BCHP_SCIRQ0_REG_START                              0x0040b200
+#define BCHP_SCIRQ0_REG_END                                0x0040b204
+#define BCHP_SCIRQ1_REG_START                              0x0040b240
+#define BCHP_SCIRQ1_REG_END                                0x0040b244
+#define BCHP_SCIRQ_SCPU_REG_START                          0x0040b280
+#define BCHP_SCIRQ_SCPU_REG_END                            0x0040b284
+#define BCHP_UARTA_REG_START                               0x0040b400
+#define BCHP_UARTA_REG_END                                 0x0040b41c
+#define BCHP_UARTB_REG_START                               0x0040b440
+#define BCHP_UARTB_REG_END                                 0x0040b45c
+#define BCHP_UARTC_REG_START                               0x0040b480
+#define BCHP_UARTC_REG_END                                 0x0040b49c
+#define BCHP_UPG_UART_DMA_REG_START                        0x0040b500
+#define BCHP_UPG_UART_DMA_REG_END                          0x0040b530
+#define BCHP_AON_CTRL_REG_START                            0x00410000
+#define BCHP_AON_CTRL_REG_END                              0x004103fc
+#define BCHP_AON_L2_REG_START                              0x00410600
+#define BCHP_AON_L2_REG_END                                0x0041062c
+#define BCHP_AON_PM_L2_REG_START                           0x00410640
+#define BCHP_AON_PM_L2_REG_END                             0x0041066c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00410700
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00410718
+#define BCHP_AON_HDMI_TX_REG_START                         0x00410800
+#define BCHP_AON_HDMI_TX_REG_END                           0x004108ac
+#define BCHP_AON_HDMI_RX_REG_START                         0x00411200
+#define BCHP_AON_HDMI_RX_REG_END                           0x004112d4
+#define BCHP_CNTControlBase_REG_START                      0x00412000
+#define BCHP_CNTControlBase_REG_END                        0x00412ffc
+#define BCHP_CNTReadBase_REG_START                         0x00414000
+#define BCHP_CNTReadBase_REG_END                           0x00414ffc
+#define BCHP_MSPI_REG_START                                0x00416000
+#define BCHP_MSPI_REG_END                                  0x0041617c
+#define BCHP_LDK_REG_START                                 0x00417000
+#define BCHP_LDK_REG_END                                   0x0041703c
+#define BCHP_PM_AON_REG_START                              0x00417040
+#define BCHP_PM_AON_REG_END                                0x00417048
+#define BCHP_ICAP_REG_START                                0x00417080
+#define BCHP_ICAP_REG_END                                  0x004170bc
+#define BCHP_KBD1_REG_START                                0x004170c0
+#define BCHP_KBD1_REG_END                                  0x004170fc
+#define BCHP_KBD2_REG_START                                0x00417100
+#define BCHP_KBD2_REG_END                                  0x0041713c
+#define BCHP_KBD3_REG_START                                0x00417140
+#define BCHP_KBD3_REG_END                                  0x0041717c
+#define BCHP_BSCC_REG_START                                0x00417180
+#define BCHP_BSCC_REG_END                                  0x004171d4
+#define BCHP_BSCD_REG_START                                0x00417200
+#define BCHP_BSCD_REG_END                                  0x00417254
+#define BCHP_IRQ0_AON_REG_START                            0x00417280
+#define BCHP_IRQ0_AON_REG_END                              0x00417284
+#define BCHP_IRQ1_AON_REG_START                            0x004172c0
+#define BCHP_IRQ1_AON_REG_END                              0x004172c4
+#define BCHP_GIO_AON_REG_START                             0x00417300
+#define BCHP_GIO_AON_REG_END                               0x0041733c
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00417400
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x0041742c
+#define BCHP_WKTMR_REG_START                               0x00417480
+#define BCHP_WKTMR_REG_END                                 0x00417490
+#define BCHP_BICAP_REG_START                               0x004174c0
+#define BCHP_BICAP_REG_END                                 0x004174f8
+#define BCHP_V3D_BPCM_REG_START                            0x0041d000
+#define BCHP_V3D_BPCM_REG_END                              0x0041d010
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0041e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0041e7fc
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0041e800
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0041e808
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0041e900
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0041e97c
+#define BCHP_BOOTSRAM_SECURE_REG_START                     0x00420000
+#define BCHP_BOOTSRAM_SECURE_REG_END                       0x0042fffc
+#define BCHP_ITCH0_REG_START                               0x00430000
+#define BCHP_ITCH0_REG_END                                 0x00430000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00430400
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00430400
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00430500
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00430500
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00430600
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00430600
+#define BCHP_NAND_SECURE_REG_START                         0x00430800
+#define BCHP_NAND_SECURE_REG_END                           0x00430800
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START       0x00430c00
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END         0x00430c00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START               0x00430e00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END                 0x00430ffc
+#define BCHP_HIF_CONTINUATION_SECURE_REG_START             0x00431000
+#define BCHP_HIF_CONTINUATION_SECURE_REG_END               0x00431004
+#define BCHP_SDIO_0_HOST_REG_START                         0x00440000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004400fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00440100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004401fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x00440200
+#define BCHP_SDIO_1_HOST_REG_END                           0x004402fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x00440300
+#define BCHP_SDIO_1_CFG_REG_END                            0x004403fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x00440400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0044043c
+#define BCHP_EBI_REG_START                                 0x00440800
+#define BCHP_EBI_REG_END                                   0x00440bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00441000
+#define BCHP_HIF_INTR2_REG_END                             0x0044102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00441100
+#define BCHP_IPI0_INTR2_REG_END                            0x0044112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00441200
+#define BCHP_IPI1_INTR2_REG_END                            0x0044122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00441500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0044153c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x00441600
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x0044163c
+#define BCHP_HIF_RGR2_REG_START                            0x00441700
+#define BCHP_HIF_RGR2_REG_END                              0x00441710
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00441a00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00441a2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00442000
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0044203c
+#define BCHP_HIF_CPUBIUARCH_REG_START                      0x00442200
+#define BCHP_HIF_CPUBIUARCH_REG_END                        0x004423fc
+#define BCHP_HIF_CPUBIUCTRL_REG_START                      0x00442400
+#define BCHP_HIF_CPUBIUCTRL_REG_END                        0x004427fc
+#define BCHP_NAND_REG_START                                0x00442800
+#define BCHP_NAND_REG_END                                  0x00442dfc
+#define BCHP_FLASH_DMA_REG_START                           0x00443000
+#define BCHP_FLASH_DMA_REG_END                             0x00443028
+#define BCHP_BSPI_REG_START                                0x00443200
+#define BCHP_BSPI_REG_END                                  0x0044324c
+#define BCHP_BSPI_RAF_REG_START                            0x00443300
+#define BCHP_BSPI_RAF_REG_END                              0x00443320
+#define BCHP_HIF_MSPI_REG_START                            0x00443400
+#define BCHP_HIF_MSPI_REG_END                              0x00443584
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START          0x00443600
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END            0x00443604
+#define BCHP_BOOTSRAM_TM_REG_START                         0x00450000
+#define BCHP_BOOTSRAM_TM_REG_END                           0x0045fffc
+#define BCHP_HIF_CONTINUATION_REG_START                    0x00462000
+#define BCHP_HIF_CONTINUATION_REG_END                      0x0046200c
+#define BCHP_SATA_GRB_REG_START                            0x00468000
+#define BCHP_SATA_GRB_REG_END                              0x0046800c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00468040
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00468060
+#define BCHP_SATA3_INTR2_REG_START                         0x00468080
+#define BCHP_SATA3_INTR2_REG_END                           0x004680ac
+#define BCHP_PORT0_SATA3_PCB_REG_START                     0x00468100
+#define BCHP_PORT0_SATA3_PCB_REG_END                       0x00468ffc
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x0046a000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x0046a028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0046a02c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0046a09c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x0046a100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0046a11c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x0046a120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x0046a134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x0046a138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0046a17c
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x0046a600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x0046a664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x0046a700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x0046a730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x0046a740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x0046a764
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x0046a800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x0046a880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x0046a900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x0046a934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x0046a940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x0046a954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x0046a958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x0046a998
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START                 0x00470000
+#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END                   0x0047003c
+#define BCHP_PCIE_0_RC_CFG_PM_REG_START                    0x00470048
+#define BCHP_PCIE_0_RC_CFG_PM_REG_END                      0x0047004c
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START                  0x004700ac
+#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END                    0x004700e4
+#define BCHP_PCIE_0_RC_CFG_AER_REG_START                   0x00470100
+#define BCHP_PCIE_0_RC_CFG_AER_REG_END                     0x00470134
+#define BCHP_PCIE_0_RC_CFG_VC_REG_START                    0x00470160
+#define BCHP_PCIE_0_RC_CFG_VC_REG_END                      0x00470178
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START                0x00470180
+#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END                  0x004701a4
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START                 0x00470404
+#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END                   0x00470418
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START                 0x00470428
+#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END                   0x00470630
+#define BCHP_PCIE_0_RC_TL_REG_START                        0x00470800
+#define BCHP_PCIE_0_RC_TL_REG_END                          0x00470998
+#define BCHP_PCIE_0_RC_DL_REG_START                        0x00471000
+#define BCHP_PCIE_0_RC_DL_REG_END                          0x00471424
+#define BCHP_PCIE_0_RC_PL_REG_START                        0x00471800
+#define BCHP_PCIE_0_RC_PL_REG_END                          0x00471e1c
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START                 0x00472000
+#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END                   0x0047203c
+#define BCHP_PCIE_0_EP_CFG_PM_REG_START                    0x00472048
+#define BCHP_PCIE_0_EP_CFG_PM_REG_END                      0x0047204c
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_START                   0x00472050
+#define BCHP_PCIE_0_EP_CFG_VPD_REG_END                     0x00472054
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_START                   0x00472058
+#define BCHP_PCIE_0_EP_CFG_MSI_REG_END                     0x00472064
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START                  0x004720a0
+#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END                    0x004720a8
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START                  0x004720ac
+#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END                    0x004720e4
+#define BCHP_PCIE_0_EP_CFG_AER_REG_START                   0x00472100
+#define BCHP_PCIE_0_EP_CFG_AER_REG_END                     0x00472134
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_START                   0x0047213c
+#define BCHP_PCIE_0_EP_CFG_DEV_REG_END                     0x00472144
+#define BCHP_PCIE_0_EP_CFG_PB_REG_START                    0x00472150
+#define BCHP_PCIE_0_EP_CFG_PB_REG_END                      0x0047215c
+#define BCHP_PCIE_0_EP_CFG_VC_REG_START                    0x00472160
+#define BCHP_PCIE_0_EP_CFG_VC_REG_END                      0x00472178
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START                0x00472180
+#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END                  0x004721a4
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START                 0x00472404
+#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END                   0x00472418
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START                 0x00472428
+#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END                   0x00472630
+#define BCHP_PCIE_0_EP_TL_REG_START                        0x00472800
+#define BCHP_PCIE_0_EP_TL_REG_END                          0x00472998
+#define BCHP_PCIE_0_EP_DL_REG_START                        0x00473000
+#define BCHP_PCIE_0_EP_DL_REG_END                          0x00473424
+#define BCHP_PCIE_0_EP_PL_REG_START                        0x00473800
+#define BCHP_PCIE_0_EP_PL_REG_END                          0x00473e1c
+#define BCHP_PCIE_0_MISC_REG_START                         0x00474000
+#define BCHP_PCIE_0_MISC_REG_END                           0x004740cc
+#define BCHP_PCIE_0_MISC_PERST_REG_START                   0x00474100
+#define BCHP_PCIE_0_MISC_PERST_REG_END                     0x00474104
+#define BCHP_PCIE_0_MISC_HARD_REG_START                    0x00474200
+#define BCHP_PCIE_0_MISC_HARD_REG_END                      0x00474204
+#define BCHP_PCIE_0_INTR2_REG_START                        0x00474300
+#define BCHP_PCIE_0_INTR2_REG_END                          0x0047432c
+#define BCHP_PCIE_0_DMA_REG_START                          0x00474400
+#define BCHP_PCIE_0_DMA_REG_END                            0x0047446c
+#define BCHP_PCIE_0_EXT_CFG_REG_START                      0x00478000
+#define BCHP_PCIE_0_EXT_CFG_REG_END                        0x00479008
+#define BCHP_PCIE_0_RGR1_REG_START                         0x00479200
+#define BCHP_PCIE_0_RGR1_REG_END                           0x00479210
+#define BCHP_PCIE_0_RG_REG_START                           0x00479300
+#define BCHP_PCIE_0_RG_REG_END                             0x0047930c
+#define BCHP_USB_CAPS_REG_START                            0x00490000
+#define BCHP_USB_CAPS_REG_END                              0x0049002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00490100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0049010c
+#define BCHP_USB_INTR2_REG_START                           0x00490180
+#define BCHP_USB_INTR2_REG_END                             0x004901ac
+#define BCHP_USB_CTRL_REG_START                            0x00490200
+#define BCHP_USB_CTRL_REG_END                              0x004902fc
+#define BCHP_USB_EHCI_REG_START                            0x00490300
+#define BCHP_USB_EHCI_REG_END                              0x004903a4
+#define BCHP_USB_OHCI_REG_START                            0x00490400
+#define BCHP_USB_OHCI_REG_END                              0x00490454
+#define BCHP_USB_EHCI1_REG_START                           0x00490500
+#define BCHP_USB_EHCI1_REG_END                             0x004905a4
+#define BCHP_USB_OHCI1_REG_START                           0x00490600
+#define BCHP_USB_OHCI1_REG_END                             0x00490654
+#define BCHP_AVS_CPU_PROG_MEM_REG_START                    0x004c0000
+#define BCHP_AVS_CPU_PROG_MEM_REG_END                      0x004c2ffc
+#define BCHP_AVS_CPU_DATA_MEM_REG_START                    0x004c4000
+#define BCHP_AVS_CPU_DATA_MEM_REG_END                      0x004c4bfc
+#define BCHP_AVS_CPU_CORE_REGS_REG_START                   0x004c8000
+#define BCHP_AVS_CPU_CORE_REGS_REG_END                     0x004c80fc
+#define BCHP_AVS_CPU_AUX_REGS_REG_START                    0x004ca000
+#define BCHP_AVS_CPU_AUX_REGS_REG_END                      0x004cb058
+#define BCHP_AVS_UART_REG_START                            0x004d0000
+#define BCHP_AVS_UART_REG_END                              0x004d0ffc
+#define BCHP_AVS_CPU_L2_REG_START                          0x004d1100
+#define BCHP_AVS_CPU_L2_REG_END                            0x004d112c
+#define BCHP_AVS_HOST_L2_REG_START                         0x004d1200
+#define BCHP_AVS_HOST_L2_REG_END                           0x004d1244
+#define BCHP_AVS_CPU_CTRL_REG_START                        0x004d1300
+#define BCHP_AVS_CPU_CTRL_REG_END                          0x004d1330
+#define BCHP_AVS_BSTI_REG_START                            0x004d1400
+#define BCHP_AVS_BSTI_REG_END                              0x004d1404
+#define BCHP_AVS_TMON_REG_START                            0x004d1500
+#define BCHP_AVS_TMON_REG_END                              0x004d1524
+#define BCHP_AVS_TOP_CTRL_REG_START                        0x004d1800
+#define BCHP_AVS_TOP_CTRL_REG_END                          0x004d18a8
+#define BCHP_AVS_HW_MNTR_REG_START                         0x004d2000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x004d20c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x004d2100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x004d2124
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x004d2200
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004d22e0
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x004d2800
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004d2804
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x004d2d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004d2dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x004d2e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004d2efc
+#define BCHP_AVS_WDOG_REG_START                            0x004d3000
+#define BCHP_AVS_WDOG_REG_END                              0x004d3ffc
+#define BCHP_AVS_PMB_S_000_REG_START                       0x004d4000
+#define BCHP_AVS_PMB_S_000_REG_END                         0x004d4024
+#define BCHP_AVS_PMB_S_001_REG_START                       0x004d4040
+#define BCHP_AVS_PMB_S_001_REG_END                         0x004d4064
+#define BCHP_AVS_PMB_S_002_REG_START                       0x004d4080
+#define BCHP_AVS_PMB_S_002_REG_END                         0x004d40a4
+#define BCHP_AVS_PMB_S_003_REG_START                       0x004d40c0
+#define BCHP_AVS_PMB_S_003_REG_END                         0x004d40e4
+#define BCHP_AVS_PMB_S_004_REG_START                       0x004d4100
+#define BCHP_AVS_PMB_S_004_REG_END                         0x004d4124
+#define BCHP_AVS_PMB_S_005_REG_START                       0x004d4140
+#define BCHP_AVS_PMB_S_005_REG_END                         0x004d4164
+#define BCHP_AVS_PMB_S_006_REG_START                       0x004d4180
+#define BCHP_AVS_PMB_S_006_REG_END                         0x004d41a4
+#define BCHP_AVS_PMB_S_007_REG_START                       0x004d41c0
+#define BCHP_AVS_PMB_S_007_REG_END                         0x004d41e4
+#define BCHP_AVS_PMB_S_008_REG_START                       0x004d4200
+#define BCHP_AVS_PMB_S_008_REG_END                         0x004d4224
+#define BCHP_AVS_PMB_S_009_REG_START                       0x004d4240
+#define BCHP_AVS_PMB_S_009_REG_END                         0x004d4264
+#define BCHP_AVS_PMB_S_010_REG_START                       0x004d4280
+#define BCHP_AVS_PMB_S_010_REG_END                         0x004d42a4
+#define BCHP_AVS_PMB_S_011_REG_START                       0x004d42c0
+#define BCHP_AVS_PMB_S_011_REG_END                         0x004d42e4
+#define BCHP_AVS_PMB_S_012_REG_START                       0x004d4300
+#define BCHP_AVS_PMB_S_012_REG_END                         0x004d4324
+#define BCHP_AVS_PMB_S_013_REG_START                       0x004d4340
+#define BCHP_AVS_PMB_S_013_REG_END                         0x004d4364
+#define BCHP_AVS_PMB_S_014_REG_START                       0x004d4380
+#define BCHP_AVS_PMB_S_014_REG_END                         0x004d43a4
+#define BCHP_AVS_PMB_S_015_REG_START                       0x004d43c0
+#define BCHP_AVS_PMB_S_015_REG_END                         0x004d43e4
+#define BCHP_AVS_PMB_REGISTERS_REG_START                   0x004d6000
+#define BCHP_AVS_PMB_REGISTERS_REG_END                     0x004d6008
+#define BCHP_CLKGEN_REG_START                              0x004e0000
+#define BCHP_CLKGEN_REG_END                                0x004e06b8
+#define BCHP_VCXO_0_RM_REG_START                           0x004e2800
+#define BCHP_VCXO_0_RM_REG_END                             0x004e2838
+#define BCHP_VCXO_1_RM_REG_START                           0x004e2880
+#define BCHP_VCXO_1_RM_REG_END                             0x004e28b8
+#define BCHP_CLKGEN_GR_REG_START                           0x004e3000
+#define BCHP_CLKGEN_GR_REG_END                             0x004e300c
+#define BCHP_CLKGEN_INTR2_REG_START                        0x004e4800
+#define BCHP_CLKGEN_INTR2_REG_END                          0x004e4844
+#define BCHP_AVS_RANGE_BLOCKER_REG_START                   0x004e5000
+#define BCHP_AVS_RANGE_BLOCKER_REG_END                     0x004e5058
+#define BCHP_PROD_OTP_GRB_REG_START                        0x004e6000
+#define BCHP_PROD_OTP_GRB_REG_END                          0x004e600c
+#define BCHP_JTAG_OTP_REG_START                            0x004e6100
+#define BCHP_JTAG_OTP_REG_END                              0x004e615c
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00600800
+#define BCHP_VFD_0_REG_END                                 0x006009fc
+#define BCHP_VFD_1_REG_START                               0x00600c00
+#define BCHP_VFD_1_REG_END                                 0x00600dfc
+#define BCHP_RDC_REG_START                                 0x00601000
+#define BCHP_RDC_REG_END                                   0x00601cfc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00602000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060202c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00602100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060212c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00602300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060232c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00602500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060252c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00602600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060262c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00602700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060272c
+#define BCHP_BVNF_INTR2_9_REG_START                        0x00602900
+#define BCHP_BVNF_INTR2_9_REG_END                          0x0060292c
+#define BCHP_BVNF_INTR2_15_REG_START                       0x00602f00
+#define BCHP_BVNF_INTR2_15_REG_END                         0x00602f2c
+#define BCHP_BVNF_INTR2_16_REG_START                       0x00603000
+#define BCHP_BVNF_INTR2_16_REG_END                         0x0060302c
+#define BCHP_BVNF_INTR2_18_REG_START                       0x00603200
+#define BCHP_BVNF_INTR2_18_REG_END                         0x0060322c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x0060401c
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_VNET_F_REG_START                              0x00620800
+#define BCHP_VNET_F_REG_END                                0x006209fc
+#define BCHP_VNET_B_REG_START                              0x00620a00
+#define BCHP_VNET_B_REG_END                                0x00620bfc
+#define BCHP_MMISC_REG_START                               0x00621000
+#define BCHP_MMISC_REG_END                                 0x0062101c
+#define BCHP_LBOX_0_REG_START                              0x00622000
+#define BCHP_LBOX_0_REG_END                                0x00622070
+#define BCHP_DNR_0_REG_START                               0x00622200
+#define BCHP_DNR_0_REG_END                                 0x006222a4
+#define BCHP_DNR_1_REG_START                               0x00622400
+#define BCHP_DNR_1_REG_END                                 0x006224a4
+#define BCHP_XSRC_0_REG_START                              0x00622800
+#define BCHP_XSRC_0_REG_END                                0x00622888
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00622c00
+#define BCHP_BVNM_INTR2_0_REG_END                          0x00622c2c
+#define BCHP_DMISC_REG_START                               0x00640000
+#define BCHP_DMISC_REG_END                                 0x0064001c
+#define BCHP_MVP_TOP_0_REG_START                           0x00650000
+#define BCHP_MVP_TOP_0_REG_END                             0x00650038
+#define BCHP_SIOB_0_REG_START                              0x00650200
+#define BCHP_SIOB_0_REG_END                                0x006502fc
+#define BCHP_HSCL_0_REG_START                              0x00650400
+#define BCHP_HSCL_0_REG_END                                0x006507fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00652000
+#define BCHP_MDI_TOP_0_REG_END                             0x006520fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00652800
+#define BCHP_MDI_PPB_0_REG_END                             0x00652bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00652c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00652ffc
+#define BCHP_CAP_0_REG_START                               0x00680000
+#define BCHP_CAP_0_REG_END                                 0x0068010c
+#define BCHP_CAP_1_REG_START                               0x00680200
+#define BCHP_CAP_1_REG_END                                 0x0068030c
+#define BCHP_GFD_0_REG_START                               0x00680400
+#define BCHP_GFD_0_REG_END                                 0x0068062c
+#define BCHP_GFD_1_REG_START                               0x00680800
+#define BCHP_GFD_1_REG_END                                 0x00680a2c
+#define BCHP_CMP_0_REG_START                               0x00681000
+#define BCHP_CMP_0_REG_END                                 0x006814c0
+#define BCHP_CMP_1_REG_START                               0x00681800
+#define BCHP_CMP_1_REG_END                                 0x00681a60
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00682000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006820a4
+#define BCHP_MASK_0_REG_START                              0x00682400
+#define BCHP_MASK_0_REG_END                                0x00682420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00684000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00685284
+#define BCHP_BVNB_INTR2_REG_START                          0x00686000
+#define BCHP_BVNB_INTR2_REG_END                            0x0068602c
+#define BCHP_BMISC_REG_START                               0x00686400
+#define BCHP_BMISC_REG_END                                 0x0068641c
+#define BCHP_MISC_REG_START                                0x006a0000
+#define BCHP_MISC_REG_END                                  0x006a00a4
+#define BCHP_IT_0_REG_START                                0x006a1000
+#define BCHP_IT_0_REG_END                                  0x006a17fc
+#define BCHP_IT_1_REG_START                                0x006a2000
+#define BCHP_IT_1_REG_END                                  0x006a27fc
+#define BCHP_VF_0_REG_START                                0x006a3000
+#define BCHP_VF_0_REG_END                                  0x006a3134
+#define BCHP_VF_1_REG_START                                0x006a3200
+#define BCHP_VF_1_REG_END                                  0x006a3334
+#define BCHP_SECAM_0_REG_START                             0x006a3400
+#define BCHP_SECAM_0_REG_END                               0x006a3414
+#define BCHP_SM_0_REG_START                                0x006a3480
+#define BCHP_SM_0_REG_END                                  0x006a34ac
+#define BCHP_SDSRC_0_REG_START                             0x006a3500
+#define BCHP_SDSRC_0_REG_END                               0x006a350c
+#define BCHP_HDSRC_0_REG_START                             0x006a3520
+#define BCHP_HDSRC_0_REG_END                               0x006a353c
+#define BCHP_CSC_0_REG_START                               0x006a3580
+#define BCHP_CSC_0_REG_END                                 0x006a35b0
+#define BCHP_CSC_1_REG_START                               0x006a3600
+#define BCHP_CSC_1_REG_END                                 0x006a3630
+#define BCHP_RM_0_REG_START                                0x006a3680
+#define BCHP_RM_0_REG_END                                  0x006a36b0
+#define BCHP_RM_1_REG_START                                0x006a36c0
+#define BCHP_RM_1_REG_END                                  0x006a36f0
+#define BCHP_ANA_DEBUG_0_REG_START                         0x006a3700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x006a3744
+#define BCHP_GRPD_0_REG_START                              0x006a3800
+#define BCHP_GRPD_0_REG_END                                0x006a38ec
+#define BCHP_DVI_MISC_0_REG_START                          0x006a3900
+#define BCHP_DVI_MISC_0_REG_END                            0x006a3900
+#define BCHP_DVI_DTG_0_REG_START                           0x006a4000
+#define BCHP_DVI_DTG_0_REG_END                             0x006a4488
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x006a4800
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x006a4830
+#define BCHP_DVI_CSC_0_REG_START                           0x006a4900
+#define BCHP_DVI_CSC_0_REG_END                             0x006a4930
+#define BCHP_DVI_FC_0_REG_START                            0x006a4a00
+#define BCHP_DVI_FC_0_REG_END                              0x006a4a04
+#define BCHP_DVI_DVF_0_REG_START                           0x006a4b00
+#define BCHP_DVI_DVF_0_REG_END                             0x006a4b18
+#define BCHP_DVI_DEBUG_0_REG_START                         0x006a4c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x006a4c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x006a5000
+#define BCHP_ITU656_DTG_0_REG_END                          0x006a5488
+#define BCHP_ITU656_CSC_0_REG_START                        0x006a5600
+#define BCHP_ITU656_CSC_0_REG_END                          0x006a5630
+#define BCHP_ITU656_DVF_0_REG_START                        0x006a5700
+#define BCHP_ITU656_DVF_0_REG_END                          0x006a5718
+#define BCHP_ITU656_0_REG_START                            0x006a5800
+#define BCHP_ITU656_0_REG_END                              0x006a5820
+#define BCHP_VEC_CFG_REG_START                             0x006a5c00
+#define BCHP_VEC_CFG_REG_END                               0x006a5d44
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x006a6000
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x006a602c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x006a6200
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x006a6320
+#define BCHP_VIDEO_ENC_STG_0_REG_START                     0x006a6400
+#define BCHP_VIDEO_ENC_STG_0_REG_END                       0x006a645c
+#define BCHP_DSCL_0_REG_START                              0x006a6800
+#define BCHP_DSCL_0_REG_END                                0x006a6bfc
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x006a7000
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x006a7008
+#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_START                 0x006a7100
+#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_END                   0x006a712c
+#define BCHP_DVP_TVG_0_REG_START                           0x006a7200
+#define BCHP_DVP_TVG_0_REG_END                             0x006a7288
+#define BCHP_VBI_ENC_REG_START                             0x006a8000
+#define BCHP_VBI_ENC_REG_END                               0x006a8074
+#define BCHP_CCE_0_REG_START                               0x006a8400
+#define BCHP_CCE_0_REG_END                                 0x006a8458
+#define BCHP_WSE_0_REG_START                               0x006a8500
+#define BCHP_WSE_0_REG_END                                 0x006a8514
+#define BCHP_CGMSAE_0_REG_START                            0x006a8600
+#define BCHP_CGMSAE_0_REG_END                              0x006a8658
+#define BCHP_TTE_0_REG_START                               0x006a8700
+#define BCHP_TTE_0_REG_END                                 0x006a8728
+#define BCHP_GSE_0_REG_START                               0x006a8800
+#define BCHP_GSE_0_REG_END                                 0x006a8880
+#define BCHP_AMOLE_0_REG_START                             0x006a8900
+#define BCHP_AMOLE_0_REG_END                               0x006a898c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x006a8a00
+#define BCHP_CCE_ANCIL_0_REG_END                           0x006a8a54
+#define BCHP_WSE_ANCIL_0_REG_START                         0x006a8b00
+#define BCHP_WSE_ANCIL_0_REG_END                           0x006a8b0c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x006a8c00
+#define BCHP_TTE_ANCIL_0_REG_END                           0x006a8c28
+#define BCHP_GSE_ANCIL_0_REG_START                         0x006a8d00
+#define BCHP_GSE_ANCIL_0_REG_END                           0x006a8d80
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x006a8e00
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x006a8e8c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x006a8f00
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x006a8f24
+#define BCHP_VICE2_VIP_0_0_REG_START                       0x006af000
+#define BCHP_VICE2_VIP_0_0_REG_END                         0x006af224
+#define BCHP_VICE2_VIP_TOP_REG_START                       0x006af800
+#define BCHP_VICE2_VIP_TOP_REG_END                         0x006af80c
+#define BCHP_DVP_HR_REG_START                              0x006b0000
+#define BCHP_DVP_HR_REG_END                                0x006b03fc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006b0400
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006b042c
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006b0600
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006b0614
+#define BCHP_HDMI_RX_FE_SHARED_REG_START                   0x006b0800
+#define BCHP_HDMI_RX_FE_SHARED_REG_END                     0x006b090c
+#define BCHP_HDMI_RX_SHARED_REG_START                      0x006b0c00
+#define BCHP_HDMI_RX_SHARED_REG_END                        0x006b0c28
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006b1000
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006b11fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006b1200
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006b13fc
+#define BCHP_HDMI_RX_0_REG_START                           0x006b2000
+#define BCHP_HDMI_RX_0_REG_END                             0x006b27fc
+#define BCHP_HDCP2_RX_0_REG_START                          0x006b2800
+#define BCHP_HDCP2_RX_0_REG_END                            0x006b29fc
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006b2a00
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006b2a2c
+#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_START               0x006b2a40
+#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_END                 0x006b2a6c
+#define BCHP_HDMI_RX_HAE_INTR2_0_REG_START                 0x006b2a80
+#define BCHP_HDMI_RX_HAE_INTR2_0_REG_END                   0x006b2aac
+#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_START                0x006b2ac0
+#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_END                  0x006b2ad4
+#define BCHP_HD_DVI_0_REG_START                            0x006b4000
+#define BCHP_HD_DVI_0_REG_END                              0x006b427c
+#define BCHP_DVP_HR_TMR_REG_START                          0x006b4cc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006b4cfc
+#define BCHP_DVP_HT_REG_START                              0x006b8000
+#define BCHP_DVP_HT_REG_END                                0x006b8114
+#define BCHP_HDMI_REG_START                                0x006b8800
+#define BCHP_HDMI_REG_END                                  0x006b8afc
+#define BCHP_HDMI_TX_AUTO_I2C_REG_START                    0x006b8b00
+#define BCHP_HDMI_TX_AUTO_I2C_REG_END                      0x006b8dfc
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006b8e00
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006b8e7c
+#define BCHP_HDMI_RM_REG_START                             0x006b8e80
+#define BCHP_HDMI_RM_REG_END                               0x006b8eb8
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006b8f00
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006b8f2c
+#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_START                0x006b8f80
+#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_END                  0x006b8fac
+#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_START                0x006b9000
+#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_END                  0x006b902c
+#define BCHP_HDMI_TX_HAE_INTR2_0_REG_START                 0x006b9080
+#define BCHP_HDMI_TX_HAE_INTR2_0_REG_END                   0x006b90ac
+#define BCHP_HDMI_RAM_REG_START                            0x006b9100
+#define BCHP_HDMI_RAM_REG_END                              0x006b92fc
+#define BCHP_BVN_RGR_REG_START                             0x006c0000
+#define BCHP_BVN_RGR_REG_END                               0x006c0010
+#define BCHP_MEMC_GEN_0_REG_START                          0x00900000
+#define BCHP_MEMC_GEN_0_REG_END                            0x009007fc
+#define BCHP_MEMC_EDIS_0_0_REG_START                       0x00900800
+#define BCHP_MEMC_EDIS_0_0_REG_END                         0x009008fc
+#define BCHP_MEMC_EDIS_0_1_REG_START                       0x00900a00
+#define BCHP_MEMC_EDIS_0_1_REG_END                         0x00900afc
+#define BCHP_MEMC_ARC_0_REG_START                          0x00900c00
+#define BCHP_MEMC_ARC_0_REG_END                            0x00900f74
+#define BCHP_MEMC_ARB_0_REG_START                          0x00901000
+#define BCHP_MEMC_ARB_0_REG_END                            0x009014cc
+#define BCHP_MEMC_DDR_0_REG_START                          0x00902000
+#define BCHP_MEMC_DDR_0_REG_END                            0x009027fc
+#define BCHP_MEMC_L2_0_0_REG_START                         0x00903000
+#define BCHP_MEMC_L2_0_0_REG_END                           0x00903044
+#define BCHP_MEMC_L2_0_1_REG_START                         0x00903200
+#define BCHP_MEMC_L2_0_1_REG_END                           0x00903244
+#define BCHP_MEMC_L2_0_2_REG_START                         0x00903400
+#define BCHP_MEMC_L2_0_2_REG_END                           0x00903444
+#define BCHP_MEMC_TRACELOG_0_0_REG_START                   0x00903800
+#define BCHP_MEMC_TRACELOG_0_0_REG_END                     0x009039fc
+#define BCHP_MEMC_RGRB_0_REG_START                         0x00904000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x00904010
+#define BCHP_MEMC_MISC_0_REG_START                         0x00905000
+#define BCHP_MEMC_MISC_0_REG_END                           0x00905010
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START            0x00906000
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END              0x00906218
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START             0x00906400
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END               0x00906518
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START             0x00906600
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END               0x00906718
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START                 0x00908000
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END                   0x009080e0
+#define BCHP_MEMC_SENTINEL_0_0_REG_START                   0x00940000
+#define BCHP_MEMC_SENTINEL_0_0_REG_END                     0x0097fffc
+#define BCHP_S_MEMC_0_REG_START                            0x00980000
+#define BCHP_S_MEMC_0_REG_END                              0x00980780
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00080
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a000fc
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001fc
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00218
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a02000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a02078
+#define BCHP_XPT_DPCR1_REG_START                           0x00a02080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a020f8
+#define BCHP_XPT_DPCR2_REG_START                           0x00a02100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a02178
+#define BCHP_XPT_DPCR3_REG_START                           0x00a02180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a021f8
+#define BCHP_XPT_DPCR4_REG_START                           0x00a02200
+#define BCHP_XPT_DPCR4_REG_END                             0x00a02278
+#define BCHP_XPT_DPCR5_REG_START                           0x00a02280
+#define BCHP_XPT_DPCR5_REG_END                             0x00a022f8
+#define BCHP_XPT_DPCR6_REG_START                           0x00a02300
+#define BCHP_XPT_DPCR6_REG_END                             0x00a02378
+#define BCHP_XPT_DPCR7_REG_START                           0x00a02380
+#define BCHP_XPT_DPCR7_REG_END                             0x00a023f8
+#define BCHP_XPT_DPCR8_REG_START                           0x00a02400
+#define BCHP_XPT_DPCR8_REG_END                             0x00a02478
+#define BCHP_XPT_DPCR9_REG_START                           0x00a02480
+#define BCHP_XPT_DPCR9_REG_END                             0x00a024f8
+#define BCHP_XPT_DPCR10_REG_START                          0x00a02500
+#define BCHP_XPT_DPCR10_REG_END                            0x00a02578
+#define BCHP_XPT_DPCR11_REG_START                          0x00a02580
+#define BCHP_XPT_DPCR11_REG_END                            0x00a025f8
+#define BCHP_XPT_DPCR12_REG_START                          0x00a02600
+#define BCHP_XPT_DPCR12_REG_END                            0x00a02678
+#define BCHP_XPT_DPCR13_REG_START                          0x00a02680
+#define BCHP_XPT_DPCR13_REG_END                            0x00a026f8
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a02800
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a02804
+#define BCHP_XPT_PSUB_REG_START                            0x00a02a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a02b88
+#define BCHP_XPT_MPOD_REG_START                            0x00a02c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a02c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a02d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a02d10
+#define BCHP_XPT_RMX1_REG_START                            0x00a02e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a02e10
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a04000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a054fc
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a06000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a07e9c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a08000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0aafc
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START           0x00a0c000
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END             0x00a0ea04
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START            0x00a0f000
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END              0x00a0f9fc
+#define BCHP_XPT_TSIO_INTR_L2_REG_START                    0x00a0fc00
+#define BCHP_XPT_TSIO_INTR_L2_REG_END                      0x00a0fc2c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a14050
+#define BCHP_XPT_FE_REG_START                              0x00a20000
+#define BCHP_XPT_FE_REG_END                                0x00a25ffc
+#define BCHP_XPT_MSG_REG_START                             0x00a30000
+#define BCHP_XPT_MSG_REG_END                               0x00a3ca14
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb1c
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb20
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END  0x00a3fb3c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb5c
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb60
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END  0x00a3fb7c
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START             0x00a3fb80
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END               0x00a3fbac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START   0x00a3fc00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END     0x00a3fc2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START   0x00a3fc40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END     0x00a3fc6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START   0x00a3fc80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END     0x00a3fcac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START  0x00a3fcc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END    0x00a3fcec
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x00a3fd00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END   0x00a3fd2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x00a3fd40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END   0x00a3fd6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x00a3fd80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END   0x00a3fdac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x00a3fdc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END   0x00a3fdec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START      0x00a3fe00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END        0x00a3fe2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START      0x00a3fe40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END        0x00a3fe6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START      0x00a3fe80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END        0x00a3feac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START     0x00a3fec0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END       0x00a3feec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START    0x00a3ff00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END      0x00a3ff2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START    0x00a3ff40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END      0x00a3ff6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START    0x00a3ff80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END      0x00a3ffac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START    0x00a3ffc0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END      0x00a3ffec
+#define BCHP_XPT_RAVE_REG_START                            0x00a40000
+#define BCHP_XPT_RAVE_REG_END                              0x00a4e178
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START        0x00a4f000
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END          0x00a4f01c
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START        0x00a4f020
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END          0x00a4f03c
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START               0x00a4f040
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END                 0x00a4f06c
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START  0x00a4f080
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END    0x00a4f0ac
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START  0x00a4f0c0
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END    0x00a4f0ec
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f100
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END   0x00a4f12c
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f140
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END   0x00a4f16c
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START  0x00a4f180
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END    0x00a4f1ac
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START  0x00a4f1c0
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END    0x00a4f1ec
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START   0x00a4f200
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END     0x00a4f22c
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START   0x00a4f240
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END     0x00a4f26c
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f280
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f2ac
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f2c0
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f2ec
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f300
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f32c
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f340
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f36c
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START     0x00a4f380
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END       0x00a4f3ac
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START     0x00a4f3c0
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END       0x00a4f3ec
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START   0x00a4f400
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END     0x00a4f42c
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START   0x00a4f440
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END     0x00a4f46c
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f480
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f4ac
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f4c0
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f4ec
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f500
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f52c
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f540
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f56c
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f580
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f5ac
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f5c0
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f5ec
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f600
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f62c
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f640
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f66c
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f680
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f6ac
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f6c0
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f6ec
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f700
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f72c
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f740
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f76c
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x00a4f780
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x00a4f7ac
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x00a4f7c0
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x00a4f7ec
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x00a4f800
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x00a4f82c
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x00a4f840
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x00a4f86c
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START       0x00a4ff80
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END         0x00a4ffac
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START      0x00a4ffc0
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END        0x00a4ffec
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END   0x00a6001c
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END   0x00a6003c
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START   0x00a60040
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END     0x00a6006c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START    0x00a600c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END      0x00a600ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START    0x00a60140
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END      0x00a6016c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
+#define BCHP_XPT_MEMDMA_MCPB_REG_START                     0x00a60800
+#define BCHP_XPT_MEMDMA_MCPB_REG_END                       0x00a60b98
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START                 0x00a60c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END                   0x00a60d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START                 0x00a60e00
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END                   0x00a60f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START                 0x00a61000
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END                   0x00a6115c
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START                 0x00a61200
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END                   0x00a6135c
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START                 0x00a61400
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END                   0x00a6155c
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START                 0x00a61600
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END                   0x00a6175c
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START                 0x00a61800
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END                   0x00a6195c
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START                 0x00a61a00
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END                   0x00a61b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START                 0x00a61c00
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END                   0x00a61d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START                 0x00a61e00
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END                   0x00a61f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START                0x00a62000
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END                  0x00a6215c
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START                0x00a62200
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END                  0x00a6235c
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START                0x00a62400
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END                  0x00a6255c
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START                0x00a62600
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END                  0x00a6275c
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START                0x00a62800
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END                  0x00a6295c
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START                0x00a62a00
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END                  0x00a62b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START                0x00a62c00
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END                  0x00a62d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START                0x00a62e00
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END                  0x00a62f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START                0x00a63000
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END                  0x00a6315c
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START                0x00a63200
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END                  0x00a6335c
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START                0x00a63400
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END                  0x00a6355c
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START                0x00a63600
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END                  0x00a6375c
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START                0x00a63800
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END                  0x00a6395c
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START                0x00a63a00
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END                  0x00a63b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START                0x00a63c00
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END                  0x00a63d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START                0x00a63e00
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END                  0x00a63f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START                0x00a64000
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END                  0x00a6415c
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START                0x00a64200
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END                  0x00a6435c
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START                0x00a64400
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END                  0x00a6455c
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START                0x00a64600
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END                  0x00a6475c
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START                0x00a64800
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END                  0x00a6495c
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START                0x00a64a00
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END                  0x00a64b5c
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START        0x00a68000
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END          0x00a6801c
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START        0x00a68020
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END          0x00a6803c
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START       0x00a68040
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END         0x00a6805c
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START                0x00a68100
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END                  0x00a68144
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START           0x00a68200
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END             0x00a68244
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START          0x00a68300
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END            0x00a68344
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START                 0x00a68400
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END                   0x00a68444
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_START                 0x00a68500
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_END                   0x00a68510
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_START                 0x00a68600
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_END                   0x00a68658
+#define BCHP_XPT_WDMA_REGS_REG_START                       0x00a69000
+#define BCHP_XPT_WDMA_REGS_REG_END                         0x00a69068
+#define BCHP_XPT_WDMA_CH0_REG_START                        0x00a6a000
+#define BCHP_XPT_WDMA_CH0_REG_END                          0x00a6a0fc
+#define BCHP_XPT_WDMA_CH1_REG_START                        0x00a6a100
+#define BCHP_XPT_WDMA_CH1_REG_END                          0x00a6a1fc
+#define BCHP_XPT_WDMA_CH2_REG_START                        0x00a6a200
+#define BCHP_XPT_WDMA_CH2_REG_END                          0x00a6a2fc
+#define BCHP_XPT_WDMA_CH3_REG_START                        0x00a6a300
+#define BCHP_XPT_WDMA_CH3_REG_END                          0x00a6a3fc
+#define BCHP_XPT_WDMA_CH4_REG_START                        0x00a6a400
+#define BCHP_XPT_WDMA_CH4_REG_END                          0x00a6a4fc
+#define BCHP_XPT_WDMA_CH5_REG_START                        0x00a6a500
+#define BCHP_XPT_WDMA_CH5_REG_END                          0x00a6a5fc
+#define BCHP_XPT_WDMA_CH6_REG_START                        0x00a6a600
+#define BCHP_XPT_WDMA_CH6_REG_END                          0x00a6a6fc
+#define BCHP_XPT_WDMA_CH7_REG_START                        0x00a6a700
+#define BCHP_XPT_WDMA_CH7_REG_END                          0x00a6a7fc
+#define BCHP_XPT_WDMA_CH8_REG_START                        0x00a6a800
+#define BCHP_XPT_WDMA_CH8_REG_END                          0x00a6a8fc
+#define BCHP_XPT_WDMA_CH9_REG_START                        0x00a6a900
+#define BCHP_XPT_WDMA_CH9_REG_END                          0x00a6a9fc
+#define BCHP_XPT_WDMA_CH10_REG_START                       0x00a6aa00
+#define BCHP_XPT_WDMA_CH10_REG_END                         0x00a6aafc
+#define BCHP_XPT_WDMA_CH11_REG_START                       0x00a6ab00
+#define BCHP_XPT_WDMA_CH11_REG_END                         0x00a6abfc
+#define BCHP_XPT_WDMA_CH12_REG_START                       0x00a6ac00
+#define BCHP_XPT_WDMA_CH12_REG_END                         0x00a6acfc
+#define BCHP_XPT_WDMA_CH13_REG_START                       0x00a6ad00
+#define BCHP_XPT_WDMA_CH13_REG_END                         0x00a6adfc
+#define BCHP_XPT_WDMA_CH14_REG_START                       0x00a6ae00
+#define BCHP_XPT_WDMA_CH14_REG_END                         0x00a6aefc
+#define BCHP_XPT_WDMA_CH15_REG_START                       0x00a6af00
+#define BCHP_XPT_WDMA_CH15_REG_END                         0x00a6affc
+#define BCHP_XPT_WDMA_CH16_REG_START                       0x00a6b000
+#define BCHP_XPT_WDMA_CH16_REG_END                         0x00a6b0fc
+#define BCHP_XPT_WDMA_CH17_REG_START                       0x00a6b100
+#define BCHP_XPT_WDMA_CH17_REG_END                         0x00a6b1fc
+#define BCHP_XPT_WDMA_CH18_REG_START                       0x00a6b200
+#define BCHP_XPT_WDMA_CH18_REG_END                         0x00a6b2fc
+#define BCHP_XPT_WDMA_CH19_REG_START                       0x00a6b300
+#define BCHP_XPT_WDMA_CH19_REG_END                         0x00a6b3fc
+#define BCHP_XPT_WDMA_CH20_REG_START                       0x00a6b400
+#define BCHP_XPT_WDMA_CH20_REG_END                         0x00a6b4fc
+#define BCHP_XPT_WDMA_CH21_REG_START                       0x00a6b500
+#define BCHP_XPT_WDMA_CH21_REG_END                         0x00a6b5fc
+#define BCHP_XPT_WDMA_CH22_REG_START                       0x00a6b600
+#define BCHP_XPT_WDMA_CH22_REG_END                         0x00a6b6fc
+#define BCHP_XPT_WDMA_CH23_REG_START                       0x00a6b700
+#define BCHP_XPT_WDMA_CH23_REG_END                         0x00a6b7fc
+#define BCHP_XPT_WDMA_CH24_REG_START                       0x00a6b800
+#define BCHP_XPT_WDMA_CH24_REG_END                         0x00a6b8fc
+#define BCHP_XPT_WDMA_CH25_REG_START                       0x00a6b900
+#define BCHP_XPT_WDMA_CH25_REG_END                         0x00a6b9fc
+#define BCHP_XPT_WDMA_CH26_REG_START                       0x00a6ba00
+#define BCHP_XPT_WDMA_CH26_REG_END                         0x00a6bafc
+#define BCHP_XPT_WDMA_CH27_REG_START                       0x00a6bb00
+#define BCHP_XPT_WDMA_CH27_REG_END                         0x00a6bbfc
+#define BCHP_XPT_WDMA_CH28_REG_START                       0x00a6bc00
+#define BCHP_XPT_WDMA_CH28_REG_END                         0x00a6bcfc
+#define BCHP_XPT_WDMA_CH29_REG_START                       0x00a6bd00
+#define BCHP_XPT_WDMA_CH29_REG_END                         0x00a6bdfc
+#define BCHP_XPT_WDMA_CH30_REG_START                       0x00a6be00
+#define BCHP_XPT_WDMA_CH30_REG_END                         0x00a6befc
+#define BCHP_XPT_WDMA_CH31_REG_START                       0x00a6bf00
+#define BCHP_XPT_WDMA_CH31_REG_END                         0x00a6bffc
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_START                   0x00a6ff00
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_END                     0x00a6fffc
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START        0x00a70000
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END          0x00a7001c
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START        0x00a70020
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END          0x00a7003c
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START          0x00a70040
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END            0x00a7006c
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START    0x00a70080
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END      0x00a700ac
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START           0x00a700c0
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END             0x00a700ec
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END   0x00a7012c
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START           0x00a70140
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END             0x00a7016c
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START   0x00a70180
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END     0x00a701ac
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a701ec
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START  0x00a702c0
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END    0x00a702ec
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
+#define BCHP_XPT_MCPB_REG_START                            0x00a70800
+#define BCHP_XPT_MCPB_REG_END                              0x00a70b98
+#define BCHP_XPT_MCPB_CH0_REG_START                        0x00a70c00
+#define BCHP_XPT_MCPB_CH0_REG_END                          0x00a70d5c
+#define BCHP_XPT_MCPB_CH1_REG_START                        0x00a70e00
+#define BCHP_XPT_MCPB_CH1_REG_END                          0x00a70f5c
+#define BCHP_XPT_MCPB_CH2_REG_START                        0x00a71000
+#define BCHP_XPT_MCPB_CH2_REG_END                          0x00a7115c
+#define BCHP_XPT_MCPB_CH3_REG_START                        0x00a71200
+#define BCHP_XPT_MCPB_CH3_REG_END                          0x00a7135c
+#define BCHP_XPT_MCPB_CH4_REG_START                        0x00a71400
+#define BCHP_XPT_MCPB_CH4_REG_END                          0x00a7155c
+#define BCHP_XPT_MCPB_CH5_REG_START                        0x00a71600
+#define BCHP_XPT_MCPB_CH5_REG_END                          0x00a7175c
+#define BCHP_XPT_MCPB_CH6_REG_START                        0x00a71800
+#define BCHP_XPT_MCPB_CH6_REG_END                          0x00a7195c
+#define BCHP_XPT_MCPB_CH7_REG_START                        0x00a71a00
+#define BCHP_XPT_MCPB_CH7_REG_END                          0x00a71b5c
+#define BCHP_XPT_MCPB_CH8_REG_START                        0x00a71c00
+#define BCHP_XPT_MCPB_CH8_REG_END                          0x00a71d5c
+#define BCHP_XPT_MCPB_CH9_REG_START                        0x00a71e00
+#define BCHP_XPT_MCPB_CH9_REG_END                          0x00a71f5c
+#define BCHP_XPT_MCPB_CH10_REG_START                       0x00a72000
+#define BCHP_XPT_MCPB_CH10_REG_END                         0x00a7215c
+#define BCHP_XPT_MCPB_CH11_REG_START                       0x00a72200
+#define BCHP_XPT_MCPB_CH11_REG_END                         0x00a7235c
+#define BCHP_XPT_MCPB_CH12_REG_START                       0x00a72400
+#define BCHP_XPT_MCPB_CH12_REG_END                         0x00a7255c
+#define BCHP_XPT_MCPB_CH13_REG_START                       0x00a72600
+#define BCHP_XPT_MCPB_CH13_REG_END                         0x00a7275c
+#define BCHP_XPT_MCPB_CH14_REG_START                       0x00a72800
+#define BCHP_XPT_MCPB_CH14_REG_END                         0x00a7295c
+#define BCHP_XPT_MCPB_CH15_REG_START                       0x00a72a00
+#define BCHP_XPT_MCPB_CH15_REG_END                         0x00a72b5c
+#define BCHP_XPT_MCPB_CH16_REG_START                       0x00a72c00
+#define BCHP_XPT_MCPB_CH16_REG_END                         0x00a72d5c
+#define BCHP_XPT_MCPB_CH17_REG_START                       0x00a72e00
+#define BCHP_XPT_MCPB_CH17_REG_END                         0x00a72f5c
+#define BCHP_XPT_MCPB_CH18_REG_START                       0x00a73000
+#define BCHP_XPT_MCPB_CH18_REG_END                         0x00a7315c
+#define BCHP_XPT_MCPB_CH19_REG_START                       0x00a73200
+#define BCHP_XPT_MCPB_CH19_REG_END                         0x00a7335c
+#define BCHP_XPT_MCPB_CH20_REG_START                       0x00a73400
+#define BCHP_XPT_MCPB_CH20_REG_END                         0x00a7355c
+#define BCHP_XPT_MCPB_CH21_REG_START                       0x00a73600
+#define BCHP_XPT_MCPB_CH21_REG_END                         0x00a7375c
+#define BCHP_XPT_MCPB_CH22_REG_START                       0x00a73800
+#define BCHP_XPT_MCPB_CH22_REG_END                         0x00a7395c
+#define BCHP_XPT_MCPB_CH23_REG_START                       0x00a73a00
+#define BCHP_XPT_MCPB_CH23_REG_END                         0x00a73b5c
+#define BCHP_XPT_MCPB_CH24_REG_START                       0x00a73c00
+#define BCHP_XPT_MCPB_CH24_REG_END                         0x00a73d5c
+#define BCHP_XPT_MCPB_CH25_REG_START                       0x00a73e00
+#define BCHP_XPT_MCPB_CH25_REG_END                         0x00a73f5c
+#define BCHP_XPT_MCPB_CH26_REG_START                       0x00a74000
+#define BCHP_XPT_MCPB_CH26_REG_END                         0x00a7415c
+#define BCHP_XPT_MCPB_CH27_REG_START                       0x00a74200
+#define BCHP_XPT_MCPB_CH27_REG_END                         0x00a7435c
+#define BCHP_XPT_MCPB_CH28_REG_START                       0x00a74400
+#define BCHP_XPT_MCPB_CH28_REG_END                         0x00a7455c
+#define BCHP_XPT_MCPB_CH29_REG_START                       0x00a74600
+#define BCHP_XPT_MCPB_CH29_REG_END                         0x00a7475c
+#define BCHP_XPT_MCPB_CH30_REG_START                       0x00a74800
+#define BCHP_XPT_MCPB_CH30_REG_END                         0x00a7495c
+#define BCHP_XPT_MCPB_CH31_REG_START                       0x00a74a00
+#define BCHP_XPT_MCPB_CH31_REG_END                         0x00a74b5c
+#define BCHP_XPT_XPU_REG_START                             0x00a78000
+#define BCHP_XPT_XPU_REG_END                               0x00a7c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a7f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a7f000
+#define BCHP_GENET_0_SYS_REG_START                         0x00b60000
+#define BCHP_GENET_0_SYS_REG_END                           0x00b60010
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00b60040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x00b6004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00b60080
+#define BCHP_GENET_0_EXT_REG_END                           0x00b600b4
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00b60200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x00b6022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00b60240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x00b6026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00b60300
+#define BCHP_GENET_0_RBUF_REG_END                          0x00b603b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00b60600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00b60628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00b60800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00b60ed8
+#define BCHP_GENET_0_RDMA_REG_START                        0x00b62000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00b630d4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00b64000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00b65084
+#define BCHP_GENET_0_HFB_REG_START                         0x00b68000
+#define BCHP_GENET_0_HFB_REG_END                           0x00b6fc48
+#define BCHP_SID_REG_START                                 0x00bc0100
+#define BCHP_SID_REG_END                                   0x00bc019c
+#define BCHP_SID_RLE_REG_START                             0x00bc0300
+#define BCHP_SID_RLE_REG_END                               0x00bc039c
+#define BCHP_SID_DQ_REG_START                              0x00bc0400
+#define BCHP_SID_DQ_REG_END                                0x00bc04bc
+#define BCHP_SID_STRM_REG_START                            0x00bc0800
+#define BCHP_SID_STRM_REG_END                              0x00bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00bc0c40
+#define BCHP_SID_ARC_REG_START                             0x00bc0f00
+#define BCHP_SID_ARC_REG_END                               0x00bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x00bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x00bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x00bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x00bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x00bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x00bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00bd5014
+#define BCHP_SID_GR_REG_START                              0x00be0000
+#define BCHP_SID_GR_REG_END                                0x00be000c
+#define BCHP_SID_L2_REG_START                              0x00be0100
+#define BCHP_SID_L2_REG_END                                0x00be012c
+#define BCHP_SICH_REG_START                                0x00be2000
+#define BCHP_SICH_REG_END                                  0x00be203c
+#define BCHP_M2MC_REG_START                                0x00be4000
+#define BCHP_M2MC_REG_END                                  0x00be47fc
+#define BCHP_M2MC_L2_REG_START                             0x00be5000
+#define BCHP_M2MC_L2_REG_END                               0x00be502c
+#define BCHP_M2MC_GR_REG_START                             0x00be5800
+#define BCHP_M2MC_GR_REG_END                               0x00be580c
+#define BCHP_V3D_CTL_REG_START                             0x00bea000
+#define BCHP_V3D_CTL_REG_END                               0x00bea07c
+#define BCHP_V3D_CLE_REG_START                             0x00bea100
+#define BCHP_V3D_CLE_REG_END                               0x00bea1ac
+#define BCHP_V3D_PTB_REG_START                             0x00bea300
+#define BCHP_V3D_PTB_REG_END                               0x00bea310
+#define BCHP_V3D_QPS_REG_START                             0x00bea400
+#define BCHP_V3D_QPS_REG_END                               0x00bea43c
+#define BCHP_V3D_VPM_REG_START                             0x00bea500
+#define BCHP_V3D_VPM_REG_END                               0x00bea504
+#define BCHP_V3D_PCTR_REG_START                            0x00bea600
+#define BCHP_V3D_PCTR_REG_END                              0x00bea6fc
+#define BCHP_V3D_AXM_REG_START                             0x00bea700
+#define BCHP_V3D_AXM_REG_END                               0x00bea714
+#define BCHP_V3D_GMP_REG_START                             0x00bea800
+#define BCHP_V3D_GMP_REG_END                               0x00bea820
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_START                   0x00bea900
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_END                     0x00bea90c
+#define BCHP_V3D_GCA_REG_START                             0x00beaa00
+#define BCHP_V3D_GCA_REG_END                               0x00beaa78
+#define BCHP_V3D_ERROR_REG_START                           0x00beaf00
+#define BCHP_V3D_ERROR_REG_END                             0x00beaf20
+#define BCHP_V3D_QPUDBG_REG_START                          0x00bec000
+#define BCHP_V3D_QPUDBG_REG_END                            0x00bedffc
+#define BCHP_V3D_HUB_CTL_REG_START                         0x00bee000
+#define BCHP_V3D_HUB_CTL_REG_END                           0x00bee07c
+#define BCHP_V3D_MSO_REG_START                             0x00bee100
+#define BCHP_V3D_MSO_REG_END                               0x00bee27c
+#define BCHP_V3D_TSY_REG_START                             0x00bee300
+#define BCHP_V3D_TSY_REG_END                               0x00bee368
+#define BCHP_V3D_TFU_REG_START                             0x00bee400
+#define BCHP_V3D_TFU_REG_END                               0x00bee464
+#define BCHP_V3D_MCS_REG_START                             0x00bee500
+#define BCHP_V3D_MCS_REG_END                               0x00bee55c
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00bf0000
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00c00000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00c00008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00c20000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x00c2044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00c21000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00c21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00c21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x00c2108c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00c21100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00c21154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00c21400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00c21678
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00c22000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00c22014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00c22200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x00c2222c
+#define BCHP_RAAGA_DSP_TIMER_INT_REG_START                 0x00c22400
+#define BCHP_RAAGA_DSP_TIMER_INT_REG_END                   0x00c22414
+#define BCHP_RAAGA_DSP_ERROR_INT_REG_START                 0x00c22600
+#define BCHP_RAAGA_DSP_ERROR_INT_REG_END                   0x00c22614
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00c22800
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x00c2282c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00c23000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x00c2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00c30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x00c3bffc
+#define BCHP_RAAGA_AX_MISC_REG_START                       0x00c40000
+#define BCHP_RAAGA_AX_MISC_REG_END                         0x00c40004
+#define BCHP_RAAGA_AX_INTR_AGGR_REG_START                  0x00c40100
+#define BCHP_RAAGA_AX_INTR_AGGR_REG_END                    0x00c40144
+#define BCHP_RAAGA_AX_RXI_ARB_REG_START                    0x00c40200
+#define BCHP_RAAGA_AX_RXI_ARB_REG_END                      0x00c40248
+#define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_START              0x00c40300
+#define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_END                0x00c40314
+#define BCHP_RAAGA_AX_EC_WATCHDOG_REG_START                0x00c40400
+#define BCHP_RAAGA_AX_EC_WATCHDOG_REG_END                  0x00c40414
+#define BCHP_RAAGA_AX_ME_WATCHDOG_REG_START                0x00c40500
+#define BCHP_RAAGA_AX_ME_WATCHDOG_REG_END                  0x00c40514
+#define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_START             0x00c40600
+#define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_END               0x00c40614
+#define BCHP_RAAGA_AX_DBLK_REG_START                       0x00c41000
+#define BCHP_RAAGA_AX_DBLK_REG_END                         0x00c411fc
+#define BCHP_RAAGA_AX_EC_REG_START                         0x00c42000
+#define BCHP_RAAGA_AX_EC_REG_END                           0x00c42158
+#define BCHP_RAAGA_AX_ME_REG_START                         0x00c43000
+#define BCHP_RAAGA_AX_ME_REG_END                           0x00c4321c
+#define BCHP_RAAGA_AX_GENAX_REG_START                      0x00c44000
+#define BCHP_RAAGA_AX_GENAX_REG_END                        0x00c44650
+#define BCHP_AUD_MISC_REG_START                            0x00c80000
+#define BCHP_AUD_MISC_REG_END                              0x00c80120
+#define BCHP_AUD_INTH_REG_START                            0x00c80800
+#define BCHP_AUD_INTH_REG_END                              0x00c8082c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x00ca0000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x00ca0d3c
+#define BCHP_AUD_FMM_BF_ESR_REG_START                      0x00ca1000
+#define BCHP_AUD_FMM_BF_ESR_REG_END                        0x00ca1074
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x00ca2000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x00ca2bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x00ca3000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x00ca3014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x00ca4000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x00ca612c
+#define BCHP_AUD_FMM_DP_ESR0_REG_START                     0x00ca7c00
+#define BCHP_AUD_FMM_DP_ESR0_REG_END                       0x00ca7c2c
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START        0x00cb0000
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END          0x00cb0084
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START             0x00cb0100
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END               0x00cb0184
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START               0x00cb0200
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END                 0x00cb02b4
+#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_START               0x00cb0300
+#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_END                 0x00cb03b4
+#define BCHP_HIFIDAC_CTRL_0_REG_START                      0x00cb0800
+#define BCHP_HIFIDAC_CTRL_0_REG_END                        0x00cb09fc
+#define BCHP_HIFIDAC_RM_0_REG_START                        0x00cb0a00
+#define BCHP_HIFIDAC_RM_0_REG_END                          0x00cb0a30
+#define BCHP_HIFIDAC_ESR_0_REG_START                       0x00cb0b00
+#define BCHP_HIFIDAC_ESR_0_REG_END                         0x00cb0b14
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START          0x00cb0c00
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END            0x00cb0c98
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_START                   0x00cb0d00
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_END                     0x00cb0d88
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_START                   0x00cb0e00
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_END                     0x00cb0e88
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_START                   0x00cb0f00
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_END                     0x00cb0f30
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_START                   0x00cb1000
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_END                     0x00cb1030
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_START                   0x00cb1100
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_END                     0x00cb1130
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_START                   0x00cb1200
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_END                     0x00cb1230
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_START                   0x00cb1300
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_END                     0x00cb1330
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START              0x00cb1400
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END                0x00cb1524
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START             0x00cb1600
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END               0x00cb165c
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START              0x00cb1800
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END                0x00cb18fc
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START               0x00cb2000
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END                 0x00cb20ac
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START         0x00cb2800
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END           0x00cb2864
+#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START                  0x00cb2900
+#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END                    0x00cb2964
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START       0x00cb4000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END         0x00cb41fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START       0x00cb4400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END         0x00cb4414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START           0x00cb6000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END             0x00cb7bfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START            0x00cb7d00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END              0x00cb7d14
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_START       0x00cb8000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_END         0x00cb81fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_START       0x00cb8400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_END         0x00cb8414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_START           0x00cba000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_END             0x00cbbbfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_START            0x00cbbd00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_END              0x00cbbd14
+#define BCHP_AUD_FMM_IOP_MISC_REG_START                    0x00cbc100
+#define BCHP_AUD_FMM_IOP_MISC_REG_END                      0x00cbc154
+#define BCHP_MPM_CPU_PROG_MEM_REG_START                    0x00d00000
+#define BCHP_MPM_CPU_PROG_MEM_REG_END                      0x00d0fffc
+#define BCHP_MPM_CPU_DATA_MEM_REG_START                    0x00d10000
+#define BCHP_MPM_CPU_DATA_MEM_REG_END                      0x00d13ffc
+#define BCHP_MPM_CPU_CORE_REGS_REG_START                   0x00d20000
+#define BCHP_MPM_CPU_CORE_REGS_REG_END                     0x00d200fc
+#define BCHP_MPM_CPU_AUX_REGS_REG_START                    0x00d22000
+#define BCHP_MPM_CPU_AUX_REGS_REG_END                      0x00d23058
+#define BCHP_MPM_UART_REG_START                            0x00d80000
+#define BCHP_MPM_UART_REG_END                              0x00d80ffc
+#define BCHP_MPM_WDOG_REG_START                            0x00d81000
+#define BCHP_MPM_WDOG_REG_END                              0x00d81ffc
+#define BCHP_MPM_CPU_L1_REG_START                          0x00d82000
+#define BCHP_MPM_CPU_L1_REG_END                            0x00d82018
+#define BCHP_MPM_CPU_L2_REG_START                          0x00d82100
+#define BCHP_MPM_CPU_L2_REG_END                            0x00d8212c
+#define BCHP_MPM_HOST_L2_REG_START                         0x00d82200
+#define BCHP_MPM_HOST_L2_REG_END                           0x00d8222c
+#define BCHP_MPM_CPU_CTRL_REG_START                        0x00d82300
+#define BCHP_MPM_CPU_CTRL_REG_END                          0x00d82344
+#define BCHP_MPM_PM_L2_REG_START                           0x00d82400
+#define BCHP_MPM_PM_L2_REG_END                             0x00d8242c
+#define BCHP_MPM_RANGE_BLOCKER_REG_START                   0x00d82500
+#define BCHP_MPM_RANGE_BLOCKER_REG_END                     0x00d82554
+#define BCHP_MPM_BSPI_REG_START                            0x00d82600
+#define BCHP_MPM_BSPI_REG_END                              0x00d8264c
+#define BCHP_MPM_MSPI_REG_START                            0x00d82800
+#define BCHP_MPM_MSPI_REG_END                              0x00d82984
+#define BCHP_DVP_MT_AON_TOP_REG_START                      0x00d83000
+#define BCHP_DVP_MT_AON_TOP_REG_END                        0x00d8300c
+#define BCHP_CBUS_INTR2_0_REG_START                        0x00d83800
+#define BCHP_CBUS_INTR2_0_REG_END                          0x00d8382c
+#define BCHP_CBUS_INTR2_1_REG_START                        0x00d83880
+#define BCHP_CBUS_INTR2_1_REG_END                          0x00d838ac
+#define BCHP_MT_CBUS_REG_START                             0x00d83a00
+#define BCHP_MT_CBUS_REG_END                               0x00d83afc
+#define BCHP_MT_MSC_REQ_REG_START                          0x00d83b00
+#define BCHP_MT_MSC_REQ_REG_END                            0x00d83b6c
+#define BCHP_MT_MSC_RESP_REG_START                         0x00d83c00
+#define BCHP_MT_MSC_RESP_REG_END                           0x00d83cac
+#define BCHP_MT_DDC_REQ_REG_START                          0x00d83d00
+#define BCHP_MT_DDC_REQ_REG_END                            0x00d83d6c
+#define BCHP_MPM_FLASH_MEM_REG_START                       0x00dc0000
+#define BCHP_MPM_FLASH_MEM_REG_END                         0x00ddfffc
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_START              0x01270200
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_END                0x01270204
+#define BCHP_DEMOD_XPT_WAKEUP_REG_START                    0x01271000
+#define BCHP_DEMOD_XPT_WAKEUP_REG_END                      0x01271fbc
+#define BCHP_DEMOD_XPT_FE_REG_START                        0x01272000
+#define BCHP_DEMOD_XPT_FE_REG_END                          0x012733fc
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD_8B
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD_8B
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD_DCXG_NO_4K
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_DCXG_NO_4K :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DCXG_NO_4K_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_GFD_DCXG_NO_4K_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD_HSCL_ONLY
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_HSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *PCIE_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - PCIE DMA Descriptor Word 0
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK               0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT              0
+
+/***************************************************************************
+ *DESC_WORD1 - PCIE DMA Descriptor Word 1
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD2 - PCIE DMA Descriptor Word 2
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK              0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT             0
+
+/***************************************************************************
+ *DESC_WORD3 - PCIE DMA Descriptor Word 3
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK             0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT            31
+
+/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK                    0x7e000000
+#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT                   25
+
+/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK            0x01ffffff
+#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT           0
+
+/***************************************************************************
+ *DESC_WORD4 - PCIE DMA Descriptor Word 4
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK        0x80000000
+#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT       31
+
+/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK                0x40000000
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT               30
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY      1
+#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE      0
+
+/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK                    0x3ffffff8
+#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT                   3
+
+/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK              0x00000004
+#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT             2
+
+/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK            0x00000003
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT           0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP         0
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32   1
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32         2
+#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved        3
+
+/***************************************************************************
+ *DESC_WORD5 - PCIE DMA Descriptor Word 5
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK         0xffffffe0
+#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT        5
+
+/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK                    0x0000001f
+#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD6 - PCIE DMA Descriptor Word 6
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK         0xffffffff
+#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT        0
+
+/***************************************************************************
+ *DESC_WORD7 - PCIE DMA Descriptor Word 7
+ ***************************************************************************/
+/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK                    0xffffff00
+#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT                   8
+
+/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK            0x000000ff
+#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT           0
+
+/***************************************************************************
+ *RAAGA_AX_MISC
+ ***************************************************************************/
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG0 - Cluster Package Data Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG0 :: ADDRESS_UPLEFTMB [63:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_UPLEFTMB_MASK 0xffffffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_UPLEFTMB_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG0 :: ADDRESS_LEFTMB [31:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_LEFTMB_MASK 0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_LEFTMB_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG1 - Cluster Package Data Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: OFFSET_REFERENCE [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_REFERENCE_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_REFERENCE_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: OFFSET_BVN_INPUT [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_BVN_INPUT_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_BVN_INPUT_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: ADDRESS_MBINFO [31:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_ADDRESS_MBINFO_MASK 0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_ADDRESS_MBINFO_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG2 - Cluster Package Data Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_TEMPORAL_LEFT [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_LEFT_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_LEFT_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_TEMPORAL_UPLEFT [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_UPLEFT_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_UPLEFT_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_SPATIAL_LEFT [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_LEFT_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_LEFT_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_SPATIAL_UPLEFT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_UPLEFT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_UPLEFT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG3 - Cluster Package Data Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_SCALEFACTOR [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_SCALEFACTOR_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_SCALEFACTOR_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_PRED_PIXELS [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_PRED_PIXELS_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_PRED_PIXELS_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_INPUT_420 [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_INPUT_420_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_INPUT_420_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_MV_TEMPORAL_DOWNLEFT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_MV_TEMPORAL_DOWNLEFT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_MV_TEMPORAL_DOWNLEFT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG4 - Cluster Package Data Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_CB_READ [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_CB_READ_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_CB_READ_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_LUMA_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_LUMA_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_CHROMA_REF [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_CHROMA_REF_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_CHROMA_REF_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG5 - Cluster Package Data Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_QUANT_OUTPUT [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_QUANT_OUTPUT_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_QUANT_OUTPUT_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CR_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CR_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CB_WRITE [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CB_WRITE_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CB_WRITE_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG6 - Cluster Package Data Structure Register 6
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_CR_TOP_WRITE [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CR_TOP_WRITE_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CR_TOP_WRITE_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_CB_TOP_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CB_TOP_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CB_TOP_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_LUMA_TOP_WRITE [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_LUMA_TOP_WRITE_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_LUMA_TOP_WRITE_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_INPUT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_INPUT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_INPUT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG7 - Cluster Package Data Structure Register 7
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_OUTPUT_INDEX [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_OUTPUT_INDEX_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_OUTPUT_INDEX_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_CR_TOP_READ [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CR_TOP_READ_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CR_TOP_READ_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_CB_TOP_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CB_TOP_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CB_TOP_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_LUMA_TOP_READ [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_LUMA_TOP_READ_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_LUMA_TOP_READ_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG0 - Private MB Info Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: reserved0 [63:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_reserved0_MASK     0xfff0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_reserved0_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_MODE_LUMA [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_MODE_LUMA_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_MODE_LUMA_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_COLUMN_NUMBER [47:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_COLUMN_NUMBER_MASK 0x0000ff0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_COLUMN_NUMBER_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_ROW_NUMBER [39:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_ROW_NUMBER_MASK 0x000000ff00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_ROW_NUMBER_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: BEST_SAD [31:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_BEST_SAD_MASK      0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_BEST_SAD_SHIFT     0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG1 - Private MB Info Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_7 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_7_MASK  0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_7_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_6 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_6_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_6_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_5 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_5_MASK  0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_5_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_4 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_4_MASK  0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_4_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_3_MASK  0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_3_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_2_MASK  0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_2_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_1_MASK  0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_1_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_0_MASK  0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_0_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG2 - Private MB Info Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_15 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_15_MASK 0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_15_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_14 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_14_MASK 0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_14_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_13 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_13_MASK 0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_13_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_12 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_12_MASK 0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_12_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_11 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_11_MASK 0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_11_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_10 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_10_MASK 0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_10_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_9 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_9_MASK  0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_9_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_8 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_8_MASK  0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_8_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG3 - Private MB Info Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_7 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_7_MASK   0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_7_SHIFT  56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_6 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_6_MASK   0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_6_SHIFT  48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_5 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_5_MASK   0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_5_SHIFT  40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_4 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_4_MASK   0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_4_SHIFT  32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_3_MASK   0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_3_SHIFT  24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_2_MASK   0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_2_SHIFT  16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_1_MASK   0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_1_SHIFT  8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_0_MASK   0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_0_SHIFT  0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG4 - Private MB Info Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_15 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_15_MASK  0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_15_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_14 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_14_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_14_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_13 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_13_MASK  0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_13_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_12 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_12_MASK  0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_12_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_11 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_11_MASK  0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_11_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_10 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_10_MASK  0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_10_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_9 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_9_MASK   0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_9_SHIFT  8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_8 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_8_MASK   0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_8_SHIFT  0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG5 - Private MB Info Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: LAMBDA_GENAX [63:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_GENAX_MASK  0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_GENAX_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved0 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved0_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved0_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_Y_COUNT [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_COUNT_MASK 0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_COUNT_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved1 [39:33] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved1_MASK     0x000000fe00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved1_SHIFT    33
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_Y_DIR [32:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_DIR_MASK 0x0000000100000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_DIR_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved2 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved2_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved2_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_X_COUNT [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_COUNT_MASK 0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_COUNT_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved3 [23:17] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved3_MASK     0x0000000000fe0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved3_SHIFT    17
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_X_DIR [16:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_DIR_MASK 0x0000000000010000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_DIR_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: LAMBDA [15:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_MASK        0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_SHIFT       0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG6 - Private MB Info Structure Register 6
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved0 [63:38] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved0_MASK     0xffffffc000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved0_SHIFT    38
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_2 [37:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_2_MASK      0x0000003f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_2_SHIFT     32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved1 [31:30] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved1_MASK     0x00000000c0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved1_SHIFT    30
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_1 [29:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_1_MASK      0x000000003f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_1_SHIFT     24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved2 [23:22] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved2_MASK     0x0000000000c00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved2_SHIFT    22
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_0 [21:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_0_MASK      0x00000000003f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_0_SHIFT     16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: LUMA_VARIANCE [15:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_VARIANCE_MASK 0x000000000000ff00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_VARIANCE_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: LUMA_MEAN [07:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_MEAN_MASK     0x00000000000000ff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_MEAN_SHIFT    0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG7 - Private MB Info Structure Register 7
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: reserved0 [63:38] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_reserved0_MASK     0xffffffc000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_reserved0_SHIFT    38
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: AVE_QPS [37:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVE_QPS_MASK       0x0000003f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVE_QPS_SHIFT      32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: AVG_ZONAL_BITS [31:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVG_ZONAL_BITS_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVG_ZONAL_BITS_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: TEXTURE_BITS [15:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_TEXTURE_BITS_MASK  0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_TEXTURE_BITS_SHIFT 0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG0 - Public MB Info Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved0 [63:62] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved0_MASK      0xc000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved0_SHIFT     62
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: INTRA_QP [61:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_INTRA_QP_MASK       0x3f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_INTRA_QP_SHIFT      56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved1 [55:54] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved1_MASK      0x00c0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved1_SHIFT     54
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: QP [53:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_QP_MASK             0x003f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_QP_SHIFT            48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved2 [47:46] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved2_MASK      0x0000c00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved2_SHIFT     46
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: CBP [45:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBP_MASK            0x00003f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBP_SHIFT           40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved3_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved3_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: MB_MODE_CHROMA [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_MB_MODE_CHROMA_MASK 0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_MB_MODE_CHROMA_SHIFT 32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved4 [31:27] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved4_MASK      0x00000000f8000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved4_SHIFT     27
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: CBF [26:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBF_MASK            0x0000000007ffffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBF_SHIFT           0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG1 - Public MB Info Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: reserved0 [63:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_reserved0_MASK      0xffffffff00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_reserved0_SHIFT     32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: MVD_Y [31:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_Y_MASK          0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_Y_SHIFT         16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: MVD_X [15:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_X_MASK          0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_X_SHIFT         0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG2 - Public MB Info Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved0 [63:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved0_MASK      0xffe0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved0_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MB_TYPE [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_MASK        0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_SHIFT       48
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_I4X4        0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_I16X16      1
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_P16X16      2
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_PSKIP       3
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_IPCM        5
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_DUMMY       31
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved1 [47:41] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved1_MASK      0x0000fe0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved1_SHIFT     41
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MB_AVAILABLE [40:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_AVAILABLE_MASK   0x0000010000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_AVAILABLE_SHIFT  40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved2 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved2_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved2_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: REF_ID [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_REF_ID_MASK         0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_REF_ID_SHIFT        32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MV_Y [31:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_Y_MASK           0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_Y_SHIFT          16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MV_X [15:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_X_MASK           0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_X_SHIFT          0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG3 - Public MB Info Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved0 [63:61] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved0_MASK      0xe000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved0_SHIFT     61
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_7 [60:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_7_MASK     0x1f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_7_SHIFT    56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved1 [55:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved1_MASK      0x00e0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved1_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_6 [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_6_MASK     0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_6_SHIFT    48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved2 [47:45] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved2_MASK      0x0000e00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved2_SHIFT     45
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_5 [44:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_5_MASK     0x00001f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_5_SHIFT    40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved3 [39:37] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved3_MASK      0x000000e000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved3_SHIFT     37
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_4 [36:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_4_MASK     0x0000001f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_4_SHIFT    32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved4 [31:29] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved4_MASK      0x00000000e0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved4_SHIFT     29
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_3 [28:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_3_MASK     0x000000001f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_3_SHIFT    24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved5 [23:21] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved5_MASK      0x0000000000e00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved5_SHIFT     21
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_2 [20:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_2_MASK     0x00000000001f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_2_SHIFT    16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved6 [15:13] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved6_MASK      0x000000000000e000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved6_SHIFT     13
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_1 [12:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_1_MASK     0x0000000000001f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_1_SHIFT    8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved7 [07:05] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved7_MASK      0x00000000000000e0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved7_SHIFT     5
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_0 [04:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_0_MASK     0x000000000000001f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_0_SHIFT    0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG4 - Public MB Info Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved0 [63:61] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved0_MASK      0xe000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved0_SHIFT     61
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_15 [60:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_15_MASK    0x1f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_15_SHIFT   56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved1 [55:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved1_MASK      0x00e0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved1_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_14 [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_14_MASK    0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_14_SHIFT   48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved2 [47:45] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved2_MASK      0x0000e00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved2_SHIFT     45
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_13 [44:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_13_MASK    0x00001f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_13_SHIFT   40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved3 [39:37] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved3_MASK      0x000000e000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved3_SHIFT     37
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_12 [36:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_12_MASK    0x0000001f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_12_SHIFT   32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved4 [31:29] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved4_MASK      0x00000000e0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved4_SHIFT     29
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_11 [28:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_11_MASK    0x000000001f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_11_SHIFT   24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved5 [23:21] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved5_MASK      0x0000000000e00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved5_SHIFT     21
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_10 [20:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_10_MASK    0x00000000001f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_10_SHIFT   16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved6 [15:13] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved6_MASK      0x000000000000e000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved6_SHIFT     13
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_9 [12:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_9_MASK     0x0000000000001f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_9_SHIFT    8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved7 [07:05] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved7_MASK      0x00000000000000e0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved7_SHIFT     5
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_8 [04:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_8_MASK     0x000000000000001f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_8_SHIFT    0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG5 - Public MB Info Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved0_MASK      0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved0_SHIFT     60
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_3 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_3_MASK         0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_3_SHIFT        56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved1_MASK      0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved1_SHIFT     52
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_2 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_2_MASK         0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_2_SHIFT        48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved2_MASK      0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved2_SHIFT     44
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_1 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_1_MASK         0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_1_SHIFT        40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved3_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved3_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_0 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_0_MASK         0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_0_SHIFT        32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved4_MASK      0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved4_SHIFT     28
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_3_MASK          0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_3_SHIFT         24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved5_MASK      0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved5_SHIFT     20
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_2_MASK          0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_2_SHIFT         16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved6_MASK      0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved6_SHIFT     12
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_1_MASK          0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_1_SHIFT         8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved7_MASK      0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved7_SHIFT     4
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_0_MASK          0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_0_SHIFT         0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_WAIT_EOP                               24
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/* union - case eop_args [22:00] */
+/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
+#define BCHP_RDC_RUL_eop_args_reserved0_MASK                       0x007fff00
+#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT                      8
+
+/* RDC :: RUL :: eop_args :: eop [07:00] */
+#define BCHP_RDC_RUL_eop_args_eop_MASK                             0x000000ff
+#define BCHP_RDC_RUL_eop_args_eop_SHIFT                            0
+
+/***************************************************************************
+ *EOP_ID_256 - EOP_ID
+ ***************************************************************************/
+/* RDC :: EOP_ID_256 :: eop_id [255:00] */
+#define BCHP_RDC_EOP_ID_256_eop_id_MASK                            0x0000000000000000000000000000000000000000000000000000000000000000
+#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT                           0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0                    0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1                    1
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2                    2
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3                    3
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4                    4
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5                    5
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6                    6
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7                    7
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0                    8
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1                    9
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2                    10
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3                    11
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4                    12
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5                    13
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6                    14
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7                    15
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0                    16
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1                    17
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2                    18
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3                    19
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4                    20
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5                    21
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6                    22
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7                    23
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0                   24
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1                   25
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2                   26
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3                   27
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4                   28
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5                   29
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6                   30
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0                    31
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0                   32
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1                   33
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2                   34
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3                   35
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4                   36
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5                   37
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6                   38
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7                   39
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0                    40
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0                   41
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be                    42
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0                   43
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_0                   44
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_1                   45
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0               46
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1               47
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0                    48
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1                    49
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2                    50
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3                    51
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4                    52
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5                    53
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6                    54
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7                    55
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8                    56
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9                    57
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10                   58
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11                   59
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12                   60
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13                   61
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2               62
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3               63
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0                           64
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1                           65
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2                           66
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3                           67
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4                           68
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5                           69
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6                           70
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7                           71
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0                           72
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1                           73
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2                           74
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3                           75
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4                           76
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5                           77
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6                           78
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7                           79
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_0                           80
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_1                           81
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_2                           82
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_3                           83
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_4                           84
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_5                           85
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_6                           86
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_7                           87
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0                           88
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1                           89
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2                           90
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3                           91
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4                           92
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5                           93
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6                           94
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7                           95
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_0                           96
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_1                           97
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_2                           98
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_3                           99
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_4                           100
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_5                           101
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_6                           102
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_7                           103
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_0                          104
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_1                          105
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_2                          106
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_3                          107
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_4                          108
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_5                          109
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_6                          110
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_7                          111
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0                           112
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1                           113
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2                           114
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3                           115
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4                           116
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5                           117
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6                           118
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7                           119
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0                           120
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1                           121
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2                           122
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3                           123
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4                           124
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5                           125
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6                           126
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7                           127
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0                           128
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1                           129
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2                           130
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3                           131
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4                           132
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5                           133
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6                           134
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7                           135
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0                        136
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1                        137
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2                        138
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3                        139
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4                        140
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5                        141
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6                        142
+#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0                           143
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_0                           144
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_1                           145
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_2                           146
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_3                           147
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_4                           148
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_5                           149
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_6                           150
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_7                           151
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0                          152
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1                          153
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2                          154
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3                          155
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4                          156
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5                          157
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6                          158
+#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0                           159
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_0                           160
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_1                           161
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_2                           162
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_3                           163
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_0                          164
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_1                          165
+#define BCHP_RDC_EOP_ID_256_eop_id_psm_0                           166
+#define BCHP_RDC_EOP_ID_256_eop_id_plm_0                           167
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0                    168
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1                    169
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2                    170
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3                    171
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4                    172
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5                    173
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6                    174
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7                    175
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0                    176
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1                    177
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2                    178
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3                    179
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0                   180
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1                   181
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0                    182
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0                    183
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0                 184
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0                 185
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0                 186
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0                 187
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0                 188
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0                 189
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0                 190
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0                 191
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1                 192
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1                 193
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1                 194
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1                 195
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1                 196
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1                 197
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1                 198
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1                 199
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0                   200
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1                   201
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2                   202
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3                   203
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4                   204
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5                   205
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6                   206
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7                   207
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0                   208
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0                    209
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0               210
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1               211
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2               212
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3               213
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4               214
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5               215
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0               216
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1               217
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2               218
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3               219
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4               220
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5               221
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6               222
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7               223
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8               224
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9               225
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10              226
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11              227
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12              228
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13              229
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_14              230
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9               231
+#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0                           232
+#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0                          233
+#define BCHP_RDC_EOP_ID_256_eop_id_v0_be                           234
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0                      235
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1                      236
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2                      237
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3                      238
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4                      239
+#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0                          240
+#define BCHP_RDC_EOP_ID_256_eop_id_frc_0                           241
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0                          242
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0                          243
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5                      244
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6                      245
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7                      246
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8                      247
+#define BCHP_RDC_EOP_ID_256_eop_id_tntd_0                          248
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_hddvi_0_passthr             249
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11                     250
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12                     251
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13                     252
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14                     253
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15                     254
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16                     255
+
+/***************************************************************************
+ *SPDIF_RCVR_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_ebi.h b/include/linux/brcmstb/7250b0/bchp_ebi.h
new file mode 100644
index 000000000000..d6a8b29db201
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_ebi.h
@@ -0,0 +1,2007 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:45 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_HI_0                    0x00440800 /* Upper 8-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_BASE_0                       0x00440804 /* Lower 32-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00440808 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_HI_1                    0x0044080c /* Upper 8-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00440810 /* Lower 32-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x00440814 /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_HI_2                    0x00440818 /* Upper 8-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_BASE_2                       0x0044081c /* Lower 32-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00440820 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_HI_3                    0x00440824 /* Upper 8-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00440828 /* Lower 32-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0044082c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_HI_4                    0x00440830 /* Upper 8-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00440834 /* Lower 32-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00440838 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_HI_5                    0x0044083c /* Upper 8-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00440840 /* Lower 32-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x00440844 /* EBI CS Config 5 Register */
+#define BCHP_EBI_CS_BASE_HI_6                    0x00440848 /* Upper 8-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_BASE_6                       0x0044084c /* Lower 32-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_CONFIG_6                     0x00440850 /* EBI CS Config 6 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00440860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00440864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00440868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0044086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00440870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00440874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_6                     0x00440878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00440900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00440918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00440920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004409f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_6 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_6_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_6_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_6 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_6_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_6_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_6_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_6 - EBI CS Config 6 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_6_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_6_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_6_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_6_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_6_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_6_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_6_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_6_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_6_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_6 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_6_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_6_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_6_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_6_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_6_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffff80
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   7
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK             0x00000040
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT            6
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff8000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     15
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK                      0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT                     7
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00440a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_hif_intr2.h b/include/linux/brcmstb/7250b0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..976e2c52f996
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_hif_intr2.h
@@ -0,0 +1,1442 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:46 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00441000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00441004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00441008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0044100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00441010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00441014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00441018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0044101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00441020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00441024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00441028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0044102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0x30000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  19
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK                   0x00030000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT                  16
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK                   0x00004000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT                  14
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_SHIFT                  6
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved5_MASK                   0x0000000e
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved5_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0x30000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     19
+
+/* HIF_INTR2 :: CPU_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK                      0x00030000
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT                     16
+
+/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK                      0x00004000
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT                     14
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved4_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_CPU_SET_reserved4_SHIFT                     6
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved5_MASK                      0x0000000e
+#define BCHP_HIF_INTR2_CPU_SET_reserved5_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0x30000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   19
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK                    0x00030000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT                   16
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK                    0x00004000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT                   14
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_SHIFT                   6
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved5_MASK                    0x0000000e
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved5_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             19
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK              0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT             14
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT             6
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_MASK              0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                19
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK                 0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT                14
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT                6
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_MASK                 0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              19
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK               0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT              14
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT              6
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_MASK               0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0x30000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  19
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK                   0x00030000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT                  16
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK                   0x00004000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT                  14
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_SHIFT                  6
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved5_MASK                   0x0000000e
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved5_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0x30000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     19
+
+/* HIF_INTR2 :: PCI_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK                      0x00030000
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT                     16
+
+/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK                      0x00004000
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT                     14
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved4_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_PCI_SET_reserved4_SHIFT                     6
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved5_MASK                      0x0000000e
+#define BCHP_HIF_INTR2_PCI_SET_reserved5_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0x30000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   19
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK                    0x00030000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT                   16
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK                    0x00004000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT                   14
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_SHIFT                   6
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved5_MASK                    0x0000000e
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved5_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             19
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK              0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT             14
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT             6
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_MASK              0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                19
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK                 0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT                14
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT                6
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_MASK                 0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              19
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK               0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT              14
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT              6
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_MASK               0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_hif_mspi.h b/include/linux/brcmstb/7250b0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..0c38a5f64160
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_hif_mspi.h
@@ -0,0 +1,1291 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:47 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00443400 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00443404 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00443408 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0044340c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00443410 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00443414 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00443418 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00443420 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00443424 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR3                      0x00443428 /* SPCR3 REGISTER */
+#define BCHP_HIF_MSPI_REVISION                   0x0044342c /* REVISION ID REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00443440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00443444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00443448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0044344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00443450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00443454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00443458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0044345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00443460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00443464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00443468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0044346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00443470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00443474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00443478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0044347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00443480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00443484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00443488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0044348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00443490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00443494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00443498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0044349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004434a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004434a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004434a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004434ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004434b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004434b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004434b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004434bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004434c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004434c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004434c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004434cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004434d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004434d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004434d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004434dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004434e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004434e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004434e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004434ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004434f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004434f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004434f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004434fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00443500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00443504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00443508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0044350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00443510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00443514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00443518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0044351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00443520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00443524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00443528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0044352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00443530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00443534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00443538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0044353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00443540 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00443544 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00443548 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0044354c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00443550 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00443554 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00443558 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0044355c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00443560 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00443564 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00443568 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0044356c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00443570 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00443574 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00443578 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0044357c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00443580 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00443584 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xfffffe00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    9
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000100
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              8
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* union - case data_reg_8 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK          0x000000c0
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT         6
+
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK               0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT              2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT            0x00000000
+
+/* union - case data_reg_32 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK              0x000000fc
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT             2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT           0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR3 - SPCR3 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
+#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK                         0xfffffc00
+#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT                        10
+
+/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
+#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK                            0x00000200
+#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT                           9
+#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK                     0x00000100
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT                    8
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT                  0x00000000
+
+/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK                         0x00000080
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT                        7
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT                      0x00000000
+
+/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK                        0x00000040
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT                       6
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT                     0x00000000
+
+/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
+#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK                          0x00000030
+#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT                         4
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK                          0x0000000c
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
+#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK                            0x00000002
+#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT                           1
+#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
+#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK                            0x00000001
+#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT                           0
+#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *REVISION - REVISION ID REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_REVISION_reserved0_MASK                      0xffffff00
+#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT                     8
+
+/* HIF_MSPI :: REVISION :: major [07:04] */
+#define BCHP_HIF_MSPI_REVISION_major_MASK                          0x000000f0
+#define BCHP_HIF_MSPI_REVISION_major_SHIFT                         4
+#define BCHP_HIF_MSPI_REVISION_major_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: REVISION :: minor [03:00] */
+#define BCHP_HIF_MSPI_REVISION_minor_MASK                          0x0000000f
+#define BCHP_HIF_MSPI_REVISION_minor_SHIFT                         0
+#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT                       0x00000005
+
+/***************************************************************************
+ *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7250b0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..1b8bc9bc6d63
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,566 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:44 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00441a00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00441a04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00441a08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00441a0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00441a10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00441a14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00441a18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00441a1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00441a20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00441a24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00441a28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00441a2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_irq0.h b/include/linux/brcmstb/7250b0/bchp_irq0.h
new file mode 100644
index 000000000000..cbfbaefc58f5
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_irq0.h
@@ -0,0 +1,156 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:49 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x0040a380 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x0040a384 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:09] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xfffffe00
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            9
+
+/* IRQ0 :: IRQEN :: irb_irqen [08:08] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000100
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            8
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: gio_irqen [07:07] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000080
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            7
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x00000040
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           6
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000020
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             5
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00000004
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          2
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00000002
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          1
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00000001
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          0
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:09] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xfffffe00
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          9
+
+/* IRQ0 :: IRQSTAT :: irbirq [08:08] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000100
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             8
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: gioirq [07:07] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000080
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             7
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x00000040
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            6
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000020
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              5
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uairq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00000004
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          2
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00000002
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          1
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00000001
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          0
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_nand.h b/include/linux/brcmstb/7250b0/bchp_nand.h
new file mode 100644
index 000000000000..074431d6157e
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_nand.h
@@ -0,0 +1,3757 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu May  8 18:43:50 2014
+ *                 Full Compile MD5 Checksum 38a69701e4a8587ad79f065a389355cd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              9624d46404976e509a15e5a9755e7873
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008005
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00442800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00442804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00442808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0044280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00442810 /* Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x00442814 /* Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00442818 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x0044281c /* Nand Flash EBI CS XOR masking on CPU address Control */
+#define BCHP_NAND_LL_OP                          0x00442820 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x00442824 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x00442828 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x00442850 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS0                 0x00442854 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS0                     0x00442858 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x0044285c /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x00442860 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x00442864 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS1                 0x00442868 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS1                     0x0044286c /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x00442870 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x00442874 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x00442878 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS2                 0x0044287c /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS2                     0x00442880 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x00442884 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x00442888 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x0044288c /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS3                 0x00442890 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS3                     0x00442894 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x00442898 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x0044289c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x004428a0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS4                 0x004428a4 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS4                     0x004428a8 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x004428ac /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x004428b0 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x004428b4 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS5                 0x004428b8 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS5                     0x004428bc /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x004428c0 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x004428c4 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS6                0x004428c8 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS6                 0x004428cc /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS6                     0x004428d0 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS6                   0x004428d4 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS6                   0x004428d8 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x004428dc /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x004428e0 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004428e4 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x004428e8 /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x004428ec /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x004428f0 /* Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x004428fc /* Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x00442900 /* Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00442904 /* Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00442908 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x0044290c /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00442910 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00442914 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x00442918 /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x0044291c /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00442920 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00442924 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x00442928 /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x0044292c /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x00442930 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x00442934 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x00442938 /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x0044293c /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x00442940 /* Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x00442944 /* Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x00442948 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0044294c /* ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x00442950 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00442994 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00442998 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x0044299c /* Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00442a00 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00442a04 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00442a08 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x00442a0c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00442a10 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00442a14 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00442a18 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x00442a1c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x00442a20 /* Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x00442a24 /* Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x00442a28 /* Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x00442a2c /* Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x00442a30 /* Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x00442a34 /* Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x00442a38 /* Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x00442a3c /* Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00442a80 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00442a84 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00442a88 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x00442a8c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00442a90 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00442a94 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00442a98 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x00442a9c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x00442aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x00442aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x00442aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x00442aac /* Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x00442ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x00442ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x00442ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x00442abc /* Nand Flash Spare Area Write Bytes 60-63 */
+#define BCHP_NAND_DDR_TIMING                     0x00442ac0 /* Nand Flash DDR TIMING */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL             0x00442ac4 /* Nand Flash Calibration Control for Master DLL */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD          0x00442ac8 /* Nand Flash Calibration Period */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT            0x00442acc /* Nand Flash Calibration Status for Master DLL */
+#define BCHP_NAND_DDR_NCDL_MODE                  0x00442ad0 /* Nand Flash NCDL mode for Slave DLLs */
+#define BCHP_NAND_DDR_NCDL_OFFSET                0x00442ad4 /* Nand Flash NCDL offset for Slave DLLs */
+#define BCHP_NAND_DDR_PHY_CTL                    0x00442ad8 /* Nand Flash DDR PHY CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_CTL               0x00442adc /* Nand Flash DDR PHY BIST CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_STAT              0x00442ae0 /* Nand Flash DDR PHY BIST STATUS */
+#define BCHP_NAND_DDR_DIAG_STAT0                 0x00442ae4 /* Nand Flash DDR DIAG STATUS0 */
+#define BCHP_NAND_DDR_DIAG_STAT1                 0x00442ae8 /* Nand Flash DDR DIAG STATUS1 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: reserved0 [31:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0xffff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000007
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000001
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:05] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5
+
+/* NAND :: CMD_START :: OPCODE [04:00] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK                      0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT                     29
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT                   0x00000001
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK                0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT               31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT             0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK               0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT              7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK               0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT              6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK               0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT              5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK               0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT              4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK               0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT              3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK               0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT              2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK               0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT              1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK               0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT              0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS0 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS0 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS0 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS0 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS0 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS0_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS0_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS0_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS0_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS1 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS1 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS1 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS1 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS1 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS1_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS1_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS1_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS1_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS2 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS2 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS2 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS2 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS2 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS2_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS2_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS2_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS2_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS3 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS3 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS3 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS3 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS3 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS3_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS3_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS3_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS3_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS4 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS4 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS4 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS4 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS4 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS4_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS4_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS4_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS4_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS5 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS5 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS5 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS5 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS5 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS5_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS5_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS5_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS5_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS6 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS6 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS6 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS6 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS6 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS6 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS6 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS6_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS6 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS6_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS6_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS6_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS6_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS6 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS6_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS6_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS6_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS6_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS6_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS6_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS6_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS6 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS6 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS6 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS6_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS6_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS6_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS6_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS6_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS6_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xfffff000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          12
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *DDR_TIMING - Nand Flash DDR TIMING
+ ***************************************************************************/
+/* NAND :: DDR_TIMING :: reserved0 [31:28] */
+#define BCHP_NAND_DDR_TIMING_reserved0_MASK                        0xf0000000
+#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT                       28
+
+/* NAND :: DDR_TIMING :: tCCS [27:24] */
+#define BCHP_NAND_DDR_TIMING_tCCS_MASK                             0x0f000000
+#define BCHP_NAND_DDR_TIMING_tCCS_SHIFT                            24
+#define BCHP_NAND_DDR_TIMING_tCCS_DEFAULT                          0x00000008
+
+/* NAND :: DDR_TIMING :: tCAD [23:20] */
+#define BCHP_NAND_DDR_TIMING_tCAD_MASK                             0x00f00000
+#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT                            20
+#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT                          0x00000004
+
+/* NAND :: DDR_TIMING :: reserved1 [19:17] */
+#define BCHP_NAND_DDR_TIMING_reserved1_MASK                        0x000e0000
+#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT                       17
+
+/* NAND :: DDR_TIMING :: tWHR [16:12] */
+#define BCHP_NAND_DDR_TIMING_tWHR_MASK                             0x0001f000
+#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT                            12
+#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT                          0x00000014
+
+/* NAND :: DDR_TIMING :: tCS [11:08] */
+#define BCHP_NAND_DDR_TIMING_tCS_MASK                              0x00000f00
+#define BCHP_NAND_DDR_TIMING_tCS_SHIFT                             8
+#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT                           0x00000002
+
+/* NAND :: DDR_TIMING :: tWB [07:04] */
+#define BCHP_NAND_DDR_TIMING_tWB_MASK                              0x000000f0
+#define BCHP_NAND_DDR_TIMING_tWB_SHIFT                             4
+#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT                           0x0000000f
+
+/* NAND :: DDR_TIMING :: tADL [03:00] */
+#define BCHP_NAND_DDR_TIMING_tADL_MASK                             0x0000000f
+#define BCHP_NAND_DDR_TIMING_tADL_SHIFT                            0
+#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT                          0x00000007
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK                0xfffffff0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT               4
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK           0x00000008
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT          3
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT        0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK             0x00000004
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT            2
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT          0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK               0x00000002
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT              1
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT            0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK                 0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT                0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK             0xfff00000
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT            20
+
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK          0x000fffff
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT         0
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK               0xffff0000
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT              16
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK              0x0000ff00
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT             8
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT           0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK               0x000000fe
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT              1
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK              0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT             0
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT           0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK                     0xffffffe0
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT                    5
+
+/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK                        0x00000010
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT                       4
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT                     0x00000000
+
+/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK                     0x0000000e
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT                    1
+
+/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK                        0x00000001
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT                       0
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK                   0xfe000000
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT                  25
+
+/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK                  0x01ff0000
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT                 16
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT               0x00000000
+
+/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK                   0x0000fe00
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT                  9
+
+/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK                  0x000001ff
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT                 0
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT               0x00000000
+
+/***************************************************************************
+ *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK                       0xfffffffc
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT                      2
+
+/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK                        0x00000002
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT                       1
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT                     0x00000000
+
+/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK                       0x00000001
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT                      0
+
+/***************************************************************************
+ *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK                  0xffffffe0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT                 5
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK                   0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT                  4
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT                0x00000000
+
+/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK                  0x0000000e
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT                 1
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT                0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK                 0xffffff80
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT                7
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK          0x00000040
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT         6
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK          0x00000020
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT         5
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK          0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT         4
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK          0x00000008
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT         3
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK               0x00000004
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT              2
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK               0x00000002
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT              1
+
+/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT                0
+
+/***************************************************************************
+ *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00442c00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7250b0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..5cf56077bdda
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,827 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Sep 13 03:11:33 2014
+ *                 Full Compile MD5 Checksum 81d1dc071f09e844b7694a9d7010032b
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              8011b86e52a731b78eada82a643ab85a
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00440100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00440104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00440108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE         0x0044010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x00440110 /* SDIO CAPABILITIES override Register[31:0] */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00440114 /* SDIO CAPABILITIES override Register[63:32] */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00440118 /* SDIO PRESET_INIT/PRESET_DS override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x0044011c /* SDIO PRESET_HS/PRESET_SDR12 override Register */
+#define BCHP_SDIO_0_CFG_PRESET3                  0x00440120 /* SDIO PRESET_SDR25/PRESET_SDR50 override Register */
+#define BCHP_SDIO_0_CFG_PRESET4                  0x00440124 /* SDIO PRESET_SDR104/PRESET_DDR50 override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x00440128 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x0044012c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00440130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00440134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00440138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0044013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY            0x00440140 /* Debug TAP delay setting register */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS  0x00440144 /* Debug A2S Bridge Status */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x00440148 /* Debug register to read AHB req start address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR   0x0044014c /* Debug register to read AHB req end address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x00440150 /* Disable Client Init */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL               0x00440154 /* SD Pin Select */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT              0x00440158 /* Max Current Override */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004401f0 /* SDIO VERSION Register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004401fc /* SDIO Scratch Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK             0x0ffc0000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT            18
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK        0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT       17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK             0x000003fc
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT            2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK          0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT         0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT       0x00000003
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000003
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK            0xfffffffe
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT           1
+
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK     0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT    0
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0xc0000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK                     0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT                    29
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK                0x10000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT               28
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK                    0x08000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT                   27
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK                 0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT                26
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK                 0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT                25
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK               0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT              23
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK                         0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT                        22
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT                      0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK                   0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT                  21
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK                    0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT                   20
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK                        0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT                       19
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK               0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT              18
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK                0x00030000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT               16
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK                0x0000ff00
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT               8
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK                 0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT                7
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK                    0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT                   6
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK             0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0xfc000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   26
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK               0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT              25
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    24
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x00ff0000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    16
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK                0x0000c000
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT               14
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK                   0x00002000
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT                  13
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK                    0x00001000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT                   12
+
+/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK                  0x00000f00
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT                 8
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK                    0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT                   7
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK                     0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT                    6
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK                     0x00000020
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT                    5
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK                     0x00000010
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT                    4
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT                   3
+
+/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK                        0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT                       2
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK                       0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT                      1
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT                    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK                        0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT                       0
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK                   0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT                  16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT                  0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK                  0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT                 0
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT               0x00000003
+
+/***************************************************************************
+ *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK                 0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT                0
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT              0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: reserved_for_padding2 [05:05] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_MASK          0x00000020
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_SHIFT         5
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000001f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xffffffc0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     6
+
+/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT                  0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT                0x00000020
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *DEBUG_TAP_DLY - Debug TAP delay setting register
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK               0xfffff000
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT              12
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK      0x00000f00
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT     8
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK               0x00000080
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT              7
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK      0x0000007f
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT     0
+
+/***************************************************************************
+ *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK     0x60000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT    29
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK  0x10000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK     0x0e000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT    25
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK     0x0000ff80
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT    7
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK     0x00000070
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT    4
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK     0x00000008
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT    3
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK     0x00000007
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT    0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK   0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT  0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK       0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT      0
+
+/***************************************************************************
+ *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK   0xfffffffe
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT  1
+
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SD_PIN_SEL - SD Pin Select
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK                    0x00000003
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT                   0
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MAX_CURRENT - Max Current Override
+ ***************************************************************************/
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK                  0x80000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT                 31
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK                 0x7f000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT                24
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK             0x00ff0000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT            16
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK             0x0000ff00
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT            8
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK             0x000000ff
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT            0
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK                     0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT                    24
+
+/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK                      0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT                     16
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT                   0x00000003
+
+/* SDIO_0_CFG :: VERSION :: IP_VERSION [15:00] */
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_MASK                    0x0000ffff
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_SHIFT                   0
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_DEFAULT                 0x00001170
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7250b0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..e50d86f2bb94
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,5876 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:52 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3       0x004040bc /* General status register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4       0x004040c0 /* General status register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404120 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404124 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404128 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040412c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404130 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404134 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0      0x004043a8 /* UART Router select 0 */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1      0x004043ac /* UART Router select 1 */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2      0x0040451c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2    0x00404520 /* OTP option status register */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x72500010
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x72500010
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffffc00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            10
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000003e0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x0000000b
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_sata [04:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_MASK       0x00000010
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rc_ep [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_MASK           0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_SHIFT          3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rc_ep_DEFAULT        0x00000001
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_enc [04:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_MASK  0x00000018
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_DEFAULT 0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_powerup [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_flash_boot [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_3 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie0_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_9 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_9_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_9_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0x001fe000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK         0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT        11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_11 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_11_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_11_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_4 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_10 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_10_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_24 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_24_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_24_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved_for_padding0 [28:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved_for_padding0_MASK 0x1c000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved_for_padding0_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_16 [25:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_16_MASK 0x03800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_16_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_15 [22:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_15_MASK 0x00600000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_15_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_6 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_6_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_6_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_6_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_25 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_25_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_25_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_0_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_27 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_27_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_27_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_26 [09:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_26_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_26_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hevc_10_bit_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_2 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_2_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_2_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_7 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_7_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_7_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_8 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_8_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_8_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p0_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_1 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_3 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie0_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_9 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_9_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_9_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0x001fe000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK       0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT      11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_11 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_11_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_11_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_4 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_10 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_10_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_10_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_24 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_24_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_24_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved_for_padding0 [28:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved_for_padding0_MASK 0x1c000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved_for_padding0_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_16 [25:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_16_MASK 0x03800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_16_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_15 [22:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_15_MASK 0x00600000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_15_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_6 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_6_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_6_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_25 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_25_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_25_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_0_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_27 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_27_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_27_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_26 [09:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_26_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_26_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hevc_10_bit_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_2 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_2_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_2_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_7 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_7_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_7_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_8 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_8_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_8_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p0_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_1 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_alt_pin_sel [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_MASK    0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_SHIFT   9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: rgmii_swap [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_DEFAULT        0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT    1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT   1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000007
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved_for_padding1 [23:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved_for_padding1_MASK 0x00fffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved_for_padding1_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_hys_en [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_hys_en_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_hys_en_SHIFT  31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_hys_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sc0_pad_sel [30:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_MASK  0x70000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sc0_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xffffe000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   13
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: sata_refsel [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_sata_refsel_MASK  0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_sata_refsel_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_sata_refsel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: mtsif_hys_en [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_mtsif_hys_en_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_mtsif_hys_en_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_mtsif_hys_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pkt2_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt2_hys_en_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt2_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt2_hys_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: gpio_91to95_pad_sel [05:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_MASK 0x00000038
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: gpio_91to95_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_gpio_91to95_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pkt3_hys_en [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt3_hys_en_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt3_hys_en_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pkt3_hys_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: ptk2_hys_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_ptk2_hys_en_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_ptk2_hys_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_ptk2_hys_en_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_STATUS_3 - General status register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_4 - General status register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_sf_mosi [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_mosi_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_mosi_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_mosi_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_mosi_ONOFF_SF_MOSI 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_mosi_TSPI_S0_MOSI 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_sf_miso [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_miso_MASK        0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_miso_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_miso_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_miso_ONOFF_SF_MISO 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_miso_TSPI_S0_MISO 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_sf_sck [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_sck_MASK         0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_sck_SHIFT        20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_sck_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_sck_ONOFF_SF_SCK 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_sf_sck_TSPI_S0_SCK  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_pcie_clkreqb [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_clkreqb_MASK   0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_clkreqb_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_clkreqb_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_clkreqb_ONOFF_PCIE_CLKREQB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_clkreqb_TP_OUT_11 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_pcie_rstb [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_rstb_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_rstb_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_rstb_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_rstb_ONOFF_PCIE_RSTB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_pcie_rstb_TP_IN_11  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_usb1_pwron [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb1_pwron_MASK     0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb1_pwron_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb1_pwron_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb1_pwron_ONOFF_USB1_PWRON 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb1_pwron_TP_OUT_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_usb0_pwron [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb0_pwron_MASK     0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb0_pwron_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb0_pwron_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb0_pwron_ONOFF_USB0_PWRON 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_usb0_pwron_TP_IN_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_aud0_spdif [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_MASK     0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_ONOFF_AUD0_SPDIF 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_TP_IN_13 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_SHIFT   28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_ONOFF_EBI_DATA_03 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_SD_CARD1_DAT3 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_TSPI_S2_SS0B 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_03_SATA_MDIO 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_MASK    0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_SHIFT   24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_ONOFF_EBI_DATA_02 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_SD_CARD1_DAT2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_TSPI_S2_MOSI 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_02_TP_IN_29 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_01 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_MASK    0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_ONOFF_EBI_DATA_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_SD_CARD1_DAT1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_TSPI_S2_MISO 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_01_TP_OUT_29 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_00 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_MASK    0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_SHIFT   16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_ONOFF_EBI_DATA_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_SD_CARD1_DAT0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_TSPI_S2_SCK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_00_SATA_MDCLK 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_emmc_clk [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_clk_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_clk_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_clk_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_clk_ONOFF_EMMC_CLK 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_clk_TP_IN_25   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_emmc_cmd [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_cmd_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_cmd_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_cmd_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_cmd_ONOFF_EMMC_CMD 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_emmc_cmd_TP_OUT_23  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_sf_wpb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_wpb_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_wpb_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_wpb_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_wpb_ONOFF_SF_WPB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_wpb_TP_IN_17     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_sf_holdb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_holdb_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_holdb_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_holdb_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_holdb_ONOFF_SF_HOLDB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_sf_holdb_TP_OUT_17  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_we0b [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_ONOFF_EBI_WE0B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_NAND_WEB   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_SD_CARD1_CLK 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_we0b_TP_OUT_20  4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_cs2b [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs2b_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs2b_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs2b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs2b_ONOFF_EBI_CS2B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs2b_TP_IN_20   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_cs1b [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_ONOFF_EBI_CS1B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_SF_CS0B    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs1b_TP_OUT_25  2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_cs0b [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_ONOFF_EBI_CS0B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_NAND_CEB   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_cs0b_TSPI_S0_SS0B 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_data_07 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_07_MASK    0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_07_SHIFT   12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_07_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_07_ONOFF_EBI_DATA_07 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_07_TSPI_S1_SS0B 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_data_06 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_06_MASK    0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_06_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_06_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_06_ONOFF_EBI_DATA_06 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_06_TSPI_S1_MOSI 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_data_05 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_05_MASK    0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_05_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_05_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_05_ONOFF_EBI_DATA_05 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_05_TSPI_S1_MISO 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_data_04 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_04_MASK    0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_04_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_04_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_04_ONOFF_EBI_DATA_04 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_data_04_TSPI_S1_SCK 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_058 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_ONOFF_GPIO_058 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_SC0_VCC    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_TEST_THP   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_UART_RXD_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_CPU_TRACE_DATA12 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_PKT_CLK3   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_SPI_M_MOSI 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_RMX_CLK0   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_LED_LD_8   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_TP_IN_00   9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_058_PM_GPIO_058 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_011 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_ONOFF_GPIO_011 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_RSVD       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_RSVD_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_RSVD_2     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_PWM2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_EXT_USB_HUB_CLK 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_011_TP_OUT_14  6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_nand_dqs [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_MASK   0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_ONOFF_EBI_NAND_DQS 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_RSVD   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_RSVD_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_SD_CARD1_PWR0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_dqs_TP_IN_23 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_nand_wpb [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_MASK   0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_ONOFF_EBI_NAND_WPB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_RSVD   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_RSVD_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_SD_CARD1_WPROT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_wpb_TP_IN_14 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_nand_rbb [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_MASK   0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_ONOFF_EBI_NAND_RBB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_RSVD   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_RSVD_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_SD_CARD1_CMD 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_TSPI_S3_SS0B 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_nand_rbb_TP_IN_31 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_dsb [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_MASK        0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_ONOFF_EBI_DSB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_NAND_ALE    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_RSVD        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_SD_CARD1_LED 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_TSPI_S3_MOSI 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_dsb_TP_IN_30    5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_tsb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_MASK        0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_ONOFF_EBI_TSB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_NAND_CLE    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_RSVD        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_SD_CARD1_PRES 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_TSPI_S3_MISO 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_tsb_TP_OUT_31   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_ebi_rdb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_ONOFF_EBI_RDB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_NAND_REB    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_RSVD        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_SD_CARD1_CLK_IN 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_TSPI_S3_SCK 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_ebi_rdb_TP_OUT_30   5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_079 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_ONOFF_GPIO_079 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_RGMII_A_RX_CLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_PKT_CLK0_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_VO0_656_0  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_IR_IN1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_MTSIF0_CLK 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_SD_CARD0_CMD 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_CPU_TRACE_CLK 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_TP_IN_09   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_079_PM_GPIO_079 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_065 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_ONOFF_GPIO_065 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_SC0_VPP    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_I2S_LR0_OUT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_I2S_LR0_IN 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_PKT_SYNC2_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_RGMII_A_RX_OK 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_LED_LD_15  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_TP_OUT_03  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_065_PM_GPIO_065 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_064 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_ONOFF_GPIO_064 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_SC0_AUX2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_I2S_DATA0_OUT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_I2S_DATA0_IN 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_PKT_DATA2_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_RGMII_A_START_STOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_LED_LD_14  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_TP_IN_03   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_064_PM_GPIO_064 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_063 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_ONOFF_GPIO_063 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_SC0_AUX1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_I2S_CLK0_OUT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_I2S_CLK0_IN 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_PKT_CLK2_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_EXT_IRQB_3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_LED_LD_13  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_TP_OUT_02  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_063_PM_GPIO_063 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_062 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_ONOFF_GPIO_062 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_SC0_PRES   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_EXT_IRQB_2 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_RSVD_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_AUD_FS_CLK0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_PKT_ERROR3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_SPI_M_SS1B 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_RMX_PAUSE0 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_LED_LD_12  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_TP_IN_02   9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_062_PM_GPIO_062 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_061 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_ONOFF_GPIO_061 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_SC0_IO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_IR_IN1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_UART_CTS_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_CPU_TRACE_DATA15 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_PKT_VALID3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_SPI_M_MISO 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_RMX_VALID0 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_LED_LD_11  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_TP_IN_01   9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_061_PM_GPIO_061 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_060 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_ONOFF_GPIO_060 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_SC0_RST    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_EXT_IRQB_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_UART_RTS_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_CPU_TRACE_DATA14 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_PKT_SYNC3  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_SPI_M_SCK  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_RMX_SYNC0  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_LED_LD_10  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_TP_OUT_01  9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_060_PM_GPIO_060 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_059 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_ONOFF_GPIO_059 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_SC0_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_EXT_IRQB_0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_UART_TXD_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_CPU_TRACE_DATA13 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_PKT_DATA3  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_SPI_M_SS0B 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_RMX_DATA0  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_LED_LD_9   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_TP_OUT_00  9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_059_PM_GPIO_059 10
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_087 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_ONOFF_GPIO_087 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_RGMII_A_TXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_PKT_ERROR1_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_VO0_656_CLK 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_UART_RXD_2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_MTSIF0_DATA5 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_SD_CARD0_WPROT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_CPU_TRACE_DATA7 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_ENET0_ACTIVITY 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_TP_IN_06   9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_087_PM_GPIO_087 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_086 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_ONOFF_GPIO_086 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_RGMII_A_TX_EN_CTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_PKT_SYNC1_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_VO0_656_7  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_UART_RTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_MTSIF0_DATA4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_SD_CARD0_PRES 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_CPU_TRACE_DATA6 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_ENET0_LINK 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_TP_IN_05   9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_086_PM_GPIO_086 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_085 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_ONOFF_GPIO_085 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_RGMII_A_TX_CLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_PKT_DATA1_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_VO0_656_6  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_UART_CTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_MTSIF0_DATA3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_SD_CARD0_CLK_IN 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_CPU_TRACE_DATA5 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_TP_IN_04   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_085_PM_GPIO_085 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_084 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_ONOFF_GPIO_084 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_RGMII_A_RXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_PKT_CLK1_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_VO0_656_5  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_UART_TXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_MTSIF0_DATA2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_SD_CARD0_DAT3 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_CPU_TRACE_DATA4 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_TP_OUT_12  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_084_PM_GPIO_084 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_083 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_ONOFF_GPIO_083 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_RGMII_A_RXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_PKT_VALID0_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_VO0_656_4  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_UART_RXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_MTSIF0_VALID 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_SD_CARD0_DAT2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_CPU_TRACE_DATA3 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_TP_IN_12   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_083_PM_GPIO_083 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_082 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_ONOFF_GPIO_082 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_RGMII_A_RXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_PKT_ERROR0_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_VO0_656_3  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_UART_RTS_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_MTSIF0_DATA1 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_SD_CARD0_DAT1 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_CPU_TRACE_DATA2 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_TP_IN_10   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_082_PM_GPIO_082 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_081 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_ONOFF_GPIO_081 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_RGMII_A_RXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_PKT_SYNC0_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_VO0_656_2  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_UART_CTS_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_MTSIF0_SYNC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_SD_CARD0_DAT0 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_CPU_TRACE_DATA1 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_TP_OUT_10  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_081_PM_GPIO_081 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_080 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_ONOFF_GPIO_080 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_RGMII_A_RX_EN_CTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_PKT_DATA0_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_VO0_656_1  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_RSVD       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_MTSIF0_DATA0 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_SD_CARD0_CLK 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_CPU_TRACE_DATA0 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_TP_OUT_09  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_080_PM_GPIO_080 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_095 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_ONOFF_GPIO_095 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_RGMIIA_IRQ 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_SPI_M_SCK  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_I2S_LR0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_RMX_SYNC0_ALT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_SD_CARD0_VOLT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_PKT_CLK2   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_TP_IN_08   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_095_PM_GPIO_095 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_094 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_ONOFF_GPIO_094 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_MII_A_TX_ERR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_SPI_M_SS0B 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_I2S_DATA0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_RMX_DATA0_ALT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_ENET0_ACTIVITY 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_SD_CARD0_LED 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_TP_IN_07   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_094_PM_GPIO_094 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_093 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_ONOFF_GPIO_093 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_MII_A_RX_ERR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_SPI_M_MOSI 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_I2S_CLK0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_RMX_CLK0_ALT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_ENET0_LINK 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_SD_CARD0_PWR0 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_TP_OUT_07  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_093_PM_GPIO_093 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_092 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_ONOFF_GPIO_092 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_RGMII_A_MDC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_I2S_LR0_OUT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_UART_TXD_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_MTSIF_ATS_RST 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_SD_CARD0_PRES 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_SD_CARD0_PWR0 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_SD_CARD0_VOLT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_ALT_TP_OUT_02 9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_092_PM_GPIO_092 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_091 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_ONOFF_GPIO_091 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_RGMII_A_MDIO 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_RSVD_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_UART_RXD_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_MTSIF_ATS_INC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_SD_CARD0_WPROT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_CPU_TRACE_DATA11 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_SD_CARD0_LED 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_ALT_TP_IN_02 9
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_091_PM_GPIO_091 10
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_090 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_ONOFF_GPIO_090 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_RGMII_A_TXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_VEC_VSYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_RSVD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_UART_RTS_2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_RSVD_1     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_RSVD_2     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_CPU_TRACE_DATA10 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_TP_OUT_06  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_090_PM_GPIO_090 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_089 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_ONOFF_GPIO_089 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_RGMII_A_TXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_VEC_HSYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_TTX0_REQ   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_UART_CTS_2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_MTSIF0_DATA7 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_RSVD       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_CPU_TRACE_DATA9 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_TP_OUT_05  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_089_PM_GPIO_089 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_088 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_ONOFF_GPIO_088 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_RGMII_A_TXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_PKT_VALID1_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_TTX0_DATA  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_UART_TXD_2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_MTSIF0_DATA6 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_RSVD       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_CPU_TRACE_DATA8 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_TP_OUT_04  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_088_PM_GPIO_088 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_111 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_ONOFF_GPIO_111 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_UART_RXD_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_EXT_SC_CLK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_AUD_FS_CLK0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_SPI_S_SS0B 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_111_PM_GPIO_111 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_110 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_ONOFF_GPIO_110 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_UART_TXD_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_SC_CLK_OUT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_IR_INT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_SPI_S_MISO 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_110_PM_GPIO_110 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_097 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_ONOFF_GPIO_097 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_MII_A_COL  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_RSVD       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_SPI_M_SS1B 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_ENET0_ACTIVITY 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_RMX_PAUSE0_ALT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_UART_TXD_2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_PKT_SYNC2  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_TP_OUT_13  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_097_PM_GPIO_097 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_096 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_ONOFF_GPIO_096 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_MII_A_CRS  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_I2S_CLK0_OUT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_SPI_M_MISO 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_ENET0_LINK 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_RMX_VALID0_ALT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_UART_RXD_2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_PKT_DATA2  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_TP_OUT_08  8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_096_PM_GPIO_096 9
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_emmc_cmd_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_emmc_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_sf_wpb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_sf_holdb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_sf_mosi_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_sf_miso_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_sf_sck_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [17:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0003c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_pcie_clkreqb_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_clkreqb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_pcie_rstb_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_pcie_rstb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [09:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x000003ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_tsb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_rdb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_we0b_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_cs2b_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_cs1b_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_cs0b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_07_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_06_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_05_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_04_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_03_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_02_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_01_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_00_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_emmc_clk_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_080_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_080_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_079_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_079_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_065_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_064_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_063_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_062_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_061_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_061_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_060_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_059_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_058_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_011_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_011_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_ebi_nand_dqs_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_dqs_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_ebi_nand_wpb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_ebi_nand_rbb_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_ebi_dsb_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_095_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_095_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_094_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_093_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_093_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_092_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_092_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_091_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_091_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_090_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_090_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_089_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_089_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_088_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_088_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_087_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_087_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_086_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_085_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_085_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_084_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_084_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_083_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_083_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_082_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_082_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_081_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_081_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [31:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0xffffc000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_111_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_110_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_097_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_097_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_096_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_096_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_gpio_092 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_092_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_092_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_092_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_gpio_091 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_091_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_091_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_091_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_ir_in0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:21] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xffe00000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            21
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: mpm_reset [20:20] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_MASK             0x00100000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_SHIFT            20
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 19
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 18
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK  0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK  0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT  12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT     10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_SHIFT  31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_24_MASK   0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_24_SHIFT  24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK        0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT       16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_MASK         0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_SHIFT        5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK      0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT     11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_31_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_24_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_24_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_24_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffff800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            11
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK         0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT        7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_MASK       0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_SHIFT      6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_MASK           0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_SHIFT          3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK       0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT      1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffff800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          11
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK       0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK       0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT      7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_MASK         0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_SHIFT        3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffff800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         11
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_SHIFT  4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffff800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_SHIFT  3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffff800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffff800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffff800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 11
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_31_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffff800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 11
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: mpm_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hdmi_aon_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MPM_TOP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     19
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVS     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0    25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0  28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE0   36
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    39
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 41
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:06] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffffc0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           6
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [05:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000003f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MPM_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 32
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         4
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MPM_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 5
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xff800000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               23
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xffffffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             5
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UART_ROUTER_SEL_0 - UART Router select 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK    0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK    0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU    6
+
+/***************************************************************************
+ *UART_ROUTER_SEL_1 - UART Router select 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK   0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID    4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU   6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK   0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID    4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU   6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU    6
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU    6
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xfffc0000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        18
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_2 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_16 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_15 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_14 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_13 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_12 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_11 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_10 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_9 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_8 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_7 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_6 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_5 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_3 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_2 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_audio_2_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_flash_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_gphy_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_hevc_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_23 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_23_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_23_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_22 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_22_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_22_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_21 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_21_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_21_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_20 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_20_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_20_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_19 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_19_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_19_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_18 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_18_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_18_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_17 [01:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_17_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_17_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_17_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_2 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_16 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_15 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_14 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_13 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_12 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_11 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_10 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_9 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_8 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_7 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_6 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_5 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_3 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_2 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_audio_2_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_flash_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_gphy_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_hevc_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_23 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_23_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_23_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_22 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_22_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_22_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_21 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_21_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_21_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_20 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_20_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_20_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_19 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_19_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_19_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_18 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_18_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_18_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_17 [01:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_17_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_17_SHIFT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7250b0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..0ee8c1a9ad9e
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_usb_ctrl.h
@@ -0,0 +1,1524 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:51 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00490200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00490204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00490208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0049021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00490220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00490224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0049022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_USB_PM                     0x00490234 /* Power Management Register */
+#define BCHP_USB_CTRL_USB_PM_STATUS              0x00490238 /* usb20 Power Management Status Register */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT              0x0049023c /* OHCI ADDRESS Extension */
+#define BCHP_USB_CTRL_PLL_LDO_CTL                0x00490240 /* 28NM USBPHY LDO Control */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS            0x00490244 /* 28NM USBPHY PLLBIAS Control */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL            0x00490248 /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_AFE_USBIO_TST              0x0049024c /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC              0x00490250 /* PLL Feedback Divider Control Register */
+#define BCHP_USB_CTRL_TP_DIAG                    0x00490254 /* diagnostic for tp bus */
+#define BCHP_USB_CTRL_SPARE3                     0x00490258 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE4                     0x0049025c /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_USB30_CTL1                 0x00490260 /* USB30 CONTROL Register 1 */
+#define BCHP_USB_CTRL_USB30_CTL2                 0x00490264 /* USB30 CONTROL Register 2 */
+#define BCHP_USB_CTRL_USB30_CTL3                 0x00490268 /* USB30 CONTROL Register 3 */
+#define BCHP_USB_CTRL_USB30_CTL4                 0x0049026c /* USB30 CONTROL Register 4 */
+#define BCHP_USB_CTRL_USB30_PCTL                 0x00490270 /* USB30 PORT CONTROL Register */
+#define BCHP_USB_CTRL_USB30_CTL5                 0x00490274 /* USB30 CONTROL Register 5 */
+#define BCHP_USB_CTRL_SPARE5                     0x00490278 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE6                     0x0049027c /* Spare2 Register for future use */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE            0x004902a0 /* SCB0 base start and end address */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE            0x004902a4 /* SCB1 base start and end address */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE            0x004902a8 /* SCB2 base start and end address */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE            0x004902ac /* SCB0 extn start and end address */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE            0x004902b0 /* SCB1 extn start and end address */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE            0x004902b4 /* SCB2 extn start and end address */
+#define BCHP_USB_CTRL_USB_REVID                  0x004902fc /* USB REVID */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK                       0xc0000000
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT                      30
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0x30000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK                   0x08000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT                  27
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK                     0x04000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT                    26
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:20] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03f00000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      20
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK                    0x00080000
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT                   19
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                   0x00040000
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                  18
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK                   0x00020000
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT                  17
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT                0x00000001
+
+/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00010000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 16
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: scb2_en [15:15] */
+#define BCHP_USB_CTRL_SETUP_scb2_en_MASK                           0x00008000
+#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT                          15
+#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT                        0x00000000
+
+/* USB_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb0_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb0_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00001000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  12
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: setup_spare1 [11:10] */
+#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK                      0x00000c00
+#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT                     10
+#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000004
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x0000f000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000020
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0x7c000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSYS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_DEFAULT               0x0000298a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0xf0000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              28
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK          0x08000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT         27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK               0x01800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT              23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK            0x00600000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT           21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK                0x00080000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT               19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK            0x00040000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT           18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK            0x00020000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT           17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK                  0x00010000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                 16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT               0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK               0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT              8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0             0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1             1
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2             2
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3             3
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4             4
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5             5
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6             6
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7             7
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8             8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9             9
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10            10
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11            11
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12            12
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13            13
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14            14
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15            15
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17            17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18            18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19            19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23            23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24            24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25            25
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffc00
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                10
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK              0x00000200
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT             9
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ohci_memreq_disable [08:08] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_MASK          0x00000100
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_SHIFT         8
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [07:07] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK                0x00000080
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT               7
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK                  0x00000040
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT                 6
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT                5
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK                0x00000010
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT               4
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x0000000f
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK              0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT             21
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK                 0x80000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT                31
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK                 0x40000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT                30
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT                29
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0x1fffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK           0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT          27
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK              0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT             26
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK       0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT      25
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK        0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT       24
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT     0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host                  0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device                1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG                   2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10                  3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK              0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT             11
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT           0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK                 0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT                10
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK          0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT         9
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT       0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK           0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT          8
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host                     0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device                   1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG                      2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10                     3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB_PM - Power Management Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM :: xdc_soft_resetb [31:31] */
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT                 31
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_soft_resetb [30:30] */
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK                  0x40000000
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT                 30
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [29:29] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT                29
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [28:28] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK                 0x10000000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT                28
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [27:16] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK                    0x0fff0000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT                   16
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK            0x00008000
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT           15
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK            0x00004000
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT           14
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK                     0x00003fe0
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT                    5
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK                       0x00000010
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT                      4
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK                0x00000008
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT               3
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK                0x00000004
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT               2
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK                      0x00000002
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT                     1
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK                       0x00000001
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT                      0
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *USB_PM_STATUS - usb20 Power Management Status Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK               0xffff0000
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT              16
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK                 0x0000ffff
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT                0
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *OHCI_ADDR_EXT - OHCI ADDRESS Extension
+ ***************************************************************************/
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK           0xffffff00
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT          8
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK             0x000000ff
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT            0
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_LDO_CTL - 28NM USBPHY LDO Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK            0xffff0000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT           16
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT         0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK                0x0000f000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT               12
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK                0x00000f00
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT               8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK               0x000000f8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT              3
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK            0x00000004
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT           2
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT         0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK             0x00000002
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT            1
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT          0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK              0x00000001
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT             0
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK           0xfffc0000
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT          18
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK    0x0003ffff
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT   0
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK        0xfffe0000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT       17
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT     0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK             0x0001f000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT            12
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT          0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK     0x0000000f
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT    0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK           0x80000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT          31
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT        0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK                   0x40000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT                  30
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT                0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK       0x3fff0000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT      16
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT    0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK          0x0000ff00
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT         8
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT       0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK          0x000000ff
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT         0
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK      0xfff00000
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT     20
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT   0x00000000
+
+/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK             0x000fffff
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT            0
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TP_DIAG - diagnostic for tp bus
+ ***************************************************************************/
+/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK                    0xffffffff
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT                   0
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SPARE3 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE4 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB30_CTL1 - USB30 CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:22] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK            0xffc00000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT           22
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT      21
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK            0x00100000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT           20
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK                  0x00080000
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT                 19
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK                   0x00040000
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT                  18
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK                    0x00020000
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT                   17
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK                  0x00010000
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT                 16
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK            0x0000ff80
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT           7
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK          0x00000040
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT         6
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT                5
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK           0x00000010
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK          0x0000000e
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT         1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT       0x00000004
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk    0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL          1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N     2
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk   4
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK          0x00000001
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT         0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *USB30_CTL2 - USB30 CONTROL Register 2
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK            0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT         0x00000020
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK          0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT         16
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK          0x0000ff00
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT         8
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK            0x000000f8
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT           3
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK          0x00000004
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT         2
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_CTL3 - USB30 CONTROL Register 3
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK     0x20000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT    29
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK        0x1f000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT       24
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT     0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK        0x00f00000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT       20
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT     0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK           0x00080000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT          19
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK     0x00040000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT    18
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK         0x00020000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT        17
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT      0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK            0x00010000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK            0x0000c000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT           14
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK        0x00002000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT       13
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK           0x00001f00
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT          8
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT        0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK           0x000000f0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT        0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK              0x00000008
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT             3
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK        0x00000004
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT       2
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK            0x00000002
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT           1
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK               0x00000001
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT            0x00000001
+
+/***************************************************************************
+ *USB30_CTL4 - USB30 CONTROL Register 4
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK            0xff000000
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK               0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT              16
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_PCTL - USB30 PORT CONTROL Register
+ ***************************************************************************/
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK             0xe0000000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT            29
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK           0x10000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT          28
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT      21
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK       0x00100000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT      20
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK                 0x000c0000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT                18
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK      0x00010000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT     16
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK           0x00008000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT          15
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK             0x00006000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT            13
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK              0x00001000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT             12
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT           0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK    0x00000100
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT   8
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK    0x00000080
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT   7
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK    0x00000040
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT   6
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK          0x00000020
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT         5
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK          0x00000010
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT         4
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK                    0x0000000c
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT                   2
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK         0x00000001
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT        0
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT      0x00000000
+
+/***************************************************************************
+ *USB30_CTL5 - USB30 CONTROL Register 5
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK                   0xffffffff
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT                  0
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPARE5 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE6 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SCB0_BASE_RANGE - SCB0 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT   0x00000007
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCB1_BASE_RANGE - SCB1 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB2_BASE_RANGE - SCB2 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB0_EXTN_RANGE - SCB0 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT   0x00000017
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010
+
+/***************************************************************************
+ *SCB1_EXTN_RANGE - SCB1 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT   0x0000003b
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030
+
+/***************************************************************************
+ *SCB2_EXTN_RANGE - SCB2 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT   0x000000cb
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0
+
+/***************************************************************************
+ *USB_REVID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK                     0xffffffff
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT                    0
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT                  0x00000001
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_bus_if.h b/include/linux/brcmstb/7250b0/bchp_xpt_bus_if.h
new file mode 100644
index 000000000000..d117cdcae558
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_bus_if.h
@@ -0,0 +1,738 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:51 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_BUS_IF_H__
+#define BCHP_XPT_BUS_IF_H__
+
+/***************************************************************************
+ *XPT_BUS_IF - Data Transport Configuration Registers
+ ***************************************************************************/
+#define BCHP_XPT_BUS_IF_MISC_CTRL0               0x00a00080 /* Data Transport Misc Control 0 Register */
+#define BCHP_XPT_BUS_IF_TEST_MODE                0x00a00084 /* Data transport test register */
+#define BCHP_XPT_BUS_IF_REVISION                 0x00a00088 /* Data Transport Revision Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG          0x00a0008c /* Interrupt Status Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN       0x00a00090 /* Interrupt Status Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG         0x00a00094 /* Interrupt Status2 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN      0x00a00098 /* Interrupt Status2 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG         0x00a0009c /* Interrupt Status3 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN      0x00a000a0 /* Interrupt Status3 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG         0x00a000a4 /* Interrupt Status4 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN      0x00a000a8 /* Interrupt Status4 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG         0x00a000ac /* Interrupt Status5 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN      0x00a000b0 /* Interrupt Status5 Enable Register */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET 0x00a000b4 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR 0x00a000b8 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS 0x00a000bc /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT 0x00a000c0 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0 0x00a000cc /* LCIF to XMEMIF Debug Registers */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG   0x00a000d0 /* LCIF to XMEMIF Debug Registers */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS            0x00a000d4 /* Data Transport max number of playbacks supported */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS          0x00a000d8 /* Data Transport max number of PID parsers supported */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS         0x00a000dc /* Data Transport max number of PID channels supported excluding MEMDMA */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS  0x00a000e0 /* Data Transport max number of PID channels supported for MEMDMA */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS          0x00a000e4 /* Data Transport max number of input bands supported */
+#define BCHP_XPT_BUS_IF_MAX_PCRS                 0x00a000e8 /* Data Transport max number of PCRs supported */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS        0x00a000ec /* Data Transport max number of TPIT channels supported */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS        0x00a000f0 /* Data Transport max number of RAVE contexts supported */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS         0x00a000f4 /* Data Transport max number of RMX channels supported */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS          0x00a000f8 /* Data Transport max number of MSG buffers supported */
+#define BCHP_XPT_BUS_IF_MAX_SCDS                 0x00a000fc /* Data Transport max number of SCDs supported */
+
+/***************************************************************************
+ *MISC_CTRL0 - Data Transport Misc Control 0 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:07] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK                  0xffffff80
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT                 7
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: XPT_COUNTER_SCF [06:05] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_MASK            0x00000060
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_SHIFT           5
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_DEFAULT         0x00000001
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_108MHz          0
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_216MHz          1
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_270MHz          2
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_324MHz          3
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [04:03] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK                  0x00000018
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT                 3
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK        0x00000004
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT       2
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: MPOD_INT_TEST_MODE [01:01] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_MASK         0x00000002
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_SHIFT        1
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_DEFAULT      0x00000000
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE - Data transport test register
+ ***************************************************************************/
+/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK                   0xfffffffe
+#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT                  1
+
+/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK            0x00000001
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT           0
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *REVISION - Data Transport Revision Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: REVISION :: reserved0 [31:16] */
+#define BCHP_XPT_BUS_IF_REVISION_reserved0_MASK                    0xffff0000
+#define BCHP_XPT_BUS_IF_REVISION_reserved0_SHIFT                   16
+
+/* XPT_BUS_IF :: REVISION :: MAJOR_REV_NUMBER [15:08] */
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_MASK             0x0000ff00
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_SHIFT            8
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_DEFAULT          0x00000040
+
+/* XPT_BUS_IF :: REVISION :: MINOR_REV_NUMBER [07:00] */
+#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_MASK             0x000000ff
+#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_SHIFT            0
+
+/***************************************************************************
+ *INTR_STATUS_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_MASK             0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_SHIFT            28
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_TB_ERR_INTR [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_MASK    0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_SHIFT   27
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_PTR_OOR_INTR [26:26] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_MASK   0x04000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_SHIFT  26
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_PTR_OOR_INTR [25:25] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_MASK   0x02000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_SHIFT  25
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_OVERFLFLOW_INTR [24:24] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_MASK 0x01000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_SHIFT 24
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_OVERFLOW_INTR [23:23] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_MASK  0x00800000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_SHIFT 23
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved1 [22:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_MASK             0x007fffff
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_SHIFT            0
+
+/***************************************************************************
+ *INTR_STATUS_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_MASK          0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_SHIFT         28
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_TB_ERR_INTR_EN [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_MASK 0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_SHIFT 27
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_PTR_OOR_INTR_EN [26:26] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_MASK 0x04000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_SHIFT 26
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_PTR_OOR_INTR_EN [25:25] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_MASK 0x02000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_SHIFT 25
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_OVERFLFLOW_INTR_EN [24:24] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_MASK 0x01000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_SHIFT 24
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_OVERFLOW_INTR_EN [23:23] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_MASK 0x00800000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_SHIFT 23
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved1 [22:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_MASK          0x007fffff
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_SHIFT         0
+
+/***************************************************************************
+ *INTR_STATUS2_REG - Interrupt Status2 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: reserved0 [31:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_MASK            0xfffffff8
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_SHIFT           3
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CA_ERR_INT [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_MASK           0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_SHIFT          2
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_DEFAULT        0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_DEC_ERR_INT [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_MASK       0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_SHIFT      1
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_ENC_ERR_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_MASK       0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_SHIFT      0
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG_EN - Interrupt Status2 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: reserved0 [31:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_MASK         0xfffffff8
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_SHIFT        3
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CA_ERR_INT_EN [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_MASK     0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_SHIFT    2
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_DEFAULT  0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_DEC_ERR_INT_EN [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_SHIFT 1
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_ENC_ERR_INT_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS3_REG - Interrupt Status3 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS3_REG :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_MASK            0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_SHIFT           1
+
+/* XPT_BUS_IF :: INTR_STATUS3_REG :: MPOD_EXTRACTOR_CRC_ERROR [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS3_REG_EN - Interrupt Status3 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_MASK         0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_SHIFT        1
+
+/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: MPOD_EXTRACTOR_CRC_ERROR_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS4_REG - Interrupt Status4 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK            0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT           28
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK          0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT         27
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_DEFAULT       0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [26:16] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK            0x07ff0000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT           16
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB15_EOB_INT [15:15] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_MASK       0x00008000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_SHIFT      15
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB14_EOB_INT [14:14] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_MASK       0x00004000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_SHIFT      14
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB13_EOB_INT [13:13] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_MASK       0x00002000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_SHIFT      13
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB12_EOB_INT [12:12] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_MASK       0x00001000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_SHIFT      12
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB11_EOB_INT [11:11] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_MASK       0x00000800
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_SHIFT      11
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB10_EOB_INT [10:10] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_MASK       0x00000400
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_SHIFT      10
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB9_EOB_INT [09:09] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_MASK        0x00000200
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_SHIFT       9
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB8_EOB_INT [08:08] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_MASK        0x00000100
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_SHIFT       8
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB7_EOB_INT [07:07] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_MASK        0x00000080
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_SHIFT       7
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB6_EOB_INT [06:06] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_MASK        0x00000040
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_SHIFT       6
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB5_EOB_INT [05:05] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_MASK        0x00000020
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_SHIFT       5
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB4_EOB_INT [04:04] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_MASK        0x00000010
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_SHIFT       4
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB3_EOB_INT [03:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_MASK        0x00000008
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_SHIFT       3
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB2_EOB_INT [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_MASK        0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_SHIFT       2
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB1_EOB_INT [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_MASK        0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_SHIFT       1
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB0_EOB_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_MASK        0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_SHIFT       0
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK         0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT        28
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: GISB_BRIDGE_EN [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_MASK    0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_SHIFT   27
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [26:16] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK         0x07ff0000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT        16
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB15_EOB_INT_EN [15:15] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_MASK 0x00008000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_SHIFT 15
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB14_EOB_INT_EN [14:14] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_MASK 0x00004000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_SHIFT 14
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB13_EOB_INT_EN [13:13] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_MASK 0x00002000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_SHIFT 13
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB12_EOB_INT_EN [12:12] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_MASK 0x00001000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_SHIFT 12
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB11_EOB_INT_EN [11:11] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_MASK 0x00000800
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_SHIFT 11
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB10_EOB_INT_EN [10:10] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_MASK 0x00000400
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_SHIFT 10
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB9_EOB_INT_EN [09:09] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_MASK  0x00000200
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_SHIFT 9
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB8_EOB_INT_EN [08:08] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_MASK  0x00000100
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_SHIFT 8
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB7_EOB_INT_EN [07:07] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_MASK  0x00000080
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_SHIFT 7
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB6_EOB_INT_EN [06:06] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_MASK  0x00000040
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_SHIFT 6
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB5_EOB_INT_EN [05:05] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_MASK  0x00000020
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_SHIFT 5
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB4_EOB_INT_EN [04:04] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_MASK  0x00000010
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_SHIFT 4
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB3_EOB_INT_EN [03:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_MASK  0x00000008
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_SHIFT 3
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB2_EOB_INT_EN [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_MASK  0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_SHIFT 2
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB1_EOB_INT_EN [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_MASK  0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_SHIFT 1
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB0_EOB_INT_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_MASK  0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS5_REG - Interrupt Status5 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK            0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT           1
+
+/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK        0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT       0
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK         0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT        1
+
+/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: WRCHECKER_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_MASK     0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_SHIFT    0
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_SET - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_MASK    0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_SHIFT   2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: MEMDMA_MCPB_SOFT_INIT_SET [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: XPT_MCPB_SOFT_INIT_SET [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_CLEAR - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_MASK  0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: MEMDMA_MCPB_SOFT_INIT_CLEAR [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: XPT_MCPB_SOFT_INIT_CLEAR [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_STATUS - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: MEMDMA_MCPB_SOFT_INIT_STATUS [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: XPT_MCPB_SOFT_INIT_STATUS [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_DO_MEM_INIT - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_MASK 0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: XPT_MCPB_SOFT_INIT_DO_MEM_INIT [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *XMEMIF_RD_LC_DEBUG_REG_0 - LCIF to XMEMIF Debug Registers
+ ***************************************************************************/
+/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: reserved0 [31:16] */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_MASK    0xffff0000
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_SHIFT   16
+
+/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: PSUB_DEBUG_REG [15:00] */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_MASK 0x0000ffff
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_SHIFT 0
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_DEFAULT 0x00000000
+
+/***************************************************************************
+ *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
+ ***************************************************************************/
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK      0xffffffe0
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT     5
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RSBUFF_WR_DEBUG_REG [04:04] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_MASK 0x00000010
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_SHIFT 4
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: XCBUFF_WR_DEBUG_REG [03:03] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_MASK 0x00000008
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_SHIFT 3
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: MSG_DEBUG_REG [02:02] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_MASK  0x00000004
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_SHIFT 2
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MAX_PLAYBACKS - Data Transport max number of playbacks supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:06] */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK               0xffffffc0
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT              6
+
+/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [05:00] */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK           0x0000003f
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT          0
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_DEFAULT        0x00000020
+
+/***************************************************************************
+ *MAX_PID_PARSERS - Data Transport max number of PID parsers supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PID_PARSERS :: reserved0 [31:06] */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_MASK             0xffffffc0
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_SHIFT            6
+
+/* XPT_BUS_IF :: MAX_PID_PARSERS :: MAX_PID_PARSERS [05:00] */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_MASK       0x0000003f
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_DEFAULT    0x00000018
+
+/***************************************************************************
+ *MAX_PID_CHANNELS - Data Transport max number of PID channels supported excluding MEMDMA
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK            0xfffff000
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT           12
+
+/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK     0x00000fff
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT    0
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT  0x00000300
+
+/***************************************************************************
+ *MEMDMA_MAX_PID_CHANNELS - Data Transport max number of PID channels supported for MEMDMA
+ ***************************************************************************/
+/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: reserved0 [31:12] */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_MASK     0xfffff000
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_SHIFT    12
+
+/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT 0x00000400
+
+/***************************************************************************
+ *MAX_INPUT_BANDS - Data Transport max number of input bands supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_INPUT_BANDS :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_MASK             0xffffffe0
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_SHIFT            5
+
+/* XPT_BUS_IF :: MAX_INPUT_BANDS :: MAX_INPUT_BANDS [04:00] */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_MASK       0x0000001f
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_DEFAULT    0x0000000d
+
+/***************************************************************************
+ *MAX_PCRS - Data Transport max number of PCRs supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PCRS :: reserved0 [31:04] */
+#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_MASK                    0xfffffff0
+#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_SHIFT                   4
+
+/* XPT_BUS_IF :: MAX_PCRS :: MAX_PCRS [03:00] */
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_MASK                     0x0000000f
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_SHIFT                    0
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_DEFAULT                  0x0000000e
+
+/***************************************************************************
+ *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK           0xffffffe0
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT          5
+
+/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [04:00] */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK   0x0000001f
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT  0
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK           0xffffff00
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT          8
+
+/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK   0x000000ff
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT  0
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MAX_RMX_CHANNELS - Data Transport max number of RMX channels supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: reserved0 [31:04] */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_MASK            0xfffffff0
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_SHIFT           4
+
+/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: MAX_RMX_CHANNELS [03:00] */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_MASK     0x0000000f
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_SHIFT    0
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_DEFAULT  0x00000002
+
+/***************************************************************************
+ *MAX_MSG_BUFFERS - Data Transport max number of MSG buffers supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: reserved0 [31:09] */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_MASK             0xfffffe00
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_SHIFT            9
+
+/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: MAX_MSG_BUFFERS [08:00] */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_MASK       0x000001ff
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_DEFAULT    0x00000100
+
+/***************************************************************************
+ *MAX_SCDS - Data Transport max number of SCDs supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:09] */
+#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK                    0xfffffe00
+#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT                   9
+
+/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [08:00] */
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK                     0x000001ff
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT                    0
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_DEFAULT                  0x00000040
+
+#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_fe.h b/include/linux/brcmstb/7250b0/bchp_xpt_fe.h
new file mode 100644
index 000000000000..e818fcdde13b
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_fe.h
@@ -0,0 +1,12516 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:49 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_FE_H__
+#define BCHP_XPT_FE_H__
+
+/***************************************************************************
+ *XPT_FE - XPT FRONTEND Control Registers
+ ***************************************************************************/
+#define BCHP_XPT_FE_FE_CTRL                      0x00a20000 /* Data Transport Front-End Control Register */
+#define BCHP_XPT_FE_PWR_CTRL                     0x00a20004 /* Data Transport Front-End Power Control Register */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL              0x00a20008 /* Maximum Pid Channel number register */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL          0x00a2000c /* Data Transport Input Band Sync detect control */
+#define BCHP_XPT_FE_INTR_STATUS0_REG             0x00a20010 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS1_REG             0x00a20014 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS2_REG             0x00a20018 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN          0x00a20024 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN          0x00a20028 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN          0x00a2002c /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG        0x00a20038 /* TSMF Demultiplexer Interrupt Status Register */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN     0x00a2003c /* TSMF Demultiplexer Interrupt Status Enable Register */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG    0x00a20040 /* Interrupt Status Register */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN 0x00a20048 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG 0x00a20050 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG 0x00a20058 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG 0x00a20060 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN 0x00a20068 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN 0x00a20070 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN 0x00a20078 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL             0x00a200a0 /* FE_ATS_COUNTER_CTRL */
+#define BCHP_XPT_FE_ATS_TS_MOD300                0x00a200a4 /* FE_ATS_TS_MOD300 */
+#define BCHP_XPT_FE_ATS_TS_BINARY                0x00a200a8 /* FE_ATS_TS_BINARY */
+#define BCHP_XPT_FE_TV_STATUS_0                  0x00a200b0 /* TV Status_0 */
+#define BCHP_XPT_FE_TV_STATUS_1                  0x00a200b4 /* TV Status_1 */
+#define BCHP_XPT_FE_TV_STATUS_2                  0x00a200b8 /* TV Status_2 */
+#define BCHP_XPT_FE_TV_STATUS_3                  0x00a200bc /* TV Status_3 */
+#define BCHP_XPT_FE_TV_STATUS_4                  0x00a200c0 /* TV Status_4 */
+#define BCHP_XPT_FE_IB0_CTRL                     0x00a20100 /* Data Transport Input Band 0 Control Register */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT               0x00a20104 /* Data Transport Input Band 0 Sync counter Register */
+#define BCHP_XPT_FE_IB1_CTRL                     0x00a20108 /* Data Transport Input Band 1 Control Register */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT               0x00a2010c /* Data Transport Input Band 1 Sync counter Register */
+#define BCHP_XPT_FE_IB2_CTRL                     0x00a20110 /* Data Transport Input Band 2 Control Register */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT               0x00a20114 /* Data Transport Input Band 2 Sync counter Register */
+#define BCHP_XPT_FE_IB3_CTRL                     0x00a20118 /* Data Transport Input Band 3 Control Register */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT               0x00a2011c /* Data Transport Input Band 3 Sync counter Register */
+#define BCHP_XPT_FE_IB4_CTRL                     0x00a20120 /* Data Transport Input Band 4 Control Register */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT               0x00a20124 /* Data Transport Input Band 4 Sync counter Register */
+#define BCHP_XPT_FE_IB5_CTRL                     0x00a20128 /* Data Transport Input Band 5 Control Register */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT               0x00a2012c /* Data Transport Input Band 5 Sync counter Register */
+#define BCHP_XPT_FE_IB6_CTRL                     0x00a20130 /* Data Transport Input Band 6 Control Register */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT               0x00a20134 /* Data Transport Input Band 6 Sync counter Register */
+#define BCHP_XPT_FE_IB7_CTRL                     0x00a20138 /* Data Transport Input Band 7 Control Register */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT               0x00a2013c /* Data Transport Input Band 7 Sync counter Register */
+#define BCHP_XPT_FE_IB8_CTRL                     0x00a20140 /* Data Transport Input Band 8 Control Register */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT               0x00a20144 /* Data Transport Input Band 8 Sync counter Register */
+#define BCHP_XPT_FE_IB9_CTRL                     0x00a20148 /* Data Transport Input Band 9 Control Register */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT               0x00a2014c /* Data Transport Input Band 9 Sync counter Register */
+#define BCHP_XPT_FE_IB10_CTRL                    0x00a20150 /* Data Transport Input Band 10 Control Register */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT              0x00a20154 /* Data Transport Input Band 10 Sync counter Register */
+#define BCHP_XPT_FE_IB11_CTRL                    0x00a20158 /* Data Transport Input Band 11 Control Register */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT              0x00a2015c /* Data Transport Input Band 11 Sync counter Register */
+#define BCHP_XPT_FE_IB12_CTRL                    0x00a20160 /* Data Transport Input Band 12 Control Register */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT              0x00a20164 /* Data Transport Input Band 12 Sync counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1       0x00a20200 /* Data Transport Parser Band 0 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2       0x00a20204 /* Data Transport Parser Band 0 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL 0x00a20208 /* Data Transport Parser Band 0 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1       0x00a2020c /* Data Transport Parser Band 1 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2       0x00a20210 /* Data Transport Parser Band 1 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL 0x00a20214 /* Data Transport Parser Band 1 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1       0x00a20218 /* Data Transport Parser Band 2 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2       0x00a2021c /* Data Transport Parser Band 2 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL 0x00a20220 /* Data Transport Parser Band 2 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1       0x00a20224 /* Data Transport Parser Band 3 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2       0x00a20228 /* Data Transport Parser Band 3 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL 0x00a2022c /* Data Transport Parser Band 3 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1       0x00a20230 /* Data Transport Parser Band 4 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2       0x00a20234 /* Data Transport Parser Band 4 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL 0x00a20238 /* Data Transport Parser Band 4 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1       0x00a2023c /* Data Transport Parser Band 5 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2       0x00a20240 /* Data Transport Parser Band 5 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL 0x00a20244 /* Data Transport Parser Band 5 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1       0x00a20248 /* Data Transport Parser Band 6 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2       0x00a2024c /* Data Transport Parser Band 6 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL 0x00a20250 /* Data Transport Parser Band 6 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1       0x00a20254 /* Data Transport Parser Band 7 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2       0x00a20258 /* Data Transport Parser Band 7 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL 0x00a2025c /* Data Transport Parser Band 7 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1       0x00a20260 /* Data Transport Parser Band 8 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2       0x00a20264 /* Data Transport Parser Band 8 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL 0x00a20268 /* Data Transport Parser Band 8 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1       0x00a2026c /* Data Transport Parser Band 9 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2       0x00a20270 /* Data Transport Parser Band 9 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL 0x00a20274 /* Data Transport Parser Band 9 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1      0x00a20278 /* Data Transport Parser Band 10 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2      0x00a2027c /* Data Transport Parser Band 10 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL 0x00a20280 /* Data Transport Parser Band 10 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1      0x00a20284 /* Data Transport Parser Band 11 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2      0x00a20288 /* Data Transport Parser Band 11 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL 0x00a2028c /* Data Transport Parser Band 11 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1      0x00a20290 /* Data Transport Parser Band 12 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2      0x00a20294 /* Data Transport Parser Band 12 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL 0x00a20298 /* Data Transport Parser Band 12 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1      0x00a2029c /* Data Transport Parser Band 13 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2      0x00a202a0 /* Data Transport Parser Band 13 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL 0x00a202a4 /* Data Transport Parser Band 13 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1      0x00a202a8 /* Data Transport Parser Band 14 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2      0x00a202ac /* Data Transport Parser Band 14 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL 0x00a202b0 /* Data Transport Parser Band 14 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1      0x00a202b4 /* Data Transport Parser Band 15 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2      0x00a202b8 /* Data Transport Parser Band 15 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL 0x00a202bc /* Data Transport Parser Band 15 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1      0x00a202c0 /* Data Transport Parser Band 16 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2      0x00a202c4 /* Data Transport Parser Band 16 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL 0x00a202c8 /* Data Transport Parser Band 16 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1      0x00a202cc /* Data Transport Parser Band 17 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2      0x00a202d0 /* Data Transport Parser Band 17 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL 0x00a202d4 /* Data Transport Parser Band 17 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1      0x00a202d8 /* Data Transport Parser Band 18 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2      0x00a202dc /* Data Transport Parser Band 18 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL 0x00a202e0 /* Data Transport Parser Band 18 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1      0x00a202e4 /* Data Transport Parser Band 19 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2      0x00a202e8 /* Data Transport Parser Band 19 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL 0x00a202ec /* Data Transport Parser Band 19 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1      0x00a202f0 /* Data Transport Parser Band 20 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2      0x00a202f4 /* Data Transport Parser Band 20 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL 0x00a202f8 /* Data Transport Parser Band 20 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1      0x00a202fc /* Data Transport Parser Band 21 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2      0x00a20300 /* Data Transport Parser Band 21 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL 0x00a20304 /* Data Transport Parser Band 21 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1      0x00a20308 /* Data Transport Parser Band 22 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2      0x00a2030c /* Data Transport Parser Band 22 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL 0x00a20310 /* Data Transport Parser Band 22 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1      0x00a20314 /* Data Transport Parser Band 23 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2      0x00a20318 /* Data Transport Parser Band 23 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL 0x00a2031c /* Data Transport Parser Band 23 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID 0x00a20380 /* MINI PID PARSER0 to PARSER3 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID 0x00a20384 /* MINI PID PARSER4 to PARSER7 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID 0x00a20388 /* MINI PID PARSER8 to PARSER11 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID 0x00a2038c /* MINI PID PARSER12 to PARSER15 BAND ID */
+#define BCHP_XPT_FE_TSMF0_CTRL                   0x00a203a0 /* Data Transport TSMF Demultiplexer -- Control Register */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO            0x00a203a4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI            0x00a203a8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
+#define BCHP_XPT_FE_TSMF0_STATUS                 0x00a203ac /* Data Transport TSMF Demultiplexer -- Status Register */
+#define BCHP_XPT_FE_TSMF1_CTRL                   0x00a203b0 /* Data Transport TSMF Demultiplexer -- Control Register */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO            0x00a203b4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI            0x00a203b8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
+#define BCHP_XPT_FE_TSMF1_STATUS                 0x00a203bc /* Data Transport TSMF Demultiplexer -- Status Register */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1              0x00a204a0 /* FE_MTSIF_RX0_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD        0x00a204a4 /* MTSIF RX0 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP 0x00a204a8 /* MTSIF RX0 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID     0x00a204ac /* MTSIF RX0 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID     0x00a204b0 /* MTSIF RX0 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID    0x00a204b4 /* MTSIF RX0 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID   0x00a204b8 /* MTSIF RX0 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID   0x00a204bc /* MTSIF RX0 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID   0x00a204c0 /* MTSIF RX0 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID   0x00a204c4 /* MTSIF RX0 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID   0x00a204c8 /* MTSIF RX0 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID   0x00a204cc /* MTSIF RX0 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID   0x00a204d0 /* MTSIF RX0 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID   0x00a204d4 /* MTSIF RX0 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID   0x00a204d8 /* MTSIF RX0 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID   0x00a204dc /* MTSIF RX0 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID   0x00a204e0 /* MTSIF RX0 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID   0x00a204e4 /* MTSIF RX0 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID   0x00a204e8 /* MTSIF RX0 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT 0x00a204ec /* MTSIF RX0 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1              0x00a204f0 /* FE_MTSIF_RX1_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD        0x00a204f4 /* MTSIF RX1 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP 0x00a204f8 /* MTSIF RX1 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID     0x00a204fc /* MTSIF RX1 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID     0x00a20500 /* MTSIF RX1 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID    0x00a20504 /* MTSIF RX1 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID   0x00a20508 /* MTSIF RX1 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID   0x00a2050c /* MTSIF RX1 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID   0x00a20510 /* MTSIF RX1 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID   0x00a20514 /* MTSIF RX1 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID   0x00a20518 /* MTSIF RX1 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID   0x00a2051c /* MTSIF RX1 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID   0x00a20520 /* MTSIF RX1 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID   0x00a20524 /* MTSIF RX1 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID   0x00a20528 /* MTSIF RX1 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID   0x00a2052c /* MTSIF RX1 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID   0x00a20530 /* MTSIF RX1 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID   0x00a20534 /* MTSIF RX1 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID   0x00a20538 /* MTSIF RX1 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT 0x00a2053c /* MTSIF RX1 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1              0x00a20540 /* FE_MTSIF_RX2_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD        0x00a20544 /* MTSIF RX2 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP 0x00a20548 /* MTSIF RX2 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID     0x00a2054c /* MTSIF RX2 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID     0x00a20550 /* MTSIF RX2 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID    0x00a20554 /* MTSIF RX2 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID   0x00a20558 /* MTSIF RX2 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID   0x00a2055c /* MTSIF RX2 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID   0x00a20560 /* MTSIF RX2 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID   0x00a20564 /* MTSIF RX2 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID   0x00a20568 /* MTSIF RX2 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID   0x00a2056c /* MTSIF RX2 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID   0x00a20570 /* MTSIF RX2 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID   0x00a20574 /* MTSIF RX2 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID   0x00a20578 /* MTSIF RX2 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID   0x00a2057c /* MTSIF RX2 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID   0x00a20580 /* MTSIF RX2 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID   0x00a20584 /* MTSIF RX2 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID   0x00a20588 /* MTSIF RX2 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT 0x00a2058c /* MTSIF RX2 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1              0x00a20590 /* FE_MTSIF_RX3_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD        0x00a20594 /* MTSIF RX3 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP 0x00a20598 /* MTSIF RX3 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID     0x00a2059c /* MTSIF RX3 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID     0x00a205a0 /* MTSIF RX3 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID    0x00a205a4 /* MTSIF RX3 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID   0x00a205a8 /* MTSIF RX3 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID   0x00a205ac /* MTSIF RX3 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID   0x00a205b0 /* MTSIF RX3 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID   0x00a205b4 /* MTSIF RX3 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID   0x00a205b8 /* MTSIF RX3 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID   0x00a205bc /* MTSIF RX3 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID   0x00a205c0 /* MTSIF RX3 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID   0x00a205c4 /* MTSIF RX3 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID   0x00a205c8 /* MTSIF RX3 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID   0x00a205cc /* MTSIF RX3 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID   0x00a205d0 /* MTSIF RX3 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID   0x00a205d4 /* MTSIF RX3 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID   0x00a205d8 /* MTSIF RX3 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT 0x00a205dc /* MTSIF RX3 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1    0x00a20800 /* Data Transport Parser Band 0 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT  0x00a20804 /* Data Transport Parser Band 0 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1    0x00a20808 /* Data Transport Parser Band 1 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT  0x00a2080c /* Data Transport Parser Band 1 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1    0x00a20810 /* Data Transport Parser Band 2 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT  0x00a20814 /* Data Transport Parser Band 2 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1    0x00a20818 /* Data Transport Parser Band 3 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT  0x00a2081c /* Data Transport Parser Band 3 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1    0x00a20820 /* Data Transport Parser Band 4 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT  0x00a20824 /* Data Transport Parser Band 4 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1    0x00a20828 /* Data Transport Parser Band 5 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT  0x00a2082c /* Data Transport Parser Band 5 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1    0x00a20830 /* Data Transport Parser Band 6 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT  0x00a20834 /* Data Transport Parser Band 6 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1    0x00a20838 /* Data Transport Parser Band 7 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT  0x00a2083c /* Data Transport Parser Band 7 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1    0x00a20840 /* Data Transport Parser Band 8 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT  0x00a20844 /* Data Transport Parser Band 8 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1    0x00a20848 /* Data Transport Parser Band 9 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT  0x00a2084c /* Data Transport Parser Band 9 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1   0x00a20850 /* Data Transport Parser Band 10 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT 0x00a20854 /* Data Transport Parser Band 10 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1   0x00a20858 /* Data Transport Parser Band 11 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT 0x00a2085c /* Data Transport Parser Band 11 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1   0x00a20860 /* Data Transport Parser Band 12 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT 0x00a20864 /* Data Transport Parser Band 12 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1   0x00a20868 /* Data Transport Parser Band 13 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT 0x00a2086c /* Data Transport Parser Band 13 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1   0x00a20870 /* Data Transport Parser Band 14 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT 0x00a20874 /* Data Transport Parser Band 14 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1   0x00a20878 /* Data Transport Parser Band 15 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT 0x00a2087c /* Data Transport Parser Band 15 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1   0x00a20880 /* Data Transport Parser Band 16 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT 0x00a20884 /* Data Transport Parser Band 16 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1   0x00a20888 /* Data Transport Parser Band 17 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT 0x00a2088c /* Data Transport Parser Band 17 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1   0x00a20890 /* Data Transport Parser Band 18 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT 0x00a20894 /* Data Transport Parser Band 18 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1   0x00a20898 /* Data Transport Parser Band 19 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT 0x00a2089c /* Data Transport Parser Band 19 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1   0x00a208a0 /* Data Transport Parser Band 20 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT 0x00a208a4 /* Data Transport Parser Band 20 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1   0x00a208a8 /* Data Transport Parser Band 21 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT 0x00a208ac /* Data Transport Parser Band 21 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1   0x00a208b0 /* Data Transport Parser Band 22 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT 0x00a208b4 /* Data Transport Parser Band 22 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1   0x00a208b8 /* Data Transport Parser Band 23 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT 0x00a208bc /* Data Transport Parser Band 23 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1              0x00a20900 /* Transponder Bonding Global Control Register 1 */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG 0x00a2090c /* Parsers Private Data Length Error Status Register */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG 0x00a20910 /* Parsers Private Data Field Length Error Status Register */
+
+/***************************************************************************
+ *FE_CTRL - Data Transport Front-End Control Register
+ ***************************************************************************/
+/* XPT_FE :: FE_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_FE_CTRL_reserved0_MASK                         0xffffe000
+#define BCHP_XPT_FE_FE_CTRL_reserved0_SHIFT                        13
+
+/* XPT_FE :: FE_CTRL :: SW_CTRL_PID_VERSION_INCR_EN [12:12] */
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_MASK       0x00001000
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_SHIFT      12
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: FE_CTRL :: reserved1 [11:09] */
+#define BCHP_XPT_FE_FE_CTRL_reserved1_MASK                         0x00000e00
+#define BCHP_XPT_FE_FE_CTRL_reserved1_SHIFT                        9
+
+/* XPT_FE :: FE_CTRL :: SPARE_FUNC [08:02] */
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_MASK                        0x000001fc
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_SHIFT                       2
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_DEFAULT                     0x00000000
+
+/* XPT_FE :: FE_CTRL :: MPOD_OP_PSUB_NULL_PKT_EN [01:01] */
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_MASK          0x00000002
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_SHIFT         1
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_DEFAULT       0x00000000
+
+/* XPT_FE :: FE_CTRL :: ERROR_INT_TEST_MODE [00:00] */
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_MASK               0x00000001
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_SHIFT              0
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PWR_CTRL - Data Transport Front-End Power Control Register
+ ***************************************************************************/
+/* XPT_FE :: PWR_CTRL :: reserved0 [31:01] */
+#define BCHP_XPT_FE_PWR_CTRL_reserved0_MASK                        0xfffffffe
+#define BCHP_XPT_FE_PWR_CTRL_reserved0_SHIFT                       1
+
+/* XPT_FE :: PWR_CTRL :: FE_TIMESTAMP_DIS [00:00] */
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_MASK                 0x00000001
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_SHIFT                0
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MAX_PID_CHANNEL - Maximum Pid Channel number register
+ ***************************************************************************/
+/* XPT_FE :: MAX_PID_CHANNEL :: reserved0 [31:12] */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_MASK                 0xfffff000
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_SHIFT                12
+
+/* XPT_FE :: MAX_PID_CHANNEL :: MAX_PID_CHANNEL [11:00] */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_MASK           0x00000fff
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_SHIFT          0
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_DEFAULT        0x000003ff
+
+/***************************************************************************
+ *IB_SYNC_DETECT_CTRL - Data Transport Input Band Sync detect control
+ ***************************************************************************/
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: reserved0 [31:06] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_MASK             0xffffffc0
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_SHIFT            6
+
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_OUT_CNT [05:03] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_MASK       0x00000038
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_SHIFT      3
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_DEFAULT    0x00000000
+
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_IN_CNT [02:00] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_MASK        0x00000007
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_SHIFT       0
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER31_LENGTH_ERROR [31:31] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_MASK    0x80000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_SHIFT   31
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER30_LENGTH_ERROR [30:30] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_MASK    0x40000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_SHIFT   30
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER29_LENGTH_ERROR [29:29] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_MASK    0x20000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_SHIFT   29
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER28_LENGTH_ERROR [28:28] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_MASK    0x10000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_SHIFT   28
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER27_LENGTH_ERROR [27:27] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_MASK    0x08000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_SHIFT   27
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER26_LENGTH_ERROR [26:26] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_MASK    0x04000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_SHIFT   26
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER25_LENGTH_ERROR [25:25] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_MASK    0x02000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_SHIFT   25
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER24_LENGTH_ERROR [24:24] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_MASK    0x01000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_SHIFT   24
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER23_LENGTH_ERROR [23:23] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_MASK    0x00800000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_SHIFT   23
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER22_LENGTH_ERROR [22:22] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_MASK    0x00400000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_SHIFT   22
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER21_LENGTH_ERROR [21:21] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_MASK    0x00200000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_SHIFT   21
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER20_LENGTH_ERROR [20:20] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_MASK    0x00100000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_SHIFT   20
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER19_LENGTH_ERROR [19:19] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_MASK    0x00080000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_SHIFT   19
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER18_LENGTH_ERROR [18:18] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_MASK    0x00040000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_SHIFT   18
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER17_LENGTH_ERROR [17:17] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_MASK    0x00020000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_SHIFT   17
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER16_LENGTH_ERROR [16:16] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_MASK    0x00010000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_SHIFT   16
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER15_LENGTH_ERROR [15:15] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_MASK    0x00008000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_SHIFT   15
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER14_LENGTH_ERROR [14:14] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_MASK    0x00004000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_SHIFT   14
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER13_LENGTH_ERROR [13:13] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_MASK    0x00002000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_SHIFT   13
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER12_LENGTH_ERROR [12:12] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_MASK    0x00001000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_SHIFT   12
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER11_LENGTH_ERROR [11:11] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_MASK    0x00000800
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_SHIFT   11
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER10_LENGTH_ERROR [10:10] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_MASK    0x00000400
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_SHIFT   10
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER9_LENGTH_ERROR [09:09] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_MASK     0x00000200
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_SHIFT    9
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER8_LENGTH_ERROR [08:08] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_MASK     0x00000100
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_SHIFT    8
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER7_LENGTH_ERROR [07:07] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_MASK     0x00000080
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_SHIFT    7
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER6_LENGTH_ERROR [06:06] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_MASK     0x00000040
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_SHIFT    6
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER5_LENGTH_ERROR [05:05] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_MASK     0x00000020
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_SHIFT    5
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER4_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_MASK     0x00000010
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_SHIFT    4
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER3_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_MASK     0x00000008
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_SHIFT    3
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER2_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_MASK     0x00000004
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_SHIFT    2
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER1_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_MASK     0x00000002
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_SHIFT    1
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER0_LENGTH_ERROR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_MASK     0x00000001
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_SHIFT    0
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_DEFAULT  0x00000000
+
+/***************************************************************************
+ *INTR_STATUS1_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER31_TRANSPORT_ERROR [31:31] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_SHIFT 31
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER30_TRANSPORT_ERROR [30:30] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_SHIFT 30
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER29_TRANSPORT_ERROR [29:29] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_SHIFT 29
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER28_TRANSPORT_ERROR [28:28] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_SHIFT 28
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER27_TRANSPORT_ERROR [27:27] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_SHIFT 27
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER26_TRANSPORT_ERROR [26:26] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_SHIFT 26
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER25_TRANSPORT_ERROR [25:25] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_SHIFT 25
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER24_TRANSPORT_ERROR [24:24] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_SHIFT 24
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER23_TRANSPORT_ERROR [23:23] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_SHIFT 23
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER22_TRANSPORT_ERROR [22:22] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_SHIFT 22
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER21_TRANSPORT_ERROR [21:21] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_SHIFT 21
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER20_TRANSPORT_ERROR [20:20] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_SHIFT 20
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER19_TRANSPORT_ERROR [19:19] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_SHIFT 19
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER18_TRANSPORT_ERROR [18:18] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_SHIFT 18
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER17_TRANSPORT_ERROR [17:17] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_SHIFT 17
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER16_TRANSPORT_ERROR [16:16] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_SHIFT 16
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER15_TRANSPORT_ERROR [15:15] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_SHIFT 15
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER14_TRANSPORT_ERROR [14:14] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_SHIFT 14
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER13_TRANSPORT_ERROR [13:13] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_SHIFT 13
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER12_TRANSPORT_ERROR [12:12] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_SHIFT 12
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER11_TRANSPORT_ERROR [11:11] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_SHIFT 11
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER10_TRANSPORT_ERROR [10:10] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_SHIFT 10
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER9_TRANSPORT_ERROR [09:09] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_MASK  0x00000200
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_SHIFT 9
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER8_TRANSPORT_ERROR [08:08] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_MASK  0x00000100
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_SHIFT 8
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER7_TRANSPORT_ERROR [07:07] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_MASK  0x00000080
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_SHIFT 7
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER6_TRANSPORT_ERROR [06:06] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_MASK  0x00000040
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_SHIFT 6
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER5_TRANSPORT_ERROR [05:05] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_MASK  0x00000020
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_SHIFT 5
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER4_TRANSPORT_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_MASK  0x00000010
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_SHIFT 4
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER3_TRANSPORT_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_MASK  0x00000008
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_SHIFT 3
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER2_TRANSPORT_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_MASK  0x00000004
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_SHIFT 2
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER1_TRANSPORT_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_MASK  0x00000002
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_SHIFT 1
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER0_TRANSPORT_ERROR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_MASK  0x00000001
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_SHIFT 0
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS2_REG :: reserved0 [31:05] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_MASK                0xffffffe0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_SHIFT               5
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 4
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 3
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 2
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 1
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: INPUT_BUFFER_OVFL_ERR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_MASK    0x00000001
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_SHIFT   0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK   0xffffffff
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS1_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS1_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_MASK   0xffffffff
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS2_REG_EN :: reserved0 [31:05] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_MASK             0xffffffe0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_SHIFT            5
+
+/* XPT_FE :: INTR_STATUS2_REG_EN :: INTR_STATUS2_REG_EN [04:00] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_MASK   0x0000001f
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TSMF_INTR_STATUS0_REG - TSMF Demultiplexer Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_SYNC_ERROR_EN [31:31] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_MASK 0x80000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_SHIFT 31
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_SYNC_ERROR_EN [30:30] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_MASK 0x40000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_SHIFT 30
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_SYNC_ERROR_EN [29:29] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_MASK 0x20000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_SHIFT 29
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_SYNC_ERROR_EN [28:28] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_MASK 0x10000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_SHIFT 28
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_SYNC_ERROR_EN [27:27] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_MASK 0x08000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_SHIFT 27
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_SYNC_ERROR_EN [26:26] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_MASK 0x04000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_SHIFT 26
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_SYNC_ERROR_EN [25:25] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_MASK 0x02000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_SHIFT 25
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_SYNC_ERROR_EN [24:24] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_MASK 0x01000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_SHIFT 24
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_SYNC_ERROR_EN [23:23] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_MASK 0x00800000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_SHIFT 23
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_SYNC_ERROR_EN [22:22] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_MASK 0x00400000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_SHIFT 22
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_SYNC_ERROR_EN [21:21] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_MASK 0x00200000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_SHIFT 21
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_SYNC_ERROR_EN [20:20] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_MASK 0x00100000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_SHIFT 20
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_SYNC_ERROR_EN [19:19] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_MASK 0x00080000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_SHIFT 19
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_SYNC_ERROR_EN [18:18] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_MASK 0x00040000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_SHIFT 18
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_SYNC_ERROR_EN [17:17] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_MASK 0x00020000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_SHIFT 17
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_SYNC_ERROR_EN [16:16] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_MASK 0x00010000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_SHIFT 16
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_FRAME_ERROR [15:15] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_MASK  0x00008000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_SHIFT 15
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_FRAME_ERROR [14:14] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_MASK  0x00004000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_SHIFT 14
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_FRAME_ERROR [13:13] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_MASK  0x00002000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_SHIFT 13
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_FRAME_ERROR [12:12] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_MASK  0x00001000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_SHIFT 12
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_FRAME_ERROR [11:11] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_MASK  0x00000800
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_SHIFT 11
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_FRAME_ERROR [10:10] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_MASK  0x00000400
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_SHIFT 10
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_FRAME_ERROR [09:09] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_MASK   0x00000200
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_SHIFT  9
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_FRAME_ERROR [08:08] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_MASK   0x00000100
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_SHIFT  8
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_FRAME_ERROR [07:07] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_MASK   0x00000080
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_SHIFT  7
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_FRAME_ERROR [06:06] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_MASK   0x00000040
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_SHIFT  6
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_FRAME_ERROR [05:05] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_MASK   0x00000020
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_SHIFT  5
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_FRAME_ERROR [04:04] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_MASK   0x00000010
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_SHIFT  4
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_FRAME_ERROR [03:03] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_MASK   0x00000008
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_SHIFT  3
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_FRAME_ERROR [02:02] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_MASK   0x00000004
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_SHIFT  2
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_FRAME_ERROR [01:01] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_MASK   0x00000002
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_SHIFT  1
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_FRAME_ERROR [00:00] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_MASK   0x00000001
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_SHIFT  0
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TSMF_INTR_STATUS0_REG_EN - TSMF Demultiplexer Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF_INTR_STATUS0_REG_EN :: INTR_STATUS1_REG_EN [31:00] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER31_LENGTH_MISMATCH [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER30_LENGTH_MISMATCH [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER29_LENGTH_MISMATCH [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER28_LENGTH_MISMATCH [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER27_LENGTH_MISMATCH [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER26_LENGTH_MISMATCH [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER25_LENGTH_MISMATCH [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER24_LENGTH_MISMATCH [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER23_LENGTH_MISMATCH [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER22_LENGTH_MISMATCH [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER21_LENGTH_MISMATCH [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER20_LENGTH_MISMATCH [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER19_LENGTH_MISMATCH [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER18_LENGTH_MISMATCH [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER17_LENGTH_MISMATCH [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER16_LENGTH_MISMATCH [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER15_LENGTH_MISMATCH [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER14_LENGTH_MISMATCH [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER13_LENGTH_MISMATCH [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER12_LENGTH_MISMATCH [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER11_LENGTH_MISMATCH [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER10_LENGTH_MISMATCH [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER9_LENGTH_MISMATCH [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER8_LENGTH_MISMATCH [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER7_LENGTH_MISMATCH [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER6_LENGTH_MISMATCH [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER5_LENGTH_MISMATCH [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER4_LENGTH_MISMATCH [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER3_LENGTH_MISMATCH [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER2_LENGTH_MISMATCH [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER1_LENGTH_MISMATCH [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER0_LENGTH_MISMATCH [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_FRAME_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_FRAME_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_FRAME_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_FRAME_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_FRAME_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_FRAME_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_FRAME_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_FRAME_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_FRAME_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_FRAME_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_FRAME_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_FRAME_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_FRAME_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_FRAME_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_FRAME_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_FRAME_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_FRAME_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_FRAME_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_FRAME_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_FRAME_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_FRAME_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_FRAME_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_FRAME_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_FRAME_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_FRAME_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_FRAME_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_FRAME_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_FRAME_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_FRAME_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_FRAME_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_FRAME_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_FRAME_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_SYNC_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_SYNC_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_SYNC_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_SYNC_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_SYNC_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_SYNC_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_SYNC_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_SYNC_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_SYNC_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_SYNC_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_SYNC_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_SYNC_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_SYNC_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_SYNC_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_SYNC_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_SYNC_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_SYNC_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_SYNC_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_SYNC_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_SYNC_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_SYNC_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_SYNC_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_SYNC_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_SYNC_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_SYNC_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_SYNC_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_SYNC_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_SYNC_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_SYNC_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_SYNC_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_SYNC_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_SYNC_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER31_INBUFF_OVFL_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER30_INBUFF_OVFL_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER29_INBUFF_OVFL_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER28_INBUFF_OVFL_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER27_INBUFF_OVFL_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER26_INBUFF_OVFL_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER25_INBUFF_OVFL_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER24_INBUFF_OVFL_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER23_INBUFF_OVFL_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER22_INBUFF_OVFL_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER21_INBUFF_OVFL_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER20_INBUFF_OVFL_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER19_INBUFF_OVFL_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER18_INBUFF_OVFL_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER17_INBUFF_OVFL_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER16_INBUFF_OVFL_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER15_INBUFF_OVFL_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER14_INBUFF_OVFL_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER13_INBUFF_OVFL_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER12_INBUFF_OVFL_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER11_INBUFF_OVFL_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER10_INBUFF_OVFL_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER9_INBUFF_OVFL_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER8_INBUFF_OVFL_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER7_INBUFF_OVFL_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER6_INBUFF_OVFL_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER5_INBUFF_OVFL_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER4_INBUFF_OVFL_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER3_INBUFF_OVFL_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER2_INBUFF_OVFL_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER1_INBUFF_OVFL_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER0_INBUFF_OVFL_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ATS_COUNTER_CTRL - FE_ATS_COUNTER_CTRL
+ ***************************************************************************/
+/* XPT_FE :: ATS_COUNTER_CTRL :: reserved0 [31:25] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_MASK                0xfe000000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_SHIFT               25
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: EXT_RESET_ENABLE [24:24] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_MASK         0x01000000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_SHIFT        24
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_DEFAULT      0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: COUNT_RESET [23:23] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_MASK              0x00800000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_SHIFT             23
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_DEFAULT           0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: INC_MUX_SEL [22:22] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_MASK              0x00400000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_SHIFT             22
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_DEFAULT           0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_MASK         0x00200000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_SHIFT        21
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_DEFAULT      0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_MASK           0x00100000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_SHIFT          20
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_MASK        0x000fffff
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_SHIFT       0
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *ATS_TS_MOD300 - FE_ATS_TS_MOD300
+ ***************************************************************************/
+/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_UPPER [31:09] */
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_MASK             0xfffffe00
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_SHIFT            9
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_DEFAULT          0x00000000
+
+/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_LOWER [08:00] */
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_MASK             0x000001ff
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_SHIFT            0
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_DEFAULT          0x00000000
+
+/***************************************************************************
+ *ATS_TS_BINARY - FE_ATS_TS_BINARY
+ ***************************************************************************/
+/* XPT_FE :: ATS_TS_BINARY :: TS_BINARY_COUNTER [31:00] */
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_MASK           0xffffffff
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_SHIFT          0
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TV_STATUS_0 - TV Status_0
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_0 :: INPUT3_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_MASK                    0xff000000
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_SHIFT                   24
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT2_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_MASK                    0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_SHIFT                   16
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT1_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT0_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_1 - TV Status_1
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_1 :: INPUT7_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_MASK                    0xff000000
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_SHIFT                   24
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT6_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_MASK                    0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_SHIFT                   16
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT5_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT4_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_2 - TV Status_2
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_2 :: INPUT11_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_MASK                   0xff000000
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_SHIFT                  24
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT10_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_MASK                   0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_SHIFT                  16
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT9_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT8_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_3 - TV Status_3
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_3 :: INPUT15_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_MASK                   0xff000000
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_SHIFT                  24
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT14_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_MASK                   0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_SHIFT                  16
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT13_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_MASK                   0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_SHIFT                  8
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT12_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_MASK                   0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_SHIFT                  0
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TV_STATUS_4 - TV Status_4
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX3_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_MASK                 0xff000000
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_SHIFT                24
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX2_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_MASK                 0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_SHIFT                16
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX1_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_MASK                 0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_SHIFT                8
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX0_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_MASK                 0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_SHIFT                0
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB0_CTRL - Data Transport Input Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB0_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB0_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB0_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB0_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB0_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB0_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB0_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB0_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB0_SYNC_COUNT - Data Transport Input Band 0 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB0_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB0_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB1_CTRL - Data Transport Input Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB1_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB1_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB1_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB1_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB1_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB1_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB1_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB1_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB1_SYNC_COUNT - Data Transport Input Band 1 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB1_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB1_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB2_CTRL - Data Transport Input Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB2_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB2_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB2_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB2_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB2_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB2_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB2_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB2_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB2_SYNC_COUNT - Data Transport Input Band 2 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB2_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB2_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB3_CTRL - Data Transport Input Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB3_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB3_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB3_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB3_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB3_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB3_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB3_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB3_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB3_SYNC_COUNT - Data Transport Input Band 3 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB3_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB3_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB4_CTRL - Data Transport Input Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB4_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB4_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB4_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB4_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB4_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB4_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB4_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB4_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB4_SYNC_COUNT - Data Transport Input Band 4 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB4_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB4_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB5_CTRL - Data Transport Input Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB5_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB5_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB5_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB5_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB5_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB5_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB5_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB5_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB5_SYNC_COUNT - Data Transport Input Band 5 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB5_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB5_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB6_CTRL - Data Transport Input Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB6_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB6_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB6_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB6_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB6_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB6_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB6_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB6_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB6_SYNC_COUNT - Data Transport Input Band 6 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB6_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB6_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB7_CTRL - Data Transport Input Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB7_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB7_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB7_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB7_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB7_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB7_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB7_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB7_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB7_SYNC_COUNT - Data Transport Input Band 7 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB7_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB7_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB8_CTRL - Data Transport Input Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB8_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB8_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB8_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB8_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB8_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB8_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB8_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB8_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB8_SYNC_COUNT - Data Transport Input Band 8 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB8_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB8_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB9_CTRL - Data Transport Input Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB9_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB9_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB9_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB9_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB9_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB9_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB9_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB9_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB9_SYNC_COUNT - Data Transport Input Band 9 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB9_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB9_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB10_CTRL - Data Transport Input Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB10_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB10_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB10_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB10_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB10_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB10_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB10_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB10_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB10_SYNC_COUNT - Data Transport Input Band 10 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB10_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB10_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB11_CTRL - Data Transport Input Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB11_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB11_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB11_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB11_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB11_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB11_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB11_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB11_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB11_SYNC_COUNT - Data Transport Input Band 11 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB11_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB11_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB12_CTRL - Data Transport Input Band 12 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB12_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB12_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB12_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB12_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB12_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB12_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB12_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB12_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB12_SYNC_COUNT - Data Transport Input Band 12 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB12_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB12_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_CTRL1 - Data Transport Parser Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_CTRL2 - Data Transport Parser Band 0 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_ALL_PASS_CTRL - Data Transport Parser Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_CTRL1 - Data Transport Parser Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_CTRL2 - Data Transport Parser Band 1 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_ALL_PASS_CTRL - Data Transport Parser Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MINI_PID_PARSER2_CTRL1 - Data Transport Parser Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_CTRL2 - Data Transport Parser Band 2 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_ALL_PASS_CTRL - Data Transport Parser Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000002
+
+/***************************************************************************
+ *MINI_PID_PARSER3_CTRL1 - Data Transport Parser Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_CTRL2 - Data Transport Parser Band 3 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_ALL_PASS_CTRL - Data Transport Parser Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000003
+
+/***************************************************************************
+ *MINI_PID_PARSER4_CTRL1 - Data Transport Parser Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_CTRL2 - Data Transport Parser Band 4 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_ALL_PASS_CTRL - Data Transport Parser Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MINI_PID_PARSER5_CTRL1 - Data Transport Parser Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_CTRL2 - Data Transport Parser Band 5 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_ALL_PASS_CTRL - Data Transport Parser Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000005
+
+/***************************************************************************
+ *MINI_PID_PARSER6_CTRL1 - Data Transport Parser Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_CTRL2 - Data Transport Parser Band 6 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_ALL_PASS_CTRL - Data Transport Parser Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000006
+
+/***************************************************************************
+ *MINI_PID_PARSER7_CTRL1 - Data Transport Parser Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_CTRL2 - Data Transport Parser Band 7 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_ALL_PASS_CTRL - Data Transport Parser Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000007
+
+/***************************************************************************
+ *MINI_PID_PARSER8_CTRL1 - Data Transport Parser Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_CTRL2 - Data Transport Parser Band 8 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_ALL_PASS_CTRL - Data Transport Parser Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MINI_PID_PARSER9_CTRL1 - Data Transport Parser Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_CTRL2 - Data Transport Parser Band 9 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_ALL_PASS_CTRL - Data Transport Parser Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000009
+
+/***************************************************************************
+ *MINI_PID_PARSER10_CTRL1 - Data Transport Parser Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_CTRL2 - Data Transport Parser Band 10 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_ALL_PASS_CTRL - Data Transport Parser Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000a
+
+/***************************************************************************
+ *MINI_PID_PARSER11_CTRL1 - Data Transport Parser Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_CTRL2 - Data Transport Parser Band 11 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_ALL_PASS_CTRL - Data Transport Parser Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000b
+
+/***************************************************************************
+ *MINI_PID_PARSER12_CTRL1 - Data Transport Parser Band 12 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER12_CTRL2 - Data Transport Parser Band 12 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER12_ALL_PASS_CTRL - Data Transport Parser Band 12 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *MINI_PID_PARSER13_CTRL1 - Data Transport Parser Band 13 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER13_CTRL2 - Data Transport Parser Band 13 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER13_ALL_PASS_CTRL - Data Transport Parser Band 13 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000d
+
+/***************************************************************************
+ *MINI_PID_PARSER14_CTRL1 - Data Transport Parser Band 14 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER14_CTRL2 - Data Transport Parser Band 14 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER14_ALL_PASS_CTRL - Data Transport Parser Band 14 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000e
+
+/***************************************************************************
+ *MINI_PID_PARSER15_CTRL1 - Data Transport Parser Band 15 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER15_CTRL2 - Data Transport Parser Band 15 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER15_ALL_PASS_CTRL - Data Transport Parser Band 15 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000f
+
+/***************************************************************************
+ *MINI_PID_PARSER16_CTRL1 - Data Transport Parser Band 16 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER16_CTRL2 - Data Transport Parser Band 16 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER16_ALL_PASS_CTRL - Data Transport Parser Band 16 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MINI_PID_PARSER17_CTRL1 - Data Transport Parser Band 17 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER17_CTRL2 - Data Transport Parser Band 17 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER17_ALL_PASS_CTRL - Data Transport Parser Band 17 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000011
+
+/***************************************************************************
+ *MINI_PID_PARSER18_CTRL1 - Data Transport Parser Band 18 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER18_CTRL2 - Data Transport Parser Band 18 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER18_ALL_PASS_CTRL - Data Transport Parser Band 18 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000012
+
+/***************************************************************************
+ *MINI_PID_PARSER19_CTRL1 - Data Transport Parser Band 19 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER19_CTRL2 - Data Transport Parser Band 19 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER19_ALL_PASS_CTRL - Data Transport Parser Band 19 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000013
+
+/***************************************************************************
+ *MINI_PID_PARSER20_CTRL1 - Data Transport Parser Band 20 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER20_CTRL2 - Data Transport Parser Band 20 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER20_ALL_PASS_CTRL - Data Transport Parser Band 20 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MINI_PID_PARSER21_CTRL1 - Data Transport Parser Band 21 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER21_CTRL2 - Data Transport Parser Band 21 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER21_ALL_PASS_CTRL - Data Transport Parser Band 21 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000015
+
+/***************************************************************************
+ *MINI_PID_PARSER22_CTRL1 - Data Transport Parser Band 22 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER22_CTRL2 - Data Transport Parser Band 22 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER22_ALL_PASS_CTRL - Data Transport Parser Band 22 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000016
+
+/***************************************************************************
+ *MINI_PID_PARSER23_CTRL1 - Data Transport Parser Band 23 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER23_CTRL2 - Data Transport Parser Band 23 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER23_ALL_PASS_CTRL - Data Transport Parser Band 23 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000017
+
+/***************************************************************************
+ *MINI_PID_PARSER0_TO_PARSER3_BAND_ID - MINI PID PARSER0 to PARSER3 BAND ID
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER3_PARSER_SEL [31:31] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_MASK 0x80000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_SHIFT 31
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved0 [30:30] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved0_MASK 0x40000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved0_SHIFT 30
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER3_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER3_BAND_ID_DEFAULT 0x00000003
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER2_PARSER_SEL [23:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_MASK 0x00800000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_SHIFT 23
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved1 [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved1_MASK 0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved1_SHIFT 22
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER2_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER2_BAND_ID_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER1_PARSER_SEL [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_MASK 0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_SHIFT 15
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved2 [14:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved2_MASK 0x00004000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved2_SHIFT 14
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER1_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER1_BAND_ID_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER0_PARSER_SEL [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_MASK 0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_SHIFT 7
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: reserved3 [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved3_MASK 0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_reserved3_SHIFT 6
+
+/* XPT_FE :: MINI_PID_PARSER0_TO_PARSER3_BAND_ID :: PARSER0_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID_PARSER0_BAND_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_TO_PARSER7_BAND_ID - MINI PID PARSER4 to PARSER7 BAND ID
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER7_PARSER_SEL [31:31] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_MASK 0x80000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_SHIFT 31
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved0 [30:30] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved0_MASK 0x40000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved0_SHIFT 30
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER7_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER7_BAND_ID_DEFAULT 0x00000007
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER6_PARSER_SEL [23:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_MASK 0x00800000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_SHIFT 23
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved1 [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved1_MASK 0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved1_SHIFT 22
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER6_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER6_BAND_ID_DEFAULT 0x00000006
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER5_PARSER_SEL [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_MASK 0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_SHIFT 15
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved2 [14:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved2_MASK 0x00004000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved2_SHIFT 14
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER5_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER5_BAND_ID_DEFAULT 0x00000005
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER4_PARSER_SEL [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_MASK 0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_SHIFT 7
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: reserved3 [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved3_MASK 0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_reserved3_SHIFT 6
+
+/* XPT_FE :: MINI_PID_PARSER4_TO_PARSER7_BAND_ID :: PARSER4_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID_PARSER4_BAND_ID_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MINI_PID_PARSER8_TO_PARSER11_BAND_ID - MINI PID PARSER8 to PARSER11 BAND ID
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER11_PARSER_SEL [31:31] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_MASK 0x80000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_SHIFT 31
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved0 [30:30] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved0_MASK 0x40000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved0_SHIFT 30
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER11_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER11_BAND_ID_DEFAULT 0x0000000b
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER10_PARSER_SEL [23:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_MASK 0x00800000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_SHIFT 23
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved1 [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved1_MASK 0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved1_SHIFT 22
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER10_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER10_BAND_ID_DEFAULT 0x0000000a
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER9_PARSER_SEL [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_MASK 0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_SHIFT 15
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved2 [14:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved2_MASK 0x00004000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved2_SHIFT 14
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER9_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER9_BAND_ID_DEFAULT 0x00000009
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER8_PARSER_SEL [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_MASK 0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_SHIFT 7
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: reserved3 [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved3_MASK 0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_reserved3_SHIFT 6
+
+/* XPT_FE :: MINI_PID_PARSER8_TO_PARSER11_BAND_ID :: PARSER8_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID_PARSER8_BAND_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MINI_PID_PARSER12_TO_PARSER15_BAND_ID - MINI PID PARSER12 to PARSER15 BAND ID
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER15_PARSER_SEL [31:31] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_MASK 0x80000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_SHIFT 31
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved0 [30:30] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved0_MASK 0x40000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved0_SHIFT 30
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER15_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER15_BAND_ID_DEFAULT 0x0000000f
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER14_PARSER_SEL [23:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_MASK 0x00800000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_SHIFT 23
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved1 [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved1_MASK 0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved1_SHIFT 22
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER14_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER14_BAND_ID_DEFAULT 0x0000000e
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER13_PARSER_SEL [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_MASK 0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_SHIFT 15
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved2 [14:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved2_MASK 0x00004000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved2_SHIFT 14
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER13_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER13_BAND_ID_DEFAULT 0x0000000d
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER12_PARSER_SEL [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_MASK 0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_SHIFT 7
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_PARSER_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: reserved3 [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved3_MASK 0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_reserved3_SHIFT 6
+
+/* XPT_FE :: MINI_PID_PARSER12_TO_PARSER15_BAND_ID :: PARSER12_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID_PARSER12_BAND_ID_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *TSMF0_CTRL - Data Transport TSMF Demultiplexer -- Control Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF0_CTRL :: reserved0 [31:28] */
+#define BCHP_XPT_FE_TSMF0_CTRL_reserved0_MASK                      0xf0000000
+#define BCHP_XPT_FE_TSMF0_CTRL_reserved0_SHIFT                     28
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_INPUT_SEL_MSB [27:27] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_MASK             0x08000000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_SHIFT            27
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MSB_DEFAULT          0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_CRC_CK_DIS [26:26] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_MASK                0x04000000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_SHIFT               26
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CRC_CK_DIS_DEFAULT             0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_STATUS_CK_DIS [25:25] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_MASK      0x02000000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_SHIFT     25
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_STATUS_CK_DIS_DEFAULT   0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_FRAME_TYPE_CK_DIS [24:24] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_MASK         0x01000000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_SHIFT        24
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_FRAME_TYPE_CK_DIS_DEFAULT      0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_MODE_CK_DIS [23:23] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_MASK        0x00800000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_SHIFT       23
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_MODE_CK_DIS_DEFAULT     0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_SYNC_CK_DIS [22:22] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_MASK               0x00400000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_SHIFT              22
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SYNC_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_CC_CK_DIS [21:21] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_MASK                 0x00200000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_SHIFT                21
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_CC_CK_DIS_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_ADAP_CK_DIS [20:20] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_MASK               0x00100000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_SHIFT              20
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ADAP_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_SC_CK_DIS [19:19] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_MASK                 0x00080000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_SHIFT                19
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_SC_CK_DIS_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_TS_PRIOR_CK_DIS [18:18] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_MASK           0x00040000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_SHIFT          18
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TS_PRIOR_CK_DIS_DEFAULT        0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_PUSI_CK_DIS [17:17] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_MASK               0x00020000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_SHIFT              17
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_PUSI_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_TEI_CK_DIS [16:16] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_MASK                0x00010000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_SHIFT               16
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_TEI_CK_DIS_DEFAULT             0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_REL_TS_NO [15:12] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_MASK                 0x0000f000
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_SHIFT                12
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_REL_TS_NO_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_MASK                 0x00000f00
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_SHIFT                8
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_INPUT_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: reserved1 [07:03] */
+#define BCHP_XPT_FE_TSMF0_CTRL_reserved1_MASK                      0x000000f8
+#define BCHP_XPT_FE_TSMF0_CTRL_reserved1_SHIFT                     3
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_VER_CHANGE_MODE [02:02] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_MASK           0x00000004
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_SHIFT          2
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_VER_CHANGE_MODE_DEFAULT        0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_AUTO_EN [01:01] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_MASK                   0x00000002
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_SHIFT                  1
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_AUTO_EN_DEFAULT                0x00000000
+
+/* XPT_FE :: TSMF0_CTRL :: TSMF_ENABLE [00:00] */
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_MASK                    0x00000001
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_SHIFT                   0
+#define BCHP_XPT_FE_TSMF0_CTRL_TSMF_ENABLE_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TSMF0_SLOT_MAP_LO - Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF0_SLOT_MAP_LO :: SLOT_MAP_LO [31:00] */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_MASK             0xffffffff
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_SHIFT            0
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO_SLOT_MAP_LO_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TSMF0_SLOT_MAP_HI - Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF0_SLOT_MAP_HI :: reserved0 [31:20] */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_reserved0_MASK               0xfff00000
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_reserved0_SHIFT              20
+
+/* XPT_FE :: TSMF0_SLOT_MAP_HI :: SLOT_MAP_HI [19:00] */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_MASK             0x000fffff
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_SHIFT            0
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI_SLOT_MAP_HI_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TSMF0_STATUS - Data Transport TSMF Demultiplexer -- Status Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF0_STATUS :: reserved0 [31:10] */
+#define BCHP_XPT_FE_TSMF0_STATUS_reserved0_MASK                    0xfffffc00
+#define BCHP_XPT_FE_TSMF0_STATUS_reserved0_SHIFT                   10
+
+/* XPT_FE :: TSMF0_STATUS :: TSMF_TEST [09:01] */
+#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_TEST_MASK                    0x000003fe
+#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_TEST_SHIFT                   1
+
+/* XPT_FE :: TSMF0_STATUS :: TSMF_OOS_STATUS [00:00] */
+#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_OOS_STATUS_MASK              0x00000001
+#define BCHP_XPT_FE_TSMF0_STATUS_TSMF_OOS_STATUS_SHIFT             0
+
+/***************************************************************************
+ *TSMF1_CTRL - Data Transport TSMF Demultiplexer -- Control Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF1_CTRL :: reserved0 [31:28] */
+#define BCHP_XPT_FE_TSMF1_CTRL_reserved0_MASK                      0xf0000000
+#define BCHP_XPT_FE_TSMF1_CTRL_reserved0_SHIFT                     28
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_INPUT_SEL_MSB [27:27] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_MASK             0x08000000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_SHIFT            27
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MSB_DEFAULT          0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_CRC_CK_DIS [26:26] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_MASK                0x04000000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_SHIFT               26
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CRC_CK_DIS_DEFAULT             0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_STATUS_CK_DIS [25:25] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_MASK      0x02000000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_SHIFT     25
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_STATUS_CK_DIS_DEFAULT   0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_FRAME_TYPE_CK_DIS [24:24] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_MASK         0x01000000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_SHIFT        24
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_FRAME_TYPE_CK_DIS_DEFAULT      0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_MODE_CK_DIS [23:23] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_MASK        0x00800000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_SHIFT       23
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_MODE_CK_DIS_DEFAULT     0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_SYNC_CK_DIS [22:22] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_MASK               0x00400000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_SHIFT              22
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SYNC_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_CC_CK_DIS [21:21] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_MASK                 0x00200000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_SHIFT                21
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_CC_CK_DIS_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_ADAP_CK_DIS [20:20] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_MASK               0x00100000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_SHIFT              20
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ADAP_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_SC_CK_DIS [19:19] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_MASK                 0x00080000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_SHIFT                19
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_SC_CK_DIS_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_TS_PRIOR_CK_DIS [18:18] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_MASK           0x00040000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_SHIFT          18
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TS_PRIOR_CK_DIS_DEFAULT        0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_PUSI_CK_DIS [17:17] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_MASK               0x00020000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_SHIFT              17
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_PUSI_CK_DIS_DEFAULT            0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_TEI_CK_DIS [16:16] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_MASK                0x00010000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_SHIFT               16
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_TEI_CK_DIS_DEFAULT             0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_REL_TS_NO [15:12] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_MASK                 0x0000f000
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_SHIFT                12
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_REL_TS_NO_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_MASK                 0x00000f00
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_SHIFT                8
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_INPUT_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: reserved1 [07:03] */
+#define BCHP_XPT_FE_TSMF1_CTRL_reserved1_MASK                      0x000000f8
+#define BCHP_XPT_FE_TSMF1_CTRL_reserved1_SHIFT                     3
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_VER_CHANGE_MODE [02:02] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_MASK           0x00000004
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_SHIFT          2
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_VER_CHANGE_MODE_DEFAULT        0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_AUTO_EN [01:01] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_MASK                   0x00000002
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_SHIFT                  1
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_AUTO_EN_DEFAULT                0x00000000
+
+/* XPT_FE :: TSMF1_CTRL :: TSMF_ENABLE [00:00] */
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_MASK                    0x00000001
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_SHIFT                   0
+#define BCHP_XPT_FE_TSMF1_CTRL_TSMF_ENABLE_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TSMF1_SLOT_MAP_LO - Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF1_SLOT_MAP_LO :: SLOT_MAP_LO [31:00] */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_MASK             0xffffffff
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_SHIFT            0
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO_SLOT_MAP_LO_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TSMF1_SLOT_MAP_HI - Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF1_SLOT_MAP_HI :: reserved0 [31:20] */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_reserved0_MASK               0xfff00000
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_reserved0_SHIFT              20
+
+/* XPT_FE :: TSMF1_SLOT_MAP_HI :: SLOT_MAP_HI [19:00] */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_MASK             0x000fffff
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_SHIFT            0
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI_SLOT_MAP_HI_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TSMF1_STATUS - Data Transport TSMF Demultiplexer -- Status Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF1_STATUS :: reserved0 [31:10] */
+#define BCHP_XPT_FE_TSMF1_STATUS_reserved0_MASK                    0xfffffc00
+#define BCHP_XPT_FE_TSMF1_STATUS_reserved0_SHIFT                   10
+
+/* XPT_FE :: TSMF1_STATUS :: TSMF_TEST [09:01] */
+#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_TEST_MASK                    0x000003fe
+#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_TEST_SHIFT                   1
+
+/* XPT_FE :: TSMF1_STATUS :: TSMF_OOS_STATUS [00:00] */
+#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_OOS_STATUS_MASK              0x00000001
+#define BCHP_XPT_FE_TSMF1_STATUS_TSMF_OOS_STATUS_SHIFT             0
+
+/***************************************************************************
+ *MTSIF_RX0_CTRL1 - FE_MTSIF_RX0_CTRL1
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: reserved0 [31:09] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved0_MASK                 0xfffffe00
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved0_SHIFT                9
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK       0x00000040
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT      6
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_MASK         0x00000030
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT        4
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT      0x00000003
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: reserved1 [03:02] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved1_MASK                 0x0000000c
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_reserved1_SHIFT                2
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK    0x00000002
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT   1
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX0_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_MASK             0x00000001
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_SHIFT            0
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1_PARSER_ENABLE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *MTSIF_RX0_SECRET_WORD - MTSIF RX0 Secret Word Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_SECRET_WORD :: SECRET_WORD [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_MASK         0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_SHIFT        0
+#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD_SECRET_WORD_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MTSIF_RX0_BAND0_BAND31_ID_DROP - MTSIF RX0 Band0 to Band31 ID Drop Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_MASK    0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT   0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX0_BAND0_BAND3_ID - MTSIF RX0 Band0 to Band3 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX0_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX0_BAND4_BAND7_ID - MTSIF RX0 Band4 to Band7 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX0_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MTSIF_RX0_BAND8_BAND11_ID - MTSIF RX0 Band8 to Band11 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved0_MASK       0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved0_SHIFT      30
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved1_MASK       0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved1_SHIFT      22
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved2_MASK       0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved2_SHIFT      14
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved3_MASK       0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_reserved3_SHIFT      6
+
+/* XPT_FE :: MTSIF_RX0_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MTSIF_RX0_BAND12_BAND15_ID - MTSIF RX0 Band12 to Band15 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *MTSIF_RX0_BAND16_BAND19_ID - MTSIF RX0 Band16 to Band19 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MTSIF_RX0_BAND20_BAND23_ID - MTSIF RX0 Band20 to Band23 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MTSIF_RX0_BAND24_BAND27_ID - MTSIF RX0 Band24 to Band27 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
+
+/***************************************************************************
+ *MTSIF_RX0_BAND28_BAND31_ID - MTSIF RX0 Band28 to Band31 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *MTSIF_RX0_BAND32_BAND35_ID - MTSIF RX0 Band32 to Band35 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
+
+/***************************************************************************
+ *MTSIF_RX0_BAND36_BAND39_ID - MTSIF RX0 Band36 to Band39 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
+
+/***************************************************************************
+ *MTSIF_RX0_BAND40_BAND43_ID - MTSIF RX0 Band40 to Band43 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
+
+/***************************************************************************
+ *MTSIF_RX0_BAND44_BAND47_ID - MTSIF RX0 Band44 to Band47 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
+
+/***************************************************************************
+ *MTSIF_RX0_BAND48_BAND51_ID - MTSIF RX0 Band48 to Band51 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MTSIF_RX0_BAND52_BAND55_ID - MTSIF RX0 Band52 to Band55 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
+
+/***************************************************************************
+ *MTSIF_RX0_BAND56_BAND59_ID - MTSIF RX0 Band56 to Band59 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
+
+/***************************************************************************
+ *MTSIF_RX0_BAND60_BAND63_ID - MTSIF RX0 Band60 to Band63 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX0_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
+
+/***************************************************************************
+ *MTSIF_RX0_PKT_BAND0_BAND31_DETECT - MTSIF RX0 Packet Band0 to Band31 Detect Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX0_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX1_CTRL1 - FE_MTSIF_RX1_CTRL1
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: reserved0 [31:09] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved0_MASK                 0xfffffe00
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved0_SHIFT                9
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK       0x00000040
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT      6
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_MASK         0x00000030
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT        4
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT      0x00000003
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: reserved1 [03:02] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved1_MASK                 0x0000000c
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_reserved1_SHIFT                2
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK    0x00000002
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT   1
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX1_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_MASK             0x00000001
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_SHIFT            0
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1_PARSER_ENABLE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *MTSIF_RX1_SECRET_WORD - MTSIF RX1 Secret Word Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_SECRET_WORD :: SECRET_WORD [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_MASK         0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_SHIFT        0
+#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD_SECRET_WORD_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MTSIF_RX1_BAND0_BAND31_ID_DROP - MTSIF RX1 Band0 to Band31 ID Drop Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_MASK    0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT   0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX1_BAND0_BAND3_ID - MTSIF RX1 Band0 to Band3 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX1_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX1_BAND4_BAND7_ID - MTSIF RX1 Band4 to Band7 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX1_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MTSIF_RX1_BAND8_BAND11_ID - MTSIF RX1 Band8 to Band11 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved0_MASK       0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved0_SHIFT      30
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved1_MASK       0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved1_SHIFT      22
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved2_MASK       0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved2_SHIFT      14
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved3_MASK       0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_reserved3_SHIFT      6
+
+/* XPT_FE :: MTSIF_RX1_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MTSIF_RX1_BAND12_BAND15_ID - MTSIF RX1 Band12 to Band15 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *MTSIF_RX1_BAND16_BAND19_ID - MTSIF RX1 Band16 to Band19 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MTSIF_RX1_BAND20_BAND23_ID - MTSIF RX1 Band20 to Band23 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MTSIF_RX1_BAND24_BAND27_ID - MTSIF RX1 Band24 to Band27 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
+
+/***************************************************************************
+ *MTSIF_RX1_BAND28_BAND31_ID - MTSIF RX1 Band28 to Band31 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *MTSIF_RX1_BAND32_BAND35_ID - MTSIF RX1 Band32 to Band35 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
+
+/***************************************************************************
+ *MTSIF_RX1_BAND36_BAND39_ID - MTSIF RX1 Band36 to Band39 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
+
+/***************************************************************************
+ *MTSIF_RX1_BAND40_BAND43_ID - MTSIF RX1 Band40 to Band43 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
+
+/***************************************************************************
+ *MTSIF_RX1_BAND44_BAND47_ID - MTSIF RX1 Band44 to Band47 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
+
+/***************************************************************************
+ *MTSIF_RX1_BAND48_BAND51_ID - MTSIF RX1 Band48 to Band51 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MTSIF_RX1_BAND52_BAND55_ID - MTSIF RX1 Band52 to Band55 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
+
+/***************************************************************************
+ *MTSIF_RX1_BAND56_BAND59_ID - MTSIF RX1 Band56 to Band59 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
+
+/***************************************************************************
+ *MTSIF_RX1_BAND60_BAND63_ID - MTSIF RX1 Band60 to Band63 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX1_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
+
+/***************************************************************************
+ *MTSIF_RX1_PKT_BAND0_BAND31_DETECT - MTSIF RX1 Packet Band0 to Band31 Detect Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX1_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX2_CTRL1 - FE_MTSIF_RX2_CTRL1
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: reserved0 [31:09] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved0_MASK                 0xfffffe00
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved0_SHIFT                9
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK       0x00000040
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT      6
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_MASK         0x00000030
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT        4
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT      0x00000003
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: reserved1 [03:02] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved1_MASK                 0x0000000c
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_reserved1_SHIFT                2
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK    0x00000002
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT   1
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX2_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_MASK             0x00000001
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_SHIFT            0
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1_PARSER_ENABLE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *MTSIF_RX2_SECRET_WORD - MTSIF RX2 Secret Word Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_SECRET_WORD :: SECRET_WORD [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_MASK         0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_SHIFT        0
+#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD_SECRET_WORD_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MTSIF_RX2_BAND0_BAND31_ID_DROP - MTSIF RX2 Band0 to Band31 ID Drop Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_MASK    0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT   0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX2_BAND0_BAND3_ID - MTSIF RX2 Band0 to Band3 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX2_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX2_BAND4_BAND7_ID - MTSIF RX2 Band4 to Band7 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX2_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MTSIF_RX2_BAND8_BAND11_ID - MTSIF RX2 Band8 to Band11 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved0_MASK       0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved0_SHIFT      30
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved1_MASK       0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved1_SHIFT      22
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved2_MASK       0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved2_SHIFT      14
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved3_MASK       0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_reserved3_SHIFT      6
+
+/* XPT_FE :: MTSIF_RX2_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MTSIF_RX2_BAND12_BAND15_ID - MTSIF RX2 Band12 to Band15 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *MTSIF_RX2_BAND16_BAND19_ID - MTSIF RX2 Band16 to Band19 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MTSIF_RX2_BAND20_BAND23_ID - MTSIF RX2 Band20 to Band23 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MTSIF_RX2_BAND24_BAND27_ID - MTSIF RX2 Band24 to Band27 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
+
+/***************************************************************************
+ *MTSIF_RX2_BAND28_BAND31_ID - MTSIF RX2 Band28 to Band31 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *MTSIF_RX2_BAND32_BAND35_ID - MTSIF RX2 Band32 to Band35 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
+
+/***************************************************************************
+ *MTSIF_RX2_BAND36_BAND39_ID - MTSIF RX2 Band36 to Band39 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
+
+/***************************************************************************
+ *MTSIF_RX2_BAND40_BAND43_ID - MTSIF RX2 Band40 to Band43 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
+
+/***************************************************************************
+ *MTSIF_RX2_BAND44_BAND47_ID - MTSIF RX2 Band44 to Band47 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
+
+/***************************************************************************
+ *MTSIF_RX2_BAND48_BAND51_ID - MTSIF RX2 Band48 to Band51 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MTSIF_RX2_BAND52_BAND55_ID - MTSIF RX2 Band52 to Band55 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
+
+/***************************************************************************
+ *MTSIF_RX2_BAND56_BAND59_ID - MTSIF RX2 Band56 to Band59 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
+
+/***************************************************************************
+ *MTSIF_RX2_BAND60_BAND63_ID - MTSIF RX2 Band60 to Band63 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX2_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
+
+/***************************************************************************
+ *MTSIF_RX2_PKT_BAND0_BAND31_DETECT - MTSIF RX2 Packet Band0 to Band31 Detect Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX2_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX3_CTRL1 - FE_MTSIF_RX3_CTRL1
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: reserved0 [31:09] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved0_MASK                 0xfffffe00
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved0_SHIFT                9
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_DECRYPTION_ENABLE_STATUS [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_DECRYPTION_ENABLE_STATUS_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_PKT_BAND_DETECT_MODE [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_PKT_BAND_DETECT_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_ERR_RPT_EN [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_MASK       0x00000040
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_SHIFT      6
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_ERR_RPT_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_IF_WIDTH [05:04] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_MASK         0x00000030
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_SHIFT        4
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_IF_WIDTH_DEFAULT      0x00000003
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: reserved1 [03:02] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved1_MASK                 0x0000000c
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_reserved1_SHIFT                2
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: MTSIF_RX_CLOCK_POL_SEL [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_MASK    0x00000002
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_SHIFT   1
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_MTSIF_RX_CLOCK_POL_SEL_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX3_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_MASK             0x00000001
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_SHIFT            0
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1_PARSER_ENABLE_DEFAULT          0x00000000
+
+/***************************************************************************
+ *MTSIF_RX3_SECRET_WORD - MTSIF RX3 Secret Word Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_SECRET_WORD :: SECRET_WORD [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_MASK         0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_SHIFT        0
+#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD_SECRET_WORD_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MTSIF_RX3_BAND0_BAND31_ID_DROP - MTSIF RX3 Band0 to Band31 ID Drop Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND31_ID_DROP :: DROP_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_MASK    0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_SHIFT   0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP_DROP_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX3_BAND0_BAND3_ID - MTSIF RX3 Band0 to Band3 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND3_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND3_BAND_ID_DEFAULT 0x00000003
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND2_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND2_BAND_ID_DEFAULT 0x00000002
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND1_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND1_BAND_ID_DEFAULT 0x00000001
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX3_BAND0_BAND3_ID :: MTSIF_BAND0_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID_MTSIF_BAND0_BAND_ID_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX3_BAND4_BAND7_ID - MTSIF RX3 Band4 to Band7 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved0_MASK        0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved0_SHIFT       30
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND7_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND7_BAND_ID_DEFAULT 0x00000007
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved1_MASK        0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved1_SHIFT       22
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND6_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND6_BAND_ID_DEFAULT 0x00000006
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved2_MASK        0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved2_SHIFT       14
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND5_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND5_BAND_ID_DEFAULT 0x00000005
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved3_MASK        0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_reserved3_SHIFT       6
+
+/* XPT_FE :: MTSIF_RX3_BAND4_BAND7_ID :: MTSIF_BAND4_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID_MTSIF_BAND4_BAND_ID_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MTSIF_RX3_BAND8_BAND11_ID - MTSIF RX3 Band8 to Band11 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved0_MASK       0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved0_SHIFT      30
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND11_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND11_BAND_ID_DEFAULT 0x0000000b
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved1_MASK       0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved1_SHIFT      22
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND10_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND10_BAND_ID_DEFAULT 0x0000000a
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved2_MASK       0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved2_SHIFT      14
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND9_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND9_BAND_ID_DEFAULT 0x00000009
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved3_MASK       0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_reserved3_SHIFT      6
+
+/* XPT_FE :: MTSIF_RX3_BAND8_BAND11_ID :: MTSIF_BAND8_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID_MTSIF_BAND8_BAND_ID_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MTSIF_RX3_BAND12_BAND15_ID - MTSIF RX3 Band12 to Band15 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND15_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND15_BAND_ID_DEFAULT 0x0000000f
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND14_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND14_BAND_ID_DEFAULT 0x0000000e
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND13_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND13_BAND_ID_DEFAULT 0x0000000d
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND12_BAND15_ID :: MTSIF_BAND12_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID_MTSIF_BAND12_BAND_ID_DEFAULT 0x0000000c
+
+/***************************************************************************
+ *MTSIF_RX3_BAND16_BAND19_ID - MTSIF RX3 Band16 to Band19 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND19_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND19_BAND_ID_DEFAULT 0x00000013
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND18_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND18_BAND_ID_DEFAULT 0x00000012
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND17_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND17_BAND_ID_DEFAULT 0x00000011
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND16_BAND19_ID :: MTSIF_BAND16_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID_MTSIF_BAND16_BAND_ID_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MTSIF_RX3_BAND20_BAND23_ID - MTSIF RX3 Band20 to Band23 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND23_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND23_BAND_ID_DEFAULT 0x00000017
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND22_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND22_BAND_ID_DEFAULT 0x00000016
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND21_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND21_BAND_ID_DEFAULT 0x00000015
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND20_BAND23_ID :: MTSIF_BAND20_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID_MTSIF_BAND20_BAND_ID_DEFAULT 0x00000014
+
+/***************************************************************************
+ *MTSIF_RX3_BAND24_BAND27_ID - MTSIF RX3 Band24 to Band27 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND27_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND27_BAND_ID_DEFAULT 0x0000001b
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND26_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND26_BAND_ID_DEFAULT 0x0000001a
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND25_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND25_BAND_ID_DEFAULT 0x00000019
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND24_BAND27_ID :: MTSIF_BAND24_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID_MTSIF_BAND24_BAND_ID_DEFAULT 0x00000018
+
+/***************************************************************************
+ *MTSIF_RX3_BAND28_BAND31_ID - MTSIF RX3 Band28 to Band31 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND31_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND31_BAND_ID_DEFAULT 0x0000001f
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND30_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND30_BAND_ID_DEFAULT 0x0000001e
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND29_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND29_BAND_ID_DEFAULT 0x0000001d
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND28_BAND31_ID :: MTSIF_BAND28_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID_MTSIF_BAND28_BAND_ID_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *MTSIF_RX3_BAND32_BAND35_ID - MTSIF RX3 Band32 to Band35 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND35_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND35_BAND_ID_DEFAULT 0x00000023
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND34_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND34_BAND_ID_DEFAULT 0x00000022
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND33_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND33_BAND_ID_DEFAULT 0x00000021
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND32_BAND35_ID :: MTSIF_BAND32_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID_MTSIF_BAND32_BAND_ID_DEFAULT 0x00000020
+
+/***************************************************************************
+ *MTSIF_RX3_BAND36_BAND39_ID - MTSIF RX3 Band36 to Band39 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND39_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND39_BAND_ID_DEFAULT 0x00000027
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND38_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND38_BAND_ID_DEFAULT 0x00000026
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND37_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND37_BAND_ID_DEFAULT 0x00000025
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND36_BAND39_ID :: MTSIF_BAND36_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID_MTSIF_BAND36_BAND_ID_DEFAULT 0x00000024
+
+/***************************************************************************
+ *MTSIF_RX3_BAND40_BAND43_ID - MTSIF RX3 Band40 to Band43 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND43_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND43_BAND_ID_DEFAULT 0x0000002b
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND42_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND42_BAND_ID_DEFAULT 0x0000002a
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND41_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND41_BAND_ID_DEFAULT 0x00000029
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND40_BAND43_ID :: MTSIF_BAND40_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID_MTSIF_BAND40_BAND_ID_DEFAULT 0x00000028
+
+/***************************************************************************
+ *MTSIF_RX3_BAND44_BAND47_ID - MTSIF RX3 Band44 to Band47 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND47_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND47_BAND_ID_DEFAULT 0x0000002f
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND46_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND46_BAND_ID_DEFAULT 0x0000002e
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND45_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND45_BAND_ID_DEFAULT 0x0000002d
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND44_BAND47_ID :: MTSIF_BAND44_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID_MTSIF_BAND44_BAND_ID_DEFAULT 0x0000002c
+
+/***************************************************************************
+ *MTSIF_RX3_BAND48_BAND51_ID - MTSIF RX3 Band48 to Band51 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND51_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND51_BAND_ID_DEFAULT 0x00000033
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND50_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND50_BAND_ID_DEFAULT 0x00000032
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND49_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND49_BAND_ID_DEFAULT 0x00000031
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND48_BAND51_ID :: MTSIF_BAND48_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID_MTSIF_BAND48_BAND_ID_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MTSIF_RX3_BAND52_BAND55_ID - MTSIF RX3 Band52 to Band55 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND55_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND55_BAND_ID_DEFAULT 0x00000037
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND54_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND54_BAND_ID_DEFAULT 0x00000036
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND53_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND53_BAND_ID_DEFAULT 0x00000035
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND52_BAND55_ID :: MTSIF_BAND52_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID_MTSIF_BAND52_BAND_ID_DEFAULT 0x00000034
+
+/***************************************************************************
+ *MTSIF_RX3_BAND56_BAND59_ID - MTSIF RX3 Band56 to Band59 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND59_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND59_BAND_ID_DEFAULT 0x0000003b
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND58_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND58_BAND_ID_DEFAULT 0x0000003a
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND57_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND57_BAND_ID_DEFAULT 0x00000039
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND56_BAND59_ID :: MTSIF_BAND56_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID_MTSIF_BAND56_BAND_ID_DEFAULT 0x00000038
+
+/***************************************************************************
+ *MTSIF_RX3_BAND60_BAND63_ID - MTSIF RX3 Band60 to Band63 ID Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved0 [31:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved0_MASK      0xc0000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved0_SHIFT     30
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND63_BAND_ID [29:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_MASK 0x3f000000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND63_BAND_ID_DEFAULT 0x0000003f
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved1 [23:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved1_MASK      0x00c00000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved1_SHIFT     22
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND62_BAND_ID [21:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_MASK 0x003f0000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND62_BAND_ID_DEFAULT 0x0000003e
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved2 [15:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved2_MASK      0x0000c000
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved2_SHIFT     14
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND61_BAND_ID [13:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_MASK 0x00003f00
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND61_BAND_ID_DEFAULT 0x0000003d
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: reserved3 [07:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved3_MASK      0x000000c0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_reserved3_SHIFT     6
+
+/* XPT_FE :: MTSIF_RX3_BAND60_BAND63_ID :: MTSIF_BAND60_BAND_ID [05:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_MASK 0x0000003f
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID_MTSIF_BAND60_BAND_ID_DEFAULT 0x0000003c
+
+/***************************************************************************
+ *MTSIF_RX3_PKT_BAND0_BAND31_DETECT - MTSIF RX3 Packet Band0 to Band31 Detect Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID31 [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID31_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID30 [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID30_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID29 [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID29_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID28 [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID28_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID27 [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID27_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID26 [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID26_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID25 [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID25_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID24 [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID24_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID23 [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID23_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID22 [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID22_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID21 [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID21_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID20 [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID20_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID19 [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID19_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID18 [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID18_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID17 [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID17_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID16 [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID16_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID15 [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID15_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID14 [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID14_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID13 [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID13_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID12 [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID12_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID11 [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID11_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID10 [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID10_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID9 [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID9_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID8 [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID8_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID7 [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID7_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID6 [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID6_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID5 [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID5_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID4 [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID4_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID3 [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID3_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID2 [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID2_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID1 [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID1_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX3_PKT_BAND0_BAND31_DETECT :: BAND_ID0 [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT_BAND_ID0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_TB_CTRL1 - Data Transport Parser Band 0 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_SYNC_COUNT - Data Transport Parser Band 0 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER0_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_TB_CTRL1 - Data Transport Parser Band 1 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_SYNC_COUNT - Data Transport Parser Band 1 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER1_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_TB_CTRL1 - Data Transport Parser Band 2 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_SYNC_COUNT - Data Transport Parser Band 2 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER2_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_TB_CTRL1 - Data Transport Parser Band 3 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_SYNC_COUNT - Data Transport Parser Band 3 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER3_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_TB_CTRL1 - Data Transport Parser Band 4 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_SYNC_COUNT - Data Transport Parser Band 4 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER4_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_TB_CTRL1 - Data Transport Parser Band 5 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_SYNC_COUNT - Data Transport Parser Band 5 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER5_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_TB_CTRL1 - Data Transport Parser Band 6 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_SYNC_COUNT - Data Transport Parser Band 6 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER6_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_TB_CTRL1 - Data Transport Parser Band 7 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_SYNC_COUNT - Data Transport Parser Band 7 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER7_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_TB_CTRL1 - Data Transport Parser Band 8 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_SYNC_COUNT - Data Transport Parser Band 8 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER8_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_TB_CTRL1 - Data Transport Parser Band 9 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved0_MASK       0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved0_SHIFT      28
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved1_MASK       0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved1_SHIFT      15
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved2_MASK       0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_reserved2_SHIFT      4
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_MASK       0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_SHIFT      0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1_TB_ENABLE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_SYNC_COUNT - Data Transport Parser Band 9 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_reserved0_SHIFT    10
+
+/* XPT_FE :: MINI_PID_PARSER9_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_TB_CTRL1 - Data Transport Parser Band 10 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_SYNC_COUNT - Data Transport Parser Band 10 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER10_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_TB_CTRL1 - Data Transport Parser Band 11 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_SYNC_COUNT - Data Transport Parser Band 11 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER11_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER12_TB_CTRL1 - Data Transport Parser Band 12 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER12_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER12_SYNC_COUNT - Data Transport Parser Band 12 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER12_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER13_TB_CTRL1 - Data Transport Parser Band 13 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER13_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER13_SYNC_COUNT - Data Transport Parser Band 13 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER13_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER13_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER14_TB_CTRL1 - Data Transport Parser Band 14 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER14_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER14_SYNC_COUNT - Data Transport Parser Band 14 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER14_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER14_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER15_TB_CTRL1 - Data Transport Parser Band 15 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER15_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER15_SYNC_COUNT - Data Transport Parser Band 15 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER15_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER15_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER16_TB_CTRL1 - Data Transport Parser Band 16 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER16_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER16_SYNC_COUNT - Data Transport Parser Band 16 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER16_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER16_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER17_TB_CTRL1 - Data Transport Parser Band 17 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER17_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER17_SYNC_COUNT - Data Transport Parser Band 17 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER17_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER17_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER18_TB_CTRL1 - Data Transport Parser Band 18 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER18_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER18_SYNC_COUNT - Data Transport Parser Band 18 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER18_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER18_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER19_TB_CTRL1 - Data Transport Parser Band 19 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER19_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER19_SYNC_COUNT - Data Transport Parser Band 19 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER19_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER19_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER20_TB_CTRL1 - Data Transport Parser Band 20 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER20_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER20_SYNC_COUNT - Data Transport Parser Band 20 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER20_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER20_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER21_TB_CTRL1 - Data Transport Parser Band 21 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER21_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER21_SYNC_COUNT - Data Transport Parser Band 21 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER21_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER21_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER22_TB_CTRL1 - Data Transport Parser Band 22 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER22_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER22_SYNC_COUNT - Data Transport Parser Band 22 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER22_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER22_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER23_TB_CTRL1 - Data Transport Parser Band 23 Transponder Bonding Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved0 [31:28] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved0_MASK      0xf0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved0_SHIFT     28
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_PARSER_PID_CH_NUM [27:16] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_MASK 0x0fff0000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_SHIFT 16
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_PARSER_PID_CH_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved1 [15:15] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved1_MASK      0x00008000
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved1_SHIFT     15
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TBG_PRI_BAND_NUM [14:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_MASK 0x00007f00
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TBG_PRI_BAND_NUM_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: reserved2 [07:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved2_MASK      0x000000f0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_reserved2_SHIFT     4
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_SKIP_ADAP_PRIVATE_DATA_PARSING [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_SKIP_ADAP_PRIVATE_DATA_PARSING_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_IGNORE_TS_PRIORITY [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_IGNORE_TS_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_DROP_BEF_FIRST_MARKER_PKT [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_DROP_BEF_FIRST_MARKER_PKT_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER23_TB_CTRL1 :: TB_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1_TB_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER23_SYNC_COUNT - Data Transport Parser Band 23 Transponder Bonding Sync Counter Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER23_SYNC_COUNT :: reserved0 [31:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_reserved0_MASK    0xfffffc00
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_reserved0_SHIFT   10
+
+/* XPT_FE :: MINI_PID_PARSER23_SYNC_COUNT :: SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_MASK   0x000003ff
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_SHIFT  0
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT_SYNC_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TB_GLOBAL_CTRL1 - Transponder Bonding Global Control Register 1
+ ***************************************************************************/
+/* XPT_FE :: TB_GLOBAL_CTRL1 :: reserved0 [31:24] */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved0_MASK                 0xff000000
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved0_SHIFT                24
+
+/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_MARKER_TAG [23:16] */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_MASK             0x00ff0000
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_SHIFT            16
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_MARKER_TAG_DEFAULT          0x000000ba
+
+/* XPT_FE :: TB_GLOBAL_CTRL1 :: reserved1 [15:11] */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved1_MASK                 0x0000f800
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_reserved1_SHIFT                11
+
+/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_SATURATE_SYNC_COUNT_EN [10:10] */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_MASK 0x00000400
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_SHIFT 10
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_EN_DEFAULT 0x00000001
+
+/* XPT_FE :: TB_GLOBAL_CTRL1 :: TB_SATURATE_SYNC_COUNT [09:00] */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_MASK    0x000003ff
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_SHIFT   0
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1_TB_SATURATE_SYNC_COUNT_DEFAULT 0x00000100
+
+/***************************************************************************
+ *TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG - Parsers Private Data Length Error Status Register
+ ***************************************************************************/
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR [31:31] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_SHIFT 31
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR [30:30] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_SHIFT 30
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR [29:29] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_SHIFT 29
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR [28:28] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_SHIFT 28
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR [27:27] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_SHIFT 27
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR [26:26] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_SHIFT 26
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR [25:25] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_SHIFT 25
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR [24:24] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_SHIFT 24
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR [23:23] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_SHIFT 23
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR [22:22] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_SHIFT 22
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR [21:21] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_SHIFT 21
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR [20:20] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_SHIFT 20
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR [19:19] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_SHIFT 19
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR [18:18] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_SHIFT 18
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR [17:17] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_SHIFT 17
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR [16:16] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_SHIFT 16
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR [15:15] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_SHIFT 15
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR [14:14] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_SHIFT 14
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR [13:13] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_SHIFT 13
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR [12:12] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_SHIFT 12
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR [11:11] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_SHIFT 11
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR [10:10] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_SHIFT 10
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR [09:09] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_SHIFT 9
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR [08:08] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_SHIFT 8
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR [07:07] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_SHIFT 7
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR [06:06] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_SHIFT 6
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR [05:05] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_SHIFT 5
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_SHIFT 4
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_SHIFT 3
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_SHIFT 2
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_SHIFT 1
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG :: TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR [00:00] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_SHIFT 0
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_LENGTH_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG - Parsers Private Data Field Length Error Status Register
+ ***************************************************************************/
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR [31:31] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 31
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER31_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR [30:30] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 30
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER30_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR [29:29] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 29
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER29_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR [28:28] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 28
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER28_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR [27:27] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 27
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER27_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR [26:26] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 26
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER26_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR [25:25] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 25
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER25_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR [24:24] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 24
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER24_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR [23:23] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 23
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER23_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR [22:22] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 22
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER22_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR [21:21] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 21
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER21_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR [20:20] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 20
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER20_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR [19:19] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 19
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER19_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR [18:18] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 18
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER18_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR [17:17] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 17
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER17_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR [16:16] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 16
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER16_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR [15:15] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 15
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER15_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR [14:14] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 14
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER14_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR [13:13] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 13
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER13_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR [12:12] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 12
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER12_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR [11:11] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 11
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER11_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR [10:10] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 10
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER10_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR [09:09] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 9
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER9_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR [08:08] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 8
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER8_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR [07:07] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 7
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER7_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR [06:06] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 6
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER6_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR [05:05] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 5
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER5_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 4
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER4_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 3
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER3_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 2
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER2_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 1
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER1_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG :: TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR [00:00] */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_SHIFT 0
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG_TB_PARSER0_PRIVATE_DATA_FIELD_LENGTH_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PID_TABLE_%i - Data Transport Primary PID Table
+ ***************************************************************************/
+#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_BASE                         0x00a21000
+#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_START                        0
+#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_END                          1023
+#define BCHP_XPT_FE_PID_TABLE_i_ARRAY_ELEMENT_SIZE                 32
+
+/***************************************************************************
+ *PID_TABLE_%i - Data Transport Primary PID Table
+ ***************************************************************************/
+/* XPT_FE :: PID_TABLE_i :: SECURITY_OUTPUT_PIPE_SEL [31:30] */
+#define BCHP_XPT_FE_PID_TABLE_i_SECURITY_OUTPUT_PIPE_SEL_MASK      0xc0000000
+#define BCHP_XPT_FE_PID_TABLE_i_SECURITY_OUTPUT_PIPE_SEL_SHIFT     30
+
+/* XPT_FE :: PID_TABLE_i :: PARSER_OUTPUT_PIPE_SEL [29:28] */
+#define BCHP_XPT_FE_PID_TABLE_i_PARSER_OUTPUT_PIPE_SEL_MASK        0x30000000
+#define BCHP_XPT_FE_PID_TABLE_i_PARSER_OUTPUT_PIPE_SEL_SHIFT       28
+
+/* XPT_FE :: PID_TABLE_i :: IGNORE_PID_VERSION [27:27] */
+#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_MASK            0x08000000
+#define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_SHIFT           27
+
+/* XPT_FE :: PID_TABLE_i :: PID_VERSION [26:24] */
+#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_MASK                   0x07000000
+#define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_SHIFT                  24
+
+/* XPT_FE :: PID_TABLE_i :: PLAYBACK_FE_SEL [23:23] */
+#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_MASK               0x00800000
+#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_SHIFT              23
+
+/* union - case INPUT_BAND_PARSER [22:16] */
+/* XPT_FE :: PID_TABLE_i :: INPUT_BAND_PARSER :: PID_CHANNEL_INPUT_SELECT [22:16] */
+#define BCHP_XPT_FE_PID_TABLE_i_INPUT_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_MASK 0x007f0000
+#define BCHP_XPT_FE_PID_TABLE_i_INPUT_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_SHIFT 16
+
+/* union - case PLAYBACK_BAND_PARSER [22:16] */
+/* XPT_FE :: PID_TABLE_i :: PLAYBACK_BAND_PARSER :: PID_CHANNEL_INPUT_SELECT [22:16] */
+#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_MASK 0x007f0000
+#define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_BAND_PARSER_PID_CHANNEL_INPUT_SELECT_SHIFT 16
+
+/* XPT_FE :: PID_TABLE_i :: MPOD_BYPASS_EN [15:15] */
+#define BCHP_XPT_FE_PID_TABLE_i_MPOD_BYPASS_EN_MASK                0x00008000
+#define BCHP_XPT_FE_PID_TABLE_i_MPOD_BYPASS_EN_SHIFT               15
+
+/* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_ENABLE [14:14] */
+#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_MASK            0x00004000
+#define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_SHIFT           14
+
+/* XPT_FE :: PID_TABLE_i :: ENABLE_HD_FILTER [13:13] */
+#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_MASK              0x00002000
+#define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_SHIFT             13
+
+/* union - case HD_FILT_EN [12:00] */
+/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: HD_FILTER_TYPE [12:12] */
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_MASK     0x00001000
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_SHIFT    12
+
+/* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: PID_CHANNEL_SCID [11:00] */
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_MASK   0x00000fff
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_SHIFT  0
+
+/* union - case HD_FILT_DIS [12:00] */
+/* XPT_FE :: PID_TABLE_i :: HD_FILT_DIS :: PID_CHANNEL_PID [12:00] */
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_MASK   0x00001fff
+#define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_SHIFT  0
+
+
+/***************************************************************************
+ *SPID_TABLE_%i - Data Transport Secondary PID Table
+ ***************************************************************************/
+#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_BASE                        0x00a23000
+#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_START                       0
+#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_END                         1023
+#define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_ELEMENT_SIZE                32
+
+/***************************************************************************
+ *SPID_TABLE_%i - Data Transport Secondary PID Table
+ ***************************************************************************/
+/* XPT_FE :: SPID_TABLE_i :: PID_DESTINATION [31:24] */
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_MASK              0xff000000
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_SHIFT             24
+
+/* XPT_FE :: SPID_TABLE_i :: TSIO_BYPASS_EN [23:23] */
+#define BCHP_XPT_FE_SPID_TABLE_i_TSIO_BYPASS_EN_MASK               0x00800000
+#define BCHP_XPT_FE_SPID_TABLE_i_TSIO_BYPASS_EN_SHIFT              23
+
+/* XPT_FE :: SPID_TABLE_i :: SPID_VERSION [22:20] */
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_VERSION_MASK                 0x00700000
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_VERSION_SHIFT                20
+
+/* XPT_FE :: SPID_TABLE_i :: SPID_MODE [19:16] */
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_MASK                    0x000f0000
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SHIFT                   16
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_DISABLE_SPID            0
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_SUBSTITUTION_NQ 1
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_SUBSTITUTION_Q  2
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_INSERTION       3
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PSG_PKT_INSERTION_DELETION 4
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE1              5
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE2              6
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_REMAP               7
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_FILTER        8
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE0              9
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_RANGE         10
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_EXTENSION_FILTER 12
+#define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SUBSTREAM_ID_FILTER     14
+
+/* union - case STREAM_ID_FILTER [15:00] */
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: STREAM_ID [15:08] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_MASK   0x0000ff00
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_SHIFT  8
+
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: reserved0 [07:00] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_MASK   0x000000ff
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_SHIFT  0
+
+/* union - case STREAM_ID_RANGE [15:00] */
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_HI [15:08] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_MASK 0x0000ff00
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_SHIFT 8
+
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_LO [07:00] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_MASK 0x000000ff
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_SHIFT 0
+
+/* union - case STREAM_ID_EXTENSION_FILTER [15:00] */
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID [15:08] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_MASK 0x0000ff00
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_SHIFT 8
+
+/* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID_EXTENSION [07:00] */
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_MASK 0x000000ff
+#define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_SHIFT 0
+
+/* union - case SUBSTREAM_ID_FILTER [15:00] */
+/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: STREAM_ID [15:08] */
+#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00
+#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_SHIFT 8
+
+/* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: SUBSTREAM_ID [07:00] */
+#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_MASK 0x000000ff
+#define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_SHIFT 0
+
+/* union - case PID_FUNCTIONS [15:00] */
+/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: reserved0 [15:13] */
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_MASK      0x0000e000
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_SHIFT     13
+
+/* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: SPID_CHANNEL_PID [12:00] */
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_MASK 0x00001fff
+#define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_SHIFT 0
+
+
+/***************************************************************************
+ *SPID_EXT_TABLE_%i - Data Transport Secondary PID Extended Table
+ ***************************************************************************/
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_BASE                    0x00a25000
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_START                   0
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_END                     1023
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_ARRAY_ELEMENT_SIZE            32
+
+/***************************************************************************
+ *SPID_EXT_TABLE_%i - Data Transport Secondary PID Extended Table
+ ***************************************************************************/
+/* XPT_FE :: SPID_EXT_TABLE_i :: reserved0 [31:08] */
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_reserved0_MASK                0xffffff00
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_reserved0_SHIFT               8
+
+/* XPT_FE :: SPID_EXT_TABLE_i :: PID_DESTINATION_EXT [07:00] */
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_PID_DESTINATION_EXT_MASK      0x000000ff
+#define BCHP_XPT_FE_SPID_EXT_TABLE_i_PID_DESTINATION_EXT_SHIFT     0
+
+
+#endif /* #ifndef BCHP_XPT_FE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb.h b/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb.h
new file mode 100644
index 000000000000..07d2265ed623
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb.h
@@ -0,0 +1,4737 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Sat Apr 12 03:17:53 2014
+ *                 Full Compile MD5 Checksum 5f2af4819d5a3039f3fe1938baf5d1f2
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              afc8344db5db4960ac3645d27d001fbc
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_MEMDMA_MCPB_H__
+#define BCHP_XPT_MEMDMA_MCPB_H__
+
+/***************************************************************************
+ *XPT_MEMDMA_MCPB - MCPB Top Control Registers
+ ***************************************************************************/
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR       0x00a60800 /* Set and Clear for the RUN bit */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET            0x00a60804 /* Set for the WAKE bit */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR 0x00a60808 /* Set and Clear for the WAKE_MODE bit */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET   0x00a6080c /* Set for the BUFF_DATA_RDY bit */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR 0x00a60810 /* Clear for the PAUSE_AT_DESC_READ bit */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR 0x00a60814 /* Clear for the PAUSE_AT_DESC_END bit */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR 0x00a60818 /* Clear for the PAUSE_AFTER_GROUP_PACKETS bit */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR 0x00a6081c /* Clear for the CRC_COMPARE_ERROR_PAUSE bit */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR 0x00a60820 /* Set and Clear for the MICRO_PAUSE bit */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31     0x00a60824 /* Run status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31    0x00a60828 /* Wake status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31 0x00a6082c /* Wake Mode status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31 0x00a60830 /* Pause at descriptor read status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31 0x00a60834 /* Pause at descriptor end status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 0x00a60838 /* Pause after group of packets status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 0x00a6083c /* CRC compare error pause status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31 0x00a60840 /* Micro Pause status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31 0x00a60844 /* Final Pause status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31 0x00a60848 /* Hardware Pause status for all the PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31 0x00a6084c /* Descriptor Read in Progress status flag */
+#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31 0x00a60850 /* Data Read in Progress status flag */
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31 0x00a60854 /* Burst Buffer Read in Progress status flag */
+#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31 0x00a60858 /* Last Descriptor Reached status flag */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31  0x00a6085c /* Buffer data ready status flag */
+#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31 0x00a60860 /* First data read operation priority flag */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR 0x00a60864 /* Set and Clear Run Invalid */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31 0x00a60868 /* Run Invalid status */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET 0x00a6086c /* Set priority for channel arbitration */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15 0x00a60870 /* Channel priority status for channels 0 to 15 */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31 0x00a60874 /* Channel priority status for channels 16 to 31 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0 0x00a60878 /* MCPB Band pause mapping vector for channel 0 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1 0x00a6087c /* MCPB Band pause mapping vector for channel 1 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2 0x00a60880 /* MCPB Band pause mapping vector for channel 2 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3 0x00a60884 /* MCPB Band pause mapping vector for channel 3 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4 0x00a60888 /* MCPB Band pause mapping vector for channel 4 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5 0x00a6088c /* MCPB Band pause mapping vector for channel 5 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6 0x00a60890 /* MCPB Band pause mapping vector for channel 6 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7 0x00a60894 /* MCPB Band pause mapping vector for channel 7 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8 0x00a60898 /* MCPB Band pause mapping vector for channel 8 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9 0x00a6089c /* MCPB Band pause mapping vector for channel 9 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10 0x00a608a0 /* MCPB Band pause mapping vector for channel 10 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11 0x00a608a4 /* MCPB Band pause mapping vector for channel 11 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12 0x00a608a8 /* MCPB Band pause mapping vector for channel 12 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13 0x00a608ac /* MCPB Band pause mapping vector for channel 13 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14 0x00a608b0 /* MCPB Band pause mapping vector for channel 14 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15 0x00a608b4 /* MCPB Band pause mapping vector for channel 15 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16 0x00a608b8 /* MCPB Band pause mapping vector for channel 16 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17 0x00a608bc /* MCPB Band pause mapping vector for channel 17 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18 0x00a608c0 /* MCPB Band pause mapping vector for channel 18 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19 0x00a608c4 /* MCPB Band pause mapping vector for channel 19 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20 0x00a608c8 /* MCPB Band pause mapping vector for channel 20 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21 0x00a608cc /* MCPB Band pause mapping vector for channel 21 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22 0x00a608d0 /* MCPB Band pause mapping vector for channel 22 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23 0x00a608d4 /* MCPB Band pause mapping vector for channel 23 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24 0x00a608d8 /* MCPB Band pause mapping vector for channel 24 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25 0x00a608dc /* MCPB Band pause mapping vector for channel 25 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26 0x00a608e0 /* MCPB Band pause mapping vector for channel 26 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27 0x00a608e4 /* MCPB Band pause mapping vector for channel 27 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28 0x00a608e8 /* MCPB Band pause mapping vector for channel 28 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29 0x00a608ec /* MCPB Band pause mapping vector for channel 29 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30 0x00a608f0 /* MCPB Band pause mapping vector for channel 30 */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31 0x00a608f4 /* MCPB Band pause mapping vector for channel 31 */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0  0x00a608f8 /* Channel independent Stream processor specific information */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1  0x00a608fc /* Channel independent Stream processor specific information */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR 0x00a60900 /* Set and clear for TMEU channel bypass bit */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31 0x00a60904 /* TMEU channel bypass status */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL           0x00a6090c /* MCPB GPC0 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL 0x00a60910 /* MCPB GPC0 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31     0x00a60914 /* MCPB GPC0 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL           0x00a60918 /* MCPB GPC1 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL 0x00a6091c /* MCPB GPC1 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31     0x00a60920 /* MCPB GPC1 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL           0x00a60924 /* MCPB GPC2 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL 0x00a60928 /* MCPB GPC2 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31     0x00a6092c /* MCPB GPC2 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL           0x00a60930 /* MCPB GPC3 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL 0x00a60934 /* MCPB GPC3 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31     0x00a60938 /* MCPB GPC3 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL           0x00a6093c /* MCPB GPC4 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL 0x00a60940 /* MCPB GPC4 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31     0x00a60944 /* MCPB GPC4 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL           0x00a60948 /* MCPB GPC5 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL 0x00a6094c /* MCPB GPC5 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31     0x00a60950 /* MCPB GPC5 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL           0x00a60954 /* MCPB GPC6 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL 0x00a60958 /* MCPB GPC6 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31     0x00a6095c /* MCPB GPC6 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL           0x00a60960 /* MCPB GPC7 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL 0x00a60964 /* MCPB GPC7 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31     0x00a60968 /* MCPB GPC7 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL           0x00a6096c /* MCPB GPC8 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL 0x00a60970 /* MCPB GPC8 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31     0x00a60974 /* MCPB GPC8 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL           0x00a60978 /* MCPB GPC9 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL 0x00a6097c /* MCPB GPC9 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31     0x00a60980 /* MCPB GPC9 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL          0x00a60984 /* MCPB GPC10 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL 0x00a60988 /* MCPB GPC10 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31    0x00a6098c /* MCPB GPC10 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL          0x00a60990 /* MCPB GPC11 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL 0x00a60994 /* MCPB GPC11 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31    0x00a60998 /* MCPB GPC11 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL          0x00a6099c /* MCPB GPC12 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL 0x00a609a0 /* MCPB GPC12 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31    0x00a609a4 /* MCPB GPC12 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL          0x00a609a8 /* MCPB GPC13 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL 0x00a609ac /* MCPB GPC13 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31    0x00a609b0 /* MCPB GPC13 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL          0x00a609b4 /* MCPB GPC14 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL 0x00a609b8 /* MCPB GPC14 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31    0x00a609bc /* MCPB GPC14 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL          0x00a609c0 /* MCPB GPC15 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL 0x00a609c4 /* MCPB GPC15 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31    0x00a609c8 /* MCPB GPC15 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL          0x00a609cc /* MCPB GPC16 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL 0x00a609d0 /* MCPB GPC16 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31    0x00a609d4 /* MCPB GPC16 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL          0x00a609d8 /* MCPB GPC17 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL 0x00a609dc /* MCPB GPC17 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31    0x00a609e0 /* MCPB GPC17 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL          0x00a609e4 /* MCPB GPC18 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL 0x00a609e8 /* MCPB GPC18 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31    0x00a609ec /* MCPB GPC18 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL          0x00a609f0 /* MCPB GPC19 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL 0x00a609f4 /* MCPB GPC19 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31    0x00a609f8 /* MCPB GPC19 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL          0x00a609fc /* MCPB GPC20 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL 0x00a60a00 /* MCPB GPC20 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31    0x00a60a04 /* MCPB GPC20 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL          0x00a60a08 /* MCPB GPC21 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL 0x00a60a0c /* MCPB GPC21 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31    0x00a60a10 /* MCPB GPC21 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL          0x00a60a14 /* MCPB GPC22 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL 0x00a60a18 /* MCPB GPC22 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31    0x00a60a1c /* MCPB GPC22 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL          0x00a60a20 /* MCPB GPC23 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL 0x00a60a24 /* MCPB GPC23 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31    0x00a60a28 /* MCPB GPC23 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL          0x00a60a2c /* MCPB GPC24 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL 0x00a60a30 /* MCPB GPC24 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31    0x00a60a34 /* MCPB GPC24 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL          0x00a60a38 /* MCPB GPC25 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL 0x00a60a3c /* MCPB GPC25 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31    0x00a60a40 /* MCPB GPC25 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL          0x00a60a44 /* MCPB GPC26 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL 0x00a60a48 /* MCPB GPC26 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31    0x00a60a4c /* MCPB GPC26 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL          0x00a60a50 /* MCPB GPC27 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL 0x00a60a54 /* MCPB GPC27 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31    0x00a60a58 /* MCPB GPC27 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL          0x00a60a5c /* MCPB GPC28 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL 0x00a60a60 /* MCPB GPC28 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31    0x00a60a64 /* MCPB GPC28 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL          0x00a60a68 /* MCPB GPC29 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL 0x00a60a6c /* MCPB GPC29 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31    0x00a60a70 /* MCPB GPC29 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL          0x00a60a74 /* MCPB GPC30 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL 0x00a60a78 /* MCPB GPC30 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31    0x00a60a7c /* MCPB GPC30 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL          0x00a60a80 /* MCPB GPC31 Control information */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL 0x00a60a84 /* MCPB GPC31 Current counter value */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31    0x00a60a88 /* MCPB GPC31 Current pause value */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY      0x00a60a8c /* MCPB Arbitration delay value */
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START  0x00a60a90 /* Address start for CFG DMA SP memory */
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START 0x00a60a94 /* Address start for CFG BBUFF memory */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START 0x00a60a98 /* Address start for TMEU memory */
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START 0x00a60a9c /* Address start for DCPM memory */
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END 0x00a60aa0 /* Address end in configuration memory for each channel */
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS 0x00a60aa4 /* Global control signals */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR 0x00a60aa8 /* Set and clear of Pause at descriptor end clear mask status bit */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 0x00a60aac /* Pause at descriptor end clear mask status bit for all PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR 0x00a60ab0 /* Set and clear of Pause at descriptor end clear mask status bit */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 0x00a60ab4 /* Pause at descriptor end clear mask status bit for all PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR 0x00a60ab8 /* Set and clear for DESCRIPTOR_LESS_MODE_STATUS bit */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31 0x00a60abc /* Descriptorless status for all PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR 0x00a60ac0 /* Set and clear for Zero Byte Transaction Priority bit */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 0x00a60ac4 /* Zero Byte Transaction Priority status for all PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR 0x00a60ac8 /* Set and clear for DCP-only-transaction priority bit */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 0x00a60acc /* DCP-only-transaction priority status for all PB channels */
+#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER 0x00a60ad4 /* Packet gapper controls for SECURITY O/P pipe */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0   0x00a60ae4 /* Manual mode select signals Selection 0 */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1   0x00a60ae8 /* Manual mode select signals Selection 1 */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2   0x00a60aec /* Manual mode select signals Selection 2 */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3   0x00a60af0 /* Manual mode select signals Selection 3 */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0             0x00a60af4 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1             0x00a60af8 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2             0x00a60afc /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3             0x00a60b00 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4             0x00a60b04 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5             0x00a60b08 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6             0x00a60b0c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7             0x00a60b10 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8             0x00a60b14 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9             0x00a60b18 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10            0x00a60b1c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11            0x00a60b20 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12            0x00a60b24 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13            0x00a60b28 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14            0x00a60b2c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15            0x00a60b30 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16            0x00a60b34 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17            0x00a60b38 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18            0x00a60b3c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19            0x00a60b40 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20            0x00a60b44 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21            0x00a60b48 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22            0x00a60b4c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23            0x00a60b50 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24            0x00a60b54 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25            0x00a60b58 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26            0x00a60b5c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27            0x00a60b60 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28            0x00a60b64 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29            0x00a60b68 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30            0x00a60b6c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31            0x00a60b70 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32            0x00a60b74 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33            0x00a60b78 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34            0x00a60b7c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35            0x00a60b80 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36            0x00a60b84 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37            0x00a60b88 /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38            0x00a60b8c /* Debug Register */
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD 0x00a60b90 /* SP Timeout Threshold */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER 0x00a60b94 /* Debug SP Force Recover */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR 0x00a60b98 /* Debug SP TX Overwrite Slot Cmd Auto Recover Overwrite */
+
+/***************************************************************************
+ *RUN_SET_CLEAR - Set and Clear for the RUN bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_reserved0_MASK          0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_reserved0_SHIFT         9
+
+/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_MASK          0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_SHIFT         8
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_SET_CLEAR_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: RUN_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_MASK   0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_RUN_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WAKE_SET - Set for the WAKE bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: WAKE_SET :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_reserved0_MASK               0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_reserved0_SHIFT              9
+
+/* XPT_MEMDMA_MCPB :: WAKE_SET :: SET [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_MASK                     0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_SHIFT                    8
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_SET_DEFAULT                  0x00000000
+
+/* XPT_MEMDMA_MCPB :: WAKE_SET :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_MASK        0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_SET_MCPB_CHANNEL_NUM_DEFAULT     0x00000000
+
+/***************************************************************************
+ *WAKE_MODE_SET_CLEAR - Set and Clear for the WAKE_MODE bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_reserved0_MASK    0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_reserved0_SHIFT   9
+
+/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_MASK    0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_SHIFT   8
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: WAKE_MODE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BUFF_DATA_RDY_SET - Set for the BUFF_DATA_RDY bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_reserved0_MASK      0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_reserved0_SHIFT     9
+
+/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: SET [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_MASK            0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_SHIFT           8
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_SET_DEFAULT         0x00000000
+
+/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_SET :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_SET_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AT_DESC_READ_CLEAR - Clear for the PAUSE_AT_DESC_READ bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_MASK   0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_SHIFT  8
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AT_DESC_END_CLEAR - Clear for the PAUSE_AT_DESC_END bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_MASK    0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_SHIFT   8
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AFTER_GROUP_PACKETS_CLEAR - Clear for the PAUSE_AFTER_GROUP_PACKETS bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CRC_COMPARE_ERROR_PAUSE_CLEAR - Clear for the CRC_COMPARE_ERROR_PAUSE bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MICRO_PAUSE_SET_CLEAR - Set and Clear for the MICRO_PAUSE bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_reserved0_MASK  0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_MASK  0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RUN_STATUS_0_31 - Run status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: RUN_STATUS_0_31 :: RUN_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_RUN_STATUS_0_31_RUN_STATUS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *WAKE_STATUS_0_31 - Wake status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: WAKE_STATUS_0_31 :: WAKE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_MASK     0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_STATUS_0_31_WAKE_STATUS_DEFAULT  0x00000000
+
+/***************************************************************************
+ *WAKE_MODE_STATUS_0_31 - Wake Mode status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: WAKE_MODE_STATUS_0_31 :: WAKE_MODE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_WAKE_MODE_STATUS_0_31_WAKE_MODE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AT_DESC_READ_STATUS_0_31 - Pause at descriptor read status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_READ_STATUS_0_31 :: PAUSE_AT_DESC_READ_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_READ_STATUS_0_31_PAUSE_AT_DESC_READ_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AT_DESC_END_STATUS_0_31 - Pause at descriptor end status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AT_DESC_END_STATUS_0_31 :: PAUSE_AT_DESC_END_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AT_DESC_END_STATUS_0_31_PAUSE_AT_DESC_END_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 - Pause after group of packets status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31 :: PAUSE_AFTER_GROUP_PACKETS_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_PAUSE_AFTER_GROUP_PACKETS_STATUS_0_31_PAUSE_AFTER_GROUP_PACKETS_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 - CRC compare error pause status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: CRC_COMPARE_ERROR_PAUSE_STATUS_0_31 :: CRC_COMPARE_ERROR_PAUSE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_CRC_COMPARE_ERROR_PAUSE_STATUS_0_31_CRC_COMPARE_ERROR_PAUSE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MICRO_PAUSE_STATUS_0_31 - Micro Pause status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MICRO_PAUSE_STATUS_0_31 :: MICRO_PAUSE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MICRO_PAUSE_STATUS_0_31_MICRO_PAUSE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FINAL_PAUSE_STATUS_0_31 - Final Pause status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: FINAL_PAUSE_STATUS_0_31 :: FINAL_PAUSE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_FINAL_PAUSE_STATUS_0_31_FINAL_PAUSE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_PAUSE_STATUS_0_31 - Hardware Pause status for all the PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: HW_PAUSE_STATUS_0_31 :: HW_PAUSE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_HW_PAUSE_STATUS_0_31_HW_PAUSE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DESC_RD_IN_PROGRESS_0_31 - Descriptor Read in Progress status flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DESC_RD_IN_PROGRESS_0_31 :: DESC_RD_IN_PROGRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DESC_RD_IN_PROGRESS_0_31_DESC_RD_IN_PROGRESS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATA_RD_IN_PROGRESS_0_31 - Data Read in Progress status flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DATA_RD_IN_PROGRESS_0_31 :: DATA_RD_IN_PROGRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DATA_RD_IN_PROGRESS_0_31_DATA_RD_IN_PROGRESS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BBUFF_RD_IN_PROGRESS_0_31 - Burst Buffer Read in Progress status flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BBUFF_RD_IN_PROGRESS_0_31 :: BBUFF_RD_IN_PROGRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_RD_IN_PROGRESS_0_31_BBUFF_RD_IN_PROGRESS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LAST_DESC_REACHED_0_31 - Last Descriptor Reached status flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: LAST_DESC_REACHED_0_31 :: LAST_DESC_REACHED [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_LAST_DESC_REACHED_0_31_LAST_DESC_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BUFF_DATA_RDY_0_31 - Buffer data ready status flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BUFF_DATA_RDY_0_31 :: BUFF_DATA_RDY [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BUFF_DATA_RDY_0_31_BUFF_DATA_RDY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FIRST_DATA_RD_OPN_PRIORITY_0_31 - First data read operation priority flag
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: FIRST_DATA_RD_OPN_PRIORITY_0_31 :: FIRST_DATA_RD_OPN_PRIORITY [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_FIRST_DATA_RD_OPN_PRIORITY_0_31_FIRST_DATA_RD_OPN_PRIORITY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RUN_INVALID_SET_CLEAR - Set and Clear Run Invalid
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_reserved0_MASK  0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_MASK  0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: RUN_INVALID_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RUN_INVALID_STATUS_0_31 - Run Invalid status
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: RUN_INVALID_STATUS_0_31 :: RUN_INVALID_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_RUN_INVALID_STATUS_0_31_RUN_INVALID_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CHANNEL_PRIORITY_SET - Set priority for channel arbitration
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: reserved0 [31:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_reserved0_MASK   0xfffffc00
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_reserved0_SHIFT  10
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: SET_PRIORITY [09:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_MASK 0x00000300
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_SET_PRIORITY_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_SET :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_SET_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CHANNEL_PRIORITY_STATUS_0_15 - Channel priority status for channels 0 to 15
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_15_PRIORITY [31:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_MASK 0xc0000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_SHIFT 30
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_15_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_14_PRIORITY [29:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_MASK 0x30000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_SHIFT 28
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_14_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_13_PRIORITY [27:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_MASK 0x0c000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_SHIFT 26
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_13_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_12_PRIORITY [25:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_MASK 0x03000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_SHIFT 24
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_12_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_11_PRIORITY [23:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_MASK 0x00c00000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_SHIFT 22
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_11_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_10_PRIORITY [21:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_MASK 0x00300000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_SHIFT 20
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_10_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_9_PRIORITY [19:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_MASK 0x000c0000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_9_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_8_PRIORITY [17:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_MASK 0x00030000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_8_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_7_PRIORITY [15:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_MASK 0x0000c000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_7_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_6_PRIORITY [13:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_MASK 0x00003000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_6_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_5_PRIORITY [11:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_MASK 0x00000c00
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_5_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_4_PRIORITY [09:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_MASK 0x00000300
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_4_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_3_PRIORITY [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_MASK 0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_3_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_2_PRIORITY [05:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_MASK 0x00000030
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_2_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_1_PRIORITY [03:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_MASK 0x0000000c
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_1_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_0_15 :: CHAN_0_PRIORITY [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_0_15_CHAN_0_PRIORITY_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CHANNEL_PRIORITY_STATUS_16_31 - Channel priority status for channels 16 to 31
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_31_PRIORITY [31:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_MASK 0xc0000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_SHIFT 30
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_31_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_30_PRIORITY [29:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_MASK 0x30000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_SHIFT 28
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_30_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_29_PRIORITY [27:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_MASK 0x0c000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_SHIFT 26
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_29_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_28_PRIORITY [25:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_MASK 0x03000000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_SHIFT 24
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_28_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_27_PRIORITY [23:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_MASK 0x00c00000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_SHIFT 22
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_27_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_26_PRIORITY [21:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_MASK 0x00300000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_SHIFT 20
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_26_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_25_PRIORITY [19:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_MASK 0x000c0000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_25_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_24_PRIORITY [17:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_MASK 0x00030000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_24_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_23_PRIORITY [15:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_MASK 0x0000c000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_23_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_22_PRIORITY [13:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_MASK 0x00003000
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_22_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_21_PRIORITY [11:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_MASK 0x00000c00
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_21_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_20_PRIORITY [09:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_MASK 0x00000300
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_20_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_19_PRIORITY [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_MASK 0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_19_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_18_PRIORITY [05:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_MASK 0x00000030
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_18_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_17_PRIORITY [03:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_MASK 0x0000000c
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_17_PRIORITY_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: CHANNEL_PRIORITY_STATUS_16_31 :: CHAN_16_PRIORITY [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_CHANNEL_PRIORITY_STATUS_16_31_CHAN_16_PRIORITY_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_0 - MCPB Band pause mapping vector for channel 0
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_0 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_0_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_1 - MCPB Band pause mapping vector for channel 1
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_1 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_1_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000002
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_2 - MCPB Band pause mapping vector for channel 2
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_2 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_2_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000004
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_3 - MCPB Band pause mapping vector for channel 3
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_3 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_3_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_4 - MCPB Band pause mapping vector for channel 4
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_4 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_4_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000010
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_5 - MCPB Band pause mapping vector for channel 5
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_5 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_5_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000020
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_6 - MCPB Band pause mapping vector for channel 6
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_6 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_6_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000040
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_7 - MCPB Band pause mapping vector for channel 7
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_7 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_7_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000080
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_8 - MCPB Band pause mapping vector for channel 8
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_8 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_8_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000100
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_9 - MCPB Band pause mapping vector for channel 9
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_9 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_9_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000200
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_10 - MCPB Band pause mapping vector for channel 10
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_10 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_10_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000400
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_11 - MCPB Band pause mapping vector for channel 11
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_11 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_11_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00000800
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_12 - MCPB Band pause mapping vector for channel 12
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_12 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_12_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00001000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_13 - MCPB Band pause mapping vector for channel 13
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_13 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_13_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00002000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_14 - MCPB Band pause mapping vector for channel 14
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_14 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_14_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00004000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_15 - MCPB Band pause mapping vector for channel 15
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_15 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_15_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00008000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_16 - MCPB Band pause mapping vector for channel 16
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_16 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_16_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00010000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_17 - MCPB Band pause mapping vector for channel 17
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_17 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_17_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00020000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_18 - MCPB Band pause mapping vector for channel 18
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_18 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_18_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00040000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_19 - MCPB Band pause mapping vector for channel 19
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_19 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_19_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00080000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_20 - MCPB Band pause mapping vector for channel 20
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_20 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_20_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00100000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_21 - MCPB Band pause mapping vector for channel 21
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_21 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_21_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00200000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_22 - MCPB Band pause mapping vector for channel 22
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_22 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_22_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00400000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_23 - MCPB Band pause mapping vector for channel 23
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_23 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_23_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x00800000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_24 - MCPB Band pause mapping vector for channel 24
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_24 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_24_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x01000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_25 - MCPB Band pause mapping vector for channel 25
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_25 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_25_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x02000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_26 - MCPB Band pause mapping vector for channel 26
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_26 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_26_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x04000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_27 - MCPB Band pause mapping vector for channel 27
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_27 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_27_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x08000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_28 - MCPB Band pause mapping vector for channel 28
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_28 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_28_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x10000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_29 - MCPB Band pause mapping vector for channel 29
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_29 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_29_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x20000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_30 - MCPB Band pause mapping vector for channel 30
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_30 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_30_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x40000000
+
+/***************************************************************************
+ *BAND_PAUSE_MAPPING_VECTOR_31 - MCPB Band pause mapping vector for channel 31
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BAND_PAUSE_MAPPING_VECTOR_31 :: BAND_PAUSE_MAPPING_VECTOR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_BAND_PAUSE_MAPPING_VECTOR_31_BAND_PAUSE_MAPPING_VECTOR_DEFAULT 0x80000000
+
+/***************************************************************************
+ *SP_GLOBAL_CFG_REG0 - Channel independent Stream processor specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: reserved0 [31:25] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_reserved0_MASK     0xfe000000
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_reserved0_SHIFT    25
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_FIRST_BYTE_ECD [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_MASK 0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_SHIFT 24
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_FIRST_BYTE_ECD_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SINGLE_SUB_PAYLOAD_PKT_TYPE_DEFAULT 0x00000006
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SUB_PAYLOAD_PKT_TYPE1 [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE1_DEFAULT 0x00000005
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG0 :: ASF_SUB_PAYLOAD_PKT_TYPE0 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG0_ASF_SUB_PAYLOAD_PKT_TYPE0_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SP_GLOBAL_CFG_REG1 - Channel independent Stream processor specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: reserved0 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_reserved0_MASK     0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_reserved0_SHIFT    24
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_SINGLE_PAYLOAD_PKT_TYPE [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_SINGLE_PAYLOAD_PKT_TYPE_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_PAYLOAD_PKT_TYPE1 [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE1_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: SP_GLOBAL_CFG_REG1 :: ASF_PAYLOAD_PKT_TYPE0 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_SP_GLOBAL_CFG_REG1_ASF_PAYLOAD_PKT_TYPE0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TMEU_CHANNEL_BYPASS_SET_CLEAR - Set and clear for TMEU channel bypass bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TMEU_CHANNEL_BYPASS_STATUS_0_31 - TMEU channel bypass status
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: TMEU_CHANNEL_BYPASS_STATUS_0_31 :: BYPASS_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_CHANNEL_BYPASS_STATUS_0_31_BYPASS_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC0_CTRL - MCPB GPC0 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC0_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC0_CURR_COUNTER_VAL - MCPB GPC0 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC0_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC0_PAUSE_0_31 - MCPB GPC0 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC0_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC0_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC1_CTRL - MCPB GPC1 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC1_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC1_CURR_COUNTER_VAL - MCPB GPC1 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC1_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC1_PAUSE_0_31 - MCPB GPC1 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC1_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC1_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC2_CTRL - MCPB GPC2 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC2_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC2_CURR_COUNTER_VAL - MCPB GPC2 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC2_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC2_PAUSE_0_31 - MCPB GPC2 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC2_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC2_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC3_CTRL - MCPB GPC3 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC3_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC3_CURR_COUNTER_VAL - MCPB GPC3 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC3_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC3_PAUSE_0_31 - MCPB GPC3 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC3_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC3_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC4_CTRL - MCPB GPC4 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC4_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC4_CURR_COUNTER_VAL - MCPB GPC4 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC4_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC4_PAUSE_0_31 - MCPB GPC4 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC4_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC4_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC5_CTRL - MCPB GPC5 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC5_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC5_CURR_COUNTER_VAL - MCPB GPC5 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC5_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC5_PAUSE_0_31 - MCPB GPC5 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC5_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC5_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC6_CTRL - MCPB GPC6 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC6_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC6_CURR_COUNTER_VAL - MCPB GPC6 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC6_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC6_PAUSE_0_31 - MCPB GPC6 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC6_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC6_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC7_CTRL - MCPB GPC7 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC7_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC7_CURR_COUNTER_VAL - MCPB GPC7 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC7_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC7_PAUSE_0_31 - MCPB GPC7 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC7_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC7_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC8_CTRL - MCPB GPC8 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC8_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC8_CURR_COUNTER_VAL - MCPB GPC8 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC8_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC8_PAUSE_0_31 - MCPB GPC8 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC8_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC8_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC9_CTRL - MCPB GPC9 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_MASK           0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_SHIFT          26
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_TIMEBASE_SEL_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_MASK           0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_SHIFT          23
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_PACING_SPEED_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_MASK           0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_SHIFT          22
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_COUNTER_MODE_DEFAULT        0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_SHIFT      21
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_MODE_DEFAULT    0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_SHIFT        20
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_EN_DEFAULT      0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC9_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_MASK      0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CTRL_SKIP_REPEAT_COUNT_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GPC9_CURR_COUNTER_VAL - MCPB GPC9 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC9_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_SHIFT   0
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC9_PAUSE_0_31 - MCPB GPC9 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC9_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_MASK        0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_SHIFT       0
+#define BCHP_XPT_MEMDMA_MCPB_GPC9_PAUSE_0_31_GPC_PAUSE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *GPC10_CTRL - MCPB GPC10 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC10_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC10_CURR_COUNTER_VAL - MCPB GPC10 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC10_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC10_PAUSE_0_31 - MCPB GPC10 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC10_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC10_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC11_CTRL - MCPB GPC11 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC11_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC11_CURR_COUNTER_VAL - MCPB GPC11 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC11_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC11_PAUSE_0_31 - MCPB GPC11 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC11_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC11_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC12_CTRL - MCPB GPC12 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC12_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC12_CURR_COUNTER_VAL - MCPB GPC12 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC12_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC12_PAUSE_0_31 - MCPB GPC12 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC12_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC12_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC13_CTRL - MCPB GPC13 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC13_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC13_CURR_COUNTER_VAL - MCPB GPC13 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC13_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC13_PAUSE_0_31 - MCPB GPC13 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC13_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC13_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC14_CTRL - MCPB GPC14 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC14_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC14_CURR_COUNTER_VAL - MCPB GPC14 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC14_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC14_PAUSE_0_31 - MCPB GPC14 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC14_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC14_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC15_CTRL - MCPB GPC15 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC15_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC15_CURR_COUNTER_VAL - MCPB GPC15 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC15_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC15_PAUSE_0_31 - MCPB GPC15 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC15_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC15_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC16_CTRL - MCPB GPC16 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC16_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC16_CURR_COUNTER_VAL - MCPB GPC16 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC16_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC16_PAUSE_0_31 - MCPB GPC16 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC16_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC16_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC17_CTRL - MCPB GPC17 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC17_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC17_CURR_COUNTER_VAL - MCPB GPC17 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC17_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC17_PAUSE_0_31 - MCPB GPC17 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC17_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC17_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC18_CTRL - MCPB GPC18 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC18_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC18_CURR_COUNTER_VAL - MCPB GPC18 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC18_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC18_PAUSE_0_31 - MCPB GPC18 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC18_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC18_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC19_CTRL - MCPB GPC19 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC19_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC19_CURR_COUNTER_VAL - MCPB GPC19 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC19_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC19_PAUSE_0_31 - MCPB GPC19 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC19_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC19_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC20_CTRL - MCPB GPC20 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC20_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC20_CURR_COUNTER_VAL - MCPB GPC20 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC20_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC20_PAUSE_0_31 - MCPB GPC20 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC20_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC20_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC21_CTRL - MCPB GPC21 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC21_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC21_CURR_COUNTER_VAL - MCPB GPC21 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC21_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC21_PAUSE_0_31 - MCPB GPC21 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC21_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC21_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC22_CTRL - MCPB GPC22 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC22_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC22_CURR_COUNTER_VAL - MCPB GPC22 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC22_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC22_PAUSE_0_31 - MCPB GPC22 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC22_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC22_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC23_CTRL - MCPB GPC23 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC23_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC23_CURR_COUNTER_VAL - MCPB GPC23 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC23_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC23_PAUSE_0_31 - MCPB GPC23 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC23_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC23_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC24_CTRL - MCPB GPC24 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC24_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC24_CURR_COUNTER_VAL - MCPB GPC24 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC24_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC24_PAUSE_0_31 - MCPB GPC24 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC24_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC24_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC25_CTRL - MCPB GPC25 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC25_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC25_CURR_COUNTER_VAL - MCPB GPC25 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC25_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC25_PAUSE_0_31 - MCPB GPC25 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC25_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC25_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC26_CTRL - MCPB GPC26 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC26_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC26_CURR_COUNTER_VAL - MCPB GPC26 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC26_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC26_PAUSE_0_31 - MCPB GPC26 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC26_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC26_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC27_CTRL - MCPB GPC27 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC27_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC27_CURR_COUNTER_VAL - MCPB GPC27 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC27_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC27_PAUSE_0_31 - MCPB GPC27 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC27_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC27_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC28_CTRL - MCPB GPC28 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC28_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC28_CURR_COUNTER_VAL - MCPB GPC28 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC28_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC28_PAUSE_0_31 - MCPB GPC28 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC28_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC28_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC29_CTRL - MCPB GPC29 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC29_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC29_CURR_COUNTER_VAL - MCPB GPC29 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC29_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC29_PAUSE_0_31 - MCPB GPC29 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC29_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC29_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC30_CTRL - MCPB GPC30 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC30_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC30_CURR_COUNTER_VAL - MCPB GPC30 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC30_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC30_PAUSE_0_31 - MCPB GPC30 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC30_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC30_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *GPC31_CTRL - MCPB GPC31 Control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: FREE_RUN_OR_LOCKED_TIMEBASE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_SHIFT 31
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_FREE_RUN_OR_LOCKED_TIMEBASE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: TIMEBASE_SEL [30:26] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_MASK          0x7c000000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_SHIFT         26
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_TIMEBASE_SEL_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: PACING_SPEED [25:23] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_MASK          0x03800000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_SHIFT         23
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_PACING_SPEED_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: COUNTER_MODE [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_MASK          0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_SHIFT         22
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_COUNTER_MODE_DEFAULT       0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_SHIFT     21
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_MODE_DEFAULT   0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_SHIFT       20
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_EN_DEFAULT     0x00000000
+
+/* XPT_MEMDMA_MCPB :: GPC31_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_MASK     0x000fffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CTRL_SKIP_REPEAT_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *GPC31_CURR_COUNTER_VAL - MCPB GPC31 Current counter value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC31_CURR_COUNTER_VAL :: COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_MASK   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_SHIFT  0
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_CURR_COUNTER_VAL_COUNTER_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GPC31_PAUSE_0_31 - MCPB GPC31 Current pause value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GPC31_PAUSE_0_31 :: GPC_PAUSE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_GPC31_PAUSE_0_31_GPC_PAUSE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *TMEU_ARB_DELAY - MCPB Arbitration delay value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: TMEU_ARB_DELAY :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_reserved0_MASK         0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_reserved0_SHIFT        16
+
+/* XPT_MEMDMA_MCPB :: TMEU_ARB_DELAY :: ARB_DELAY [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_MASK         0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_SHIFT        0
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_ARB_DELAY_ARB_DELAY_DEFAULT      0x000000c8
+
+/***************************************************************************
+ *DMA_MEM_ADDR_START - Address start for CFG DMA SP memory
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DMA_MEM_ADDR_START :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_reserved0_MASK     0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_reserved0_SHIFT    8
+
+/* XPT_MEMDMA_MCPB :: DMA_MEM_ADDR_START :: ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_MASK       0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_SHIFT      0
+#define BCHP_XPT_MEMDMA_MCPB_DMA_MEM_ADDR_START_ADDRESS_DEFAULT    0x00000000
+
+/***************************************************************************
+ *BBUFF_MEM_ADDR_START - Address start for CFG BBUFF memory
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: BBUFF_MEM_ADDR_START :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_reserved0_MASK   0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_reserved0_SHIFT  8
+
+/* XPT_MEMDMA_MCPB :: BBUFF_MEM_ADDR_START :: ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_MASK     0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_SHIFT    0
+#define BCHP_XPT_MEMDMA_MCPB_BBUFF_MEM_ADDR_START_ADDRESS_DEFAULT  0x00000032
+
+/***************************************************************************
+ *TMEU_MEM_ADDR_START - Address start for TMEU memory
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: TMEU_MEM_ADDR_START :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_reserved0_MASK    0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_reserved0_SHIFT   8
+
+/* XPT_MEMDMA_MCPB :: TMEU_MEM_ADDR_START :: ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_MASK      0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_TMEU_MEM_ADDR_START_ADDRESS_DEFAULT   0x00000038
+
+/***************************************************************************
+ *DCPM_MEM_ADDR_START - Address start for DCPM memory
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DCPM_MEM_ADDR_START :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_reserved0_MASK    0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_reserved0_SHIFT   8
+
+/* XPT_MEMDMA_MCPB :: DCPM_MEM_ADDR_START :: ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_MASK      0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_DCPM_MEM_ADDR_START_ADDRESS_DEFAULT   0x00000048
+
+/***************************************************************************
+ *PER_CH_MEM_ADDR_END - Address end in configuration memory for each channel
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: PER_CH_MEM_ADDR_END :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_reserved0_MASK    0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_reserved0_SHIFT   8
+
+/* XPT_MEMDMA_MCPB :: PER_CH_MEM_ADDR_END :: ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_MASK      0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_SHIFT     0
+#define BCHP_XPT_MEMDMA_MCPB_PER_CH_MEM_ADDR_END_ADDRESS_DEFAULT   0x00000058
+
+/***************************************************************************
+ *GLOBAL_CTRL_SIGNALS - Global control signals
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: GLOBAL_CTRL_SIGNALS :: reserved_for_padding0 [31:01] */
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_reserved_for_padding0_MASK 0xfffffffe
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_reserved_for_padding0_SHIFT 1
+
+/* XPT_MEMDMA_MCPB :: GLOBAL_CTRL_SIGNALS :: CS_EN_ALWAYS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_GLOBAL_CTRL_SIGNALS_CS_EN_ALWAYS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR - Set and clear of Pause at descriptor end clear mask status bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: reserved_for_padding0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_reserved_for_padding0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 - Pause at descriptor end clear mask status bit for all PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31 :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_MEMDMA_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR - Set and clear of Pause at descriptor end clear mask status bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: reserved_for_padding0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_reserved_for_padding0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 - Pause at descriptor end clear mask status bit for all PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31 :: MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_0_31_MASK_CLEAR_PAUSE_AT_DESC_END_FROM_HOST_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DESCRIPTOR_LESS_MODE_SET_CLEAR - Set and clear for DESCRIPTOR_LESS_MODE_STATUS bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: reserved0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_reserved0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_reserved0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DESCRIPTOR_LESS_MODE_STATUS_0_31 - Descriptorless status for all PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DESCRIPTOR_LESS_MODE_STATUS_0_31 :: DESCRIPTOR_LESS_MODE_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DESCRIPTOR_LESS_MODE_STATUS_0_31_DESCRIPTOR_LESS_MODE_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR - Set and clear for Zero Byte Transaction Priority bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: reserved_for_padding0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_reserved_for_padding0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 - Zero Byte Transaction Priority status for all PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31 :: ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_0_31_ARBITER_ZERO_BYTE_TRANS_PRIORITY_STATUS_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR - Set and clear for DCP-only-transaction priority bit
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: reserved_for_padding0 [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_reserved_for_padding0_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_reserved_for_padding0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: SET_CLEAR [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_SET_CLEAR_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR :: MCPB_CHANNEL_NUM [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_SET_CLEAR_MCPB_CHANNEL_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 - DCP-only-transaction priority status for all PB channels
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31 :: ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_0_31_ARBITER_SEND_DCP_ONLY_TRANS_AS_HIGH_PRIORITY_STATUS_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *SEC_OUTPUT_PIPE_PACKET_GAPPER - Packet gapper controls for SECURITY O/P pipe
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: SEC_OUTPUT_PIPE_PACKET_GAPPER :: BLOCK_OUT_COUNT [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_SEC_OUTPUT_PIPE_PACKET_GAPPER_BLOCK_OUT_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MANUAL_MODE_SEL_0 - Manual mode select signals Selection 0
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved0_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved0_SHIFT     19
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T4 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T4 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved1_MASK      0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved1_SHIFT     15
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T3 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T3 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: reserved2 [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved2_MASK      0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_reserved2_SHIFT     11
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T2 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T2 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T1 [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_SHIFT 7
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T1 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_SHIFT 5
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: FORCE_TS_CONFIG_T0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_SHIFT 3
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: RESET_SP_PARSER_T0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_SHIFT 1
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_RESET_SP_PARSER_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_0 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_0_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MANUAL_MODE_SEL_1 - Manual mode select signals Selection 1
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved0_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved0_SHIFT     19
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T4 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T4 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved1_MASK      0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved1_SHIFT     15
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T3 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T3 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: reserved2 [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved2_MASK      0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_reserved2_SHIFT     11
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T2 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T2 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T1 [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_SHIFT 7
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T1 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_SHIFT 5
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: FORCE_TS_CONFIG_T0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_SHIFT 3
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: RESET_SP_PARSER_T0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_SHIFT 1
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_RESET_SP_PARSER_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_1 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_1_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MANUAL_MODE_SEL_2 - Manual mode select signals Selection 2
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved0_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved0_SHIFT     19
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T4 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T4 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved1_MASK      0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved1_SHIFT     15
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T3 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T3 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: reserved2 [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved2_MASK      0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_reserved2_SHIFT     11
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T2 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T2 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T1 [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_SHIFT 7
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T1 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_SHIFT 5
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: FORCE_TS_CONFIG_T0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_SHIFT 3
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: RESET_SP_PARSER_T0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_SHIFT 1
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_RESET_SP_PARSER_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_2 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_2_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MANUAL_MODE_SEL_3 - Manual mode select signals Selection 3
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved0_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved0_SHIFT     19
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T4 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_SHIFT 18
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T4 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_SHIFT 17
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T4 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_SHIFT 16
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T4_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved1_MASK      0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved1_SHIFT     15
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T3 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_SHIFT 14
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T3 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_SHIFT 13
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T3 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T3_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: reserved2 [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved2_MASK      0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_reserved2_SHIFT     11
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T2 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T2 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_SHIFT 9
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T2 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T2_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T1 [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_SHIFT 7
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T1 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T1 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_SHIFT 5
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_BEFORE_CUR_DATA_T1_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: FORCE_TS_CONFIG_T0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_SHIFT 3
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_FORCE_TS_CONFIG_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: PUSH_RESIDUAL_BYTES_T0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_PUSH_RESIDUAL_BYTES_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: RESET_SP_PARSER_T0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_SHIFT 1
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_RESET_SP_PARSER_T0_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: MANUAL_MODE_SEL_3 :: SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_MANUAL_MODE_SEL_3_SEND_0_BYTE_TRANS_WITH_PREV_DESC_INFO_T0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DEBUG_0 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_0 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_0_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_1 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_1 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_1_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_2 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_2 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_2_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_3 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_3 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_3_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_4 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_4 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_4_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_5 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_8 [31:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_8_MASK                  0xf8000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_8_SHIFT                 27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: reserved0 [26:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved0_MASK                0x07c00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved0_SHIFT               22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_7 [21:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_7_MASK                  0x00380000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_7_SHIFT                 19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_6 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_6_MASK                  0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_6_SHIFT                 18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_5 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_5_MASK                  0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_5_SHIFT                 17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_4 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_4_MASK                  0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_4_SHIFT                 16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: reserved1 [15:10] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved1_MASK                0x0000fc00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_reserved1_SHIFT               10
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_3 [09:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_3_MASK                  0x000003e0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_3_SHIFT                 5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_2 [04:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_2_MASK                  0x0000001c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_2_SHIFT                 2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_1 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_1_MASK                  0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_1_SHIFT                 1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_5 :: VALUE_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_0_MASK                  0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_5_VALUE_0_SHIFT                 0
+
+/***************************************************************************
+ *DEBUG_6 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_6 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_6_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_7 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: reserved0 [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved0_MASK                0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved0_SHIFT               28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_9 [27:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_9_MASK                  0x0f800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_9_SHIFT                 23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_8 [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_8_MASK                  0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_8_SHIFT                 22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_7 [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_7_MASK                  0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_7_SHIFT                 21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_6 [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_6_MASK                  0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_6_SHIFT                 20
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_5 [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_5_MASK                  0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_5_SHIFT                 19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_4 [18:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_4_MASK                  0x00070000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_4_SHIFT                 16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: reserved1 [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved1_MASK                0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_reserved1_SHIFT               11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_3 [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_3_MASK                  0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_3_SHIFT                 6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_2 [05:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_2_MASK                  0x0000003c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_2_SHIFT                 2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_1 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_1_MASK                  0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_1_SHIFT                 1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_7 :: VALUE_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_0_MASK                  0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_7_VALUE_0_SHIFT                 0
+
+/***************************************************************************
+ *DEBUG_8 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_8 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8_VALUE_MASK                    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_8_VALUE_SHIFT                   0
+
+/***************************************************************************
+ *DEBUG_9 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_9 :: reserved0 [31:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_reserved0_MASK                0xffffe000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_reserved0_SHIFT               13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_3 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_3_MASK                  0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_3_SHIFT                 12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_2 [11:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_2_MASK                  0x00000f00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_2_SHIFT                 8
+
+/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_1 [07:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_1_MASK                  0x000000f8
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_1_SHIFT                 3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_9 :: VALUE_0 [02:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_0_MASK                  0x00000007
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_9_VALUE_0_SHIFT                 0
+
+/***************************************************************************
+ *DEBUG_10 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W0_OUT_DMA_END [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_DMA_END_MASK       0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_DMA_END_SHIFT      31
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W1_OUT_DMA_END [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_DMA_END_MASK       0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_DMA_END_SHIFT      30
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W2_OUT_DMA_END [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_DMA_END_MASK       0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_DMA_END_SHIFT      29
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W3_OUT_DMA_END [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_DMA_END_MASK       0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_DMA_END_SHIFT      28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_DMA_END [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_DMA_END_MASK       0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_DMA_END_SHIFT      27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W0_OUT_READY [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_READY_MASK         0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W0_OUT_READY_SHIFT        26
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W1_OUT_READY [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_READY_MASK         0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W1_OUT_READY_SHIFT        25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W2_OUT_READY [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_READY_MASK         0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W2_OUT_READY_SHIFT        24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W3_OUT_READY [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_READY_MASK         0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W3_OUT_READY_SHIFT        23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_READY [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_READY_MASK         0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_READY_SHIFT        22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W4_OUT_ACCEPT [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_ACCEPT_MASK        0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W4_OUT_ACCEPT_SHIFT       21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W5_IN_ACCEPT [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_ACCEPT_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_ACCEPT_SHIFT        20
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_W5_IN_READY [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_READY_MASK          0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_W5_IN_READY_SHIFT         19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_STATE [18:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_STATE_MASK                0x0007e000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_STATE_SHIFT               13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_BAND_ID [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_BAND_ID_MASK              0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_BAND_ID_SHIFT             5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_PKT_BUF2SP_DONE [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_PKT_BUF2SP_DONE_MASK      0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_PKT_BUF2SP_DONE_SHIFT     4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_CFG_DCP2SP_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DCP2SP_DONE_MASK      0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DCP2SP_DONE_SHIFT     3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_CFG_DMA_SP2SP_DONE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DMA_SP2SP_DONE_MASK   0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_CFG_DMA_SP2SP_DONE_SHIFT  2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_SMU2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SMU2SP_DONE_MASK          0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SMU2SP_DONE_SHIFT         1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_10 :: TS_SP2DMA_START [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SP2DMA_START_MASK         0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_10_TS_SP2DMA_START_SHIFT        0
+
+/***************************************************************************
+ *DEBUG_11 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_reserved0_MASK               0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_reserved0_SHIFT              8
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PT_SEARCH_IN_PROGRESS [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_IN_PROGRESS_SHIFT 7
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PT_SEARCH_DONE [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_DONE_MASK       0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PT_SEARCH_DONE_SHIFT      6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_DMA_END [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_DMA_END_MASK              0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_DMA_END_SHIFT             5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PKT_END [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_END_MASK              0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_END_SHIFT             4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PKT_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_DONE_MASK             0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PKT_DONE_SHIFT            3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_LAST_TRANS [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_LAST_TRANS_MASK           0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_LAST_TRANS_SHIFT          2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_SKIP_PKT_BUF2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_SKIP_PKT_BUF2SP_DONE_SHIFT 1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_11 :: TS_PARSING_IN_PROGRESS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PARSING_IN_PROGRESS_MASK  0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_11_TS_PARSING_IN_PROGRESS_SHIFT 0
+
+/***************************************************************************
+ *DEBUG_12 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W0_OUT_DMA_END [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_DMA_END_MASK      0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_DMA_END_SHIFT     31
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W1_OUT_DMA_END [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_DMA_END_MASK      0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_DMA_END_SHIFT     30
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W2_OUT_DMA_END [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_DMA_END_MASK      0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_DMA_END_SHIFT     29
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W3_OUT_DMA_END [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_DMA_END_MASK      0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_DMA_END_SHIFT     28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_DMA_END [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_DMA_END_MASK      0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_DMA_END_SHIFT     27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W0_OUT_READY [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_READY_MASK        0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W0_OUT_READY_SHIFT       26
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W1_OUT_READY [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_READY_MASK        0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W1_OUT_READY_SHIFT       25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W2_OUT_READY [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_READY_MASK        0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W2_OUT_READY_SHIFT       24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W3_OUT_READY [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_READY_MASK        0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W3_OUT_READY_SHIFT       23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_READY [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_READY_MASK        0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_READY_SHIFT       22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W4_OUT_ACCEPT [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_ACCEPT_MASK       0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W4_OUT_ACCEPT_SHIFT      21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W5_IN_ACCEPT [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_ACCEPT_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_ACCEPT_SHIFT       20
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_W5_IN_READY [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_READY_MASK         0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_W5_IN_READY_SHIFT        19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_STATE [18:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_STATE_MASK               0x0007e000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_STATE_SHIFT              13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_BAND_ID [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_BAND_ID_MASK             0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_BAND_ID_SHIFT            5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_PKT_BUF2SP_DONE [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_PKT_BUF2SP_DONE_MASK     0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_PKT_BUF2SP_DONE_SHIFT    4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_CFG_DCP2SP_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DCP2SP_DONE_MASK     0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DCP2SP_DONE_SHIFT    3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_CFG_DMA_SP2SP_DONE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DMA_SP2SP_DONE_MASK  0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_CFG_DMA_SP2SP_DONE_SHIFT 2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_SMU2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SMU2SP_DONE_MASK         0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SMU2SP_DONE_SHIFT        1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_12 :: PES_SP2DMA_START [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SP2DMA_START_MASK        0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_12_PES_SP2DMA_START_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_13 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: reserved0 [31:10] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_reserved0_MASK               0xfffffc00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_reserved0_SHIFT              10
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_SET_START_DCP [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SET_START_DCP_MASK       0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SET_START_DCP_SHIFT      9
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_VALID_PUSH_RESIDUAL_DATA [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_VALID_PUSH_RESIDUAL_DATA_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_VALID_PUSH_RESIDUAL_DATA_SHIFT 8
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PT_SEARCH_IN_PROGRESS [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_IN_PROGRESS_SHIFT 7
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PT_SEARCH_DONE [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_DONE_MASK      0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PT_SEARCH_DONE_SHIFT     6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_DMA_END [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_DMA_END_MASK             0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_DMA_END_SHIFT            5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PKT_END [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_END_MASK             0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_END_SHIFT            4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PKT_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_DONE_MASK            0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PKT_DONE_SHIFT           3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_LAST_TRANS [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_LAST_TRANS_MASK          0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_LAST_TRANS_SHIFT         2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_SKIP_PKT_BUF2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_SKIP_PKT_BUF2SP_DONE_SHIFT 1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_13 :: PES_PARSING_IN_PROGRESS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PARSING_IN_PROGRESS_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_13_PES_PARSING_IN_PROGRESS_SHIFT 0
+
+/***************************************************************************
+ *DEBUG_14 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: reserved0 [31:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved0_MASK               0xf8000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved0_SHIFT              27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_13 [26:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_13_MASK                0x07c00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_13_SHIFT               22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_12 [21:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_12_MASK                0x00380000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_12_SHIFT               19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: reserved1 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved1_MASK               0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_reserved1_SHIFT              18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_11 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_11_MASK                0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_11_SHIFT               17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_10 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_10_MASK                0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_10_SHIFT               16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_9 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_9_MASK                 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_9_SHIFT                15
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_8 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_8_MASK                 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_8_SHIFT                14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_7 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_7_MASK                 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_7_SHIFT                13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_6 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_6_MASK                 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_6_SHIFT                12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_5 [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_5_MASK                 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_5_SHIFT                11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_4 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_4_MASK                 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_4_SHIFT                10
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_3 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_3_MASK                 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_3_SHIFT                9
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_2 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_2_MASK                 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_2_SHIFT                8
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_1 [07:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_1_MASK                 0x000000f8
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_1_SHIFT                3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_14 :: VALUE_0 [02:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_0_MASK                 0x00000007
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_14_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_15 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: reserved0 [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved0_MASK               0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved0_SHIFT              28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_5 [27:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_5_MASK                 0x0fc00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_5_SHIFT                22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_4 [21:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_4_MASK                 0x003c0000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_4_SHIFT                18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_3 [17:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_3_MASK                 0x00030000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_3_SHIFT                16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: reserved1 [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved1_MASK               0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_reserved1_SHIFT              11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_2 [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_2_MASK                 0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_2_SHIFT                6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_1 [05:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_1_MASK                 0x0000003c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_1_SHIFT                2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_15 :: VALUE_0 [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_0_MASK                 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_15_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_16 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_16 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_16_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_17 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_17 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_17_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_18 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_18 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_18_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_19 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_19 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_19_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_20 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_20 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_20_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_21 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_21 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_21_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_22 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_22 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_22_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_23 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_23 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_23_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_24 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_24 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_24_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_25 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_25 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_25_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_26 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: reserved0 [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved0_MASK               0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved0_SHIFT              28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_5 [27:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_5_MASK                 0x0fc00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_5_SHIFT                22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_4 [21:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_4_MASK                 0x003c0000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_4_SHIFT                18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_3 [17:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_3_MASK                 0x00030000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_3_SHIFT                16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: reserved1 [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved1_MASK               0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_reserved1_SHIFT              11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_2 [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_2_MASK                 0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_2_SHIFT                6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_1 [05:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_1_MASK                 0x0000003c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_1_SHIFT                2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_26 :: VALUE_0 [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_0_MASK                 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_26_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_27 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W0_OUT_DMA_END [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_DMA_END_MASK       0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_DMA_END_SHIFT      31
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W1_OUT_DMA_END [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_DMA_END_MASK       0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_DMA_END_SHIFT      30
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W2_OUT_DMA_END [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_DMA_END_MASK       0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_DMA_END_SHIFT      29
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W3_OUT_DMA_END [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_DMA_END_MASK       0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_DMA_END_SHIFT      28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W4_OUT_DMA_END [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_DMA_END_MASK       0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_DMA_END_SHIFT      27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_DMA_END [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_DMA_END_MASK       0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_DMA_END_SHIFT      26
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W0_OUT_READY [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_READY_MASK         0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W0_OUT_READY_SHIFT        25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W1_OUT_READY [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_READY_MASK         0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W1_OUT_READY_SHIFT        24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W2_OUT_READY [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_READY_MASK         0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W2_OUT_READY_SHIFT        23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W3_OUT_READY [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_READY_MASK         0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W3_OUT_READY_SHIFT        22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W4_OUT_READY [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_READY_MASK         0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W4_OUT_READY_SHIFT        21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_READY [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_READY_MASK         0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_READY_SHIFT        20
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W5_OUT_ACCEPT [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_ACCEPT_MASK        0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W5_OUT_ACCEPT_SHIFT       19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W6_IN_ACCEPT [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_ACCEPT_MASK         0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_ACCEPT_SHIFT        18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_W6_IN_READY [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_READY_MASK          0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_W6_IN_READY_SHIFT         17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_STATE [16:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_STATE_MASK                0x0001e000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_STATE_SHIFT               13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_BAND_ID [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_BAND_ID_MASK              0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_BAND_ID_SHIFT             5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_PKT_BUF2SP_DONE [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_PKT_BUF2SP_DONE_MASK      0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_PKT_BUF2SP_DONE_SHIFT     4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_CFG_DCP2SP_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DCP2SP_DONE_MASK      0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DCP2SP_DONE_SHIFT     3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_CFG_DMA_SP2SP_DONE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DMA_SP2SP_DONE_MASK   0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_CFG_DMA_SP2SP_DONE_SHIFT  2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_SMU2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SMU2SP_DONE_MASK          0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SMU2SP_DONE_SHIFT         1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_27 :: BM_SP2DMA_START [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SP2DMA_START_MASK         0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_27_BM_SP2DMA_START_SHIFT        0
+
+/***************************************************************************
+ *DEBUG_28 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: reserved0 [31:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_reserved0_MASK               0xfffff000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_reserved0_SHIFT              12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_NUM_BYTES [11:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_NUM_BYTES_MASK            0x00000ff0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_NUM_BYTES_SHIFT           4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_PT_SEARCH_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PT_SEARCH_DONE_MASK       0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PT_SEARCH_DONE_SHIFT      3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_DMA_END [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_DMA_END_MASK              0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_DMA_END_SHIFT             2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_LAST_TRANS [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_LAST_TRANS_MASK           0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_LAST_TRANS_SHIFT          1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_28 :: BM_PARSING_IN_PROGRESS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PARSING_IN_PROGRESS_MASK  0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_28_BM_PARSING_IN_PROGRESS_SHIFT 0
+
+/***************************************************************************
+ *DEBUG_29 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_29 :: reserved0 [31:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_reserved0_MASK               0xfffff800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_reserved0_SHIFT              11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_2 [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_2_MASK                 0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_2_SHIFT                6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_1 [05:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_1_MASK                 0x0000003c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_1_SHIFT                2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_29 :: VALUE_0 [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_0_MASK                 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_29_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_30 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_30 :: VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30_VALUE_MASK                   0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_30_VALUE_SHIFT                  0
+
+/***************************************************************************
+ *DEBUG_31 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_12 [31:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_12_MASK                0xf8000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_12_SHIFT               27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_11 [26:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_11_MASK                0x07fc0000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_11_SHIFT               18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_10 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_10_MASK                0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_10_SHIFT               17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_9 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_9_MASK                 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_9_SHIFT                16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_8 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_8_MASK                 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_8_SHIFT                15
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_7 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_7_MASK                 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_7_SHIFT                14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_6 [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_6_MASK                 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_6_SHIFT                13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_5 [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_5_MASK                 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_5_SHIFT                12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_4 [11:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_4_MASK                 0x00000ff0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_4_SHIFT                4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_3 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_3_MASK                 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_3_SHIFT                3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_2 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_2_MASK                 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_2_SHIFT                2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_1 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_1_MASK                 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_1_SHIFT                1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_31 :: VALUE_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_0_MASK                 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_31_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_32 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: reserved0 [31:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_reserved0_MASK               0xffe00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_reserved0_SHIFT              21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_8 [20:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_8_MASK                 0x001f0000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_8_SHIFT                16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_7 [15:07] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_7_MASK                 0x0000ff80
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_7_SHIFT                7
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_6 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_6_MASK                 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_6_SHIFT                6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_5 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_5_MASK                 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_5_SHIFT                5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_4 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_4_MASK                 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_4_SHIFT                4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_3 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_3_MASK                 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_3_SHIFT                3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_2 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_2_MASK                 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_2_SHIFT                2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_1 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_1_MASK                 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_1_SHIFT                1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_32 :: VALUE_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_0_MASK                 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_32_VALUE_0_SHIFT                0
+
+/***************************************************************************
+ *DEBUG_33 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: reserved0 [31:26] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_reserved0_MASK               0xfc000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_reserved0_SHIFT              26
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W0_OUT_DMA_END [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_DMA_END_MASK      0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_DMA_END_SHIFT     25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W1_OUT_DMA_END [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_DMA_END_MASK      0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_DMA_END_SHIFT     24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W2_OUT_DMA_END [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_DMA_END_MASK      0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_DMA_END_SHIFT     23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W3_OUT_DMA_END [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_DMA_END_MASK      0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_DMA_END_SHIFT     22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_DMA_END [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_DMA_END_MASK      0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_DMA_END_SHIFT     21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W0_OUT_READY [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_READY_MASK        0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W0_OUT_READY_SHIFT       20
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W1_OUT_READY [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_READY_MASK        0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W1_OUT_READY_SHIFT       19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W2_OUT_READY [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_READY_MASK        0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W2_OUT_READY_SHIFT       18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W3_OUT_READY [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_READY_MASK        0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W3_OUT_READY_SHIFT       17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_READY [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_READY_MASK        0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_READY_SHIFT       16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W4_OUT_ACCEPT [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_ACCEPT_MASK       0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W4_OUT_ACCEPT_SHIFT      15
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W5_IN_ACCEPT [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_ACCEPT_MASK        0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_ACCEPT_SHIFT       14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_W5_IN_READY [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_READY_MASK         0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_W5_IN_READY_SHIFT        13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_BAND_ID [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_BAND_ID_MASK             0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_BAND_ID_SHIFT            5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_PKT_BUF2SP_DONE [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_PKT_BUF2SP_DONE_MASK     0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_PKT_BUF2SP_DONE_SHIFT    4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_CFG_DCP2SP_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DCP2SP_DONE_MASK     0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DCP2SP_DONE_SHIFT    3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_CFG_DMA_SP2SP_DONE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DMA_SP2SP_DONE_MASK  0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_CFG_DMA_SP2SP_DONE_SHIFT 2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_SMU2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SMU2SP_DONE_MASK         0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SMU2SP_DONE_SHIFT        1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_33 :: ASF_SP2DMA_START [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SP2DMA_START_MASK        0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_33_ASF_SP2DMA_START_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_34 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: reserved0 [31:15] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_reserved0_MASK               0xffff8000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_reserved0_SHIFT              15
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_STATE [14:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_STATE_MASK               0x00007f00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_STATE_SHIFT              8
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PT_SEARCH_IN_PROGRESS [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_IN_PROGRESS_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_IN_PROGRESS_SHIFT 7
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PT_SEARCH_DONE [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_DONE_MASK      0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PT_SEARCH_DONE_SHIFT     6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_DMA_END [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_DMA_END_MASK             0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_DMA_END_SHIFT            5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PKT_END [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_END_MASK             0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_END_SHIFT            4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PKT_DONE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_DONE_MASK            0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PKT_DONE_SHIFT           3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_LAST_TRANS [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_LAST_TRANS_MASK          0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_LAST_TRANS_SHIFT         2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_SKIP_PKT_BUF2SP_DONE [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_SKIP_PKT_BUF2SP_DONE_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_SKIP_PKT_BUF2SP_DONE_SHIFT 1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_34 :: ASF_PARSING_IN_PROGRESS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PARSING_IN_PROGRESS_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_34_ASF_PARSING_IN_PROGRESS_SHIFT 0
+
+/***************************************************************************
+ *DEBUG_35 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: reserved0 [31:29] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_reserved0_MASK               0xe0000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_reserved0_SHIFT              29
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: SP_SLOT_BUS_DCP_SLOT_VALID [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_SLOT_BUS_DCP_SLOT_VALID_MASK 0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_SLOT_BUS_DCP_SLOT_VALID_SHIFT 28
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: SP_TIME_OUT [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_TIME_OUT_MASK             0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_SP_TIME_OUT_SHIFT            27
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_MCPB_CH_NUM [26:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_MCPB_CH_NUM_MASK      0x07c00000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_MCPB_CH_NUM_SHIFT     22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: PARSER_STREAM_TYPE [21:19] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_PARSER_STREAM_TYPE_MASK      0x00380000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_PARSER_STREAM_TYPE_SHIFT     19
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PKT_SLOT_NUM [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_NUM_MASK     0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_NUM_SHIFT    18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_DCP_SLOT_NUM [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DCP_SLOT_NUM_MASK     0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DCP_SLOT_NUM_SHIFT    17
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_DESC_SLOT_NUM [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DESC_SLOT_NUM_MASK    0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_DESC_SLOT_NUM_SHIFT   16
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PKT_SLOT_IN_USE [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_IN_USE_MASK  0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PKT_SLOT_IN_USE_SHIFT 15
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_D_REGION [14:07] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_D_REGION_MASK         0x00007f80
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_D_REGION_SHIFT        7
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_ZERO_BYTE_TRANS [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_ZERO_BYTE_TRANS_MASK  0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_ZERO_BYTE_TRANS_SHIFT 6
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_FIRST_PKT_AFT_RUN_ASSERT [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_LAST_TRANS [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_LAST_TRANS_MASK       0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_LAST_TRANS_SHIFT      4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_RESET_PARSER [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_RESET_PARSER_MASK     0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_RESET_PARSER_SHIFT    3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_PUSH_RESIDUAL_BYTES [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PUSH_RESIDUAL_BYTES_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_PUSH_RESIDUAL_BYTES_SHIFT 2
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_FORCE_TS_CFG [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FORCE_TS_CFG_MASK     0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_FORCE_TS_CFG_SHIFT    1
+
+/* XPT_MEMDMA_MCPB :: DEBUG_35 :: DMA2SP_GEN_BTP_PKT [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_GEN_BTP_PKT_MASK      0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_35_DMA2SP_GEN_BTP_PKT_SHIFT     0
+
+/***************************************************************************
+ *DEBUG_36 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: DMA2SP_NUM_BYTES [31:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_DMA2SP_NUM_BYTES_MASK        0xff800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_DMA2SP_NUM_BYTES_SHIFT       23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BYS_PKT_SLOT_VALID [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BYS_PKT_SLOT_VALID_MASK 0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BYS_PKT_SLOT_VALID_SHIFT 22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_SLOT_IN_USE [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_SHIFT 21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_OP_PIPE_SEL [20:18] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_OP_PIPE_SEL_MASK 0x001c0000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_OP_PIPE_SEL_SHIFT 18
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_NUM_OF_DUP [17:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_OF_DUP_MASK  0x0003c000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_OF_DUP_SHIFT 14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DCP_ONLY_FOR_PES_PACING_SHIFT 13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_DROP_THE_PKT [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DROP_THE_PKT_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_DROP_THE_PKT_SHIFT 12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_SLOT_IN_USE_FOR_PES_PACING_SHIFT 11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_ASF_PD_PKT_COMPLETE [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_ASF_PD_PKT_COMPLETE_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_ASF_PD_PKT_COMPLETE_SHIFT 10
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_PKT_DROP_AS_RUN_INVALID_SHIFT 9
+
+/* XPT_MEMDMA_MCPB :: DEBUG_36 :: SP_SLOT_BUS_NUM_BYTES [08:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_BYTES_MASK   0x000001ff
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_36_SP_SLOT_BUS_NUM_BYTES_SHIFT  0
+
+/***************************************************************************
+ *DEBUG_37 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: reserved0 [31:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_reserved0_MASK               0xfe000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_reserved0_SHIFT              25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_READY [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_READY_MASK     0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_READY_SHIFT    24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_ACCEPT [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_ACCEPT_MASK    0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_ACCEPT_SHIFT   23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_DROP_FLAG [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DROP_FLAG_MASK 0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DROP_FLAG_SHIFT 22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_SP_DMA_END [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DMA_END_MASK   0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_SP_DMA_END_SHIFT  21
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_BYTE_EN [20:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_BYTE_EN_MASK  0x001fe000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_BYTE_EN_SHIFT 13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_READY [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_READY_MASK    0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_READY_SHIFT   12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OUT_ACCEPT [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_ACCEPT_MASK   0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OUT_ACCEPT_SHIFT  11
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_OFFSET_ADDR [10:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OFFSET_ADDR_MASK  0x000007f8
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_OFFSET_ADDR_SHIFT 3
+
+/* XPT_MEMDMA_MCPB :: DEBUG_37 :: PKT_BUF_32_IN_STATE [02:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_IN_STATE_MASK     0x00000007
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_37_PKT_BUF_32_IN_STATE_SHIFT    0
+
+/***************************************************************************
+ *DEBUG_38 - Debug Register
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: reserved0 [31:26] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_reserved0_MASK               0xfc000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_reserved0_SHIFT              26
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_READY [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_READY_MASK      0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_READY_SHIFT     25
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_ACCEPT [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_ACCEPT_MASK     0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_ACCEPT_SHIFT    24
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_DROP_FLAG [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DROP_FLAG_MASK  0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DROP_FLAG_SHIFT 23
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_SP_DMA_END [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DMA_END_MASK    0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_SP_DMA_END_SHIFT   22
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_BYTE_EN [21:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_BYTE_EN_MASK   0x003fc000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_BYTE_EN_SHIFT  14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_READY [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_READY_MASK     0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_READY_SHIFT    13
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OUT_ACCEPT [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_ACCEPT_MASK    0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OUT_ACCEPT_SHIFT   12
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_OFFSET_ADDR [11:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OFFSET_ADDR_MASK   0x00000ff0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_OFFSET_ADDR_SHIFT  4
+
+/* XPT_MEMDMA_MCPB :: DEBUG_38 :: PKT_BUF_8_IN_STATE [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_IN_STATE_MASK      0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_38_PKT_BUF_8_IN_STATE_SHIFT     0
+
+/***************************************************************************
+ *SP_TIME_OUT_THRESHOLD - SP Timeout Threshold
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: reserved0 [31:14] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_reserved0_MASK  0xffffc000
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_reserved0_SHIFT 14
+
+/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: AUTO_RECOVER_EN [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_SHIFT 13
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_AUTO_RECOVER_EN_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: TIMEOUT_INTR_EN [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_TIMEOUT_INTR_EN_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: SP_TIME_OUT_THRESHOLD :: SP_TIMEOUT_THRESHOLD [11:00] */
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_MASK 0x00000fff
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_SP_TIME_OUT_THRESHOLD_SP_TIMEOUT_THRESHOLD_DEFAULT 0x00000400
+
+/***************************************************************************
+ *DEBUG_SP_FORCE_RECOVER - Debug SP Force Recover
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: reserved0 [31:05] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_reserved0_MASK 0xffffffe0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_reserved0_SHIFT 5
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_AUTO_RECOVER [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_AUTO_RECOVER_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_CFG_DCP_WRITE [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_SHIFT 3
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DCP_WRITE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_CFG_DMA_SP_WRITE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_CFG_DMA_SP_WRITE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_SMU_SLOT_BUS_START [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_SHIFT 1
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_SMU_SLOT_BUS_START_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_FORCE_RECOVER :: SP_FORCE_DMA_SLOT_BUS_START [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_FORCE_RECOVER_SP_FORCE_DMA_SLOT_BUS_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR - Debug SP TX Overwrite Slot Cmd Auto Recover Overwrite
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: reserved0 [31:14] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_reserved0_MASK 0xffffc000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_reserved0_SHIFT 14
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_SLOT_VALID [13:12] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_MASK 0x00003000
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_SHIFT 12
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_VALID_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_SLOT_IN_USE [11:10] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_MASK 0x00000c00
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_SHIFT 10
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_SLOT_IN_USE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: RETRANSMIT_SLOT_CMD [09:08] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_MASK 0x00000300
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_SHIFT 8
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_RETRANSMIT_SLOT_CMD_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: LAST_DATA_TRANS [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_MASK 0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_SHIFT 6
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_LAST_DATA_TRANS_DEFAULT 0x00000002
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: DROP_THE_PACKET [05:04] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_MASK 0x00000030
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_SHIFT 4
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_DROP_THE_PACKET_DEFAULT 0x00000001
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: ASF_PD_PKT_COMPLETE [03:02] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_MASK 0x0000000c
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_SHIFT 2
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_ASF_PD_PKT_COMPLETE_DEFAULT 0x00000000
+
+/* XPT_MEMDMA_MCPB :: DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR :: PKT_DROP_AS_RUN_INVALID [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_SHIFT 0
+#define BCHP_XPT_MEMDMA_MCPB_DEBUG_SP_TX_SLOT_CMD_AUTO_RECOVER_OVERWR_PKT_DROP_AS_RUN_INVALID_DEFAULT 0x00000002
+
+#endif /* #ifndef BCHP_XPT_MEMDMA_MCPB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb_ch0.h b/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb_ch0.h
new file mode 100644
index 000000000000..00e42a601aa0
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_memdma_mcpb_ch0.h
@@ -0,0 +1,2315 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:52 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__
+#define BCHP_XPT_MEMDMA_MCPB_CH0_H__
+
+/***************************************************************************
+ *XPT_MEMDMA_MCPB_CH0 - MCPB Channel 0 Configuration
+ ***************************************************************************/
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL 0x00a60c00 /* MCPB Channel x Descriptor control information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL 0x00a60c04 /* MCPB Channel x Data control information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS 0x00a60c08 /* MCPB Channel x Current Descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS 0x00a60c0c /* MCPB Channel x Next Descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER 0x00a60c10 /* MCPB Channel x Data Buffer Base address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER 0x00a60c14 /* MCPB Channel x Data Buffer Base address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER 0x00a60c18 /* MCPB Channel x Data Buffer End address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER 0x00a60c1c /* MCPB Channel x Data Buffer End address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER 0x00a60c20 /* MCPB Channel x Current Data Buffer Read address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER 0x00a60c24 /* MCPB Channel x Current Data Buffer Read address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER 0x00a60c28 /* MCPB Channel x Data Buffer Write address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER 0x00a60c2c /* MCPB Channel x Data Buffer Write address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0    0x00a60c30 /* MCPB Channel x Status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1    0x00a60c34 /* MCPB Channel x CRC value */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2    0x00a60c38 /* MCPB Channel x Manual mode status */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0 0x00a60c3c /* MCPB channel x Descriptor Slot 0 status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1 0x00a60c40 /* MCPB channel x Descriptor Slot 0 status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR 0x00a60c44 /* MCPB Channel x  Descriptor Slot 0 Current Descriptor Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER 0x00a60c48 /* MCPB Channel x  Descriptor Slot 0 Current Data Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER 0x00a60c4c /* MCPB Channel x  Descriptor Slot 0 Current Data Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP 0x00a60c50 /* MCPB Channel x Descriptor Slot 0 Next Packet Timestamp */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA 0x00a60c54 /* MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0 0x00a60c58 /* MCPB channel x Descriptor Slot 1 status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1 0x00a60c5c /* MCPB channel x Descriptor Slot 1 status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR 0x00a60c60 /* MCPB Channel x  Descriptor Slot 1 Current Descriptor Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER 0x00a60c64 /* MCPB Channel x  Descriptor Slot 1 Current Data Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER 0x00a60c68 /* MCPB Channel x  Descriptor Slot 1 Current Data Address */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP 0x00a60c6c /* MCPB Channel x Descriptor Slot 1 Next Packet Timestamp */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA 0x00a60c70 /* MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN      0x00a60c74 /* MCPB Channel x Packet length control */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL  0x00a60c78 /* MCPB Channel x Parser control */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1 0x00a60c7c /* MCPB Channel x Parser control 1 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG    0x00a60c80 /* MCPB Channel x TS Configuration */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG 0x00a60c84 /* MCPB Channel x PES and ES Configuration */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER 0x00a60c88 /* MCPB Channel x PES Sync counter */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG   0x00a60c8c /* MCPB Channel x ASF Configuration */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0  0x00a60c90 /* MCPB Channel x Stream Processor State Register 0 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1  0x00a60c94 /* MCPB Channel x Stream Processor State Register 1 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2  0x00a60c98 /* MCPB Channel x Stream Processor State Register 2 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3  0x00a60c9c /* MCPB Channel x Stream Processor State Register 3 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4  0x00a60ca0 /* MCPB Channel x Stream Processor State Register 4 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5  0x00a60ca4 /* MCPB Channel x Stream Processor State Register 5 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6  0x00a60ca8 /* MCPB Channel x Stream Processor State Register 6 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7  0x00a60cac /* MCPB Channel x Stream Processor State Register 7 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8  0x00a60cb0 /* MCPB Channel x Stream Processor State Register 8 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9  0x00a60cb4 /* MCPB Channel x Stream Processor State Register 9 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10 0x00a60cb8 /* MCPB Channel x Stream Processor State Register 10 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11 0x00a60cbc /* MCPB Channel x Stream Processor State Register 11 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12 0x00a60cc0 /* MCPB Channel x Stream Processor State Register 12 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13 0x00a60cc4 /* MCPB Channel x Stream Processor State Register 13 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL  0x00a60cc8 /* MCPB Channel x Burst buffer control */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC   0x00a60ccc /* MCPB Channel x Current CRC value */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS 0x00a60cd0 /* MCPB Channel x Burst buffer 0 data specific information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS 0x00a60cd4 /* MCPB Channel x Burst buffer 0 control specific information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS 0x00a60cd8 /* MCPB Channel x Burst buffer 1 data specific information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS 0x00a60cdc /* MCPB Channel x Burst buffer 1 control specific information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL 0x00a60ce0 /* MCPB Channel x Blockout control information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON 0x00a60ce4 /* MCPB Channel x next Blockout monitor information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL 0x00a60ce8 /* MCPB Channel x next Blockout monitor information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX 0x00a60cec /* MCPB Channel x reference difference value and next Timestamp information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY 0x00a60cf0 /* MCPB Channel x TS error bound early information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE 0x00a60cf4 /* MCPB Channel x TS error bound late information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON 0x00a60cf8 /* MCPB Channel x next Global Pacing Counter and Timestamp monitor information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN 0x00a60cfc /* MCPB Channel x reference difference value sign information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL 0x00a60d00 /* MCPB Channel x PES pacing control information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS 0x00a60d04 /* MCPB Channel x Slot 0 and Slot 1 information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1 0x00a60d08 /* MCPB Channel x timing information for Slot 0 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2 0x00a60d0c /* MCPB Channel x timing information for Slot 0 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1 0x00a60d10 /* MCPB Channel x timing information for Slot 1 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2 0x00a60d14 /* MCPB Channel x timing information for Slot 1 */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA 0x00a60d18 /* MCPB Channel x last TS delta value */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP 0x00a60d1c /* MCPB Channel x last NEXT TS value */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS     0x00a60d20 /* MCPB Channel x DCPM status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR  0x00a60d24 /* MCPB Channel x DCPM descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR 0x00a60d28 /* MCPB Channel x DCPM descriptor done interrupt address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL 0x00a60d2c /* MCPB Channel x Pause after group of packets control information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER 0x00a60d30 /* MCPB Channel x Pause after group of packets local packet counter */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER 0x00a60d34 /* MCPB Channel x local packet counter */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER 0x00a60d38 /* MCPB Channel x DCPM data address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER 0x00a60d3c /* MCPB Channel x DCPM data address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR 0x00a60d40 /* MCPB Channel x DCPM current descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS 0x00a60d44 /* MCPB Channel x DCPM slot status information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0 0x00a60d48 /* MCPB Channel x DCPM completed slot 0 descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER 0x00a60d4c /* MCPB Channel x DCPM completed slot 0 data address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER 0x00a60d50 /* MCPB Channel x DCPM completed slot 0 data address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1 0x00a60d54 /* MCPB Channel x DCPM completed slot 1 descriptor address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER 0x00a60d58 /* MCPB Channel x DCPM completed slot 1 data address information */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER 0x00a60d5c /* MCPB Channel x DCPM completed slot 1 data address information */
+
+/***************************************************************************
+ *DMA_DESC_CONTROL - MCPB Channel x Descriptor control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: FIRST_DESC_ADDRESS [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_FIRST_DESC_ADDRESS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: reserved0 [03:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_MASK   0x0000000c
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_reserved0_SHIFT  2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_CONTROL :: LLD_TYPE [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_MASK    0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_CONTROL_LLD_TYPE_SHIFT   0
+
+/***************************************************************************
+ *DMA_DATA_CONTROL - MCPB Channel x Data control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_MASK   0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_reserved0_SHIFT  16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: RUN_VERSION [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_MASK 0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_RUN_VERSION_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: ENDIAN_CONTROL [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_ENDIAN_CONTROL_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DATA_CONTROL :: DRAM_REQ_SIZE [09:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_MASK 0x000003ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DATA_CONTROL_DRAM_REQ_SIZE_SHIFT 0
+
+/***************************************************************************
+ *DMA_CURR_DESC_ADDRESS - MCPB Channel x Current Descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: CURR_DESC_ADDRESS [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_CURR_DESC_ADDRESS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_CURR_DESC_ADDRESS :: reserved0 [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_CURR_DESC_ADDRESS_reserved0_SHIFT 0
+
+/***************************************************************************
+ *DMA_NEXT_DESC_ADDRESS - MCPB Channel x Next Descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: NEXT_DESC_ADDRESS [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_NEXT_DESC_ADDRESS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_NEXT_DESC_ADDRESS :: reserved0 [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_NEXT_DESC_ADDRESS_reserved0_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_BASE_ADDRESS_UPPER - MCPB Channel x Data Buffer Base address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_UPPER :: BUFF_BASE_ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_UPPER_BUFF_BASE_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_BASE_ADDRESS_LOWER - MCPB Channel x Data Buffer Base address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_BASE_ADDRESS_LOWER :: BUFF_BASE_ADDRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_BASE_ADDRESS_LOWER_BUFF_BASE_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_END_ADDRESS_UPPER - MCPB Channel x Data Buffer End address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_UPPER :: BUFF_END_ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_UPPER_BUFF_END_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_END_ADDRESS_LOWER - MCPB Channel x Data Buffer End address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_END_ADDRESS_LOWER :: BUFF_END_ADDRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_END_ADDRESS_LOWER_BUFF_END_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_CURR_RD_ADDRESS_UPPER - MCPB Channel x Current Data Buffer Read address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_UPPER :: BUFF_CURR_RD_ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_UPPER_BUFF_CURR_RD_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_CURR_RD_ADDRESS_LOWER - MCPB Channel x Current Data Buffer Read address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_CURR_RD_ADDRESS_LOWER :: BUFF_CURR_RD_ADDRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_CURR_RD_ADDRESS_LOWER_BUFF_CURR_RD_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_WRITE_ADDRESS_UPPER - MCPB Channel x Data Buffer Write address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_UPPER :: BUFF_WRITE_ADDRESS [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_UPPER_BUFF_WRITE_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_BUFF_WRITE_ADDRESS_LOWER - MCPB Channel x Data Buffer Write address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BUFF_WRITE_ADDRESS_LOWER :: BUFF_WRITE_ADDRESS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BUFF_WRITE_ADDRESS_LOWER_BUFF_WRITE_ADDRESS_SHIFT 0
+
+/***************************************************************************
+ *DMA_STATUS_0 - MCPB Channel x Status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_SLOT_NUM_TO_USE [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_SLOT_NUM_TO_USE_SHIFT 31
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_BAND_ID_CHANGE_TRANS [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_MASK 0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_BAND_ID_CHANGE_TRANS_SHIFT 30
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_0B_CONTROL_TRANS [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_MASK 0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_0B_CONTROL_TRANS_SHIFT 29
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SEND_RESET_PARSER_ON_1ST_NON_0_TRAN [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_MASK 0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SEND_RESET_PARSER_ON_1ST_NON_0_TRAN_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FIRST_DESC_RD_AFTER_RUN_ASSERT [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_MASK 0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FIRST_DESC_RD_AFTER_RUN_ASSERT_SHIFT 27
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: ZERO_BYTE_DESC [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_MASK  0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_ZERO_BYTE_DESC_SHIFT 26
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: LAST_DESC_IND [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_MASK   0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_LAST_DESC_IND_SHIFT  25
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: HOST_DATA_INS_EN [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_MASK 0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_HOST_DATA_INS_EN_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: FORCE_RESYNC [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_MASK    0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_FORCE_RESYNC_SHIFT   23
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PREV_PARTIAL_PACKET [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_MASK 0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PREV_PARTIAL_PACKET_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PUSH_PARTIAL_PACKET [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PUSH_PARTIAL_PACKET_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID [20:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_MASK    0x001fe000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_SHIFT   13
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_BAND_ID_EN [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_BAND_ID_EN_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DESC_PARSER_SEL [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DESC_PARSER_SEL_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: DATA_UNIT_SIZE [10:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DATA_UNIT_SIZE_MASK  0x00000600
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_DATA_UNIT_SIZE_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_LOAD [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_MASK        0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_LOAD_SHIFT       8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPARE [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_MASK     0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPARE_SHIFT    7
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: CRC_COMPUTE [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_MASK     0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_CRC_COMPUTE_SHIFT    6
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_START [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_MASK     0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_START_SHIFT    5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: SCRAM_END [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_MASK       0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_SCRAM_END_SHIFT      4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: NEXT_TIMESTAMP_VALID [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_READ [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_READ_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_0 :: PAUSE_AT_DESC_END [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_0_PAUSE_AT_DESC_END_SHIFT 0
+
+/***************************************************************************
+ *DMA_STATUS_1 - MCPB Channel x CRC value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_1 :: CRC_IN [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_MASK          0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_1_CRC_IN_SHIFT         0
+
+/***************************************************************************
+ *DMA_STATUS_2 - MCPB Channel x Manual mode status
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: reserved0 [31:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_MASK       0xfffffff8
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_reserved0_SHIFT      3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_TYPE [02:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_MASK 0x00000006
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_TYPE_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_STATUS_2 :: SP_COMMAND_FROM_DESC_EN [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_STATUS_2_SP_COMMAND_FROM_DESC_EN_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_STATUS_0 - MCPB channel x Descriptor Slot 0 status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_MASK 0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_reserved0_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: INTR_EN [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_INTR_EN_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: DESC_ID [15:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_MASK 0x0000f000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_DESC_ID_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: RUN_VERSION [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_MASK 0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_RUN_VERSION_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_START [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_START_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_END [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_END_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: SCRAM_INIT [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_SCRAM_INIT_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_STATUS_1 - MCPB channel x Descriptor Slot 0 status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: reserved0 [31:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_MASK 0xffe00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_reserved0_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_EN_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_PARSER_SEL [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_PARSER_SEL_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: DESC_BAND_ID [18:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_MASK 0x0007f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_DESC_BAND_ID_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL_VALID [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_VALID_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_STATUS_1 :: PID_CHANNEL [09:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_MASK 0x000003ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_STATUS_1_PID_CHANNEL_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_CURR_DESC_ADDR - MCPB Channel x  Descriptor Slot 0 Current Descriptor Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER - MCPB Channel x  Descriptor Slot 0 Current Data Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER - MCPB Channel x  Descriptor Slot 0 Current Data Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 0 Next Packet Timestamp
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 0 Packet to packet Timestamp delta
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT0_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_STATUS_0 - MCPB channel x Descriptor Slot 1 status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: reserved0 [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_MASK 0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_reserved0_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: INTR_EN [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_INTR_EN_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_READ [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_READ_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PAUSE_AT_DESCRIPTOR_END [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PAUSE_AT_DESCRIPTOR_END_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: DESC_ID [15:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_MASK 0x0000f000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_DESC_ID_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RANDOM_ACCESS_IND [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RANDOM_ACCESS_IND_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: RUN_VERSION [10:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_MASK 0x000007c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_RUN_VERSION_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: HOST_DATA_INS_AS_BTP_PKT [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_HOST_DATA_INS_AS_BTP_PKT_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_START [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_START_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_END [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_END_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: SCRAM_INIT [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_SCRAM_INIT_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: NEXT_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_NEXT_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_0 :: PKT2PKT_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_0_PKT2PKT_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_STATUS_1 - MCPB channel x Descriptor Slot 1 status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: reserved0 [31:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_MASK 0xffe00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_reserved0_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_EN_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_PARSER_SEL [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_PARSER_SEL_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: DESC_BAND_ID [18:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_MASK 0x0007f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_DESC_BAND_ID_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL_VALID [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_VALID_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_STATUS_1 :: PID_CHANNEL [09:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_MASK 0x000003ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_STATUS_1_PID_CHANNEL_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_CURR_DESC_ADDR - MCPB Channel x  Descriptor Slot 1 Current Descriptor Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER - MCPB Channel x  Descriptor Slot 1 Current Data Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER :: CUR_DATA_ADDR [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_UPPER_CUR_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER - MCPB Channel x  Descriptor Slot 1 Current Data Address
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER :: CUR_DATA_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_CURR_DATA_ADDR_LOWER_CUR_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_NEXT_TIMESTAMP - MCPB Channel x Descriptor Slot 1 Next Packet Timestamp
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_NEXT_TIMESTAMP :: NEXT_TIMESTAMP [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_NEXT_TIMESTAMP_NEXT_TIMESTAMP_SHIFT 0
+
+/***************************************************************************
+ *DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA - MCPB Channel x Descriptor Slot 1 Packet to packet Timestamp delta
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA :: PKT2PKT_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_DESC_SLOT1_PKT2PKT_TIMESTAMP_DELTA_PKT2PKT_TIMESTAMP_DELTA_SHIFT 0
+
+/***************************************************************************
+ *SP_PKT_LEN - MCPB Channel x Packet length control
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PKT_LEN :: PACKET_LENGTH [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_MASK     0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PKT_LEN_PACKET_LENGTH_SHIFT    0
+
+/***************************************************************************
+ *SP_PARSER_CTRL - MCPB Channel x Parser control
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved0 [31:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_MASK     0xfc000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved0_SHIFT    26
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL [25:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_MASK 0x03000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_MEM_DMA_GR_SEL_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: STANDALONE_BLOCK_MODE_EN [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_MASK 0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_STANDALONE_BLOCK_MODE_EN_SHIFT 23
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: SCRAM_START_END_FOR_EVERY_PACKET [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_MASK 0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_SCRAM_START_END_FOR_EVERY_PACKET_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved1 [21:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_MASK     0x003c0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved1_SHIFT    18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PUSI_SET_DIS [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_MASK  0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PUSI_SET_DIS_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved2 [16:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_MASK     0x00018000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved2_SHIFT    15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_SEL [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_SEL_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PB_PARSER_BAND_ID [13:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_MASK 0x00003fc0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PB_PARSER_BAND_ID_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: reserved3 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_MASK     0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_reserved3_SHIFT    5
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ALL_PASS_CTRL [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ALL_PASS_CTRL_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_STREAM_TYPE [03:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_MASK 0x0000000e
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_STREAM_TYPE_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL_PARSER_ENABLE_SHIFT 0
+
+/***************************************************************************
+ *SP_PARSER_CTRL1 - MCPB Channel x Parser control 1
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: reserved0 [31:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_MASK    0xffffe000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_reserved0_SHIFT   13
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_PIDP_DEBUG_MODE_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PARSER_CTRL1 :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PARSER_CTRL1_ALL_PASS_PID_CH_NUM_SHIFT 0
+
+/***************************************************************************
+ *SP_TS_CONFIG - MCPB Channel x TS Configuration
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved0 [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_MASK       0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved0_SHIFT      31
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFID [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_MASK     0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFID_SHIFT    30
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CFF [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_MASK      0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CFF_SHIFT     29
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_RTS00 [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_MASK    0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_RTS00_SHIFT   28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_AFS [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_MASK      0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_AFS_SHIFT     27
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_CC [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_MASK       0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_CC_SHIFT      26
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_OCF [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_MASK      0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_OCF_SHIFT     25
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: IGNORE_SCF [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_MASK      0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_IGNORE_SCF_SHIFT     24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved1 [23:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_MASK       0x00e00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved1_SHIFT      21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PCR_PACING_PID [20:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_MASK  0x001fff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PCR_PACING_PID_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved2 [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_MASK       0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved2_SHIFT      6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_TEI_IGNORE [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_TEI_IGNORE_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: reserved3 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_MASK       0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_reserved3_SHIFT      4
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: PARSER_ACCEPT_NULL_PKT [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_PARSER_ACCEPT_NULL_PKT_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: ATS_PARITY_CHECK_DIS [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_ATS_PARITY_CHECK_DIS_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: INPUT_HAS_ATS [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_MASK   0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_INPUT_HAS_ATS_SHIFT  1
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_TS_CONFIG :: MPEG_TS_AUTO_SYNC_DETECT [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_TS_CONFIG_MPEG_TS_AUTO_SYNC_DETECT_SHIFT 0
+
+/***************************************************************************
+ *SP_PES_ES_CONFIG - MCPB Channel x PES and ES Configuration
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: reserved0 [31:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_MASK   0xffc00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_reserved0_SHIFT  22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PKTZ_SC [21:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_MASK     0x00300000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PKTZ_SC_SHIFT    20
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: STREAM_ID_EXT_EN [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_STREAM_ID_EXT_EN_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SUB_STREAM_ID_EXT_EN [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SUB_STREAM_ID_EXT_EN_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_EN [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_EN_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: PROGRAM_STREAM_MODE [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_PROGRAM_STREAM_MODE_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_HIGH [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_HIGH_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_ES_CONFIG :: SYNC_ID_LOW [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_ES_CONFIG_SYNC_ID_LOW_SHIFT 0
+
+/***************************************************************************
+ *SP_PES_SYNC_COUNTER - MCPB Channel x PES Sync counter
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_PES_SYNC_COUNTER :: PES_SYNC_COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_PES_SYNC_COUNTER_PES_SYNC_COUNTER_SHIFT 0
+
+/***************************************************************************
+ *SP_ASF_CONFIG - MCPB Channel x ASF Configuration
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved0 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_MASK      0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved0_SHIFT     24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SPACE [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SPACE_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved1 [15:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_MASK      0x0000f000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved1_SHIFT     12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_DATA_PACKET_LENGTH_VALID [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_DATA_PACKET_LENGTH_VALID_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_ADAPTIVE_PACKET_LENGTH_ENABLE [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_ADAPTIVE_PACKET_LENGTH_ENABLE_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_PAYLOAD_SC [09:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_MASK 0x00000300
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_PAYLOAD_SC_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_SUB_PAYLOAD_SC [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_MASK 0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_SUB_PAYLOAD_SC_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved2 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_MASK      0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved2_SHIFT     5
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_80_GEN_EN [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_80_GEN_EN_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TYPE_8F_GEN_EN [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TYPE_8F_GEN_EN_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_TEST_HALT [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_MASK  0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_TEST_HALT_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: ASF_STREAM_LENGTH_ENDIANESS [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_ASF_STREAM_LENGTH_ENDIANESS_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_ASF_CONFIG :: reserved3 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_MASK      0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_ASF_CONFIG_reserved3_SHIFT     0
+
+/***************************************************************************
+ *SP_STATE_REG_0 - MCPB Channel x Stream Processor State Register 0
+ ***************************************************************************/
+/* union - case NON_BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE4 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_MASK 0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE4_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE3 [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE3_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE2 [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE2_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: NON_BLOCK_MODE :: RA1_BYTE1 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_NON_BLOCK_MODE_RA1_BYTE1_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_0 :: BLOCK_MODE :: RA1_WORD5 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_0_BLOCK_MODE_RA1_WORD5_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_1 - MCPB Channel x Stream Processor State Register 1
+ ***************************************************************************/
+/* union - case MPEG [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DATA_ACCUM_VALID [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DATA_ACCUM_VALID_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TS_STATE [27:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_MASK 0x0fc00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TS_STATE_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: OUT_OF_SYNC [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_OUT_OF_SYNC_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: TIMESTAMP_VALID [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_TIMESTAMP_VALID_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_CNTL_1 [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_CNTL_1_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: ADP_LEN [18:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_MASK  0x0007f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_ADP_LEN_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DISCONT_IND [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DISCONT_IND_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: PCR_FLAG [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_PCR_FLAG_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved0 [08:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_MASK 0x00000180
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved0_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: DESC_BASE_PACING [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_DESC_BASE_PACING_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved1 [05:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_MASK 0x00000038
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved1_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: SMU_PKT_DROP [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_SMU_PKT_DROP_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: MPEG :: reserved2 [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_MPEG_reserved2_SHIFT 0
+
+/* union - case DSS [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DATA_ACCUM_VALID [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DATA_ACCUM_VALID_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TS_STATE [27:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_MASK  0x0fc00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TS_STATE_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: OUT_OF_SYNC [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_OUT_OF_SYNC_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: TIMESTAMP_VALID [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_TIMESTAMP_VALID_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CC_ZERO [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_MASK   0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CC_ZERO_SHIFT  19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: HD_ZERO [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_MASK   0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_HD_ZERO_SHIFT  18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: CFF_ONE [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_MASK   0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_CFF_ONE_SHIFT  17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFID_THREE [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFID_THREE_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: AFS_7D [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_MASK    0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_AFS_7D_SHIFT   15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: RTS00 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_MASK     0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_RTS00_SHIFT    14
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: ORIG_CF [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_MASK   0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_ORIG_CF_SHIFT  13
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: PF [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_MASK        0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_PF_SHIFT       12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved0 [11:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_MASK 0x00000f80
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved0_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: DESC_BASE_PACING [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_DESC_BASE_PACING_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved1 [05:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_MASK 0x00000038
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved1_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: SMU_PKT_DROP [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_SMU_PKT_DROP_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: DSS :: reserved2 [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_DSS_reserved2_SHIFT 0
+
+/* union - case PES_ES_RAW [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DATA_ACCUM_VALID [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DATA_ACCUM_VALID_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_STATE [27:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_MASK 0x0fc00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_STATE_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: OUT_OF_SYNC [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_OUT_OF_SYNC_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PTS_DTS_FLAGS [20:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_MASK 0x00180000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PTS_DTS_FLAGS_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ESCR_FLAG [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ESCR_FLAG_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: ES_RATE_FLAG [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_ES_RATE_FLAG_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: DSM_TRICK_MODE_FLAG [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_DSM_TRICK_MODE_FLAG_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: COPY_INFO_FLAG [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_MASK 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_COPY_INFO_FLAG_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_CRC_FLAG [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_CRC_FLAG_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT1_FLAG [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT1_FLAG_SHIFT 13
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_PRIVATE_DATA_FLAG [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_PRIVATE_DATA_FLAG_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PHF_FLAG [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PHF_FLAG_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PGRM_PKT_SEQ_FLAG [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PGRM_PKT_SEQ_FLAG_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PSTD_BUFFER_FLAG [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PSTD_BUFFER_FLAG_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: PES_EXT2_FLAG [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_PES_EXT2_FLAG_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved0 [07:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_MASK 0x000000f8
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved0_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: SMU_PKT_DROP [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_SMU_PKT_DROP_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: NEW_PKT_START [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_NEW_PKT_START_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: PES_ES_RAW :: reserved1 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_PES_ES_RAW_reserved1_SHIFT 0
+
+/* union - case ASF [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: DATA_ACCUM_VALID [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_DATA_ACCUM_VALID_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: ASF_STATE [27:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_MASK 0x0fe00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_ASF_STATE_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SEQUENCE_TYPE [20:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_MASK 0x00180000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SEQUENCE_TYPE_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PADDING_LEN_TYPE [18:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_MASK 0x00060000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PADDING_LEN_TYPE_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PKT_LEN_TYPE [16:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_MASK 0x00018000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PKT_LEN_TYPE_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_TYPE [14:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_MASK 0x00006000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_TYPE_SHIFT 13
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_NUM_LEN_TYPE [12:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_MASK 0x00001800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_NUM_LEN_TYPE_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MD_OBJ_LEN_TYPE [10:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_MASK 0x00000600
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MD_OBJ_LEN_TYPE_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: PAYLD_LEN_TYPE [08:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_MASK 0x00000180
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_PAYLD_LEN_TYPE_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: MUL_PAYLD_PRESENT [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_MUL_PAYLD_PRESENT_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: REP_DATA_LEN_EQ_ONE [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_REP_DATA_LEN_EQ_ONE_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved0 [04:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_MASK 0x00000018
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved0_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: SMU_PKT_DROP [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_SMU_PKT_DROP_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: OFS_2MED_OBJ_LEN_ZERO [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_OFS_2MED_OBJ_LEN_ZERO_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: ASF :: reserved1 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_ASF_reserved1_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_1 :: BLOCK_MODE :: RA1_WORD4 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_1_BLOCK_MODE_RA1_WORD4_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_2 - MCPB Channel x Stream Processor State Register 2
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: reserved0 [31:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_MASK     0xc0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_reserved0_SHIFT    30
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_SEARCH_DONE [29:29] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_MASK 0x20000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_SEARCH_DONE_SHIFT 29
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PT_MATCH [28:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_MASK      0x10000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PT_MATCH_SHIFT     28
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_CH_NUM [27:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_MASK    0x0fff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_CH_NUM_SHIFT   16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_2 :: PKT_DESTINATION [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_MASK 0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_2_PKT_DESTINATION_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_3 - MCPB Channel x Stream Processor State Register 3
+ ***************************************************************************/
+/* union - case MPEG [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PID [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PID_SHIFT     19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved0 [16:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_MASK 0x0001fc00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved0_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: FORCE_RESYNC [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_FORCE_RESYNC_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: PCR_FORCE_RESYNC [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_PCR_FORCE_RESYNC_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: MPEG :: reserved1 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_MPEG_reserved1_SHIFT 0
+
+/* union - case DSS [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: SCID [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_MASK      0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_SCID_SHIFT     19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FIRST_PKT_AFT_FUN_ASSERT [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FIRST_PKT_AFT_FUN_ASSERT_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved0 [16:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_MASK 0x0001fc00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved0_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: FORCE_RESYNC [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_FORCE_RESYNC_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: PCR_FORCE_RESYNC [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_PCR_FORCE_RESYNC_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: DSS :: reserved1 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_DSS_reserved1_SHIFT 0
+
+/* union - case PES_or_ES_or_RAW [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PID [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_MASK 0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PID_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: PUSI [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_PUSI_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: RAI_LEVEL_1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_MASK 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_RAI_LEVEL_1_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved0 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved0_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: AFC [13:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_MASK 0x00003000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_AFC_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved1 [11:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_MASK 0x00000c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved1_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: FORCE_RESYNC [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_FORCE_RESYNC_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: PES_or_ES_or_RAW :: reserved2 [08:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_MASK 0x000001ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_PES_or_ES_or_RAW_reserved2_SHIFT 0
+
+/* union - case ASF [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PID [31:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_MASK       0xfff80000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PID_SHIFT      19
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FIRST_PKT_AFT_RUN_ASSERT [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FIRST_PKT_AFT_RUN_ASSERT_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: PUSI [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_MASK      0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_PUSI_SHIFT     17
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_MASK       0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_SHIFT      16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: RAI_LEVEL_1 [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_MASK 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_RAI_LEVEL_1_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved0 [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved0_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: AFC [13:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_MASK       0x00003000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_AFC_SHIFT      12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved1 [11:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_MASK 0x00000c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved1_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: FORCE_RESYNC [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_FORCE_RESYNC_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: reserved2 [08:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_MASK 0x000001c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_reserved2_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: ASF :: NUM_OF_PAYLD [05:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_MASK 0x0000003f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_ASF_NUM_OF_PAYLD_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_3 :: BLOCK_MODE :: RA1_WORD3 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_3_BLOCK_MODE_RA1_WORD3_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_4 - MCPB Channel x Stream Processor State Register 4
+ ***************************************************************************/
+/* union - case MPEG_or_DSS [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: GEN_COUNT0 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_MASK 0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_GEN_COUNT0_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: MPEG_or_DSS :: reserved0 [23:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_MASK 0x00ffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_MPEG_or_DSS_reserved0_SHIFT 0
+
+/* union - case PES_or_ES_or_RAW [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: GEN_COUNT0 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_MASK 0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_GEN_COUNT0_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved0 [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved0_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: PAYLD_SECT_LEN [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_PAYLD_SECT_LEN_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: PES_or_ES_or_RAW :: reserved1 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_PES_or_ES_or_RAW_reserved1_SHIFT 0
+
+/* union - case ASF [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: GEN_COUNT0 [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_MASK 0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_GEN_COUNT0_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PRIVATE_DATA_SECT_LEN [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PRIVATE_DATA_SECT_LEN_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: PAYLD_SECT_LEN [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_PAYLD_SECT_LEN_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: ASF :: reserved0 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_ASF_reserved0_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_4 :: BLOCK_MODE :: RA1_WORD2 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_4_BLOCK_MODE_RA1_WORD2_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_5 - MCPB Channel x Stream Processor State Register 5
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_5 :: GEN_COUNT1 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_5_GEN_COUNT1_SHIFT   0
+
+/***************************************************************************
+ *SP_STATE_REG_6 - MCPB Channel x Stream Processor State Register 6
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_6 :: GEN_COUNT2 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_6_GEN_COUNT2_SHIFT   0
+
+/***************************************************************************
+ *SP_STATE_REG_7 - MCPB Channel x Stream Processor State Register 7
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_7 :: GEN_COUNT3 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_MASK    0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_7_GEN_COUNT3_SHIFT   0
+
+/***************************************************************************
+ *SP_STATE_REG_8 - MCPB Channel x Stream Processor State Register 8
+ ***************************************************************************/
+/* union - case MPEG [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_BASE [31:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_MASK 0xfffffe00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_BASE_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: MPEG :: PCR_EXT [08:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_MASK  0x000001ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_MPEG_PCR_EXT_SHIFT 0
+
+/* union - case DSS [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: DSS :: RTS [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_MASK       0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_DSS_RTS_SHIFT      0
+
+/* union - case PES_or_ES_or_RAW [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_MASK 0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT [23:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_MASK 0x00ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_VALID [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_VALID_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: STREAM_ID_EXT_VALID [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_STREAM_ID_EXT_VALID_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: SUB_ID_VALID [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_SUB_ID_VALID_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: PES_or_ES_or_RAW :: reserved0 [04:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_MASK 0x0000001f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_PES_or_ES_or_RAW_reserved0_SHIFT 0
+
+/* union - case ASF [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: ASF :: ASF_PKT_LEN [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_ASF_ASF_PKT_LEN_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_8 :: BLOCK_MODE :: RA1_WORD1 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_8_BLOCK_MODE_RA1_WORD1_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_9 - MCPB Channel x Stream Processor State Register 9
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: DRAM_REGION [31:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_MASK   0xff000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_DRAM_REGION_SHIFT  24
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SEC_OP_PIPE_SEL [23:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_MASK 0x00c00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SEC_OP_PIPE_SEL_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SECONDARY_PACKET [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SECONDARY_PACKET_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SPID_VERSION [20:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_MASK  0x001c0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SPID_VERSION_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PID_VERSION [17:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_MASK   0x00038000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PID_VERSION_SHIFT  15
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: BUF_OP_PIPE_SEL [14:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_MASK 0x00007000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_BUF_OP_PIPE_SEL_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: LAST_CHUNK [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_MASK    0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_LAST_CHUNK_SHIFT   11
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: reserved0 [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_MASK     0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_reserved0_SHIFT    10
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_INIT [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_MASK    0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_INIT_SHIFT   9
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: SCRAM_START [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_MASK   0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_SCRAM_START_SHIFT  8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_9 :: PKT_BUF_POINTER [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_9_PKT_BUF_POINTER_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_10 - MCPB Channel x Stream Processor State Register 10
+ ***************************************************************************/
+/* union - case NON_BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_reserved0_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR4 [15:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_MASK 0x0000f000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR4_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR3 [11:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_MASK 0x00000f00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR3_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR2 [07:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_MASK 0x000000f0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR2_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: NON_BLOCK_MODE :: EDR1 [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_NON_BLOCK_MODE_EDR1_SHIFT 0
+
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: reserved0 [31:29] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_MASK 0xe0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_reserved0_SHIFT 29
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: BLOCK_MODE_STATES [28:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_MASK 0x1e000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_BLOCK_MODE_STATES_SHIFT 25
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_VALID_5_WORDS [24:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_MASK 0x01f00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_VALID_5_WORDS_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_5_VALID [19:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_MASK 0x000f0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_5_VALID_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_4_VALID [15:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_MASK 0x0000f000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_4_VALID_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_3_VALID [11:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_MASK 0x00000f00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_3_VALID_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_2_VALID [07:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_MASK 0x000000f0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_2_VALID_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_10 :: BLOCK_MODE :: RA1_1_VALID [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_10_BLOCK_MODE_RA1_1_VALID_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_11 - MCPB Channel x Stream Processor State Register 11
+ ***************************************************************************/
+/* union - case BLOCK_MODE [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W5 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W5_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: BLOCK_MODE :: EDR_W4 [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_MASK 0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_BLOCK_MODE_EDR_W4_SHIFT 0
+
+/* union - case ASF [31:00] */
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_11 :: ASF :: ASF_PPI_PKT_LEN [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_11_ASF_ASF_PPI_PKT_LEN_SHIFT 0
+
+/***************************************************************************
+ *SP_STATE_REG_12 - MCPB Channel x Stream Processor State Register 12
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W3 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_MASK       0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W3_SHIFT      16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_12 :: EDR_W2 [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_MASK       0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_12_EDR_W2_SHIFT      0
+
+/***************************************************************************
+ *SP_STATE_REG_13 - MCPB Channel x Stream Processor State Register 13
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: EDR_W1 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_MASK       0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_EDR_W1_SHIFT      16
+
+/* XPT_MEMDMA_MCPB_CH0 :: SP_STATE_REG_13 :: reserved0 [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_MASK    0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_SP_STATE_REG_13_reserved0_SHIFT   0
+
+/***************************************************************************
+ *DMA_BBUFF_CTRL - MCPB Channel x Burst buffer control
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: reserved0 [31:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_MASK     0xfffffc00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_reserved0_SHIFT    10
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: CRC_ERROR_PAUSE_EN [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_CRC_ERROR_PAUSE_EN_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: DMA_BBUFF_SLOT_WISE_READ_EN [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_DMA_BBUFF_SLOT_WISE_READ_EN_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CTRL :: STREAM_PROC_FEED_SIZE [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CTRL_STREAM_PROC_FEED_SIZE_SHIFT 0
+
+/***************************************************************************
+ *DMA_BBUFF_CRC - MCPB Channel x Current CRC value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF_CRC :: CRC_VALUE [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_MASK      0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF_CRC_CRC_VALUE_SHIFT     0
+
+/***************************************************************************
+ *DMA_BBUFF0_RW_STATUS - MCPB Channel x Burst buffer 0 data specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved0 [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved0_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: RESET_PARSER [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_MASK 0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_RESET_PARSER_SHIFT 26
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: DEPTH [25:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_MASK   0x03ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_DEPTH_SHIFT  16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: reserved1 [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_MASK 0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_reserved1_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: BYTE_EN [10:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_MASK 0x00000780
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_BYTE_EN_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RW_STATUS :: CURR_READ [06:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_MASK 0x0000007f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RW_STATUS_CURR_READ_SHIFT 0
+
+/***************************************************************************
+ *DMA_BBUFF0_RO_STATUS - MCPB Channel x Burst buffer 0 control specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_reserved0_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: DESC_SLOT_NUM [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_DESC_SLOT_NUM_SHIFT 13
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: SECURE_RD [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_MASK 0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_SECURE_RD_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: LAST_DATA_TRANS [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_LAST_DATA_TRANS_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: FORCE_TS_CONFIG [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF0_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF0_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0
+
+/***************************************************************************
+ *DMA_BBUFF1_RW_STATUS - MCPB Channel x Burst buffer 1 data specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved0 [31:28] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_MASK 0xf0000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved0_SHIFT 28
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: FIRST_TRANS_AFTER_RUN [27:27] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_MASK 0x08000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_FIRST_TRANS_AFTER_RUN_SHIFT 27
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: RESET_PARSER [26:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_MASK 0x04000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_RESET_PARSER_SHIFT 26
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: DEPTH [25:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_MASK   0x03ff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_DEPTH_SHIFT  16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: reserved1 [15:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_MASK 0x0000f800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_reserved1_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: BYTE_EN [10:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_MASK 0x00000780
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_BYTE_EN_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RW_STATUS :: CURR_READ [06:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_MASK 0x0000007f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RW_STATUS_CURR_READ_SHIFT 0
+
+/***************************************************************************
+ *DMA_BBUFF1_RO_STATUS - MCPB Channel x Burst buffer 1 control specific information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_reserved0_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_END [15:15] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_MASK 0x00008000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_END_SHIFT 15
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PAUSE_AT_DESC_RD [14:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_MASK 0x00004000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PAUSE_AT_DESC_RD_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: DESC_SLOT_NUM [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_DESC_SLOT_NUM_SHIFT 13
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: SECURE_RD [12:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_MASK 0x00001fe0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_SECURE_RD_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: ZERO_BYTE_TRAN [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_ZERO_BYTE_TRAN_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: LAST_DATA_TRANS [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_LAST_DATA_TRANS_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: PUSH_RESIDUAL_BYTES [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_PUSH_RESIDUAL_BYTES_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: FORCE_TS_CONFIG [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_FORCE_TS_CONFIG_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DMA_BBUFF1_RO_STATUS :: IS_ASF_PD_PACKET [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DMA_BBUFF1_RO_STATUS_IS_ASF_PD_PACKET_SHIFT 0
+
+/***************************************************************************
+ *TMEU_BLOCKOUT_CTRL - MCPB Channel x Blockout control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: reserved0 [31:31] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_MASK 0x80000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_reserved0_SHIFT 31
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_SPARE_BW_EN [30:30] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_MASK 0x40000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_SPARE_BW_EN_SHIFT 30
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_BLOCKOUT_CTRL :: BO_COUNT [29:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_MASK  0x3fffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_BLOCKOUT_CTRL_BO_COUNT_SHIFT 0
+
+/***************************************************************************
+ *TMEU_NEXT_BO_MON - MCPB Channel x next Blockout monitor information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_BO_MON :: NEXT_BO_MON [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_BO_MON_NEXT_BO_MON_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_CTRL - MCPB Channel x next Blockout monitor information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved0 [31:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_MASK   0xfe000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved0_SHIFT  25
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_PAUSE_EN [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_MASK 0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_PAUSE_EN_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved1 [23:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_MASK   0x00c00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved1_SHIFT  22
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_RESTART [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_RESTART_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_ERROR_EN [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_ERROR_EN_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_AUTOSTART_ON_FORCE_RESYNC_EN [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_AUTOSTART_ON_FORCE_RESYNC_EN_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_TYPE [18:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_MASK 0x00060000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_TYPE_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: PACING_EN [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_MASK   0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_PACING_EN_SHIFT  16
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: reserved2 [15:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_MASK   0x0000fe00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_reserved2_SHIFT  9
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: GPC_SELECT [08:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_MASK  0x000001f0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_GPC_SELECT_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: RE_TIMESTAMP_EN [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_RE_TIMESTAMP_EN_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: OUTPUT_ATS_MODE [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_OUTPUT_ATS_MODE_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_CTRL :: INPUT_ATS_FORMAT [01:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_MASK 0x00000003
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_CTRL_INPUT_ATS_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *TMEU_REF_DIFF_VALUE_TS_MBOX - MCPB Channel x reference difference value and next Timestamp information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_TS_MBOX :: REF_DIFF_VALUE_TS_MBOX [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_TS_MBOX_REF_DIFF_VALUE_TS_MBOX_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TS_ERR_BOUND_EARLY - MCPB Channel x TS error bound early information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: reserved0 [31:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_MASK 0xff800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_reserved0_SHIFT 23
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_EARLY :: TS_ERROR_BOUND [22:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_MASK 0x007fffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_EARLY_TS_ERROR_BOUND_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TS_ERR_BOUND_LATE - MCPB Channel x TS error bound late information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: reserved0 [31:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_MASK 0xff800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_reserved0_SHIFT 23
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TS_ERR_BOUND_LATE :: TS_ERROR_BOUND [22:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_MASK 0x007fffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TS_ERR_BOUND_LATE_TS_ERROR_BOUND_SHIFT 0
+
+/***************************************************************************
+ *TMEU_NEXT_GPC_MON - MCPB Channel x next Global Pacing Counter and Timestamp monitor information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_NEXT_GPC_MON :: NEXT_GPC_MON [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_NEXT_GPC_MON_NEXT_GPC_MON_SHIFT 0
+
+/***************************************************************************
+ *TMEU_REF_DIFF_VALUE_SIGN - MCPB Channel x reference difference value sign information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: reserved0 [31:14] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_MASK 0xffffc000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_reserved0_SHIFT 14
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_NEXT_TS_VAL [13:13] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_MASK 0x00002000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_NEXT_TS_VAL_SHIFT 13
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: LAST_TS_DEL_VAL [12:12] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_MASK 0x00001000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_LAST_TS_DEL_VAL_SHIFT 12
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_NEXT_TS [11:11] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_MASK 0x00000800
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_NEXT_TS_SHIFT 11
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MON_TS_DEL [10:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_MASK 0x00000400
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MON_TS_DEL_SHIFT 10
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_NEXT_TS [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_NEXT_TS_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MBOX_TS_DEL [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MBOX_TS_DEL_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: GPC_MS2_BITS [07:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_MASK 0x000000c0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_GPC_MS2_BITS_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: PCR_TS_MS2_BITS [05:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_MASK 0x00000030
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_PCR_TS_MS2_BITS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_REF_DIFF_VALUE_SIGN :: MSB_REF_DIFF_VALUE_SIGN [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_REF_DIFF_VALUE_SIGN_MSB_REF_DIFF_VALUE_SIGN_SHIFT 0
+
+/***************************************************************************
+ *TMEU_PES_PACING_CTRL - MCPB Channel x PES pacing control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved0 [31:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_MASK 0xfe000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved0_SHIFT 25
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_MASK 0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_CHECK_EN_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: reserved1 [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_MASK 0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_reserved1_SHIFT 23
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_PES_PACING_CTRL :: NEXT_PACKET_TIMESTAMP_ERROR_BOUND [22:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_MASK 0x007fffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_PES_PACING_CTRL_NEXT_PACKET_TIMESTAMP_ERROR_BOUND_SHIFT 0
+
+/***************************************************************************
+ *TMEU_SLOT_STATUS - MCPB Channel x Slot 0 and Slot 1 information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved0 [31:26] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_MASK   0xfc000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved0_SHIFT  26
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_1 [25:25] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_MASK 0x02000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_1_SHIFT 25
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_1 [24:24] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_MASK 0x01000000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_1_SHIFT 24
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_1 [23:23] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_MASK 0x00800000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_1_SHIFT 23
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_1 [22:22] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_MASK 0x00400000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_1_SHIFT 22
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_1 [21:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_MASK 0x00200000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_1_SHIFT 21
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_1 [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_1_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_1 [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_1_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_1 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_1_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_1 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_1_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_1 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_1_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: reserved1 [15:10] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_MASK   0x0000fc00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_reserved1_SHIFT  10
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PARITY_ERROR_0 [09:09] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_MASK 0x00000200
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PARITY_ERROR_0_SHIFT 9
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: MARKED_DISCON_IND_0 [08:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_MASK 0x00000100
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_MARKED_DISCON_IND_0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PKT2PKT_TIMESTAMP_DELTA_VALID_0 [07:07] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_MASK 0x00000080
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PKT2PKT_TIMESTAMP_DELTA_VALID_0_SHIFT 7
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: NEXT_TIMESTAMP_VALID_0 [06:06] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_MASK 0x00000040
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_NEXT_TIMESTAMP_VALID_0_SHIFT 6
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FORCE_RESYNC_0 [05:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_MASK 0x00000020
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FORCE_RESYNC_0_SHIFT 5
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_FIRST_PKT_AFTER_RUN_0 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_FIRST_PKT_AFTER_RUN_0_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FORCE_RESYNC_0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FORCE_RESYNC_0_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: FIRST_PKT_AFTER_RUN_0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_FIRST_PKT_AFTER_RUN_0_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: PCR_VALID_0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_PCR_VALID_0_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_SLOT_STATUS :: TIMESTAMP_VALID_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_SLOT_STATUS_TIMESTAMP_VALID_0_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_SLOT0_REG1 - MCPB Channel x timing information for Slot 0
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG1 :: TIMESTAMP_OR_NEXT_TS_0 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG1_TIMESTAMP_OR_NEXT_TS_0_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_SLOT0_REG2 - MCPB Channel x timing information for Slot 0
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT0_REG2 :: PCR_OR_TS_DELTA_0 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT0_REG2_PCR_OR_TS_DELTA_0_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_SLOT1_REG1 - MCPB Channel x timing information for Slot 1
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG1 :: TIMESTAMP_OR_NEXT_TS_1 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG1_TIMESTAMP_OR_NEXT_TS_1_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_SLOT1_REG2 - MCPB Channel x timing information for Slot 1
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_SLOT1_REG2 :: PCR_OR_TS_DELTA_1 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_SLOT1_REG2_PCR_OR_TS_DELTA_1_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA - MCPB Channel x last TS delta value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA :: LAST_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_TIMESTAMP_DELTA_LAST_TIMESTAMP_DELTA_SHIFT 0
+
+/***************************************************************************
+ *TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP - MCPB Channel x last NEXT TS value
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP :: LAST_NEXT_TIMESTAMP [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_TMEU_TIMING_INFO_LAST_NEXT_TIMESTAMP_LAST_NEXT_TIMESTAMP_SHIFT 0
+
+/***************************************************************************
+ *DCPM_STATUS - MCPB Channel x DCPM status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: reserved0 [31:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_MASK        0xfffffff8
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_reserved0_SHIFT       3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_ADDRESS_STATUS [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_ADDRESS_STATUS_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DESC_DONE_INT_ADDRESS_STATUS [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DESC_DONE_INT_ADDRESS_STATUS_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_STATUS :: DATA_ADDR_CUR_DESC_ADDR_STATUS [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_STATUS_DATA_ADDR_CUR_DESC_ADDR_STATUS_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DESC_ADDR - MCPB Channel x DCPM descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ADDRESS [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_MASK  0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ADDRESS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR :: DESC_ID [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_MASK       0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_DESC_ID_SHIFT      0
+
+/***************************************************************************
+ *DCPM_DESC_DONE_INT_ADDR - MCPB Channel x DCPM descriptor done interrupt address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ADDRESS [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ADDRESS_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_DONE_INT_ADDR :: DESC_DONE_INT_ID [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_DONE_INT_ADDR_DESC_DONE_INT_ID_SHIFT 0
+
+/***************************************************************************
+ *DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL - MCPB Channel x Pause after group of packets control information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: PAUSE_AFTER_PACKET_COUNT [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_PAUSE_AFTER_PACKET_COUNT_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: BTP_PACKET_GROUP_ID [15:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_MASK 0x0000ff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_BTP_PACKET_GROUP_ID_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: reserved0 [07:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_MASK 0x000000f8
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_reserved0_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DIS_DUPLICATION_COUNTING [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DIS_DUPLICATION_COUNTING_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: DONT_SEND_BTP_PACKET [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_DONT_SEND_BTP_PACKET_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL :: ENABLE [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_CTRL_ENABLE_SHIFT 0
+
+/***************************************************************************
+ *DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER - MCPB Channel x Pause after group of packets local packet counter
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: reserved0 [31:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_MASK 0xffff0000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_reserved0_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER :: PKT_COUNTER [15:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_MASK 0x0000ffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_PAUSE_AFTER_GROUP_PACKETS_PKT_COUNTER_PKT_COUNTER_SHIFT 0
+
+/***************************************************************************
+ *DCPM_LOCAL_PACKET_COUNTER - MCPB Channel x local packet counter
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_LOCAL_PACKET_COUNTER :: PACKET_COUNTER [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_LOCAL_PACKET_COUNTER_PACKET_COUNTER_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_UPPER - MCPB Channel x DCPM data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_UPPER :: DATA_ADDR [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_UPPER_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_LOWER - MCPB Channel x DCPM data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_LOWER :: DATA_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_LOWER_DATA_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DCPM_CURR_DESC_ADDR - MCPB Channel x DCPM current descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_CURR_DESC_ADDR :: CUR_DESC_ADDR [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_CURR_DESC_ADDR_CUR_DESC_ADDR_SHIFT 0
+
+/***************************************************************************
+ *DCPM_SLOT_STATUS - MCPB Channel x DCPM slot status information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved0 [31:21] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_MASK   0xffe00000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved0_SHIFT  21
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_1 [20:20] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_MASK 0x00100000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_1_SHIFT 20
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_1 [19:19] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_MASK 0x00080000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_1_SHIFT 19
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_1 [18:18] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_MASK 0x00040000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_1_SHIFT 18
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_1 [17:17] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_MASK 0x00020000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_1_SHIFT 17
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_1 [16:16] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_MASK 0x00010000
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_1_SHIFT 16
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: reserved1 [15:05] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_MASK   0x0000ffe0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_reserved1_SHIFT  5
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_READ_INTR_0 [04:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_MASK 0x00000010
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_READ_INTR_0_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: GENERATE_PAUSE_AT_DESC_END_INTR_0 [03:03] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_MASK 0x00000008
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_GENERATE_PAUSE_AT_DESC_END_INTR_0_SHIFT 3
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_UPDATE_0 [02:02] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_MASK 0x00000004
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_UPDATE_0_SHIFT 2
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DESC_DONE_INT_UPDATE_0 [01:01] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_MASK 0x00000002
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DESC_DONE_INT_UPDATE_0_SHIFT 1
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_SLOT_STATUS :: DATA_ADDR_CUR_DESC_ADDR_UPDATE_0 [00:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_MASK 0x00000001
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_SLOT_STATUS_DATA_ADDR_CUR_DESC_ADDR_UPDATE_0_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DESC_ADDR_SLOT_0 - MCPB Channel x DCPM completed slot 0 descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ADDR_SLOT_0 [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ADDR_SLOT_0_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_0 :: DESC_ID_SLOT_0 [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_0_DESC_ID_SLOT_0_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_SLOT_0_UPPER - MCPB Channel x DCPM completed slot 0 data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_UPPER :: DATA_ADDR_0 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_UPPER_DATA_ADDR_0_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_SLOT_0_LOWER - MCPB Channel x DCPM completed slot 0 data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_0_LOWER :: DATA_ADDR_0 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_0_LOWER_DATA_ADDR_0_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DESC_ADDR_SLOT_1 - MCPB Channel x DCPM completed slot 1 descriptor address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ADDR_SLOT_1 [31:04] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_MASK 0xfffffff0
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ADDR_SLOT_1_SHIFT 4
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DESC_ADDR_SLOT_1 :: DESC_ID_SLOT_1 [03:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_MASK 0x0000000f
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DESC_ADDR_SLOT_1_DESC_ID_SLOT_1_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_SLOT_1_UPPER - MCPB Channel x DCPM completed slot 1 data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: reserved0 [31:08] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_MASK 0xffffff00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_reserved0_SHIFT 8
+
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_UPPER :: DATA_ADDR_1 [07:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_MASK 0x000000ff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_UPPER_DATA_ADDR_1_SHIFT 0
+
+/***************************************************************************
+ *DCPM_DATA_ADDR_SLOT_1_LOWER - MCPB Channel x DCPM completed slot 1 data address information
+ ***************************************************************************/
+/* XPT_MEMDMA_MCPB_CH0 :: DCPM_DATA_ADDR_SLOT_1_LOWER :: DATA_ADDR_1 [31:00] */
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_MASK 0xffffffff
+#define BCHP_XPT_MEMDMA_MCPB_CH0_DCPM_DATA_ADDR_SLOT_1_LOWER_DATA_ADDR_1_SHIFT 0
+
+#endif /* #ifndef BCHP_XPT_MEMDMA_MCPB_CH0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_pmu.h b/include/linux/brcmstb/7250b0/bchp_xpt_pmu.h
new file mode 100644
index 000000000000..be3bfd6149b6
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_pmu.h
@@ -0,0 +1,397 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Nov 19 03:12:51 2014
+ *                 Full Compile MD5 Checksum 090c477e923b422fcfb8d82b056c5fac
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              3f553d4cd3bba7438ffdad1405cbf563
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_PMU_H__
+#define BCHP_XPT_PMU_H__
+
+/***************************************************************************
+ *XPT_PMU - XPT PMU Control Registers
+ ***************************************************************************/
+#define BCHP_XPT_PMU_CLK_CTRL                    0x00a00200 /* Power Management control */
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL               0x00a00204 /* Power Management control */
+#define BCHP_XPT_PMU_RBUS_RSP_VAL                0x00a00208 /* Power Management control */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL                0x00a0020c /* Power Management control */
+#define BCHP_XPT_PMU_STBY_CTRL                   0x00a00210 /* Power Management control */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL               0x00a00214 /* Power Management control */
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL         0x00a00218 /* Power Management control */
+
+/***************************************************************************
+ *CLK_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: CLK_CTRL :: reserved0 [31:20] */
+#define BCHP_XPT_PMU_CLK_CTRL_reserved0_MASK                       0xfff00000
+#define BCHP_XPT_PMU_CLK_CTRL_reserved0_SHIFT                      20
+
+/* XPT_PMU :: CLK_CTRL :: TSIO_DISABLE [19:19] */
+#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_MASK                    0x00080000
+#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_SHIFT                   19
+#define BCHP_XPT_PMU_CLK_CTRL_TSIO_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: MEMDMA_DISABLE [18:18] */
+#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_MASK                  0x00040000
+#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_SHIFT                 18
+#define BCHP_XPT_PMU_CLK_CTRL_MEMDMA_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: FULL_PID_PARSER_DISABLE [17:17] */
+#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_MASK         0x00020000
+#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_SHIFT        17
+#define BCHP_XPT_PMU_CLK_CTRL_FULL_PID_PARSER_DISABLE_DEFAULT      0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: WAKEUP_DISABLE [16:16] */
+#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_MASK                  0x00010000
+#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_SHIFT                 16
+#define BCHP_XPT_PMU_CLK_CTRL_WAKEUP_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: RMX1_DISABLE [15:15] */
+#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_MASK                    0x00008000
+#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_SHIFT                   15
+#define BCHP_XPT_PMU_CLK_CTRL_RMX1_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: RMX0_DISABLE [14:14] */
+#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_MASK                    0x00004000
+#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_SHIFT                   14
+#define BCHP_XPT_PMU_CLK_CTRL_RMX0_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: MPOD_DISABLE [13:13] */
+#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_MASK                    0x00002000
+#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_SHIFT                   13
+#define BCHP_XPT_PMU_CLK_CTRL_MPOD_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: XPT_IO_DISABLE [12:12] */
+#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_MASK                  0x00001000
+#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_SHIFT                 12
+#define BCHP_XPT_PMU_CLK_CTRL_XPT_IO_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: PB_DISABLE [11:11] */
+#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_MASK                      0x00000800
+#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_SHIFT                     11
+#define BCHP_XPT_PMU_CLK_CTRL_PB_DISABLE_DEFAULT                   0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: PSUB_DISABLE [10:10] */
+#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_MASK                    0x00000400
+#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_SHIFT                   10
+#define BCHP_XPT_PMU_CLK_CTRL_PSUB_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: BUS_IF_DISABLE [09:09] */
+#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_MASK                  0x00000200
+#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_SHIFT                 9
+#define BCHP_XPT_PMU_CLK_CTRL_BUS_IF_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: PCROFFSET_DISABLE [08:08] */
+#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_MASK               0x00000100
+#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_SHIFT              8
+#define BCHP_XPT_PMU_CLK_CTRL_PCROFFSET_DISABLE_DEFAULT            0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: RAVE_DISABLE [07:07] */
+#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_MASK                    0x00000080
+#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_SHIFT                   7
+#define BCHP_XPT_PMU_CLK_CTRL_RAVE_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: MSG_DISABLE [06:06] */
+#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_MASK                     0x00000040
+#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_SHIFT                    6
+#define BCHP_XPT_PMU_CLK_CTRL_MSG_DISABLE_DEFAULT                  0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: DPCR_DISABLE [05:05] */
+#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_MASK                    0x00000020
+#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_SHIFT                   5
+#define BCHP_XPT_PMU_CLK_CTRL_DPCR_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: XMEMIF_216_DISABLE [04:04] */
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_MASK              0x00000010
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_SHIFT             4
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_216_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: XMEMIF_108_DISABLE [03:03] */
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_MASK              0x00000008
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_SHIFT             3
+#define BCHP_XPT_PMU_CLK_CTRL_XMEMIF_108_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: XCBUFF_DISABLE [02:02] */
+#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_MASK                  0x00000004
+#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_SHIFT                 2
+#define BCHP_XPT_PMU_CLK_CTRL_XCBUFF_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: RSBUFF_DISABLE [01:01] */
+#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_MASK                  0x00000002
+#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_SHIFT                 1
+#define BCHP_XPT_PMU_CLK_CTRL_RSBUFF_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: CLK_CTRL :: FE_DISABLE [00:00] */
+#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_MASK                      0x00000001
+#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_SHIFT                     0
+#define BCHP_XPT_PMU_CLK_CTRL_FE_DISABLE_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *RBUS_RSP_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: RBUS_RSP_CTRL :: reserved0 [31:02] */
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_reserved0_MASK                  0xfffffffc
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_reserved0_SHIFT                 2
+
+/* XPT_PMU :: RBUS_RSP_CTRL :: RBUS_WR_RSP [01:01] */
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_MASK                0x00000002
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_SHIFT               1
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_WR_RSP_DEFAULT             0x00000000
+
+/* XPT_PMU :: RBUS_RSP_CTRL :: RBUS_RD_RSP [00:00] */
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_MASK                0x00000001
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_SHIFT               0
+#define BCHP_XPT_PMU_RBUS_RSP_CTRL_RBUS_RD_RSP_DEFAULT             0x00000000
+
+/***************************************************************************
+ *RBUS_RSP_VAL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: RBUS_RSP_VAL :: RD_RSP_VAL [31:00] */
+#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_MASK                  0xffffffff
+#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_SHIFT                 0
+#define BCHP_XPT_PMU_RBUS_RSP_VAL_RD_RSP_VAL_DEFAULT               0xdeaddead
+
+/***************************************************************************
+ *PSM_VDD_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: PSM_VDD_CTRL :: reserved0 [31:14] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_reserved0_MASK                   0xffffc000
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_reserved0_SHIFT                  14
+
+/* XPT_PMU :: PSM_VDD_CTRL :: TSIO_DISABLE [13:13] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_MASK                0x00002000
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_SHIFT               13
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_TSIO_DISABLE_DEFAULT             0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: MEMDMA_DISABLE [12:12] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_MASK              0x00001000
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_SHIFT             12
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MEMDMA_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: PB_DISABLE [11:11] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_MASK                  0x00000800
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_SHIFT                 11
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PB_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: PSUB_DISABLE [10:10] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_MASK                0x00000400
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_SHIFT               10
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PSUB_DISABLE_DEFAULT             0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: PCROFFSET_DISABLE [09:09] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_MASK           0x00000200
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_SHIFT          9
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_PCROFFSET_DISABLE_DEFAULT        0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: RAVE_DISABLE [08:08] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_MASK                0x00000100
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_SHIFT               8
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_DISABLE_DEFAULT             0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: MSG_DISABLE [07:07] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_MASK                 0x00000080
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_SHIFT                7
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_MSG_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: XMEMIF_DISABLE [06:06] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_MASK              0x00000040
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_SHIFT             6
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XMEMIF_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: FPP_DISABLE [05:05] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_MASK                 0x00000020
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_SHIFT                5
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FPP_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: XCBUFF_DISABLE [04:04] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_MASK              0x00000010
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_SHIFT             4
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_XCBUFF_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: RSBUFF_DISABLE [03:03] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_MASK              0x00000008
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_SHIFT             3
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RSBUFF_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: FE_DISABLE [02:02] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_MASK                  0x00000004
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_SHIFT                 2
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_FE_DISABLE_DEFAULT               0x00000000
+
+/* XPT_PMU :: PSM_VDD_CTRL :: WAKEUP_CFG_DISABLE [01:01] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_MASK          0x00000002
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_SHIFT         1
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_WAKEUP_CFG_DISABLE_DEFAULT       0x00000001
+
+/* XPT_PMU :: PSM_VDD_CTRL :: RAVE_IMEM_DISABLE [00:00] */
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_MASK           0x00000001
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_SHIFT          0
+#define BCHP_XPT_PMU_PSM_VDD_CTRL_RAVE_IMEM_DISABLE_DEFAULT        0x00000001
+
+/***************************************************************************
+ *STBY_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: STBY_CTRL :: reserved0 [31:14] */
+#define BCHP_XPT_PMU_STBY_CTRL_reserved0_MASK                      0xffffc000
+#define BCHP_XPT_PMU_STBY_CTRL_reserved0_SHIFT                     14
+
+/* XPT_PMU :: STBY_CTRL :: TSIO_DISABLE [13:13] */
+#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_MASK                   0x00002000
+#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_SHIFT                  13
+#define BCHP_XPT_PMU_STBY_CTRL_TSIO_DISABLE_DEFAULT                0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: MEMDMA_DISABLE [12:12] */
+#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_MASK                 0x00001000
+#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_SHIFT                12
+#define BCHP_XPT_PMU_STBY_CTRL_MEMDMA_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: PB_DISABLE [11:11] */
+#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_MASK                     0x00000800
+#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_SHIFT                    11
+#define BCHP_XPT_PMU_STBY_CTRL_PB_DISABLE_DEFAULT                  0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: PSUB_DISABLE [10:10] */
+#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_MASK                   0x00000400
+#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_SHIFT                  10
+#define BCHP_XPT_PMU_STBY_CTRL_PSUB_DISABLE_DEFAULT                0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: PCROFFSET_DISABLE [09:09] */
+#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_MASK              0x00000200
+#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_SHIFT             9
+#define BCHP_XPT_PMU_STBY_CTRL_PCROFFSET_DISABLE_DEFAULT           0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: RAVE_DISABLE [08:08] */
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_MASK                   0x00000100
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_SHIFT                  8
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_DISABLE_DEFAULT                0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: MSG_DISABLE [07:07] */
+#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_MASK                    0x00000080
+#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_SHIFT                   7
+#define BCHP_XPT_PMU_STBY_CTRL_MSG_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: XMEMIF_DISABLE [06:06] */
+#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_MASK                 0x00000040
+#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_SHIFT                6
+#define BCHP_XPT_PMU_STBY_CTRL_XMEMIF_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: FPP_DISABLE [05:05] */
+#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_MASK                    0x00000020
+#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_SHIFT                   5
+#define BCHP_XPT_PMU_STBY_CTRL_FPP_DISABLE_DEFAULT                 0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: XCBUFF_DISABLE [04:04] */
+#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_MASK                 0x00000010
+#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_SHIFT                4
+#define BCHP_XPT_PMU_STBY_CTRL_XCBUFF_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: RSBUFF_DISABLE [03:03] */
+#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_MASK                 0x00000008
+#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_SHIFT                3
+#define BCHP_XPT_PMU_STBY_CTRL_RSBUFF_DISABLE_DEFAULT              0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: FE_DISABLE [02:02] */
+#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_MASK                     0x00000004
+#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_SHIFT                    2
+#define BCHP_XPT_PMU_STBY_CTRL_FE_DISABLE_DEFAULT                  0x00000000
+
+/* XPT_PMU :: STBY_CTRL :: WAKEUP_CFG_DISABLE [01:01] */
+#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_MASK             0x00000002
+#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_SHIFT            1
+#define BCHP_XPT_PMU_STBY_CTRL_WAKEUP_CFG_DISABLE_DEFAULT          0x00000001
+
+/* XPT_PMU :: STBY_CTRL :: RAVE_IMEM_DISABLE [00:00] */
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_MASK              0x00000001
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_SHIFT             0
+#define BCHP_XPT_PMU_STBY_CTRL_RAVE_IMEM_DISABLE_DEFAULT           0x00000001
+
+/***************************************************************************
+ *MEM_INIT_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: MEM_INIT_CTRL :: reserved0 [31:06] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_reserved0_MASK                  0xffffffc0
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_reserved0_SHIFT                 6
+
+/* XPT_PMU :: MEM_INIT_CTRL :: FE_PID_SPID_MEM_INIT [05:05] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_MASK       0x00000020
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_SHIFT      5
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FE_PID_SPID_MEM_INIT_DEFAULT    0x00000000
+
+/* XPT_PMU :: MEM_INIT_CTRL :: FPP_SCM_INIT [04:04] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_MASK               0x00000010
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_SHIFT              4
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_FPP_SCM_INIT_DEFAULT            0x00000000
+
+/* XPT_PMU :: MEM_INIT_CTRL :: PCROFFSET_PID_MEM_INIT [03:03] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_MASK     0x00000008
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_SHIFT    3
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_PID_MEM_INIT_DEFAULT  0x00000000
+
+/* XPT_PMU :: MEM_INIT_CTRL :: PCROFFSET_CFG_MEM_INIT [02:02] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_MASK     0x00000004
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_SHIFT    2
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_PCROFFSET_CFG_MEM_INIT_DEFAULT  0x00000000
+
+/* XPT_PMU :: MEM_INIT_CTRL :: MSG_PID2BUF_MEM_INIT [01:01] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_MASK       0x00000002
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_SHIFT      1
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_MSG_PID2BUF_MEM_INIT_DEFAULT    0x00000000
+
+/* XPT_PMU :: MEM_INIT_CTRL :: WAKEUP_CFG_MEM_INIT [00:00] */
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_MASK        0x00000001
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_SHIFT       0
+#define BCHP_XPT_PMU_MEM_INIT_CTRL_WAKEUP_CFG_MEM_INIT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *MEMDMA_SW_INIT_CTRL - Power Management control
+ ***************************************************************************/
+/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: reserved0 [31:02] */
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_reserved0_MASK            0xfffffffc
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_reserved0_SHIFT           2
+
+/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: PMU_MEMDMA_SW_INIT [01:01] */
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_MASK   0x00000002
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SHIFT  1
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_DEFAULT 0x00000000
+
+/* XPT_PMU :: MEMDMA_SW_INIT_CTRL :: PMU_MEMDMA_SW_INIT_SEL [00:00] */
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_MASK 0x00000001
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_SHIFT 0
+#define BCHP_XPT_PMU_MEMDMA_SW_INIT_CTRL_PMU_MEMDMA_SW_INIT_SEL_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_XPT_PMU_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_security_ns.h b/include/linux/brcmstb/7250b0/bchp_xpt_security_ns.h
new file mode 100644
index 000000000000..6b3753b8386e
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_security_ns.h
@@ -0,0 +1,593 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Tue Mar 25 03:12:52 2014
+ *                 Full Compile MD5 Checksum 4593e257971177815cc4a01913c4bcb6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              eacd1ac88c53d22793d18644f3aae7d3
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_SECURITY_NS_H__
+#define BCHP_XPT_SECURITY_NS_H__
+
+/***************************************************************************
+ *XPT_SECURITY_NS - XPT_SECURITY_NS Registers
+ ***************************************************************************/
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0  0x00380200 /* Streamscram0 Blockout count 0 - RAVE */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1  0x00380204 /* Streamscram0 Blockout count 1 - RS Buffer */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2  0x00380208 /* Streamscram0 Blockout count 2 - Playback */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3  0x0038020c /* Streamscram0 Blockout count 3 - DMA */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0  0x00380210 /* Streamscram1 Blockout count 0 - RAVE */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1  0x00380214 /* Streamscram1 Blockout count 1 - RS Buffer */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2  0x00380218 /* Streamscram1 Blockout count 2 - Playback */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3  0x0038021c /* Streamscram1 Blockout count 3 - DMA */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL       0x00380220 /* Streamscram0/1 Blockout Control */
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL       0x00380224 /* Watchdog timer control */
+#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS    0x00380228 /* SEC_POWAY cipher core status */
+#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE      0x0038022c /* semaphore for MAC0 (CMAC/CBCMAC) */
+#define BCHP_XPT_SECURITY_NS_MAC0_0              0x00380230 /* MAC0[31:0] */
+#define BCHP_XPT_SECURITY_NS_MAC0_1              0x00380234 /* MAC0[63:32] */
+#define BCHP_XPT_SECURITY_NS_MAC0_2              0x00380238 /* MAC0[95:64] */
+#define BCHP_XPT_SECURITY_NS_MAC0_3              0x0038023c /* MAC0[127:96] */
+#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE      0x00380240 /* semaphore for MAC1 (CMAC/CBCMAC) */
+#define BCHP_XPT_SECURITY_NS_MAC1_0              0x00380244 /* MAC1[31:0] */
+#define BCHP_XPT_SECURITY_NS_MAC1_1              0x00380248 /* MAC1[63:32] */
+#define BCHP_XPT_SECURITY_NS_MAC1_2              0x0038024c /* MAC1[95:64] */
+#define BCHP_XPT_SECURITY_NS_MAC1_3              0x00380250 /* MAC1[127:96] */
+#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE      0x00380254 /* semaphore for MAC2 (CMAC/CBCMAC) */
+#define BCHP_XPT_SECURITY_NS_MAC2_0              0x00380258 /* MAC2[31:0] */
+#define BCHP_XPT_SECURITY_NS_MAC2_1              0x0038025c /* MAC2[63:32] */
+#define BCHP_XPT_SECURITY_NS_MAC2_2              0x00380260 /* MAC2[95:64] */
+#define BCHP_XPT_SECURITY_NS_MAC2_3              0x00380264 /* MAC2[127:96] */
+#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE      0x00380268 /* semaphore for MAC3 (CMAC/CBCMAC) */
+#define BCHP_XPT_SECURITY_NS_MAC3_0              0x0038026c /* MAC3[31:0] */
+#define BCHP_XPT_SECURITY_NS_MAC3_1              0x00380270 /* MAC3[63:32] */
+#define BCHP_XPT_SECURITY_NS_MAC3_2              0x00380274 /* MAC3[95:64] */
+#define BCHP_XPT_SECURITY_NS_MAC3_3              0x00380278 /* MAC3[127:96] */
+#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE     0x0038027c /* semaphore for SHA20 */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL          0x00380280 /* SHA2 Control for Module 0 */
+#define BCHP_XPT_SECURITY_NS_SHA20_0             0x00380284 /* SHA20[31:0] */
+#define BCHP_XPT_SECURITY_NS_SHA20_1             0x00380288 /* SHA20[63:32] */
+#define BCHP_XPT_SECURITY_NS_SHA20_2             0x0038028c /* SHA20[95:64] */
+#define BCHP_XPT_SECURITY_NS_SHA20_3             0x00380290 /* SHA20[127:96] */
+#define BCHP_XPT_SECURITY_NS_SHA20_4             0x00380294 /* SHA20[159:128] */
+#define BCHP_XPT_SECURITY_NS_SHA20_5             0x00380298 /* SHA20[191:160] */
+#define BCHP_XPT_SECURITY_NS_SHA20_6             0x0038029c /* SHA20[223:192] */
+#define BCHP_XPT_SECURITY_NS_SHA20_7             0x003802a0 /* SHA20[255:224] */
+#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE     0x003802a4 /* semaphore for SHA21 */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL          0x003802a8 /* SHA2 Control for Module 1 */
+#define BCHP_XPT_SECURITY_NS_SHA21_0             0x003802ac /* SHA21[31:0] */
+#define BCHP_XPT_SECURITY_NS_SHA21_1             0x003802b0 /* SHA21[63:32] */
+#define BCHP_XPT_SECURITY_NS_SHA21_2             0x003802b4 /* SHA21[95:64] */
+#define BCHP_XPT_SECURITY_NS_SHA21_3             0x003802b8 /* SHA21[127:96] */
+#define BCHP_XPT_SECURITY_NS_SHA21_4             0x003802bc /* SHA21[159:128] */
+#define BCHP_XPT_SECURITY_NS_SHA21_5             0x003802c0 /* SHA21[191:160] */
+#define BCHP_XPT_SECURITY_NS_SHA21_6             0x003802c4 /* SHA21[223:192] */
+#define BCHP_XPT_SECURITY_NS_SHA21_7             0x003802c8 /* SHA21[255:224] */
+
+/***************************************************************************
+ *S0_BLOCKOUT_COUNT0 - Streamscram0 Blockout count 0 - RAVE
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT0 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT0 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S0_BLOCKOUT_COUNT1 - Streamscram0 Blockout count 1 - RS Buffer
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT1 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT1 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S0_BLOCKOUT_COUNT2 - Streamscram0 Blockout count 2 - Playback
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT2 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT2 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S0_BLOCKOUT_COUNT3 - Streamscram0 Blockout count 3 - DMA
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT3 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S0_BLOCKOUT_COUNT3 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S0_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S1_BLOCKOUT_COUNT0 - Streamscram1 Blockout count 0 - RAVE
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT0 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT0 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT0_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S1_BLOCKOUT_COUNT1 - Streamscram1 Blockout count 1 - RS Buffer
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT1 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT1 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT1_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S1_BLOCKOUT_COUNT2 - Streamscram1 Blockout count 2 - Playback
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT2 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT2 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT2_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *S1_BLOCKOUT_COUNT3 - Streamscram1 Blockout count 3 - DMA
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT3 :: reserved0 [31:16] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_reserved0_MASK     0xffff0000
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_reserved0_SHIFT    16
+
+/* XPT_SECURITY_NS :: S1_BLOCKOUT_COUNT3 :: BLOCKOUT_COUNT [15:00] */
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_MASK 0x0000ffff
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_S1_BLOCKOUT_COUNT3_BLOCKOUT_COUNT_DEFAULT 0x0000032c
+
+/***************************************************************************
+ *BLOCKOUT_CTRL - Streamscram0/1 Blockout Control
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: reserved0 [31:04] */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_reserved0_SHIFT         4
+
+/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE3_DISALLOW_UNUSED [03:03] */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE3_DISALLOW_UNUSED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE2_DISALLOW_UNUSED [02:02] */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_MASK 0x00000004
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE2_DISALLOW_UNUSED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE1_DISALLOW_UNUSED [01:01] */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE1_DISALLOW_UNUSED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS :: BLOCKOUT_CTRL :: PIPE0_DISALLOW_UNUSED [00:00] */
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_MASK 0x00000001
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_BLOCKOUT_CTRL_PIPE0_DISALLOW_UNUSED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WATCHDOG_CTRL - Watchdog timer control
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: WATCHDOG_CTRL :: reserved0 [31:01] */
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_reserved0_MASK          0xfffffffe
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_reserved0_SHIFT         1
+
+/* XPT_SECURITY_NS :: WATCHDOG_CTRL :: WATCHDOG_EN [00:00] */
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_MASK        0x00000001
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_SHIFT       0
+#define BCHP_XPT_SECURITY_NS_WATCHDOG_CTRL_WATCHDOG_EN_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_POWAY_STATUS - SEC_POWAY cipher core status
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SEC_POWAY_STATUS :: SEC_POWAY_STATUS [31:00] */
+#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS_SEC_POWAY_STATUS_MASK 0xffffffff
+#define BCHP_XPT_SECURITY_NS_SEC_POWAY_STATUS_SEC_POWAY_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MAC0_SEMAPHORE - semaphore for MAC0 (CMAC/CBCMAC)
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC0_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_reserved0_MASK         0xffffff00
+#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_reserved0_SHIFT        8
+
+/* XPT_SECURITY_NS :: MAC0_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_semaphore_ctrl_MASK    0x000000ff
+#define BCHP_XPT_SECURITY_NS_MAC0_SEMAPHORE_semaphore_ctrl_SHIFT   0
+
+/***************************************************************************
+ *MAC0_0 - MAC0[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC0_0 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC0_0_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC0_0_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC0_1 - MAC0[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC0_1 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC0_1_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC0_1_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC0_2 - MAC0[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC0_2 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC0_2_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC0_2_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC0_3 - MAC0[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC0_3 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC0_3_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC0_3_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC1_SEMAPHORE - semaphore for MAC1 (CMAC/CBCMAC)
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC1_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_reserved0_MASK         0xffffff00
+#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_reserved0_SHIFT        8
+
+/* XPT_SECURITY_NS :: MAC1_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_semaphore_ctrl_MASK    0x000000ff
+#define BCHP_XPT_SECURITY_NS_MAC1_SEMAPHORE_semaphore_ctrl_SHIFT   0
+
+/***************************************************************************
+ *MAC1_0 - MAC1[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC1_0 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC1_0_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC1_0_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC1_1 - MAC1[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC1_1 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC1_1_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC1_1_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC1_2 - MAC1[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC1_2 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC1_2_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC1_2_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC1_3 - MAC1[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC1_3 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC1_3_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC1_3_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC2_SEMAPHORE - semaphore for MAC2 (CMAC/CBCMAC)
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC2_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_reserved0_MASK         0xffffff00
+#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_reserved0_SHIFT        8
+
+/* XPT_SECURITY_NS :: MAC2_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_semaphore_ctrl_MASK    0x000000ff
+#define BCHP_XPT_SECURITY_NS_MAC2_SEMAPHORE_semaphore_ctrl_SHIFT   0
+
+/***************************************************************************
+ *MAC2_0 - MAC2[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC2_0 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC2_0_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC2_0_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC2_1 - MAC2[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC2_1 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC2_1_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC2_1_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC2_2 - MAC2[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC2_2 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC2_2_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC2_2_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC2_3 - MAC2[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC2_3 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC2_3_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC2_3_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC3_SEMAPHORE - semaphore for MAC3 (CMAC/CBCMAC)
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC3_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_reserved0_MASK         0xffffff00
+#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_reserved0_SHIFT        8
+
+/* XPT_SECURITY_NS :: MAC3_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_semaphore_ctrl_MASK    0x000000ff
+#define BCHP_XPT_SECURITY_NS_MAC3_SEMAPHORE_semaphore_ctrl_SHIFT   0
+
+/***************************************************************************
+ *MAC3_0 - MAC3[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC3_0 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC3_0_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC3_0_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC3_1 - MAC3[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC3_1 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC3_1_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC3_1_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC3_2 - MAC3[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC3_2 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC3_2_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC3_2_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *MAC3_3 - MAC3[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: MAC3_3 :: MAC_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_MAC3_3_MAC_OUTPUT_MASK                0xffffffff
+#define BCHP_XPT_SECURITY_NS_MAC3_3_MAC_OUTPUT_SHIFT               0
+
+/***************************************************************************
+ *SHA20_SEMAPHORE - semaphore for SHA20
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_reserved0_MASK        0xffffff00
+#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_reserved0_SHIFT       8
+
+/* XPT_SECURITY_NS :: SHA20_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_semaphore_ctrl_MASK   0x000000ff
+#define BCHP_XPT_SECURITY_NS_SHA20_SEMAPHORE_semaphore_ctrl_SHIFT  0
+
+/***************************************************************************
+ *SHA20_CTRL - SHA2 Control for Module 0
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_CTRL :: reserved0 [31:11] */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_reserved0_MASK             0xfffff800
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_reserved0_SHIFT            11
+
+/* XPT_SECURITY_NS :: SHA20_CTRL :: PB_BAND [10:10] */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_MASK               0x00000400
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_SHIFT              10
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_PB_BAND_DEFAULT            0x00000000
+
+/* XPT_SECURITY_NS :: SHA20_CTRL :: BAND_NUM [09:03] */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_MASK              0x000003f8
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_SHIFT             3
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_BAND_NUM_DEFAULT           0x00000000
+
+/* XPT_SECURITY_NS :: SHA20_CTRL :: SHA2_SEL [02:01] */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_MASK              0x00000006
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHIFT             1
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_DEFAULT           0x00000000
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA1              0
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA224            1
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_SEL_SHA256            2
+
+/* XPT_SECURITY_NS :: SHA20_CTRL :: SHA2_EN [00:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_MASK               0x00000001
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_SHIFT              0
+#define BCHP_XPT_SECURITY_NS_SHA20_CTRL_SHA2_EN_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SHA20_0 - SHA20[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_0 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_0_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_0_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_1 - SHA20[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_1 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_1_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_1_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_2 - SHA20[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_2 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_2_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_2_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_3 - SHA20[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_3 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_3_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_3_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_4 - SHA20[159:128]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_4 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_4_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_4_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_5 - SHA20[191:160]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_5 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_5_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_5_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_6 - SHA20[223:192]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_6 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_6_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_6_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA20_7 - SHA20[255:224]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA20_7 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA20_7_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA20_7_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_SEMAPHORE - semaphore for SHA21
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_reserved0_MASK        0xffffff00
+#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_reserved0_SHIFT       8
+
+/* XPT_SECURITY_NS :: SHA21_SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_semaphore_ctrl_MASK   0x000000ff
+#define BCHP_XPT_SECURITY_NS_SHA21_SEMAPHORE_semaphore_ctrl_SHIFT  0
+
+/***************************************************************************
+ *SHA21_CTRL - SHA2 Control for Module 1
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_CTRL :: reserved0 [31:11] */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_reserved0_MASK             0xfffff800
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_reserved0_SHIFT            11
+
+/* XPT_SECURITY_NS :: SHA21_CTRL :: PB_BAND [10:10] */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_MASK               0x00000400
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_SHIFT              10
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_PB_BAND_DEFAULT            0x00000000
+
+/* XPT_SECURITY_NS :: SHA21_CTRL :: BAND_NUM [09:03] */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_MASK              0x000003f8
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_SHIFT             3
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_BAND_NUM_DEFAULT           0x00000000
+
+/* XPT_SECURITY_NS :: SHA21_CTRL :: SHA2_SEL [02:01] */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_MASK              0x00000006
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHIFT             1
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_DEFAULT           0x00000000
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA1              0
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA224            1
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_SEL_SHA256            2
+
+/* XPT_SECURITY_NS :: SHA21_CTRL :: SHA2_EN [00:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_MASK               0x00000001
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_SHIFT              0
+#define BCHP_XPT_SECURITY_NS_SHA21_CTRL_SHA2_EN_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SHA21_0 - SHA21[31:0]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_0 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_0_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_0_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_1 - SHA21[63:32]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_1 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_1_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_1_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_2 - SHA21[95:64]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_2 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_2_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_2_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_3 - SHA21[127:96]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_3 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_3_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_3_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_4 - SHA21[159:128]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_4 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_4_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_4_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_5 - SHA21[191:160]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_5 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_5_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_5_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_6 - SHA21[223:192]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_6 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_6_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_6_SHA2_OUTPUT_SHIFT             0
+
+/***************************************************************************
+ *SHA21_7 - SHA21[255:224]
+ ***************************************************************************/
+/* XPT_SECURITY_NS :: SHA21_7 :: SHA2_OUTPUT [31:00] */
+#define BCHP_XPT_SECURITY_NS_SHA21_7_SHA2_OUTPUT_MASK              0xffffffff
+#define BCHP_XPT_SECURITY_NS_SHA21_7_SHA2_OUTPUT_SHIFT             0
+
+#endif /* #ifndef BCHP_XPT_SECURITY_NS_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7250b0/bchp_xpt_security_ns_intr2_0.h b/include/linux/brcmstb/7250b0/bchp_xpt_security_ns_intr2_0.h
new file mode 100644
index 000000000000..d688eb984af6
--- /dev/null
+++ b/include/linux/brcmstb/7250b0/bchp_xpt_security_ns_intr2_0.h
@@ -0,0 +1,866 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Tue Mar 25 03:12:55 2014
+ *                 Full Compile MD5 Checksum 4593e257971177815cc4a01913c4bcb6
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              eacd1ac88c53d22793d18644f3aae7d3
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_SECURITY_NS_INTR2_0_H__
+#define BCHP_XPT_SECURITY_NS_INTR2_0_H__
+
+/***************************************************************************
+ *XPT_SECURITY_NS_INTR2_0 - XPT_SECURITY_NS_INTR2_0 Registers
+ ***************************************************************************/
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS  0x00380080 /* CPU interrupt Status Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET     0x00380084 /* CPU interrupt Set Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR   0x00380088 /* CPU interrupt Clear Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS 0x0038008c /* CPU interrupt Mask Status Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET 0x00380090 /* CPU interrupt Mask Set Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR 0x00380094 /* CPU interrupt Mask Clear Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS  0x00380098 /* PCI interrupt Status Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET     0x0038009c /* PCI interrupt Set Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR   0x003800a0 /* PCI interrupt Clear Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS 0x003800a4 /* PCI interrupt Mask Status Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET 0x003800a8 /* PCI interrupt Mask Set Register */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR 0x003800ac /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_reserved0_SHIFT    12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_MASK   0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_SHIFT  10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_MASK   0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_SHIFT  8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_MASK    0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_SHIFT   6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_MASK    0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_SHIFT   4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_MASK    0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_SHIFT   2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_STATUS :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_MASK    0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_SHIFT   0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_STATUS_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_reserved0_MASK        0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_reserved0_SHIFT       12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_MASK      0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_SHIFT     10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA21_READY_DEFAULT   0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_MASK      0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_SHIFT     8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_SHA20_READY_DEFAULT   0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_MASK       0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_SHIFT      6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC3_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_MASK       0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_SHIFT      4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC2_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_MASK       0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_SHIFT      2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC1_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_SET :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_MASK       0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_SHIFT      0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_SET_MAC0_READY_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_reserved0_MASK      0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_reserved0_SHIFT     12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_MASK    0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_SHIFT   10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_MASK    0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_SHIFT   8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_MASK     0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_SHIFT    6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC3_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_MASK     0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_SHIFT    4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC2_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_MASK     0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_SHIFT    2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC1_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_CLEAR :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_MASK     0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_SHIFT    0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_CLEAR_MAC0_READY_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_reserved0_SHIFT 12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_MASK 0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_MASK 0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_MASK 0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_STATUS :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_MASK 0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_STATUS_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_reserved0_MASK   0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_reserved0_SHIFT  12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_MASK  0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_MASK  0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_MASK  0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_SET :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_MASK  0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_SET_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_reserved0_MASK 0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_reserved0_SHIFT 12
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_MASK 0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_MASK 0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_MASK 0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: CPU_MASK_CLEAR :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_MASK 0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_CPU_MASK_CLEAR_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_reserved0_SHIFT    12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_MASK   0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_SHIFT  10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_MASK   0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_SHIFT  8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_MASK    0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_SHIFT   6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_MASK    0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_SHIFT   4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_MASK    0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_SHIFT   2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_STATUS :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_MASK    0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_SHIFT   0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_STATUS_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_reserved0_MASK        0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_reserved0_SHIFT       12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_MASK      0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_SHIFT     10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA21_READY_DEFAULT   0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_MASK      0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_SHIFT     8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_SHA20_READY_DEFAULT   0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_MASK       0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_SHIFT      6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC3_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_MASK       0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_SHIFT      4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC2_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_MASK       0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_SHIFT      2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC1_READY_DEFAULT    0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_SET :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_MASK       0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_SHIFT      0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_SET_MAC0_READY_DEFAULT    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_reserved0_MASK      0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_reserved0_SHIFT     12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_MASK    0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_SHIFT   10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_MASK    0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_SHIFT   8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_MASK     0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_SHIFT    6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC3_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_MASK     0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_SHIFT    4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC2_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_MASK     0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_SHIFT    2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC1_READY_DEFAULT  0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_CLEAR :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_MASK     0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_SHIFT    0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_CLEAR_MAC0_READY_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_reserved0_SHIFT 12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_MASK 0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_MASK 0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_MASK 0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_STATUS :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_MASK 0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_STATUS_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_reserved0_MASK   0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_reserved0_SHIFT  12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_MASK  0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_MASK  0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_MASK  0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_SET :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_MASK  0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_SET_MAC0_READY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: reserved0 [31:12] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_reserved0_MASK 0xfffff000
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_reserved0_SHIFT 12
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA21_SEMAPHORE_FREED [11:11] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_MASK 0x00000800
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_SHIFT 11
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA21_READY [10:10] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_MASK 0x00000400
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_SHIFT 10
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA21_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA20_SEMAPHORE_FREED [09:09] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_MASK 0x00000200
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_SHIFT 9
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: SHA20_READY [08:08] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_MASK 0x00000100
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_SHIFT 8
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_SHA20_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC3_SEMAPHORE_FREED [07:07] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_MASK 0x00000080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_SHIFT 7
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC3_READY [06:06] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_MASK 0x00000040
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_SHIFT 6
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC3_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC2_SEMAPHORE_FREED [05:05] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_MASK 0x00000020
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_SHIFT 5
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC2_READY [04:04] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_MASK 0x00000010
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_SHIFT 4
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC2_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC1_SEMAPHORE_FREED [03:03] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_MASK 0x00000008
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_SHIFT 3
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC1_READY [02:02] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_MASK 0x00000004
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_SHIFT 2
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC1_READY_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC0_SEMAPHORE_FREED [01:01] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_MASK 0x00000002
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_SHIFT 1
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_SEMAPHORE_FREED_DEFAULT 0x00000000
+
+/* XPT_SECURITY_NS_INTR2_0 :: PCI_MASK_CLEAR :: MAC0_READY [00:00] */
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_MASK 0x00000001
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_SHIFT 0
+#define BCHP_XPT_SECURITY_NS_INTR2_0_PCI_MASK_CLEAR_MAC0_READY_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_XPT_SECURITY_NS_INTR2_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..148a7011897d
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_ctrl.h
@@ -0,0 +1,1606 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:13:45 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:29p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00408090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xfffffe00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             9
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [08:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000100
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 8
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      12
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 1
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 1
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..08b938550477
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,545 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:55:25 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:29p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_14 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SDS0_DSEC_VCTL 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_SDS0_IF_AGC   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_AIO_EXTMCLK0  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_14_PM_AON_GPIO_14 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_13 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SDS0_DSEC_SELVTOP 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_I2S_BIDIR_CLK_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_I2S_BIDIR_CLK_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_SDS0_RF_AGC   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_TP_OUT_26     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_13_PM_AON_GPIO_13 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_12 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_SDS0_DSEC_TXEN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_I2S_BIDIR_SYNC_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_I2S_BIDIR_SYNC_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_TP_OUT_25     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_12_PM_AON_GPIO_12 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_11 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_SDS0_DSEC_TXOUT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_I2S_BIDIR_DATA_IN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_I2S_BIDIR_DATA_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_TP_OUT_24     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_11_PM_AON_GPIO_11 5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_KD_3      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQB_5    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_UART_RTSCB    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_PM_LED_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_OUT_03     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_02 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_AON_GPIO_02   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_LED_KD_2      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_EXT_IRQB_4    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_UART_CTSCB    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_SC0_RST_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_TP_OUT_02     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_02_PM_AON_GPIO_02 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_LED_KD_1      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_EXT_IRQB_3    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_UART_TXDC     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SC0_CLK_OUT_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PM_AON_GPIO_01 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_LED_KD_0      1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_EXT_IRQB_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_UART_RXDC     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SC0_IO_ALT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_ALT_TP_IN_00  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_PM_AON_GPIO_00 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_IR_IN0        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UHF_LNA_PWRDN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_ALT_TP_OUT_08 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_EXT_IRQB_10   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_IR_INT        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_RMX_PAUSE1    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC0_VPP_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_OUT_31     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_EXT_IRQB_9    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LS_3      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_RMX_VALID1    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC0_IO_AUX2_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_OUT_30     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_EXT_IRQB_8    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LS_2      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_RMX_SYNC1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC0_IO_AUX1_ALT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_OUT_29     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_05 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_EXT_IRQB_7    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_LED_LS_1      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_RMX_DATA1     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_SC0_VCC_ALT   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_TP_OUT_28     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_05_PM_AON_GPIO_05 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_04 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_EXT_IRQB_6    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_LED_LS_0      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_RMX_CLK1      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_SC0_PRES_ALT  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_TP_OUT_27     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_04_PM_AON_GPIO_04 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_16 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_AON_PM_LED_OUT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_16_PM_AON_GPIO_16 2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_15 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_EXT_IRQB_16   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_P1_INTR       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_AIO_EXTMCLK1  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_15_PM_AON_GPIO_15 4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_miso [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_MASK       0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_SHIFT      28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_AON_SPI_M_MISO 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_miso_ALT_TP_OUT_04 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_mosi [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_MASK       0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_SHIFT      24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_AON_SPI_M_MOSI 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_mosi_ALT_TP_OUT_03 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_spi_m_sck [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_MASK        0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_SHIFT       20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_DEFAULT     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_AON_SPI_M_SCK 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_spi_m_sck_ALT_TP_OUT_02 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_01_BSC_M2_SDA   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M2_SCL   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_03 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_03_AON_BSC_M0_SDA 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_02 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_02_AON_BSC_M0_SCL 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_10 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_IR_IN1        1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_UHF_LNA_PWRDN 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_10_PM_AON_GPIO_10 3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xffff0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           16
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_18 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_18_AON_IRQB1     1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_17 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_17_AON_IRQB0     1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_spi_m_ss1b [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_MASK       0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_SHIFT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_AON_SPI_M_SS1B 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss1b_ALT_TP_OUT_06 1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_spi_m_ss0b [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_MASK       0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_SHIFT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_AON_SPI_M_SS0B 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_spi_m_ss0b_ALT_TP_OUT_05 1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_16_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_15_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_14_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_13_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_12_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_11_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_02_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_02_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3ffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xffffffc0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       6
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff8
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       3
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_10 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_10_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_14 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_14_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..1aa1c4f5398e
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1407 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:15 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 12:42p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffe00000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  21
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00100000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       20
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00080000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   19
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00040000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          18
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00020000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       17
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       16
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       15
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        13
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffe00000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     21
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00100000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          20
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00080000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      19
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00040000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             18
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00020000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          17
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          16
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          15
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       14
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           13
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffe00000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   21
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00100000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        20
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00080000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    19
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00040000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           18
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00020000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        17
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        16
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     14
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         13
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             21
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  20
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              19
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     18
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  17
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                21
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     20
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 19
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        18
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     17
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffe00000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              21
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   20
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               19
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      18
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   17
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffe00000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  21
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00100000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       20
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00080000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   19
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00040000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          18
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00020000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       17
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       16
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       15
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        13
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffe00000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     21
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00100000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          20
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00080000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      19
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00040000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             18
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00020000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          17
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          16
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          15
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       14
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           13
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffe00000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   21
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00100000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        20
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00080000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    19
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00040000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           18
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00020000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        17
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        16
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     14
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         13
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             21
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  20
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              19
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     18
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  17
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                21
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     20
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 19
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        18
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     17
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffe00000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              21
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   20
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               19
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      18
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   17
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_bspi.h b/include/linux/brcmstb/7344b0/bchp_bspi.h
new file mode 100644
index 000000000000..8ce791854017
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:35:16 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:01p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00003000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00003004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00003008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0000300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00003010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00003014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00003018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0000301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00003020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00003024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00003028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0000302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00003030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00003034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00003038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0000303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00003040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00003044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00003048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0000304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_bspi_raf.h b/include/linux/brcmstb/7344b0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..2071da666d94
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:47:07 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:01p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00003100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00003104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00003108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0000310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00003110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00003114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00003118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0000311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00003120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_clkgen.h b/include/linux/brcmstb/7344b0/bchp_clkgen.h
new file mode 100644
index 000000000000..9d9fe32418f6
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_clkgen.h
@@ -0,0 +1,5694 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:02 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00040000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00040004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00040008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0004000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00040010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00040014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00040018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0004001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00040020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00040024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00040028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0004002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00040030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00040034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00040038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0004003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00040040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00040044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00040048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0004004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00040050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00040054 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00040058 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x0004005c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00040060 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00040064 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00040068 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x0004006c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00040070 /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00040074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00040078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x0004007c /* Test Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00040080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x00040084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00040088 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x0004008c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00040090 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00040094 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x00040098 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x0004009c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x000400a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x000400a4 /* Resets */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x000400a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x000400ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x000400b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x000400b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x000400b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x000400bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x000400c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x000400c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x000400c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x000400cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x000400d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x000400d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x000400d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x000400dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x000400e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x000400e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x000400e8 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x000400ec /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x000400f0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x000400f4 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x000400f8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x000400fc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x00040100 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x00040104 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x00040108 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x0004010c /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x00040110 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x00040114 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00040118 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x0004011c /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00040120 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00040124 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00040128 /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x0004012c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00040130 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00040134 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00040138 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x0004013c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00040140 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00040144 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x00040148 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x0004014c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00040150 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00040154 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00040158 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x0004015c /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00040160 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00040164 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00040168 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0004016c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00040170 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00040174 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00040178 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x0004017c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00040180 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00040184 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00040188 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x0004018c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00040190 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x00040194 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00040198 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0004019c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x000401a0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x000401a4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x000401a8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x000401ac /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x000401b0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x000401b4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x000401b8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x000401bc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x000401c0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x000401c4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x000401c8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x000401cc /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x000401d0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x000401d4 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x000401d8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x000401dc /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x000401e0 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x000401e4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x000401e8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x000401ec /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x000401f0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x000401f4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x000401f8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x000401fc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00040200 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00040204 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00040208 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x0004020c /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00040210 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00040214 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00040218 /* Test Status */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x0004021c /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040220 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00040224 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x00040228 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE     0x0004022c /* Clkgen inst clock enable */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00040230 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00040234 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x00040238 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x0004023c /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00040240 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00040244 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x00040248 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x0004024c /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00040250 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x00040254 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00040258 /* Disable DUAL_GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x0004025c /* Dual genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00040260 /* Dual genet top rgmii inst clock select */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00040264 /* Dual genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00040268 /* Dual genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x0004026c /* Dual genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00040270 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x00040274 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00040278 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x0004027c /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x00040280 /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE    0x00040284 /* Fsk top inst clock enable */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040288 /* Fsk top inst memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY 0x0004028c /* Fsk top inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE  0x00040290 /* Disable GRAPHICS_INST's clocks */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00040294 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x00040298 /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x0004029c /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x000402a0 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x000402a4 /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x000402a8 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x000402ac /* Memsys 32 inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x000402b0 /* Memsys 32 inst memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x000402b4 /* Memsys 32 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x000402b8 /* Memsys 32 inst power switch memory */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS        0x000402bc /* Memsys 32 inst status */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x000402c0 /* Moca top inst clock enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x000402c4 /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x000402c8 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x000402cc /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x000402d0 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION      0x000402d4 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x000402d8 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x000402dc /* Select observation clk */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x000402e0 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x000402e4 /* Select observation clk */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x000402e8 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x000402ec /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x000402f0 /* PLL_AVD Reset Status */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x000402f4 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x000402f8 /* PLL_MIPS Glitchless Clock Switching */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x000402fc /* PLL_MIPS Glitchless Switching */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x00040300 /* PLL_MIPS Reset Status */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL      0x00040304 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00040308 /* PLL_MOCA Reset Status */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x0004030c /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00040310 /* PLL_RAAGA Reset Status */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x00040314 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00040318 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x0004031c /* Disable */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL      0x00040320 /* PLL RDB Macro Disable */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00040324 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x00040328 /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x0004032c /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00040330 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00040334 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00040338 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0004033c /* Power management LDO PLL state machine */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00040340 /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040344 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00040348 /* Raaga dsp top inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x0004034c /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x00040350 /* Sds0 afec top inst clock enable */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040354 /* Sds0 afec top inst memory standby enable */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00040358 /* Sds0 afec top inst observe clock */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x0004035c /* Sds0 afec top inst power switch memory */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE  0x00040360 /* Disable SDS0_TOP_INST's clocks */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE   0x00040364 /* Sds0 top inst clock enable */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK  0x00040368 /* Sds0 top inst observe clock */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0004036c /* Sectop inst clock enable m2mdma */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00040370 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00040374 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00040378 /* Spares */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0004037c /* Svd0 top inst clock enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040380 /* Svd0 top inst memory standby enable */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00040384 /* Svd0 top inst power switch memory */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x00040388 /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x0004038c /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE   0x00040390 /* Sys ctrl inst clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00040394 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x00040398 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_TESTPORT                     0x0004039c /* Special Testport Controls */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x000403a0 /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x000403a4 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x000403a8 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x000403ac /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x000403b0 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x000403b4 /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x000403b8 /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x000403bc /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x000403c0 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x000403c4 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x000403c8 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x000403cc /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x000403d0 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x000403d4 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x000403d8 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x000403dc /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x000403e0 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x000403e4 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x000403e8 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x000403ec /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x000403f0 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x000403f4 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x000403f8 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x000403fc /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x00040400 /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00040404 /* Zcpu top inst clock enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x00040408 /* Zcpu top inst observe clock */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               142
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 3
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 100
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              150
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 75
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00001c00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x60000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x07000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00600000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             21
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x000c0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           16
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x00008000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           15
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00004000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  96
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 81
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 48
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  1
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              72
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 45
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Dual genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff8000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 15
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT - Dual genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Dual genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_VEC_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_INST_CLOCK_ENABLE - Fsk top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      2
+
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FSK_TOP_INST_MEMORY_STANDBY_ENABLE - Fsk top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_INST_POWER_SWITCH_MEMORY - Fsk top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_V3D_CORE_CLOCK [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffff80
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     7
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         4
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 1
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:05] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffe0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            5
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: STRAP_OVERRIDE_HIF_SPI_CLOCK [04:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: HIF_SPI_CLOCK [01:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_MASK         0x00000003
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_SHIFT        0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_DEFAULT      0
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: MEMSYS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_STATUS - Memsys 32 inst status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_SHIFT          1
+
+/* CLKGEN :: MEMSYS_32_INST_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_ACC_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_MASK         0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_SHIFT        9
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKACC_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:10] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffc00
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 10
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [09:07] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x00000380
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   7
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKACC_CLOCK [06:04] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_MASK    0x00000070
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_SHIFT   4
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [03:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x0000000e
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 31
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4
+
+/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK         0xffffffe0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT        5
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [04:04] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [03:00] */
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK           0x0000000f
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
+#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_STRAP_OVERRIDE - Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLSYS0_DISABLE [01:01] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_SHIFT 1
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT        3
+
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO [02:02] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: OPTIONS [01:00] */
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000003
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
+#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         3
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTOP0 [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FSK [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_DEFAULT 0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             3
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_ENABLE - Sds0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS_TOP0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_TOP_INST_OBSERVE_CLOCK - Sds0 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xfffff000
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    12
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK [11:11] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK [09:06] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable m2mdma
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xffffff00
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           8
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UHFR_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_ENABLE - Sys ctrl inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_common.h b/include/linux/brcmstb/7344b0/bchp_common.h
new file mode 100644
index 000000000000..f03d4a479ea5
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_common.h
@@ -0,0 +1,2220 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jul  8 19:13:13 2011
+ *                 MD5 Checksum         6d43009b3dfb16bef651d8873360bc15
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/3   7/11/11 12:10p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7344_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000800 /* EBI is first */
+#define BCHP_REGISTER_END                                  0x01410348 /* FTM_SW_SPARE is last */
+#define BCHP_REGISTER_SIZE                                 0x00503ed2 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_EBI_REG_START                                 0x00000800
+#define BCHP_EBI_REG_END                                   0x00000bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00001000
+#define BCHP_HIF_INTR2_REG_END                             0x0000102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00001100
+#define BCHP_IPI0_INTR2_REG_END                            0x0000112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00001200
+#define BCHP_IPI1_INTR2_REG_END                            0x0000122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00001400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0000142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00001600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0000162c
+#define BCHP_HIF_RGR_REG_START                             0x00001800
+#define BCHP_HIF_RGR_REG_END                               0x00001810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00001d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00001d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00002400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x00002418
+#define BCHP_NAND_REG_START                                0x00002800
+#define BCHP_NAND_REG_END                                  0x00002bfc
+#define BCHP_BSPI_REG_START                                0x00003000
+#define BCHP_BSPI_REG_END                                  0x0000304c
+#define BCHP_BSPI_RAF_REG_START                            0x00003100
+#define BCHP_BSPI_RAF_REG_END                              0x00003120
+#define BCHP_HIF_MSPI_REG_START                            0x00003200
+#define BCHP_HIF_MSPI_REG_END                              0x00003384
+#define BCHP_SDIO_0_HOST_REG_START                         0x00003500
+#define BCHP_SDIO_0_HOST_REG_END                           0x000035fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00003600
+#define BCHP_SDIO_0_CFG_REG_END                            0x000036fc
+#define BCHP_MICH_REG_START                                0x00020000
+#define BCHP_MICH_REG_END                                  0x00020000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00020100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00020100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00020200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00020200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00020300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00020300
+#define BCHP_NAND_SECURE_REG_START                         0x00020400
+#define BCHP_NAND_SECURE_REG_END                           0x00020400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00020800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00020800
+#define BCHP_CLKGEN_REG_START                              0x00040000
+#define BCHP_CLKGEN_REG_END                                0x00040408
+#define BCHP_VCXO_RM_REG_START                             0x00042800
+#define BCHP_VCXO_RM_REG_END                               0x0004282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00043000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00043074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00043100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0004311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00043200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00043218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00043300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x000433dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00043400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0004348c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00043500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x000435e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00043600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x000436e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00044000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0004402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00044800
+#define BCHP_CLKGEN_GR_REG_END                             0x0004480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00080000
+#define BCHP_GENET_0_SYS_REG_END                           0x0008000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00080040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0008004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00080080
+#define BCHP_GENET_0_EXT_REG_END                           0x00080098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00080200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0008022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00080240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0008026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00080300
+#define BCHP_GENET_0_RBUF_REG_END                          0x000803ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00080600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00080628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00080800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00080ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00081000
+#define BCHP_GENET_0_HFB_REG_END                           0x00082010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00083000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00083cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00084000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00084c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00090000
+#define BCHP_GENET_1_SYS_REG_END                           0x0009000c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00090040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0009004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00090080
+#define BCHP_GENET_1_EXT_REG_END                           0x00090098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00090200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0009022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00090240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0009026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00090300
+#define BCHP_GENET_1_RBUF_REG_END                          0x000903ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00090600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00090628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00090800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00090ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00091000
+#define BCHP_GENET_1_HFB_REG_END                           0x00092010
+#define BCHP_GENET_1_RDMA_REG_START                        0x00093000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00093cb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00094000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00094c88
+#define BCHP_XPT_SECURITY_REG_START                        0x000a0000
+#define BCHP_XPT_SECURITY_REG_END                          0x000afffc
+#define BCHP_MMSCRAM_REG_START                             0x000b0000
+#define BCHP_MMSCRAM_REG_END                               0x000b1ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x000b2000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x000b200c
+#define BCHP_SECTOP_GRB_REG_START                          0x000b4000
+#define BCHP_SECTOP_GRB_REG_END                            0x000b400c
+#define BCHP_JTAG_OTP_REG_START                            0x000b4100
+#define BCHP_JTAG_OTP_REG_END                              0x000b4138
+#define BCHP_MEM_DMA_0_REG_START                           0x000b4200
+#define BCHP_MEM_DMA_0_REG_END                             0x000b4224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x000b4300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x000b4310
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x000c0000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x000c00b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x000c0700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x000c0704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x000c0800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x000c087c
+#define BCHP_S_MEMC_0_REG_START                            0x000e0000
+#define BCHP_S_MEMC_0_REG_END                              0x000e0220
+#define BCHP_MFD_0_REG_START                               0x00100000
+#define BCHP_MFD_0_REG_END                                 0x00100264
+#define BCHP_MFD_1_REG_START                               0x00100400
+#define BCHP_MFD_1_REG_END                                 0x001005fc
+#define BCHP_VFD_0_REG_START                               0x00101000
+#define BCHP_VFD_0_REG_END                                 0x001011fc
+#define BCHP_VFD_1_REG_START                               0x00101200
+#define BCHP_VFD_1_REG_END                                 0x001013fc
+#define BCHP_VFD_2_REG_START                               0x00101400
+#define BCHP_VFD_2_REG_END                                 0x001015fc
+#define BCHP_VFD_3_REG_START                               0x00101600
+#define BCHP_VFD_3_REG_END                                 0x001017fc
+#define BCHP_RDC_REG_START                                 0x00102000
+#define BCHP_RDC_REG_END                                   0x001029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00103000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0010302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00103100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0010312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00103300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0010332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00103400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0010342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00103500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0010352c
+#define BCHP_FMISC_REG_START                               0x00104000
+#define BCHP_FMISC_REG_END                                 0x00104020
+#define BCHP_SCL_0_REG_START                               0x00120000
+#define BCHP_SCL_0_REG_END                                 0x001203fc
+#define BCHP_SCL_1_REG_START                               0x00120400
+#define BCHP_SCL_1_REG_END                                 0x001207fc
+#define BCHP_SCL_2_REG_START                               0x00120800
+#define BCHP_SCL_2_REG_END                                 0x00120bfc
+#define BCHP_SCL_3_REG_START                               0x00120c00
+#define BCHP_SCL_3_REG_END                                 0x00120ffc
+#define BCHP_VNET_F_REG_START                              0x00122000
+#define BCHP_VNET_F_REG_END                                0x001220ac
+#define BCHP_VNET_B_REG_START                              0x00122200
+#define BCHP_VNET_B_REG_END                                0x001222bc
+#define BCHP_MMISC_REG_START                               0x00122800
+#define BCHP_MMISC_REG_END                                 0x00122820
+#define BCHP_LBOX_0_REG_START                              0x00125000
+#define BCHP_LBOX_0_REG_END                                0x00125070
+#define BCHP_LBOX_1_REG_START                              0x00125200
+#define BCHP_LBOX_1_REG_END                                0x00125270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00126000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0012602c
+#define BCHP_DNR_0_REG_START                               0x00127000
+#define BCHP_DNR_0_REG_END                                 0x001270a4
+#define BCHP_CAP_0_REG_START                               0x00140000
+#define BCHP_CAP_0_REG_END                                 0x0014007c
+#define BCHP_CAP_1_REG_START                               0x00140200
+#define BCHP_CAP_1_REG_END                                 0x0014027c
+#define BCHP_CAP_2_REG_START                               0x00140400
+#define BCHP_CAP_2_REG_END                                 0x0014047c
+#define BCHP_CAP_3_REG_START                               0x00140600
+#define BCHP_CAP_3_REG_END                                 0x0014067c
+#define BCHP_GFD_0_REG_START                               0x00141000
+#define BCHP_GFD_0_REG_END                                 0x00141228
+#define BCHP_GFD_1_REG_START                               0x00141400
+#define BCHP_GFD_1_REG_END                                 0x00141554
+#define BCHP_CMP_0_REG_START                               0x00142000
+#define BCHP_CMP_0_REG_END                                 0x001424b4
+#define BCHP_CMP_1_REG_START                               0x00142800
+#define BCHP_CMP_1_REG_END                                 0x00142cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00143000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x001430a4
+#define BCHP_MASK_0_REG_START                              0x00143400
+#define BCHP_MASK_0_REG_END                                0x00143420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00144000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00145484
+#define BCHP_BVNB_INTR2_REG_START                          0x00146000
+#define BCHP_BVNB_INTR2_REG_END                            0x0014602c
+#define BCHP_BMISC_REG_START                               0x00146400
+#define BCHP_BMISC_REG_END                                 0x0014641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00160000
+#define BCHP_MVP_TOP_0_REG_END                             0x0016002c
+#define BCHP_SIOB_0_REG_START                              0x00160200
+#define BCHP_SIOB_0_REG_END                                0x001602fc
+#define BCHP_HSCL_0_REG_START                              0x00160400
+#define BCHP_HSCL_0_REG_END                                0x001607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00162000
+#define BCHP_MDI_TOP_0_REG_END                             0x00162044
+#define BCHP_MDI_PPB_0_REG_START                           0x00162800
+#define BCHP_MDI_PPB_0_REG_END                             0x00162bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00162c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00162ffc
+#define BCHP_MISC_REG_START                                0x00180000
+#define BCHP_MISC_REG_END                                  0x0018009c
+#define BCHP_IT_0_REG_START                                0x00181000
+#define BCHP_IT_0_REG_END                                  0x001817fc
+#define BCHP_IT_1_REG_START                                0x00182000
+#define BCHP_IT_1_REG_END                                  0x001827fc
+#define BCHP_VF_0_REG_START                                0x00183000
+#define BCHP_VF_0_REG_END                                  0x00183134
+#define BCHP_VF_1_REG_START                                0x00183200
+#define BCHP_VF_1_REG_END                                  0x00183334
+#define BCHP_SECAM_0_REG_START                             0x00183400
+#define BCHP_SECAM_0_REG_END                               0x00183414
+#define BCHP_SM_0_REG_START                                0x00183480
+#define BCHP_SM_0_REG_END                                  0x001834ac
+#define BCHP_SDSRC_0_REG_START                             0x00183500
+#define BCHP_SDSRC_0_REG_END                               0x0018350c
+#define BCHP_HDSRC_0_REG_START                             0x00183520
+#define BCHP_HDSRC_0_REG_END                               0x0018353c
+#define BCHP_CSC_0_REG_START                               0x00183580
+#define BCHP_CSC_0_REG_END                                 0x001835b0
+#define BCHP_CSC_1_REG_START                               0x00183600
+#define BCHP_CSC_1_REG_END                                 0x00183630
+#define BCHP_RM_0_REG_START                                0x00183680
+#define BCHP_RM_0_REG_END                                  0x001836a4
+#define BCHP_RM_1_REG_START                                0x001836c0
+#define BCHP_RM_1_REG_END                                  0x001836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00183700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00183744
+#define BCHP_GRPD_0_REG_START                              0x00183800
+#define BCHP_GRPD_0_REG_END                                0x001838ec
+#define BCHP_DTRAM_0_REG_START                             0x00184000
+#define BCHP_DTRAM_0_REG_END                               0x0018447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00184800
+#define BCHP_DVI_DTG_0_REG_END                             0x00184954
+#define BCHP_DVI_CSC_0_REG_START                           0x00184a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00184a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00184b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00184b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00184c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00184c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x00185000
+#define BCHP_ITU656_DTG_0_REG_END                          0x00185154
+#define BCHP_ITU656_CSC_0_REG_START                        0x00185200
+#define BCHP_ITU656_CSC_0_REG_END                          0x00185230
+#define BCHP_ITU656_DVF_0_REG_START                        0x00185300
+#define BCHP_ITU656_DVF_0_REG_END                          0x00185314
+#define BCHP_ITU656_0_REG_START                            0x00185400
+#define BCHP_ITU656_0_REG_END                              0x00185420
+#define BCHP_VEC_CFG_REG_START                             0x00185600
+#define BCHP_VEC_CFG_REG_END                               0x00185708
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00185a00
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x00185a2c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00185b00
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00185b18
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00185c00
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00185c08
+#define BCHP_DVP_TVG_0_REG_START                           0x00185d00
+#define BCHP_DVP_TVG_0_REG_END                             0x00185d88
+#define BCHP_VBI_ENC_REG_START                             0x00186000
+#define BCHP_VBI_ENC_REG_END                               0x00186074
+#define BCHP_CCE_0_REG_START                               0x00186400
+#define BCHP_CCE_0_REG_END                                 0x00186458
+#define BCHP_CCE_1_REG_START                               0x00186500
+#define BCHP_CCE_1_REG_END                                 0x00186558
+#define BCHP_WSE_0_REG_START                               0x00186600
+#define BCHP_WSE_0_REG_END                                 0x00186614
+#define BCHP_WSE_1_REG_START                               0x00186700
+#define BCHP_WSE_1_REG_END                                 0x00186714
+#define BCHP_CGMSAE_0_REG_START                            0x00186800
+#define BCHP_CGMSAE_0_REG_END                              0x00186858
+#define BCHP_CGMSAE_1_REG_START                            0x00186900
+#define BCHP_CGMSAE_1_REG_END                              0x00186958
+#define BCHP_TTE_0_REG_START                               0x00186a00
+#define BCHP_TTE_0_REG_END                                 0x00186a28
+#define BCHP_TTE_1_REG_START                               0x00186b00
+#define BCHP_TTE_1_REG_END                                 0x00186b28
+#define BCHP_GSE_0_REG_START                               0x00186c00
+#define BCHP_GSE_0_REG_END                                 0x00186c80
+#define BCHP_GSE_1_REG_START                               0x00186d00
+#define BCHP_GSE_1_REG_END                                 0x00186d80
+#define BCHP_AMOLE_0_REG_START                             0x00186e00
+#define BCHP_AMOLE_0_REG_END                               0x00186e8c
+#define BCHP_AMOLE_1_REG_START                             0x00186f00
+#define BCHP_AMOLE_1_REG_END                               0x00186f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00187000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00187054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00187100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0018710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00187200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00187228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00187300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00187380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00187400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0018748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00187500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00187524
+#define BCHP_DVP_HT_REG_START                              0x001a0000
+#define BCHP_DVP_HT_REG_END                                0x001a00d4
+#define BCHP_HDMI_REG_START                                0x001a0800
+#define BCHP_HDMI_REG_END                                  0x001a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x001a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x001a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x001a0b00
+#define BCHP_HDMI_RM_REG_END                               0x001a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x001a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x001a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x001a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x001a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x001a8000
+#define BCHP_BVN_RGR_REG_END                               0x001a8010
+#define BCHP_DATA_MEM_REG_START                            0x00200000
+#define BCHP_DATA_MEM_REG_END                              0x0023fffc
+#define BCHP_CNTL_MEM_REG_START                            0x00240000
+#define BCHP_CNTL_MEM_REG_END                              0x0025fffc
+#define BCHP_MOCA_DMA_Channel0_REG_START                   0x00280000
+#define BCHP_MOCA_DMA_Channel0_REG_END                     0x0028000c
+#define BCHP_MOCA_DMA_Channel1_REG_START                   0x00280010
+#define BCHP_MOCA_DMA_Channel1_REG_END                     0x0028001c
+#define BCHP_MOCA_DMA_Channel2_REG_START                   0x00280020
+#define BCHP_MOCA_DMA_Channel2_REG_END                     0x0028002c
+#define BCHP_MOCA_DMA_Channel3_REG_START                   0x00280030
+#define BCHP_MOCA_DMA_Channel3_REG_END                     0x0028003c
+#define BCHP_MOCA_DMA_Channel4_REG_START                   0x00280040
+#define BCHP_MOCA_DMA_Channel4_REG_END                     0x0028004c
+#define BCHP_MOCA_DMA_Channel5_REG_START                   0x00280050
+#define BCHP_MOCA_DMA_Channel5_REG_END                     0x0028005c
+#define BCHP_MOCA_DMA_Channel6_REG_START                   0x00280060
+#define BCHP_MOCA_DMA_Channel6_REG_END                     0x0028006c
+#define BCHP_MOCA_MAC_REG_START                            0x00280400
+#define BCHP_MOCA_MAC_REG_END                              0x00280480
+#define BCHP_MOCA_PHY_REG_START                            0x00288000
+#define BCHP_MOCA_PHY_REG_END                              0x0028a9fc
+#define BCHP_MOCA_TRX_REG_START                            0x0028c000
+#define BCHP_MOCA_TRX_REG_END                              0x0028c0d0
+#define BCHP_MOCA_GMII_REG_START                           0x00290000
+#define BCHP_MOCA_GMII_REG_END                             0x00290058
+#define BCHP_MOCA_DMA_Channel_rx_REG_START                 0x00290400
+#define BCHP_MOCA_DMA_Channel_rx_REG_END                   0x0029040c
+#define BCHP_MOCA_DMA_Channel_tx_REG_START                 0x00290410
+#define BCHP_MOCA_DMA_Channel_tx_REG_END                   0x0029041c
+#define BCHP_MOCA_ECL_REG_START                            0x00290800
+#define BCHP_MOCA_ECL_REG_END                              0x00290848
+#define BCHP_MOCA_PRI_REG_START                            0x00292000
+#define BCHP_MOCA_PRI_REG_END                              0x0029207c
+#define BCHP_MOCA_NID_REG_START                            0x00294000
+#define BCHP_MOCA_NID_REG_END                              0x002943fc
+#define BCHP_MOCA_TIMER_0_REG_START                        0x002a0000
+#define BCHP_MOCA_TIMER_0_REG_END                          0x002a0010
+#define BCHP_MOCA_TIMER_1_REG_START                        0x002a0020
+#define BCHP_MOCA_TIMER_1_REG_END                          0x002a0030
+#define BCHP_MOCA_TIMER_2_REG_START                        0x002a0040
+#define BCHP_MOCA_TIMER_2_REG_END                          0x002a0050
+#define BCHP_MOCA_GPIO_REG_START                           0x002a1000
+#define BCHP_MOCA_GPIO_REG_END                             0x002a1018
+#define BCHP_MOCA_EXTRAS_REG_START                         0x002a1400
+#define BCHP_MOCA_EXTRAS_REG_END                           0x002a1494
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x002a2000
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x002a200c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x002a2040
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x002a2064
+#define BCHP_MOCA_L2_REG_START                             0x002a2080
+#define BCHP_MOCA_L2_REG_END                               0x002a20ac
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x002a20c0
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x002a20cc
+#define BCHP_MOCA_HOSTMISC_MMP_REG_START                   0x002a2100
+#define BCHP_MOCA_HOSTMISC_MMP_REG_END                     0x002a212c
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_BUS_IF_REG_START                          0x00380000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00380088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00381000
+#define BCHP_XPT_XMEMIF_REG_END                            0x0038109c
+#define BCHP_XPT_PMU_REG_START                             0x00381800
+#define BCHP_XPT_PMU_REG_END                               0x00381808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00382000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00382fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00383000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00383020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00383100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00383120
+#define BCHP_XPT_FE_REG_START                              0x00384000
+#define BCHP_XPT_FE_REG_END                                0x00384ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00386000
+#define BCHP_XPT_DPCR0_REG_END                             0x00386074
+#define BCHP_XPT_DPCR1_REG_START                           0x00386080
+#define BCHP_XPT_DPCR1_REG_END                             0x003860f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00386100
+#define BCHP_XPT_DPCR2_REG_END                             0x00386174
+#define BCHP_XPT_DPCR3_REG_START                           0x00386180
+#define BCHP_XPT_DPCR3_REG_END                             0x003861f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00386400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00386404
+#define BCHP_XPT_PSUB_REG_START                            0x00386600
+#define BCHP_XPT_PSUB_REG_END                              0x003866c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00386800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00386f2c
+#define BCHP_XPT_PB0_REG_START                             0x00387000
+#define BCHP_XPT_PB0_REG_END                               0x00387060
+#define BCHP_XPT_PB1_REG_START                             0x00387080
+#define BCHP_XPT_PB1_REG_END                               0x003870e0
+#define BCHP_XPT_PB2_REG_START                             0x00387100
+#define BCHP_XPT_PB2_REG_END                               0x00387160
+#define BCHP_XPT_PB3_REG_START                             0x00387180
+#define BCHP_XPT_PB3_REG_END                               0x003871e0
+#define BCHP_XPT_MPOD_REG_START                            0x00388000
+#define BCHP_XPT_MPOD_REG_END                              0x00388020
+#define BCHP_XPT_RMX0_REG_START                            0x00388400
+#define BCHP_XPT_RMX0_REG_END                              0x00388408
+#define BCHP_XPT_RMX1_REG_START                            0x00388500
+#define BCHP_XPT_RMX1_REG_END                              0x00388508
+#define BCHP_XPT_XCBUFF_REG_START                          0x0038a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x0038bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00390000
+#define BCHP_XPT_RAVE_REG_END                              0x0039a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x0039b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x0039bffc
+#define BCHP_XPT_MSG_REG_START                             0x003a0000
+#define BCHP_XPT_MSG_REG_END                               0x003a4814
+#define BCHP_XPT_GR_REG_START                              0x003a5000
+#define BCHP_XPT_GR_REG_END                                0x003a500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x003a6000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x003a7050
+#define BCHP_XPT_XPU_REG_START                             0x003a8000
+#define BCHP_XPT_XPU_REG_END                               0x003ac7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x003b8000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x003b8000
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCD_REG_START                                0x00406300
+#define BCHP_BSCD_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_PWMB_REG_START                                0x004066c0
+#define BCHP_PWMB_REG_END                                  0x004066e4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040675c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_MCIF_REG_START                                0x00406e00
+#define BCHP_MCIF_REG_END                                  0x00406e20
+#define BCHP_MCIF_INTR2_REG_START                          0x00406e40
+#define BCHP_MCIF_INTR2_REG_END                            0x00406e6c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406e80
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406eac
+#define BCHP_TMON_REG_START                                0x00406f00
+#define BCHP_TMON_REG_END                                  0x00406f50
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCC_REG_START                                0x00408980
+#define BCHP_BSCC_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c3c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00800000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0080007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00800100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x008001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00800200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0080027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00800300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0080031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00800320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0080033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00800340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0080035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00800400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0080045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00800500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0080057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00800600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0080060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00800700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0080071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00800720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0080073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00800740
+#define BCHP_DECODE_MB_0_REG_END                           0x0080075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00800b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00800bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00800c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00800dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00800e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00800efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00800f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00800f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00800f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00800ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00801800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x008018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00801a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x008021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00802400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x008027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00803000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x008031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0080cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0080ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00840800
+#define BCHP_DECODE_SD_0_REG_END                           0x00840ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00841000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0084107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00844000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00844ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00845000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00845ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00846000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00847ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00848000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0084fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00851000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0085107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00851800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x008518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00851a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x008521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00854000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00854ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00855000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00855ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00856000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00857ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00858000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0085fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00860000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00860084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00862000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0086203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00870000
+#define BCHP_ILS_REGS_0_REG_END                            0x0087007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00870100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0087010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00870180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00870180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00870200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0087038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00880000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0088002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00880400
+#define BCHP_SVD_RGR_0_REG_END                             0x00880410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00900000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0090007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00900100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x009001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00900200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0090027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00900300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0090031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00900320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0090033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00900340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0090035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00900400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0090045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00900500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0090057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00900600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0090060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00900700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0090071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00900720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0090073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00900740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0090075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00900b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00900bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00900c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00900dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00900e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00900efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00900f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00900f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00900f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00900ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00901800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x009018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00901a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x009021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00902400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x009027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00903000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x009031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0090cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0090ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00940800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00940ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00941000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0094107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00944000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00944ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00945000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00945ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00946000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00947ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00948000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0094fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00951000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0095107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00951800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x009518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00951a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x009521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00954000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00954ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00955000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00955ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00956000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00957ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00958000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0095fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00960000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00960084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00962000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0096203c
+#define BCHP_MEMC_GEN_0_REG_START                          0x00a00000
+#define BCHP_MEMC_GEN_0_REG_END                            0x00a004f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x00a01000
+#define BCHP_MEMC_ARB_0_REG_END                            0x00a01244
+#define BCHP_MEMC_DDR_0_REG_START                          0x00a02000
+#define BCHP_MEMC_DDR_0_REG_END                            0x00a022fc
+#define BCHP_MEMC_L2_0_REG_START                           0x00a03000
+#define BCHP_MEMC_L2_0_REG_END                             0x00a0302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x00a03800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x00a0382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x00a04000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x00a04010
+#define BCHP_MEMC_MISC_0_REG_START                         0x00a05000
+#define BCHP_MEMC_MISC_0_REG_END                           0x00a05010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x00a06000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x00a060c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x00a06200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x00a063b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x00a06400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x00a065b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x00a08000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x00a08138
+#define BCHP_VICH_0_REG_START                              0x00b00000
+#define BCHP_VICH_0_REG_END                                0x00b0008b
+#define BCHP_SID_REG_START                                 0x00c00100
+#define BCHP_SID_REG_END                                   0x00c0019c
+#define BCHP_SID_RLE_REG_START                             0x00c00300
+#define BCHP_SID_RLE_REG_END                               0x00c0039c
+#define BCHP_SID_DQ_REG_START                              0x00c00400
+#define BCHP_SID_DQ_REG_END                                0x00c004bc
+#define BCHP_SID_STRM_REG_START                            0x00c00800
+#define BCHP_SID_STRM_REG_END                              0x00c0087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00c00c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00c00c40
+#define BCHP_SID_ARC_REG_START                             0x00c00f00
+#define BCHP_SID_ARC_REG_END                               0x00c00f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00c01800
+#define BCHP_SID_ARCDMA_REG_END                            0x00c01840
+#define BCHP_SID_DMARAM_REG_START                          0x00c01a00
+#define BCHP_SID_DMARAM_REG_END                            0x00c01bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00c02b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00c02b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00c02b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00c02b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00c03000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00c037fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00c03900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00c039fc
+#define BCHP_SID_SYMB_REG_START                            0x00c03a00
+#define BCHP_SID_SYMB_REG_END                              0x00c03a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00c03a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00c03a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00c08000
+#define BCHP_SID_BIGRAM_REG_END                            0x00c0fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00c11000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00c11010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00c15000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00c15014
+#define BCHP_M2MC_REG_START                                0x00c20000
+#define BCHP_M2MC_REG_END                                  0x00c207fc
+#define BCHP_V3D_CTL_REG_START                             0x00c21000
+#define BCHP_V3D_CTL_REG_END                               0x00c21040
+#define BCHP_V3D_CLE_REG_START                             0x00c21100
+#define BCHP_V3D_CLE_REG_END                               0x00c21138
+#define BCHP_V3D_PTB_REG_START                             0x00c21300
+#define BCHP_V3D_PTB_REG_END                               0x00c21310
+#define BCHP_V3D_QPS_REG_START                             0x00c21400
+#define BCHP_V3D_QPS_REG_END                               0x00c2143c
+#define BCHP_V3D_VPM_REG_START                             0x00c21500
+#define BCHP_V3D_VPM_REG_END                               0x00c21504
+#define BCHP_V3D_PCTR_REG_START                            0x00c21600
+#define BCHP_V3D_PCTR_REG_END                              0x00c216fc
+#define BCHP_V3D_GCA_REG_START                             0x00c21a00
+#define BCHP_V3D_GCA_REG_END                               0x00c21a54
+#define BCHP_V3D_DBG_REG_START                             0x00c21e00
+#define BCHP_V3D_DBG_REG_END                               0x00c21f20
+#define BCHP_GFX_L2_REG_START                              0x00c23000
+#define BCHP_GFX_L2_REG_END                                0x00c2302c
+#define BCHP_GFX_GR_REG_START                              0x00c24000
+#define BCHP_GFX_GR_REG_END                                0x00c2400c
+#define BCHP_SICH_REG_START                                0x00c50000
+#define BCHP_SICH_REG_END                                  0x00c5003c
+#define BCHP_UHFR_REG_START                                0x00d00000
+#define BCHP_UHFR_REG_END                                  0x00d000f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00d00200
+#define BCHP_UHFR_INTR2_REG_END                            0x00d0022c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00d00300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x00d0030c
+#define BCHP_SDS_CG_REG_START                              0x01100000
+#define BCHP_SDS_CG_REG_END                                0x01100038
+#define BCHP_SDS_FE_REG_START                              0x01100080
+#define BCHP_SDS_FE_REG_END                                0x011000bc
+#define BCHP_SDS_AGC_REG_START                             0x01100100
+#define BCHP_SDS_AGC_REG_END                               0x01100124
+#define BCHP_SDS_BL_REG_START                              0x01100140
+#define BCHP_SDS_BL_REG_END                                0x01100160
+#define BCHP_SDS_CL_REG_START                              0x01100180
+#define BCHP_SDS_CL_REG_END                                0x011001fc
+#define BCHP_SDS_EQ_REG_START                              0x01100200
+#define BCHP_SDS_EQ_REG_END                                0x0110028c
+#define BCHP_SDS_HP_REG_START                              0x01100300
+#define BCHP_SDS_HP_REG_END                                0x011003d4
+#define BCHP_SDS_VIT_REG_START                             0x01100400
+#define BCHP_SDS_VIT_REG_END                               0x01100428
+#define BCHP_SDS_FEC_REG_START                             0x01100440
+#define BCHP_SDS_FEC_REG_END                               0x01100454
+#define BCHP_SDS_OI_REG_START                              0x01100480
+#define BCHP_SDS_OI_REG_END                                0x011004c8
+#define BCHP_SDS_SNR_REG_START                             0x01100500
+#define BCHP_SDS_SNR_REG_END                               0x01100518
+#define BCHP_SDS_BERT_REG_START                            0x01100540
+#define BCHP_SDS_BERT_REG_END                              0x0110055c
+#define BCHP_SDS_DFT_REG_START                             0x01100580
+#define BCHP_SDS_DFT_REG_END                               0x011005a8
+#define BCHP_SDS_CWC_REG_START                             0x01100600
+#define BCHP_SDS_CWC_REG_END                               0x01100694
+#define BCHP_SDS_MISC_REG_START                            0x01100700
+#define BCHP_SDS_MISC_REG_END                              0x01100798
+#define BCHP_SDS_DSEC_REG_START                            0x01100800
+#define BCHP_SDS_DSEC_REG_END                              0x011008c8
+#define BCHP_SDS_TUNER_REG_START                           0x01100900
+#define BCHP_SDS_TUNER_REG_END                             0x011009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x01100a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x01100a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x01100b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x01100b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x01100c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x01100c0c
+#define BCHP_TFEC_REG_START                                0x01130000
+#define BCHP_TFEC_REG_END                                  0x01130060
+#define BCHP_TFEC_MISC_REG_START                           0x01130100
+#define BCHP_TFEC_MISC_REG_END                             0x01130108
+#define BCHP_TFEC_INTR2_REG_START                          0x01130200
+#define BCHP_TFEC_INTR2_REG_END                            0x0113022c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x01130300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0113030c
+#define BCHP_AFEC_REG_START                                0x01200000
+#define BCHP_AFEC_REG_END                                  0x012003fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x01200800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0120082c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x01200900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0120090c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x01200a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x01200a0c
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x01300000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x01300008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x01320000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0132044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x01321000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x01321058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x01321080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0132109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x01321100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x01321154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x01321400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x01321664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x01322000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x01322014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x01322200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0132222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x01322400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0132242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x01323000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0132357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x01330000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0133bffc
+#define BCHP_AIO_MISC_REG_START                            0x01380000
+#define BCHP_AIO_MISC_REG_END                              0x01380010
+#define BCHP_AIO_INTH_REG_START                            0x01380800
+#define BCHP_AIO_INTH_REG_END                              0x0138082c
+#define BCHP_AIO_INTD0_REG_START                           0x01380a00
+#define BCHP_AIO_INTD0_REG_END                             0x01380a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x013a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x013a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x013a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x013a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x013a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x013a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x013a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x013a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x013a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x013a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x013a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x013a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x013a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x013a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x013a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x013a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x013a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x013a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x013a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x013a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x013a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x013a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x013abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x013abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x013abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x013abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x013b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x013b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x013b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x013b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x013ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x013ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x013ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x013ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x013ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x013ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x013ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x013ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x013bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x013bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x013bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x013bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x013bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x013bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x013bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x013bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x013be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x013be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x01400000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x01400000
+#define BCHP_FTM_UART_REG_START                            0x01410000
+#define BCHP_FTM_UART_REG_END                              0x014100fc
+#define BCHP_FTM_PHY_REG_START                             0x01410000
+#define BCHP_FTM_PHY_REG_END                               0x014101fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x01410000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x01410210
+#define BCHP_FTM_SKIT_REG_START                            0x01410000
+#define BCHP_FTM_SKIT_REG_END                              0x01410248
+#define BCHP_FTM_INTR2_REG_START                           0x01410000
+#define BCHP_FTM_INTR2_REG_END                             0x0141032c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x01410000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0141033c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x01410000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x01410344
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..836adfbe3d74
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:38 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x00a06000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x00a06004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x00a06010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x00a06014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x00a06018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x00a0601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x00a06020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x00a06030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x00a06034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x00a06038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x00a0603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x00a06040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x00a06044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x00a06048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x00a0604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x00a06050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x00a06054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x00a06058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x00a0605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x00a06060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x00a06064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x00a06068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x00a0606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x00a06070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x00a06074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x00a06078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x00a0607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x00a06080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x00a06084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x00a06090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x00a06094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x00a06098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x00a0609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x00a060a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x00a060a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x00a060b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x00a060b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x00a060b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x00a060bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x00a060c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x00a060c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..8d52161aad05
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 13:56:57 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:28p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x00a06200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x00a06204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x00a06208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x00a0620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00a06210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00a06214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00a06218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x00a0621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00a06220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00a06224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00a06228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x00a0622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x00a06230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00a06234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00a06238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x00a0623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00a06240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00a06244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00a06248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x00a0624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00a06250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00a06254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00a06258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x00a0625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00a06260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00a06264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00a06268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x00a0626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00a06270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00a06274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x00a062a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x00a062a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x00a062ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x00a062b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x00a062b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x00a062b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x00a062bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x00a062c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x00a062c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x00a062c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x00a062cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x00a062d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x00a062d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x00a062d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x00a062dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x00a062e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x00a062e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x00a062e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x00a062ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x00a062f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x00a062f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x00a062f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x00a062fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00a06300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00a06304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00a06308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x00a0630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00a06310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00a06314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00a06328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x00a0632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00a06330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00a06334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x00a06338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x00a0633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00a06348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x00a0634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00a06350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00a06354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x00a06358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x00a0635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x00a06360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x00a06364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x00a06370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x00a06374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x00a06378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x00a0637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x00a06380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x00a06384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x00a06388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x00a0638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x00a06390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x00a06394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x00a063a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x00a063a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x00a063a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x00a063ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x00a063b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 000000000000..72871d7f215c
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:38:02 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:09p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x00a06400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x00a06404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x00a06408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x00a0640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x00a06410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x00a06414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x00a06418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x00a0641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x00a06420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x00a06424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x00a06428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x00a0642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x00a06430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x00a06434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x00a06438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x00a0643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x00a06440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x00a06444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x00a06448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x00a0644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x00a06450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x00a06454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x00a06458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x00a0645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x00a06460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x00a06464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x00a06468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x00a0646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x00a06470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x00a06474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x00a064a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x00a064a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x00a064ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x00a064b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x00a064b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x00a064b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x00a064bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x00a064c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x00a064c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x00a064c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x00a064cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x00a064d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x00a064d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x00a064d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x00a064dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x00a064e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x00a064e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x00a064e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x00a064ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x00a064f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x00a064f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x00a064f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x00a064fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x00a06500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x00a06504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x00a06508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x00a0650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x00a06510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x00a06514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x00a06528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x00a0652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x00a06530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x00a06534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x00a06538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x00a0653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x00a06548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x00a0654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x00a06550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x00a06554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x00a06558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x00a0655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x00a06560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x00a06564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x00a06570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x00a06574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x00a06578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x00a0657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x00a06580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x00a06584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x00a06588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x00a0658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x00a06590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x00a06594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x00a065a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x00a065a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x00a065a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x00a065ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x00a065b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_ebi.h b/include/linux/brcmstb/7344b0/bchp_ebi.h
new file mode 100644
index 000000000000..9f1aad8b1e68
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:34:35 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:18p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00000800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00000804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00000808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0000080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00000810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00000814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00000818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0000081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00000820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00000824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00000828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0000082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00000840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00000844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00000848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0000084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00000850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00000854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00000900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00000918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0000091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00000920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x000009f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00000a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..43318e81ae32
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:48:39 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:30p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00001400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00001404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00001408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0000140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00001410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00001414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00001418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0000141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00001420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00001424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00001428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0000142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_MASK        0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_SHIFT       4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_MASK    0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_SHIFT   3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_MASK        0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_SHIFT       2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK     0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT    22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_MASK      0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_SHIFT     4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 000000000000..269f9c4769ac
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1855 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:39:29 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00001600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00001604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00001608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0000160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00001610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00001614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00001618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0000161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00001620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00001624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00001628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0000162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_MC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_20_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_19_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_18_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_17_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_16_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_15_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_SPI_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HIF_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: HDMI_TX_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GFX_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_B_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: GENET_1_A_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xff800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  23
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_MC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_intr2.h b/include/linux/brcmstb/7344b0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..6002a992019b
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_intr2.h
@@ -0,0 +1,1035 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:42:23 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00001000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00001004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00001008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0000100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00001010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00001014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00001018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0000101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00001020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00001024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00001028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0000102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_mspi.h b/include/linux/brcmstb/7344b0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..28cf2954b111
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:44:34 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:31p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00003200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00003204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00003208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0000320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00003210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00003214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00003218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00003220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00003224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00003240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00003244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00003248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0000324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00003250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00003254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00003258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0000325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00003260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00003264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00003268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0000326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00003270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00003274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00003278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0000327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00003280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00003284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00003288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0000328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00003290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00003294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00003298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0000329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x000032a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x000032a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x000032a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x000032ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x000032b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x000032b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x000032b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x000032bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x000032c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x000032c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x000032c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x000032cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x000032d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x000032d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x000032d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x000032dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x000032e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x000032e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x000032e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x000032ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x000032f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x000032f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x000032f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x000032fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00003300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00003304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00003308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0000330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00003310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00003314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00003318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0000331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00003320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00003324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00003328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0000332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00003330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00003334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00003338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0000333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00003340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00003344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00003348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0000334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00003350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00003354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00003358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0000335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00003360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00003364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00003368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0000336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00003370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00003374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00003378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0000337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00003380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00003384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..23109e8dcda3
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:07 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:32p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00001d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00001d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00001d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00001d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00001d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00001d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00001d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00001d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00001d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00001d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00001d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00001d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_irq0.h b/include/linux/brcmstb/7344b0/bchp_irq0.h
new file mode 100644
index 000000000000..797dc359170b
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Sep 16 19:16:14 2011
+ *                 MD5 Checksum         823a10b379073d7995e16a4f32a03392
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   9/19/11 4:07p pntruong
+ * SW7425-1183: Added new int id and synced with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicd_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iicdirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_irq1.h b/include/linux/brcmstb/7344b0/bchp_irq1.h
new file mode 100644
index 000000000000..7df0bdca7323
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_irq1.h
@@ -0,0 +1,50 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:08:30 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..68e7759ca246
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:10:42 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:25p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x000b4200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x000b4204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x000b4208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x000b420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x000b4214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x000b4218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x000b421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x000b4224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..e25d4b44524e
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 17:09:42 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:52p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x00a02000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x00a02004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x00a02008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x00a0200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x00a02010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x00a02014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x00a02018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x00a0201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x00a02020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x00a02024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x00a02028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x00a0202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x00a02030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x00a02034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x00a02038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x00a0203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x00a02040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x00a02044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x00a02048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x00a0204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x00a02050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x00a02054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x00a02058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x00a0205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x00a02060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x00a02064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x00a02068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x00a0206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x00a02070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x00a02074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x00a02078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x00a0207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x00a02080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x00a02084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x00a02088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x00a0208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x00a02090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x00a02094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x00a02098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x00a0209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x00a020a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x00a020a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x00a020a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x00a020ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x00a020b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x00a020b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x00a020b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x00a020bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x00a020c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x00a020c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x00a020c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x00a020cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x00a020d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x00a020d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x00a020d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x00a020dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x00a020e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x00a020e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x00a020e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x00a020ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x00a020f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x00a020f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x00a020f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x00a020fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x00a02100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x00a02104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x00a02108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x00a0210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x00a02110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x00a02114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x00a02118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x00a0211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x00a02120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x00a02124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x00a02128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x00a0212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x00a02130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x00a02134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x00a02138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x00a0213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x00a02140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x00a02144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x00a02148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x00a0214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x00a02150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x00a02154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x00a02158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x00a0215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x00a02160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x00a02164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x00a02168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x00a0216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x00a02170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x00a02174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x00a02178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x00a0217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x00a02180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x00a02184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x00a02188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x00a0218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x00a02190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x00a02194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x00a02198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x00a0219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x00a021a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x00a021a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x00a021a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x00a021ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x00a021b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x00a021b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x00a021b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x00a021bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x00a021c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x00a021c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x00a021c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x00a021cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x00a021d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x00a021d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x00a021d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x00a021dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x00a021e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x00a021e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x00a021e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x00a021ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x00a021f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x00a021f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x00a021f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x00a021fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x00a02200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x00a02204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x00a02208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x00a0220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x00a02210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x00a02214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x00a02218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x00a0221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x00a02220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x00a02224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x00a02228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x00a0222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x00a02230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x00a02234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x00a02238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x00a0223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x00a02240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x00a02244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x00a02248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x00a0224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x00a02250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x00a02254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x00a02258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x00a0225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x00a02260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x00a02264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x00a02268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x00a0226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x00a02270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x00a02274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x00a02278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x00a0227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x00a02280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x00a02284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x00a02288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x00a0228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x00a02290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x00a02294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x00a02298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x00a0229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x00a022a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x00a022a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x00a022a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x00a022ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x00a022b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x00a022b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x00a022b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x00a022bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x00a022c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x00a022c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x00a022c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x00a022cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x00a022d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x00a022d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x00a022d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x00a022dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x00a022e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x00a022e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x00a022e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x00a022ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x00a022f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x00a022f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x00a022f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x00a022fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h
new file mode 100644
index 000000000000..632e9b5a01f6
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_moca_hostmisc.h
@@ -0,0 +1,195 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:41:09 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_moca_hostmisc.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 1:59p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_SW_RESET              0x002a2040 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x002a2044 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG      0x002a204c /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0             0x002a2050 /* Moca Host Messaging Register 0 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1             0x002a2054 /* Moca Host Messaging Register 1 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2             0x002a2058 /* Moca Host Messaging Register 2 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3             0x002a205c /* Moca Host Messaging Register 3 */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x002a2060 /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x002a2064 /* Host-to-MoCA Wakeup Interrupt */
+
+/***************************************************************************
+ *SW_RESET - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SW_RESET :: spare_control [31:15] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_MASK             0xffff8000
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_SHIFT            15
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_DEFAULT          131071
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_status [14:08] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_MASK              0x00007f00
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_SHIFT             8
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_DEFAULT           127
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_MASK       0x00000080
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_SHIFT      7
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_DEFAULT    0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset2 [06:04] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_DEFAULT           7
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_MASK         0x00000008
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_SHIFT        3
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_DEFAULT      0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_MASK               0x00000004
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_SHIFT              2
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_DEFAULT            1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_DEFAULT         1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_cpu_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_DEFAULT         1
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: VALUE [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_DEFAULT                   0
+
+/***************************************************************************
+ *MOCA_VERSION_REG - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_MASK           0xffff0000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_SHIFT          16
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_DEFAULT        26146
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_MASK     0x0000f000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_SHIFT    12
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_MASK      0x00000f00
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_SHIFT     8
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_DEFAULT   1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_MASK     0x000000f0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_SHIFT    4
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_MASK         0x0000000f
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_DEFAULT      0
+
+/***************************************************************************
+ *HOST_MMP0 - Moca Host Messaging Register 0
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP0 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP1 - Moca Host Messaging Register 1
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP1 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP2 - Moca Host Messaging Register 2
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP2 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP3 - Moca Host Messaging Register 3
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP3 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffe
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  1
+
+/* MOCA_HOSTMISC :: WAKEUP :: wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_MASK                  0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_DEFAULT               0
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_nand.h b/include/linux/brcmstb/7344b0/bchp_nand.h
new file mode 100644
index 000000000000..ef922ca32092
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:36:59 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:02p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00002800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00002804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00002808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0000280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00002810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00002814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00002818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00002820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00002824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00002828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0000282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00002830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00002834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00002838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0000283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00002840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00002848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00002850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00002854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00002858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00002860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00002864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00002868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0000286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00002870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00002874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00002878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0000287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00002880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00002884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00002888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0000288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00002890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00002894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00002898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0000289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x000028a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x000028a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x000028a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x000028ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x000028b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x000028b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x000028c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x000028d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x000028d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x000028d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x000028dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x000028e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x000028e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x000028e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x000028ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x000028f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x000028f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x000028f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x000028fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00002900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00002904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00002908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0000290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00002910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00002914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00002918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0000291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00002930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00002934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00002938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0000293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00002940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00002944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00002948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0000294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00002978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0000297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00002a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..786f6c644758
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 14:09:57 2011
+ *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   5/31/11 3:23p albertl
+ * SW7344-40: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00003600 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00003604 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00003608 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0000360c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00003610 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00003614 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00003618 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0000361c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00003620 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00003630 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00003634 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x000036fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x000036f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..854210168573
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6592 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 20:14:25 2011
+ *                 MD5 Checksum         bdb30c5d18c5d13008bcd4430a6d3384
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   8/9/11 11:21a pntruong
+ * SW7344-144: Synced with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x00404178 /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x0040417c /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1933836304
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1933836304
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffff800
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            11
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000003c0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   10
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_mips_freq [05:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_MASK       0x00000030
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_DEFAULT    0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK      0x0000001c
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT   2
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_enable_ext_cml [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_freq_pllmips [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_freq_pllmips_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pvtmon_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pvtmon_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_adjust_voltage [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_adjust_voltage_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_freq_pllmips [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_freq_pllmips_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pvtmon_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pvtmon_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_adjust_voltage [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_adjust_voltage_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [06:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_31_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_30_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_29_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_28_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_27_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_26_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_25_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_24_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_51 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_51_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_50 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_50_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_49 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_49_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_48 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_48_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_47 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_47_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_46 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_46_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_45 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_45_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_44 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_44_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_19_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_18_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_16_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_15_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_14_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_12_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_11_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_10_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_09_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_08_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_07_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_06_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_05_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_04_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_03_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_02_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_01_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_00_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_75 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_VO_656_7          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDIO_CMD          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_DEMOD_ERROR  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_SDS0_BERT_ERROR   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_74 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_VO_656_6          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDIO_WPROT        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_DEMOD_VALID  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_SDS0_BERT_VALID   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_73 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_VO_656_5          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDIO_PRES         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_SDS0_BERT_SYNC    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_73_PM_GPIO_73        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_72 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_VO_656_4          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDIO_PWR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_DEMOD_DATA   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_SDS0_BERT_DATA    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_72_PM_GPIO_72        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_71 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_VO_656_3          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDIO_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_DEMOD_CLK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_SDS0_BERT_CLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_71_PM_GPIO_71        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_70 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_VO_656_2          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_EXT_IRQB_15       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_SDIO_DATA2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_69 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_VO_656_1          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_EXT_IRQB_14       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_SDIO_DATA1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_69_PM_GPIO_69        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_68 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_VO_656_0          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_EXT_IRQB_13       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_SDIO_DATA0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_68_PM_GPIO_68        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data1 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_EBI_DATA1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data1_ALT_TP_IN_01    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_EBI_DATA0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_ALT_TP_IN_00    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: clk_acc [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_CLK_ACC           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_clk_acc_EXT_SC_CLK        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: usb0_pwron [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_USB0_PWRON     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_usb0_pwron_TP_IN_20       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: aud_spdif [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_AUD_SPDIF       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_aud_spdif_RO_TEST_OUT     1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_78 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_GPIO_78           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_TTX_DATA          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_EXT_IRQB_15       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_78_PM_GPIO_78        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_77 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_GPIO_77           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_TTX_REQ           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_SDIO_LED          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_77_PM_GPIO_77        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_76 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_VO_656_CLK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_SDIO_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_76_PM_GPIO_76        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data9 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_EBI_DATA9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data9_ALT_TP_IN_09    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data8 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_EBI_DATA8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_ALT_TP_IN_08    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data7 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_EBI_DATA7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_ALT_TP_IN_07    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data6 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_EBI_DATA6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_ALT_TP_IN_06    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data5 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_EBI_DATA5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_ALT_TP_IN_05    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data4 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_EBI_DATA4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_ALT_TP_IN_04    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data3 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_EBI_DATA3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_ALT_TP_IN_03    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_EBI_DATA2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_ALT_TP_IN_02    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr1 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_EBI_ADDR1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr1_ALT_TP_IN_17    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_EBI_ADDR0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_ALT_TP_IN_16    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data15 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_EBI_DATA15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_ALT_TP_IN_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data14 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_EBI_DATA14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_ALT_TP_IN_14   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data13 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_EBI_DATA13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_ALT_TP_IN_13   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data12 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_EBI_DATA12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_ALT_TP_IN_12   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data11 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_EBI_DATA11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_ALT_TP_IN_11   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data10 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_EBI_DATA10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_ALT_TP_IN_10   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr9 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_EBI_ADDR9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr9_ALT_TP_IN_25    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr8 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_EBI_ADDR8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_ALT_TP_OUT_24   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr7 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_EBI_ADDR7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_ALT_TP_IN_23    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr6 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_EBI_ADDR6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_ALT_TP_IN_22    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr5 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_EBI_ADDR5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_ALT_TP_IN_21    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr4 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_EBI_ADDR4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_ALT_TP_IN_20    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr3 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_EBI_ADDR3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_ALT_TP_IN_19    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_EBI_ADDR2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_ALT_TP_IN_18    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_82 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_GPIO_82           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_USB2_PWRFLT       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_82_PM_GPIO_82        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_81 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_GPIO_81           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_USB2_PWRON        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_81_PM_GPIO_81        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr15 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_EBI_ADDR15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_ALT_TP_IN_31   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr14 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_EBI_ADDR14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_ALT_TP_IN_30   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr13 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_EBI_ADDR13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_ALT_TP_IN_29   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr12 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_EBI_ADDR12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_ALT_TP_OUT_28  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr11 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_EBI_ADDR11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_ALT_TP_IN_27   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr10 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_EBI_ADDR10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_ALT_TP_IN_26   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_05 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_CHIP2CI_MDO_5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PPKT_O_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_SDS0_O_DATA_5     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_IN  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_I2S_BIDIR_CLK_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_TP_OUT_09         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_05_PM_GPIO_05        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_04 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_CHIP2CI_MDO_4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PPKT_O_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_SDS0_O_DATA_4     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_IN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_I2S_BIDIR_SYNC_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_TP_OUT_08         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_04_PM_GPIO_04        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_03 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_CHIP2CI_MDO_3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PPKT_O_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_SDS0_O_DATA_3     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_IN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_I2S_BIDIR_DATA_OUT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_TP_OUT_07         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_03_PM_GPIO_03        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_02 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_CHIP2CI_MDO_2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PPKT_O_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_SDS0_O_DATA_2     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_TP_OUT_06         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_02_PM_GPIO_02        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_01 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_CHIP2CI_MDO_1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PPKT_O_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_SDS0_O_DATA_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_TP_OUT_05         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_01_PM_GPIO_01        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_00 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_CHIP2CI_MDO_0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PPKT_O_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_SDS0_O_DATA_0     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_TP_OUT_04         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_00_PM_GPIO_00        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_84 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_GPIO_84           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_USB3_PWRFLT       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_84_PM_GPIO_84        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_83 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_GPIO_83           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_USB3_PWRON        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_83_PM_GPIO_83        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_13 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_CI2CHIP_MIVAL     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_TP_OUT_17         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_13_PM_GPIO_13        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_12 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_CI2CHIP_MISTRT    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_TP_OUT_16         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_12_PM_GPIO_12        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_11 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MOCLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PPKT_O_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_SDS0_O_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_CHIP2CI_MCLKO     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_TP_OUT_15         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_11_PM_GPIO_11        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_10 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MCLKO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PPKT_O_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_CHIP2CI_MOCLK     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_TP_OUT_14         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_10_PM_GPIO_10        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_09 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_CHIP2CI_MOVAL     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PPKT_O_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_SDS0_O_VALID      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_TP_OUT_13         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_09_PM_GPIO_09        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_08 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_CHIP2CI_MOSTRT    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PPKT_O_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_SDS0_O_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_TP_OUT_12         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_08_PM_GPIO_08        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_07 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_CHIP2CI_MDO_7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PPKT_O_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_SDS0_O_DATA_7     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_TP_OUT_11         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_07_PM_GPIO_07        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_06 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_CHIP2CI_MDO_6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PPKT_O_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_SDS0_O_DATA_6     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_TP_OUT_10         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_06_PM_GPIO_06        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_24 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_MII_RGMII_RXD_02  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_VEC_VSYNC_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_TP_IN_01          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_24_PM_GPIO_24        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_23 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_MII_RGMII_RXD_03  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_VEC_VSYNC_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_TP_IN_00          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_23_PM_GPIO_23        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_19 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_SPI_S_MISO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PWM_3             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_EXT_SC_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_AIO_EXTMCLK1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_CHIP2CC_SCTL      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_TP_OUT_23         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_19_PM_GPIO_19        7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_18 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_SPI_S_SS0B        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PWM_2             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_AIO_EXTMCLK0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_CHIP2CC_SCLK      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_TP_OUT_22         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_18_PM_GPIO_18        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_17 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_I2S_O_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_RMX_VALID0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_CHIP2CC_SDO       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_17_PM_GPIO_17        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_16 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_I2S_O_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_RMX_PAUSE0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_CC2CHIP_SDI       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_16_PM_GPIO_16        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_15 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MICLK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_CI2CHIP_MCLKI     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_TP_OUT_19         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_15_PM_GPIO_15        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_14 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MCLKI     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_CI2CHIP_MICLK     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_TP_OUT_18         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_14_PM_GPIO_14        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_34 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_MII_RGMII_TX_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_FSK_UART_MAN_DATA 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_TP_IN_11          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_34_PM_GPIO_34        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_31 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_MII_RGMII_RX_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_TP_IN_08          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_31_PM_GPIO_31        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_30 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_MII_COL           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_TP_IN_07          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_30_PM_GPIO_30        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_29 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_MII_CRS           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_TP_IN_06          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_29_PM_GPIO_29        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_28 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_MII_RXDV_RGMII_RXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_TP_IN_05          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_28_PM_GPIO_28        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_27 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_MII_RX_ER         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_TP_IN_04          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_27_PM_GPIO_27        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_26 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_MII_RGMII_RXD_00  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_VEC_HSYNC_1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_TP_IN_03          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_25 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_MII_RGMII_RXD_01  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_VEC_HSYNC_0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_TP_IN_02          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_25_PM_GPIO_25        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_33 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_GPIO_33          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_MII_MDC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_TP_IN_10         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_33_PM_GPIO_33       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_32 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_GPIO_32          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_MII_MDIO         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_TP_IN_09         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_32_PM_GPIO_32       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_40 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_GPIO_40          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_MII_RGMII_TXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_TP_IN_17         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_40_PM_GPIO_40       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_39 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_GPIO_39          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_MII_RGMII_TXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_TP_IN_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_39_PM_GPIO_39       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_38 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_GPIO_38          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_MII_RGMII_TXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_TP_IN_15         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_38_PM_GPIO_38       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_37 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_GPIO_37          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_MII_RGMII_TXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_TP_IN_14         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_37_PM_GPIO_37       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_36 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_GPIO_36          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_MII_TXER         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_TP_IN_13         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_36_PM_GPIO_36       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_35 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_GPIO_35          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_MII_TXEN_RGMII_TXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_FSK_RX_DATA_BYP  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_TP_IN_12         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_35_PM_GPIO_35       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_49 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_GPIO_49          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_SC0_IO_AUX1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_CI2CHIP_MDI_5    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PPKT_I_DATA_5    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_TP_IN_26         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_49_PM_GPIO_49       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_48 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_GPIO_48          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_CI2CHIP_MDI_4    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PPKT_I_DATA_4    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_TP_IN_25         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_48_PM_GPIO_48       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_47 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_GPIO_47          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_CI2CHIP_MDI_3    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PPKT_I_DATA_3    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_TP_IN_24         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_47_PM_GPIO_47       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_46 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_GPIO_46          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_CI2CHIP_MDI_2    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PPKT_I_DATA_2    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_TP_IN_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_46_PM_GPIO_46       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_45 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_GPIO_45          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_SC0_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_CI2CHIP_MDI_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PPKT_I_DATA_1    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_TP_IN_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_45_PM_GPIO_45       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_44 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_GPIO_44          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_CI2CHIP_MDI_0    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PPKT_I_DATA_0    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_TP_IN_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_44_PM_GPIO_44       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_42 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_GPIO_42          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PWM_1            1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_TP_IN_19         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_42_PM_GPIO_42       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_41 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_GPIO_41          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PWM_0            1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PVTMON_DATA_FREQ 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_TP_IN_18         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_41_PM_GPIO_41       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_20 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_GPIO_20          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_SC1_IO_AUX1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_20_PM_GPIO_20       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_56 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_GPIO_56          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_SC1_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_ALT_TP_OUT_01    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_56_PM_GPIO_56       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_55 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_GPIO_55          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_SC1_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_ALT_TP_OUT_00    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_55_PM_GPIO_55       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_54 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_GPIO_54          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_SC1_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_TP_IN_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_54_PM_GPIO_54       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_53 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_GPIO_53          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_SC1_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_TP_IN_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_53_PM_GPIO_53       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_52 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_GPIO_52          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_SC1_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_TP_IN_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_52_PM_GPIO_52       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_51 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_GPIO_51          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_CI2CHIP_MDI_7    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PPKT_I_DATA_7    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_TP_IN_28         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_51_PM_GPIO_51       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_50 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_GPIO_50          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_SC0_IO_AUX2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_CI2CHIP_MDI_6    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PPKT_I_DATA_6    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_TP_IN_27         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_50_PM_GPIO_50       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: rmx_clk0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_RMX_CLK0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_rmx_clk0_ALT_TP_OUT_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_error0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PKT_ERROR0    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_DEMOD_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_SDS0_BERT_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_MTSIF_RX_DATA_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_error0_PM_PKT_ERROR0 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_valid0 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PKT_VALID0    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_DEMOD_VALID 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_SDS0_BERT_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_MTSIF_RX_DATA_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_valid0_PM_PKT_VALID0 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_sync0 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PKT_SYNC0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_DEMOD_SYNC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_SDS0_BERT_SYNC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_MTSIF_RX_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_sync0_PM_PKT_SYNC0   4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_data0 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PKT_DATA0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_DEMOD_DATA 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_SDS0_BERT_DATA 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_MTSIF_RX_DATA_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_data0_PM_PKT_DATA0   4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: pkt_clk0 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PKT_CLK0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_DEMOD_CLK  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_SDS0_BERT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_MTSIF_RX_CLK    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_pkt_clk0_PM_PKT_CLK0     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_22 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_GPIO_22          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_SC1_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_22_PM_GPIO_22       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_21 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_GPIO_21          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_SC1_IO_AUX2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_21_PM_GPIO_21       2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_62 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_GPIO_62          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PKT_CLK2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_MTSIF_RX_DATA_7  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_ALT_TP_OUT_07    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_62_PM_GPIO_62       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_61 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_GPIO_61          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PKT_ERROR1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_SDS0_DEMOD_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_I2S_O_CLK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_61_PM_GPIO_61       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_60 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_GPIO_60          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PKT_VALID1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_SDS0_DEMOD_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_MTSIF_RX_DATA_6  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_60_PM_GPIO_60       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_59 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_GPIO_59          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PKT_SYNC1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_SDS0_DEMOD_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_MTSIF_RX_DATA_5  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_59_PM_GPIO_59       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_58 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_GPIO_58          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PKT_DATA1        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_SDS0_DEMOD_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_MTSIF_RX_DATA_4  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_58_PM_GPIO_58       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_57 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_GPIO_57          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PKT_CLK1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_SDS0_DEMOD_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_MTSIF_RX_DATA_3  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_57_PM_GPIO_57       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_sync0 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_RMX_SYNC0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_sync0_ALT_TP_OUT_17  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: rmx_data0 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_RMX_DATA0      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_rmx_data0_ALT_TP_OUT_16  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_80 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_MOCA_ACTIVITY_N  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_EXT_IRQB_20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_79 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_MOCA_LINK_N      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_EXT_IRQB_19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_GPIO_66          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ENET_ACTIVITY    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_MOCA_ACTIVE_N    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_ALT_TP_OUT_14    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_66_PM_GPIO_66       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_43 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_GPIO_43          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ENET_LINK        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_MOCA_LINK_N      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_ALT_TP_OUT_13    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_43_PM_GPIO_43       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_67 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_GPIO_67          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PKT_ERROR2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_MTSIC_ATS_RESET  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_ALT_TP_OUT_12    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_67_PM_GPIO_67       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_65 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_GPIO_65          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PKT_VALID2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_MTSIF_ATS_INC    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_ALT_TP_OUT_11    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_65_PM_GPIO_65       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_64 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_GPIO_64          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PKT_SYNC2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_EXT_IRQB_18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_ALT_TP_OUT_10    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_64_PM_GPIO_64       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_63 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_GPIO_63          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PKT_DATA2        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_EXT_IRQB_17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_ALT_TP_OUT_09    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_63_PM_GPIO_63       4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sdi [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_CODEC_SDI      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_ALT_TP_OUT_21  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sdi_PM_CODEC_SDI   2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_sclk [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_MASK          0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_CODEC_SCLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_I2S_O_SYNC    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_ALT_TP_OUT_20 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_sclk_PM_CODEC_SCLK 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_mclk [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_CODEC_MCLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_I2S_O_DATA    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_ALT_TP_OUT_19 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_PM_CODEC_MCLK 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: ir_out [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_IR_OUT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_ALT_TP_OUT_18     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_PM_IR_OUT         2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_05 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_05_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_04 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_BSC_M3_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txdb [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_UART_TXDB      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txdb_ALT_TP_OUT_29  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxdb [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_UART_RXDB      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxdb_ALT_TP_IN_28   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rtsab [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_UART_RTSAB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_ALT_TP_OUT_27 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_ctsab [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_UART_CTSAB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_ALT_TP_OUT_26 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txda [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_UART_TXDA      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_ALT_TP_OUT_25  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxda [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_UART_RXDA      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_ALT_TP_IN_24   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_fsync [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_CODEC_FSYNC  0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_ALT_TP_OUT_23 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_PM_CODEC_FSYNC 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sdo [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_CODEC_SDO      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_I2S_O_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_ALT_TP_OUT_22  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_PM_CODEC_SDO   3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xffffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_rtsbb [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_MASK          0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_UART_RTSBB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_ALT_TP_OUT_31 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_ctsbb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_MASK          0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_UART_CTSBB    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_ALT_TP_OUT_30 1
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x3f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_78_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_77_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_76_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_75_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_74_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_73_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_72_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_71_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_70_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_70_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_69_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_68_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr23_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved1 [25:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_MASK        0x03ffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_dsb_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       12
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr26_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr25_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr24_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved2 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_14_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_13_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_12_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_11_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_10_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_09_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_08_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_08_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_07_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_06_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_05_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_04_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_03_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_02_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_01_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_00_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_34_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_31_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_30_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_29_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_28_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_27_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_26_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_25_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_24_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_23_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_19_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_18_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_17_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_16_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_15_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_48_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_47_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_46_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_45_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_44_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_42_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_41_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_33_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_32_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_40_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_40_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_39_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_38_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_37_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_36_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_35_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_35_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_22_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_21_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_20_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_56_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_55_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_55_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_54_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_53_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_52_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_51_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_50_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_49_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_49_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_43_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_67_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_65_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_64_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_63_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_62_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_61_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_60_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_59_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_58_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_57_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [07:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK       0x3fffffc0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_80_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_79_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_66_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0xffff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved1 [13:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_MASK       0x00003fff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved1_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffe00000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       21
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_79 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_79_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_59 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_59_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_58 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_58_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_57 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_57_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_valid0 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_clk0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_rbb [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs5b [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs5b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs4b [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_moca_clk [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_clk_acc [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_vcxo27 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb1_pwrflt [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb0_pwrflt [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_76 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_76_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_72 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_71 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_71_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_69 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_68 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         29
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xe0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xe0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         7
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffff80
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffff80
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xe0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 29
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffff80
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 7
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 8
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 3
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_timer.h b/include/linux/brcmstb/7344b0/bchp_timer.h
new file mode 100644
index 000000000000..41dbc1622381
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:31:37 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:26p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uarta.h b/include/linux/brcmstb/7344b0/bchp_uarta.h
new file mode 100644
index 000000000000..febb3bf55859
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:45:48 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:28p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uartb.h b/include/linux/brcmstb/7344b0/bchp_uartb.h
new file mode 100644
index 000000000000..6e9845880045
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uartb.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:10:53 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_uartc.h b/include/linux/brcmstb/7344b0/bchp_uartc.h
new file mode 100644
index 000000000000..ee6b0a59c88a
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_uartc.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri May 21 13:01:00 2010
+ *                 MD5 Checksum         34dd0d3bbf3478606c423cca67439a45
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h
new file mode 100644
index 000000000000..9fe8a3dd8b0b
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:30:48 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:30p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..9aacc97e5375
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_usb_ctrl.h
@@ -0,0 +1,685 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:37:40 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:32p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x78000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/* USB_CTRL :: USB_SIMCTL :: USB_CAP_DIS [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_MASK                  0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_SHIFT                 0
+#define BCHP_USB_CTRL_USB_SIMCTL_USB_CAP_DIS_DEFAULT               0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/bchp_wktmr.h b/include/linux/brcmstb/7344b0/bchp_wktmr.h
new file mode 100644
index 000000000000..37afa672766c
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Apr  1 16:31:43 2011
+ *                 MD5 Checksum         d03d08c4839c3311c9d35c4cd5e10373
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/4/11 2:39p albertl
+ * SW7344-40: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7344b0/brcmirq.h b/include/linux/brcmstb/7344b0/brcmirq.h
new file mode 100644
index 000000000000..0a3ce03733dc
--- /dev/null
+++ b/include/linux/brcmstb/7344b0/brcmirq.h
@@ -0,0 +1,47 @@
+/*
+ * 7344b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	31
+#define BRCM_IRQ_GENET_0_B	32
+#define BRCM_IRQ_GENET_1_A	33
+#define BRCM_IRQ_GENET_1_B	34
+#define BRCM_IRQ_HIF		37
+#define BRCM_IRQ_HIF_SPI	38
+#define BRCM_IRQ_MOCA		42
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h b/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..d672f409ddef
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_ctrl.h
@@ -0,0 +1,1606 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:17:52 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:51p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL   0x00408090 /* Ana xtal low cur 40g m7fc external CML control */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xfffffe00
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             9
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [08:08] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000100
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 8
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [07:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000080
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 7
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [06:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000078
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      8
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xffffff00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                8
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_alternate_enable [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_MASK 0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_alternate_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0
+
+/***************************************************************************
+ *ANA_XTAL_EXT_CML_CONTROL - Ana xtal low cur 40g m7fc external CML control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: reserved0 [31:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_MASK      0xffffffc0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_reserved0_SHIFT     6
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_PMSM_S3_pd_buffer [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_PMSM_S3_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_override_strap [04:04] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_MASK 0x00000010
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_SHIFT 4
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_override_strap_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_pd_buffer [03:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_MASK  0x00000008
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_SHIFT 3
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_pd_buffer_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_div2_sel [02:02] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_MASK   0x00000004
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_SHIFT  2
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_div2_sel_DEFAULT 1
+
+/* AON_CTRL :: ANA_XTAL_EXT_CML_CONTROL :: osc_current [01:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_MASK    0x00000003
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_SHIFT   0
+#define BCHP_AON_CTRL_ANA_XTAL_EXT_CML_CONTROL_osc_current_DEFAULT 1
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..2dd9862b14d8
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,658 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:05:37 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:51p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_005 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_AON_GPIO_005 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_LED_LS_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_SC0_PRES     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_CI2CHIP_MDI3 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_PKT_VALID4   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_005_TP_OUT_05    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_004 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_AON_GPIO_004 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_LED_LS_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_SC0_RST      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_CI2CHIP_MDI2 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_PKT_DATA4    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_TP_OUT_04    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_004_PM_AON_GPIO_004 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_sgpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_AON_SGPIO_03 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_LED_KD_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_03_BSC_M4_SDA   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_sgpio_02 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_AON_SGPIO_02 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_LED_KD_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_sgpio_02_BSC_M4_SCL   2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_001 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_AON_GPIO_001 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_LED_KD_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_SC_EXT_CLK   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_CI2CHIP_MIVAL 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_001_PM_AON_GPIO_001 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_000 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_AON_GPIO_000 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_LED_KD_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_SC_CLK_OUT   2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_CI2CHIP_MISTRT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_000_PM_AON_GPIO_000 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_03       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_PM_AON_IR_IN0  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: hdmi_htplg [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_HDMI_HTPLG     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_hdmi_htplg_ALT_TP_OUT_26  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_013 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_AON_GPIO_013 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_LED_LD_4     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SC1_RST      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_CHIP2CI_MDO0 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_EXT_IRQB_1   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_SPI_M_SS0B   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_TP_OUT_13    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_013_PM_AON_GPIO_013 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_012 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_AON_GPIO_012 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_LED_LD_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_SC1_PRES     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_CHIP2CI_MOSTRT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_EXT_IRQB_0   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_TP_OUT_12    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_012_PM_AON_GPIO_012 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_011 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_AON_GPIO_011 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_LED_LD_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_SC1_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_CHIP2CI_MOVAL 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_IR_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_TP_OUT_19    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_011_PM_AON_GPIO_011 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_010 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_AON_GPIO_010 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_LED_LD_1     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_SC1_IO       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_CI2CHIP_MICLK 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_010_PM_AON_GPIO_010 4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_009 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_AON_GPIO_009 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_LED_LD_0     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_SC0_VPP      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_CI2CHIP_MDI7 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_I2S_LR1_OUT  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_I2S_LR1_IN   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_009_PM_AON_GPIO_009 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_008 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_AON_GPIO_008 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_LED_LS_4     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_SC0_AUX_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_CI2CHIP_MDI6 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_I2S_DATA1_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_I2S_DATA1_IN 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_PKT_CLK4     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_TP_OUT_08    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_008_PM_AON_GPIO_008 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_007 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_AON_GPIO_007 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_LED_LS_3     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_SC0_AUX_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_CI2CHIP_MDI5 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_I2S_CLK1_OUT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_I2S_CLK1_IN  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_PKT_ERROR4   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_TP_OUT_24    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_007_PM_AON_GPIO_007 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_006 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_AON_GPIO_006 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_LED_LS_2     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_SC0_VCC      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_CI2CHIP_MDI4 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_PKT_SYNC4    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_006_TP_OUT_06    5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_021 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_AON_GPIO_021 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_SPI_M_SCK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_CHIP2CI_MOCLK 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_TTX0_REQ     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_VEC_VSYNC_0  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_VEC_HSYNC_0  5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_TP_IN_07     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_021_PM_AON_GPIO_021 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_020 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_AON_GPIO_020 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_SPI_M_MISO   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_CHIP2CI_MDO7 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_VEC_VSYNC_1  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_VEC_HSYNC_1  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_TTX0_DATA    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_TP_OUT_22    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_020_PM_AON_GPIO_020 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_019 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_AON_GPIO_019 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_SPI_M_MOSI   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_CHIP2CI_MDO6 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_VEC_VSYNC_0  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_VEC_HSYNC_0  4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_019_TP_OUT_27    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_018 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_AON_GPIO_018 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_SPI_M_SCK    1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_CHIP2CI_MDO5 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_018_TP_OUT_16    3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_017 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_DEFAULT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_AON_GPIO_017 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_IR_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_SC1_VPP      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_CHIP2CI_MDO4 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_LED_OUT      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_017_TP_OUT_15    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_016 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_AON_GPIO_016 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_LED_LD_7     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SC1_AUX_2    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_CHIP2CI_MDO3 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_EXT_IRQB_4   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_SPI_M_MISO   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_TP_IN_21     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_016_PM_AON_GPIO_016 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_015 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_AON_GPIO_015 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_LED_LD_6     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SC1_AUX_1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_CHIP2CI_MDO2 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_EXT_IRQB_3   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_SPI_M_MOSI   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_TP_IN_04     6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_015_PM_AON_GPIO_015 7
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_014 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_AON_GPIO_014 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_LED_LD_5     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SC1_VCC      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_CHIP2CI_MDO1 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_EXT_IRQB_2   4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_SPI_M_SCK    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_TP_OUT_14    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_014_PM_AON_GPIO_014 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           28
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M0_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_22     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_00 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_MASK         0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_SHIFT        20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_BSC_M0_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_00_TP_IN_23     2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_026 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_MASK         0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_SHIFT        16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_AON_GPIO_026 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_IR_IN1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_AUD_FS_CLK1  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_SDS1_DSEC_TXEN 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_CI2CHIP_MDI1 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_TP_OUT_00    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_026_PM_AON_GPIO_026 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_025 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_MASK         0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_SHIFT        12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_AON_GPIO_025 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_IR_INT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_AUD_FS_CLK0  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_SDS1_DSEC_TXOUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_CI2CHIP_MDI0 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_TP_IN_29     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_025_PM_AON_GPIO_025 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_024 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_MASK         0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SHIFT        8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_AON_GPIO_024 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SPI_M_SS0B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_AUD_FS_CLK1  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_CI2CHIP_MCLKI 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_SC0_CLK      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_TP_IN_28     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_024_PM_AON_GPIO_024 6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_023 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_MASK         0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SHIFT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_AON_GPIO_023 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SPI_M_SS1B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_AUD_FS_CLK0  2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_CHIP2CI_MCLKO 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_SC0_IO       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_023_TP_OUT_10    5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_gpio_022 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_AON_GPIO_022 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_SPI_M_SS2B   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_gpio_022_TP_OUT_09    2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_012_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_012_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_011_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_011_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_010_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_010_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_009_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_009_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_008_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_008_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_007_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_007_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [17:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0003c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       14
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_004_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_004_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK        0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT       8
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_001_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_001_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_000_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_000_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_ir_in0_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_DEFAULT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_ir_in0_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved2 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       28
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_026_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_026_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_025_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_025_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_024_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_024_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [21:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x003c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       18
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_021_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_021_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_020_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_020_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved2 [13:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_MASK        0x00003f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved2_SHIFT       8
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_016_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_016_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_015_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_015_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_014_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_014_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_013_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_013_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_010 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_010_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_009 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_009_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_001 [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_001_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_gpio_000 [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_gpio_000_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..f511dfdd905b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_aon_pm_l2.h
@@ -0,0 +1,1647 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:10 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 2:26p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xfe000000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  25
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x01000000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       24
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00800000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   23
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00400000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          22
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_MASK                        0x00200000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_SHIFT                       21
+#define BCHP_AON_PM_L2_CPU_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_MASK                        0x00100000
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_SHIFT                       20
+#define BCHP_AON_PM_L2_CPU_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_MASK                        0x00080000
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_SHIFT                       19
+#define BCHP_AON_PM_L2_CPU_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00040000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    18
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00020000
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        17
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_MASK                   0x00010000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_SHIFT                  16
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_MASK                   0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_SHIFT                  15
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_MASK                 0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_SHIFT                14
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_MASK                 0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_SHIFT                13
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS1_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_CPU_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xfe000000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     25
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x01000000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          24
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00800000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      23
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00400000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             22
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_SET_USB1_MASK                           0x00200000
+#define BCHP_AON_PM_L2_CPU_SET_USB1_SHIFT                          21
+#define BCHP_AON_PM_L2_CPU_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_SET_USB0_MASK                           0x00100000
+#define BCHP_AON_PM_L2_CPU_SET_USB0_SHIFT                          20
+#define BCHP_AON_PM_L2_CPU_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_MASK                           0x00080000
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_SHIFT                          19
+#define BCHP_AON_PM_L2_CPU_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00040000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       18
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00020000
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           17
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_MASK                      0x00010000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_SHIFT                     16
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_MASK                      0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_SHIFT                     15
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_MASK                    0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_SHIFT                   13
+#define BCHP_AON_PM_L2_CPU_SET_SDS1_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_CPU_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_CPU_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xfe000000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   25
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x01000000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        24
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00800000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    23
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00400000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           22
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_MASK                         0x00200000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_SHIFT                        21
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_MASK                         0x00100000
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_SHIFT                        20
+#define BCHP_AON_PM_L2_CPU_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_MASK                         0x00080000
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_SHIFT                        19
+#define BCHP_AON_PM_L2_CPU_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00040000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     18
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00020000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         17
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_MASK                    0x00010000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_SHIFT                   16
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_MASK                    0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_SHIFT                   15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_MASK                  0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_SHIFT                 13
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS1_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_CPU_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             25
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  24
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              23
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     22
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_MASK                   0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_SHIFT                  21
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_MASK                   0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_SHIFT                  20
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_MASK                   0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_SHIFT                  19
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               18
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   17
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_MASK              0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_SHIFT             16
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_MASK              0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_SHIFT             15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_MASK            0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_SHIFT           14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS1_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                25
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     24
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 23
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        22
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_MASK                      0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_SHIFT                     21
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_MASK                      0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_SHIFT                     20
+#define BCHP_AON_PM_L2_CPU_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_MASK                      0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_SHIFT                     19
+#define BCHP_AON_PM_L2_CPU_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  18
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      17
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_MASK                 0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_SHIFT                16
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_MASK                 0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_SHIFT                15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_MASK               0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_SHIFT              13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS1_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xfe000000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              25
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x01000000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   24
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00800000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               23
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00400000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      22
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_MASK                    0x00200000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_SHIFT                   21
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_MASK                    0x00100000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_SHIFT                   20
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_MASK                    0x00080000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_SHIFT                   19
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00040000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                18
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00020000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    17
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_MASK               0x00010000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_SHIFT              16
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_MASK               0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_SHIFT              15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_MASK             0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_SHIFT            14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_MASK             0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_SHIFT            13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS1_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xfe000000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  25
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x01000000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       24
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00800000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   23
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00400000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          22
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_MASK                        0x00200000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_SHIFT                       21
+#define BCHP_AON_PM_L2_PCI_STATUS_USB1_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_MASK                        0x00100000
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_SHIFT                       20
+#define BCHP_AON_PM_L2_PCI_STATUS_USB0_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_MASK                        0x00080000
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_SHIFT                       19
+#define BCHP_AON_PM_L2_PCI_STATUS_MOCA_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00040000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    18
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00020000
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        17
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_MASK                   0x00010000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_SHIFT                  16
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_MASK                   0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_SHIFT                  15
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_MASK                 0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_SHIFT                14
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_MASK                 0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_SHIFT                13
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS1_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  11
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_MOCA_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_MASK                        0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_SHIFT                       6
+#define BCHP_AON_PM_L2_PCI_STATUS_UHFR_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xfe000000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     25
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x01000000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          24
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00800000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      23
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00400000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             22
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_SET_USB1_MASK                           0x00200000
+#define BCHP_AON_PM_L2_PCI_SET_USB1_SHIFT                          21
+#define BCHP_AON_PM_L2_PCI_SET_USB1_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_SET_USB0_MASK                           0x00100000
+#define BCHP_AON_PM_L2_PCI_SET_USB0_SHIFT                          20
+#define BCHP_AON_PM_L2_PCI_SET_USB0_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_MASK                           0x00080000
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_SHIFT                          19
+#define BCHP_AON_PM_L2_PCI_SET_MOCA_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00040000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       18
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00020000
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           17
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_MASK                      0x00010000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_SHIFT                     16
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_MASK                      0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_SHIFT                     15
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_MASK                    0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_SHIFT                   13
+#define BCHP_AON_PM_L2_PCI_SET_SDS1_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     11
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      8
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_MASK                       0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_SHIFT                      7
+#define BCHP_AON_PM_L2_PCI_SET_WOL_MOCA_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_MASK                           0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_SHIFT                          6
+#define BCHP_AON_PM_L2_PCI_SET_UHFR_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xfe000000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   25
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x01000000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        24
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00800000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    23
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00400000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           22
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_MASK                         0x00200000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_SHIFT                        21
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB1_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_MASK                         0x00100000
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_SHIFT                        20
+#define BCHP_AON_PM_L2_PCI_CLEAR_USB0_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_MASK                         0x00080000
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_SHIFT                        19
+#define BCHP_AON_PM_L2_PCI_CLEAR_MOCA_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00040000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     18
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00020000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         17
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_MASK                    0x00010000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_SHIFT                   16
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_MASK                    0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_SHIFT                   15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_MASK                  0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_SHIFT                 13
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS1_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   12
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    8
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_MASK                     0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_SHIFT                    7
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_MOCA_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_MASK                         0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_SHIFT                        6
+#define BCHP_AON_PM_L2_PCI_CLEAR_UHFR_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             25
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  24
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              23
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     22
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_MASK                   0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_SHIFT                  21
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB1_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_MASK                   0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_SHIFT                  20
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_USB0_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_MASK                   0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_SHIFT                  19
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_MOCA_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               18
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   17
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_MASK              0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_SHIFT             16
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_MASK              0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_SHIFT             15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_MASK            0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_SHIFT           14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS1_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_MOCA_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_MASK                   0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_SHIFT                  6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_UHFR_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                25
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     24
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 23
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        22
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_MASK                      0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_SHIFT                     21
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB1_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_MASK                      0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_SHIFT                     20
+#define BCHP_AON_PM_L2_PCI_MASK_SET_USB0_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_MASK                      0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_SHIFT                     19
+#define BCHP_AON_PM_L2_PCI_MASK_SET_MOCA_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  18
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      17
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_MASK                 0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_SHIFT                16
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_MASK                 0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_SHIFT                15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_MASK               0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_SHIFT              13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS1_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_MOCA_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_MASK                      0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_SHIFT                     6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_UHFR_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:25] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xfe000000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              25
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [24:24] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x01000000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   24
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [23:23] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00800000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               23
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [22:22] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00400000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      22
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB1 [21:21] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_MASK                    0x00200000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_SHIFT                   21
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB1_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: USB0 [20:20] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_MASK                    0x00100000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_SHIFT                   20
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_USB0_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: MOCA [19:19] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_MASK                    0x00080000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_SHIFT                   19
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_MOCA_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [18:18] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00040000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                18
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [17:17] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00020000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    17
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_AFEC [16:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_MASK               0x00010000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_SHIFT              16
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_TFEC [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_MASK               0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_SHIFT              15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_RCVR_1 [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_MASK             0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_SHIFT            14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS1_RCVR_0 [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_MASK             0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_SHIFT            13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS1_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_MOCA [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_MASK                0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_SHIFT               7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_MOCA_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: UHFR [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_UHFR_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_bspi.h b/include/linux/brcmstb/7346b0/bchp_bspi.h
new file mode 100644
index 000000000000..7de27889124b
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:30 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:00p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_bspi_raf.h b/include/linux/brcmstb/7346b0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..30c224429847
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:36:17 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:00p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_clkgen.h b/include/linux/brcmstb/7346b0/bchp_clkgen.h
new file mode 100644
index 000000000000..f5fdf2c599f3
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_clkgen.h
@@ -0,0 +1,6147 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 16:33:38 2011
+ *                 MD5 Checksum         0b9cc5de2a03cabbf9a0a767bc10763a
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/3   5/31/11 5:25p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x00420000 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00420004 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00420008 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x0042000c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00420010 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420014 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0042001c /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x00420020 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00420024 /* Lock Status */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x00420028 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x0042002c /* Resets */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x00420030 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00420034 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00420038 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x0042003c /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x00420040 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420044 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x00420048 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x0042004c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00420050 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00420054 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00420058 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x0042005c /* Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420060 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420064 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420068 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x0042006c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x00420070 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420074 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x00420078 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x0042007c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420080 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420084 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420088 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x00420094 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420098 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x0042009c /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x004200a0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x004200a4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x004200a8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x004200b0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2           0x004200b4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x004200b8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x004200bc /* Test Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x004200c0 /* Resets */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x004200c4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x004200c8 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x004200cc /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004200d0 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004200d4 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004200d8 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004200dc /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004200e0 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004200e4 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x004200e8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004200f0 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x004200f4 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x004200f8 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x004200fc /* Lock Status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x00420100 /* Test Status */
+#define BCHP_CLKGEN_SCRATCH5                     0x00420104 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_SCRATCH3                     0x0042010c /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00420110 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00420114 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00420118 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0042011c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00420120 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00420124 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00420128 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0042012c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420130 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00420134 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00420138 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x0042013c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x00420140 /* Test Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x00420144 /* Resets */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00420148 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x0042014c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x00420150 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x00420154 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x0042015c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00420164 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x00420168 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x0042016c /* Lock Status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00420170 /* Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00420174 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x00420178 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042017c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420180 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420184 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420188 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x0042018c /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420190 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00420194 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00420198 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042019c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x004201a0 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004201a4 /* Test Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x004201a8 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x004201ac /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x004201b0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x004201b4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x004201b8 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x004201bc /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x004201c0 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x004201c4 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 0x004201c8 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x004201cc /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x004201d0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x004201d4 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x004201d8 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x004201dc /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x004201e0 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x004201e4 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x004201e8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x004201ec /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x004201f0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x004201f4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004201f8 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004201fc /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x00420200 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420204 /* Test Status */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x00420208 /* Disable HIF_INST's clocks */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x0042020c /* Memsys 32 inst memory standby enable */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE  0x00420210 /* Disable SDS0_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x00420214 /* Usb1 inst observe clock */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE    0x00420218 /* Ftm top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x0042021c /* Disable VEC_AIO_TOP_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x00420220 /* Usb0 inst memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00420224 /* Graphics inst clock enable */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420228 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x0042022c /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x00420230 /* Disable SYS_CTRL_INST's clocks */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420234 /* Sds0 afec top inst memory standby enable */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION  0x00420238 /* Select observation clk */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x0042023c /* Memsys 32 inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x00420240 /* Usb1 inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x00420244 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420248 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x0042024c /* Disable UHFR_TOP_INST's clocks */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420250 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00420254 /* Disable DVP_HT_INST's clocks */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x00420258 /* Usb0 inst observe clock */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x0042025c /* Disable USB0_INST's clocks */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00420260 /* Disable CORE_XPT_INST's clocks */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00420264 /* Dvp ht inst memory standby enable */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420268 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x0042026c /* Sys aon inst observe clock */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00420270 /* Uhfr top inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420274 /* Dual genet top dual rgmii inst power switch memory a */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00420278 /* Usb0 inst power switch memory */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x0042027c /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x00420280 /* Disable USB1_INST's clocks */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE  0x00420284 /* Disable SDS1_TOP_INST's clocks */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE  0x00420288 /* Disable GRAPHICS_INST's clocks */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE 0x0042028c /* Sds1 afec top inst clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x00420290 /* Vec aio top inst clock enable aio */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420294 /* Sds0 afec top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x00420298 /* Vec aio top inst memory standby enable aio */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0042029c /* Dvp ht inst power switch memory */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x004202a0 /* Dual genet top dual rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x004202a4 /* Dvp ht inst clock enable */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x004202a8 /* Memsys 32 inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT 0x004202ac /* Memsys 32 inst power management */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004202b0 /* Core xpt inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004202b4 /* Core xpt inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004202b8 /* Vec aio top inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x004202bc /* Graphics inst memory standby enable */
+#define BCHP_CLKGEN_SCRATCH7                     0x004202c0 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x004202c4 /* Uhfr top inst observe clock */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x004202c8 /* Dvp ht inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT 0x004202cc /* Dual genet top dual rgmii inst clock select */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004202d0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d4 /* Ftm top inst memory standby enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d8 /* Uhfr top inst memory standby enable */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202dc /* Sds1 afec top inst memory standby enable */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x004202e0 /* Disable ZCPU_TOP_INST's clocks */
+#define BCHP_CLKGEN_SCRATCH6                     0x004202e4 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK 0x004202e8 /* Sds1 receiver inst observe clock */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK 0x004202ec /* Sds1 tfec top inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004202f0 /* Vec aio top inst clock enable */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY 0x004202f4 /* Ftm top inst power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x004202f8 /* Vec aio top inst memory standby enable vec */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x004202fc /* Sds0 afec top inst clock enable */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK 0x00420300 /* Sds0 receiver inst observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00420304 /* Vec aio top inst power switch memory aio */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x00420308 /* Raaga dsp top inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Moca top inst memory standby enable */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x00420310 /* Select observation clk */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420314 /* Svd top inst memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00420318 /* Raaga Dsp top inst observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x0042031c /* Raaga dsp top inst clock enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420320 /* Bvn top inst memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00420324 /* Bvn top inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x00420328 /* Sata3 top inst clock select */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x0042032c /* Vec aio top inst power switch memory vec */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420330 /* Sds1 afec top inst observe clock */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE   0x00420334 /* Sds0  top inst clock enable */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x00420338 /* Usb1 inst power switch memory */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x0042033c /* Usb0 inst clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420340 /* Sata3 top inst memory standby enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x00420344 /* Vec aio top inst clock enable vec */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x00420348 /* Moca top inst observe clock */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x0042034c /* Select observation clk */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420350 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x00420354 /* Memsys 32 inst power switch memory */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00420358 /* Graphics inst power switch memory */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK 0x0042035c /* Sds0 tfec top inst observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00420360 /* Sata3 top inst power switch memory */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE    0x00420364 /* Svd top inst clock enable */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x00420368 /* Hif inst power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x0042036c /* Sata3 top inst clock enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00420370 /* Core xpt inst observe clock */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x00420374 /* Hif inst memory standby enable */
+#define BCHP_CLKGEN_SCRATCH8                     0x00420378 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY 0x0042037c /* Svd top inst power switch memory */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE   0x00420380 /* Sds1 top inst clock enable */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x00420384 /* Uhfr top inst clock enable */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x00420388 /* Sds1 afec top inst power switch memory */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x0042038c /* Usb1 inst clock enable */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE     0x00420390 /* Disable SATA3_TOP_INST's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x00420394 /* Sata3 top inst observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00420398 /* Sys ctrl inst memory standby enable */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x0042039c /* Dual genet top dual rgmii inst observe clock */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004203a0 /* Dual genet top dual rgmii inst clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x004203a4 /* Raaga dsp top inst memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004203a8 /* Core xpt inst power switch memory */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x004203ac /* Select observation clk */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x004203b0 /* Zcpu top inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x004203b4 /* Graphics inst observe clock */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE 0x004203b8 /* Disable GRAPHICS_INST's m2mc clock */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x004203bc /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x004203c0 /* Sds0 afec top inst power switch memory */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x004203c4 /* Sys ctrl inst observe clock */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x004203c8 /* Bvn top inst clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004203cc /* Sys ctrl inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x004203d0 /* Moca top inst power switch memory */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x004203d4 /* Moca top inst clock enable */
+#define BCHP_CLKGEN_SCRATCH4                     0x004203d8 /* clkgen  Scratch register */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS      0x004203dc /* Lock Status */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004203e0 /* pll alive in standby mode */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT             0x004203e4 /* spi clock control */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x004203e8 /* Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks */
+#define BCHP_CLKGEN_SCRATCH2                     0x004203ec /* clkgen  Scratch register */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE 0x004203f0 /* Graphics inst V3D clock enable */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL                0x004203f4 /* Mips PLL Control Register */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x004203f8 /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004203fc /* Resets status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420400 /* Resets status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x00420404 /* Resets status */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00420408 /* Resets status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042040c /* Resets status */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00420410 /* Resets status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420414 /* Resets status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420418 /* Resets status */
+#define BCHP_CLKGEN_TESTPORT                     0x0042041c /* Special Testport Controls */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET           0x00420428 /* Resets */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN           0x0042042c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL         0x00420430 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV             0x00420434 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 0x00420438 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 0x0042043c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 0x00420440 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN            0x00420444 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW 0x00420448 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH 0x0042044c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC            0x00420450 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS     0x00420454 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS          0x00420458 /* Status */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS    0x0042045c /* Resets status */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00420460 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00420464 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00420468 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x0042046c /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x00420470 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00420474 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00420478 /* Power management LDO PLL */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0042047c /* Power management LDO PLL state machine */
+
+/***************************************************************************
+ *PLL_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               3
+
+/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0
+
+/***************************************************************************
+ *PLL_AVD_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AVD_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x00001ff8
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 3
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               142
+
+/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00000007
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     0
+#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x00003fc0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   6
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000007
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       0
+#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x40000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             30
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              29
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x10000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             28
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x08000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               27
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x04000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 26
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x03000000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 24
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x00c00000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                22
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00300000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               20
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00080000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                19
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00040000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               18
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             17
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x0001c000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             14
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00002000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             13
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             1
+
+/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12
+
+/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: LOCK_LOST [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_SHIFT            0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200
+
+/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 36
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_MOCA_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *SCRATCH5 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH5 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH5_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH5_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH5_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *SCRATCH3 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH3 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH3_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH3_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH3_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffe0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 5
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [03:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000008
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 6
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 48
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 10
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 144
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            30
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x20000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x03000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00c00000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00300000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1
+
+/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x00001ff8
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143
+
+/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4
+
+/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [30:30] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x40000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           30
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [29:29] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            29
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [28:28] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x10000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           28
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [27:27] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             27
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x04000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               26
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [25:24] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x03000000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               24
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [23:22] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00c00000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              22
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [21:20] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00300000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             20
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00080000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              19
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00040000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             18
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x00020000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           17
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0001c000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           14
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00002000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           13
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           1
+
+/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12
+
+/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x00001ff8
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  3
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x00003fc0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    6
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x00000007
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x20000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              29
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x06000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x01800000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 23
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00600000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x00100000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             20
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00080000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x00020000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              17
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x0001c000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   12
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 4
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            29
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x10000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x06000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x01800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               23
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x00100000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           20
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         3
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: DDR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *FTM_TOP_INST_CLOCK_ENABLE - Ftm top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH1_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 8
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_EPHY_PLL_INPUT_CLOCK [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_OBSERVE_PLL_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_MASK     0xfffffe00
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_SHIFT    9
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              6
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [05:05] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK [03:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKUSB_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffffc
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            2
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKUSB_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_MASK    0x00000002
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT   1
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000001
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/***************************************************************************
+ *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_FREERUN_CLOCK [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TOP_INST_CLOCK_DISABLE - Disable SDS1_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_CLOCK_ENABLE - Sds1 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_VEC_ENABLE [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_MAX_ENABLE [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_MANAGEMENT - Memsys 32 inst power management
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH7 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH7 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH7_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH7_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH7_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT - Dual genet top dual rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1
+
+/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *FTM_TOP_INST_MEMORY_STANDBY_ENABLE - Ftm top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds1 afec top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1
+
+/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_FUNC_BYP_CLOCK [00:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH6 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH6 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH6_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH6_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH6_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *SDS1_RECEIVER_INST_OBSERVE_CLOCK - Sds1 receiver inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TFEC_TOP_INST_OBSERVE_CLOCK - Sds1 tfec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_ENABLE_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FTM_TOP_INST_POWER_SWITCH_MEMORY - Ftm top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS0_RECEIVER_INST_OBSERVE_CLOCK - Sds0 receiver inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SVD_TOP_INST_MEMORY_STANDBY_ENABLE - Svd top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga Dsp top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_OBSERVE_CLOCK - Sds1 afec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TOP_INST_CLOCK_ENABLE - Sds0  top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1
+
+/***************************************************************************
+ *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: DDR_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_TFEC_TOP_INST_OBSERVE_CLOCK - Sds0 tfec top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_ENABLE_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SVD_TOP_INST_CLOCK_ENABLE - Svd top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffe0
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      5
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH8 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH8 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH8_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH8_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH8_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *SVD_TOP_INST_POWER_SWITCH_MEMORY - Svd top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS1_TOP_INST_CLOCK_ENABLE - Sds1 top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: SDS1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds1 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SATA3_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: DISABLE_27_FUNC_CLK_30 [00:00] */
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_SHIFT 0
+#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_DEFAULT 0
+
+/***************************************************************************
+ *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:16] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 16
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *PAD_VCXO27_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_INST_M2MC_CLOCK_ENABLE - Disable GRAPHICS_INST's m2mc clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:05] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         5
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS1 [04:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_MASK  0x00000010
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_SHIFT 4
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS0 [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_MASK  0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC1 [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FTM [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_DEFAULT 0
+
+/***************************************************************************
+ *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SCRATCH4 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH4 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH4_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH4_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH4_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *PLL_DDR_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT        1
+
+/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR_LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_SHIFT         0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - pll alive in standby mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_MASK                  0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_SHIFT                 2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_DEFAULT               0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/***************************************************************************
+ *SPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: SPI_CLOCK_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_SHIFT               1
+
+/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0
+
+/***************************************************************************
+ *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks
+ ***************************************************************************/
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1
+
+/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
+#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0
+
+/***************************************************************************
+ *SCRATCH2 - clkgen  Scratch register
+ ***************************************************************************/
+/* CLKGEN :: SCRATCH2 :: VALUE [31:00] */
+#define BCHP_CLKGEN_SCRATCH2_VALUE_MASK                            0xffffffff
+#define BCHP_CLKGEN_SCRATCH2_VALUE_SHIFT                           0
+#define BCHP_CLKGEN_SCRATCH2_VALUE_DEFAULT                         0
+
+/***************************************************************************
+ *GRAPHICS_INST_V3D_CLOCK_ENABLE - Graphics inst V3D clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *PLL_MIPS_CTRL - Mips PLL Control Register
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_MASK                   0x80000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_SHIFT                  31
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_RQ [30:30] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_MASK               0x40000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_SHIFT              30
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_DEFAULT            0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_STATE [29:29] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_MASK            0x20000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_SHIFT           29
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_DEFAULT         0
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1
+
+/* union - case normal_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_MASK   0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT  28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_MASK   0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT  27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_MASK    0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT   24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0
+
+/* union - case bypassed_PLL_mode [28:23] */
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:24] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK  0x07000000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 24
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0
+
+/* CLKGEN :: PLL_MIPS_CTRL :: reserved1 [22:00] */
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_MASK                   0x007fffff
+#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_SHIFT                  0
+
+/***************************************************************************
+ *PLL_MIPS_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_DEFAULT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_DEFAULT     1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_SHIFT       1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_DEFAULT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_MASK        0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_SHIFT       0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_DEFAULT     1
+
+/***************************************************************************
+ *PLL_AVD_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_MASK           0x00000002
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_SHIFT          1
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_DEFAULT        1
+
+/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_SHIFT          0
+#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_DEFAULT        1
+
+/***************************************************************************
+ *PLL_MOCA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_RAAGA_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_MASK         0x00000002
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_SHIFT        1
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_DEFAULT      1
+
+/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_SHIFT        0
+#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_DEFAULT      1
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_MASK            0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_SHIFT           1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_DEFAULT         1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_SHIFT           0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_DEFAULT         1
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_AFEC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AFEC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: NDIV_INT [12:03] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_SHIFT                3
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/* CLKGEN :: PLL_AFEC_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_MASK                     0x00000007
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_SHIFT                    0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_DEFAULT                  2
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 4
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/***************************************************************************
+ *PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: MDIV_RELOCK [29:29] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_MASK             0x20000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_SHIFT            29
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: FAST_LOCK [28:28] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_MASK               0x10000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_SHIFT              28
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2 [27:27] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_MASK                 0x08000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_SHIFT                27
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCO_DLY [26:25] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_MASK                 0x06000000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_SHIFT                25
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: PWM_RATE [24:23] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_MASK                0x01800000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_SHIFT               23
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2_POST [20:20] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_MASK            0x00100000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_SHIFT           20
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: AUX_CTRL [19:19] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_MASK                0x00080000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_SHIFT               19
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_UPDATE [17:17] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_MASK             0x00020000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_SHIFT            17
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_SELECT [16:14] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_MASK             0x0001c000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_SHIFT            14
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_RESET_ [13:13] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__MASK             0x00002000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__SHIFT            13
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_AFEC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_AFEC_PLL_RESET_STATUS - Resets status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_MASK          0x00000002
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_SHIFT         1
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_DEFAULT       1
+
+/* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_SHIFT         0
+#define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_DEFAULT       1
+
+/***************************************************************************
+ *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1
+
+/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP - Power management LDO PLL
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SYS1 [03:03] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_MASK     0x00000008
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_SHIFT    3
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1
+
+/***************************************************************************
+ *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200
+
+/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
+#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_common.h b/include/linux/brcmstb/7346b0/bchp_common.h
new file mode 100644
index 000000000000..6350d1b5186a
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_common.h
@@ -0,0 +1,2396 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 31 16:16:36 2011
+ *                 MD5 Checksum         0b9cc5de2a03cabbf9a0a767bc10763a
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/3   5/31/11 5:25p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7346_B0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a3f004 /* XPT_SECURE_BUS_IF is last */
+#define BCHP_REGISTER_SIZE                                 0x0028fc01 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_ILS_REGS_0_REG_START                          0x00070000
+#define BCHP_ILS_REGS_0_REG_END                            0x0007007c
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00070100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0007010c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00070180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00070180
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00070200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0007038c
+#define BCHP_SVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_SVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_SVD_RGR_0_REG_START                           0x00080400
+#define BCHP_SVD_RGR_0_REG_END                             0x00080410
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_START            0x00100000
+#define BCHP_BLD_DECODE_RBNODE_REGS_0_REG_END              0x0010007c
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00100100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001001fc
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_START                   0x00100200
+#define BCHP_BLD_SDRAM_DEBUG_0_REG_END                     0x0010027c
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00100300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0010031c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00100320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0010033c
+#define BCHP_BLD_DECODE_WPRD_0_REG_START                   0x00100340
+#define BCHP_BLD_DECODE_WPRD_0_REG_END                     0x0010035c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00100400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0010045c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00100500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0010057c
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_START               0x00100600
+#define BCHP_BLD_DECODE_VP8_XFRM_0_REG_END                 0x0010060c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00100700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0010071c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00100720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0010073c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00100740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0010075c
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_START                0x00100b00
+#define BCHP_BLD_REG_CABAC2BINS_0_REG_END                  0x00100bfc
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00100c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00100dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00100e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00100efc
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_START                0x00100f00
+#define BCHP_BLD_DECODE_CPUREGS_0_REG_END                  0x00100f7c
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_START               0x00100f80
+#define BCHP_BLD_DECODE_CPUREGS2_0_REG_END                 0x00100ffc
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_START                 0x00101800
+#define BCHP_BLD_DECODE_CPUDMA_0_REG_END                   0x001018fc
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_START                 0x00101a00
+#define BCHP_BLD_DECODE_DMAMEM_0_REG_END                   0x001021fc
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_START               0x00102400
+#define BCHP_BLD_REG_CABAC2BINS2_0_REG_END                 0x001027fc
+#define BCHP_BLD_DECODE_WPTBL_0_REG_START                  0x00103000
+#define BCHP_BLD_DECODE_WPTBL_0_REG_END                    0x001031fc
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_START             0x0010cc00
+#define BCHP_BLD_DECODE_SINT_OLOOP_0_REG_END               0x0010ccfc
+#define BCHP_BLD_DECODE_SD_0_REG_START                     0x00140800
+#define BCHP_BLD_DECODE_SD_0_REG_END                       0x00140ffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_START         0x00141000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS_0_REG_END           0x0014107c
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_START                0x00144000
+#define BCHP_BLD_DECODE_CPUCORE_0_REG_END                  0x00144ffc
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_START                 0x00145000
+#define BCHP_BLD_DECODE_CPUAUX_0_REG_END                   0x00145ffc
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_START                0x00146000
+#define BCHP_BLD_DECODE_CPUIMEM_0_REG_END                  0x00147ffc
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_START                0x00148000
+#define BCHP_BLD_DECODE_CPUDMEM_0_REG_END                  0x0014fffc
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_START        0x00151000
+#define BCHP_BLD_DECODE_IND_SDRAM_REGS2_0_REG_END          0x0015107c
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_START                0x00151800
+#define BCHP_BLD_DECODE_CPUDMA2_0_REG_END                  0x001518fc
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_START                0x00151a00
+#define BCHP_BLD_DECODE_DMAMEM2_0_REG_END                  0x001521fc
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_START               0x00154000
+#define BCHP_BLD_DECODE_CPUCORE2_0_REG_END                 0x00154ffc
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_START                0x00155000
+#define BCHP_BLD_DECODE_CPUAUX2_0_REG_END                  0x00155ffc
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_START               0x00156000
+#define BCHP_BLD_DECODE_CPUIMEM2_0_REG_END                 0x00157ffc
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_START               0x00158000
+#define BCHP_BLD_DECODE_CPUDMEM2_0_REG_END                 0x0015fffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x00160000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x00160084
+#define BCHP_BLD_AVD_CACHE_0_REG_START                     0x00162000
+#define BCHP_BLD_AVD_CACHE_0_REG_END                       0x0016203c
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_DATA_MEM_REG_START                            0x00200000
+#define BCHP_DATA_MEM_REG_END                              0x0023fffc
+#define BCHP_CNTL_MEM_REG_START                            0x00240000
+#define BCHP_CNTL_MEM_REG_END                              0x0025fffc
+#define BCHP_MOCA_DMA_Channel0_REG_START                   0x00280000
+#define BCHP_MOCA_DMA_Channel0_REG_END                     0x0028000c
+#define BCHP_MOCA_DMA_Channel1_REG_START                   0x00280010
+#define BCHP_MOCA_DMA_Channel1_REG_END                     0x0028001c
+#define BCHP_MOCA_DMA_Channel2_REG_START                   0x00280020
+#define BCHP_MOCA_DMA_Channel2_REG_END                     0x0028002c
+#define BCHP_MOCA_DMA_Channel3_REG_START                   0x00280030
+#define BCHP_MOCA_DMA_Channel3_REG_END                     0x0028003c
+#define BCHP_MOCA_DMA_Channel4_REG_START                   0x00280040
+#define BCHP_MOCA_DMA_Channel4_REG_END                     0x0028004c
+#define BCHP_MOCA_DMA_Channel5_REG_START                   0x00280050
+#define BCHP_MOCA_DMA_Channel5_REG_END                     0x0028005c
+#define BCHP_MOCA_DMA_Channel6_REG_START                   0x00280060
+#define BCHP_MOCA_DMA_Channel6_REG_END                     0x0028006c
+#define BCHP_MOCA_MAC_REG_START                            0x00280400
+#define BCHP_MOCA_MAC_REG_END                              0x00280480
+#define BCHP_MOCA_PHY_REG_START                            0x00288000
+#define BCHP_MOCA_PHY_REG_END                              0x0028a9fc
+#define BCHP_MOCA_TRX_REG_START                            0x0028c000
+#define BCHP_MOCA_TRX_REG_END                              0x0028c0d0
+#define BCHP_MOCA_GMII_REG_START                           0x00290000
+#define BCHP_MOCA_GMII_REG_END                             0x00290058
+#define BCHP_MOCA_DMA_Channel_rx_REG_START                 0x00290400
+#define BCHP_MOCA_DMA_Channel_rx_REG_END                   0x0029040c
+#define BCHP_MOCA_DMA_Channel_tx_REG_START                 0x00290410
+#define BCHP_MOCA_DMA_Channel_tx_REG_END                   0x0029041c
+#define BCHP_MOCA_ECL_REG_START                            0x00290800
+#define BCHP_MOCA_ECL_REG_END                              0x00290848
+#define BCHP_MOCA_PRI_REG_START                            0x00292000
+#define BCHP_MOCA_PRI_REG_END                              0x0029207c
+#define BCHP_MOCA_NID_REG_START                            0x00294000
+#define BCHP_MOCA_NID_REG_END                              0x002943fc
+#define BCHP_MOCA_TIMER_0_REG_START                        0x002a0000
+#define BCHP_MOCA_TIMER_0_REG_END                          0x002a0010
+#define BCHP_MOCA_TIMER_1_REG_START                        0x002a0020
+#define BCHP_MOCA_TIMER_1_REG_END                          0x002a0030
+#define BCHP_MOCA_TIMER_2_REG_START                        0x002a0040
+#define BCHP_MOCA_TIMER_2_REG_END                          0x002a0050
+#define BCHP_MOCA_GPIO_REG_START                           0x002a1000
+#define BCHP_MOCA_GPIO_REG_END                             0x002a1018
+#define BCHP_MOCA_EXTRAS_REG_START                         0x002a1400
+#define BCHP_MOCA_EXTRAS_REG_END                           0x002a1494
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x002a2000
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x002a200c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x002a2040
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x002a2064
+#define BCHP_MOCA_L2_REG_START                             0x002a2080
+#define BCHP_MOCA_L2_REG_END                               0x002a20ac
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x002a20c0
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x002a20cc
+#define BCHP_MOCA_HOSTMISC_MMP_REG_START                   0x002a2100
+#define BCHP_MOCA_HOSTMISC_MMP_REG_END                     0x002a212c
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f4
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_START             0x003b6400
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_REG_END               0x003b65b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_TPCAP_REG_START                               0x00400c00
+#define BCHP_TPCAP_REG_END                                 0x00400c84
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_BSCD_REG_START                                0x00406380
+#define BCHP_BSCD_REG_END                                  0x004063d4
+#define BCHP_PWM_REG_START                                 0x00406580
+#define BCHP_PWM_REG_END                                   0x004065a4
+#define BCHP_GIO_REG_START                                 0x00406700
+#define BCHP_GIO_REG_END                                   0x0040675c
+#define BCHP_IRQ0_REG_START                                0x00406780
+#define BCHP_IRQ0_REG_END                                  0x00406784
+#define BCHP_IRQ1_REG_START                                0x00406788
+#define BCHP_IRQ1_REG_END                                  0x0040678c
+#define BCHP_TIMER_REG_START                               0x004067c0
+#define BCHP_TIMER_REG_END                                 0x004067fc
+#define BCHP_PWMB_REG_START                                0x00406800
+#define BCHP_PWMB_REG_END                                  0x00406824
+#define BCHP_UARTA_REG_START                               0x00406900
+#define BCHP_UARTA_REG_END                                 0x0040691c
+#define BCHP_UARTB_REG_START                               0x00406940
+#define BCHP_UARTB_REG_END                                 0x0040695c
+#define BCHP_UARTC_REG_START                               0x00406980
+#define BCHP_UARTC_REG_END                                 0x0040699c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406ac0
+#define BCHP_SCB_REG_END                                   0x00406b7c
+#define BCHP_SCIRQ0_REG_START                              0x00406c40
+#define BCHP_SCIRQ0_REG_END                                0x00406c44
+#define BCHP_SCIRQ1_REG_START                              0x00406c48
+#define BCHP_SCIRQ1_REG_END                                0x00406c4c
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x00406d00
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x00406d2c
+#define BCHP_TMON_REG_START                                0x00406d80
+#define BCHP_TMON_REG_END                                  0x00406dd0
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCE_REG_START                                0x00408980
+#define BCHP_BSCE_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x00412418
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_SDIO_0_HOST_REG_START                         0x00413500
+#define BCHP_SDIO_0_HOST_REG_END                           0x004135fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00413600
+#define BCHP_SDIO_0_CFG_REG_END                            0x004136fc
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_UHFR_REG_START                                0x00416000
+#define BCHP_UHFR_REG_END                                  0x004160f8
+#define BCHP_UHFR_INTR2_REG_START                          0x00416200
+#define BCHP_UHFR_INTR2_REG_END                            0x0041622c
+#define BCHP_UHFR_GR_BRIDGE_REG_START                      0x00416300
+#define BCHP_UHFR_GR_BRIDGE_REG_END                        0x0041630c
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042047c
+#define BCHP_VCXO_RM_REG_START                             0x00422000
+#define BCHP_VCXO_RM_REG_END                               0x0042202c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00422800
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00422874
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00422900
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042291c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00422a00
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00422a18
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00422b00
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x00422bdc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00422c00
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x00422ca4
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00422d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x00422de4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00422e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x00422ee4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00422f00
+#define BCHP_CLKGEN_INTR2_REG_END                          0x00422f2c
+#define BCHP_CLKGEN_GR_REG_START                           0x00423300
+#define BCHP_CLKGEN_GR_REG_END                             0x0042330c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_GENET_1_SYS_REG_START                         0x00438000
+#define BCHP_GENET_1_SYS_REG_END                           0x0043800c
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00438040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x0043804c
+#define BCHP_GENET_1_EXT_REG_START                         0x00438080
+#define BCHP_GENET_1_EXT_REG_END                           0x00438098
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00438200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x0043822c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00438240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x0043826c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00438300
+#define BCHP_GENET_1_RBUF_REG_END                          0x004383ec
+#define BCHP_GENET_1_TBUF_REG_START                        0x00438600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00438628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00438800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00438ed8
+#define BCHP_GENET_1_HFB_REG_START                         0x00439000
+#define BCHP_GENET_1_HFB_REG_END                           0x0043a010
+#define BCHP_GENET_1_RDMA_REG_START                        0x0043b000
+#define BCHP_GENET_1_RDMA_REG_END                          0x0043bcb4
+#define BCHP_GENET_1_TDMA_REG_START                        0x0043c000
+#define BCHP_GENET_1_TDMA_REG_END                          0x0043cc88
+#define BCHP_SID_REG_START                                 0x00440100
+#define BCHP_SID_REG_END                                   0x0044019c
+#define BCHP_SID_RLE_REG_START                             0x00440300
+#define BCHP_SID_RLE_REG_END                               0x0044039c
+#define BCHP_SID_DQ_REG_START                              0x00440400
+#define BCHP_SID_DQ_REG_END                                0x004404bc
+#define BCHP_SID_STRM_REG_START                            0x00440800
+#define BCHP_SID_STRM_REG_END                              0x0044087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00440c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00440c40
+#define BCHP_SID_ARC_REG_START                             0x00440f00
+#define BCHP_SID_ARC_REG_END                               0x00440f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00441800
+#define BCHP_SID_ARCDMA_REG_END                            0x00441840
+#define BCHP_SID_DMARAM_REG_START                          0x00441a00
+#define BCHP_SID_DMARAM_REG_END                            0x00441bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00442b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00442b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00442b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00442b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00443000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x004437fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00443900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x004439fc
+#define BCHP_SID_SYMB_REG_START                            0x00443a00
+#define BCHP_SID_SYMB_REG_END                              0x00443a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00443a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00443a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00448000
+#define BCHP_SID_BIGRAM_REG_END                            0x0044fffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00451000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00451010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00455000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00455014
+#define BCHP_M2MC_REG_START                                0x00460000
+#define BCHP_M2MC_REG_END                                  0x004607fc
+#define BCHP_V3D_CTL_REG_START                             0x00461000
+#define BCHP_V3D_CTL_REG_END                               0x00461040
+#define BCHP_V3D_CLE_REG_START                             0x00461100
+#define BCHP_V3D_CLE_REG_END                               0x00461138
+#define BCHP_V3D_PTB_REG_START                             0x00461300
+#define BCHP_V3D_PTB_REG_END                               0x00461310
+#define BCHP_V3D_QPS_REG_START                             0x00461400
+#define BCHP_V3D_QPS_REG_END                               0x0046143c
+#define BCHP_V3D_VPM_REG_START                             0x00461500
+#define BCHP_V3D_VPM_REG_END                               0x00461504
+#define BCHP_V3D_PCTR_REG_START                            0x00461600
+#define BCHP_V3D_PCTR_REG_END                              0x004616fc
+#define BCHP_V3D_GCA_REG_START                             0x00461a00
+#define BCHP_V3D_GCA_REG_END                               0x00461a54
+#define BCHP_V3D_DBG_REG_START                             0x00461e00
+#define BCHP_V3D_DBG_REG_END                               0x00461f20
+#define BCHP_GFX_L2_REG_START                              0x00463000
+#define BCHP_GFX_L2_REG_END                                0x0046302c
+#define BCHP_GFX_GR_REG_START                              0x00464000
+#define BCHP_GFX_GR_REG_END                                0x0046400c
+#define BCHP_SICH_REG_START                                0x00468000
+#define BCHP_SICH_REG_END                                  0x0046803c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_OTG_REG_START                             0x00482000
+#define BCHP_USB_OTG_REG_END                               0x00482e00
+#define BCHP_USB1_CAPS_REG_START                           0x00490000
+#define BCHP_USB1_CAPS_REG_END                             0x0049002c
+#define BCHP_USB1_GR_BRIDGE_REG_START                      0x00490100
+#define BCHP_USB1_GR_BRIDGE_REG_END                        0x0049010c
+#define BCHP_USB1_INTR2_REG_START                          0x00490180
+#define BCHP_USB1_INTR2_REG_END                            0x004901ac
+#define BCHP_USB1_CTRL_REG_START                           0x00490200
+#define BCHP_USB1_CTRL_REG_END                             0x00490238
+#define BCHP_USB1_EHCI_REG_START                           0x00490300
+#define BCHP_USB1_EHCI_REG_END                             0x004903a4
+#define BCHP_USB1_OHCI_REG_START                           0x00490400
+#define BCHP_USB1_OHCI_REG_END                             0x00490454
+#define BCHP_USB1_EHCI1_REG_START                          0x00490500
+#define BCHP_USB1_EHCI1_REG_END                            0x004905a4
+#define BCHP_USB1_OHCI1_REG_START                          0x00490600
+#define BCHP_USB1_OHCI1_REG_END                            0x00490654
+#define BCHP_USB1_OTG_REG_START                            0x00492000
+#define BCHP_USB1_OTG_REG_END                              0x00492e00
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x00600264
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_VFD_2_REG_START                               0x00601400
+#define BCHP_VFD_2_REG_END                                 0x006015fc
+#define BCHP_VFD_3_REG_START                               0x00601600
+#define BCHP_VFD_3_REG_END                                 0x006017fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_SCL_2_REG_START                               0x00620800
+#define BCHP_SCL_2_REG_END                                 0x00620bfc
+#define BCHP_SCL_3_REG_START                               0x00620c00
+#define BCHP_SCL_3_REG_END                                 0x00620ffc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x006220ac
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222bc
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_LBOX_1_REG_START                              0x00625200
+#define BCHP_LBOX_1_REG_END                                0x00625270
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_CAP_2_REG_START                               0x00640400
+#define BCHP_CAP_2_REG_END                                 0x0064047c
+#define BCHP_CAP_3_REG_START                               0x00640600
+#define BCHP_CAP_3_REG_END                                 0x0064067c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641554
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x006424b4
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x00643420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068009c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_DTRAM_0_REG_START                             0x00683800
+#define BCHP_DTRAM_0_REG_END                               0x00683c7c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684000
+#define BCHP_DVI_DTG_0_REG_END                             0x00684154
+#define BCHP_DVI_CSC_0_REG_START                           0x00684200
+#define BCHP_DVI_CSC_0_REG_END                             0x00684230
+#define BCHP_DVI_DVF_0_REG_START                           0x00684300
+#define BCHP_DVI_DVF_0_REG_END                             0x00684314
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684400
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684444
+#define BCHP_ITU656_DTG_0_REG_START                        0x00684800
+#define BCHP_ITU656_DTG_0_REG_END                          0x00684954
+#define BCHP_ITU656_CSC_0_REG_START                        0x00684a00
+#define BCHP_ITU656_CSC_0_REG_END                          0x00684a30
+#define BCHP_ITU656_DVF_0_REG_START                        0x00684b00
+#define BCHP_ITU656_DVF_0_REG_END                          0x00684b14
+#define BCHP_ITU656_0_REG_START                            0x00684c00
+#define BCHP_ITU656_0_REG_END                              0x00684c20
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x00685100
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686074
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x00687000
+#define BCHP_CCE_ANCIL_0_REG_END                           0x00687054
+#define BCHP_WSE_ANCIL_0_REG_START                         0x00687100
+#define BCHP_WSE_ANCIL_0_REG_END                           0x0068710c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x00687200
+#define BCHP_TTE_ANCIL_0_REG_END                           0x00687228
+#define BCHP_GSE_ANCIL_0_REG_START                         0x00687300
+#define BCHP_GSE_ANCIL_0_REG_END                           0x00687380
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x00687400
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x0068748c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x00687500
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x00687524
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00d4
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_0_REG_START                            0x00700000
+#define BCHP_SDS_CG_0_REG_END                              0x00700038
+#define BCHP_SDS_FE_0_REG_START                            0x00700080
+#define BCHP_SDS_FE_0_REG_END                              0x007000bc
+#define BCHP_SDS_AGC_0_REG_START                           0x00700100
+#define BCHP_SDS_AGC_0_REG_END                             0x00700124
+#define BCHP_SDS_BL_0_REG_START                            0x00700140
+#define BCHP_SDS_BL_0_REG_END                              0x00700160
+#define BCHP_SDS_CL_0_REG_START                            0x00700180
+#define BCHP_SDS_CL_0_REG_END                              0x007001fc
+#define BCHP_SDS_EQ_0_REG_START                            0x00700200
+#define BCHP_SDS_EQ_0_REG_END                              0x0070028c
+#define BCHP_SDS_HP_0_REG_START                            0x00700300
+#define BCHP_SDS_HP_0_REG_END                              0x007003d4
+#define BCHP_SDS_VIT_0_REG_START                           0x00700400
+#define BCHP_SDS_VIT_0_REG_END                             0x00700428
+#define BCHP_SDS_FEC_0_REG_START                           0x00700440
+#define BCHP_SDS_FEC_0_REG_END                             0x00700454
+#define BCHP_SDS_OI_0_REG_START                            0x00700480
+#define BCHP_SDS_OI_0_REG_END                              0x007004c8
+#define BCHP_SDS_SNR_0_REG_START                           0x00700500
+#define BCHP_SDS_SNR_0_REG_END                             0x00700518
+#define BCHP_SDS_BERT_0_REG_START                          0x00700540
+#define BCHP_SDS_BERT_0_REG_END                            0x0070055c
+#define BCHP_SDS_DFT_0_REG_START                           0x00700580
+#define BCHP_SDS_DFT_0_REG_END                             0x007005a8
+#define BCHP_SDS_CWC_0_REG_START                           0x00700600
+#define BCHP_SDS_CWC_0_REG_END                             0x00700694
+#define BCHP_SDS_MISC_0_REG_START                          0x00700700
+#define BCHP_SDS_MISC_0_REG_END                            0x00700798
+#define BCHP_SDS_DSEC_0_REG_START                          0x00700800
+#define BCHP_SDS_DSEC_0_REG_END                            0x007008c8
+#define BCHP_SDS_TUNER_0_REG_START                         0x00700900
+#define BCHP_SDS_TUNER_0_REG_END                           0x007009fc
+#define BCHP_SDS_INTR2_0_0_REG_START                       0x00700a00
+#define BCHP_SDS_INTR2_0_0_REG_END                         0x00700a2c
+#define BCHP_SDS_INTR2_1_0_REG_START                       0x00700b00
+#define BCHP_SDS_INTR2_1_0_REG_END                         0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_0_REG_START                     0x00700c00
+#define BCHP_SDS_GR_BRIDGE_0_REG_END                       0x00700c0c
+#define BCHP_SDS_CG_1_REG_START                            0x00701000
+#define BCHP_SDS_CG_1_REG_END                              0x00701038
+#define BCHP_SDS_FE_1_REG_START                            0x00701080
+#define BCHP_SDS_FE_1_REG_END                              0x007010bc
+#define BCHP_SDS_AGC_1_REG_START                           0x00701100
+#define BCHP_SDS_AGC_1_REG_END                             0x00701124
+#define BCHP_SDS_BL_1_REG_START                            0x00701140
+#define BCHP_SDS_BL_1_REG_END                              0x00701160
+#define BCHP_SDS_CL_1_REG_START                            0x00701180
+#define BCHP_SDS_CL_1_REG_END                              0x007011fc
+#define BCHP_SDS_EQ_1_REG_START                            0x00701200
+#define BCHP_SDS_EQ_1_REG_END                              0x0070128c
+#define BCHP_SDS_HP_1_REG_START                            0x00701300
+#define BCHP_SDS_HP_1_REG_END                              0x007013d4
+#define BCHP_SDS_VIT_1_REG_START                           0x00701400
+#define BCHP_SDS_VIT_1_REG_END                             0x00701428
+#define BCHP_SDS_FEC_1_REG_START                           0x00701440
+#define BCHP_SDS_FEC_1_REG_END                             0x00701454
+#define BCHP_SDS_OI_1_REG_START                            0x00701480
+#define BCHP_SDS_OI_1_REG_END                              0x007014c8
+#define BCHP_SDS_SNR_1_REG_START                           0x00701500
+#define BCHP_SDS_SNR_1_REG_END                             0x00701518
+#define BCHP_SDS_BERT_1_REG_START                          0x00701540
+#define BCHP_SDS_BERT_1_REG_END                            0x0070155c
+#define BCHP_SDS_DFT_1_REG_START                           0x00701580
+#define BCHP_SDS_DFT_1_REG_END                             0x007015a8
+#define BCHP_SDS_CWC_1_REG_START                           0x00701600
+#define BCHP_SDS_CWC_1_REG_END                             0x00701694
+#define BCHP_SDS_MISC_1_REG_START                          0x00701700
+#define BCHP_SDS_MISC_1_REG_END                            0x00701798
+#define BCHP_SDS_DSEC_1_REG_START                          0x00701800
+#define BCHP_SDS_DSEC_1_REG_END                            0x007018c8
+#define BCHP_SDS_TUNER_1_REG_START                         0x00701900
+#define BCHP_SDS_TUNER_1_REG_END                           0x007019fc
+#define BCHP_SDS_INTR2_0_1_REG_START                       0x00701a00
+#define BCHP_SDS_INTR2_0_1_REG_END                         0x00701a2c
+#define BCHP_SDS_INTR2_1_1_REG_START                       0x00701b00
+#define BCHP_SDS_INTR2_1_1_REG_END                         0x00701b2c
+#define BCHP_SDS_GR_BRIDGE_1_REG_START                     0x00701c00
+#define BCHP_SDS_GR_BRIDGE_1_REG_END                       0x00701c0c
+#define BCHP_TFEC_0_REG_START                              0x00702000
+#define BCHP_TFEC_0_REG_END                                0x00702060
+#define BCHP_TFEC_MISC_0_REG_START                         0x00702100
+#define BCHP_TFEC_MISC_0_REG_END                           0x00702108
+#define BCHP_TFEC_INTR2_0_REG_START                        0x00702200
+#define BCHP_TFEC_INTR2_0_REG_END                          0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_0_REG_START                    0x00702300
+#define BCHP_TFEC_GR_BRIDGE_0_REG_END                      0x0070230c
+#define BCHP_TFEC_1_REG_START                              0x00703000
+#define BCHP_TFEC_1_REG_END                                0x00703060
+#define BCHP_TFEC_MISC_1_REG_START                         0x00703100
+#define BCHP_TFEC_MISC_1_REG_END                           0x00703108
+#define BCHP_TFEC_INTR2_1_REG_START                        0x00703200
+#define BCHP_TFEC_INTR2_1_REG_END                          0x0070322c
+#define BCHP_TFEC_GR_BRIDGE_1_REG_START                    0x00703300
+#define BCHP_TFEC_GR_BRIDGE_1_REG_END                      0x0070330c
+#define BCHP_AFEC_0_REG_START                              0x00704000
+#define BCHP_AFEC_0_REG_END                                0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_0_REG_START                   0x00704800
+#define BCHP_AFEC_INTR_CTRL2_0_REG_END                     0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_0_REG_START                    0x00704900
+#define BCHP_AFEC_GR_BRIDGE_0_REG_END                      0x0070490c
+#define BCHP_AFEC_GLOBAL_0_REG_START                       0x00704a00
+#define BCHP_AFEC_GLOBAL_0_REG_END                         0x00704a0c
+#define BCHP_AFEC_1_REG_START                              0x00705000
+#define BCHP_AFEC_1_REG_END                                0x007053fc
+#define BCHP_AFEC_INTR_CTRL2_1_REG_START                   0x00705800
+#define BCHP_AFEC_INTR_CTRL2_1_REG_END                     0x0070582c
+#define BCHP_AFEC_GR_BRIDGE_1_REG_START                    0x00705900
+#define BCHP_AFEC_GR_BRIDGE_1_REG_END                      0x0070590c
+#define BCHP_AFEC_GLOBAL_1_REG_START                       0x00705a00
+#define BCHP_AFEC_GLOBAL_1_REG_END                         0x00705a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001a0
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00208
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a057fc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a07000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a07074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a07080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a070f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a07100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a07174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a07180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a071f4
+#define BCHP_XPT_DPCR4_REG_START                           0x00a07200
+#define BCHP_XPT_DPCR4_REG_END                             0x00a07274
+#define BCHP_XPT_DPCR5_REG_START                           0x00a07280
+#define BCHP_XPT_DPCR5_REG_END                             0x00a072f4
+#define BCHP_XPT_DPCR6_REG_START                           0x00a07300
+#define BCHP_XPT_DPCR6_REG_END                             0x00a07374
+#define BCHP_XPT_DPCR7_REG_START                           0x00a07380
+#define BCHP_XPT_DPCR7_REG_END                             0x00a073f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a07400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a07404
+#define BCHP_XPT_PSUB_REG_START                            0x00a07a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a07ac8
+#define BCHP_XPT_MPOD_REG_START                            0x00a07c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a07c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a07d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a07d08
+#define BCHP_XPT_RMX1_REG_START                            0x00a07e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a07e08
+#define BCHP_XPT_PB_TOP_REG_START                          0x00a08000
+#define BCHP_XPT_PB_TOP_REG_END                            0x00a08084
+#define BCHP_XPT_PB0_REG_START                             0x00a08100
+#define BCHP_XPT_PB0_REG_END                               0x00a08174
+#define BCHP_XPT_PB1_REG_START                             0x00a08180
+#define BCHP_XPT_PB1_REG_END                               0x00a081f4
+#define BCHP_XPT_PB2_REG_START                             0x00a08200
+#define BCHP_XPT_PB2_REG_END                               0x00a08274
+#define BCHP_XPT_PB3_REG_START                             0x00a08280
+#define BCHP_XPT_PB3_REG_END                               0x00a082f4
+#define BCHP_XPT_PB4_REG_START                             0x00a08300
+#define BCHP_XPT_PB4_REG_END                               0x00a08374
+#define BCHP_XPT_PB5_REG_START                             0x00a08380
+#define BCHP_XPT_PB5_REG_END                               0x00a083f4
+#define BCHP_XPT_PB6_REG_START                             0x00a08400
+#define BCHP_XPT_PB6_REG_END                               0x00a08474
+#define BCHP_XPT_PB7_REG_START                             0x00a08480
+#define BCHP_XPT_PB7_REG_END                               0x00a084f4
+#define BCHP_XPT_PB8_REG_START                             0x00a08500
+#define BCHP_XPT_PB8_REG_END                               0x00a08574
+#define BCHP_XPT_PB9_REG_START                             0x00a08580
+#define BCHP_XPT_PB9_REG_END                               0x00a085f4
+#define BCHP_XPT_PB10_REG_START                            0x00a08600
+#define BCHP_XPT_PB10_REG_END                              0x00a08674
+#define BCHP_XPT_PB11_REG_START                            0x00a08680
+#define BCHP_XPT_PB11_REG_END                              0x00a086f4
+#define BCHP_XPT_PB12_REG_START                            0x00a08700
+#define BCHP_XPT_PB12_REG_END                              0x00a08774
+#define BCHP_XPT_PB13_REG_START                            0x00a08780
+#define BCHP_XPT_PB13_REG_END                              0x00a087f4
+#define BCHP_XPT_PB14_REG_START                            0x00a08800
+#define BCHP_XPT_PB14_REG_END                              0x00a08874
+#define BCHP_XPT_PB15_REG_START                            0x00a08880
+#define BCHP_XPT_PB15_REG_END                              0x00a088f4
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a0c000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0d8fc
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a12050
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a15000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a15b44
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a16000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a17ccc
+#define BCHP_XPT_MSG_REG_START                             0x00a18000
+#define BCHP_XPT_MSG_REG_END                               0x00a1e014
+#define BCHP_XPT_RAVE_REG_START                            0x00a20000
+#define BCHP_XPT_RAVE_REG_END                              0x00a2c79c
+#define BCHP_XPT_XPU_REG_START                             0x00a30000
+#define BCHP_XPT_XPU_REG_END                               0x00a347fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a3f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a3f000
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *GFD_1
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_1 :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK    0xffffffff
+#define BCHP_GFD_1_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT   0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: PUSH_PARTIAL_PACKET [28:28] */
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_MASK                0x10000000
+#define BCHP_XPT_PB_DESC_2_PUSH_PARTIAL_PACKET_SHIFT               28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved0 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *DESC_4 - Playback Linked-List Descriptor Word 4
+ ***************************************************************************/
+/* XPT_PB :: DESC_4 :: reserved0 [31:00] */
+#define BCHP_XPT_PB_DESC_4_reserved0_MASK                          0xffffffff
+#define BCHP_XPT_PB_DESC_4_reserved0_SHIFT                         0
+
+/***************************************************************************
+ *DESC_5 - Playback Linked-List Descriptor Word 5
+ ***************************************************************************/
+/* XPT_PB :: DESC_5 :: reserved0 [31:03] */
+#define BCHP_XPT_PB_DESC_5_reserved0_MASK                          0xfffffff8
+#define BCHP_XPT_PB_DESC_5_reserved0_SHIFT                         3
+
+/* XPT_PB :: DESC_5 :: RANDOM_ACCESS_INDICATION [02:02] */
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_MASK           0x00000004
+#define BCHP_XPT_PB_DESC_5_RANDOM_ACCESS_INDICATION_SHIFT          2
+
+/* XPT_PB :: DESC_5 :: NEXT_PACKET_PACING_TIMESTAMP_VALID [01:01] */
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_MASK 0x00000002
+#define BCHP_XPT_PB_DESC_5_NEXT_PACKET_PACING_TIMESTAMP_VALID_SHIFT 1
+
+/* XPT_PB :: DESC_5 :: PKT2PKT_PACING_TIMESTAMP_DELTA_VALID [00:00] */
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_MASK 0x00000001
+#define BCHP_XPT_PB_DESC_5_PKT2PKT_PACING_TIMESTAMP_DELTA_VALID_SHIFT 0
+
+/***************************************************************************
+ *DESC_6 - Playback Linked-List Descriptor Word 6
+ ***************************************************************************/
+/* XPT_PB :: DESC_6 :: NEXT_PACKET_PACING_TIMESTAMP [31:00] */
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_MASK       0xffffffff
+#define BCHP_XPT_PB_DESC_6_NEXT_PACKET_PACING_TIMESTAMP_SHIFT      0
+
+/***************************************************************************
+ *DESC_7 - Playback Linked-List Descriptor Word 7
+ ***************************************************************************/
+/* XPT_PB :: DESC_7 :: PKT2PKT_PACING_TIMESTAMP_DELTA [31:00] */
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_MASK     0xffffffff
+#define BCHP_XPT_PB_DESC_7_PKT2PKT_PACING_TIMESTAMP_DELTA_SHIFT    0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..3da72416b179
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1513 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:22 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:13p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       5
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..44e513d3f647
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:28:33 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:14p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h
new file mode 100644
index 000000000000..9cd00d499cb8
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ddr40_phy_word_lane_1_0.h
@@ -0,0 +1,139 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:16:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:14p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_ebi.h b/include/linux/brcmstb/7346b0/bchp_ebi.h
new file mode 100644
index 000000000000..4da641f76883
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_ebi.h
@@ -0,0 +1,1711 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:14:00 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:31p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00410828 /* EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x0041082c /* EBI CS Config 5 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00410854 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_5 - EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffc0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   6
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..bcae0dcdcb18
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1835 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:23:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:50p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK        0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT       28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK  0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK        0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT       22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK       0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT      3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK      0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT     2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          22
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK  0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK      0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT     28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK      0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT     22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK    0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT   2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xffc00000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      22
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h b/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h
new file mode 100644
index 000000000000..c7c393acc9db
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_cpu_tp1_intr1.h
@@ -0,0 +1,1835 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:08 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
+#define BCHP_HIF_CPU_TP1_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00411600 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00411604 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00411608 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041160c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00411610 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00411614 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00411618 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0041161c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00411620 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00411624 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00411628 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041162c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK    0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT   19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_MASK  0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MEMC0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK    0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT   13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK  0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK  0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_TFEC_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_1_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_RCVR_0_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS1_AFEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS1_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:22] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xffc00000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  22
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_intr2.h b/include/linux/brcmstb/7346b0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..e794d4373616
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_intr2.h
@@ -0,0 +1,1035 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:18:50 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK          0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT         19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_DEFAULT       0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00007ffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK             0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT            19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00007ffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00007ffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK     0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT    19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK     0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT    15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_DEFAULT  1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK        0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT       19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK        0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT       15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK      0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT     15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00007ffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_mspi.h b/include/linux/brcmstb/7346b0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..105201547923
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:20:45 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..498fe388f5dd
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:04 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 3:54p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_irq0.h b/include/linux/brcmstb/7346b0/bchp_irq0.h
new file mode 100644
index 000000000000..09e162962185
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_irq0.h
@@ -0,0 +1,227 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Thu Sep 29 16:50:59 2011
+ *                 MD5 Checksum         8155245fdf91c26162667953fda076c2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   9/30/11 10:50a pntruong
+ * SW7346-170: Resync with central RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406780 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406784 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:28] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf0000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            28
+
+/* IRQ0 :: IRQEN :: iicd_irqen [27:27] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x08000000
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           27
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:28] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf0000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          28
+
+/* IRQ0 :: IRQSTAT :: iicdirq [27:27] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x08000000
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            27
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_irq1.h b/include/linux/brcmstb/7346b0/bchp_irq1.h
new file mode 100644
index 000000000000..2ec0b49d9a17
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:16:18 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 6:34p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406788 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x0040678c /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h b/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..3ac5ec0d28fe
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:23:22 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:30p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..defb72385c72
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:54:00 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:32p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h b/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h
new file mode 100644
index 000000000000..3bc447e7dc81
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_moca_hostmisc.h
@@ -0,0 +1,195 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:17:58 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_moca_hostmisc.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:45p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MOCA_HOSTMISC_H__
+#define BCHP_MOCA_HOSTMISC_H__
+
+/***************************************************************************
+ *MOCA_HOSTMISC - MOCA_HOSTMISC registers
+ ***************************************************************************/
+#define BCHP_MOCA_HOSTMISC_SW_RESET              0x002a2040 /* Moca Software Reset */
+#define BCHP_MOCA_HOSTMISC_SCRATCH               0x002a2044 /* Moca Scratch Register */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG      0x002a204c /* MoCA version register */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0             0x002a2050 /* Moca Host Messaging Register 0 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1             0x002a2054 /* Moca Host Messaging Register 1 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2             0x002a2058 /* Moca Host Messaging Register 2 */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3             0x002a205c /* Moca Host Messaging Register 3 */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG          0x002a2060 /* Host-to-MoCA Interrupt Trigger */
+#define BCHP_MOCA_HOSTMISC_WAKEUP                0x002a2064 /* Host-to-MoCA Wakeup Interrupt */
+
+/***************************************************************************
+ *SW_RESET - Moca Software Reset
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SW_RESET :: spare_control [31:15] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_MASK             0xffff8000
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_SHIFT            15
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_control_DEFAULT          131071
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_status [14:08] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_MASK              0x00007f00
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_SHIFT             8
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_status_DEFAULT           127
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_disable_clocks [07:07] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_MASK       0x00000080
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_SHIFT      7
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_disable_clocks_DEFAULT    0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset2 [06:04] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_MASK              0x00000070
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_SHIFT             4
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset2_DEFAULT           7
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_gmii_sw_init [03:03] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_MASK         0x00000008
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_SHIFT        3
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_gmii_sw_init_DEFAULT      0
+
+/* MOCA_HOSTMISC :: SW_RESET :: spare_reset [02:02] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_MASK               0x00000004
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_SHIFT              2
+#define BCHP_MOCA_HOSTMISC_SW_RESET_spare_reset_DEFAULT            1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_sys_reset [01:01] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_MASK            0x00000002
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_SHIFT           1
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_sys_reset_DEFAULT         1
+
+/* MOCA_HOSTMISC :: SW_RESET :: moca_cpu_reset [00:00] */
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_MASK            0x00000001
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_SHIFT           0
+#define BCHP_MOCA_HOSTMISC_SW_RESET_moca_cpu_reset_DEFAULT         1
+
+/***************************************************************************
+ *SCRATCH - Moca Scratch Register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: SCRATCH :: VALUE [31:00] */
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_SCRATCH_VALUE_DEFAULT                   0
+
+/***************************************************************************
+ *MOCA_VERSION_REG - MoCA version register
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_id [31:16] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_MASK           0xffff0000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_SHIFT          16
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_id_DEFAULT        26146
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: moca_spec_ver [15:12] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_MASK     0x0000f000
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_SHIFT    12
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_moca_spec_ver_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_version [11:08] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_MASK      0x00000f00
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_SHIFT     8
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_version_DEFAULT   1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_revision [07:04] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_MASK     0x000000f0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_SHIFT    4
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_revision_DEFAULT  1
+
+/* MOCA_HOSTMISC :: MOCA_VERSION_REG :: core_mask [03:00] */
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_MASK         0x0000000f
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_SHIFT        0
+#define BCHP_MOCA_HOSTMISC_MOCA_VERSION_REG_core_mask_DEFAULT      0
+
+/***************************************************************************
+ *HOST_MMP0 - Moca Host Messaging Register 0
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP0 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP0_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP1 - Moca Host Messaging Register 1
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP1 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP1_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP2 - Moca Host Messaging Register 2
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP2 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP2_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *HOST_MMP3 - Moca Host Messaging Register 3
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: HOST_MMP3 :: MMP [31:00] */
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_MASK                      0xffffffff
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_SHIFT                     0
+#define BCHP_MOCA_HOSTMISC_HOST_MMP3_MMP_DEFAULT                   0
+
+/***************************************************************************
+ *H2M_INT_TRIG - Host-to-MoCA Interrupt Trigger
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: reserved0 [31:08] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_MASK             0xffffff00
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_reserved0_SHIFT            8
+
+/* MOCA_HOSTMISC :: H2M_INT_TRIG :: INT_TRIG [07:00] */
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_MASK              0x000000ff
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_SHIFT             0
+#define BCHP_MOCA_HOSTMISC_H2M_INT_TRIG_INT_TRIG_DEFAULT           0
+
+/***************************************************************************
+ *WAKEUP - Host-to-MoCA Wakeup Interrupt
+ ***************************************************************************/
+/* MOCA_HOSTMISC :: WAKEUP :: reserved0 [31:01] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_MASK                   0xfffffffe
+#define BCHP_MOCA_HOSTMISC_WAKEUP_reserved0_SHIFT                  1
+
+/* MOCA_HOSTMISC :: WAKEUP :: wakeup_int [00:00] */
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_MASK                  0x00000001
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_SHIFT                 0
+#define BCHP_MOCA_HOSTMISC_WAKEUP_wakeup_int_DEFAULT               0
+
+#endif /* #ifndef BCHP_MOCA_HOSTMISC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_nand.h b/include/linux/brcmstb/7346b0/bchp_nand.h
new file mode 100644
index 000000000000..37c451baabeb
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_nand.h
@@ -0,0 +1,2486 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:29:45 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 4:51p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x00412910 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS5                     0x00412914 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x00412918 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x0041291c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS5 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS5_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h
new file mode 100644
index 000000000000..b54f228bb228
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:12:38 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:55p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           1
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..1ac557f0f910
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sdio_0_cfg.h
@@ -0,0 +1,589 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue May 24 13:15:22 2011
+ *                 MD5 Checksum         20406eb4287081a441630135cf8f15e2
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sdio_0_cfg.h $
+ * 
+ * Hydra_Software_Devel/2   5/24/11 5:55p albertl
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00413600 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00413604 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00413608 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041360c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00413610 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00413614 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00413618 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041361c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00413620 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00413630 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00413634 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004136fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004136f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        1
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           4
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              1
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        1
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             1
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    1
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 100
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          1
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              50
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  1
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            2
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            10
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   1
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   2
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 3
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     1
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                5
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                5
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               3
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     48
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    67
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        160
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    1
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..d6e212be5016
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6596 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  8 22:03:23 2011
+ *                 MD5 Checksum         311e89d3d4fe94a8e2842dfaef9c3871
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   8/9/11 2:40p pntruong
+ * SW7346-143: Updated to match RDB.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x00404178 /* Pad pull-up/pull-down control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12    0x0040417c /* Pad pull-up/pull-down control register 12 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404180 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1933967376
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1933967376
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xfffff800
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            11
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 1
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [09:06] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000003c0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   10
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_cpu_freq [05:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_MASK        0x00000030
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_DEFAULT     0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spare0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spare0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_pad_config [01:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_MASK  0x00000003
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_pad_config_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_xcore_bias [04:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_MASK 0x0000001c
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_xcore_bias_DEFAULT 2
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xtal_enable_ext_cml [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xtal_enable_ext_cml_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_out_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_out_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet0_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_svc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_svc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uhf_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec0_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc0_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec1_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb23_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb01_otg_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_genet1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_genet1_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_out_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_out_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet0_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_svc_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_svc_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uhf_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner1_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner1_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner1_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner0_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner0_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner0_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec0_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec0_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec0_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc0_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc0_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc0_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec1_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec1_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec1_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc1_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb23_otg_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb23_otg_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb01_otg_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb01_otg_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_genet1_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_genet1_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT  0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb1_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb1_mode_DEFAULT         0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT         0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xfffc0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   18
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: sdio_pad_amp_en [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: sdio_pad_slew [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_sdio_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_1 [15:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_1_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_slew [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [11:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_rx_pad_amp_en [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_tx_pad_amp_en [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_slew [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_0 [06:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_0_HSTL_CLASS1_1P8V 3
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_rx_pad_amp_en [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_rx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_tx_pad_amp_en [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_tx_pad_amp_en_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_slew [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_slew_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_GMII_CMOS_3P3V 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_RGMII_CMOS_2P5V 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P5V 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_HSTL_CLASS1_1P8V 3
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: mii_col [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_MII_COL           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SDS1_PKTP_DAT_4   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_col_SDS0_PKTP_DAT_4   2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: mii_rxer [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_MII_RXER         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SDS1_PKTP_DAT_3  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_SDS0_PKTP_DAT_3  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_mii_rxer_TP_IN_30         3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxctl [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_RGMII_RXCTL   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SDS1_PKTP_DAT_2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_SDS0_PKTP_DAT_2 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxctl_ALT_TP_IN_01  3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxclk [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_MASK          0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SHIFT         16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_RGMII_RXCLK   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SDS1_PKTP_DAT_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_SDS0_PKTP_DAT_1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxclk_TP_IN_26      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_03 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_MASK         0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SHIFT        12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_RGMII_RXD_03 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SDS1_PKTP_DAT_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_SDS0_PKTP_DAT_0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_03_TP_IN_25     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_02 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_RGMII_RXD_02 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SDS1_PKTP_SYNC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_SDS0_PKTP_SYNC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_02_TP_IN_31     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_01 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_RGMII_RXD_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SDS1_PKTP_VALID 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_SDS0_PKTP_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_01_ALT_TP_IN_00 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rgmii_rxd_00 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_MASK         0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_RGMII_RXD_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SDS1_PKTP_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_SDS0_PKTP_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rgmii_rxd_00_ALT_TP_OUT_25 3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_EBI_DATA0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data0_ALT_TP_OUT_23   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: mii_txer [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_MII_TXER         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_txer_UART_TXD_2       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txctl [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_MASK          0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_SHIFT         20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_RGMII_TXCTL   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txctl_UART_RTS_1    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_03 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_MASK         0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_RGMII_TXD_03 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_03_UART_RTS_2   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_02 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_MASK         0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_SHIFT        12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_RGMII_TXD_02 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_02_UART_TXD_1   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_01 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_RGMII_TXD_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_01_UART_RTS_0   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: rgmii_txd_00 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_MASK         0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_SHIFT        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_RGMII_TXD_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_rgmii_txd_00_UART_TXD_0   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: mii_crs [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_MII_CRS           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_mii_crs_TP_IN_24          1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data8 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_EBI_DATA8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data8_ALT_TP_IN_08    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data7 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_EBI_DATA7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data7_ALT_TP_IN_07    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data6 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_EBI_DATA6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data6_ALT_TP_IN_06    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data5 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_EBI_DATA5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data5_ALT_TP_IN_05    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data4 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_EBI_DATA4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data4_ALT_TP_IN_04    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data3 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_EBI_DATA3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data3_ALT_TP_IN_03    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data2 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_EBI_DATA2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data2_ALT_TP_IN_02    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_EBI_DATA1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data1_ALT_TP_OUT_24   1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_EBI_ADDR0       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr0_ALT_TP_IN_16    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data15 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_EBI_DATA15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data15_ALT_TP_IN_15   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data14 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_EBI_DATA14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data14_ALT_TP_IN_14   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data13 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_EBI_DATA13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data13_ALT_TP_IN_13   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data12 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_EBI_DATA12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data12_ALT_TP_IN_12   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data11 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_EBI_DATA11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data11_ALT_TP_IN_11   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data10 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_EBI_DATA10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data10_ALT_TP_IN_10   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_data9 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_EBI_DATA9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_data9_ALT_TP_IN_09    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr8 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_EBI_ADDR8       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr8_ALT_TP_IN_24    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr7 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_EBI_ADDR7       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr7_ALT_TP_IN_23    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr6 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_EBI_ADDR6       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr6_ALT_TP_IN_22    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr5 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_EBI_ADDR5       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr5_ALT_TP_IN_21    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr4 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_EBI_ADDR4       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr4_ALT_TP_IN_20    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr3 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_EBI_ADDR3       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr3_ALT_TP_IN_19    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr2 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_EBI_ADDR2       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr2_ALT_TP_IN_18    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_EBI_ADDR1       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr1_ALT_TP_IN_17    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr16 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_EBI_ADDR16     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr16_ALT_TP_OUT_11  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr15 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_EBI_ADDR15     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr15_ALT_TP_IN_31   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr14 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_EBI_ADDR14     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr14_ALT_TP_IN_30   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr13 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_MASK           0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_SHIFT          16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_EBI_ADDR13     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr13_ALT_TP_IN_29   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr12 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_EBI_ADDR12     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr12_ALT_TP_IN_28   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr11 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_EBI_ADDR11     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr11_ALT_TP_IN_27   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr10 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_EBI_ADDR10     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr10_ALT_TP_OUT_10  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr9 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_EBI_ADDR9       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr9_ALT_TP_IN_25    1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr23 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_SHIFT          28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_EBI_ADDR23     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr23_ALT_TP_OUT_02  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr22 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_MASK           0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_SHIFT          24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_EBI_ADDR22     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr22_ALT_TP_OUT_01  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr21 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_MASK           0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_SHIFT          20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_EBI_ADDR21     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr21_ALT_TP_OUT_00  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_waitb [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_EBI_WAITB       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_waitb_ALT_TP_OUT_03   1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr20 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_MASK           0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_SHIFT          12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_EBI_ADDR20     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr20_ALT_TP_OUT_31  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr19 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_MASK           0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_EBI_ADDR19     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr19_ALT_TP_OUT_30  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr18 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_EBI_ADDR18     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr18_ALT_TP_OUT_29  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_addr17 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_MASK           0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_EBI_ADDR17     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_addr17_ALT_TP_OUT_28  1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_004 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_GPIO_004         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_CODEC_FSYNCB     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_EXT_IRQB_13      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_UART_TXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_PM_GPIO_004      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_003 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_GPIO_003         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_CODEC_SCLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_UART_RTS_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_PM_GPIO_003      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_002 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_GPIO_002         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_CODEC_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_UART_CTS_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_P1_INTR_0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_ALT_TP_OUT_04    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_PM_GPIO_002      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_001 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_GPIO_001         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_IR_IN1           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PWM_1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_EXT_IRQB_6       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_AUD_FS_CLK1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_TP_OUT_18        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PM_GPIO_001      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_000 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_GPIO_000         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_IR_INT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PWM_0            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_EXT_IRQB_5       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_AUD_FS_CLK0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_TP_OUT_17        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PM_GPIO_000      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: usb_clkout25 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_MASK         0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_DEFAULT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_USB_CLKOUT25 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_usb_clkout25_MDIO_SATA    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_addr25 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_EBI_ADDR25     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_addr25_ALT_TP_OUT_14  1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_cs4b [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_EBI_CS4B         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_cs4b_MDCLK            1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_012 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_GPIO_012         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_TP_IN_09         2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_011 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_GPIO_011         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_TP_OUT_28        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_010 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_GPIO_010         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_TP_IN_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_PM_GPIO_010      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_009 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_GPIO_009         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_TP_OUT_26        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_PM_GPIO_009      3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_008 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_GPIO_008         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TNR0_TST_MISO    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TP_OUT_25        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_007 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GPIO_007         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GENET0_LINK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GENET1_LINK      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_EXT_IRQB_8       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_UART_RTS_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_TP_IN_05         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_PM_GPIO_007      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_006 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GPIO_006         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GENET0_ACTIVITY  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GENET1_ACTIVITY  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_EXT_IRQB_7       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_UART_TXD_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_TP_OUT_01        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_PM_GPIO_006      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_005 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_GPIO_005         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_CODEC_MCLK       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_EXT_IRQB_14      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_UART_RXD_0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_PM_GPIO_005      4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_020 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_GPIO_020         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_UART_RTS_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_EXT_IRQB_12      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_LED_LS_3         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PKT_SYNC3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_VEC_VSYNC_0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SC0_AUX_2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_TP_OUT_20        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PM_GPIO_020      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_019 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_GPIO_019         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_UART_CTS_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_I2S_LR0          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_LED_LS_2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_PKT_DATA3        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_VEC_VSYNC_1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SC0_AUX_1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_PM_GPIO_019      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_018 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_GPIO_018         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_UART_RXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_EXT_IRQB_11      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_LED_LS_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_PKT_ERROR3       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_TP_IN_02         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_PM_GPIO_018      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_017 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_GPIO_017         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_UART_TXD_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_EXT_IRQB_10      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_LED_LS_0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PKT_SYNC2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_TP_OUT_03        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PM_GPIO_017      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_016 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_GPIO_016         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_UART_RTS_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_I2S_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_LED_KD_3         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PKT_ERROR2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EXT_IRQB_8       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_VEC_HSYNC_1      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_TP_OUT_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PM_GPIO_016      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_015 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_GPIO_015         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_UART_CTS_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_I2S_CLK0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_LED_KD_2         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_PKT_DATA2        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_EXT_IRQB_7       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_VEC_HSYNC_0      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SC0_VPP          7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_TP_IN_01         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_PM_GPIO_015      9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_014 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_GPIO_014         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_UART_RXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PWM_1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_LED_KD_1         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PKT_CLK2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_EXT_IRQB_6       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_IR_IN1           6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_TP_IN_00         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PM_GPIO_014      8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_013 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_GPIO_013         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_UART_TXD_0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PWM_0            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_LED_KD_0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PKT_VALID2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_EXT_IRQB_5       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_IR_INT           6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_TP_OUT_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PM_GPIO_013      8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_028 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_GPIO_028        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SC1_RST         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_LED_LD_3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_PKT_ERROR3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_TP_IN_13        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_027 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_GPIO_027        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SC1_PRES        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_LED_LD_2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_PKT_DATA3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_TP_IN_12        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_PM_GPIO_027     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_026 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_GPIO_026        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SC1_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_LED_LD_1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_PKT_CLK3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_TP_OUT_11       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_PM_GPIO_026     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_025 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_GPIO_025        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SC1_IO          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_LED_LD_0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_PKT_VALID3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_UART_CTS_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_TP_IN_10        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_024 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_GPIO_024        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_UART_RTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_CHIP2CI_MCLKO   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_RMX_PAUSE1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SC_EXT_CLK      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_P1_INTR_1       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_TP_OUT_29       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_PM_GPIO_024     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_023 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_GPIO_023        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_UART_CTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_CI2CHIP_MCLKI   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_RMX_PAUSE0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_SC_CLK_OUT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_TP_IN_08        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_PM_GPIO_023     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_022 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_GPIO_022        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_UART_RXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_EXT_IRQB_14     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PKT_ERROR1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_CHIP2CI_MOSTRT  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_TP_IN_06        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PM_GPIO_022     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_021 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_GPIO_021        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_UART_TXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_EXT_IRQB_13     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_LED_LS_4        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PKT_ERROR0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_CHIP2CI_MOVAL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_TP_OUT_07       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PM_GPIO_021     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_036 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_GPIO_036        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_CI2CHIP_MIVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PPKT_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PKT_ERROR1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_RGMII_1_RXD_00  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_MTSIF_RX1_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_ALT_TP_OUT_06   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_035 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_GPIO_035        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_CI2CHIP_MISTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PPKT_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PKT_ERROR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_MTSIF_RX0_DATA_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_ALT_TP_OUT_05   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_034 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_GPIO_034        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_SC_EXT_CLK      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PPKT_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_MTSIF_ATS_RESET 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_TP_IN_19        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PM_GPIO_034     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_033 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_GPIO_033        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SC_CLK_OUT      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MTSIF_ATS_INC   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_TP_IN_18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_PM_GPIO_033     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_032 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_GPIO_032        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SC1_VPP         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_LED_LD_7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_I2S_LR0         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_TP_IN_17        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PM_GPIO_032     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_031 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_GPIO_031        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_SC1_AUX_2       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_LED_LD_6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_I2S_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_TP_IN_16        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_PM_GPIO_031     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_030 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_GPIO_030        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_SC1_AUX_1       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_LED_LD_5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_I2S_CLK0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_TP_IN_15        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_PM_GPIO_030     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_029 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_GPIO_029        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_SC1_VCC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_LED_LD_4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_PKT_SYNC3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_TP_IN_14        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_044 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_GPIO_044        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_CI2CHIP_MDI7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_PPKT_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_PKT_SYNC1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_RGMII_1_TXD_02  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_MTSIF_RX1_DATA_6 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_TP_OUT_23       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_043 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_GPIO_043        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_CI2CHIP_MDI6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_PPKT_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_PKT_SYNC0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_RGMII_1_TXD_01  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_MTSIF_RX1_DATA_5 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_ALT_TP_OUT_09   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_042 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_GPIO_042        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_CI2CHIP_MDI5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_PPKT_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_PKT_DATA1       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_RGMII_1_TXD_00  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_MTSIF_RX1_DATA_4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_ALT_TP_OUT_08   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_041 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_GPIO_041        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_CI2CHIP_MDI4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PPKT_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PKT_DATA0       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_RGMII_1_RXCTL   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MTSIF_RX1_DATA_3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_ALT_TP_OUT_07   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_040 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_GPIO_040        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_CI2CHIP_MDI3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PPKT_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PKT_CLK1        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_RGMII_1_RXCLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SDS1_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MTSIF_RX1_DATA_2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_ALT_TP_OUT_27   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_039 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_GPIO_039        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_CI2CHIP_MDI2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PPKT_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PKT_CLK0        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_RGMII_1_RXD_03  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_SDS1_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_MTSIF_RX1_DATA_1 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_038 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_GPIO_038        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_CI2CHIP_MDI1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PPKT_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PKT_VALID1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_RGMII_1_RXD_02  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_UART_RTS_2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_MTSIF_RX1_DATA_0 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_037 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_GPIO_037        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_CI2CHIP_MDI0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_PPKT_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_PKT_VALID0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_RGMII_1_RXD_01  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_UART_TXD_2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_MTSIF_RX1_SYNC  6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_052 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_GPIO_052        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_CHIP2CI_MDO4    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_RMXP_DATA4      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_PKT_CLK3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_MII_1_CRS       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_EXT_IRQB_11     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_ALT_TP_OUT_18   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_051 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_GPIO_051        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_CHIP2CI_MDO3    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_RMXP_DATA3      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_MII_1_COL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_EXT_IRQB_10     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_ALT_TP_OUT_17   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_050 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_GPIO_050        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_CHIP2CI_MDO2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_RMXP_DATA2      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_MII_1_RXER      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_EXT_IRQB_9      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_ALT_TP_OUT_16   5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_049 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_GPIO_049        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_CHIP2CI_MDO1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMXP_DATA1      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_EXT_IRQB_8      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RGMII_1_MDIO    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMX_PAUSE1      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_PKT_SYNC5       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_ALT_TP_OUT_15   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_048 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_GPIO_048        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_CHIP2CI_MDO0    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RMXP_DATA0      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_EXT_IRQB_7      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RGMII_1_MDC     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RMX_PAUSE0      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_PKT_ERROR5      6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_047 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_GPIO_047        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_CHIP2CI_MOSTRT  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_RMXP_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_EXT_IRQB_6      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_RGMII_1_TXCTL   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_SPI_M_SS2B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_PKT_DATA5       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_ALT_TP_OUT_13   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_046 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_GPIO_046        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_CHIP2CI_MOVAL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_RMXP_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_EXT_IRQB_5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_RGMII_1_TXCLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_SPI_M_SS1B      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_PKT_CLK5        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_ALT_TP_OUT_12   7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_045 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_GPIO_045        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_CI2CHIP_MICLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PPKT_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PKT_VALID5      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_RGMII_1_TXD_03  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_MTSIF_RX1_DATA_7 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PM_GPIO_045     6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_060 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_GPIO_060        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS1_PKTP_DAT_5 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS0_PKTP_DAT_5 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SDS0_IF_AGC     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_PKT_SYNC5       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_059 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_GPIO_059        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS1_PKTP_CLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS0_PKTP_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SDS0_RF_AGC     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_PKT_ERROR5      4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_058 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_GPIO_058        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_SPI_M_MISO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_PKT_DATA5       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_MTSIF_RX0_SYNC  3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_057 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_GPIO_057        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SPI_M_MOSI      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_PKT_CLK5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_VEC_VSYNC_1     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_VEC_HSYNC_1     4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_056 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_GPIO_056        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_CHIP2CI_MOCLK   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_RMXP_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PKT_SYNC3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_EXT_IRQB_2      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_I2S_LR1_IN      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SC0_VPP         7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_ALT_TP_OUT_22   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PM_GPIO_056     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_055 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_GPIO_055        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_CHIP2CI_MDO7    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_RMXP_DATA7      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_PKT_ERROR3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_EXT_IRQB_1      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_I2S_DATA1_IN    6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SC0_AUX_2       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_ALT_TP_OUT_21   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_PM_GPIO_055     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_054 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_GPIO_054        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_CHIP2CI_MDO6    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_RMXP_DATA6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_PKT_DATA3       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_EXT_IRQB_0      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_I2S_CLK1_IN     6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SC0_AUX_1       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_ALT_TP_OUT_20   8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_PM_GPIO_054     9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_053 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_GPIO_053        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_CHIP2CI_MDO5    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_RMXP_DATA5      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_PKT_VALID3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_MII_1_TXER      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_EXT_IRQB_12     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_ALT_TP_OUT_19   6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_068 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GPIO_068        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GENET0_ACTIVITY 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GENET1_LINK     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_SPI_M_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_EXT_IRQB_5      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_MTSIF_RX0_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_TP_OUT_02       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_067 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_GPIO_067        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS1_BERT_ERROR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS1_DEMOD_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS0_BERT_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SDS0_DEMOD_ERROR 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_PKT_ERROR2      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_MTSIF_RX0_DATA_5 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_066 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_GPIO_066        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_TNR_TSPI_RSTB   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS1_BERT_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS1_DEMOD_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS0_BERT_VALID 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SDS0_DEMOD_VALID 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_PKT_VALID2      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_MTSIF_RX0_DATA_4 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_065 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_GPIO_065        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_TNR_TST_MOSI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS1_BERT_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS1_DEMOD_SYNC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS0_BERT_SYNC  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SDS0_DEMOD_SYNC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_PKT_SYNC2       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MTSIF_RX0_DATA_3 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_064 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_GPIO_064        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_TNR1_TST_SS_N   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS1_BERT_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS1_DEMOD_DATA 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS0_BERT_DATA  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SDS0_DEMOD_DATA 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PKT_DATA2       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MTSIF_RX0_DATA_7 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_063 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_GPIO_063        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_TNR0_TST_SS_N   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS1_BERT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS1_DEMOD_CLK  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS0_BERT_CLK   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SDS0_DEMOD_CLK  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_PKT_CLK2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MTSIF_RX0_DATA_6 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_062 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_GPIO_062        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_TNR_TST_SCK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS1_PKTP_DAT_7 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS0_PKTP_DAT_7 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SPI_S_MISO      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SDS1_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_TTX0_REQ        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_EXT_IRQB_3      7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_061 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_GPIO_061        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS1_PKTP_DAT_6 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS0_PKTP_DAT_6 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SPI_S_SS0B      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SDS1_RF_AGC     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_TTX0_DATA       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_PKT_VALID5      6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_04 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SGPIO_04        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_BSC_M2_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_04_SDS0_RF_AGC     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_UHFR_GLB_PWRDN  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_TP_IN_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_UHFR_GLB_PWRDN  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SDIO_LED        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_01 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_01_BSC_M3_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_00 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_00_BSC_M3_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_071 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_GPIO_071        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_CODEC_SDO       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_070 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_GPIO_070        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_GENET1_LINK     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_TNR1_TST_MISO   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_EXT_IRQB_7      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_SPI_S_MISO      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MTSIF_RX0_DATA_2 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_069 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_GPIO_069        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_GENET1_ACTIVITY 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_EXT_IRQB_6      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MTSIF_RX0_DATA_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_SPI_S_SS0B      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_TP_OUT_21       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_17 - Pinmux control register 17
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_5 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_VO_656_5        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_UART_CTS_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_5_SDIO_PRES       2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_4 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_VO_656_4        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDIO_PWR0       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS1_BERT_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS1_DEMOD_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS0_BERT_ERROR 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_4_SDS0_DEMOD_ERROR 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_3 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_VO_656_3        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_UART_CTS_1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDIO_DAT3       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS1_BERT_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS1_DEMOD_VALID 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS0_BERT_VALID 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_3_SDS0_DEMOD_VALID 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_2 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_VO_656_2        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_UART_RXD_1      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDIO_DAT2       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS1_BERT_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS1_DEMOD_SYNC 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS0_BERT_SYNC  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_2_SDS0_DEMOD_SYNC 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_1 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_VO_656_1        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_UART_CTS_0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDIO_DAT1       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS1_BERT_DATA  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS1_DEMOD_DATA 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS0_BERT_DATA  5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_1_SDS0_DEMOD_DATA 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: vo_656_0 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_VO_656_0        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_UART_RXD_0      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDIO_DAT0       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS1_BERT_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS1_DEMOD_CLK  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS0_BERT_CLK   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_vo_656_0_SDS0_DEMOD_CLK  6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: clk27_out [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_DEFAULT        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_CLK27_OUT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_clk27_out_TP_IN_11       1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: sgpio_05 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SGPIO_05        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_BSC_M2_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_sgpio_05_SDS0_IF_AGC     2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_18 - Pinmux control register 18
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          28
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_selvtop [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_MASK   0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_SHIFT  24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_SDS1_DSEC_SELVTOP 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_FTM_TXEN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_selvtop_ALT_TP_IN_26 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_txen [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_SDS1_DSEC_TXEN 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txen_FTM_RX_DATA_BYP 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds1_dsec_txout [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_MASK     0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_DEFAULT  0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_SDS1_DSEC_TXOUT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds1_dsec_txout_FTM_UART_MAN_DATA 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: sds0_dsec_selvtop [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_MASK   0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_SDS0_DSEC_SELVTOP 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_sds0_dsec_selvtop_FTM_TXEN 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_clk [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_MASK          0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_DEFAULT       0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_VO_656_CLK    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_clk_SDIO_CLK      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_7 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_VO_656_7        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_7_SDIO_CMD        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: vo_656_6 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_VO_656_6        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_UART_RXD_2      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_vo_656_6_SDIO_WPROT      2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr26_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr25_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr25_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr24_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved1 [17:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_MASK        0x0003f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved1_SHIFT       12
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr23_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr23_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved2 [09:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_MASK        0x000003ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved2_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [27:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x0fffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: ebi_dsb_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: ebi_tsb_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved1 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_MASK        0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved0 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_MASK        0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_010_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_009_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved1 [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_MASK        0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_007_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_006_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_005_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_004_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_003_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_002_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_001_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_001_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: reserved0 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_MASK        0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved0_SHIFT       24
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_027_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_026_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: reserved1 [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved1_MASK        0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_reserved1_SHIFT       18
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_024_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_023_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_022_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_021_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_020_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_019_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_018_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_017_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_016_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_016_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_042_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_041_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_040_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_039_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_038_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_037_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_036_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_035_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_034_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_033_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_032_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_031_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_031_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_057_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_056_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_055_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_054_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_053_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_052_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_051_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_050_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_049_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_048_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_047_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_046_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_046_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK       0x3fc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT      22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_071_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_070_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_069_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_068_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_067_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_066_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_065_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_064_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_063_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_062_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_061_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_061_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [29:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0x3fffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK       0xfc000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT      26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved1 [23:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved1_MASK       0x00ffffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved1_SHIFT      0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xc0000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       30
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_dsp_clk [29:29] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_avd_clk [28:28] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [27:27] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_sys9_clk [26:26] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_068 [25:25] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_068_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_058 [24:24] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_058_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_057 [23:23] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_057_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_056 [22:22] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_056_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_055 [21:21] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_055_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_054 [20:20] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_054_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_053 [19:19] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_053_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_052 [18:18] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_052_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_051 [17:17] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_051_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_050 [16:16] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_050_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_049 [15:15] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_049_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_048 [14:14] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_048_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_045 [13:13] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_045_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_040 [12:12] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_040_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_039 [11:11] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_039_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_038 [10:10] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_038_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_037 [09:09] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_037_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_019 [08:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_019_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_005 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_005_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_004 [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_004_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_003 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_003_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs2b [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs1b [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs1b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs4b [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs4b_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_mii_col [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_mii_col_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK          0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT         25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_svd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_svd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xc0000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         30
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK       0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT      25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_svd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xc0000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK  0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xc0000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_svd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_MASK        0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_SHIFT       7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_MASK          0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_uhfr_sw_init_DEFAULT       0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_uhfr_sw_init_DEFAULT     0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_MASK     0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_SHIFT    7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_MASK       0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_uhfr_sw_init_DEFAULT    1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffc00
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_a_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_uhfr_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 30
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: svd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_svd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_a_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: uhfr_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_uhfr_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R  7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_A  8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T  9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     29
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1    46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UHFR    50
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 8
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 3
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SVD0_BL   4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID       5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_timer.h b/include/linux/brcmstb/7346b0/bchp_timer.h
new file mode 100644
index 000000000000..7680ffca55ce
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:26:15 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:53p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x004067c0 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x004067c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x004067c8 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x004067cc /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x004067d0 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x004067d4 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x004067d8 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x004067dc /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004067e0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004067e4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004067e8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004067ec /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004067f0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004067f4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004067f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004067fc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uarta.h b/include/linux/brcmstb/7346b0/bchp_uarta.h
new file mode 100644
index 000000000000..b537d8ece86c
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:35:13 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:55p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406900 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406900 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406904 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406900 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406904 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406908 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406908 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040690c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406910 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406914 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406918 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040691c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uartb.h b/include/linux/brcmstb/7346b0/bchp_uartb.h
new file mode 100644
index 000000000000..dad148bb77bc
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:19:59 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 7:58p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406940 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406940 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406944 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406940 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406944 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406948 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406948 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040694c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406950 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406954 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406958 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040695c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_uartc.h b/include/linux/brcmstb/7346b0/bchp_uartc.h
new file mode 100644
index 000000000000..547c9abbeee5
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug  2 15:05:39 2010
+ *                 MD5 Checksum         616c5da46e7f2e811fb57b174083665d
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/1   8/2/10 7:59p pntruong
+ * SW7346-2: Initial version.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406980 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406980 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406984 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406980 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406984 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406988 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406988 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040698c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406990 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406994 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406998 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040699c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h b/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h
new file mode 100644
index 000000000000..6a1e949cde86
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_usb1_ctrl.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:11:35 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_usb1_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 6:01p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB1_CTRL_H__
+#define BCHP_USB1_CTRL_H__
+
+/***************************************************************************
+ *USB1_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB1_CTRL_SETUP                     0x00490200 /* Setup Register */
+#define BCHP_USB1_CTRL_PLL_CTL                   0x00490204 /* PLL Control Register */
+#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00490208 /* Frame Adjust Value */
+#define BCHP_USB1_CTRL_EBRIDGE                   0x0049020c /* Control Register for EHCI Bridge */
+#define BCHP_USB1_CTRL_OBRIDGE                   0x00490210 /* Control Register for OHCI Bridge */
+#define BCHP_USB1_CTRL_MDIO                      0x00490214 /* MDIO Interface Programming Register */
+#define BCHP_USB1_CTRL_MDIO2                     0x00490218 /* MDIO Interface Read Register */
+#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0049021c /* Test Port Control Register */
+#define BCHP_USB1_CTRL_USB_SIMCTL                0x00490220 /* Simulation Register */
+#define BCHP_USB1_CTRL_USB_TESTCTL               0x00490224 /* Throutput Test Control */
+#define BCHP_USB1_CTRL_USB_TESTMON               0x00490228 /* Throughput Test Monitor */
+#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0049022c /* UTMI Control Register */
+#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00490230 /* UTMI Control 2 Register */
+#define BCHP_USB1_CTRL_SPARE1                    0x00490234 /* Spare1 Register for future use */
+#define BCHP_USB1_CTRL_SPARE2                    0x00490238 /* Spare2 Register for future use */
+
+#endif /* #ifndef BCHP_USB1_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h b/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..f21414381919
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_usb_ctrl.h
@@ -0,0 +1,675 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:30:07 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 5:58p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0e000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      25
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [24:15] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x01ff8000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      15
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: scb_client_swap [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00004000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  14
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0
+
+/* USB_CTRL :: SETUP :: scb1_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_CLK_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_CLK_SEL_DEFAULT                    0
+
+/* USB_CTRL :: MDIO :: MDIO_XVER_SELECT [30:29] */
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_MASK                   0x60000000
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_SHIFT                  29
+#define BCHP_USB_CTRL_MDIO_MDIO_XVER_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TERM_SELECT [28:28] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_MASK                   0x10000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_SHIFT                  28
+#define BCHP_USB_CTRL_MDIO_MDIO_TERM_SELECT_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_FS_XVER_OWN [27:27] */
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_MASK                   0x08000000
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_SHIFT                  27
+#define BCHP_USB_CTRL_MDIO_MDIO_FS_XVER_OWN_DEFAULT                0
+
+/* USB_CTRL :: MDIO :: MDIO_TESTMODE [26:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_MASK                      0x04000000
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_SHIFT                     26
+#define BCHP_USB_CTRL_MDIO_MDIO_TESTMODE_DEFAULT                   0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7c000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [24:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x01000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [20:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x00180000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [18:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00070000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03ffffff
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x06000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000600
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/bchp_wktmr.h b/include/linux/brcmstb/7346b0/bchp_wktmr.h
new file mode 100644
index 000000000000..d54f9036c35e
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 13 13:12:06 2011
+ *                 MD5 Checksum         c1b53a9408066d1e6123c0860dfb8065
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/1   4/14/11 6:12p albertl
+ * SW7346-143: Initial revision.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7346b0/brcmirq.h b/include/linux/brcmstb/7346b0/brcmirq.h
new file mode 100644
index 000000000000..ef2f3cb8ad6e
--- /dev/null
+++ b/include/linux/brcmstb/7346b0/brcmirq.h
@@ -0,0 +1,48 @@
+/*
+ * 7346b0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	69
+#define BRCM_IRQ_EHCI0_1	70
+#define BRCM_IRQ_EHCI1_0	74
+#define BRCM_IRQ_EHCI1_1	75
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_GENET_1_A	27
+#define BRCM_IRQ_GENET_1_B	28
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_MOCA		36
+#define BRCM_IRQ_OHCI0_0	71
+#define BRCM_IRQ_OHCI0_1	72
+#define BRCM_IRQ_OHCI1_0	76
+#define BRCM_IRQ_OHCI1_1	77
+#define BRCM_IRQ_SATA		41
+#define BRCM_IRQ_SDIO0		86
+#define BRCM_IRQ_STANDBY	54
+#define BRCM_IRQ_UARTA		65
+#define BRCM_IRQ_UARTB		66
+#define BRCM_IRQ_UARTC		67
+#define BRCM_IRQLIST_EHCI	{ 69, 70, 74, 75 }
+#define BRCM_IRQLIST_OHCI	{ 71, 72, 76, 77 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..4b53fb3b0283
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_ctrl.h
@@ -0,0 +1,1970 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:56 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 11:28a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HASH_VALUE_0               0x00408030 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_1               0x00408034 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_2               0x00408038 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_3               0x0040803c /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_4               0x00408040 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_5               0x00408044 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_6               0x00408048 /* DRAM Hash Value */
+#define BCHP_AON_CTRL_HASH_VALUE_7               0x0040804c /* DRAM Hash Value */
+#define BCHP_AON_CTRL_DRAM_START_0               0x00408050 /* DRAM Start Address 0 */
+#define BCHP_AON_CTRL_DRAM_END_0                 0x00408054 /* DRAM End Address 0 */
+#define BCHP_AON_CTRL_DRAM_START_1               0x00408058 /* DRAM Start Address 1 */
+#define BCHP_AON_CTRL_DRAM_END_1                 0x0040805c /* DRAM End Address 1 */
+#define BCHP_AON_CTRL_DRAM_START_2               0x00408060 /* DRAM Start Address 2 */
+#define BCHP_AON_CTRL_DRAM_END_2                 0x00408064 /* DRAM End Address 2 */
+#define BCHP_AON_CTRL_DRAM_START_3               0x00408068 /* DRAM Start Address 3 */
+#define BCHP_AON_CTRL_DRAM_END_3                 0x0040806c /* DRAM End Address 3 */
+#define BCHP_AON_CTRL_DRAM_START_4               0x00408070 /* DRAM Start Address 4 */
+#define BCHP_AON_CTRL_DRAM_END_4                 0x00408074 /* DRAM End Address 4 */
+#define BCHP_AON_CTRL_DRAM_START_5               0x00408078 /* DRAM Start Address 5 */
+#define BCHP_AON_CTRL_DRAM_END_5                 0x0040807c /* DRAM End Address 5 */
+#define BCHP_AON_CTRL_DRAM_START_6               0x00408080 /* DRAM Start Address 6 */
+#define BCHP_AON_CTRL_DRAM_END_6                 0x00408084 /* DRAM End Address 6 */
+#define BCHP_AON_CTRL_DRAM_START_7               0x00408088 /* DRAM Start Address 7 */
+#define BCHP_AON_CTRL_DRAM_END_7                 0x0040808c /* DRAM End Address 7 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_00             0x00408090 /* System Data 00 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_01             0x00408094 /* System Data 01 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_02             0x00408098 /* System Data 02 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_03             0x0040809c /* System Data 03 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_04             0x004080a0 /* System Data 04 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_05             0x004080a4 /* System Data 05 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_06             0x004080a8 /* System Data 06 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_07             0x004080ac /* System Data 07 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_08             0x004080b0 /* System Data 08 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_09             0x004080b4 /* System Data 09 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_10             0x004080b8 /* System Data 10 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_11             0x004080bc /* System Data 11 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_12             0x004080c0 /* System Data 12 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_13             0x004080c4 /* System Data 13 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_14             0x004080c8 /* System Data 14 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_15             0x004080cc /* System Data 15 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_16             0x004080d0 /* System Data 16 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_17             0x004080d4 /* System Data 17 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_18             0x004080d8 /* System Data 18 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_19             0x004080dc /* System Data 19 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_20             0x004080e0 /* System Data 20 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_21             0x004080e4 /* System Data 21 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_22             0x004080e8 /* System Data 22 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_23             0x004080ec /* System Data 23 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_24             0x004080f0 /* System Data 24 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_25             0x004080f4 /* System Data 25 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_26             0x004080f8 /* System Data 26 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_27             0x004080fc /* System Data 27 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_28             0x00408100 /* System Data 28 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_29             0x00408104 /* System Data 29 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_30             0x00408108 /* System Data 30 */
+#define BCHP_AON_CTRL_SYSTEM_DATA_31             0x0040810c /* System Data 31 */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408120 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408124 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408128 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x00408130 /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408134 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408138 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x0040813c /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x00408140 /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408150 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408154 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408158 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408180 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408184 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408190 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x00408194 /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408198 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x004081a0 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x004081b0 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x004081b4 /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x004081b8 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x004081bc /* Final latched sub-testmode value */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      1
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 16
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 540000
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0
+
+/***************************************************************************
+ *HASH_VALUE_0 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_0 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_0_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_1 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_1 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_1_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_2 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_2 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_2_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_3 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_3 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_3_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_4 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_4 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_4_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_5 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_5 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_5_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_6 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_6 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_6_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *HASH_VALUE_7 - DRAM Hash Value
+ ***************************************************************************/
+/* AON_CTRL :: HASH_VALUE_7 :: hash_value [31:00] */
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_MASK                 0xffffffff
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_SHIFT                0
+#define BCHP_AON_CTRL_HASH_VALUE_7_hash_value_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_START_0 - DRAM Start Address 0
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_0 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_0_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_0 - DRAM End Address 0
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_0 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_0_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_1 - DRAM Start Address 1
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_1 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_1_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_1 - DRAM End Address 1
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_1 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_1_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_2 - DRAM Start Address 2
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_2 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_2_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_2 - DRAM End Address 2
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_2 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_2_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_3 - DRAM Start Address 3
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_3 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_3_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_3 - DRAM End Address 3
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_3 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_3_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_4 - DRAM Start Address 4
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_4 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_4_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_4 - DRAM End Address 4
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_4 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_4_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_5 - DRAM Start Address 5
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_5 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_5_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_5 - DRAM End Address 5
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_5 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_5_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_6 - DRAM Start Address 6
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_6 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_6_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_6 - DRAM End Address 6
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_6 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_6_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *DRAM_START_7 - DRAM Start Address 7
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_START_7 :: dram_start [31:00] */
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_MASK                 0xffffffff
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_SHIFT                0
+#define BCHP_AON_CTRL_DRAM_START_7_dram_start_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_END_7 - DRAM End Address 7
+ ***************************************************************************/
+/* AON_CTRL :: DRAM_END_7 :: dram_end [31:00] */
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_MASK                     0xffffffff
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_SHIFT                    0
+#define BCHP_AON_CTRL_DRAM_END_7_dram_end_DEFAULT                  0
+
+/***************************************************************************
+ *SYSTEM_DATA_00 - System Data 00
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_00 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_00_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_01 - System Data 01
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_01 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_01_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_02 - System Data 02
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_02 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_02_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_03 - System Data 03
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_03 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_03_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_04 - System Data 04
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_04 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_04_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_05 - System Data 05
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_05 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_05_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_06 - System Data 06
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_06 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_06_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_07 - System Data 07
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_07 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_07_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_08 - System Data 08
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_08 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_08_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_09 - System Data 09
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_09 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_09_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_10 - System Data 10
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_10 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_10_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_11 - System Data 11
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_11 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_11_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_12 - System Data 12
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_12 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_12_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_13 - System Data 13
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_13 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_13_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_14 - System Data 14
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_14 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_14_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_15 - System Data 15
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_15 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_15_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_16 - System Data 16
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_16 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_16_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_17 - System Data 17
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_17 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_17_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_18 - System Data 18
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_18 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_18_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_19 - System Data 19
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_19 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_19_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_20 - System Data 20
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_20 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_20_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_21 - System Data 21
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_21 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_21_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_22 - System Data 22
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_22 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_22_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_23 - System Data 23
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_23 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_23_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_24 - System Data 24
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_24 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_24_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_25 - System Data 25
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_25 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_25_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_26 - System Data 26
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_26 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_26_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_27 - System Data 27
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_27 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_27_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_28 - System Data 28
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_28 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_28_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_29 - System Data 29
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_29 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_29_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_30 - System Data 30
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_30 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_30_system_data_DEFAULT           0
+
+/***************************************************************************
+ *SYSTEM_DATA_31 - System Data 31
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_31 :: system_data [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_MASK              0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_SHIFT             0
+#define BCHP_AON_CTRL_SYSTEM_DATA_31_system_data_DEFAULT           0
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 32
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 36
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 24
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 28
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      1
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 1
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           1
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         1
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             1
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 4
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..a11f191ebf0e
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,609 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:03 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/5   9/20/11 11:29a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408300 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408304 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408308 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040830c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408310 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408314 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x00408318 /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RTS 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           4
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       30
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..f893dfc26f14
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1047 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:29a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408240 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408244 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408248 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040824c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408250 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408254 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408258 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040825c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408260 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408264 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408268 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040826c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff8000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  15
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff8000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     15
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff8000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   15
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             15
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                15
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               1
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff8000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              15
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             1
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             1
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_bspi.h b/include/linux/brcmstb/7358a0/bchp_bspi.h
new file mode 100644
index 000000000000..dbd3ad77236d
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:55 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:38a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        4
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       1
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       1
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              8
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          11
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              3
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_bspi_raf.h b/include/linux/brcmstb/7358a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..cb96e230ff6e
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:45:43 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:38a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    1
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_clkgen.h b/include/linux/brcmstb/7358a0/bchp_clkgen.h
new file mode 100644
index 000000000000..bcebaefa55ac
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_clkgen.h
@@ -0,0 +1,4808 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:24 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/6   9/20/11 11:42a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00420088 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x0042008c /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00420090 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420094 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420098 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x0042009c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x004200a0 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a8 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200b0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200bc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200c0 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c4 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c8 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200cc /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200d0 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d4 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d8 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200dc /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200e0 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e4 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e8 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200ec /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200f0 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f4 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f8 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200fc /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x00420100 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420104 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420108 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x0042010c /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420110 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x00420114 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420118 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x0042011c /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420120 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x00420124 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420128 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x0042012c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420130 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x00420134 /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420138 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x0042013c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420140 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x00420144 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420148 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x0042014c /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420150 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00420154 /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420158 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x0042015c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420160 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00420164 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420168 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x0042016c /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420170 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x00420174 /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420178 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x0042017c /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420180 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x00420184 /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420188 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x0042018c /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420190 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x00420194 /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420198 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x0042019c /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x004201a0 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201ac /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b0 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b8 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201bc /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201c0 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201c4 /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c8 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201cc /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201d0 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201d4 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d8 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201dc /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201e0 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201e4 /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e8 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201ec /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201f0 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK         0x004201f4 /* Ds top observe clock */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201f8 /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201fc /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x00420200 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x00420204 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x00420208 /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x0042020c /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420210 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420214 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x00420218 /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x0042021c /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420220 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420224 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00420228 /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x0042022c /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420230 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420234 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x00420238 /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x0042023c /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420240 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420244 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x00420248 /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x0042024c /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420250 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420254 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00420258 /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x0042025c /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420260 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420264 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x00420268 /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x0042026c /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420274 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x00420278 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x0042027c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420280 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420284 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x00420288 /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x0042028c /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420290 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420294 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x00420298 /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x0042029c /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004202a0 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004202a4 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x004202a8 /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202ac /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202b0 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202b4 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202b8 /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202bc /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202c0 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202c4 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202c8 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202cc /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202d0 /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202d4 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202d8 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202dc /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202e0 /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202e4 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202e8 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202ec /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202f0 /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x004202f4 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x004202f8 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x004202fc /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x00420300 /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420304 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420308 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x0042030c /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x00420310 /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420314 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420318 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x0042031c /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x00420320 /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420324 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420328 /* Special Testport Controls */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE         0x0042032c /* Thd top clock enable */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP               0x00420330 /* Ts ctrl0 cktap */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP               0x00420334 /* Ts ctrl1 cktap */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP               0x00420338 /* Ts ctrl2 cktap */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT       0x0042033c /* Mux selects for TS_CTRL_CLK clocks */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP           0x00420340 /* Ts ctrl data cktap */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420344 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x00420348 /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x0042034c /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420350 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420354 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x00420358 /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x0042035c /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420360 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420364 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x00420368 /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x0042036c /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420370 /* Vec aio top power switch memory b */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 10
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 8
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              3
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          167
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  8
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  50
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 12
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 96
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 54
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              96
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 9
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 75
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 250
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:03] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xfffffff8
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         3
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    1
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      1
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      1
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_THD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *DS_TOP_OBSERVE_CLOCK - Ds top observe clock
+ ***************************************************************************/
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_reserved0_SHIFT           2
+
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: DSTOP_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DS_TOP_OBSERVE_CLOCK :: DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DS_TOP_OBSERVE_CLOCK_DSTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     1
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  1
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  1
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          2
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0
+
+/***************************************************************************
+ *THD_TOP_CLOCK_ENABLE - Thd top clock enable
+ ***************************************************************************/
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: THD_TOP_CLOCK_ENABLE :: THD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *TS_CTRL0_CKTAP - Ts ctrl0 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL0_CKTAP :: reserved0 [31:22] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_reserved0_MASK                  0xffc00000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_reserved0_SHIFT                 22
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: TOGGLE_CNT_CKTAP [21:17] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_MASK           0x003e0000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_SHIFT          17
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_TOGGLE_CNT_CKTAP_DEFAULT        0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: SEL_MUX2_CKTAP [16:16] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_MASK             0x00010000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_SHIFT            16
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX2_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: SEL_MUX1_CKTAP [15:15] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_MASK             0x00008000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_SHIFT            15
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_SEL_MUX1_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: RO_SEL_CKTAP [14:14] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_MASK               0x00004000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_SHIFT              14
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_SEL_CKTAP_DEFAULT            0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: RO_EN_CKTAP [13:13] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_MASK                0x00002000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_SHIFT               13
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_RO_EN_CKTAP_DEFAULT             0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: GATE_CTRL_EN_CKTAP [12:12] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_MASK         0x00001000
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_SHIFT        12
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_GATE_CTRL_EN_CKTAP_DEFAULT      0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: EN_RAND_CKTAP [11:08] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_MASK              0x00000f00
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_SHIFT             8
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_RAND_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: EN_ORD_CKTAP [07:04] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_MASK               0x000000f0
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_SHIFT              4
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_EN_ORD_CKTAP_DEFAULT            0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: DIV2SEL_CKTAP [03:03] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_MASK              0x00000008
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_SHIFT             3
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_DIV2SEL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: CLK_GATE_EN_CKTAP [02:02] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_MASK          0x00000004
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_SHIFT         2
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CLK_GATE_EN_CKTAP_DEFAULT       0
+
+/* CLKGEN :: TS_CTRL0_CKTAP :: CKTAP_SEL_CKTAP [01:00] */
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_MASK            0x00000003
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_SHIFT           0
+#define BCHP_CLKGEN_TS_CTRL0_CKTAP_CKTAP_SEL_CKTAP_DEFAULT         0
+
+/***************************************************************************
+ *TS_CTRL1_CKTAP - Ts ctrl1 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL1_CKTAP :: reserved0 [31:26] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_reserved0_MASK                  0xfc000000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_reserved0_SHIFT                 26
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP3VAL_CKTAP [25:22] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_MASK              0x03c00000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_SHIFT             22
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP3VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP2VAL_CKTAP [21:18] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_MASK              0x003c0000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_SHIFT             18
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP2VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP1VAL_CKTAP [17:14] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_MASK              0x0003c000
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_SHIFT             14
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP1VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: TAP0VAL_CKTAP [13:10] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_MASK              0x00003c00
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_SHIFT             10
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_TAP0VAL_CKTAP_DEFAULT           0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: RISE_VAL_CKTAP [09:07] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_MASK             0x00000380
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_SHIFT            7
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_RISE_VAL_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: FALL_VAL_CKTAP [06:04] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_MASK             0x00000070
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_SHIFT            4
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_VAL_CKTAP_DEFAULT          0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: FALL_TRANS_CKTAP [03:03] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_MASK           0x00000008
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_SHIFT          3
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_FALL_TRANS_CKTAP_DEFAULT        0
+
+/* CLKGEN :: TS_CTRL1_CKTAP :: APRIOR_SWITCH_CNT_CKTAP [02:00] */
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_MASK    0x00000007
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_SHIFT   0
+#define BCHP_CLKGEN_TS_CTRL1_CKTAP_APRIOR_SWITCH_CNT_CKTAP_DEFAULT 0
+
+/***************************************************************************
+ *TS_CTRL2_CKTAP - Ts ctrl2 cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL2_CKTAP :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_reserved0_MASK                  0xfffffffc
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_reserved0_SHIFT                 2
+
+/* CLKGEN :: TS_CTRL2_CKTAP :: START_CKTAP [01:01] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_MASK                0x00000002
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_SHIFT               1
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_START_CKTAP_DEFAULT             0
+
+/* CLKGEN :: TS_CTRL2_CKTAP :: CLEAR_CKTAP [00:00] */
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_MASK                0x00000001
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_SHIFT               0
+#define BCHP_CLKGEN_TS_CTRL2_CKTAP_CLEAR_CKTAP_DEFAULT             0
+
+/***************************************************************************
+ *TS_CTRL_CLK_MUX_SELECT - Mux selects for TS_CTRL_CLK clocks
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL_CLK_MUX_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_reserved0_SHIFT         2
+
+/* CLKGEN :: TS_CTRL_CLK_MUX_SELECT :: CKTAP_TS_CLK [01:00] */
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_MASK       0x00000003
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_SHIFT      0
+#define BCHP_CLKGEN_TS_CTRL_CLK_MUX_SELECT_CKTAP_TS_CLK_DEFAULT    0
+
+/***************************************************************************
+ *TS_CTRL_DATA_CKTAP - Ts ctrl data cktap
+ ***************************************************************************/
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: reserved0 [31:31] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_reserved0_MASK              0x80000000
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_reserved0_SHIFT             31
+
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: TS_DATA_VALID_STATUS_CKTAP [30:30] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_VALID_STATUS_CKTAP_MASK 0x40000000
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_VALID_STATUS_CKTAP_SHIFT 30
+
+/* CLKGEN :: TS_CTRL_DATA_CKTAP :: TS_DATA_STATUS_CKTAP [29:00] */
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_STATUS_CKTAP_MASK   0x3fffffff
+#define BCHP_CLKGEN_TS_CTRL_DATA_CKTAP_TS_DATA_STATUS_CKTAP_SHIFT  0
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 1
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_common.h b/include/linux/brcmstb/7358a0/bchp_common.h
new file mode 100644
index 000000000000..3c90fdbdaeb1
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_common.h
@@ -0,0 +1,1896 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:35:36 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_common.h $
+ * 
+ * Hydra_Software_Devel/7   9/20/11 11:42a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7358_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00a2c800 /* XPT_XPU is last */
+#define BCHP_REGISTER_SIZE                                 0x0028b200 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060080
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00328800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00328ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b08c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00360000
+#define BCHP_SECTOP_GRB_REG_END                            0x0036000c
+#define BCHP_JTAG_OTP_REG_START                            0x00360100
+#define BCHP_JTAG_OTP_REG_END                              0x00360138
+#define BCHP_MEM_DMA_0_REG_START                           0x00360200
+#define BCHP_MEM_DMA_0_REG_END                             0x00360224
+#define BCHP_MMSCRAM_REG_START                             0x00364000
+#define BCHP_MMSCRAM_REG_END                               0x00364ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00366000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0036600c
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b03c8
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22f8
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63ac
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b80e4
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_PWMB_REG_START                                0x00406700
+#define BCHP_PWMB_REG_END                                  0x00406724
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004081bc
+#define BCHP_AON_L2_REG_START                              0x00408200
+#define BCHP_AON_L2_REG_END                                0x0040822c
+#define BCHP_AON_PM_L2_REG_START                           0x00408240
+#define BCHP_AON_PM_L2_REG_END                             0x0040826c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408300
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00408318
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408400
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408498
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e830
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410410
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x00420370
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004234a4
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00503ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642cb4
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x0068007c
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_DGEN_0_REG_START                          0x00685700
+#define BCHP_DVP_DGEN_0_REG_END                            0x00685738
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a0070
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a09b4
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ac0
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_NTCH_REG_START                            0x007005c0
+#define BCHP_SDS_NTCH_REG_END                              0x007005e0
+#define BCHP_SDS_MISC_REG_START                            0x00700600
+#define BCHP_SDS_MISC_REG_END                              0x00700698
+#define BCHP_SDS_DSEC_REG_START                            0x00700700
+#define BCHP_SDS_DSEC_REG_END                              0x007007c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700800
+#define BCHP_SDS_TUNER_REG_END                             0x007008fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x0070205c
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082040c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821200
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821364
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00078
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK  0xffffffff
+#define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK  0xffffffff
+#define BCHP_BVN_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..2c04cab751a8
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1490 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:50 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:43a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       4
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xfe000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..0cc131a3c1c4
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3259 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:39:04 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:43a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 1
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 11
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_ebi.h b/include/linux/brcmstb/7358a0/bchp_ebi.h
new file mode 100644
index 000000000000..3b8908123803
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:38:29 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:46a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       1
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        1
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    7
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               1
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             1
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         1024
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            1
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            1
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..5a0b1032d625
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,1931 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:46:47 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/7   9/20/11 11:54a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_MASK       0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_SHIFT      30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_MCIF_CPU_INTR_DEFAULT    0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          23
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved1_MASK           0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved1_SHIFT          18
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_MCIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved1_MASK      0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved1_SHIFT     18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   1
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  1
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_MASK     0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_SHIFT    30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_MCIF_CPU_INTR_DEFAULT  1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved1_MASK         0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved1_SHIFT        18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 1
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: MCIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_MCIF_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [27:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0x0f800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      23
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved1 [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved1_MASK       0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved1_SHIFT      18
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 1
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 1
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_intr2.h b/include/linux/brcmstb/7358a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..5b3dff8c8959
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:42:55 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:54a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 1
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    1
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  1
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_mspi.h b/include/linux/brcmstb/7358a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..a5a98b316edd
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:44:08 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:55a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..94ca7ec8b0a2
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:35:53 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 11:55a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h
new file mode 100644
index 000000000000..4f52679e4f45
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,527 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:42:41 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 11:56a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_DEFAULT            0
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_irq0.h b/include/linux/brcmstb/7358a0/bchp_irq0.h
new file mode 100644
index 000000000000..904a491ac769
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:37:56 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 11:58a pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_irq1.h b/include/linux/brcmstb/7358a0/bchp_irq1.h
new file mode 100644
index 000000000000..a43a82aeb990
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:01:23 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:17p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..e47974bb04eb
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:47:01 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   9/20/11 12:03p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00360200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00360204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00360208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0036020c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00360214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00360218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0036021c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00360224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      2
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      10
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..76c046953157
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2647 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 22:00:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/4   9/20/11 12:03p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                2
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               1
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           1
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           1
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                6
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                5
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                4
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                2
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                1
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_misb_bridge.h b/include/linux/brcmstb/7358a0/bchp_misb_bridge.h
new file mode 100644
index 000000000000..6a04b969ec4f
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_misb_bridge.h
@@ -0,0 +1,126 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:30 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_misb_bridge.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:05p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT       0x0041040c /* Write Gathering Mode & Timeout. */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE         0x00410410 /* MISB Split Mode */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 4
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+/***************************************************************************
+ *WG_MODE_N_TIMEOUT - Write Gathering Mode & Timeout.
+ ***************************************************************************/
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: reserved0 [31:10] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_MASK          0xfffffc00
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_SHIFT         10
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: MODE [09:08] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MASK               0x00000300
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_SHIFT              8
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_DEFAULT            0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_0             0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_1             1
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_2             2
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: TIMEOUT [07:00] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_MASK            0x000000ff
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_SHIFT           0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_DEFAULT         100
+
+/***************************************************************************
+ *MISB_SPLIT_MODE - MISB Split Mode
+ ***************************************************************************/
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: reserved0 [31:01] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_MASK            0xfffffffe
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_SHIFT           1
+
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: SPLIT_MODE [00:00] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_MASK           0x00000001
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_SHIFT          0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DEFAULT        0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_ENABLE         1
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DISABLE        0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_nand.h b/include/linux/brcmstb/7358a0/bchp_nand.h
new file mode 100644
index 000000000000..d0dd5f8318a3
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:39:49 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:07p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                1
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           5
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        255
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       255
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    1
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  1
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  15
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    15
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            16
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              16
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             6
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             5
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             7
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             8
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            4
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            5
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            11
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             15
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            9
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           6
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  1
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          1
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            1
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              1
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                15
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          16
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         6
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         5
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         7
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         8
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        4
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        5
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        11
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         15
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        9
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       6
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       255
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      255
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      255
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      255
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..aedb2fe353bf
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6324 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:48:00 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/6   9/20/11 12:21p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404144 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404148 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x0040414c /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404150 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404154 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404158 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x0040415c /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404160 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404164 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404168 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    1935147008
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            1935147008
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  1
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_isdbt_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_2 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_3 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spares [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spares_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_31_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_1 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_1_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_isdbt_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_2 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_2_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_3 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_3_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spares [14:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spares_MASK 0x00007c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spares_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_31_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_31_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib2_source [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_MASK           0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_SHIFT          4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib2_source_DEFAULT        0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib1_source [03:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_MASK           0x0000000c
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_SHIFT          2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib1_source_DEFAULT        0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ib0_source [01:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_MASK           0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ib0_source_DEFAULT        0
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_src_0 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: mii_drive_sel_0 [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_mii_drive_sel_0_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_4 [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_4_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_3 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_3 [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_3_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_2 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_2 [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_2_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_1 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_1 [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_1_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_src_0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_src_0_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_drive_sel_0 [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DEFAULT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_drive_sel_0_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 1
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_DEFAULT 1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_DEFAULT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_OOB_AGC_CTL       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DS_AGC_CTL        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MPOD_M_SDI        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MPOD_M_SDO        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MPOD_SCLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MPOD_SCTL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_01 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_SGPIO_01        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_01_BSC_M0_SDA      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_00 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_SGPIO_00        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_00_BSC_M0_SCL      1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_16 - Pinmux control register 16
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_reserved0_MASK           0xffffff00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_reserved0_SHIFT          8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_03 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: sgpio_02 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_DEFAULT         0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_EXT_IRQ6        2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xfc000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [23:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x00ff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 1
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_MASK             0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved0_SHIFT            27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_MASK           0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved0_SHIFT          27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_MASK          0xf8000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved0_SHIFT         27
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_MASK     0xf8000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved0_SHIFT    27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_MASK   0xf8000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved0_SHIFT  27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_r_sw_init_DEFAULT     0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_SHIFT   2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_r_sw_init_DEFAULT   0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         10
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_7_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_6_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_5_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_r_sw_init_DEFAULT  1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_2_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     1
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_not_used_sw_init_0_DEFAULT 1
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfffffc00
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfffffc00
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_r_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_not_used_sw_init_0_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_r_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved0 [31:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_MASK 0xf8000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved0_SHIFT 27
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 1
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfffffc00
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 10
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_7_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_6_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_5_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_r_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_r_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: not_used_sw_init_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_not_used_sw_init_0_DEFAULT 0
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         1
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 127
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DVP_HT  26
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 1
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 24
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        4
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     1
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 31
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 16
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_timer.h b/include/linux/brcmstb/7358a0/bchp_timer.h
new file mode 100644
index 000000000000..51d25e23c7fb
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_timer.h
@@ -0,0 +1,340 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:57 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:22p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_WDCRS                         0x004066b4 /* WATCHDOG CHIP RESET STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             50331647
+
+/***************************************************************************
+ *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCRS :: reserved0 [31:01] */
+#define BCHP_TIMER_WDCRS_reserved0_MASK                            0xfffffffe
+#define BCHP_TIMER_WDCRS_reserved0_SHIFT                           1
+
+/* TIMER :: WDCRS :: WDCR [00:00] */
+#define BCHP_TIMER_WDCRS_WDCR_MASK                                 0x00000001
+#define BCHP_TIMER_WDCRS_WDCR_SHIFT                                0
+#define BCHP_TIMER_WDCRS_WDCR_DEFAULT                              0
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uarta.h b/include/linux/brcmstb/7358a0/bchp_uarta.h
new file mode 100644
index 000000000000..cfc3fcf031a7
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:44:58 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:23p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 1
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                1
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                1
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uartb.h b/include/linux/brcmstb/7358a0/bchp_uartb.h
new file mode 100644
index 000000000000..bfaf8d6fd6d5
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:03:36 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_uartc.h b/include/linux/brcmstb/7358a0/bchp_uartc.h
new file mode 100644
index 000000000000..ea77c9f1bf82
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 10:54:53 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..eba3dd80d38e
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:40:10 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:23p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   1
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  1
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       3
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       10
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     1
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     40
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                786464
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                2
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 4
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               9994
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          1
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/bchp_wktmr.h b/include/linux/brcmstb/7358a0/bchp_wktmr.h
new file mode 100644
index 000000000000..a2b07ef5c47e
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2011, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Sep 19 21:36:59 2011
+ *                 MD5 Checksum         e020a976c1177b900eff0f3d00f22e40
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/3   9/20/11 12:26p pntruong
+ * SW7358-127: Added a1 and synced with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               27000000
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7358a0/brcmirq.h b/include/linux/brcmstb/7358a0/brcmirq.h
new file mode 100644
index 000000000000..629b174fd189
--- /dev/null
+++ b/include/linux/brcmstb/7358a0/brcmirq.h
@@ -0,0 +1,37 @@
+/*
+ * 7358a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..9bf2b2819baf
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:24a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_hys_en [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_MASK     0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_SHIFT    0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_DEFAULT  0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..aa67f146892f
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,651 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..f4e7e25ff8e9
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1107 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_bspi.h b/include/linux/brcmstb/7360a0/bchp_bspi.h
new file mode 100644
index 000000000000..35cd173db469
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_bspi_raf.h b/include/linux/brcmstb/7360a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..22407cc13912
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_clkgen.h b/include/linux/brcmstb/7360a0/bchp_clkgen.h
new file mode 100644
index 000000000000..097fbb9bac65
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_clkgen.h
@@ -0,0 +1,4636 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_clkgen.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:41a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420088 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042009c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a4 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200e8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004200fc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420100 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420104 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420114 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420118 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042011c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420120 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042012c /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420168 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x0042016c /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420170 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x00420174 /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420178 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x0042017c /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420180 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420184 /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420188 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x0042018c /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420190 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x00420194 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x00420198 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x0042019c /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a0 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201ac /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b0 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201ec /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201f0 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x004201f4 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201fc /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420200 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420204 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420208 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x0042020c /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420210 /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420214 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420218 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0042021c /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420220 /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420224 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420228 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x0042022c /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420230 /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420234 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420238 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x0042023c /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x00420240 /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420244 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420248 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0042024c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x00420250 /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420254 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420258 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x0042025c /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x00420260 /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420264 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420268 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x0042026c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420274 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420278 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042027c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420280 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420284 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420288 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042028c /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x00420290 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420294 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420298 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x0042029c /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202a0 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202a4 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202a8 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202ac /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202b0 /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202b4 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202b8 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202bc /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202c0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Sata3 memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202c8 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL         0x004202cc /* Sata3 top PLL Ref Sel */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202d0 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202d4 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202d8 /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202dc /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202e0 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202e4 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202e8 /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202ec /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202f0 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202f4 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202f8 /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x00420300 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x00420304 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420308 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420310 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420314 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420318 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042031c /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420320 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420324 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420328 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042032c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420330 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420334 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420338 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x0042033c /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420340 /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420344 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420348 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420354 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420358 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x0042035c /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420360 /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420364 /* Vec aio top power switch memory b */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000032
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      0x00000001
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:08] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 8
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_WAIT_COUNT [07:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_MASK 0x000000fc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_SHIFT 2
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_DEFAULT 0x0000000f
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     0x00000001
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff8
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            3
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_FUNC_30_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_PLLREF_SEL - Sata3 top PLL Ref Sel
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_SHIFT           1
+
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: SATA_TOP_PLLREF_SEL [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_MASK  0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_common.h b/include/linux/brcmstb/7360a0/bchp_common.h
new file mode 100644
index 000000000000..a4d4a7333453
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_common.h
@@ -0,0 +1,1969 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 23 03:10:04 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/***************************************************************************
+ *BCM7360_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00b01010 /* RFM_GRB is last */
+#define BCHP_REGISTER_SIZE                                 0x002c0404 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_BSCC_REG_START                                0x00406300
+#define BCHP_BSCC_REG_END                                  0x00406354
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_KBD3_REG_START                                0x00408940
+#define BCHP_KBD3_REG_END                                  0x0040897c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410410
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x00420364
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042349c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x00680080
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00dc
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_CWC_REG_START                             0x00700600
+#define BCHP_SDS_CWC_REG_END                               0x00700694
+#define BCHP_SDS_MISC_REG_START                            0x00700700
+#define BCHP_SDS_MISC_REG_END                              0x00700798
+#define BCHP_SDS_DSEC_REG_START                            0x00700800
+#define BCHP_SDS_DSEC_REG_END                              0x007008c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700900
+#define BCHP_SDS_TUNER_REG_END                             0x007009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x00702060
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a38000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a38000
+#define BCHP_RFM_SYSCLK_REG_START                          0x00b00000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00b00118
+#define BCHP_RFM_CLK27_REG_START                           0x00b00000
+#define BCHP_RFM_CLK27_REG_END                             0x00b00470
+#define BCHP_RFM_L2_REG_START                              0x00b00c00
+#define BCHP_RFM_L2_REG_END                                0x00b00c2c
+#define BCHP_RFM_GRB_REG_START                             0x00b01000
+#define BCHP_RFM_GRB_REG_END                               0x00b0100c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..3549fcd460c6
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1539 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:43a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000006
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..c7800bb634a5
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:44a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_ebi.h b/include/linux/brcmstb/7360a0/bchp_ebi.h
new file mode 100644
index 000000000000..ef241e78950a
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:47a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..d2b84918793a
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2019 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:55a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_intr2.h b/include/linux/brcmstb/7360a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..89a2bf190fbe
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_mspi.h b/include/linux/brcmstb/7360a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..65e2169d7ee3
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..dabf442f5cfc
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h
new file mode 100644
index 000000000000..855a502546de
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,530 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:57a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_UnSupport          3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_irq0.h b/include/linux/brcmstb/7360a0/bchp_irq0.h
new file mode 100644
index 000000000000..15148a3a0754
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:59a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_irq1.h b/include/linux/brcmstb/7360a0/bchp_irq1.h
new file mode 100644
index 000000000000..a43a82aeb990
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_irq1.h
@@ -0,0 +1,53 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:01:23 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_irq1.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:17p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..8c5d18b68bbc
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:04p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..6c9890dc7dc3
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:25:00 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:05p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_misb_bridge.h b/include/linux/brcmstb/7360a0/bchp_misb_bridge.h
new file mode 100644
index 000000000000..f44fd74ea2b1
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_misb_bridge.h
@@ -0,0 +1,126 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_misb_bridge.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:07p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT       0x0041040c /* Write Gathering Mode & Timeout. */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE         0x00410410 /* MISB Split Mode */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0x00000000
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 0x00000004
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+/***************************************************************************
+ *WG_MODE_N_TIMEOUT - Write Gathering Mode & Timeout.
+ ***************************************************************************/
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: reserved0 [31:10] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_MASK          0xfffffc00
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_reserved0_SHIFT         10
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: MODE [09:08] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MASK               0x00000300
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_SHIFT              8
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_DEFAULT            0x00000000
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_0             0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_1             1
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_MODE_MODE_2             2
+
+/* MISB_BRIDGE :: WG_MODE_N_TIMEOUT :: TIMEOUT [07:00] */
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_MASK            0x000000ff
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_SHIFT           0
+#define BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT_TIMEOUT_DEFAULT         0x00000064
+
+/***************************************************************************
+ *MISB_SPLIT_MODE - MISB Split Mode
+ ***************************************************************************/
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: reserved0 [31:01] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_MASK            0xfffffffe
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_reserved0_SHIFT           1
+
+/* MISB_BRIDGE :: MISB_SPLIT_MODE :: SPLIT_MODE [00:00] */
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_MASK           0x00000001
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_SHIFT          0
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DEFAULT        0x00000000
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_ENABLE         1
+#define BCHP_MISB_BRIDGE_MISB_SPLIT_MODE_SPLIT_MODE_DISABLE        0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_nand.h b/include/linux/brcmstb/7360a0/bchp_nand.h
new file mode 100644
index 000000000000..6ad6a8eb1b92
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:09p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h
new file mode 100644
index 000000000000..8b921ce667d3
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:19p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..72e35553fd64
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,627 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Apr 23 03:10:13 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00410138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: CFG_RESERVED [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_MASK          0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_SHIFT         29
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_CFG_RESERVED_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000002
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000064
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       31
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_MASK 0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_SHIFT 30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [29:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x3ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a7
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..bbbc75778674
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6201 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Fri Jan 27 16:43:37 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sun_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/3   1/27/12 5:26p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404164 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x73600000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x73600000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000007
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_RSVD_MPOD_M_SDI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_RSVD_MPOD_M_SDO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_RSVD_MPOD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_RSVD_MPOD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xffc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_timer.h b/include/linux/brcmstb/7360a0/bchp_timer.h
new file mode 100644
index 000000000000..65a3318a6373
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_timer.h
@@ -0,0 +1,327 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:32p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uarta.h b/include/linux/brcmstb/7360a0/bchp_uarta.h
new file mode 100644
index 000000000000..3c5e61a8bb62
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uartb.h b/include/linux/brcmstb/7360a0/bchp_uartb.h
new file mode 100644
index 000000000000..bfaf8d6fd6d5
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uartb.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 11:03:36 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartb.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_uartc.h b/include/linux/brcmstb/7360a0/bchp_uartc.h
new file mode 100644
index 000000000000..ea77c9f1bf82
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_uartc.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2010, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Mon Aug 16 10:54:53 2010
+ *                 MD5 Checksum         442d8de773a92e76786307c9f37b5c82
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7358/rdb/a0/bchp_uartc.h $
+ * 
+ * Hydra_Software_Devel/2   8/16/10 12:22p pntruong
+ * SW7358-2: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..e116fa226117
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/bchp_wktmr.h b/include/linux/brcmstb/7360a0/bchp_wktmr.h
new file mode 100644
index 000000000000..e0d95f7ebb0c
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:38p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7360a0/brcmirq.h b/include/linux/brcmstb/7360a0/brcmirq.h
new file mode 100644
index 000000000000..b899a30b2f54
--- /dev/null
+++ b/include/linux/brcmstb/7360a0/brcmirq.h
@@ -0,0 +1,39 @@
+/*
+ * 7360a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_SATA		87
+#define BRCM_IRQ_SDIO0		83
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h b/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h
new file mode 100644
index 000000000000..9bf2b2819baf
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_ctrl.h
@@ -0,0 +1,1578 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:24a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_CTRL_H__
+#define BCHP_AON_CTRL_H__
+
+/***************************************************************************
+ *AON_CTRL - AON Control Registers
+ ***************************************************************************/
+#define BCHP_AON_CTRL_RESET_CTRL                 0x00408000 /* Reset Control register for AON */
+#define BCHP_AON_CTRL_PM_CTRL                    0x00408004 /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_STATUS                  0x00408008 /* Status register for Power Controller */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS        0x0040800c /* Power Management IRQ input status */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT         0x00408010 /* Power Management Wait counter in place of Wait for MIPS IRQ */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER        0x00408014 /* Deep Standby Assertion Timer */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER         0x00408018 /* Deep Standby Wakeup Timer */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE    0x0040801c /* Control register for Power Controller */
+#define BCHP_AON_CTRL_PM_LED_CTRL                0x00408020 /* LED set control register */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES     0x00408024 /* LED set control register */
+#define BCHP_AON_CTRL_HLCD_CTRL                  0x00408030 /* HW LED Clock Driver Control */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER    0x00408034 /* Second Fraction Counter Initial value */
+#define BCHP_AON_CTRL_TIME_COUNTER               0x00408038 /* Hour/Minute Counter Initial value */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0           0x0040803c /* Digit Code for digit 0, 1, 2, 3 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1           0x00408040 /* Digit Code for digit 4, 5, 6, 7 */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2           0x00408044 /* Digit Code for digit 8, 9 */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET      0x00408048 /* Hour MSD/LSD and minute MSD/LSD address offset */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL            0x0040804c /* LED status control */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0             0x00408050 /* General control register 0 */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0           0x00408054 /* General status register 0 */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0     0x00408058 /* General control register without scan 0 */
+#define BCHP_AON_CTRL_SPARE_CTRL_0               0x00408060 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_SPARE_CTRL_1               0x00408064 /* Spare control bits reserved for future use */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH          0x00408068 /* Scratch register */
+#define BCHP_AON_CTRL_RESET_HISTORY              0x0040806c /* Reset History Register For AON */
+#define BCHP_AON_CTRL_NMI_CTRL                   0x00408070 /* Control register for NMI */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL           0x00408074 /* Ana xtal low cur 40g m7fc gisb control */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL         0x00408078 /* Test_mode control register */
+#define BCHP_AON_CTRL_SUB_TEST_MODE              0x0040807c /* Register source for sub_test_mode */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE          0x00408080 /* Final latched testmode value */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE      0x00408084 /* Final latched sub-testmode value */
+#define BCHP_AON_CTRL_PM_INITIATE                0x00408088 /* Power down initiate */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS             0x0040808c /* Power up restore */
+
+/***************************************************************************
+ *RESET_CTRL - Reset Control register for AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_CTRL :: reserved0 [31:04] */
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_MASK                    0xfffffff0
+#define BCHP_AON_CTRL_RESET_CTRL_reserved0_SHIFT                   4
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [03:03] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000008
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 3
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_lock_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_enable [02:02] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_MASK     0x00000004
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT    2
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_enable_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: front_panel_reset_polarity [01:01] */
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK   0x00000002
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT  1
+#define BCHP_AON_CTRL_RESET_CTRL_front_panel_reset_polarity_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK          0x00000001
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_SHIFT         0
+#define BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PM_CTRL - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_CTRL :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_MASK                       0xffffff00
+#define BCHP_AON_CTRL_PM_CTRL_reserved0_SHIFT                      8
+
+/* AON_CTRL :: PM_CTRL :: min_s3_width_timer_bypass [07:07] */
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_MASK       0x00000080
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_SHIFT      7
+#define BCHP_AON_CTRL_PM_CTRL_min_s3_width_timer_bypass_DEFAULT    0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_fast_power_down [06:06] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK              0x00000040
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_SHIFT             6
+#define BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_DEFAULT           0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_warm_boot [05:05] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_MASK                    0x00000020
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_SHIFT                   5
+#define BCHP_AON_CTRL_PM_CTRL_pm_warm_boot_DEFAULT                 0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_deep_standby [04:04] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK                 0x00000010
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_SHIFT                4
+#define BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_DEFAULT              0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK         0x00000008
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT        3
+#define BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_DEFAULT      0x00000001
+
+/* AON_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK          0x00000004
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT         2
+#define BCHP_AON_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_DEFAULT       0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK             0x00000002
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT            1
+#define BCHP_AON_CTRL_PM_CTRL_pm_enable_pll_pwrdn_DEFAULT          0x00000000
+
+/* AON_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK                  0x00000001
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT                 0
+#define BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PM_STATUS - Status register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_STATUS :: pm_wait_count_upper_bits [31:26] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_MASK      0xfc000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_count_upper_bits_SHIFT     26
+
+/* AON_CTRL :: PM_STATUS :: pm_wait_counter_active [25:25] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_MASK        0x02000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_wait_counter_active_SHIFT       25
+
+/* AON_CTRL :: PM_STATUS :: pm_s3_wakeup_reset_ [24:24] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__MASK           0x01000000
+#define BCHP_AON_CTRL_PM_STATUS_pm_s3_wakeup_reset__SHIFT          24
+
+/* AON_CTRL :: PM_STATUS :: pm_boundary_scan_request [23:23] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_MASK      0x00800000
+#define BCHP_AON_CTRL_PM_STATUS_pm_boundary_scan_request_SHIFT     23
+
+/* AON_CTRL :: PM_STATUS :: pm_fast_pd_precharge_valid [22:22] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_MASK    0x00400000
+#define BCHP_AON_CTRL_PM_STATUS_pm_fast_pd_precharge_valid_SHIFT   22
+
+/* AON_CTRL :: PM_STATUS :: pm_led_out [21:21] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_MASK                    0x00200000
+#define BCHP_AON_CTRL_PM_STATUS_pm_led_out_SHIFT                   21
+
+/* AON_CTRL :: PM_STATUS :: pm_standby_b [20:20] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_MASK                  0x00100000
+#define BCHP_AON_CTRL_PM_STATUS_pm_standby_b_SHIFT                 20
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs_ng [19:19] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_MASK           0x00080000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_ng_SHIFT          19
+
+/* AON_CTRL :: PM_STATUS :: pm_ignore_inputs [18:18] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_MASK              0x00040000
+#define BCHP_AON_CTRL_PM_STATUS_pm_ignore_inputs_SHIFT             18
+
+/* AON_CTRL :: PM_STATUS :: pm_rst_clock_div [17:17] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_MASK              0x00020000
+#define BCHP_AON_CTRL_PM_STATUS_pm_rst_clock_div_SHIFT             17
+
+/* AON_CTRL :: PM_STATUS :: pm_pwrdn_pll_req [16:16] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_MASK              0x00010000
+#define BCHP_AON_CTRL_PM_STATUS_pm_pwrdn_pll_req_SHIFT             16
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_xtal_clocks [15:15] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_MASK            0x00008000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_xtal_clocks_SHIFT           15
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_all_clocks [14:14] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_MASK             0x00004000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_all_clocks_SHIFT            14
+
+/* AON_CTRL :: PM_STATUS :: pm_dphy_standby [13:13] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_MASK               0x00002000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dphy_standby_SHIFT              13
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_cpu_clock [12:12] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_MASK              0x00001000
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_cpu_clock_SHIFT             12
+
+/* AON_CTRL :: PM_STATUS :: pm_dis_avd_rptd_clock [11:11] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_MASK         0x00000800
+#define BCHP_AON_CTRL_PM_STATUS_pm_dis_avd_rptd_clock_SHIFT        11
+
+/* AON_CTRL :: PM_STATUS :: pm_power_ctrl_disable [10:10] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_MASK         0x00000400
+#define BCHP_AON_CTRL_PM_STATUS_pm_power_ctrl_disable_SHIFT        10
+
+/* AON_CTRL :: PM_STATUS :: pm_pll_lock [09:09] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_MASK                   0x00000200
+#define BCHP_AON_CTRL_PM_STATUS_pm_pll_lock_SHIFT                  9
+
+/* AON_CTRL :: PM_STATUS :: pm_dram_ready_for_pwrdn [08:08] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_MASK       0x00000100
+#define BCHP_AON_CTRL_PM_STATUS_pm_dram_ready_for_pwrdn_SHIFT      8
+
+/* AON_CTRL :: PM_STATUS :: pm_bsp_ready_for_pwrdn [07:07] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK        0x00000080
+#define BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_SHIFT       7
+
+/* AON_CTRL :: PM_STATUS :: pm_mips_ready_for_pwrdn [06:06] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_MASK       0x00000040
+#define BCHP_AON_CTRL_PM_STATUS_pm_mips_ready_for_pwrdn_SHIFT      6
+
+/* AON_CTRL :: PM_STATUS :: pm_sec_avd_rptd_clk_disable [05:05] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_MASK   0x00000020
+#define BCHP_AON_CTRL_PM_STATUS_pm_sec_avd_rptd_clk_disable_SHIFT  5
+
+/* AON_CTRL :: PM_STATUS :: pm_state [04:00] */
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_MASK                      0x0000001f
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_SHIFT                     0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_ACTIVE                 0
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_PWRDN_RDY              1
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_AVD_RPTD       2
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DISABLE_CPU            3
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_STANDBY  4
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY                5
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_STANDBY_WITH_PLLS_ON   6
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_RESET_216_108_CLKS     7
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_TRANSITION_TO_ACTIVE   8
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_FAST_PWRDN             9
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S1  10
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_COLD_ENTRY_S2 11
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_WARM_ENTRY_S2 12
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_ENTRY_S3  13
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY           14
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S1   15
+#define BCHP_AON_CTRL_PM_STATUS_pm_state_PM_DEEP_STANDBY_EXIT_S2   16
+
+/***************************************************************************
+ *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
+ ***************************************************************************/
+/* AON_CTRL :: PM_IRQ_INPUT_STATUS :: pm_irq_input_status [31:00] */
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_MASK 0xffffffff
+#define BCHP_AON_CTRL_PM_IRQ_INPUT_STATUS_pm_irq_input_status_SHIFT 0
+
+/***************************************************************************
+ *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
+ ***************************************************************************/
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK            0xffff0000
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT           16
+
+/* AON_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK  0x0000ffff
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_DEFAULT 0x00000010
+
+/***************************************************************************
+ *PM_S3_STANDBY_TIMER - Deep Standby Assertion Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_MASK           0xf8000000
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_reserved0_SHIFT          27
+
+/* AON_CTRL :: PM_S3_STANDBY_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_MASK 0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_STANDBY_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_S3_WAKEUP_TIMER - Deep Standby Wakeup Timer
+ ***************************************************************************/
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: reserved0 [31:27] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_MASK            0xf8000000
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_reserved0_SHIFT           27
+
+/* AON_CTRL :: PM_S3_WAKEUP_TIMER :: counter_start_value [26:00] */
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_MASK  0x07ffffff
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_SHIFT 0
+#define BCHP_AON_CTRL_PM_S3_WAKEUP_TIMER_counter_start_value_DEFAULT 0x00083d60
+
+/***************************************************************************
+ *PM_FAST_PWRDN_PRECHARGE - Control register for Power Controller
+ ***************************************************************************/
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: reserved0 [31:24] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_MASK       0xff000000
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_reserved0_SHIFT      24
+
+/* AON_CTRL :: PM_FAST_PWRDN_PRECHARGE :: pm_fast_power_down_precharge [23:00] */
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_MASK 0x00ffffff
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_SHIFT 0
+#define BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE_pm_fast_power_down_precharge_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_LED_CTRL - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_CTRL :: reserved0 [31:03] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_MASK                   0xfffffff8
+#define BCHP_AON_CTRL_PM_LED_CTRL_reserved0_SHIFT                  3
+
+/* AON_CTRL :: PM_LED_CTRL :: led_status [02:02] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_MASK                  0x00000004
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_status_SHIFT                 2
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_on [01:01] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK                 0x00000002
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_SHIFT                1
+
+/* AON_CTRL :: PM_LED_CTRL :: led_turn_off [00:00] */
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_MASK                0x00000001
+#define BCHP_AON_CTRL_PM_LED_CTRL_led_turn_off_SHIFT               0
+
+/***************************************************************************
+ *PM_LED_AUTO_ON_ENABLES - LED set control register
+ ***************************************************************************/
+/* AON_CTRL :: PM_LED_AUTO_ON_ENABLES :: led_status [31:00] */
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_MASK       0xffffffff
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_SHIFT      0
+#define BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES_led_status_DEFAULT    0x00000000
+
+/***************************************************************************
+ *HLCD_CTRL - HW LED Clock Driver Control
+ ***************************************************************************/
+/* AON_CTRL :: HLCD_CTRL :: reserved0 [31:02] */
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_MASK                     0xfffffffc
+#define BCHP_AON_CTRL_HLCD_CTRL_reserved0_SHIFT                    2
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable_status [01:01] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_MASK            0x00000002
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_status_SHIFT           1
+
+/* AON_CTRL :: HLCD_CTRL :: hlcd_enable [00:00] */
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_MASK                   0x00000001
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_SHIFT                  0
+#define BCHP_AON_CTRL_HLCD_CTRL_hlcd_enable_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SECOND_FRACTION_COUNTER - Second Fraction Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: reserved0 [31:25] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_MASK       0xfe000000
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_reserved0_SHIFT      25
+
+/* AON_CTRL :: SECOND_FRACTION_COUNTER :: second_fraction_counter_init [24:00] */
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_MASK 0x01ffffff
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_SHIFT 0
+#define BCHP_AON_CTRL_SECOND_FRACTION_COUNTER_second_fraction_counter_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TIME_COUNTER - Hour/Minute Counter Initial value
+ ***************************************************************************/
+/* AON_CTRL :: TIME_COUNTER :: reserved0 [31:20] */
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_MASK                  0xfff00000
+#define BCHP_AON_CTRL_TIME_COUNTER_reserved0_SHIFT                 20
+
+/* AON_CTRL :: TIME_COUNTER :: hour_display_mode [19:19] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_MASK          0x00080000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_SHIFT         19
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_display_mode_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: mode_12h_24h_init [18:18] */
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_MASK          0x00040000
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_SHIFT         18
+#define BCHP_AON_CTRL_TIME_COUNTER_mode_12h_24h_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: am_pm_counter_init [17:17] */
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_MASK         0x00020000
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_SHIFT        17
+#define BCHP_AON_CTRL_TIME_COUNTER_am_pm_counter_init_DEFAULT      0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: hour_counter_init [16:12] */
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_MASK          0x0001f000
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_SHIFT         12
+#define BCHP_AON_CTRL_TIME_COUNTER_hour_counter_init_DEFAULT       0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: minute_counter_init [11:06] */
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_MASK        0x00000fc0
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_SHIFT       6
+#define BCHP_AON_CTRL_TIME_COUNTER_minute_counter_init_DEFAULT     0x00000000
+
+/* AON_CTRL :: TIME_COUNTER :: second_counter_init [05:00] */
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_MASK        0x0000003f
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_SHIFT       0
+#define BCHP_AON_CTRL_TIME_COUNTER_second_counter_init_DEFAULT     0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_0 - Digit Code for digit 0, 1, 2, 3
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_3 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_3_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_2 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_2_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_1 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_1_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_0 :: digit_code_0 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_0_digit_code_0_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_1 - Digit Code for digit 4, 5, 6, 7
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_7 [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_MASK           0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_SHIFT          24
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_7_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_6 [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_MASK           0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_SHIFT          16
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_6_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_5 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_5_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_1 :: digit_code_4 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_1_digit_code_4_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_CODE_2 - Digit Code for digit 8, 9
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: reserved0 [31:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_MASK              0xffff0000
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_reserved0_SHIFT             16
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_9 [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_MASK           0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_SHIFT          8
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_9_DEFAULT        0x00000000
+
+/* AON_CTRL :: LED_DIGIT_CODE_2 :: digit_code_8 [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_MASK           0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_SHIFT          0
+#define BCHP_AON_CTRL_LED_DIGIT_CODE_2_digit_code_8_DEFAULT        0x00000000
+
+/***************************************************************************
+ *LED_DIGIT_ADDR_OFFSET - Hour MSD/LSD and minute MSD/LSD address offset
+ ***************************************************************************/
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_msd_addr_offset [31:24] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_MASK 0xff000000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_SHIFT 24
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_msd_addr_offset_DEFAULT 0x00000020
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: hour_lsd_addr_offset [23:16] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_MASK 0x00ff0000
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_SHIFT 16
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_hour_lsd_addr_offset_DEFAULT 0x00000024
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_msd_addr_offset [15:08] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_MASK 0x0000ff00
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_SHIFT 8
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_msd_addr_offset_DEFAULT 0x00000018
+
+/* AON_CTRL :: LED_DIGIT_ADDR_OFFSET :: minute_lsd_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_MASK 0x000000ff
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_SHIFT 0
+#define BCHP_AON_CTRL_LED_DIGIT_ADDR_OFFSET_minute_lsd_addr_offset_DEFAULT 0x0000001c
+
+/***************************************************************************
+ *LED_STATUS_CTRL - LED status control
+ ***************************************************************************/
+/* AON_CTRL :: LED_STATUS_CTRL :: reserved0 [31:28] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_MASK               0xf0000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_reserved0_SHIFT              28
+
+/* AON_CTRL :: LED_STATUS_CTRL :: hlcd_state [27:25] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_MASK              0x0e000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_SHIFT             25
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_IDLE         0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_COUNT        1
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_LSD 2
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_MINUTE_MSD 3
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_LSD 4
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_HOUR_MSD 5
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_hlcd_state_HLCD_PROGRAM_STATUS 6
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_update_enable [24:24] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_MASK    0x01000000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_SHIFT   24
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_update_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_mask [23:12] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_MASK             0x00fff000
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_SHIFT            12
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_mask_DEFAULT          0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_bit_offset [11:08] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_MASK       0x00000f00
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_SHIFT      8
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_bit_offset_DEFAULT    0x00000000
+
+/* AON_CTRL :: LED_STATUS_CTRL :: status_addr_offset [07:00] */
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_MASK      0x000000ff
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_SHIFT     0
+#define BCHP_AON_CTRL_LED_STATUS_CTRL_status_addr_offset_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK         0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT        31
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK         0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT        30
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK         0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT        29
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK         0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT        28
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK         0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT        27
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK         0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT        26
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK         0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT        25
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK         0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT        24
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK         0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT        23
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK         0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT        22
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK         0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT        21
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK         0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT        20
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK         0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT        19
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK         0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT        18
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK         0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT        17
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK         0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT        16
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT      0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK         0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT        15
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK         0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT        14
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK         0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT        13
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK         0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT        12
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK         0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT        11
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK         0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT        10
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT      0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK          0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT         9
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK          0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT         8
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK          0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT         7
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK          0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT         6
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK          0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT         5
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK          0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT         4
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK          0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT         3
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK          0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT         2
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK          0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT         1
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT       0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK          0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT         0
+#define BCHP_AON_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT       0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_MASK              0xffffff00
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_reserved0_SHIFT             8
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_MASK      0x00000080
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT     7
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_MASK      0x00000040
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT     6
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_MASK      0x00000020
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT     5
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_MASK      0x00000010
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT     4
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_MASK      0x00000008
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT     3
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_MASK      0x00000004
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT     2
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_MASK      0x00000002
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT     1
+
+/* AON_CTRL :: GENERAL_STATUS_0 :: ejtag_ce_wakeup_event [00:00] */
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_MASK  0x00000001
+#define BCHP_AON_CTRL_GENERAL_STATUS_0_ejtag_ce_wakeup_event_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_31 [31:31] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_MASK 0x80000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_SHIFT 31
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_31_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_30 [30:30] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_MASK 0x40000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_SHIFT 30
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_30_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_29 [29:29] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_MASK 0x20000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_SHIFT 29
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_29_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_28 [28:28] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_MASK 0x10000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_SHIFT 28
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_28_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_27 [27:27] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_MASK 0x08000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_SHIFT 27
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_27_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_26 [26:26] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_MASK 0x04000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_SHIFT 26
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_26_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_25 [25:25] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_MASK 0x02000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_SHIFT 25
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_25_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_24 [24:24] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_MASK 0x01000000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_SHIFT 24
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_24_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_23 [23:23] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_MASK 0x00800000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_SHIFT 23
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_23_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_22 [22:22] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_MASK 0x00400000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_SHIFT 22
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_22_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_21 [21:21] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_MASK 0x00200000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_SHIFT 21
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_21_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_20 [20:20] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_MASK 0x00100000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_SHIFT 20
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_20_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_17 [17:17] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_MASK 0x00020000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_SHIFT 17
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_17_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_16 [16:16] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_MASK 0x00010000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_SHIFT 16
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_16_DEFAULT 0x00000001
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_15 [15:15] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_MASK 0x00008000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_SHIFT 15
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_15_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_14 [14:14] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_MASK 0x00004000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_SHIFT 14
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_14_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_13 [13:13] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_MASK 0x00002000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_SHIFT 13
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_13_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_12 [12:12] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_MASK 0x00001000
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_SHIFT 12
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_12_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_5 [05:05] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_MASK 0x00000020
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_SHIFT 5
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_5_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_4 [04:04] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_MASK 0x00000010
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_SHIFT 4
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_4_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_3 [03:03] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_MASK 0x00000008
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_SHIFT 3
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_3_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_2 [02:02] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_MASK 0x00000004
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_SHIFT 2
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_2_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_hys_en [00:00] */
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_MASK     0x00000001
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_SHIFT    0
+#define BCHP_AON_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_hys_en_DEFAULT  0x00000001
+
+/***************************************************************************
+ *SPARE_CTRL_0 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_0 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_0_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL_1 - Spare control bits reserved for future use
+ ***************************************************************************/
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_31 [31:31] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_MASK              0x80000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_SHIFT             31
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_31_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_30 [30:30] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_MASK              0x40000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_SHIFT             30
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_30_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_29 [29:29] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_MASK              0x20000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_SHIFT             29
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_29_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_28 [28:28] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_MASK              0x10000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_SHIFT             28
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_28_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_27 [27:27] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_MASK              0x08000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_SHIFT             27
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_27_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_26 [26:26] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_MASK              0x04000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_SHIFT             26
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_26_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_25 [25:25] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_MASK              0x02000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_SHIFT             25
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_25_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_24 [24:24] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_MASK              0x01000000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_SHIFT             24
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_24_DEFAULT           0x00000001
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_23 [23:23] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_MASK              0x00800000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_SHIFT             23
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_23_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_22 [22:22] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_MASK              0x00400000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_SHIFT             22
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_22_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_21 [21:21] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_MASK              0x00200000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_SHIFT             21
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_21_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_20 [20:20] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_MASK              0x00100000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_SHIFT             20
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_20_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_19 [19:19] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_MASK              0x00080000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_SHIFT             19
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_19_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_18 [18:18] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_MASK              0x00040000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_SHIFT             18
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_18_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_17 [17:17] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_MASK              0x00020000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_SHIFT             17
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_17_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_16 [16:16] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_MASK              0x00010000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_SHIFT             16
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_16_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_15 [15:15] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_MASK              0x00008000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_SHIFT             15
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_15_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_14 [14:14] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_MASK              0x00004000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_SHIFT             14
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_14_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_13 [13:13] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_MASK              0x00002000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_SHIFT             13
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_13_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_12 [12:12] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_MASK              0x00001000
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_SHIFT             12
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_12_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_11 [11:11] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_MASK              0x00000800
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_SHIFT             11
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_11_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_10 [10:10] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_MASK              0x00000400
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_SHIFT             10
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_10_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_09 [09:09] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_MASK              0x00000200
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_SHIFT             9
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_09_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_08 [08:08] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_MASK              0x00000100
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_SHIFT             8
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_08_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_07 [07:07] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_MASK              0x00000080
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_SHIFT             7
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_07_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_06 [06:06] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_MASK              0x00000040
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_SHIFT             6
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_06_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_05 [05:05] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_MASK              0x00000020
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_SHIFT             5
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_05_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_04 [04:04] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_MASK              0x00000010
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_SHIFT             4
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_04_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_03 [03:03] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_MASK              0x00000008
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_SHIFT             3
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_03_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_02 [02:02] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_MASK              0x00000004
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_SHIFT             2
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_02_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_01 [01:01] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_MASK              0x00000002
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_SHIFT             1
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_01_DEFAULT           0x00000000
+
+/* AON_CTRL :: SPARE_CTRL_1 :: spare_ctrl_00 [00:00] */
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_MASK              0x00000001
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_SHIFT             0
+#define BCHP_AON_CTRL_SPARE_CTRL_1_spare_ctrl_00_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* AON_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK     0xffffffff
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT    0
+#define BCHP_AON_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT  0x00000000
+
+/***************************************************************************
+ *RESET_HISTORY - Reset History Register For AON
+ ***************************************************************************/
+/* AON_CTRL :: RESET_HISTORY :: reserved0 [31:19] */
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_MASK                 0xfff80000
+#define BCHP_AON_CTRL_RESET_HISTORY_reserved0_SHIFT                19
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK    0x00040000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT   18
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_1_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK    0x00020000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT   17
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_level_reset_0_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK     0x00010000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT    16
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [15:15] */
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK     0x00008000
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT    15
+#define BCHP_AON_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [14:14] */
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK           0x00004000
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT          14
+#define BCHP_AON_CTRL_RESET_HISTORY_cpu_ejtag_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overtemp_reset [13:13] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_MASK            0x00002000
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_SHIFT           13
+#define BCHP_AON_CTRL_RESET_HISTORY_overtemp_reset_DEFAULT         0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_MASK         0x00001000
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT        12
+#define BCHP_AON_CTRL_RESET_HISTORY_overvoltage_reset_DEFAULT      0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: undervoltage_reset [11:11] */
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_MASK        0x00000800
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT       11
+#define BCHP_AON_CTRL_RESET_HISTORY_undervoltage_reset_DEFAULT     0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_dl_sw_reset [10:10] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK      0x00000400
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT     10
+#define BCHP_AON_CTRL_RESET_HISTORY_security_dl_sw_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: security_master_reset [09:09] */
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_MASK     0x00000200
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_SHIFT    9
+#define BCHP_AON_CTRL_RESET_HISTORY_security_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: software_master_reset [08:08] */
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_MASK     0x00000100
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_SHIFT    8
+#define BCHP_AON_CTRL_RESET_HISTORY_software_master_reset_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [07:07] */
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK       0x00000080
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT      7
+#define BCHP_AON_CTRL_RESET_HISTORY_pcie_hot_boot_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: watchdog_timer_reset [06:06] */
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK      0x00000040
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT     6
+#define BCHP_AON_CTRL_RESET_HISTORY_watchdog_timer_reset_DEFAULT   0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: smartcard_insert_reset [05:05] */
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK    0x00000020
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT   5
+#define BCHP_AON_CTRL_RESET_HISTORY_smartcard_insert_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: s3_wakeup_reset [04:04] */
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK           0x00000010
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_SHIFT          4
+#define BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_DEFAULT        0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [03:03] */
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK    0x00000008
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT   3
+#define BCHP_AON_CTRL_RESET_HISTORY_front_panel_4sec_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: tap_in_system_reset [02:02] */
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_MASK       0x00000004
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_SHIFT      2
+#define BCHP_AON_CTRL_RESET_HISTORY_tap_in_system_reset_DEFAULT    0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_MASK     0x00000002
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT    1
+#define BCHP_AON_CTRL_RESET_HISTORY_main_chip_reset_input_DEFAULT  0x00000000
+
+/* AON_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_MASK            0x00000001
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_SHIFT           0
+#define BCHP_AON_CTRL_RESET_HISTORY_power_on_reset_DEFAULT         0x00000001
+
+/***************************************************************************
+ *NMI_CTRL - Control register for NMI
+ ***************************************************************************/
+/* AON_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_MASK                0x80000000
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_SHIFT               31
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_config_lock_DEFAULT             0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: reserved0 [30:03] */
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_MASK                      0x7ffffff8
+#define BCHP_AON_CTRL_NMI_CTRL_reserved0_SHIFT                     3
+
+/* AON_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_MASK                0x00000004
+#define BCHP_AON_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT               2
+
+/* AON_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_MASK            0x00000002
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT           1
+#define BCHP_AON_CTRL_NMI_CTRL_config_nmi_polarity_DEFAULT         0x00000000
+
+/* AON_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_MASK                0x00000001
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT               0
+#define BCHP_AON_CTRL_NMI_CTRL_disable_pad_nmi_DEFAULT             0x00000001
+
+/***************************************************************************
+ *ANA_XTAL_CONTROL - Ana xtal low cur 40g m7fc gisb control
+ ***************************************************************************/
+/* AON_CTRL :: ANA_XTAL_CONTROL :: reserved0 [31:07] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_MASK              0xffffff80
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_reserved0_SHIFT             7
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_test_select_gisb_control [06:06] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_MASK 0x00000040
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_SHIFT 6
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_test_select_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_select_current_gisb_control [05:05] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_MASK 0x00000020
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_SHIFT 5
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_select_current_gisb_control_DEFAULT 0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_cml_sel_pd [04:03] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_MASK         0x00000018
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_SHIFT        3
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_cml_sel_pd_DEFAULT      0x00000000
+
+/* AON_CTRL :: ANA_XTAL_CONTROL :: osc_d2cbias_gisb_control [02:00] */
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_MASK 0x00000007
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_SHIFT 0
+#define BCHP_AON_CTRL_ANA_XTAL_CONTROL_osc_d2cbias_gisb_control_DEFAULT 0x00000004
+
+/***************************************************************************
+ *SUB_TEST_MODE_CTRL - Test_mode control register
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: reserved0 [31:01] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_reserved0_SHIFT           1
+
+/* AON_CTRL :: SUB_TEST_MODE_CTRL :: use_sub_test_mode_reg_src [00:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_MASK 0x00000001
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_SHIFT 0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_CTRL_use_sub_test_mode_reg_src_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_TEST_MODE - Register source for sub_test_mode
+ ***************************************************************************/
+/* AON_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_MASK                 0xfffffe00
+#define BCHP_AON_CTRL_SUB_TEST_MODE_reserved0_SHIFT                9
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK     0x00000100
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT    8
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [07:07] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK     0x00000080
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT    7
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_DEFAULT  0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK  0x00000040
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK   0x00000020
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT  5
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_DEFAULT 0x00000000
+
+/* AON_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK   0x00000003
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT  0
+#define BCHP_AON_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_DEFAULT 0x00000000
+
+/***************************************************************************
+ *LATCHED_TEST_MODE - Final latched testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK     0xffffffff
+#define BCHP_AON_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT    0
+
+/***************************************************************************
+ *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
+ ***************************************************************************/
+/* AON_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
+#define BCHP_AON_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0
+
+/***************************************************************************
+ *PM_INITIATE - Power down initiate
+ ***************************************************************************/
+/* AON_CTRL :: PM_INITIATE :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_MASK                   0xffffff00
+#define BCHP_AON_CTRL_PM_INITIATE_reserved0_SHIFT                  8
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_7 [07:07] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_MASK               0x00000080
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_SHIFT              7
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_7_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_6 [06:06] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_MASK               0x00000040
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_SHIFT              6
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_6_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_5 [05:05] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_MASK               0x00000020
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_SHIFT              5
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_5_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_4 [04:04] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_MASK               0x00000010
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_SHIFT              4
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_4_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_3 [03:03] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_MASK               0x00000008
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_SHIFT              3
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_3_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_2 [02:02] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_MASK               0x00000004
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_SHIFT              2
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_2_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_1 [01:01] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_MASK               0x00000002
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_SHIFT              1
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_1_DEFAULT            0x00000000
+
+/* AON_CTRL :: PM_INITIATE :: pm_initiate_0 [00:00] */
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_MASK               0x00000001
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_SHIFT              0
+#define BCHP_AON_CTRL_PM_INITIATE_pm_initiate_0_DEFAULT            0x00000000
+
+/***************************************************************************
+ *HOST_MISC_CMDS - Power up restore
+ ***************************************************************************/
+/* AON_CTRL :: HOST_MISC_CMDS :: reserved0 [31:08] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_MASK                0xffffff00
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_reserved0_SHIFT               8
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_7 [07:07] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_MASK         0x00000080
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_SHIFT        7
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_7_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_6 [06:06] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_MASK         0x00000040
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_SHIFT        6
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_6_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_5 [05:05] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_MASK         0x00000020
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_SHIFT        5
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_5_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_4 [04:04] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_MASK         0x00000010
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_SHIFT        4
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_4_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_3 [03:03] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_MASK         0x00000008
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_SHIFT        3
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_3_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: host_misc_cmds_2 [02:02] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_MASK         0x00000004
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_SHIFT        2
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_host_misc_cmds_2_DEFAULT      0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: dram_scram_key_reuse_req [01:01] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_MASK 0x00000002
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_SHIFT 1
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_dram_scram_key_reuse_req_DEFAULT 0x00000000
+
+/* AON_CTRL :: HOST_MISC_CMDS :: pm_restore [00:00] */
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK               0x00000001
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_SHIFT              0
+#define BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_BASE                  0x00408200
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_START                 0
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_END                   127
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_ARRAY_ELEMENT_SIZE          32
+
+/***************************************************************************
+ *SYSTEM_DATA_RAM%i - System Data RAM Address 0..127
+ ***************************************************************************/
+/* AON_CTRL :: SYSTEM_DATA_RAMi :: SYSTEM_DATA_RAM [31:00] */
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_MASK        0xffffffff
+#define BCHP_AON_CTRL_SYSTEM_DATA_RAMi_SYSTEM_DATA_RAM_SHIFT       0
+
+
+#endif /* #ifndef BCHP_AON_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h b/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h
new file mode 100644
index 000000000000..aa67f146892f
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_pin_ctrl.h
@@ -0,0 +1,651 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pin_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PIN_CTRL_H__
+#define BCHP_AON_PIN_CTRL_H__
+
+/***************************************************************************
+ *AON_PIN_CTRL - AON Pinmux Control Registers
+ ***************************************************************************/
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0         0x00408500 /* Pinmux control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1         0x00408504 /* Pinmux control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2         0x00408508 /* Pinmux control register 2 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3         0x0040850c /* Pinmux control register 3 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0     0x00408510 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1     0x00408514 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2     0x00408518 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0     0x0040851c /* Bypass clock unselect register 0 */
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SDS0_DSEC_SELVTOP 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP       7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT        5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES    7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0          2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT        4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01     8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF     1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1    2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00     3
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK       0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT    0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02   1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK      0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT   0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01  1
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK           0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT          0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT        0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0     0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00       1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK          0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT         28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0          4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05     8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT       4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02     6
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST       2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_FSK_RX_BYP_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO        2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB  3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2      4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_FSK_UART_DATA 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SDS0_DSEC_VCTL 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 9
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK         0xf0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT        28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16     5
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK          0x0f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT         24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0    3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT   5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV      6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK          0x00f00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT         20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES      3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD     5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK          0x000f0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT         16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO        3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK          0x0000f000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT         12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON    6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4  7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12      8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK          0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT         8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK          0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT         4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK      2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC       3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B    4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0    5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2  6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10      7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK          0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT       0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14   0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC     2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT   3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED     4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC   6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06     7
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xfffff000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           12
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK             0x00000f00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT            8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK             0x000000f0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT            4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT          0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00         0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL       1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL  2
+
+/* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK         0x0000000f
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT        0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT      0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA   1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3     3
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_08_pad_ctrl [29:28] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_MASK 0x30000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_SHIFT 28
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_08_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [27:26] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x0c000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 26
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [25:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x03000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 24
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003fff
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [23:22] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x00c00000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 22
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [21:20] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00300000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 20
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [19:18] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x000c0000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 18
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [17:16] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x00030000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 16
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [15:14] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x0000c000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 14
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [13:12] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x00003000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 12
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [11:10] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00000c00
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 10
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [09:08] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000300
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 8
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [07:06] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x000000c0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 6
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [05:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x00000030
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 4
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [03:02] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x0000000c
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 2
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [01:00] */
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK        0x00000003
+#define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT       0
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffff0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       4
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000
+
+/* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0
+#define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h b/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h
new file mode 100644
index 000000000000..f4e7e25ff8e9
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_aon_pm_l2.h
@@ -0,0 +1,1107 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_aon_pm_l2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:25a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_AON_PM_L2_H__
+#define BCHP_AON_PM_L2_H__
+
+/***************************************************************************
+ *AON_PM_L2 - AON Power Management L2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_AON_PM_L2_CPU_STATUS                0x00408440 /* CPU interrupt Status Register */
+#define BCHP_AON_PM_L2_CPU_SET                   0x00408444 /* CPU interrupt Set Register */
+#define BCHP_AON_PM_L2_CPU_CLEAR                 0x00408448 /* CPU interrupt Clear Register */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS           0x0040844c /* CPU interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_CPU_MASK_SET              0x00408450 /* CPU interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR            0x00408454 /* CPU interrupt Mask Clear Register */
+#define BCHP_AON_PM_L2_PCI_STATUS                0x00408458 /* PCI interrupt Status Register */
+#define BCHP_AON_PM_L2_PCI_SET                   0x0040845c /* PCI interrupt Set Register */
+#define BCHP_AON_PM_L2_PCI_CLEAR                 0x00408460 /* PCI interrupt Clear Register */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS           0x00408464 /* PCI interrupt Mask Status Register */
+#define BCHP_AON_PM_L2_PCI_MASK_SET              0x00408468 /* PCI interrupt Mask Set Register */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR            0x0040846c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_CPU_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_CPU_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_CPU_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_CPU_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_CPU_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_CPU_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_CPU_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_CPU_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_CPU_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_CPU_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_CPU_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_CPU_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_CPU_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_CPU_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_CPU_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_CPU_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_CPU_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_CPU_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_CPU_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_CPU_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_CPU_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_CPU_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_CPU_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_CPU_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_CPU_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: CPU_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_CPU_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_CPU_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_CPU_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_CPU_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_CPU_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_CPU_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_CPU_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_CPU_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_CPU_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_CPU_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_CPU_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_CPU_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_CPU_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: CPU_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_CPU_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_CPU_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_CPU_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_CPU_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_CPU_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_CPU_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_CPU_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_CPU_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_CPU_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_CPU_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_CPU_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_CPU_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_CPU_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: CPU_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_CPU_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_MASK                   0xffff0000
+#define BCHP_AON_PM_L2_PCI_STATUS_reserved0_SHIFT                  16
+
+/* AON_PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK        0x00008000
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT       15
+#define BCHP_AON_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_MASK                    0x00004000
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_SHIFT                   14
+#define BCHP_AON_PM_L2_PCI_STATUS_FP_RESET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_MASK           0x00002000
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_SHIFT          13
+#define BCHP_AON_PM_L2_PCI_STATUS_BOUNDARY_SCAN_REQ_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_MASK                     0x00001000
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_SHIFT                    12
+#define BCHP_AON_PM_L2_PCI_STATUS_XPT_PMU_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_MASK                         0x00000800
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_SHIFT                        11
+#define BCHP_AON_PM_L2_PCI_STATUS_FTM_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_MASK                   0x00000400
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_SHIFT                  10
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_AFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_MASK                   0x00000200
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_SHIFT                  9
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_TFEC_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_MASK                 0x00000100
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_SHIFT                8
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_1_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_MASK                 0x00000080
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_SHIFT                7
+#define BCHP_AON_PM_L2_PCI_STATUS_SDS0_RCVR_0_DEFAULT              0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_MASK                    0x00000040
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_SHIFT                   6
+#define BCHP_AON_PM_L2_PCI_STATUS_WOL_ENET_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_MASK                        0x00000020
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_SHIFT                       5
+#define BCHP_AON_PM_L2_PCI_STATUS_GPIO_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_MASK                  0x00000010
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_SHIFT                 4
+#define BCHP_AON_PM_L2_PCI_STATUS_NMI_B_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_MASK                  0x00000008
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_SHIFT                 3
+#define BCHP_AON_PM_L2_PCI_STATUS_TIMER_INTR_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_MASK                    0x00000004
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_SHIFT                   2
+#define BCHP_AON_PM_L2_PCI_STATUS_KPD_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_MASK                    0x00000002
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_SHIFT                   1
+#define BCHP_AON_PM_L2_PCI_STATUS_IRR_INTR_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_MASK                    0x00000001
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_SHIFT                   0
+#define BCHP_AON_PM_L2_PCI_STATUS_CEC_INTR_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_MASK                      0xffff0000
+#define BCHP_AON_PM_L2_PCI_SET_reserved0_SHIFT                     16
+
+/* AON_PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK           0x00008000
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT          15
+#define BCHP_AON_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_DEFAULT        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_MASK                       0x00004000
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_SHIFT                      14
+#define BCHP_AON_PM_L2_PCI_SET_FP_RESET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_MASK              0x00002000
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_SHIFT             13
+#define BCHP_AON_PM_L2_PCI_SET_BOUNDARY_SCAN_REQ_DEFAULT           0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_MASK                        0x00001000
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_SHIFT                       12
+#define BCHP_AON_PM_L2_PCI_SET_XPT_PMU_DEFAULT                     0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_SET_FTM_MASK                            0x00000800
+#define BCHP_AON_PM_L2_PCI_SET_FTM_SHIFT                           11
+#define BCHP_AON_PM_L2_PCI_SET_FTM_DEFAULT                         0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_MASK                      0x00000400
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_SHIFT                     10
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_AFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_MASK                      0x00000200
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_SHIFT                     9
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_TFEC_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_MASK                    0x00000100
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_SHIFT                   8
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_1_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_MASK                    0x00000080
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_SHIFT                   7
+#define BCHP_AON_PM_L2_PCI_SET_SDS0_RCVR_0_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_MASK                       0x00000040
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_SHIFT                      6
+#define BCHP_AON_PM_L2_PCI_SET_WOL_ENET_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_MASK                           0x00000020
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_SHIFT                          5
+#define BCHP_AON_PM_L2_PCI_SET_GPIO_DEFAULT                        0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_MASK                     0x00000010
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_SHIFT                    4
+#define BCHP_AON_PM_L2_PCI_SET_NMI_B_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_MASK                     0x00000008
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_SHIFT                    3
+#define BCHP_AON_PM_L2_PCI_SET_TIMER_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_MASK                       0x00000004
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_SHIFT                      2
+#define BCHP_AON_PM_L2_PCI_SET_KPD_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_MASK                       0x00000002
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_SHIFT                      1
+#define BCHP_AON_PM_L2_PCI_SET_IRR_INTR_DEFAULT                    0x00000000
+
+/* AON_PM_L2 :: PCI_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_MASK                       0x00000001
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_SHIFT                      0
+#define BCHP_AON_PM_L2_PCI_SET_CEC_INTR_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_MASK                    0xffff0000
+#define BCHP_AON_PM_L2_PCI_CLEAR_reserved0_SHIFT                   16
+
+/* AON_PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK         0x00008000
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT        15
+#define BCHP_AON_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_MASK                     0x00004000
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_SHIFT                    14
+#define BCHP_AON_PM_L2_PCI_CLEAR_FP_RESET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_MASK            0x00002000
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_SHIFT           13
+#define BCHP_AON_PM_L2_PCI_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT         0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_MASK                      0x00001000
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_SHIFT                     12
+#define BCHP_AON_PM_L2_PCI_CLEAR_XPT_PMU_DEFAULT                   0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_MASK                          0x00000800
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_SHIFT                         11
+#define BCHP_AON_PM_L2_PCI_CLEAR_FTM_DEFAULT                       0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_MASK                    0x00000400
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_SHIFT                   10
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_AFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_MASK                    0x00000200
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_SHIFT                   9
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_TFEC_DEFAULT                 0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_MASK                  0x00000100
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_SHIFT                 8
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_1_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_MASK                  0x00000080
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_SHIFT                 7
+#define BCHP_AON_PM_L2_PCI_CLEAR_SDS0_RCVR_0_DEFAULT               0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_MASK                     0x00000040
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_SHIFT                    6
+#define BCHP_AON_PM_L2_PCI_CLEAR_WOL_ENET_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_MASK                         0x00000020
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_SHIFT                        5
+#define BCHP_AON_PM_L2_PCI_CLEAR_GPIO_DEFAULT                      0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_MASK                   0x00000010
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_SHIFT                  4
+#define BCHP_AON_PM_L2_PCI_CLEAR_NMI_B_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_MASK                   0x00000008
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_SHIFT                  3
+#define BCHP_AON_PM_L2_PCI_CLEAR_TIMER_INTR_DEFAULT                0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_MASK                     0x00000004
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_SHIFT                    2
+#define BCHP_AON_PM_L2_PCI_CLEAR_KPD_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_MASK                     0x00000002
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_SHIFT                    1
+#define BCHP_AON_PM_L2_PCI_CLEAR_IRR_INTR_DEFAULT                  0x00000000
+
+/* AON_PM_L2 :: PCI_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_MASK                     0x00000001
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_SHIFT                    0
+#define BCHP_AON_PM_L2_PCI_CLEAR_CEC_INTR_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_MASK              0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT             16
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK   0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT  15
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_MASK               0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_SHIFT              14
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FP_RESET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_MASK      0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_SHIFT     13
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_BOUNDARY_SCAN_REQ_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_MASK                0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_SHIFT               12
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_XPT_PMU_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_MASK                    0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_SHIFT                   11
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_FTM_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_MASK              0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_SHIFT             10
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_AFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_MASK              0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_SHIFT             9
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_TFEC_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_MASK            0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_SHIFT           8
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_1_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_MASK            0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_SHIFT           7
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_SDS0_RCVR_0_DEFAULT         0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_MASK               0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_SHIFT              6
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_WOL_ENET_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_MASK                   0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_SHIFT                  5
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_GPIO_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_MASK             0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_SHIFT            4
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_NMI_B_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_MASK             0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_SHIFT            3
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_TIMER_INTR_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_MASK               0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_SHIFT              2
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_KPD_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_MASK               0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_SHIFT              1
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_IRR_INTR_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_STATUS :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_MASK               0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_SHIFT              0
+#define BCHP_AON_PM_L2_PCI_MASK_STATUS_CEC_INTR_DEFAULT            0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_SET :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_MASK                 0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_reserved0_SHIFT                16
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK      0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT     15
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_DEFAULT   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_MASK                  0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_SHIFT                 14
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FP_RESET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_MASK         0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_SHIFT        13
+#define BCHP_AON_PM_L2_PCI_MASK_SET_BOUNDARY_SCAN_REQ_DEFAULT      0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_MASK                   0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_SHIFT                  12
+#define BCHP_AON_PM_L2_PCI_MASK_SET_XPT_PMU_DEFAULT                0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_MASK                       0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_SHIFT                      11
+#define BCHP_AON_PM_L2_PCI_MASK_SET_FTM_DEFAULT                    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_MASK                 0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_SHIFT                10
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_AFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_MASK                 0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_SHIFT                9
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_TFEC_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_MASK               0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_SHIFT              8
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_1_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_MASK               0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_SHIFT              7
+#define BCHP_AON_PM_L2_PCI_MASK_SET_SDS0_RCVR_0_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_MASK                  0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_SHIFT                 6
+#define BCHP_AON_PM_L2_PCI_MASK_SET_WOL_ENET_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_MASK                      0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_SHIFT                     5
+#define BCHP_AON_PM_L2_PCI_MASK_SET_GPIO_DEFAULT                   0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_MASK                0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_SHIFT               4
+#define BCHP_AON_PM_L2_PCI_MASK_SET_NMI_B_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_MASK                0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_SHIFT               3
+#define BCHP_AON_PM_L2_PCI_MASK_SET_TIMER_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_MASK                  0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_SHIFT                 2
+#define BCHP_AON_PM_L2_PCI_MASK_SET_KPD_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_MASK                  0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_SHIFT                 1
+#define BCHP_AON_PM_L2_PCI_MASK_SET_IRR_INTR_DEFAULT               0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_SET :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_MASK                  0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_SHIFT                 0
+#define BCHP_AON_PM_L2_PCI_MASK_SET_CEC_INTR_DEFAULT               0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:16] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_MASK               0xffff0000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT              16
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [15:15] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK    0x00008000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT   15
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_DEFAULT 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FP_RESET [14:14] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_MASK                0x00004000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_SHIFT               14
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FP_RESET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: BOUNDARY_SCAN_REQ [13:13] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_MASK       0x00002000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_SHIFT      13
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_BOUNDARY_SCAN_REQ_DEFAULT    0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: XPT_PMU [12:12] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_MASK                 0x00001000
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_SHIFT                12
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_XPT_PMU_DEFAULT              0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: FTM [11:11] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_MASK                     0x00000800
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_SHIFT                    11
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_FTM_DEFAULT                  0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_AFEC [10:10] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_MASK               0x00000400
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_SHIFT              10
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_AFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_TFEC [09:09] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_MASK               0x00000200
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_SHIFT              9
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_TFEC_DEFAULT            0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_1 [08:08] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_MASK             0x00000100
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_SHIFT            8
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_1_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: SDS0_RCVR_0 [07:07] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_MASK             0x00000080
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_SHIFT            7
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_SDS0_RCVR_0_DEFAULT          0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: WOL_ENET [06:06] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_MASK                0x00000040
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_SHIFT               6
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_WOL_ENET_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: GPIO [05:05] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_MASK                    0x00000020
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_SHIFT                   5
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_GPIO_DEFAULT                 0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: NMI_B_INTR [04:04] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_MASK              0x00000010
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_SHIFT             4
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_NMI_B_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: TIMER_INTR [03:03] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_MASK              0x00000008
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_SHIFT             3
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_TIMER_INTR_DEFAULT           0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: KPD_INTR [02:02] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_MASK                0x00000004
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_SHIFT               2
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_KPD_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: IRR_INTR [01:01] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_MASK                0x00000002
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_SHIFT               1
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_IRR_INTR_DEFAULT             0x00000001
+
+/* AON_PM_L2 :: PCI_MASK_CLEAR :: CEC_INTR [00:00] */
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_MASK                0x00000001
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_SHIFT               0
+#define BCHP_AON_PM_L2_PCI_MASK_CLEAR_CEC_INTR_DEFAULT             0x00000001
+
+#endif /* #ifndef BCHP_AON_PM_L2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_bspi.h b/include/linux/brcmstb/7362a0/bchp_bspi.h
new file mode 100644
index 000000000000..35cd173db469
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_bspi.h
@@ -0,0 +1,446 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00413000 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00413004 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00413008 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0041300c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00413010 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00413014 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00413018 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0041301c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00413020 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00413024 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00413028 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0041302c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00413030 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00413034 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00413038 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0041303c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00413040 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00413044 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00413048 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0041304c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000000
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_bspi_raf.h b/include/linux/brcmstb/7362a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..22407cc13912
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_bspi_raf.h
@@ -0,0 +1,163 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_bspi_raf.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:37a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00413100 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00413104 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00413108 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0041310c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00413110 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00413114 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00413118 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0041311c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00413120 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_clkgen.h b/include/linux/brcmstb/7362a0/bchp_clkgen.h
new file mode 100644
index 000000000000..39493d2956b2
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_clkgen.h
@@ -0,0 +1,4689 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:41 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_CLKGEN_H__
+#define BCHP_CLKGEN_H__
+
+/***************************************************************************
+ *CLKGEN - clkgen registers
+ ***************************************************************************/
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00420024 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00420028 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0042002c /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00420030 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00420034 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00420038 /* Resets */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0042003c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420040 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00420044 /* Test Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420048 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x0042004c /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x00420050 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420054 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420058 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042005c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420060 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420064 /* Lock Status */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420068 /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042006c /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420070 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420074 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420078 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x0042007c /* Test Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420080 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420084 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3 0x00420088 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x0042008c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00420090 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00420094 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00420098 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x0042009c /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x004200a0 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x004200a4 /* Resets */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x004200a8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x004200ac /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004200b0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x004200b4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x004200b8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x004200bc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x004200c0 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x004200c4 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x004200c8 /* PLL CHANNEL control CH 5 */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x004200cc /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x004200d0 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x004200d4 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x004200d8 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x004200dc /* Miscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x004200e0 /* Miscellaneous control bus continued. */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x004200e4 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x004200e8 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200f0 /* Test Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x004200f4 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x004200f8 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x004200fc /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x00420100 /* PLL CHANNEL control CH 3 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x00420104 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x00420108 /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x0042010c /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x00420110 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x00420114 /* Lock Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x00420118 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x0042011c /* Powerdowns */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x00420120 /* Resets */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x00420124 /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x00420128 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x0042012c /* Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x00420130 /* PLL CHANNEL control CH 0 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x00420134 /* PLL CHANNEL control CH 1 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x00420138 /* PLL CHANNEL control CH 2 */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x0042013c /* Miscellaneous Controls */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x00420140 /* Pre multiplier */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x00420144 /* Fractional */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x00420148 /* PLL GAIN */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x0042014c /* Lock Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00420150 /* Mscellaneous control bus. */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00420154 /* Powerdowns */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x00420158 /* Resets */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x0042015c /* Higher bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00420164 /* Status */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x00420168 /* Avd0 top clock enable */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x0042016c /* Avd0 top memory standby enable */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x00420170 /* Avd0 top observe clock */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x00420174 /* Avd0 top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE   0x00420178 /* Disable BCM_MIPS_TOP's clocks */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x0042017c /* Bcm mips top clock enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420180 /* Bcm mips top memory standby enable */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420184 /* Bcm mips top observe clock */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x00420188 /* Bcm mips top power switch memory */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT          0x0042018c /* Bcm mips top select */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE               0x00420190 /* Bvn top enable */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE 0x00420194 /* Bvn top memory standby enable */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY  0x00420198 /* Bvn top power switch memory */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x0042019c /* Cktap 108 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a0 /* Cktap 108 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a4 /* Cktap 108 2 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201a8 /* Cktap 216 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK 0x004201ac /* CKTAP CPU Adjustment System 108 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK 0x004201b0 /* CKTAP CPU Adjustment System 216 Clock */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK 0x004201b4 /* CKTAP CPU Adjustment System Scb Clock */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201b8 /* Cktap scb 0 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION 0x004201bc /* Cktap scb 1 cktap cpu adjustment selection */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x004201c0 /* Disable CLKGEN's clocks */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x004201c4 /* Clock Monitor Control */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x004201c8 /* Clock Monitor Max Reference Count */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x004201cc /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x004201d0 /* Clock Monitor Reference Counter */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x004201d4 /* Clock Monitor View Counter */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x004201d8 /* Disable CORE_XPT's clocks */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x004201dc /* Core xpt clock enable */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x004201e0 /* Core xpt memory standby enable */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x004201e4 /* Core xpt observe clock */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x004201e8 /* Core xpt power switch memory */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x004201ec /* Disable DVP_HT's clocks */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x004201f0 /* Dvp ht clock enable */
+#define BCHP_CLKGEN_DVP_HT_ENABLE                0x004201f4 /* Dvp ht enable */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201f8 /* Dvp ht memory standby enable */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201fc /* Dvp ht observe clock */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x00420200 /* Dvp ht power switch memory */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE         0x00420204 /* Fsk top clock enable */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE 0x00420208 /* Fsk top memory standby enable */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY  0x0042020c /* Fsk top power switch memory */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00420210 /* Disable GENET_TOP_RGMII_INST's clocks */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x00420214 /* Genet top rgmii inst clock enable */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00420218 /* Genet top rgmii inst clock select */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0042021c /* Genet top rgmii inst memory standby enable a */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00420220 /* Genet top rgmii inst observe clock */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420224 /* Genet top rgmii inst power switch memory a */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE       0x00420228 /* Disable GRAPHICS's clocks */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE        0x0042022c /* Graphics clock enable */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE 0x00420230 /* Graphics memory standby enable */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK       0x00420234 /* Graphics observe clock */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY 0x00420238 /* Graphics power switch memory */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE            0x0042023c /* Disable HIF's clocks */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE             0x00420240 /* Hif clock enable */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE    0x00420244 /* Hif memory standby enable */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY      0x00420248 /* Hif power switch memory */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x0042024c /* Mux selects for Internal clocks */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE       0x00420250 /* Memsys 16 clock enable */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE 0x00420254 /* Memsys 16 memory standby enable */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK      0x00420258 /* Memsys 16 observe clock */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY 0x0042025c /* Memsys 16 power switch memory */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS             0x00420260 /* Memsys 16 status */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420264 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420268 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x0042026c /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x00420270 /* Select observation clk */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420274 /* Disable PAD's clocks */
+#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420278 /* Mux selects for Pad clocks */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042027c /* PLL_AUDIO0 Reset Status */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x00420280 /* PLL_AUDIO1 Reset Status */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00420284 /* PLL_SC Reset Status */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00420288 /* PLL_SYS1 Reset Status */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042028c /* PLL_VCXO Reset Status */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x00420290 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420294 /* Select clocks that can stay alive during power management standby mode. */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420298 /* PLL Alive in Standby Mode */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE   0x0042029c /* Raaga dsp top clock enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE 0x004202a0 /* Raaga dsp top memory standby enable */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK  0x004202a4 /* Raaga dsp top observe clock */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY 0x004202a8 /* Raaga dsp top power switch memory */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x004202ac /* Rfm top clock enable */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x004202b0 /* Rfm top memory standby enable */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x004202b4 /* Rfm top observe clock */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x004202b8 /* Rfm top power switch memory */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE       0x004202bc /* Sata3 top clock enable */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE      0x004202c0 /* Disable SATA3_TOP's clocks */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE 0x004202c4 /* Sata3 memory standby enable */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK      0x004202c8 /* Sata3 top observe clock */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL         0x004202cc /* Sata3 top PLL Ref Sel */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY 0x004202d0 /* Sata3 top power switch memory */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE    0x004202d4 /* Sds afec top clock enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202d8 /* Sds afec top memory standby enable */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK   0x004202dc /* Sds afec top observe clock */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY 0x004202e0 /* Sds afec top power switch memory */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE   0x004202e4 /* Disable SDS_RECEIVER's clocks */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE    0x004202e8 /* Sds receiver clock enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE 0x004202ec /* Sds receiver memory standby enable */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK   0x004202f0 /* Sds receiver observe clock */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY 0x004202f4 /* Sds receiver power switch memory */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE    0x004202f8 /* Sds tfec top clock enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE 0x004202fc /* Sds tfec top memory standby enable */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK   0x00420300 /* Sds tfec top observe clock */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY 0x00420304 /* Sds tfec top power switch memory */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x00420308 /* Sectop inst clock enable */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Sectop inst memory standby enable */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00420310 /* Sectop inst observe clock */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420314 /* Mux selects for Smartcard clocks */
+#define BCHP_CLKGEN_SPARE                        0x00420318 /* Spares */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042031c /* Sys aon observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420320 /* Disable SYS_CTRL's clocks */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420324 /* Sys ctrl clock enable */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420328 /* Sys ctrl memory standby enable */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x0042032c /* Sys ctrl observe clock */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420330 /* Sys ctrl power switch memory */
+#define BCHP_CLKGEN_TESTPORT                     0x00420334 /* Special Testport Controls */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420338 /* Disable USB's clocks */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x0042033c /* Usb clock enable */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420340 /* Usb memory standby enable */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420344 /* Usb observe clock */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420348 /* Usb power switch memory */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042034c /* Disable VEC_AIO_TOP's clocks */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE     0x00420350 /* Vec aio top clock enable */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A 0x00420354 /* Vec aio top memory standby enable a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B 0x00420358 /* Vec aio top memory standby enable b */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x0042035c /* Vec aio top observe clock */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A 0x00420360 /* Vec aio top power switch memory a */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B 0x00420364 /* Vec aio top power switch memory b */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 0x00420368 /* PLL CHANNEL control CH 4 */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x0042036c /* spi clock control */
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3
+
+/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000001
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12
+
+/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000005
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000a
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x00000028
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xffffc000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   14
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000032
+
+/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                0x00000040
+
+/***************************************************************************
+ *PLL_SC_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      0x00000001
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1
+
+/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0
+
+/***************************************************************************
+ *PLL_SC_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1
+
+/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SC_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12
+
+/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
+#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000006
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036
+
+/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060
+
+/***************************************************************************
+ *PLL_SYS0_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1
+
+/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS0_PLL_STATUS - Test Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000012
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000009
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000005a
+
+/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  0x00000003
+
+/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              0x0000007d
+
+/***************************************************************************
+ *PLL_SYS1_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              0x00000001
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             0x00000002
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_SYS1_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000004b
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x000000fa
+
+/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1
+
+/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_DIV - Pre multiplier
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040
+
+/***************************************************************************
+ *PLL_VCXO_PLL_FRAC - Fractional
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20
+
+/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_GAIN - PLL GAIN
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1
+
+/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_PWRDN - Powerdowns
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1
+
+/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET - Resets
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
+#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_VCXO_PLL_STATUS - Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12
+
+/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
+#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0
+
+/***************************************************************************
+ *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          5
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_DISABLE - Disable BCM_MIPS_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_DISABLE :: DISABLE_MIPS_SYSTEM_216_CLOCK [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_DISABLE_DISABLE_MIPS_SYSTEM_216_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      4
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_MIPS_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_MIPS_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BCM_MIPS_TOP_SELECT - Bcm mips top select
+ ***************************************************************************/
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_MASK             0xfffffffe
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_reserved0_SHIFT            1
+
+/* CLKGEN :: BCM_MIPS_TOP_SELECT :: MIPS_PLL_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_BCM_MIPS_TOP_SELECT_MIPS_PLL_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_ENABLE - Bvn top enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_reserved0_SHIFT                 3
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK       0x00000004
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT      2
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT    0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK         0x00000002
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT        1
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT      0x00000001
+
+/* CLKGEN :: BVN_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK         0x00000001
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT        0
+#define BCHP_CLKGEN_BVN_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT      0x00000001
+
+/***************************************************************************
+ *BVN_TOP_MEMORY_STANDBY_ENABLE - Bvn top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: BVN_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BVN_TOP_POWER_SWITCH_MEMORY - Bvn top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: BVN_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_RFM_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_DSTOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_1_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 108 2 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_TOP_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_FSK_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_SDS_AFEC_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION :: CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_108_2_CKTAP_CPU_ADJUSTMENT_SELECTION_CLKGEN_108_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap 216 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:28] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 28
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_DVP_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_216_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_216_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK - CKTAP CPU Adjustment System 108 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: reserved0 [31:08] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_MASK 0xffffff00
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_reserved0_SHIFT 8
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_WAIT_COUNT [07:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_MASK 0x000000fc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_SHIFT 2
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_WAIT_COUNT_DEFAULT 0x0000000f
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_108_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK - CKTAP CPU Adjustment System 216 Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_216_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK - CKTAP CPU Adjustment System Scb Clock
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_reserved0_SHIFT 2
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_UPDATE [01:01] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_MASK 0x00000002
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_SHIFT 1
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_UPDATE_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK :: CKTAP_REG_SELECT [00:00] */
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_CPU_ADJUSTMENT_SYSTEM_SCB_CLOCK_CKTAP_REG_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 0 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [31:28] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0xf0000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 28
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_VEC_AIO_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [27:24] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0f000000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 24
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_USB_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [23:20] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00f00000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 20
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_RAAGA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [19:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000f0000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 16
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MIPS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_MEMSYS_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_GENET_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_BVN_M2MC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION :: AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_0_CKTAP_CPU_ADJUSTMENT_SELECTION_AVD_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION - Cktap scb 1 cktap cpu adjustment selection
+ ***************************************************************************/
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: reserved0 [31:16] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_MASK 0xffff0000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_reserved0_SHIFT 16
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [15:12] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000f000
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 12
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SATA_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [11:08] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x00000f00
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 8
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SYS_CTRL_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [07:04] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x000000f0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 4
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_SEC_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/* CLKGEN :: CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION :: HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION [03:00] */
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_MASK 0x0000000f
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_SHIFT 0
+#define BCHP_CLKGEN_CKTAP_SCB_1_CKTAP_CPU_ADJUSTMENT_SELECTION_HIF_XPT_SCB_CKTAP_CPU_ADJUSTMENT_SELECTION_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
+ ***************************************************************************/
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
+#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CLOCK_MONITOR_CONTROL - Clock Monitor Control
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001
+
+/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
+#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1
+
+/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
+#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0
+
+/***************************************************************************
+ *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
+ ***************************************************************************/
+/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
+#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
+ ***************************************************************************/
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *DVP_HT_ENABLE - Dvp ht enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_ENABLE_reserved0_SHIFT                  1
+
+/* CLKGEN :: DVP_HT_ENABLE :: DVPHT_CLK_MAX_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK        0x00000001
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT       0
+#define BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT     0x00000001
+
+/***************************************************************************
+ *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1
+
+/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
+ ***************************************************************************/
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2
+
+/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_CLOCK_ENABLE - Fsk top clock enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffff8
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_reserved0_SHIFT           3
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_PHY_PRIMARY_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_PHY_PRIMARY_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: FSK_TOP_CLOCK_ENABLE :: FSK_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_CLOCK_ENABLE_FSK_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *FSK_TOP_MEMORY_STANDBY_ENABLE - Fsk top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: FSK_TOP_MEMORY_STANDBY_ENABLE :: FSK_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_MEMORY_STANDBY_ENABLE_FSK_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *FSK_TOP_POWER_SWITCH_MEMORY - Fsk top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: FSK_TOP_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_FSK_TOP_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable GENET_TOP_RGMII_INST's clocks
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 4
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_ENABLE - Genet top rgmii inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:09] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffe00
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 9
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [08:08] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00000100
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 8
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [07:07] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00000080
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 7
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_CLOCK_SELECT - Genet top rgmii inst clock select
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Genet top rgmii inst memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Genet top rgmii inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: DUAL_GENET_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_DUAL_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Genet top rgmii inst power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_DISABLE - Disable GRAPHICS's clocks
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_reserved0_SHIFT         1
+
+/* CLKGEN :: GRAPHICS_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_CLOCK_ENABLE - Graphics clock enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_reserved0_SHIFT          4
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: GRAPHICS_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GRAPHICS_MEMORY_STANDBY_ENABLE - Graphics memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: GRAPHICS_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_OBSERVE_CLOCK - Graphics observe clock
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: GRAPHICS_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GRAPHICS_POWER_SWITCH_MEMORY - Graphics power switch memory
+ ***************************************************************************/
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: GRAPHICS_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_DISABLE - Disable HIF's clocks
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_DISABLE :: reserved0 [31:04] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_reserved0_SHIFT              4
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_SDIO_48_CLOCK [03:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_MASK   0x00000008
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_SHIFT  3
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_SDIO_48_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK   0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT  2
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK   0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT  1
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: HIF_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
+#define BCHP_CLKGEN_HIF_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_CLOCK_ENABLE - Hif clock enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_reserved0_SHIFT               3
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_MASK     0x00000004
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_SHIFT    2
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_SCB_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK     0x00000002
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT    1
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/* CLKGEN :: HIF_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK     0x00000001
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT    0
+#define BCHP_CLKGEN_HIF_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT  0x00000001
+
+/***************************************************************************
+ *HIF_MEMORY_STANDBY_ENABLE - Hif memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: HIF_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_HIF_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HIF_POWER_SWITCH_MEMORY - Hif power switch memory
+ ***************************************************************************/
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: HIF_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_HIF_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
+ ***************************************************************************/
+/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:04] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffff0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            4
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_USE_PROG_CLK [03:03] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_MASK 0x00000008
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_SHIFT 3
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_USE_PROG_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [02:02] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:01] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: INTERNAL_MUX_SELECT :: GFX_M2MC_CORE_CLOCK [00:00] */
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_MASK   0x00000001
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_SHIFT  0
+#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_GFX_M2MC_CORE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_CLOCK_ENABLE - Memsys 16 clock enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: MEMSYS_16_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MEMSYS_16_MEMORY_STANDBY_ENABLE - Memsys 16 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: MEMSYS_16_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_OBSERVE_CLOCK - Memsys 16 observe clock
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: MEMSYS_16_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_POWER_SWITCH_MEMORY - Memsys 16 power switch memory
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: MEMSYS_16_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_MEMSYS_16_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_16_STATUS - Memsys 16 status
+ ***************************************************************************/
+/* CLKGEN :: MEMSYS_16_STATUS :: reserved0 [31:01] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_MASK                0xfffffffe
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_reserved0_SHIFT               1
+
+/* CLKGEN :: MEMSYS_16_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_MEMSYS_16_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_CLOCK_DISABLE - Disable PAD's clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              3
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_SC_OUT_CLOCK [02:02] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK    0x00000004
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_SHIFT   2
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PAD_MUX_SELECT - Mux selects for Pad clocks
+ ***************************************************************************/
+/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
+#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3
+
+/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [02:00] */
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000007
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
+#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000
+
+/***************************************************************************
+ *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
+ ***************************************************************************/
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1
+
+/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0
+
+/***************************************************************************
+ *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:04] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         4
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTFEC [03:03] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_MASK 0x00000008
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_SHIFT 3
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSRCVR [02:02] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_MASK 0x00000004
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_SHIFT 2
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSRCVR_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC [01:01] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_MASK 0x00000002
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_SHIFT 1
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC_DEFAULT 0x00000000
+
+/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_ [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__MASK      0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__SHIFT     0
+#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG__DEFAULT   0x00000000
+
+/***************************************************************************
+ *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
+ ***************************************************************************/
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1
+
+/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
+#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
+ ***************************************************************************/
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000
+
+/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_AVD_MIPS [00:00] */
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_MASK             0x00000001
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_SHIFT            0
+#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_AVD_MIPS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_CLOCK_ENABLE - Raaga dsp top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_reserved0_SHIFT     3
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: RAAGA_DSP_TOP_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE - Raaga dsp top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_OBSERVE_CLOCK - Raaga dsp top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_reserved0_SHIFT    2
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RAAGA_DSP_TOP_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RAAGA_DSP_TOP_POWER_SWITCH_MEMORY - Raaga dsp top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: RAAGA_DSP_TOP_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1
+
+/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1
+
+/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2
+
+/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_ENABLE - Sata3 top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_reserved0_SHIFT         2
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: SATA3_TOP_CLOCK_ENABLE :: SATA_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_ENABLE_SATA_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_CLOCK_DISABLE - Disable SATA3_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_MASK         0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_reserved0_SHIFT        1
+
+/* CLKGEN :: SATA3_TOP_CLOCK_DISABLE :: DISABLE_SATA_FUNC_30_CLOCK [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_CLOCK_DISABLE_DISABLE_SATA_FUNC_30_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_MEMORY_STANDBY_ENABLE - Sata3 memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SATA3_TOP_MEMORY_STANDBY_ENABLE :: SATA_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_MEMORY_STANDBY_ENABLE_SATA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_OBSERVE_CLOCK - Sata3 top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_reserved0_SHIFT        6
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SATA3_TOP_OBSERVE_CLOCK :: SATA_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_OBSERVE_CLOCK_SATA_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SATA3_TOP_PLLREF_SEL - Sata3 top PLL Ref Sel
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_MASK            0xfffffffe
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_reserved0_SHIFT           1
+
+/* CLKGEN :: SATA3_TOP_PLLREF_SEL :: SATA_TOP_PLLREF_SEL [00:00] */
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_MASK  0x00000001
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_PLLREF_SEL_SATA_TOP_PLLREF_SEL_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SATA3_TOP_POWER_SWITCH_MEMORY - Sata3 top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT  2
+
+/* CLKGEN :: SATA3_TOP_POWER_SWITCH_MEMORY :: SATA_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SATA3_TOP_POWER_SWITCH_MEMORY_SATA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_CLOCK_ENABLE - Sds afec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_AFEC_TOP_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE - Sds afec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_OBSERVE_CLOCK - Sds afec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_AFEC_TOP_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_AFEC_TOP_POWER_SWITCH_MEMORY - Sds afec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_AFEC_TOP_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_AFEC_TOP_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_DISABLE - Disable SDS_RECEIVER's clocks
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_MASK      0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_reserved0_SHIFT     1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_DISABLE :: DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_DISABLE_DISABLE_SDSRCVR_108_PRESPMBALANCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_CLOCK_ENABLE - Sds receiver clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_RECEIVER_CLOCK_ENABLE :: SDSRCVR0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_CLOCK_ENABLE_SDSRCVR0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_RECEIVER_MEMORY_STANDBY_ENABLE - Sds receiver memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_RECEIVER_MEMORY_STANDBY_ENABLE :: SDSRCVR0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_MEMORY_STANDBY_ENABLE_SDSRCVR0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_OBSERVE_CLOCK - Sds receiver observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_RECEIVER_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_RECEIVER_POWER_SWITCH_MEMORY - Sds receiver power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_RECEIVER_POWER_SWITCH_MEMORY :: SDSRCVR0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_RECEIVER_POWER_SWITCH_MEMORY_SDSRCVR0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_CLOCK_ENABLE - Sds tfec top clock enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: SDS_TFEC_TOP_CLOCK_ENABLE :: SDSTFEC0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_CLOCK_ENABLE_SDSTFEC0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE - Sds tfec top memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE :: SDS_TFEC0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_MEMORY_STANDBY_ENABLE_SDS_TFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_OBSERVE_CLOCK - Sds tfec top observe clock
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SDS_TFEC_TOP_OBSERVE_CLOCK :: SDS_TFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_OBSERVE_CLOCK_SDS_TFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SDS_TFEC_TOP_POWER_SWITCH_MEMORY - Sds tfec top power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2
+
+/* CLKGEN :: SDS_TFEC_TOP_POWER_SWITCH_MEMORY :: SDS_TFEC0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SDS_TFEC_TOP_POWER_SWITCH_MEMORY_SDS_TFEC0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1
+
+/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SEC_ALTERNATE_SCB_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
+ ***************************************************************************/
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
+ ***************************************************************************/
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000
+
+/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE - Spares
+ ***************************************************************************/
+/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000
+
+/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
+#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:05] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         5
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [03:03] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000008
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 3
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK [02:02] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_MASK 0x00000004
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_SHIFT 2
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_54_UNDIVIDED_SCANCLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK  0x00000002
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1
+
+/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1
+
+/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
+ ***************************************************************************/
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2
+
+/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TESTPORT - Special Testport Controls
+ ***************************************************************************/
+/* CLKGEN :: TESTPORT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff8
+#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       3
+
+/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [02:00] */
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000007
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
+#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_DISABLE - Disable USB's clocks
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1
+
+/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_CLOCK_ENABLE - Usb clock enable
+ ***************************************************************************/
+/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
+#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
+ ***************************************************************************/
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_OBSERVE_CLOCK - Usb observe clock
+ ***************************************************************************/
+/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *USB_POWER_SWITCH_MEMORY - Usb power switch memory
+ ***************************************************************************/
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2
+
+/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
+#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_CLOCK_ENABLE - Vec aio top clock enable
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: reserved0 [31:07] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_MASK        0xffffff80
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_reserved0_SHIFT       7
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [06:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000040
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 6
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_SCB_CLOCK_ENABLE [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_216_CLOCK_ENABLE [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE_108_CLOCK_ENABLE [03:03] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000008
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_SHIFT 3
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_ALTERNATE2_108_CLOCK_ENABLE [02:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_MASK 0x00000004
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_SHIFT 2
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE2_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_216_CLOCK_ENABLE [01:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_MASK 0x00000002
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_SHIFT 1
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_216_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A - Vec aio top memory standby enable a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A :: VEC_MEMORY_STANDBY_ENABLE_A [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_A_VEC_MEMORY_STANDBY_ENABLE_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B - Vec aio top memory standby enable b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: reserved0 [31:01] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_MASK 0xfffffffe
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_reserved0_SHIFT 1
+
+/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B :: AIO_MEMORY_STANDBY_ENABLE_B [00:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_MASK 0x00000001
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_B_AIO_MEMORY_STANDBY_ENABLE_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      6
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_A - Vec aio top power switch memory a
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_A :: VEC_POWER_SWITCH_MEMORY_A [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A_VEC_POWER_SWITCH_MEMORY_A_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VEC_AIO_TOP_POWER_SWITCH_MEMORY_B - Vec aio top power switch memory b
+ ***************************************************************************/
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2
+
+/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_B :: AIO_POWER_SWITCH_MEMORY_B [01:00] */
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_MASK 0x00000003
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_SHIFT 0
+#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_B_AIO_POWER_SWITCH_MEMORY_B_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
+ ***************************************************************************/
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008
+
+/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
+#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000
+
+/***************************************************************************
+ *BSPI_CLOCK_SELECT - spi clock control
+ ***************************************************************************/
+/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000
+
+/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
+#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_CLKGEN_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_common.h b/include/linux/brcmstb/7362a0/bchp_common.h
new file mode 100644
index 000000000000..5dbe6e9a8595
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_common.h
@@ -0,0 +1,1986 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:33 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7362_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0x10000000
+#define BCHP_REGISTER_START                                0x00000000 /* DECODE_RBNODE_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x00b01010 /* RFM_GRB is last */
+#define BCHP_REGISTER_SIZE                                 0x002c0404 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_DECODE_RBNODE_REGS_0_REG_START                0x00000000
+#define BCHP_DECODE_RBNODE_REGS_0_REG_END                  0x0000007c
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00000100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x000001fc
+#define BCHP_SDRAM_DEBUG_0_REG_START                       0x00000200
+#define BCHP_SDRAM_DEBUG_0_REG_END                         0x0000027c
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00000300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0000031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00000320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0000033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00000340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0000035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00000400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0000045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00000500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0000057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00000600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0000060c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00000700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0000071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00000720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0000073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00000740
+#define BCHP_DECODE_MB_0_REG_END                           0x0000075c
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00000b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00000bfc
+#define BCHP_DECODE_SINT_0_REG_START                       0x00000c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00000dfc
+#define BCHP_DECODE_RVC_0_REG_START                        0x00000e00
+#define BCHP_DECODE_RVC_0_REG_END                          0x00000efc
+#define BCHP_DECODE_CPUREGS_0_REG_START                    0x00000f00
+#define BCHP_DECODE_CPUREGS_0_REG_END                      0x00000f7c
+#define BCHP_DECODE_CPUREGS2_0_REG_START                   0x00000f80
+#define BCHP_DECODE_CPUREGS2_0_REG_END                     0x00000ffc
+#define BCHP_DECODE_CPUDMA_0_REG_START                     0x00001800
+#define BCHP_DECODE_CPUDMA_0_REG_END                       0x000018fc
+#define BCHP_DECODE_DMAMEM_0_REG_START                     0x00001a00
+#define BCHP_DECODE_DMAMEM_0_REG_END                       0x000021fc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00002400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x000027fc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00003000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x000031fc
+#define BCHP_DECODE_SINT_OLOOP_0_REG_START                 0x0000cc00
+#define BCHP_DECODE_SINT_OLOOP_0_REG_END                   0x0000ccfc
+#define BCHP_DECODE_SD_0_REG_START                         0x00040800
+#define BCHP_DECODE_SD_0_REG_END                           0x00040ffc
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START             0x00041000
+#define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END               0x0004107c
+#define BCHP_DECODE_CPUCORE_0_REG_START                    0x00044000
+#define BCHP_DECODE_CPUCORE_0_REG_END                      0x00044ffc
+#define BCHP_DECODE_CPUAUX_0_REG_START                     0x00045000
+#define BCHP_DECODE_CPUAUX_0_REG_END                       0x00045ffc
+#define BCHP_DECODE_CPUIMEM_0_REG_START                    0x00046000
+#define BCHP_DECODE_CPUIMEM_0_REG_END                      0x00047ffc
+#define BCHP_DECODE_CPUDMEM_0_REG_START                    0x00048000
+#define BCHP_DECODE_CPUDMEM_0_REG_END                      0x0004fffc
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START            0x00051000
+#define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END              0x0005107c
+#define BCHP_DECODE_CPUDMA2_0_REG_START                    0x00051800
+#define BCHP_DECODE_CPUDMA2_0_REG_END                      0x000518fc
+#define BCHP_DECODE_DMAMEM2_0_REG_START                    0x00051a00
+#define BCHP_DECODE_DMAMEM2_0_REG_END                      0x000521fc
+#define BCHP_DECODE_CPUCORE2_0_REG_START                   0x00054000
+#define BCHP_DECODE_CPUCORE2_0_REG_END                     0x00054ffc
+#define BCHP_DECODE_CPUAUX2_0_REG_START                    0x00055000
+#define BCHP_DECODE_CPUAUX2_0_REG_END                      0x00055ffc
+#define BCHP_DECODE_CPUIMEM2_0_REG_START                   0x00056000
+#define BCHP_DECODE_CPUIMEM2_0_REG_END                     0x00057ffc
+#define BCHP_DECODE_CPUDMEM2_0_REG_START                   0x00058000
+#define BCHP_DECODE_CPUDMEM2_0_REG_END                     0x0005fffc
+#define BCHP_DECODE_IP_SHIM_0_REG_START                    0x00060000
+#define BCHP_DECODE_IP_SHIM_0_REG_END                      0x00060084
+#define BCHP_AVD_CACHE_0_REG_START                         0x00062000
+#define BCHP_AVD_CACHE_0_REG_END                           0x0006203c
+#define BCHP_AVD_INTR2_0_REG_START                         0x00080000
+#define BCHP_AVD_INTR2_0_REG_END                           0x0008002c
+#define BCHP_AVD_RGR_0_REG_START                           0x00080400
+#define BCHP_AVD_RGR_0_REG_END                             0x00080410
+#define BCHP_VICH_0_REG_START                              0x00170000
+#define BCHP_VICH_0_REG_END                                0x0017008b
+#define BCHP_SATA_GRB_REG_START                            0x00180000
+#define BCHP_SATA_GRB_REG_END                              0x0018000c
+#define BCHP_SATA_TOP_CTRL_REG_START                       0x00180020
+#define BCHP_SATA_TOP_CTRL_REG_END                         0x00180038
+#define BCHP_SATA3_INTR2_REG_START                         0x00180080
+#define BCHP_SATA3_INTR2_REG_END                           0x001800ac
+#define BCHP_SATA_AHCI_GHC_REG_START                       0x00181000
+#define BCHP_SATA_AHCI_GHC_REG_END                         0x00181028
+#define BCHP_SATA_GLOBAL_RESERVED_REG_START                0x0018102c
+#define BCHP_SATA_GLOBAL_RESERVED_REG_END                  0x0018109c
+#define BCHP_SATA_PORT0_AHCI_S1_REG_START                  0x00181100
+#define BCHP_SATA_PORT0_AHCI_S1_REG_END                    0x0018111c
+#define BCHP_SATA_PORT0_AHCI_S2_REG_START                  0x00181120
+#define BCHP_SATA_PORT0_AHCI_S2_REG_END                    0x00181134
+#define BCHP_SATA_PORT0_AHCI_S3_REG_START                  0x00181138
+#define BCHP_SATA_PORT0_AHCI_S3_REG_END                    0x0018117c
+#define BCHP_SATA_PORT1_AHCI_S1_REG_START                  0x00181180
+#define BCHP_SATA_PORT1_AHCI_S1_REG_END                    0x0018119c
+#define BCHP_SATA_PORT1_AHCI_S2_REG_START                  0x001811a0
+#define BCHP_SATA_PORT1_AHCI_S2_REG_END                    0x001811b4
+#define BCHP_SATA_PORT1_AHCI_S3_REG_START                  0x001811b8
+#define BCHP_SATA_PORT1_AHCI_S3_REG_END                    0x001811fc
+#define BCHP_SATA_AHCI_PCICFG_REG_START                    0x00181600
+#define BCHP_SATA_AHCI_PCICFG_REG_END                      0x00181664
+#define BCHP_SATA_PORT0_CTRL_REG_START                     0x00181700
+#define BCHP_SATA_PORT0_CTRL_REG_END                       0x00181730
+#define BCHP_SATA_PORT0_CJPAT_REG_START                    0x00181740
+#define BCHP_SATA_PORT0_CJPAT_REG_END                      0x00181764
+#define BCHP_SATA_PORT1_CTRL_REG_START                     0x00181780
+#define BCHP_SATA_PORT1_CTRL_REG_END                       0x001817b0
+#define BCHP_SATA_PORT1_CJPAT_REG_START                    0x001817c0
+#define BCHP_SATA_PORT1_CJPAT_REG_END                      0x001817e4
+#define BCHP_SATA_LEG_PCICFG_REG_START                     0x00181800
+#define BCHP_SATA_LEG_PCICFG_REG_END                       0x00181880
+#define BCHP_SATA_PORT0_LEG_S1_REG_START                   0x00181900
+#define BCHP_SATA_PORT0_LEG_S1_REG_END                     0x00181934
+#define BCHP_SATA_PORT0_LEG_S2_REG_START                   0x00181940
+#define BCHP_SATA_PORT0_LEG_S2_REG_END                     0x00181954
+#define BCHP_SATA_PORT0_LEG_S3_REG_START                   0x00181958
+#define BCHP_SATA_PORT0_LEG_S3_REG_END                     0x00181998
+#define BCHP_SATA_PORT1_LEG_S1_REG_START                   0x00181a00
+#define BCHP_SATA_PORT1_LEG_S1_REG_END                     0x00181a34
+#define BCHP_SATA_PORT1_LEG_S2_REG_START                   0x00181a40
+#define BCHP_SATA_PORT1_LEG_S2_REG_END                     0x00181a54
+#define BCHP_SATA_PORT1_LEG_S3_REG_START                   0x00181a58
+#define BCHP_SATA_PORT1_LEG_S3_REG_END                     0x00181a98
+#define BCHP_BESTROM_REG_START                             0x00200000
+#define BCHP_BESTROM_REG_END                               0x00203ffc
+#define BCHP_BSP_CMDBUF_REG_START                          0x00329800
+#define BCHP_BSP_CMDBUF_REG_END                            0x00329ffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032b000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032b098
+#define BCHP_BSP_PKL_REG_START                             0x0032b300
+#define BCHP_BSP_PKL_REG_END                               0x0032b37c
+#define BCHP_BSP_INST_PATCH_CTRL_REG_START                 0x0032b400
+#define BCHP_BSP_INST_PATCH_CTRL_REG_END                   0x0032b404
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032b800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032b82c
+#define BCHP_BSP_INST_PATCHRAM_REG_START                   0x0032c000
+#define BCHP_BSP_INST_PATCHRAM_REG_END                     0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0036fffc
+#define BCHP_MMSCRAM_REG_START                             0x00370000
+#define BCHP_MMSCRAM_REG_END                               0x00371ffc
+#define BCHP_MEM_DMA_SECURE_REG_START                      0x00372000
+#define BCHP_MEM_DMA_SECURE_REG_END                        0x0037200c
+#define BCHP_SECTOP_GRB_REG_START                          0x00374000
+#define BCHP_SECTOP_GRB_REG_END                            0x0037400c
+#define BCHP_JTAG_OTP_REG_START                            0x00374100
+#define BCHP_JTAG_OTP_REG_END                              0x00374138
+#define BCHP_MEM_DMA_0_REG_START                           0x00374200
+#define BCHP_MEM_DMA_0_REG_END                             0x00374224
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00374300
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x00374310
+#define BCHP_MEMC_GEN_0_REG_START                          0x003b0000
+#define BCHP_MEMC_GEN_0_REG_END                            0x003b04f8
+#define BCHP_MEMC_GEN_2_0_REG_START                        0x003b0600
+#define BCHP_MEMC_GEN_2_0_REG_END                          0x003b06ec
+#define BCHP_MEMC_ARB_0_REG_START                          0x003b1000
+#define BCHP_MEMC_ARB_0_REG_END                            0x003b1244
+#define BCHP_MEMC_DDR_0_REG_START                          0x003b2000
+#define BCHP_MEMC_DDR_0_REG_END                            0x003b22fc
+#define BCHP_MEMC_L2_0_REG_START                           0x003b3000
+#define BCHP_MEMC_L2_0_REG_END                             0x003b302c
+#define BCHP_MEMC_L2_1_0_REG_START                         0x003b3800
+#define BCHP_MEMC_L2_1_0_REG_END                           0x003b382c
+#define BCHP_MEMC_RGRB_0_REG_START                         0x003b4000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x003b4010
+#define BCHP_MEMC_MISC_0_REG_START                         0x003b5000
+#define BCHP_MEMC_MISC_0_REG_END                           0x003b5010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_START            0x003b6000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REG_END              0x003b60c4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_START             0x003b6200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_REG_END               0x003b63b0
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_START         0x003b8000
+#define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_REG_END           0x003b8138
+#define BCHP_S_MEMC_0_REG_START                            0x003ba000
+#define BCHP_S_MEMC_0_REG_END                              0x003ba220
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004000d8
+#define BCHP_SUN_RGR_REG_START                             0x00400400
+#define BCHP_SUN_RGR_REG_END                               0x00400410
+#define BCHP_SUN_RG_REG_START                              0x00400800
+#define BCHP_SUN_RG_REG_END                                0x0040080c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x0040302c
+#define BCHP_SM_L2_REG_START                               0x00403400
+#define BCHP_SM_L2_REG_END                                 0x0040342c
+#define BCHP_SM_REG_START                                  0x00403800
+#define BCHP_SM_REG_END                                    0x00403824
+#define BCHP_SM_FAST_REG_START                             0x00403c00
+#define BCHP_SM_FAST_REG_END                               0x00403c18
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x00404518
+#define BCHP_IRB_REG_START                                 0x00406000
+#define BCHP_IRB_REG_END                                   0x00406138
+#define BCHP_PM_REG_START                                  0x00406180
+#define BCHP_PM_REG_END                                    0x00406188
+#define BCHP_BSCA_REG_START                                0x00406200
+#define BCHP_BSCA_REG_END                                  0x00406254
+#define BCHP_BSCB_REG_START                                0x00406280
+#define BCHP_BSCB_REG_END                                  0x004062d4
+#define BCHP_PWM_REG_START                                 0x00406400
+#define BCHP_PWM_REG_END                                   0x00406424
+#define BCHP_GIO_REG_START                                 0x00406500
+#define BCHP_GIO_REG_END                                   0x0040659c
+#define BCHP_IRQ0_REG_START                                0x00406600
+#define BCHP_IRQ0_REG_END                                  0x00406604
+#define BCHP_IRQ1_REG_START                                0x00406640
+#define BCHP_IRQ1_REG_END                                  0x00406644
+#define BCHP_TIMER_REG_START                               0x00406680
+#define BCHP_TIMER_REG_END                                 0x004066bc
+#define BCHP_UARTA_REG_START                               0x00406800
+#define BCHP_UARTA_REG_END                                 0x0040681c
+#define BCHP_UARTB_REG_START                               0x00406840
+#define BCHP_UARTB_REG_END                                 0x0040685c
+#define BCHP_UARTC_REG_START                               0x00406880
+#define BCHP_UARTC_REG_END                                 0x0040689c
+#define BCHP_SCA_REG_START                                 0x00406a00
+#define BCHP_SCA_REG_END                                   0x00406abc
+#define BCHP_SCB_REG_START                                 0x00406b00
+#define BCHP_SCB_REG_END                                   0x00406bbc
+#define BCHP_SCIRQ0_REG_START                              0x00406c00
+#define BCHP_SCIRQ0_REG_END                                0x00406c04
+#define BCHP_SCIRQ1_REG_START                              0x00406c80
+#define BCHP_SCIRQ1_REG_END                                0x00406c84
+#define BCHP_AON_CTRL_REG_START                            0x00408000
+#define BCHP_AON_CTRL_REG_END                              0x004083fc
+#define BCHP_AON_L2_REG_START                              0x00408400
+#define BCHP_AON_L2_REG_END                                0x0040842c
+#define BCHP_AON_PM_L2_REG_START                           0x00408440
+#define BCHP_AON_PM_L2_REG_END                             0x0040846c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00408500
+#define BCHP_AON_PIN_CTRL_REG_END                          0x0040851c
+#define BCHP_AON_HDMI_TX_REG_START                         0x00408600
+#define BCHP_AON_HDMI_TX_REG_END                           0x00408698
+#define BCHP_LDK_REG_START                                 0x00408800
+#define BCHP_LDK_REG_END                                   0x0040883c
+#define BCHP_PM_AON_REG_START                              0x00408840
+#define BCHP_PM_AON_REG_END                                0x00408848
+#define BCHP_ICAP_REG_START                                0x00408880
+#define BCHP_ICAP_REG_END                                  0x004088bc
+#define BCHP_KBD1_REG_START                                0x004088c0
+#define BCHP_KBD1_REG_END                                  0x004088fc
+#define BCHP_KBD2_REG_START                                0x00408900
+#define BCHP_KBD2_REG_END                                  0x0040893c
+#define BCHP_BSCD_REG_START                                0x00408980
+#define BCHP_BSCD_REG_END                                  0x004089d4
+#define BCHP_MSPI_REG_START                                0x00408a00
+#define BCHP_MSPI_REG_END                                  0x00408b7c
+#define BCHP_IRQ0_AON_REG_START                            0x00408b80
+#define BCHP_IRQ0_AON_REG_END                              0x00408b84
+#define BCHP_IRQ1_AON_REG_START                            0x00408b88
+#define BCHP_IRQ1_AON_REG_END                              0x00408b8c
+#define BCHP_GIO_AON_REG_START                             0x00408c00
+#define BCHP_GIO_AON_REG_END                               0x00408c5c
+#define BCHP_BICAP_REG_START                               0x00408e00
+#define BCHP_BICAP_REG_END                                 0x00408e38
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00408e40
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x00408e6c
+#define BCHP_WKTMR_REG_START                               0x00408e80
+#define BCHP_WKTMR_REG_END                                 0x00408e90
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0040e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0040e0b4
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0040e700
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0040e704
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0040e800
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0040e87c
+#define BCHP_SDIO_0_HOST_REG_START                         0x00410000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004100fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00410100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004101fc
+#define BCHP_MISB_BRIDGE_REG_START                         0x00410400
+#define BCHP_MISB_BRIDGE_REG_END                           0x00410408
+#define BCHP_EBI_REG_START                                 0x00410800
+#define BCHP_EBI_REG_END                                   0x00410bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00411000
+#define BCHP_HIF_INTR2_REG_END                             0x0041102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00411100
+#define BCHP_IPI0_INTR2_REG_END                            0x0041112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00411200
+#define BCHP_IPI1_INTR2_REG_END                            0x0041122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00411400
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0041142c
+#define BCHP_HIF_CPU_TP1_INTR1_REG_START                   0x00411600
+#define BCHP_HIF_CPU_TP1_INTR1_REG_END                     0x0041162c
+#define BCHP_HIF_RGR_REG_START                             0x00411800
+#define BCHP_HIF_RGR_REG_END                               0x00411810
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00411d00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00411d2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00412400
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0041241c
+#define BCHP_NAND_REG_START                                0x00412800
+#define BCHP_NAND_REG_END                                  0x00412bfc
+#define BCHP_BSPI_REG_START                                0x00413000
+#define BCHP_BSPI_REG_END                                  0x0041304c
+#define BCHP_BSPI_RAF_REG_START                            0x00413100
+#define BCHP_BSPI_RAF_REG_END                              0x00413120
+#define BCHP_HIF_MSPI_REG_START                            0x00413200
+#define BCHP_HIF_MSPI_REG_END                              0x00413384
+#define BCHP_MICH_REG_START                                0x00414000
+#define BCHP_MICH_REG_END                                  0x00414000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00414100
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00414100
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00414200
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00414200
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00414300
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00414300
+#define BCHP_NAND_SECURE_REG_START                         0x00414400
+#define BCHP_NAND_SECURE_REG_END                           0x00414400
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_START        0x00414800
+#define BCHP_HIF_SECURE_INDIRECT_SPI_PIPE_REG_END          0x00414800
+#define BCHP_CLKGEN_REG_START                              0x00420000
+#define BCHP_CLKGEN_REG_END                                0x0042036c
+#define BCHP_VCXO_RM_REG_START                             0x00422800
+#define BCHP_VCXO_RM_REG_END                               0x0042282c
+#define BCHP_AVS_HW_MNTR_REG_START                         0x00423000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x00423074
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x00423100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x0042311c
+#define BCHP_AVS_ASB_REGISTERS_REG_START                   0x00423200
+#define BCHP_AVS_ASB_REGISTERS_REG_END                     0x00423218
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x00423300
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004233dc
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x00423400
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x0042349c
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x00423500
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004235e4
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x00423600
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004236e4
+#define BCHP_CLKGEN_INTR2_REG_START                        0x00424000
+#define BCHP_CLKGEN_INTR2_REG_END                          0x0042402c
+#define BCHP_CLKGEN_GR_REG_START                           0x00424800
+#define BCHP_CLKGEN_GR_REG_END                             0x0042480c
+#define BCHP_GENET_0_SYS_REG_START                         0x00430000
+#define BCHP_GENET_0_SYS_REG_END                           0x0043000c
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00430040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x0043004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00430080
+#define BCHP_GENET_0_EXT_REG_END                           0x00430098
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00430200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x0043022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00430240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x0043026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00430300
+#define BCHP_GENET_0_RBUF_REG_END                          0x004303ec
+#define BCHP_GENET_0_TBUF_REG_START                        0x00430600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00430628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00430800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00430ed8
+#define BCHP_GENET_0_HFB_REG_START                         0x00431000
+#define BCHP_GENET_0_HFB_REG_END                           0x00432010
+#define BCHP_GENET_0_RDMA_REG_START                        0x00433000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00433cb4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00434000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00434c88
+#define BCHP_M2MC_REG_START                                0x00450000
+#define BCHP_M2MC_REG_END                                  0x004507fc
+#define BCHP_M2MC_TOP_L2_REG_START                         0x00451000
+#define BCHP_M2MC_TOP_L2_REG_END                           0x0045102c
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_START                  0x00452000
+#define BCHP_M2MC_TOP_GR_BRIDGE_REG_END                    0x0045200c
+#define BCHP_USB_INTR2_REG_START                           0x00480000
+#define BCHP_USB_INTR2_REG_END                             0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x00480238
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480458
+#define BCHP_BOOTROM_REG_START                             0x00500000
+#define BCHP_BOOTROM_REG_END                               0x00500ffc
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_VFD_0_REG_START                               0x00601000
+#define BCHP_VFD_0_REG_END                                 0x006011fc
+#define BCHP_VFD_1_REG_START                               0x00601200
+#define BCHP_VFD_1_REG_END                                 0x006013fc
+#define BCHP_RDC_REG_START                                 0x00602000
+#define BCHP_RDC_REG_END                                   0x006029fc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00603000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060302c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00603100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060312c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00603300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060332c
+#define BCHP_BVNF_INTR2_4_REG_START                        0x00603400
+#define BCHP_BVNF_INTR2_4_REG_END                          0x0060342c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00603500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060352c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00603600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060362c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00603700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060372c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x00604020
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620800
+#define BCHP_SCL_1_REG_END                                 0x00620bfc
+#define BCHP_VNET_F_REG_START                              0x00622000
+#define BCHP_VNET_F_REG_END                                0x0062209c
+#define BCHP_VNET_B_REG_START                              0x00622200
+#define BCHP_VNET_B_REG_END                                0x006222ac
+#define BCHP_MMISC_REG_START                               0x00622800
+#define BCHP_MMISC_REG_END                                 0x00622820
+#define BCHP_LBOX_0_REG_START                              0x00625000
+#define BCHP_LBOX_0_REG_END                                0x00625070
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00626000
+#define BCHP_BVNM_INTR2_0_REG_END                          0x0062602c
+#define BCHP_DNR_0_REG_START                               0x00627000
+#define BCHP_DNR_0_REG_END                                 0x006270a4
+#define BCHP_CAP_0_REG_START                               0x00640000
+#define BCHP_CAP_0_REG_END                                 0x0064007c
+#define BCHP_CAP_1_REG_START                               0x00640200
+#define BCHP_CAP_1_REG_END                                 0x0064027c
+#define BCHP_GFD_0_REG_START                               0x00641000
+#define BCHP_GFD_0_REG_END                                 0x00641228
+#define BCHP_GFD_1_REG_START                               0x00641400
+#define BCHP_GFD_1_REG_END                                 0x00641628
+#define BCHP_CMP_0_REG_START                               0x00642000
+#define BCHP_CMP_0_REG_END                                 0x00642264
+#define BCHP_CMP_1_REG_START                               0x00642800
+#define BCHP_CMP_1_REG_END                                 0x00642a64
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00643000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006430a4
+#define BCHP_MASK_0_REG_START                              0x00643400
+#define BCHP_MASK_0_REG_END                                0x0064341c
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00644000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00645484
+#define BCHP_BVNB_INTR2_REG_START                          0x00646000
+#define BCHP_BVNB_INTR2_REG_END                            0x0064602c
+#define BCHP_BMISC_REG_START                               0x00646400
+#define BCHP_BMISC_REG_END                                 0x0064641c
+#define BCHP_MVP_TOP_0_REG_START                           0x00660000
+#define BCHP_MVP_TOP_0_REG_END                             0x0066002c
+#define BCHP_SIOB_0_REG_START                              0x00660200
+#define BCHP_SIOB_0_REG_END                                0x006602fc
+#define BCHP_HSCL_0_REG_START                              0x00660400
+#define BCHP_HSCL_0_REG_END                                0x006607fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00662000
+#define BCHP_MDI_TOP_0_REG_END                             0x00662044
+#define BCHP_MDI_PPB_0_REG_START                           0x00662800
+#define BCHP_MDI_PPB_0_REG_END                             0x00662bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00662c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00662ffc
+#define BCHP_MISC_REG_START                                0x00680000
+#define BCHP_MISC_REG_END                                  0x00680080
+#define BCHP_IT_0_REG_START                                0x00681000
+#define BCHP_IT_0_REG_END                                  0x006817fc
+#define BCHP_IT_1_REG_START                                0x00682000
+#define BCHP_IT_1_REG_END                                  0x006827fc
+#define BCHP_VF_0_REG_START                                0x00683000
+#define BCHP_VF_0_REG_END                                  0x00683134
+#define BCHP_VF_1_REG_START                                0x00683200
+#define BCHP_VF_1_REG_END                                  0x00683334
+#define BCHP_SECAM_0_REG_START                             0x00683400
+#define BCHP_SECAM_0_REG_END                               0x00683414
+#define BCHP_SM_0_REG_START                                0x00683480
+#define BCHP_SM_0_REG_END                                  0x006834ac
+#define BCHP_SDSRC_0_REG_START                             0x00683500
+#define BCHP_SDSRC_0_REG_END                               0x0068350c
+#define BCHP_HDSRC_0_REG_START                             0x00683520
+#define BCHP_HDSRC_0_REG_END                               0x0068353c
+#define BCHP_CSC_0_REG_START                               0x00683580
+#define BCHP_CSC_0_REG_END                                 0x006835b0
+#define BCHP_CSC_1_REG_START                               0x00683600
+#define BCHP_CSC_1_REG_END                                 0x00683630
+#define BCHP_RM_0_REG_START                                0x00683680
+#define BCHP_RM_0_REG_END                                  0x006836a4
+#define BCHP_RM_1_REG_START                                0x006836c0
+#define BCHP_RM_1_REG_END                                  0x006836e4
+#define BCHP_ANA_DEBUG_0_REG_START                         0x00683700
+#define BCHP_ANA_DEBUG_0_REG_END                           0x00683744
+#define BCHP_GRPD_0_REG_START                              0x00683800
+#define BCHP_GRPD_0_REG_END                                0x006838ec
+#define BCHP_DTRAM_0_REG_START                             0x00684000
+#define BCHP_DTRAM_0_REG_END                               0x0068447c
+#define BCHP_DVI_DTG_0_REG_START                           0x00684800
+#define BCHP_DVI_DTG_0_REG_END                             0x00684954
+#define BCHP_DVI_CSC_0_REG_START                           0x00684a00
+#define BCHP_DVI_CSC_0_REG_END                             0x00684a30
+#define BCHP_DVI_DVF_0_REG_START                           0x00684b00
+#define BCHP_DVI_DVF_0_REG_END                             0x00684b14
+#define BCHP_DVI_DEBUG_0_REG_START                         0x00684c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x00684c44
+#define BCHP_VEC_CFG_REG_START                             0x00685000
+#define BCHP_VEC_CFG_REG_END                               0x006850d4
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x00685400
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x0068542c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x00685500
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x00685518
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x00685600
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x00685608
+#define BCHP_DVP_TVG_0_REG_START                           0x00685700
+#define BCHP_DVP_TVG_0_REG_END                             0x00685788
+#define BCHP_VBI_ENC_REG_START                             0x00686000
+#define BCHP_VBI_ENC_REG_END                               0x00686054
+#define BCHP_CCE_0_REG_START                               0x00686400
+#define BCHP_CCE_0_REG_END                                 0x00686458
+#define BCHP_CCE_1_REG_START                               0x00686500
+#define BCHP_CCE_1_REG_END                                 0x00686558
+#define BCHP_WSE_0_REG_START                               0x00686600
+#define BCHP_WSE_0_REG_END                                 0x00686614
+#define BCHP_WSE_1_REG_START                               0x00686700
+#define BCHP_WSE_1_REG_END                                 0x00686714
+#define BCHP_CGMSAE_0_REG_START                            0x00686800
+#define BCHP_CGMSAE_0_REG_END                              0x00686858
+#define BCHP_CGMSAE_1_REG_START                            0x00686900
+#define BCHP_CGMSAE_1_REG_END                              0x00686958
+#define BCHP_TTE_0_REG_START                               0x00686a00
+#define BCHP_TTE_0_REG_END                                 0x00686a28
+#define BCHP_TTE_1_REG_START                               0x00686b00
+#define BCHP_TTE_1_REG_END                                 0x00686b28
+#define BCHP_GSE_0_REG_START                               0x00686c00
+#define BCHP_GSE_0_REG_END                                 0x00686c80
+#define BCHP_GSE_1_REG_START                               0x00686d00
+#define BCHP_GSE_1_REG_END                                 0x00686d80
+#define BCHP_AMOLE_0_REG_START                             0x00686e00
+#define BCHP_AMOLE_0_REG_END                               0x00686e8c
+#define BCHP_AMOLE_1_REG_START                             0x00686f00
+#define BCHP_AMOLE_1_REG_END                               0x00686f8c
+#define BCHP_DVP_HT_REG_START                              0x006a0000
+#define BCHP_DVP_HT_REG_END                                0x006a00dc
+#define BCHP_HDMI_REG_START                                0x006a0800
+#define BCHP_HDMI_REG_END                                  0x006a0994
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006a0a80
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006a0ad8
+#define BCHP_HDMI_RM_REG_START                             0x006a0b00
+#define BCHP_HDMI_RM_REG_END                               0x006a0b2c
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006a0b40
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006a0b6c
+#define BCHP_HDMI_RAM_REG_START                            0x006a0c00
+#define BCHP_HDMI_RAM_REG_END                              0x006a0dfc
+#define BCHP_BVN_RGR_REG_START                             0x006a8000
+#define BCHP_BVN_RGR_REG_END                               0x006a8010
+#define BCHP_SDS_CG_REG_START                              0x00700000
+#define BCHP_SDS_CG_REG_END                                0x00700038
+#define BCHP_SDS_FE_REG_START                              0x00700080
+#define BCHP_SDS_FE_REG_END                                0x007000bc
+#define BCHP_SDS_AGC_REG_START                             0x00700100
+#define BCHP_SDS_AGC_REG_END                               0x00700124
+#define BCHP_SDS_BL_REG_START                              0x00700140
+#define BCHP_SDS_BL_REG_END                                0x00700160
+#define BCHP_SDS_CL_REG_START                              0x00700180
+#define BCHP_SDS_CL_REG_END                                0x007001fc
+#define BCHP_SDS_EQ_REG_START                              0x00700200
+#define BCHP_SDS_EQ_REG_END                                0x0070028c
+#define BCHP_SDS_HP_REG_START                              0x00700300
+#define BCHP_SDS_HP_REG_END                                0x007003d4
+#define BCHP_SDS_VIT_REG_START                             0x00700400
+#define BCHP_SDS_VIT_REG_END                               0x00700428
+#define BCHP_SDS_FEC_REG_START                             0x00700440
+#define BCHP_SDS_FEC_REG_END                               0x00700454
+#define BCHP_SDS_OI_REG_START                              0x00700480
+#define BCHP_SDS_OI_REG_END                                0x007004c8
+#define BCHP_SDS_SNR_REG_START                             0x00700500
+#define BCHP_SDS_SNR_REG_END                               0x00700518
+#define BCHP_SDS_BERT_REG_START                            0x00700540
+#define BCHP_SDS_BERT_REG_END                              0x0070055c
+#define BCHP_SDS_DFT_REG_START                             0x00700580
+#define BCHP_SDS_DFT_REG_END                               0x007005a8
+#define BCHP_SDS_CWC_REG_START                             0x00700600
+#define BCHP_SDS_CWC_REG_END                               0x00700694
+#define BCHP_SDS_MISC_REG_START                            0x00700700
+#define BCHP_SDS_MISC_REG_END                              0x00700798
+#define BCHP_SDS_DSEC_REG_START                            0x00700800
+#define BCHP_SDS_DSEC_REG_END                              0x007008c8
+#define BCHP_SDS_TUNER_REG_START                           0x00700900
+#define BCHP_SDS_TUNER_REG_END                             0x007009fc
+#define BCHP_SDS_INTR2_0_REG_START                         0x00700a00
+#define BCHP_SDS_INTR2_0_REG_END                           0x00700a2c
+#define BCHP_SDS_INTR2_1_REG_START                         0x00700b00
+#define BCHP_SDS_INTR2_1_REG_END                           0x00700b2c
+#define BCHP_SDS_GR_BRIDGE_REG_START                       0x00700c00
+#define BCHP_SDS_GR_BRIDGE_REG_END                         0x00700c0c
+#define BCHP_TFEC_REG_START                                0x00702000
+#define BCHP_TFEC_REG_END                                  0x00702060
+#define BCHP_TFEC_MISC_REG_START                           0x00702100
+#define BCHP_TFEC_MISC_REG_END                             0x00702108
+#define BCHP_TFEC_INTR2_REG_START                          0x00702200
+#define BCHP_TFEC_INTR2_REG_END                            0x0070222c
+#define BCHP_TFEC_GR_BRIDGE_REG_START                      0x00702300
+#define BCHP_TFEC_GR_BRIDGE_REG_END                        0x0070230c
+#define BCHP_AFEC_REG_START                                0x00704000
+#define BCHP_AFEC_REG_END                                  0x007043fc
+#define BCHP_AFEC_INTR_CTRL2_REG_START                     0x00704800
+#define BCHP_AFEC_INTR_CTRL2_REG_END                       0x0070482c
+#define BCHP_AFEC_GR_BRIDGE_REG_START                      0x00704900
+#define BCHP_AFEC_GR_BRIDGE_REG_END                        0x0070490c
+#define BCHP_AFEC_GLOBAL_REG_START                         0x00704a00
+#define BCHP_AFEC_GLOBAL_REG_END                           0x00704a0c
+#define BCHP_FTM_UART_REG_START                            0x00706000
+#define BCHP_FTM_UART_REG_END                              0x007060fc
+#define BCHP_FTM_PHY_REG_START                             0x00706000
+#define BCHP_FTM_PHY_REG_END                               0x007061fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x00706000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x00706210
+#define BCHP_FTM_SKIT_REG_START                            0x00706000
+#define BCHP_FTM_SKIT_REG_END                              0x00706248
+#define BCHP_FTM_INTR2_REG_START                           0x00706000
+#define BCHP_FTM_INTR2_REG_END                             0x0070632c
+#define BCHP_FTM_GR_BRIDGE_REG_START                       0x00706000
+#define BCHP_FTM_GR_BRIDGE_REG_END                         0x0070633c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x00706000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x00706344
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00800000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00800008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00820000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x0082044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00821000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00821058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00821080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x0082109c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00821100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00821154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00821400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00821664
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00822000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00822014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00822200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x0082222c
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00822400
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x0082242c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00823000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x0082357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00830000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x0083bffc
+#define BCHP_AIO_MISC_REG_START                            0x00880000
+#define BCHP_AIO_MISC_REG_END                              0x00880010
+#define BCHP_AIO_INTH_REG_START                            0x00880800
+#define BCHP_AIO_INTH_REG_END                              0x0088082c
+#define BCHP_AIO_INTD0_REG_START                           0x00880a00
+#define BCHP_AIO_INTD0_REG_END                             0x00880a14
+#define BCHP_AUD_FMM_MISC_REG_START                        0x008a0000
+#define BCHP_AUD_FMM_MISC_REG_END                          0x008a010c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x008a2000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x008a2b7c
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_START                   0x008a3000
+#define BCHP_AUD_FMM_BF_ESR0_H_REG_END                     0x008a3014
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_START                   0x008a3020
+#define BCHP_AUD_FMM_BF_ESR1_H_REG_END                     0x008a3034
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_START                   0x008a3040
+#define BCHP_AUD_FMM_BF_ESR2_H_REG_END                     0x008a3054
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_START                  0x008a3100
+#define BCHP_AUD_FMM_BF_ESR0_D0_REG_END                    0x008a3114
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_START                  0x008a3120
+#define BCHP_AUD_FMM_BF_ESR1_D0_REG_END                    0x008a3134
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_START                  0x008a3140
+#define BCHP_AUD_FMM_BF_ESR2_D0_REG_END                    0x008a3154
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x008a4000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x008a4bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x008a5000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x008a5014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x008a8000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x008a98ec
+#define BCHP_AUD_FMM_DP_ESR00_REG_START                    0x008abc00
+#define BCHP_AUD_FMM_DP_ESR00_REG_END                      0x008abc14
+#define BCHP_AUD_FMM_DP_ESR20_REG_START                    0x008abc80
+#define BCHP_AUD_FMM_DP_ESR20_REG_END                      0x008abc94
+#define BCHP_AUD_FMM_IOP_CTRL_REG_START                    0x008b8000
+#define BCHP_AUD_FMM_IOP_CTRL_REG_END                      0x008b8144
+#define BCHP_AUD_FMM_IOP_ESR_REG_START                     0x008b8400
+#define BCHP_AUD_FMM_IOP_ESR_REG_END                       0x008b8414
+#define BCHP_AUD_FMM_OP_CTRL_REG_START                     0x008ba000
+#define BCHP_AUD_FMM_OP_CTRL_REG_END                       0x008ba1fc
+#define BCHP_AUD_FMM_OP_ESR_REG_START                      0x008ba400
+#define BCHP_AUD_FMM_OP_ESR_REG_END                        0x008ba414
+#define BCHP_AUD_FMM_PLL0_REG_START                        0x008ba800
+#define BCHP_AUD_FMM_PLL0_REG_END                          0x008ba834
+#define BCHP_AUD_FMM_PLL1_REG_START                        0x008ba900
+#define BCHP_AUD_FMM_PLL1_REG_END                          0x008ba934
+#define BCHP_HIFIDAC_CTRL0_REG_START                       0x008bb000
+#define BCHP_HIFIDAC_CTRL0_REG_END                         0x008bb1fc
+#define BCHP_HIFIDAC_RM0_REG_START                         0x008bb200
+#define BCHP_HIFIDAC_RM0_REG_END                           0x008bb224
+#define BCHP_HIFIDAC_ESR0_REG_START                        0x008bb300
+#define BCHP_HIFIDAC_ESR0_REG_END                          0x008bb314
+#define BCHP_AUD_FMM_MS_CTRL_REG_START                     0x008bc000
+#define BCHP_AUD_FMM_MS_CTRL_REG_END                       0x008bdbfc
+#define BCHP_AUD_FMM_MS_ESR_REG_START                      0x008be000
+#define BCHP_AUD_FMM_MS_ESR_REG_END                        0x008be014
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00900000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00900000
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00000
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a00088
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a01000
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a0109c
+#define BCHP_XPT_PMU_REG_START                             0x00a01800
+#define BCHP_XPT_PMU_REG_END                               0x00a01808
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a02000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a02fbc
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a03000
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a03020
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a03100
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a03120
+#define BCHP_XPT_FE_REG_START                              0x00a04000
+#define BCHP_XPT_FE_REG_END                                0x00a04ffc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a06000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a06074
+#define BCHP_XPT_DPCR1_REG_START                           0x00a06080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a060f4
+#define BCHP_XPT_DPCR2_REG_START                           0x00a06100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a06174
+#define BCHP_XPT_DPCR3_REG_START                           0x00a06180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a061f4
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a06400
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a06404
+#define BCHP_XPT_PSUB_REG_START                            0x00a06600
+#define BCHP_XPT_PSUB_REG_END                              0x00a066c8
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a06800
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a06f2c
+#define BCHP_XPT_PB0_REG_START                             0x00a07000
+#define BCHP_XPT_PB0_REG_END                               0x00a07060
+#define BCHP_XPT_PB1_REG_START                             0x00a07080
+#define BCHP_XPT_PB1_REG_END                               0x00a070e0
+#define BCHP_XPT_PB2_REG_START                             0x00a07100
+#define BCHP_XPT_PB2_REG_END                               0x00a07160
+#define BCHP_XPT_PB3_REG_START                             0x00a07180
+#define BCHP_XPT_PB3_REG_END                               0x00a071e0
+#define BCHP_XPT_MPOD_REG_START                            0x00a08000
+#define BCHP_XPT_MPOD_REG_END                              0x00a08020
+#define BCHP_XPT_RMX0_REG_START                            0x00a08400
+#define BCHP_XPT_RMX0_REG_END                              0x00a08408
+#define BCHP_XPT_RMX1_REG_START                            0x00a08500
+#define BCHP_XPT_RMX1_REG_END                              0x00a08508
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a0a000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a0bcc8
+#define BCHP_XPT_RAVE_REG_START                            0x00a10000
+#define BCHP_XPT_RAVE_REG_END                              0x00a1a69c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a1b000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a1bffc
+#define BCHP_XPT_MSG_REG_START                             0x00a20000
+#define BCHP_XPT_MSG_REG_END                               0x00a24814
+#define BCHP_XPT_GR_REG_START                              0x00a25000
+#define BCHP_XPT_GR_REG_END                                0x00a2500c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a26000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a27050
+#define BCHP_XPT_XPU_REG_START                             0x00a28000
+#define BCHP_XPT_XPU_REG_END                               0x00a2c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a38000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a38000
+#define BCHP_RFM_SYSCLK_REG_START                          0x00b00000
+#define BCHP_RFM_SYSCLK_REG_END                            0x00b00118
+#define BCHP_RFM_CLK27_REG_START                           0x00b00000
+#define BCHP_RFM_CLK27_REG_END                             0x00b00470
+#define BCHP_RFM_L2_REG_START                              0x00b00c00
+#define BCHP_RFM_L2_REG_END                                0x00b00c2c
+#define BCHP_RFM_GRB_REG_START                             0x00b01000
+#define BCHP_RFM_GRB_REG_END                               0x00b0100c
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK      0xffffffff
+#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT     0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_DST_COLOR_MATRIX_N - Linked-List Packet Word N for group DST_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_DST_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_11_DST_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_12_OUTPUT_COLOR_MATRIX_N - Linked-List Packet Word N for group OUTPUT_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_12_OUTPUT_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_12_OUTPUT_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_13_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_13_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_13_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *LIST_PKT_14_DST_CLUT - Linked-List Packet Word for group DST_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_14_DST_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_14_DST_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_14_DST_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *MEM_DMA
+ ***************************************************************************/
+/***************************************************************************
+ *DESC_WORD0 - MEM DMA Descriptor Word 0
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD1 - MEM DMA Descriptor Word 1
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK                    0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD2 - MEM DMA Descriptor Word 2
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK                   0x80000000
+#define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT                  31
+
+/* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK                          0x40000000
+#define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT                         30
+
+/* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK                   0x20000000
+#define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT                  29
+
+/* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK                     0x1e000000
+#define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT                    25
+
+/* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK                 0x01ffffff
+#define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT                0
+
+/***************************************************************************
+ *DESC_WORD3 - MEM DMA Descriptor Word 3
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK                0xffffffe0
+#define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT               5
+
+/* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK                     0x00000018
+#define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT                    3
+
+/* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK              0x00000004
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT             2
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN        0
+#define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN     1
+
+/* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK       0x00000003
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT      0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2
+#define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved   3
+
+/***************************************************************************
+ *DESC_WORD4 - MEM DMA Descriptor Word 4
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT                    16
+
+/* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK                0x0000c000
+#define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT               14
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK                  0x00002000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT                 13
+
+/* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK                0x00001000
+#define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT               12
+
+/* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK                     0x00000800
+#define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT                    11
+
+/* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK                  0x00000400
+#define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT                 10
+
+/* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK                      0x00000300
+#define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT                     8
+
+/* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK                    0x000000ff
+#define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT                   0
+
+/***************************************************************************
+ *DESC_WORD5 - MEM DMA Descriptor Word 5
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD6 - MEM DMA Descriptor Word 6
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *DESC_WORD7 - MEM DMA Descriptor Word 7
+ ***************************************************************************/
+/* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK                     0xffffffff
+#define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT                    0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right -2147483648
+
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/***************************************************************************
+ *XPT_PB
+ ***************************************************************************/
+/***************************************************************************
+ *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract
+ ***************************************************************************/
+/* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK     0xffffffff
+#define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT    0
+
+/***************************************************************************
+ *DESC_0 - Playback Linked-List Descriptor Word 0
+ ***************************************************************************/
+/* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK               0xffffffff
+#define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT              0
+
+/***************************************************************************
+ *DESC_1 - Playback Linked-List Descriptor Word 1
+ ***************************************************************************/
+/* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK                   0xffffffff
+#define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT                  0
+
+/***************************************************************************
+ *DESC_2 - Playback Linked-List Descriptor Word 2
+ ***************************************************************************/
+/* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK                0x80000000
+#define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT               31
+
+/* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK                    0x40000000
+#define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT                   30
+
+/* XPT_PB :: DESC_2 :: PB_HOST_DATA_INS_EN [29:29] */
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_MASK                0x20000000
+#define BCHP_XPT_PB_DESC_2_PB_HOST_DATA_INS_EN_SHIFT               29
+
+/* XPT_PB :: DESC_2 :: reserved0 [28:28] */
+#define BCHP_XPT_PB_DESC_2_reserved0_MASK                          0x10000000
+#define BCHP_XPT_PB_DESC_2_reserved0_SHIFT                         28
+
+/* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK                     0x0f000000
+#define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT                    24
+
+/* XPT_PB :: DESC_2 :: reserved1 [23:00] */
+#define BCHP_XPT_PB_DESC_2_reserved1_MASK                          0x00ffffff
+#define BCHP_XPT_PB_DESC_2_reserved1_SHIFT                         0
+
+/***************************************************************************
+ *DESC_3 - Playback Linked-List Descriptor Word 3
+ ***************************************************************************/
+/* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK                  0xfffffff0
+#define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT                 4
+
+/* XPT_PB :: DESC_3 :: reserved0 [03:01] */
+#define BCHP_XPT_PB_DESC_3_reserved0_MASK                          0x0000000e
+#define BCHP_XPT_PB_DESC_3_reserved0_SHIFT                         1
+
+/* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK                   0x00000001
+#define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT                  0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h
new file mode 100644
index 000000000000..3549fcd460c6
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_control_regs_0.h
@@ -0,0 +1,1539 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_control_regs_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:43a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */
+
+/***************************************************************************
+ *REVISION - Address & Control revision register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       0x00000040
+
+/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       0x00000006
+
+/***************************************************************************
+ *CLK_PM_CTRL - PHY clock power management control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_STATUS - PHY PLL status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0
+
+/***************************************************************************
+ *PLL_CONFIG - PHY PLL configuration register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PLL_CONTROL - PHY PLL control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     0x0000000a
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     0x00000003
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_DIVIDERS - PHY PLL dividers control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    0x00000004
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    0x00000020
+
+/***************************************************************************
+ *AUX_CONTROL - Aux Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0x00000000
+
+/***************************************************************************
+ *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 0x00000007
+
+/***************************************************************************
+ *VDL_CALIBRATE - PHY VDL calibration control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 0x00000001
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_CALIB_STATUS - PHY VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 0x00000001
+
+/***************************************************************************
+ *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 0x00ffffff
+
+/***************************************************************************
+ *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 0x0003ffff
+
+/***************************************************************************
+ *VREF_DAC_CONTROL - VREF DAC Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
+
+/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
+
+/***************************************************************************
+ *PHYBIST_CNTRL - PhyBist Control Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_SEED - PhyBist Seed Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    0x250e4af6
+
+/***************************************************************************
+ *PHYBIST_STATUS - PhyBist General Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0
+
+/***************************************************************************
+ *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0
+
+/***************************************************************************
+ *COMMAND_REG - DRAM Command Register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0x00000000
+
+/***************************************************************************
+ *MODE_REG0 - Mode Register 0
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG1 - Mode Register 1
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG2 - Mode Register 2
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MODE_REG3 - Mode Register 3
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STANDBY_CONTROL - Standby Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 0x00000002
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_CONTROL2 - Strap Control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STRAP_STATUS - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0
+
+/***************************************************************************
+ *STRAP_STATUS2 - Strap Status register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7
+
+/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0
+
+/***************************************************************************
+ *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DATAPATH_LOOPBACK - Datapth Loopback control register
+ ***************************************************************************/
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0x00000000
+
+/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
+#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h
new file mode 100644
index 000000000000..c7800bb634a5
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ddr40_phy_word_lane_0_0.h
@@ -0,0 +1,3334 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ddr40_phy_word_lane_0_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:44a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_H__
+
+/***************************************************************************
+ *DDR40_PHY_WORD_LANE_0_0 - DDR40 DDR40 word lane #0 control registers 0
+ ***************************************************************************/
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6200 /* Read Enable Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W 0x003b6204 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P 0x003b6208 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N 0x003b620c /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6210 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6214 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6218 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b621c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6220 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6224 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6228 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b622c /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6230 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6234 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6238 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b623c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6240 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6244 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6248 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b624c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6250 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6254 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6258 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b625c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6260 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6264 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6268 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b626c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6270 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6274 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W 0x003b62a4 /* Write Byte VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P 0x003b62a8 /* Read Byte DQSP VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N 0x003b62ac /* Read Byte DQSN VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b62b0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b62b4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b62b8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b62bc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b62c0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b62c4 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b62c8 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b62cc /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W 0x003b62d0 /* Write Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b62d4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b62d8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b62dc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b62e0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b62e4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b62e8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b62ec /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b62f0 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b62f4 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b62f8 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b62fc /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6300 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6304 /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6308 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b630c /* Read DQSP Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6310 /* Read DQSN Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6314 /* Read Enable Bit VDL static override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6328 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b632c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6330 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6334 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6338 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b633c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6348 /* Read DQSP VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b634c /* Read DQSN VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6350 /* Read DQ-P VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6354 /* Read DQ-N VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6358 /* Write DQ Byte VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b635c /* Write DQ Bit VDL dynamic override control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY 0x003b6360 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL 0x003b6364 /* Word Lane read channel control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0 0x003b6370 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1 0x003b6374 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2 0x003b6378 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3 0x003b637c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0 0x003b6380 /* Read fifo data register, first data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1 0x003b6384 /* Read fifo data register, second data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2 0x003b6388 /* Read fifo data register, third data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3 0x003b638c /* Read fifo data register, fourth data */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS 0x003b6390 /* Read fifo status register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR 0x003b6394 /* Read fifo status clear register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL 0x003b63a0 /* Idle mode SSTL pad control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL 0x003b63a4 /* SSTL pad drive characteristics control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE 0x003b63a8 /* Clock pad disable register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE 0x003b63ac /* Write cycle preamble control register */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ 0x003b63b0 /* PHYBIST mode VDL step select adjustment register */
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE_RD_EN - Read Enable Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE0_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_W - Write Byte VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_MASK  0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_P - Read Byte DQSP VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_R_N - Read Byte DQSN VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_DM_W - Write Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_DM_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT0_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT1_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT2_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT2_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT3_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT3_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT4_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT4_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT5_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT5_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT6_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT6_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_P - Read DQSP Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT7_R_N - Read DQSN Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT7_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VDL_OVRIDE_BYTE1_BIT_RD_EN - Read Enable Bit VDL static override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_MASK 0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_SHIFT 31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_busy_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_MASK 0x7ffc0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved0_SHIFT 18
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_MASK 0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_force_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE0_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_P - Read DQSP VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_R_N - Read DQSN VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_P - Read DQ-P VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_R_N - Read DQ-N VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_W - Write DQ Byte VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_MASK 0xfffe0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved0_SHIFT 17
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_MASK 0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DYN_VDL_OVRIDE_BYTE1_BIT_W - Write DQ Bit VDL dynamic override control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_MASK 0xfe000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved0_SHIFT 25
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_MASK 0x01000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_dm_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_MASK 0x00ff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_MASK 0x0000fe00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved1_SHIFT 9
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_byte_sel_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_MASK 0x000000c0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_reserved2_SHIFT 6
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_MASK 0x0000003f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_ovr_step_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_DATA_DLY - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_MASK  0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_MASK 0x00000007
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_DATA_DLY_rd_data_dly_DEFAULT 0x00000001
+
+/***************************************************************************
+ *READ_CONTROL - Word Lane read channel control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_MASK   0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_reserved0_SHIFT  3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_enable [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_enable_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_te_adj_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_CONTROL_dq_odt_le_adj_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL0_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL0_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_0 - Read fifo data register, first data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_0_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_1 - Read fifo data register, second data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_1_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_2 - Read fifo data register, third data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_2_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_DATA_BL1_3 - Read fifo data register, fourth data
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_MASK 0xffff0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_reserved0_SHIFT 16
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_MASK 0x0000ff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_p_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_MASK 0x000000ff
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_DATA_BL1_3_data_n_SHIFT 0
+
+/***************************************************************************
+ *READ_FIFO_STATUS - Read fifo status register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xffffff00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 8
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status1 [07:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_MASK 0x000000f0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status1_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_STATUS :: status0 [03:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_MASK 0x0000000f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_STATUS_status0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *READ_FIFO_CLEAR - Read fifo status clear register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
+
+/* DDR40_PHY_WORD_LANE_0_0 :: READ_FIFO_CLEAR :: clear [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_READ_FIFO_CLEAR_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_MASK    0x80000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_SHIFT   31
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_idle_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 24
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_MASK 0x00c00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_SHIFT 22
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_rxenb_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_MASK 0x00300000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_SHIFT 20
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_auto_dq_iddq_mode_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00080000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 19
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00040000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 18
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_MASK  0x00020000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 17
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_MASK  0x00010000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dq_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00008000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 15
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_rxenb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00004000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 14
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00002000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 13
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00001000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 12
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_read_enb_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_iddq_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_dqs_oeb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_MASK 0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_SHIFT 6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_MASK 0x00000010
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_SHIFT 4
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk1_oeb_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_MASK 0x00000008
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_rxenb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_iddq_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_reb_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_IDLE_PAD_CONTROL_clk0_oeb_DEFAULT 0x00000000
+
+/***************************************************************************
+ *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK  0xfffff000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 12
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_MASK  0x00000800
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_SHIFT 11
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_no_dqs_rd_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_MASK 0x00000400
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_SHIFT 10
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_always_on_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_MASK 0x00000200
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_SHIFT 9
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_dqs_tx_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_MASK 0x00000100
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_ck_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000080
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_SHIFT 7
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_MASK    0x00000040
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_SHIFT   6
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rdqs_en_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_MASK      0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_SHIFT     2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt60b_DEFAULT   0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_MASK   0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_SHIFT  1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 0x00000001
+
+/* DDR40_PHY_WORD_LANE_0_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_MASK      0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_SHIFT     0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_DRIVE_PAD_CTL_g_ddr_DEFAULT   0x00000000
+
+/***************************************************************************
+ *CLOCK_PAD_DISABLE - Clock pad disable register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffff8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 3
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_MASK 0x00000004
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_SHIFT 2
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_dm_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_MASK 0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_SHIFT 1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk1_pad_dis_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_MASK 0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_CLOCK_PAD_DISABLE_clk0_pad_dis_DEFAULT 0x00000000
+
+/***************************************************************************
+ *WR_PREAMBLE_MODE - Write cycle preamble control register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffc
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 2
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: long [01:01] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_MASK    0x00000002
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_SHIFT   1
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_long_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: WR_PREAMBLE_MODE :: mode [00:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_MASK    0x00000001
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_SHIFT   0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_WR_PREAMBLE_MODE_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHYBIST_VDL_ADJ - PHYBIST mode VDL step select adjustment register
+ ***************************************************************************/
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_MASK 0xe0000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved0_SHIFT 29
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_MASK 0x1f000000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_SHIFT 24
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_MASK 0x00e00000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved1_SHIFT 21
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_MASK 0x001f0000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_SHIFT 16
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dq0_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_MASK 0x0000e000
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved2_SHIFT 13
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_MASK 0x00001f00
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_SHIFT 8
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs1_vdl_adj_DEFAULT 0x00000000
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_MASK 0x000000e0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_reserved3_SHIFT 5
+
+/* DDR40_PHY_WORD_LANE_0_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_MASK 0x0000001f
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_SHIFT 0
+#define BCHP_DDR40_PHY_WORD_LANE_0_0_PHYBIST_VDL_ADJ_dqs0_vdl_adj_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_0_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_ebi.h b/include/linux/brcmstb/7362a0/bchp_ebi.h
new file mode 100644
index 000000000000..ef241e78950a
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_ebi.h
@@ -0,0 +1,1472 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_ebi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:47a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_0                       0x00410800 /* EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00410804 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00410808 /* EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x0041080c /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_2                       0x00410810 /* EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00410814 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00410818 /* EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0041081c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00410820 /* EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00410824 /* EBI CS Config 4 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00410840 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00410844 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00410848 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0041084c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00410850 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00410900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00410918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_TA_CFG                          0x0041091c /* EBI TA Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00410920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004109f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_0 - EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000001
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_1 - EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffffe0
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   5
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TA_CFG - EBI TA Configuration Register
+ ***************************************************************************/
+/* EBI :: TA_CFG :: reserved0 [31:04] */
+#define BCHP_EBI_TA_CFG_reserved0_MASK                             0xfffffff0
+#define BCHP_EBI_TA_CFG_reserved0_SHIFT                            4
+
+/* EBI :: TA_CFG :: use_ta3 [03:03] */
+#define BCHP_EBI_TA_CFG_use_ta3_MASK                               0x00000008
+#define BCHP_EBI_TA_CFG_use_ta3_SHIFT                              3
+#define BCHP_EBI_TA_CFG_use_ta3_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: use_ta2 [02:02] */
+#define BCHP_EBI_TA_CFG_use_ta2_MASK                               0x00000004
+#define BCHP_EBI_TA_CFG_use_ta2_SHIFT                              2
+#define BCHP_EBI_TA_CFG_use_ta2_DEFAULT                            0x00000000
+
+/* EBI :: TA_CFG :: use_ta1 [01:01] */
+#define BCHP_EBI_TA_CFG_use_ta1_MASK                               0x00000002
+#define BCHP_EBI_TA_CFG_use_ta1_SHIFT                              1
+#define BCHP_EBI_TA_CFG_use_ta1_DEFAULT                            0x00000001
+
+/* EBI :: TA_CFG :: reserved1 [00:00] */
+#define BCHP_EBI_TA_CFG_reserved1_MASK                             0x00000001
+#define BCHP_EBI_TA_CFG_reserved1_SHIFT                            0
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:16] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff0000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     16
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_7_USES_SPI [15:15] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_MASK              0x00008000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_SHIFT             15
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_7_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_7_SEL [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_MASK               0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_SHIFT              7
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_7_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00410a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h b/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h
new file mode 100644
index 000000000000..d2b84918793a
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_cpu_intr1.h
@@ -0,0 +1,2019 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_cpu_intr1.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:55a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_CPU_INTR1_H__
+#define BCHP_HIF_CPU_INTR1_H__
+
+/***************************************************************************
+ *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00411400 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00411404 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00411408 /* Interrupt Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0041140c /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00411410 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00411414 /* Interrupt Mask Status Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00411418 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0041141c /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00411420 /* Interrupt Mask Set Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00411424 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00411428 /* Interrupt Mask Clear Register */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0041142c /* Interrupt Mask Clear Register */
+
+/***************************************************************************
+ *INTR_W0_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK    0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT   29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_MASK       0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_SHIFT      28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_M2MC_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK  0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK  0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK     0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT    7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK     0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT    6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK     0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT    5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK     0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT    4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK     0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT    3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK        0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT       1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_W1_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_MASK  0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_MASK    0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_SHIFT   28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_MASK    0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_SHIFT   27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK     0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT    26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK    0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT   22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK     0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT    18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK    0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT   17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK        0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT       16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_MASK   0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_SHIFT  13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_MASK   0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_SHIFT  12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_MASK  0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_MASK  0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK      0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT     5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT   0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK    0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT   4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_MASK     0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_SHIFT    2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_MEMC_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_DEFAULT    0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_W2_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_MASK   0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_SHIFT  31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_MASK   0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_SHIFT  29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_MASK   0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_SHIFT  27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_MASK   0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_SHIFT  25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_MASK   0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_SHIFT  24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_MASK        0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_SHIFT       23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_RFM_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_MASK   0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_SHIFT  21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_MASK     0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_SHIFT    20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_AVD0_0_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_MASK   0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_SHIFT  19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_MASK    0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_SHIFT   18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK    0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT   15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK   0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT  14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK    0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT   12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK     0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT    11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT  0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK        0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT       10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT     0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_MASK   0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_SHIFT  9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_MASK   0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_SHIFT  8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000000
+
+/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK   0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT  16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_MASK   0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_SHIFT  23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT  10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK  0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_MASK     0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_SHIFT    28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_M2MC_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK   0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT  7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK   0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT  6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK   0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT  5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK   0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT  4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK   0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT  3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK      0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT     1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK   0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT  26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK   0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT  18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK  0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK      0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT     16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK    0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT   5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK  0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_SHIFT  2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_DEFAULT  0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_SET - Interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_MASK      0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_SHIFT     23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_RFM_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_MASK   0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_SHIFT  20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_MASK  0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK  0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT  11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK      0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT     10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT   0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   30
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: M2MC_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_MASK   0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_SHIFT  28
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_M2MC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_01_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SPARE_00_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SPARE_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_09_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_08_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_07_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK    0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT   1
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   0
+#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART2_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART1_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_UART0_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_TMR_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SPI_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 23
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_08_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_08_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_07_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_07_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK    0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT   16
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_06_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_06_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_05_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_05_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_04_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_04_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_03_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_03_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_TFEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_MASK 0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_SHIFT 10
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_TFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_1_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_RCVR_0_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_RCVR_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SDS0_AFEC_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SDS0_AFEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK  0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: SPARE_02_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_SPARE_02_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: MEMC_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_MEMC_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  1
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  0
+#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_24_CPU_INTR [31:31] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_MASK 0x80000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_SHIFT 31
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_24_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_23_CPU_INTR [30:30] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_MASK 0x40000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_SHIFT 30
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_23_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_22_CPU_INTR [29:29] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_MASK 0x20000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_SHIFT 29
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_22_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_21_CPU_INTR [28:28] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_MASK 0x10000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_SHIFT 28
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_21_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_20_CPU_INTR [27:27] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_MASK 0x08000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_SHIFT 27
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_20_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_19_CPU_INTR [26:26] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_MASK 0x04000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_SHIFT 26
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_19_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_18_CPU_INTR [25:25] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_MASK 0x02000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_SHIFT 25
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_18_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_17_CPU_INTR [24:24] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_MASK 0x01000000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_SHIFT 24
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_17_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: RFM_CPU_INTR [23:23] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_MASK    0x00800000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_SHIFT   23
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_RFM_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_AHCI_CPU_INTR [22:22] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00400000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 22
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SATA_GRB_CPU_INTR [21:21] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00200000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 21
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: AVD0_0_CPU_INTR [20:20] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_MASK 0x00100000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_SHIFT 20
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_AVD0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_16_CPU_INTR [19:19] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_MASK 0x00080000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_SHIFT 19
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_16_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SDIO0_0_CPU_INTR [18:18] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00040000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 18
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [17:17] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00020000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 17
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [16:16] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00010000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 16
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [15:15] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00008000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 15
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [14:14] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00004000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 14
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [13:13] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00002000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 13
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [12:12] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00001000
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 12
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [11:11] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00000800
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 11
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000400
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT   10
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_15_CPU_INTR [09:09] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_MASK 0x00000200
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_SHIFT 9
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_15_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_14_CPU_INTR [08:08] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_MASK 0x00000100
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_SHIFT 8
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_14_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_13_CPU_INTR [07:07] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_MASK 0x00000080
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_SHIFT 7
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_13_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_12_CPU_INTR [06:06] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_MASK 0x00000040
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_SHIFT 6
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_12_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_11_CPU_INTR [05:05] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_MASK 0x00000020
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_SHIFT 5
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_11_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_10_CPU_INTR [04:04] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_MASK 0x00000010
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_SHIFT 4
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_10_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_09_CPU_INTR [03:03] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_MASK 0x00000008
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_SHIFT 3
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_09_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [02:02] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x00000004
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 2
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_OHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [01:01] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x00000002
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 1
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_EHCI_0_CPU_INTR_DEFAULT 0x00000001
+
+/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: USB_BRIDGE_CPU_INTR [00:00] */
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_MASK 0x00000001
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_SHIFT 0
+#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_USB_BRIDGE_CPU_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_intr2.h b/include/linux/brcmstb/7362a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..89a2bf190fbe
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_intr2.h
@@ -0,0 +1,975 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00411000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00411004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00411008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0041100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00411010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00411014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00411018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0041101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00411020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00411024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00411028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0041102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_CPU_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0xf0000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_MASK           0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_SHIFT          19
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST_RD_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK            0x00020000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT           17
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK                0x00010000
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT               16
+#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x0000fffe
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0xf0000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_SHIFT             19
+#define BCHP_HIF_INTR2_PCI_SET_MICH_INST_RD_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK               0x00020000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT              17
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK                   0x00010000
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT                  16
+#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x0000fffe
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_MASK            0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_SHIFT           0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR_BRIDGE_INTR_DEFAULT         0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0xf0000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_MASK            0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_SHIFT           19
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST_RD_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK             0x00020000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT            17
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK                 0x00010000
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT                16
+#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x0000fffe
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_MASK          0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT         0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_MASK      0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_SHIFT     19
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST_RD_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_MASK         0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_SHIFT        19
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST_RD_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_MASK       0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_SHIFT      0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR_BRIDGE_INTR_DEFAULT    0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0xf0000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST_RD_INTR [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_MASK       0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_SHIFT      19
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST_RD_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [15:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x0000fffe
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_MASK     0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_SHIFT    0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR_BRIDGE_INTR_DEFAULT  0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_mspi.h b/include/linux/brcmstb/7362a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..65e2169d7ee3
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_mspi.h
@@ -0,0 +1,1214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_mspi.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
+#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..dabf442f5cfc
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,567 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_hif_spi_intr2.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:56a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00411d00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00411d04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00411d08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00411d0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00411d10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00411d14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00411d18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00411d1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00411d20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00411d24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00411d28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00411d2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h
new file mode 100644
index 000000000000..bff221ea8ebe
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_hif_top_ctrl.h
@@ -0,0 +1,527 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:42 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_TOP_CTRL_H__
+#define BCHP_HIF_TOP_CTRL_H__
+
+/***************************************************************************
+ *HIF_TOP_CTRL - HIF Top Control Registers
+ ***************************************************************************/
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2               0x00412418 /* HIF Power Management Control Register:used to control SDIO_0 (CARD) */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL          0x00412400 /* External IRQ Active Level Control Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0               0x00412404 /* HIF Power Management Control0 Register */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1               0x00412408 /* HIF Power Management Control1 Register */
+#define BCHP_HIF_TOP_CTRL_SCRATCH                0x0041240c /* HIF Scratch Register */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE             0x00412410 /* HIF Decoded Flash Type */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL            0x00412414 /* SPI test port select register */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL               0x0041241c /* HIF HIF_CTRL Register */
+
+/***************************************************************************
+ *PM_CTRL2 - HIF Power Management Control Register:used to control SDIO_0 (CARD)
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved0 [31:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_MASK                  0xff000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved0_SHIFT                 24
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_MASK 0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_SHIFT 22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CARD_DETECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_MASK 0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_SHIFT 20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_WRITE_PROTECT_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_IN_DRIVE_INACTIVE [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_IN_DRIVE_INACTIVE [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_MASK 0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_SHIFT 16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: reserved1 [15:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_MASK                  0x0000f000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_reserved1_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_VOLTAGE_PM_OUT_CTRL [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_LOW    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_HIGH   2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_VOLTAGE_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_POWER_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_MASK     0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_SHIFT    8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_DEFAULT  0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_LOW      1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_HIGH     2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_POWER_PM_OUT_CTRL_Tristate 3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_LED_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_MASK       0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_SHIFT      6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_LED_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_DATA_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_MASK      0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CMD_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CMD_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL2 :: SDIO_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_MASK       0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_SHIFT      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL2_SDIO_CLK_PM_OUT_CTRL_Tristate   3
+
+/***************************************************************************
+ *EXT_IRQ_LEVEL - External IRQ Active Level Control Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: reserved0 [31:15] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_MASK             0xffff8000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_reserved0_SHIFT            15
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_14_level [14:14] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_MASK      0x00004000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_SHIFT     14
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_14_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_13_level [13:13] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_MASK      0x00002000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_SHIFT     13
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_13_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_12_level [12:12] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_MASK      0x00001000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_SHIFT     12
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_12_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_11_level [11:11] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_MASK      0x00000800
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_SHIFT     11
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_11_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_10_level [10:10] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_MASK      0x00000400
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_SHIFT     10
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_10_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_09_level [09:09] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_MASK      0x00000200
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_SHIFT     9
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_09_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_08_level [08:08] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_MASK      0x00000100
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_SHIFT     8
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_08_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_07_level [07:07] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_MASK      0x00000080
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_SHIFT     7
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_07_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_06_level [06:06] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_MASK      0x00000040
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_06_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_05_level [05:05] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_MASK      0x00000020
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_SHIFT     5
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_05_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_04_level [04:04] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_MASK      0x00000010
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_SHIFT     4
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_04_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_03_level [03:03] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_MASK      0x00000008
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_SHIFT     3
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_03_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_02_level [02:02] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_02_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_01_level [01:01] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_MASK      0x00000002
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_SHIFT     1
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_01_level_HIGH      1
+
+/* HIF_TOP_CTRL :: EXT_IRQ_LEVEL :: ext_irq_00_level [00:00] */
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_MASK      0x00000001
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_SHIFT     0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_LOW       0
+#define BCHP_HIF_TOP_CTRL_EXT_IRQ_LEVEL_ext_irq_00_level_HIGH      1
+
+/***************************************************************************
+ *PM_CTRL0 - HIF Power Management Control0 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_PM_IN_DRIVE_INACTIVE [31:30] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_MASK   0xc0000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_SHIFT  30
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_IN_DRIVE_INACTIVE [29:28] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_MASK 0x30000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_SHIFT 28
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_Low 1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_IN_DRIVE_INACTIVE_HIGH 2
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: reserved0 [27:26] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_MASK                  0x0c000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_reserved0_SHIFT                 26
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_DATA_PM_OUT_CTRL [25:24] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_MASK       0x03000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_SHIFT      24
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_DATA_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_ADDR_PM_OUT_CTRL [23:22] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_MASK       0x00c00000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_SHIFT      22
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_ADDR_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: EBI_CTRL_PM_OUT_CTRL [21:20] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_MASK       0x00300000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_SHIFT      20
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_EBI_CTRL_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_DATA_PM_OUT_CTRL [19:18] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_MASK      0x000c0000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_SHIFT     18
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_DATA_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: NAND_CTRL_PM_OUT_CTRL [17:16] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_MASK      0x00030000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_SHIFT     16
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_NAND_CTRL_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS7 [15:14] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_MASK            0x0000c000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_SHIFT           14
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS7_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS6 [13:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_MASK            0x00003000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_SHIFT           12
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS6_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS5 [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_MASK            0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_SHIFT           10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS5_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS4 [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_MASK            0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_SHIFT           8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS4_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS3 [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_MASK            0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_SHIFT           6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS3_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS2 [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_MASK            0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_SHIFT           4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS2_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS1 [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_MASK            0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_SHIFT           2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS1_Tristate        3
+
+/* HIF_TOP_CTRL :: PM_CTRL0 :: PM_OUT_CTRL_CS0 [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_MASK            0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_SHIFT           0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_DEFAULT         0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_FUNCTIONAL      0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_LOW             1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_HIGH            2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL0_PM_OUT_CTRL_CS0_Tristate        3
+
+/***************************************************************************
+ *PM_CTRL1 - HIF Power Management Control1 Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: PM_CTRL1 :: reserved0 [31:12] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_MASK                  0xfffff000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_reserved0_SHIFT                 12
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_PM_IN_DRIVE_INACTIVE [11:10] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_MASK   0x00000c00
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_SHIFT  10
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_DEFAULT 0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_Low    1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_PM_IN_DRIVE_INACTIVE_HIGH   2
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_WPB_PM_OUT_CTRL [09:08] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_MASK        0x00000300
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_SHIFT       8
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_WPB_PM_OUT_CTRL_Tristate    3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_HOLDB_PM_OUT_CTRL [07:06] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_MASK      0x000000c0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_SHIFT     6
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_DEFAULT   0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_LOW       1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_HIGH      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_HOLDB_PM_OUT_CTRL_Tristate  3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MISO_PM_OUT_CTRL [05:04] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_MASK       0x00000030
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_SHIFT      4
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MISO_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_MOSI_PM_OUT_CTRL [03:02] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_MASK       0x0000000c
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_SHIFT      2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_DEFAULT    0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_FUNCTIONAL 0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_LOW        1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_HIGH       2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_MOSI_PM_OUT_CTRL_Tristate   3
+
+/* HIF_TOP_CTRL :: PM_CTRL1 :: SPI_CLK_PM_OUT_CTRL [01:00] */
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_MASK        0x00000003
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_SHIFT       0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_DEFAULT     0x00000000
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_FUNCTIONAL  0
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_LOW         1
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_HIGH        2
+#define BCHP_HIF_TOP_CTRL_PM_CTRL1_SPI_CLK_PM_OUT_CTRL_Tristate    3
+
+/***************************************************************************
+ *SCRATCH - HIF Scratch Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_MASK                 0xffffffff
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_SHIFT                0
+#define BCHP_HIF_TOP_CTRL_SCRATCH_SCRATCH_BIT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *FLASH_TYPE - HIF Decoded Flash Type
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: FLASH_TYPE :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_MASK                0xfffffff8
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_reserved0_SHIFT               3
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: InvalidStrap [02:02] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_MASK             0x00000004
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_SHIFT            2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_InvalidStrap_DEFAULT          0x00000000
+
+/* HIF_TOP_CTRL :: FLASH_TYPE :: FLASH_TYPE [01:00] */
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_MASK               0x00000003
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SHIFT              0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_ParallelNOR        0
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_Nand               1
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_SerialNOR          2
+#define BCHP_HIF_TOP_CTRL_FLASH_TYPE_FLASH_TYPE_eMMC               3
+
+/***************************************************************************
+ *SPI_DBG_SEL - SPI test port select register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: reserved0 [31:03] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_MASK               0xfffffff8
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_reserved0_SHIFT              3
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: DISABLE_MSPI_FLUSH [02:02] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_MASK      0x00000004
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_SHIFT     2
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_DISABLE_MSPI_FLUSH_DEFAULT   0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_RBUS_TIMER_EN [01:01] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_MASK       0x00000002
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_SHIFT      1
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_RBUS_TIMER_EN_DEFAULT    0x00000000
+
+/* HIF_TOP_CTRL :: SPI_DBG_SEL :: SPI_TP_SEL [00:00] */
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_MASK              0x00000001
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_SHIFT             0
+#define BCHP_HIF_TOP_CTRL_SPI_DBG_SEL_SPI_TP_SEL_DEFAULT           0x00000000
+
+/***************************************************************************
+ *HIF_CTRL - HIF HIF_CTRL Register
+ ***************************************************************************/
+/* HIF_TOP_CTRL :: HIF_CTRL :: reserved0 [31:01] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_reserved0_SHIFT                 1
+
+/* HIF_TOP_CTRL :: HIF_CTRL :: ENABLE_FULL_USE_OF_EBI [00:00] */
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_MASK     0x00000001
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_SHIFT    0
+#define BCHP_HIF_TOP_CTRL_HIF_CTRL_ENABLE_FULL_USE_OF_EBI_DEFAULT  0x00000000
+
+#endif /* #ifndef BCHP_HIF_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_irq0.h b/include/linux/brcmstb/7362a0/bchp_irq0.h
new file mode 100644
index 000000000000..15148a3a0754
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_irq0.h
@@ -0,0 +1,217 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_irq0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 11:59a pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x00406600 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x00406604 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ0 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ0_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ0_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ0_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ0_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ0_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ0 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ0_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ0_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ0 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ0_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ0 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ0_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ0 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ0_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ0_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ0_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ0_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ0_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ0_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ0 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ0_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ0 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ0_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_irq1.h b/include/linux/brcmstb/7362a0/bchp_irq1.h
new file mode 100644
index 000000000000..ab0551e591a0
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_irq1.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ1_H__
+#define BCHP_IRQ1_H__
+
+/***************************************************************************
+ *IRQ1 - Level 2 PCI Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ1_IRQEN                          0x00406640 /* Interrupt Enable */
+#define BCHP_IRQ1_IRQSTAT                        0x00406644 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ1 :: IRQEN :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQEN_reserved0_MASK                             0xf8000000
+#define BCHP_IRQ1_IRQEN_reserved0_SHIFT                            27
+
+/* IRQ1 :: IRQEN :: iicc_irqen [26:26] */
+#define BCHP_IRQ1_IRQEN_iicc_irqen_MASK                            0x04000000
+#define BCHP_IRQ1_IRQEN_iicc_irqen_SHIFT                           26
+#define BCHP_IRQ1_IRQEN_iicc_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iicb_irqen [25:25] */
+#define BCHP_IRQ1_IRQEN_iicb_irqen_MASK                            0x02000000
+#define BCHP_IRQ1_IRQEN_iicb_irqen_SHIFT                           25
+#define BCHP_IRQ1_IRQEN_iicb_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: iica_irqen [24:24] */
+#define BCHP_IRQ1_IRQEN_iica_irqen_MASK                            0x01000000
+#define BCHP_IRQ1_IRQEN_iica_irqen_SHIFT                           24
+#define BCHP_IRQ1_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ1 :: IRQEN :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQEN_reserved1_MASK                             0x00f80000
+#define BCHP_IRQ1_IRQEN_reserved1_SHIFT                            19
+
+/* IRQ1 :: IRQEN :: uartc_irqen [18:18] */
+#define BCHP_IRQ1_IRQEN_uartc_irqen_MASK                           0x00040000
+#define BCHP_IRQ1_IRQEN_uartc_irqen_SHIFT                          18
+#define BCHP_IRQ1_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uartb_irqen [17:17] */
+#define BCHP_IRQ1_IRQEN_uartb_irqen_MASK                           0x00020000
+#define BCHP_IRQ1_IRQEN_uartb_irqen_SHIFT                          17
+#define BCHP_IRQ1_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: uarta_irqen [16:16] */
+#define BCHP_IRQ1_IRQEN_uarta_irqen_MASK                           0x00010000
+#define BCHP_IRQ1_IRQEN_uarta_irqen_SHIFT                          16
+#define BCHP_IRQ1_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQEN :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQEN_reserved2_MASK                             0x0000fc00
+#define BCHP_IRQ1_IRQEN_reserved2_SHIFT                            10
+
+/* IRQ1 :: IRQEN :: uc_irqen [09:09] */
+#define BCHP_IRQ1_IRQEN_uc_irqen_MASK                              0x00000200
+#define BCHP_IRQ1_IRQEN_uc_irqen_SHIFT                             9
+#define BCHP_IRQ1_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQEN_reserved3_MASK                             0x00000180
+#define BCHP_IRQ1_IRQEN_reserved3_SHIFT                            7
+
+/* IRQ1 :: IRQEN :: gio_irqen [06:06] */
+#define BCHP_IRQ1_IRQEN_gio_irqen_MASK                             0x00000040
+#define BCHP_IRQ1_IRQEN_gio_irqen_SHIFT                            6
+#define BCHP_IRQ1_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQEN_reserved4_MASK                             0x00000020
+#define BCHP_IRQ1_IRQEN_reserved4_SHIFT                            5
+
+/* IRQ1 :: IRQEN :: ua_irqen [04:04] */
+#define BCHP_IRQ1_IRQEN_ua_irqen_MASK                              0x00000010
+#define BCHP_IRQ1_IRQEN_ua_irqen_SHIFT                             4
+#define BCHP_IRQ1_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: ub_irqen [03:03] */
+#define BCHP_IRQ1_IRQEN_ub_irqen_MASK                              0x00000008
+#define BCHP_IRQ1_IRQEN_ub_irqen_SHIFT                             3
+#define BCHP_IRQ1_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQEN :: irb_irqen [02:02] */
+#define BCHP_IRQ1_IRQEN_irb_irqen_MASK                             0x00000004
+#define BCHP_IRQ1_IRQEN_irb_irqen_SHIFT                            2
+#define BCHP_IRQ1_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQEN :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQEN_reserved5_MASK                             0x00000003
+#define BCHP_IRQ1_IRQEN_reserved5_SHIFT                            0
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ1 :: IRQSTAT :: reserved0 [31:27] */
+#define BCHP_IRQ1_IRQSTAT_reserved0_MASK                           0xf8000000
+#define BCHP_IRQ1_IRQSTAT_reserved0_SHIFT                          27
+
+/* IRQ1 :: IRQSTAT :: iiccirq [26:26] */
+#define BCHP_IRQ1_IRQSTAT_iiccirq_MASK                             0x04000000
+#define BCHP_IRQ1_IRQSTAT_iiccirq_SHIFT                            26
+#define BCHP_IRQ1_IRQSTAT_iiccirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicbirq [25:25] */
+#define BCHP_IRQ1_IRQSTAT_iicbirq_MASK                             0x02000000
+#define BCHP_IRQ1_IRQSTAT_iicbirq_SHIFT                            25
+#define BCHP_IRQ1_IRQSTAT_iicbirq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: iicairq [24:24] */
+#define BCHP_IRQ1_IRQSTAT_iicairq_MASK                             0x01000000
+#define BCHP_IRQ1_IRQSTAT_iicairq_SHIFT                            24
+#define BCHP_IRQ1_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved1 [23:19] */
+#define BCHP_IRQ1_IRQSTAT_reserved1_MASK                           0x00f80000
+#define BCHP_IRQ1_IRQSTAT_reserved1_SHIFT                          19
+
+/* IRQ1 :: IRQSTAT :: uartc_irq [18:18] */
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_MASK                           0x00040000
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_SHIFT                          18
+#define BCHP_IRQ1_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uartb_irq [17:17] */
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_MASK                           0x00020000
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_SHIFT                          17
+#define BCHP_IRQ1_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: uarta_irq [16:16] */
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_MASK                           0x00010000
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_SHIFT                          16
+#define BCHP_IRQ1_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved2 [15:10] */
+#define BCHP_IRQ1_IRQSTAT_reserved2_MASK                           0x0000fc00
+#define BCHP_IRQ1_IRQSTAT_reserved2_SHIFT                          10
+
+/* IRQ1 :: IRQSTAT :: ucirq [09:09] */
+#define BCHP_IRQ1_IRQSTAT_ucirq_MASK                               0x00000200
+#define BCHP_IRQ1_IRQSTAT_ucirq_SHIFT                              9
+#define BCHP_IRQ1_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved3 [08:07] */
+#define BCHP_IRQ1_IRQSTAT_reserved3_MASK                           0x00000180
+#define BCHP_IRQ1_IRQSTAT_reserved3_SHIFT                          7
+
+/* IRQ1 :: IRQSTAT :: gioirq [06:06] */
+#define BCHP_IRQ1_IRQSTAT_gioirq_MASK                              0x00000040
+#define BCHP_IRQ1_IRQSTAT_gioirq_SHIFT                             6
+#define BCHP_IRQ1_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved4 [05:05] */
+#define BCHP_IRQ1_IRQSTAT_reserved4_MASK                           0x00000020
+#define BCHP_IRQ1_IRQSTAT_reserved4_SHIFT                          5
+
+/* IRQ1 :: IRQSTAT :: uairq [04:04] */
+#define BCHP_IRQ1_IRQSTAT_uairq_MASK                               0x00000010
+#define BCHP_IRQ1_IRQSTAT_uairq_SHIFT                              4
+#define BCHP_IRQ1_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: ubirq [03:03] */
+#define BCHP_IRQ1_IRQSTAT_ubirq_MASK                               0x00000008
+#define BCHP_IRQ1_IRQSTAT_ubirq_SHIFT                              3
+#define BCHP_IRQ1_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ1 :: IRQSTAT :: irbirq [02:02] */
+#define BCHP_IRQ1_IRQSTAT_irbirq_MASK                              0x00000004
+#define BCHP_IRQ1_IRQSTAT_irbirq_SHIFT                             2
+#define BCHP_IRQ1_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ1 :: IRQSTAT :: reserved5 [01:00] */
+#define BCHP_IRQ1_IRQSTAT_reserved5_MASK                           0x00000003
+#define BCHP_IRQ1_IRQSTAT_reserved5_SHIFT                          0
+
+#endif /* #ifndef BCHP_IRQ1_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h b/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h
new file mode 100644
index 000000000000..8c5d18b68bbc
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_mem_dma_0.h
@@ -0,0 +1,157 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_mem_dma_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:04p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEM_DMA_0_H__
+#define BCHP_MEM_DMA_0_H__
+
+/***************************************************************************
+ *MEM_DMA_0 - MEM_DMA_0 Registers
+ ***************************************************************************/
+#define BCHP_MEM_DMA_0_REVISION                  0x00374200 /* MEM_DMA REVISION */
+#define BCHP_MEM_DMA_0_FIRST_DESC                0x00374204 /* MEM_DMA First Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CTRL                      0x00374208 /* MEM_DMA Control Register */
+#define BCHP_MEM_DMA_0_WAKE_CTRL                 0x0037420c /* MEM_DMA Wake Control Register */
+#define BCHP_MEM_DMA_0_STATUS                    0x00374214 /* MEM_DMA Status Register */
+#define BCHP_MEM_DMA_0_CUR_DESC                  0x00374218 /* MEM_DMA Current Descriptor Address Register */
+#define BCHP_MEM_DMA_0_CUR_BYTE                  0x0037421c /* MEM_DMA Current Byte Count Register */
+#define BCHP_MEM_DMA_0_SCRATCH                   0x00374224 /* MEM_DMA Scratch Register */
+
+/***************************************************************************
+ *REVISION - MEM_DMA REVISION
+ ***************************************************************************/
+/* MEM_DMA_0 :: REVISION :: reserved0 [31:16] */
+#define BCHP_MEM_DMA_0_REVISION_reserved0_MASK                     0xffff0000
+#define BCHP_MEM_DMA_0_REVISION_reserved0_SHIFT                    16
+
+/* MEM_DMA_0 :: REVISION :: MAJOR [15:08] */
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_MASK                         0x0000ff00
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_SHIFT                        8
+#define BCHP_MEM_DMA_0_REVISION_MAJOR_DEFAULT                      0x00000002
+
+/* MEM_DMA_0 :: REVISION :: MINOR [07:00] */
+#define BCHP_MEM_DMA_0_REVISION_MINOR_MASK                         0x000000ff
+#define BCHP_MEM_DMA_0_REVISION_MINOR_SHIFT                        0
+#define BCHP_MEM_DMA_0_REVISION_MINOR_DEFAULT                      0x0000000a
+
+/***************************************************************************
+ *FIRST_DESC - MEM_DMA First Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: FIRST_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_MASK                        0xffffffff
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_SHIFT                       0
+#define BCHP_MEM_DMA_0_FIRST_DESC_ADDR_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CTRL - MEM_DMA Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CTRL :: reserved0 [31:01] */
+#define BCHP_MEM_DMA_0_CTRL_reserved0_MASK                         0xfffffffe
+#define BCHP_MEM_DMA_0_CTRL_reserved0_SHIFT                        1
+
+/* MEM_DMA_0 :: CTRL :: RUN [00:00] */
+#define BCHP_MEM_DMA_0_CTRL_RUN_MASK                               0x00000001
+#define BCHP_MEM_DMA_0_CTRL_RUN_SHIFT                              0
+#define BCHP_MEM_DMA_0_CTRL_RUN_DEFAULT                            0x00000000
+
+/***************************************************************************
+ *WAKE_CTRL - MEM_DMA Wake Control Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: WAKE_CTRL :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_MASK                    0xfffffffc
+#define BCHP_MEM_DMA_0_WAKE_CTRL_reserved0_SHIFT                   2
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE_MODE [01:01] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_MASK                    0x00000002
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_SHIFT                   1
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MODE_DEFAULT                 0x00000000
+
+/* MEM_DMA_0 :: WAKE_CTRL :: WAKE [00:00] */
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_MASK                         0x00000001
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_SHIFT                        0
+#define BCHP_MEM_DMA_0_WAKE_CTRL_WAKE_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *STATUS - MEM_DMA Status Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: STATUS :: reserved0 [31:02] */
+#define BCHP_MEM_DMA_0_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_MEM_DMA_0_STATUS_reserved0_SHIFT                      2
+
+/* MEM_DMA_0 :: STATUS :: DMA_STATUS [01:00] */
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_MASK                      0x00000003
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_SHIFT                     0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_DEFAULT                   0x00000000
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Idle                      0
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Busy                      1
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Sleep                     2
+#define BCHP_MEM_DMA_0_STATUS_DMA_STATUS_Reserved                  3
+
+/***************************************************************************
+ *CUR_DESC - MEM_DMA Current Descriptor Address Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_DESC :: ADDR [31:00] */
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_MASK                          0xffffffff
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_SHIFT                         0
+#define BCHP_MEM_DMA_0_CUR_DESC_ADDR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *CUR_BYTE - MEM_DMA Current Byte Count Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: CUR_BYTE :: reserved0 [31:25] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_MASK                     0xfe000000
+#define BCHP_MEM_DMA_0_CUR_BYTE_reserved0_SHIFT                    25
+
+/* MEM_DMA_0 :: CUR_BYTE :: COUNT [24:00] */
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_MASK                         0x01ffffff
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_SHIFT                        0
+#define BCHP_MEM_DMA_0_CUR_BYTE_COUNT_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *SCRATCH - MEM_DMA Scratch Register
+ ***************************************************************************/
+/* MEM_DMA_0 :: SCRATCH :: SCRATCH_BIT [31:00] */
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_MASK                    0xffffffff
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_SHIFT                   0
+#define BCHP_MEM_DMA_0_SCRATCH_SCRATCH_BIT_DEFAULT                 0x00000000
+
+#endif /* #ifndef BCHP_MEM_DMA_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h b/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h
new file mode 100644
index 000000000000..6c9890dc7dc3
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_memc_ddr_0.h
@@ -0,0 +1,2665 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:25:00 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_memc_ddr_0.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:05p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MEMC_DDR_0_H__
+#define BCHP_MEMC_DDR_0_H__
+
+/***************************************************************************
+ *MEMC_DDR_0 - Memory Controller Sequencer (DDR Param/Control) Registers 0
+ ***************************************************************************/
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG            0x003b2000 /* Memory Controller Mode-Configuration Register. */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL          0x003b2004 /* Dram iniitialization control */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS         0x003b2008 /* Dram iniitialization status */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0              0x003b200c /* Dram Mode0 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1              0x003b2010 /* Dram Mode1 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2              0x003b2014 /* Dram Mode2 register */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3              0x003b2018 /* Dram Mode3 register */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG               0x003b201c /* Precharge power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG              0x003b2020 /* Self-refresh power down mode configuration register */
+#define BCHP_MEMC_DDR_0_SSPD_CMD                 0x003b2024 /* Software standby power down mode */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS        0x003b2028 /* Power down status */
+#define BCHP_MEMC_DDR_0_WARM_BOOT                0x003b202c /* Warm boot control registers */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0            0x003b2030 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1            0x003b2034 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2            0x003b2038 /* Read to Write & write to read timing register */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3            0x003b203c /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4            0x003b2040 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5            0x003b2044 /* DDR-SDRAM Timing Register. */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ         0x003b2048 /* Memory Controller Sequencer Enable */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT        0x003b204c /* Memory Controller , state machine timeout register. */
+#define BCHP_MEMC_DDR_0_BANK_STATUS              0x003b2050 /* Memory Controller, Bank Status Register. */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY           0x003b2054 /* Memory Controller, Tester Latency Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0               0x003b2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1               0x003b205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2               0x003b2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3               0x003b2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD   0x003b2068 /* Memory Controller, DDR3 DRAM reset Register. */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL             0x003b206c /* Statistics Control register */
+#define BCHP_MEMC_DDR_0_STAT_TIMER               0x003b2070 /* Statistics Timer */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP            0x003b2074 /* DRAM Idle_NOP Cycle Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP        0x003b2078 /* Maximum DRAM idle_NOP cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL             0x003b207c /* CAS Count Register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL         0x003b2080 /* Maximum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL         0x003b2084 /* DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x003b2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL      0x003b208c /* Number of overall system memory read transactions. */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL     0x003b2090 /* Number of overall system memory write transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL       0x003b2094 /* Maximum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL       0x003b2098 /* Minimum Number of Overall System memory transactions. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS  0x003b209c /* Service CAS Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x003b20a0 /* Maximum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x003b20a4 /* Minimum service CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003b20a8 /* Service Intra DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x003b20ac /* Service Post DRAM Penalty Cycle Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003b20b0 /* Maximum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003b20b4 /* Minimum service cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x003b20b8 /* Service Read Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003b20bc /* Service Write Transaction Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x003b20c0 /* Maximum service Transaction count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x003b20c4 /* Minimum service cycle Transaction register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x003b20c8 /* Service Latency Count register. */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003b20cc /* Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003b20d0 /* Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003b20d4 /* Absolute Minimum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003b20d8 /* Absolute Maximum Service Latency count register. */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH             0x003b20dc /* Total number of refreshes issuedr. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0        0x003b20e0 /* CAS cycle count register for client 0. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1        0x003b20e4 /* CAS cycle count register for client 1. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2        0x003b20e8 /* CAS cycle count register for client 2. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3        0x003b20ec /* CAS cycle count register for client 3. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4        0x003b20f0 /* CAS cycle count register for client 4. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5        0x003b20f4 /* CAS cycle count register for client 5. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6        0x003b20f8 /* CAS cycle count register for client 6. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7        0x003b20fc /* CAS cycle count register for client 7. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8        0x003b2100 /* CAS cycle count register for client 8. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9        0x003b2104 /* CAS cycle count register for client 9. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10       0x003b2108 /* CAS cycle count register for client 10. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11       0x003b210c /* CAS cycle count register for client 11. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12       0x003b2110 /* CAS cycle count register for client 12. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13       0x003b2114 /* CAS cycle count register for client 13. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14       0x003b2118 /* CAS cycle count register for client 14. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15       0x003b211c /* CAS cycle count register for client 15. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16       0x003b2120 /* CAS cycle count register for client 16. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17       0x003b2124 /* CAS cycle count register for client 17. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18       0x003b2128 /* CAS cycle count register for client 18. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19       0x003b212c /* CAS cycle count register for client 19. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20       0x003b2130 /* CAS cycle count register for client 20. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21       0x003b2134 /* CAS cycle count register for client 21. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22       0x003b2138 /* CAS cycle count register for client 22. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23       0x003b213c /* CAS cycle count register for client 23. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24       0x003b2140 /* CAS cycle count register for client 24. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25       0x003b2144 /* CAS cycle count register for client 25. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26       0x003b2148 /* CAS cycle count register for client 26. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27       0x003b214c /* CAS cycle count register for client 27. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28       0x003b2150 /* CAS cycle count register for client 28. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29       0x003b2154 /* CAS cycle count register for client 29. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30       0x003b2158 /* CAS cycle count register for client 30. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31       0x003b215c /* CAS cycle count register for client 31. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32       0x003b2160 /* CAS cycle count register for client 32. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33       0x003b2164 /* CAS cycle count register for client 33. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34       0x003b2168 /* CAS cycle count register for client 34. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35       0x003b216c /* CAS cycle count register for client 35. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36       0x003b2170 /* CAS cycle count register for client 36. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37       0x003b2174 /* CAS cycle count register for client 37. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38       0x003b2178 /* CAS cycle count register for client 38. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39       0x003b217c /* CAS cycle count register for client 39. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40       0x003b2180 /* CAS cycle count register for client 40. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41       0x003b2184 /* CAS cycle count register for client 41. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42       0x003b2188 /* CAS cycle count register for client 42. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43       0x003b218c /* CAS cycle count register for client 43. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44       0x003b2190 /* CAS cycle count register for client 44. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45       0x003b2194 /* CAS cycle count register for client 45. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46       0x003b2198 /* CAS cycle count register for client 46. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47       0x003b219c /* CAS cycle count register for client 47. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48       0x003b21a0 /* CAS cycle count register for client 48. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49       0x003b21a4 /* CAS cycle count register for client 49. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50       0x003b21a8 /* CAS cycle count register for client 50. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51       0x003b21ac /* CAS cycle count register for client 51. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52       0x003b21b0 /* CAS cycle count register for client 52. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53       0x003b21b4 /* CAS cycle count register for client 53. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54       0x003b21b8 /* CAS cycle count register for client 54. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55       0x003b21bc /* CAS cycle count register for client 55. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56       0x003b21c0 /* CAS cycle count register for client 56. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57       0x003b21c4 /* CAS cycle count register for client 57. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58       0x003b21c8 /* CAS cycle count register for client 58. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59       0x003b21cc /* CAS cycle count register for client 59. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60       0x003b21d0 /* CAS cycle count register for client 60. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61       0x003b21d4 /* CAS cycle count register for client 61. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62       0x003b21d8 /* CAS cycle count register for client 62. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63       0x003b21dc /* CAS cycle count register for client 63. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64       0x003b21e0 /* CAS cycle count register for client 64. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65       0x003b21e4 /* CAS cycle count register for client 65. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66       0x003b21e8 /* CAS cycle count register for client 66. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67       0x003b21ec /* CAS cycle count register for client 67. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68       0x003b21f0 /* CAS cycle count register for client 68. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69       0x003b21f4 /* CAS cycle count register for client 69. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70       0x003b21f8 /* CAS cycle count register for client 70. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71       0x003b21fc /* CAS cycle count register for client 71. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72       0x003b2200 /* CAS cycle count register for client 72. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73       0x003b2204 /* CAS cycle count register for client 73. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74       0x003b2208 /* CAS cycle count register for client 74. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75       0x003b220c /* CAS cycle count register for client 75. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76       0x003b2210 /* CAS cycle count register for client 76. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77       0x003b2214 /* CAS cycle count register for client 77. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78       0x003b2218 /* CAS cycle count register for client 78. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79       0x003b221c /* CAS cycle count register for client 79. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80       0x003b2220 /* CAS cycle count register for client 80. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81       0x003b2224 /* CAS cycle count register for client 81. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82       0x003b2228 /* CAS cycle count register for client 82. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83       0x003b222c /* CAS cycle count register for client 83. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84       0x003b2230 /* CAS cycle count register for client 84. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85       0x003b2234 /* CAS cycle count register for client 85. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86       0x003b2238 /* CAS cycle count register for client 86. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87       0x003b223c /* CAS cycle count register for client 87. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88       0x003b2240 /* CAS cycle count register for client 88. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89       0x003b2244 /* CAS cycle count register for client 89. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90       0x003b2248 /* CAS cycle count register for client 90. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91       0x003b224c /* CAS cycle count register for client 91. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92       0x003b2250 /* CAS cycle count register for client 92. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93       0x003b2254 /* CAS cycle count register for client 93. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94       0x003b2258 /* CAS cycle count register for client 94. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95       0x003b225c /* CAS cycle count register for client 95. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96       0x003b2260 /* CAS cycle count register for client 96. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97       0x003b2264 /* CAS cycle count register for client 97. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98       0x003b2268 /* CAS cycle count register for client 98. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99       0x003b226c /* CAS cycle count register for client 99. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100      0x003b2270 /* CAS cycle count register for client 100. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101      0x003b2274 /* CAS cycle count register for client 101. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102      0x003b2278 /* CAS cycle count register for client 102. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103      0x003b227c /* CAS cycle count register for client 103. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104      0x003b2280 /* CAS cycle count register for client 104. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105      0x003b2284 /* CAS cycle count register for client 105. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106      0x003b2288 /* CAS cycle count register for client 106. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107      0x003b228c /* CAS cycle count register for client 107. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108      0x003b2290 /* CAS cycle count register for client 108. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109      0x003b2294 /* CAS cycle count register for client 109. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110      0x003b2298 /* CAS cycle count register for client 110. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111      0x003b229c /* CAS cycle count register for client 111. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112      0x003b22a0 /* CAS cycle count register for client 112. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113      0x003b22a4 /* CAS cycle count register for client 113. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114      0x003b22a8 /* CAS cycle count register for client 114. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115      0x003b22ac /* CAS cycle count register for client 115. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116      0x003b22b0 /* CAS cycle count register for client 116. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117      0x003b22b4 /* CAS cycle count register for client 117. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118      0x003b22b8 /* CAS cycle count register for client 118. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119      0x003b22bc /* CAS cycle count register for client 119. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120      0x003b22c0 /* CAS cycle count register for client 120. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121      0x003b22c4 /* CAS cycle count register for client 121. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122      0x003b22c8 /* CAS cycle count register for client 122. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123      0x003b22cc /* CAS cycle count register for client 123. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124      0x003b22d0 /* CAS cycle count register for client 124. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125      0x003b22d4 /* CAS cycle count register for client 125. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126      0x003b22d8 /* CAS cycle count register for client 126. */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127      0x003b22dc /* CAS cycle count register for client 127. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL         0x003b22e0 /* Minimum DRAM CAS cycle count register. */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x003b22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL 0x003b22e8 /* MEMSYS Auto Init Control. */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS  0x003b22ec /* MEMSYS Auto Init Status. */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003b22f0 /* PHY VDL calibrate override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003b22f4 /* SHIM PLL pndiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003b22f8 /* SHIM PLL mdiv override from memc auto init. */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY          0x003b22fc /* Dynamic VDL shmoo command delay. */
+
+/***************************************************************************
+ *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT              3
+
+/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
+#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          0x00000003
+
+/***************************************************************************
+ *DRAM_INIT_CNTRL - Dram iniitialization control
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT            3
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1
+
+/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0x00000000
+
+/***************************************************************************
+ *DRAM_INIT_STATUS - Dram iniitialization status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
+#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_0 - Dram Mode0 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_WR_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_CL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BT_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR2_BL_DEFAULT                0x00000002
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT                  9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            0x00000004
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_1 - Dram Mode1 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_RDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DQSB_DISABLE              1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_AL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE              0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT                  3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1
+
+/***************************************************************************
+ *DRAM_MODE_2 - Dram Mode2 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK                  0x0000e000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT                 13
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0x00000000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR2_PASR_DEFAULT              0x00000000
+
+/* union - case DDR3 [12:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT               0x00000001
+
+/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT                0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DRAM_MODE_3 - Dram Mode3 register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK                 0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT                16
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:03] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT                 3
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT               0x00000000
+
+/* union - case DDR2 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0x00000000
+
+/* union - case DDR3 [02:00] */
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT               0x00000000
+
+/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
+#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0x00000000
+
+/***************************************************************************
+ *PPD_CONFIG - Precharge power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:13] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK                  0xffffe000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT                 13
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK                     0x00001000
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT                    12
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT                  0x00000000
+
+/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SRPD_CONFIG - Self-refresh power down mode configuration register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT                17
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT                  16
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT                0x00000000
+
+/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SSPD_CMD - Software standby power down mode
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK                    0xfffffffe
+#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT                   1
+
+/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK                         0x00000001
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT                        0
+#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *POWER_DOWN_STATUS - Power down status
+ ***************************************************************************/
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT          3
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT               2
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT               1
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT             0x00000000
+
+/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT                0
+#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT              0x00000000
+
+/***************************************************************************
+ *WARM_BOOT - Warm boot control registers
+ ***************************************************************************/
+/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK                   0xfffffffe
+#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT                  1
+
+/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT             0x00000006
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT             0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT                8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT              0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT             0x00000014
+
+/***************************************************************************
+ *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT             0x0000001b
+
+/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT             0x00000004
+
+/***************************************************************************
+ *DRAM_TIMING_2 - Read to Write & write to read timing register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: reserved0 [31:16] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_MASK               0xffff0000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_reserved0_SHIFT              16
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            0x0000000e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            0x00000009
+
+/***************************************************************************
+ *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: reserved0 [31:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_MASK               0xff000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_reserved0_SHIFT              24
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    0x0000005e
+
+/* MEMC_DDR_0 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  0x00000008
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      0x0000000c
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        0x00000058
+
+/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        0x00000200
+
+/***************************************************************************
+ *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:29] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK               0xe0000000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT              29
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   0x00000105
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        0x00000003
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      0x0000000d
+
+/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
+#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   0x00000200
+
+/***************************************************************************
+ *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_reserved0_SHIFT           1
+
+/* MEMC_DDR_0 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
+#define BCHP_MEMC_DDR_0_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0x00000000
+
+/***************************************************************************
+ *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0x00000000
+
+/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            0x0000ffff
+
+/***************************************************************************
+ *BANK_STATUS - Memory Controller, Bank Status Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:08] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT                8
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK7_STATUS [07:07] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_SHIFT             7
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK7_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK6_STATUS [06:06] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_SHIFT             6
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK6_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK5_STATUS [05:05] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_SHIFT             5
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK5_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK4_STATUS [04:04] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_SHIFT             4
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK4_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK3_STATUS [03:03] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_SHIFT             3
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK3_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK2_STATUS [02:02] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_SHIFT             2
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK2_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK1_STATUS [01:01] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_SHIFT             1
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK1_STATUS_DEFAULT           0x00000001
+
+/* MEMC_DDR_0 :: BANK_STATUS :: BANK0_STATUS [00:00] */
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_SHIFT             0
+#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK0_STATUS_DEFAULT           0x00000001
+
+/***************************************************************************
+ *TESTER_LATENCY - Memory Controller, Tester Latency Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:07] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK              0xffffff80
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT             7
+
+/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
+#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE0_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE1_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE2_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved0 [31:31] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_MASK                  0x80000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved0_SHIFT                 31
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_7_SEL_DEFAULT                0x00000007
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved1 [27:27] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_MASK                  0x08000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved1_SHIFT                 27
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_6_SEL_DEFAULT                0x00000006
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved2 [23:23] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_MASK                  0x00800000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved2_SHIFT                 23
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_5_SEL_DEFAULT                0x00000005
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved3 [19:19] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_MASK                  0x00080000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved3_SHIFT                 19
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_4_SEL_DEFAULT                0x00000004
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved4 [15:15] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_MASK                  0x00008000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved4_SHIFT                 15
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_3_SEL_DEFAULT                0x00000003
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved5 [11:11] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_MASK                  0x00000800
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved5_SHIFT                 11
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_2_SEL_DEFAULT                0x00000002
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved6 [07:07] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_MASK                  0x00000080
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved6_SHIFT                 7
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_1_SEL_DEFAULT                0x00000001
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: reserved7 [03:03] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_MASK                  0x00000008
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_reserved7_SHIFT                 3
+
+/* MEMC_DDR_0 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
+#define BCHP_MEMC_DDR_0_DTPM_BYTE3_DT_0_SEL_DEFAULT                0x00000000
+
+/***************************************************************************
+ *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20
+
+/* MEMC_DDR_0 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
+#define BCHP_MEMC_DDR_0_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 0x0000a8c0
+
+/***************************************************************************
+ *STAT_CONTROL - Statistics Control register
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:09] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK                0xfffffe00
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT               9
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT            8
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT          0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT             7
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT           0x00000000
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE            1
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE           0
+
+/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [06:00] */
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_TIMER - Statistics Timer
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK                      0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT                     0
+#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT                  0
+#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT                0x00000000
+
+/***************************************************************************
+ *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_ALL - CAS Count Register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
+#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
+#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
+
+/***************************************************************************
+ *STAT_REFRESH - Total number of refreshes issuedr.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK                    0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT                   0
+#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
+#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
+#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT             0xffffffff
+
+/***************************************************************************
+ *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
+ ***************************************************************************/
+/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
+#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    0xffffffff
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0x00000000
+
+/* MEMC_DDR_0 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
+#define BCHP_MEMC_DDR_0_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 0x10000000
+
+/***************************************************************************
+ *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 0x23b00000
+
+/***************************************************************************
+ *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
+#define BCHP_MEMC_DDR_0_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 0x00001003
+
+/***************************************************************************
+ *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
+ ***************************************************************************/
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_reserved0_SHIFT            12
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0x00000000
+
+/* MEMC_DDR_0 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
+#define BCHP_MEMC_DDR_0_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0x00000000
+
+#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_misb_bridge.h b/include/linux/brcmstb/7362a0/bchp_misb_bridge.h
new file mode 100644
index 000000000000..1785df3a15c9
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_misb_bridge.h
@@ -0,0 +1,87 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_MISB_BRIDGE_H__
+#define BCHP_MISB_BRIDGE_H__
+
+/***************************************************************************
+ *MISB_BRIDGE - MISB_BRIDGE Registers
+ ***************************************************************************/
+#define BCHP_MISB_BRIDGE_CORE_REV_ID             0x00410400 /* MISB Bridge Revision ID Register. */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET 0x00410404 /* "Exception Vector Offset Address" */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID            0x00410408 /* Processor ID Register. */
+
+/***************************************************************************
+ *CORE_REV_ID - MISB Bridge Revision ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: CORE_REV_ID :: reserved0 [31:16] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_MASK                0xffff0000
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_reserved0_SHIFT               16
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MAJOR [15:08] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_MASK                    0x0000ff00
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_SHIFT                   8
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MAJOR_DEFAULT                 0x00000000
+
+/* MISB_BRIDGE :: CORE_REV_ID :: MINOR [07:00] */
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_MASK                    0x000000ff
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_SHIFT                   0
+#define BCHP_MISB_BRIDGE_CORE_REV_ID_MINOR_DEFAULT                 0x00000001
+
+/***************************************************************************
+ *EXCEPTION_VECTOR_OFFSET - "Exception Vector Offset Address"
+ ***************************************************************************/
+/* MISB_BRIDGE :: EXCEPTION_VECTOR_OFFSET :: ADDRS [31:00] */
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_MASK        0xffffffff
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_SHIFT       0
+#define BCHP_MISB_BRIDGE_EXCEPTION_VECTOR_OFFSET_ADDRS_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PROCESSOR_ID - Processor ID Register.
+ ***************************************************************************/
+/* MISB_BRIDGE :: PROCESSOR_ID :: reserved0 [31:08] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_MASK               0xffffff00
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_reserved0_SHIFT              8
+
+/* MISB_BRIDGE :: PROCESSOR_ID :: ID [07:00] */
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_MASK                      0x000000ff
+#define BCHP_MISB_BRIDGE_PROCESSOR_ID_ID_SHIFT                     0
+
+#endif /* #ifndef BCHP_MISB_BRIDGE_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_nand.h b/include/linux/brcmstb/7362a0/bchp_nand.h
new file mode 100644
index 000000000000..6ad6a8eb1b92
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_nand.h
@@ -0,0 +1,2260 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_nand.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:09p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00412800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00412804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00412808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0041280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00412810 /* Nand Flash Command End Address */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00412814 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x00412818 /* Nand Flash EBI CS Address XOR with 1FC0 Control */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00412820 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00412824 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00412828 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x0041282c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00412830 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00412834 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00412838 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x0041283c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_ACC_CONTROL                    0x00412840 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG                         0x00412848 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1                       0x00412850 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2                       0x00412854 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SEMAPHORE                      0x00412858 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00412860 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00412864 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00412868 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_INTFC_STATUS                   0x0041286c /* Nand Flash Interface Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x00412870 /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00412874 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00412878 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x0041287c /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00412880 /* Read Error Count */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x00412884 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_ONFI_STATUS                    0x00412888 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0041288c /* ONFI Debug Data */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x00412890 /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00412894 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00412898 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x0041289c /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x004128a0 /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x004128a4 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x004128a8 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x004128ac /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x004128b0 /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x004128b4 /* Flash Invalid Data Address */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004128c0 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x004128d0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS1                     0x004128d4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x004128d8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x004128dc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x004128e0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS2                     0x004128e4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x004128e8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x004128ec /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x004128f0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS3                     0x004128f4 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x004128f8 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x004128fc /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x00412900 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_CS4                     0x00412904 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x00412908 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x0041290c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00412930 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00412934 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00412938 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x0041293c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00412940 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00412944 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00412948 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x0041294c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_LL_OP                          0x00412978 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_LL_RDDATA                      0x0041297c /* Nand Flash Low Level Read Data */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
+#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001
+
+/* NAND :: REVISION :: reserved0 [30:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000005
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:29] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xe0000000
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        29
+
+/* NAND :: CMD_START :: OPCODE [28:24] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x1f000000
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           24
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+
+/* NAND :: CMD_START :: reserved1 [23:00] */
+#define BCHP_NAND_CMD_START_reserved1_MASK                         0x00ffffff
+#define BCHP_NAND_CMD_START_reserved1_SHIFT                        0
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   29
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved1 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved1_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS Address XOR with 1FC0 Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_1FC0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_MASK           0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_SHIFT          31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_1FC0_XOR_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_1FC0_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_MASK          0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_SHIFT         7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_1FC0_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_MASK          0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_SHIFT         6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_1FC0_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_MASK          0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_SHIFT         5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_1FC0_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_MASK          0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_SHIFT         4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_1FC0_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_MASK          0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_SHIFT         3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_1FC0_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_MASK          0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_SHIFT         2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_1FC0_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_MASK          0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_SHIFT         1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_1FC0_XOR_DEFAULT       0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_1FC0_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_MASK          0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_1FC0_XOR_SHIFT         0
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *ACC_CONTROL - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_MASK                       0x80000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_SHIFT                      31
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_MASK                       0x40000000
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_SHIFT                      30
+#define BCHP_NAND_ACC_CONTROL_WR_ECC_EN_DEFAULT                    0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ECC_BLK0_EN [29:29] */
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_MASK                  0x20000000
+#define BCHP_NAND_ACC_CONTROL_RD_ECC_BLK0_EN_SHIFT                 29
+
+/* NAND :: ACC_CONTROL :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_SHIFT                  28
+#define BCHP_NAND_ACC_CONTROL_FAST_PGM_RDIN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_MASK                0x08000000
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_SHIFT               27
+#define BCHP_NAND_ACC_CONTROL_RD_ERASED_ECC_EN_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_MASK                 0x04000000
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_SHIFT                26
+#define BCHP_NAND_ACC_CONTROL_PARTIAL_PAGE_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_MASK                   0x02000000
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_SHIFT                  25
+#define BCHP_NAND_ACC_CONTROL_WR_PREEMPT_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_MASK                     0x01000000
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_SHIFT                    24
+#define BCHP_NAND_ACC_CONTROL_PAGE_HIT_EN_DEFAULT                  0x00000001
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL_0 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_MASK                     0x00f00000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_SHIFT                    20
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_0_DEFAULT                  0x0000000f
+
+/* NAND :: ACC_CONTROL :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_MASK                       0x000f0000
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_SHIFT                      16
+#define BCHP_NAND_ACC_CONTROL_ECC_LEVEL_DEFAULT                    0x0000000f
+
+/* NAND :: ACC_CONTROL :: reserved0 [15:15] */
+#define BCHP_NAND_ACC_CONTROL_reserved0_MASK                       0x00008000
+#define BCHP_NAND_ACC_CONTROL_reserved0_SHIFT                      15
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K_0 [14:14] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_MASK                0x00004000
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_SHIFT               14
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_0_DEFAULT             0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE_0 [13:08] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_MASK               0x00003f00
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_SHIFT              8
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_0_DEFAULT            0x00000010
+
+/* NAND :: ACC_CONTROL :: reserved1 [07:07] */
+#define BCHP_NAND_ACC_CONTROL_reserved1_MASK                       0x00000080
+#define BCHP_NAND_ACC_CONTROL_reserved1_SHIFT                      7
+
+/* NAND :: ACC_CONTROL :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_MASK                  0x00000040
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_SHIFT                 6
+#define BCHP_NAND_ACC_CONTROL_SECTOR_SIZE_1K_DEFAULT               0x00000000
+
+/* NAND :: ACC_CONTROL :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_MASK                 0x0000003f
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_SHIFT                0
+#define BCHP_NAND_ACC_CONTROL_SPARE_AREA_SIZE_DEFAULT              0x00000010
+
+/***************************************************************************
+ *CONFIG - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_MASK                          0x80000000
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_SHIFT                         31
+#define BCHP_NAND_CONFIG_CONFIG_LOCK_DEFAULT                       0x00000000
+
+/* NAND :: CONFIG :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_MASK                           0x70000000
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_SHIFT                          28
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_2048KB                 6
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_1024KB                 5
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_512KB                  3
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_128KB                  1
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_16KB                   0
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_8KB                    2
+#define BCHP_NAND_CONFIG_BLOCK_SIZE_BK_SIZE_256KB                  4
+
+/* NAND :: CONFIG :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_MASK                          0x0f000000
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_SHIFT                         24
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4MB                  0
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8MB                  1
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16MB                 2
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32MB                 3
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64MB                 4
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128MB                5
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_256MB                6
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_512MB                7
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_1GB                  8
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_2GB                  9
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_4GB                  10
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_8GB                  11
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_16GB                 12
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_32GB                 13
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_64GB                 14
+#define BCHP_NAND_CONFIG_DEVICE_SIZE_DVC_SIZE_128GB                15
+
+/* NAND :: CONFIG :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_MASK                         0x00800000
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_SHIFT                        23
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_8                  0
+#define BCHP_NAND_CONFIG_DEVICE_WIDTH_DVC_WIDTH_16                 1
+
+/* NAND :: CONFIG :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_reserved0_MASK                            0x00400000
+#define BCHP_NAND_CONFIG_reserved0_SHIFT                           22
+
+/* NAND :: CONFIG :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_PAGE_SIZE_MASK                            0x00300000
+#define BCHP_NAND_CONFIG_PAGE_SIZE_SHIFT                           20
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_512                     0
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_2KB                     1
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_4KB                     2
+#define BCHP_NAND_CONFIG_PAGE_SIZE_PG_SIZE_8KB                     3
+
+/* NAND :: CONFIG :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_reserved1_MASK                            0x00080000
+#define BCHP_NAND_CONFIG_reserved1_SHIFT                           19
+
+/* NAND :: CONFIG :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_MASK                        0x00070000
+#define BCHP_NAND_CONFIG_FUL_ADR_BYTES_SHIFT                       16
+
+/* NAND :: CONFIG :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_reserved2_MASK                            0x00008000
+#define BCHP_NAND_CONFIG_reserved2_SHIFT                           15
+
+/* NAND :: CONFIG :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_MASK                        0x00007000
+#define BCHP_NAND_CONFIG_COL_ADR_BYTES_SHIFT                       12
+
+/* NAND :: CONFIG :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_reserved3_MASK                            0x00000800
+#define BCHP_NAND_CONFIG_reserved3_SHIFT                           11
+
+/* NAND :: CONFIG :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_MASK                        0x00000700
+#define BCHP_NAND_CONFIG_BLK_ADR_BYTES_SHIFT                       8
+
+/* NAND :: CONFIG :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_reserved4_MASK                            0x000000ff
+#define BCHP_NAND_CONFIG_reserved4_SHIFT                           0
+
+/***************************************************************************
+ *TIMING_1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_tWP_MASK                                0xf0000000
+#define BCHP_NAND_TIMING_1_tWP_SHIFT                               28
+#define BCHP_NAND_TIMING_1_tWP_DEFAULT                             0x00000006
+
+/* NAND :: TIMING_1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_tWH_MASK                                0x0f000000
+#define BCHP_NAND_TIMING_1_tWH_SHIFT                               24
+#define BCHP_NAND_TIMING_1_tWH_DEFAULT                             0x00000005
+
+/* NAND :: TIMING_1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_tRP_MASK                                0x00f00000
+#define BCHP_NAND_TIMING_1_tRP_SHIFT                               20
+#define BCHP_NAND_TIMING_1_tRP_DEFAULT                             0x00000007
+
+/* NAND :: TIMING_1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_tREH_MASK                               0x000f0000
+#define BCHP_NAND_TIMING_1_tREH_SHIFT                              16
+#define BCHP_NAND_TIMING_1_tREH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_tCS_MASK                                0x0000f000
+#define BCHP_NAND_TIMING_1_tCS_SHIFT                               12
+#define BCHP_NAND_TIMING_1_tCS_DEFAULT                             0x00000008
+
+/* NAND :: TIMING_1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_tCLH_MASK                               0x00000f00
+#define BCHP_NAND_TIMING_1_tCLH_SHIFT                              8
+#define BCHP_NAND_TIMING_1_tCLH_DEFAULT                            0x00000004
+
+/* NAND :: TIMING_1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_tALH_MASK                               0x000000f0
+#define BCHP_NAND_TIMING_1_tALH_SHIFT                              4
+#define BCHP_NAND_TIMING_1_tALH_DEFAULT                            0x00000005
+
+/* NAND :: TIMING_1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_tADL_MASK                               0x0000000f
+#define BCHP_NAND_TIMING_1_tADL_SHIFT                              0
+#define BCHP_NAND_TIMING_1_tADL_DEFAULT                            0x0000000b
+
+/***************************************************************************
+ *TIMING_2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CLK_SELECT_MASK                         0x80000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_SHIFT                        31
+#define BCHP_NAND_TIMING_2_CLK_SELECT_DEFAULT                      0x00000000
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_108                      0
+#define BCHP_NAND_TIMING_2_CLK_SELECT_CLK_216                      1
+
+/* NAND :: TIMING_2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_reserved0_MASK                          0x7fffe000
+#define BCHP_NAND_TIMING_2_reserved0_SHIFT                         13
+
+/* NAND :: TIMING_2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_tWB_MASK                                0x00001e00
+#define BCHP_NAND_TIMING_2_tWB_SHIFT                               9
+#define BCHP_NAND_TIMING_2_tWB_DEFAULT                             0x0000000f
+
+/* NAND :: TIMING_2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_tWHR_MASK                               0x000001f0
+#define BCHP_NAND_TIMING_2_tWHR_SHIFT                              4
+#define BCHP_NAND_TIMING_2_tWHR_DEFAULT                            0x00000009
+
+/* NAND :: TIMING_2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_tREAD_MASK                              0x0000000f
+#define BCHP_NAND_TIMING_2_tREAD_SHIFT                             0
+#define BCHP_NAND_TIMING_2_tREAD_DEFAULT                           0x00000006
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: reserved0 [26:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x07ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:05] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xffffffe0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              5
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD [04:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_MASK     0x0000001f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_SHIFT    0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_DEFAULT  0x00000001
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: reserved0 [27:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x0fffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS1 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS1_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS2 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS2_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS3 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS3_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  29
+
+/* NAND :: ACC_CONTROL_CS4 :: FAST_PGM_RDIN [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_MASK               0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_SHIFT              28
+#define BCHP_NAND_ACC_CONTROL_CS4_FAST_PGM_RDIN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [23:20] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00f00000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  20
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [19:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x000f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff80
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  7
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [06:06] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000040
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             6
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [05:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000003f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              3
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              1
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               0
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                2
+#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              4
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22
+
+/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
+#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3
+
+/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00412a00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h
new file mode 100644
index 000000000000..8b921ce667d3
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sata_top_ctrl.h
@@ -0,0 +1,164 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_sata_top_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:19p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SATA_TOP_CTRL_H__
+#define BCHP_SATA_TOP_CTRL_H__
+
+/***************************************************************************
+ *SATA_TOP_CTRL - SATA3 MISC Control Registers
+ ***************************************************************************/
+#define BCHP_SATA_TOP_CTRL_Version               0x00180020 /* SATA3 Version Register */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL              0x00180024 /* SATA3 System Bus Access Control Register */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL               0x00180028 /* SATA3 Test Port Control register */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1            0x0018002c /* SATA3 phy interface control 1 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2            0x00180030 /* SATA3 phy interface control 2 */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3            0x00180034 /* SATA3 phy interface control 3 */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT           0x00180038 /* SATA3 TP OUT */
+
+/***************************************************************************
+ *Version - SATA3 Version Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: Version :: reserved0 [31:08] */
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_MASK                  0xffffff00
+#define BCHP_SATA_TOP_CTRL_Version_reserved0_SHIFT                 8
+
+/* SATA_TOP_CTRL :: Version :: major_version [07:04] */
+#define BCHP_SATA_TOP_CTRL_Version_major_version_MASK              0x000000f0
+#define BCHP_SATA_TOP_CTRL_Version_major_version_SHIFT             4
+#define BCHP_SATA_TOP_CTRL_Version_major_version_DEFAULT           0x00000000
+
+/* SATA_TOP_CTRL :: Version :: minor_version [03:00] */
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_MASK              0x0000000f
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_SHIFT             0
+#define BCHP_SATA_TOP_CTRL_Version_minor_version_DEFAULT           0x00000001
+
+/***************************************************************************
+ *BUS_CTRL - SATA3 System Bus Access Control Register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_31_17 [31:17] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_MASK            0xfffe0000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_SHIFT           17
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_31_17_DEFAULT         0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: overide_hwinit_registers [16:16] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_MASK  0x00010000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_SHIFT 16
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_overide_hwinit_registers_DEFAULT 0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: bus_ctrl_15_8 [15:08] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_MASK             0x0000ff00
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_SHIFT            8
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_bus_ctrl_15_8_DEFAULT          0x00000000
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: piodata_endian_ctrl [07:06] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_MASK       0x000000c0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SHIFT      6
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_piodata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadata_endian_ctrl [05:04] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_MASK       0x00000030
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SHIFT      4
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadata_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: dmadesc_endian_ctrl [03:02] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_MASK       0x0000000c
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SHIFT      2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_DEFAULT    0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_SwapEndianess 2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_HalfWordSwap 1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_dmadesc_endian_ctrl_NoSwap     0
+
+/* SATA_TOP_CTRL :: BUS_CTRL :: reg_endian_ctrl [01:00] */
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_MASK           0x00000003
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SHIFT          0
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_DEFAULT        0x00000000
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_SwapEndianess  2
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_HalfWordSwap   1
+#define BCHP_SATA_TOP_CTRL_BUS_CTRL_reg_endian_ctrl_NoSwap         0
+
+/***************************************************************************
+ *TP_CTRL - SATA3 Test Port Control register
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: TP_CTRL :: tp_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_MASK                    0xffffffff
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_SHIFT                   0
+#define BCHP_SATA_TOP_CTRL_TP_CTRL_tp_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_1 - SATA3 phy interface control 1
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_1 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_1_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_2 - SATA3 phy interface control 2
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_2 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_2_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *PHY_CTRL_3 - SATA3 phy interface control 3
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: PHY_CTRL_3 :: phy_ctrl [31:00] */
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_MASK                0xffffffff
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_SHIFT               0
+#define BCHP_SATA_TOP_CTRL_PHY_CTRL_3_phy_ctrl_DEFAULT             0x00000000
+
+/***************************************************************************
+ *SATA_TP_OUT - SATA3 TP OUT
+ ***************************************************************************/
+/* SATA_TOP_CTRL :: SATA_TP_OUT :: TP_OUT [31:00] */
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_MASK                 0xffffffff
+#define BCHP_SATA_TOP_CTRL_SATA_TP_OUT_TP_OUT_SHIFT                0
+
+#endif /* #ifndef BCHP_SATA_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..7ccf567d32d8
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,635 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO_0 (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00410100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00410104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00410108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x0041010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00410110 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00410114 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x00410118 /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x0041011c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x00410120 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00410130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00410134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00410138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0041013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004101fc /* SDIO Scratch Register */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004101f0 /* SDIO VERSION Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DDR_TAP_DELAY [27:24] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_MASK         0x0f000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_SHIFT        24
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DDR_TAP_DELAY_DEFAULT      0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DELAY_CTRL [23:21] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_MASK            0x00e00000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_SHIFT           21
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DELAY_CTRL_DEFAULT         0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_ENA [20:20] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_MASK       0x00100000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_SHIFT      20
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_ENA_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: HREADY_IDLE_PULSE [19:19] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_MASK     0x00080000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_SHIFT    19
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_HREADY_IDLE_PULSE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: DATA_PENDING [18:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_MASK          0x00040000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_SHIFT         18
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_DATA_PENDING_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_MASK              0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_SHIFT             17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WR_FLUSH_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_RD_THRESH [09:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_MASK         0x000003e0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_SHIFT        5
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_RD_THRESH_DEFAULT      0x00000002
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SIZE [04:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_MASK              0x0000001f
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_SHIFT             0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SIZE_DEFAULT           0x00000004
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffe
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 1
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [00:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000001
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: DDR50_SUPPORT [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_SHIFT               31
+#define BCHP_SDIO_0_CFG_CAP_REG0_DDR50_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SD104_SUPPORT [30:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_MASK                0x40000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_SHIFT               30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SD104_SUPPORT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDR50 [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_MASK                        0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_SHIFT                       29
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDR50_DEFAULT                     0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [28:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0x18000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   27
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: ASYNCH_INT_SUPPORT [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_MASK           0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_SHIFT          26
+#define BCHP_SDIO_0_CFG_CAP_REG0_ASYNCH_INT_SUPPORT_DEFAULT        0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 64B_SYS_BUS_SUPPORT [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_MASK          0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_SHIFT         25
+#define BCHP_SDIO_0_CFG_CAP_REG0_64B_SYS_BUS_SUPPORT_DEFAULT       0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: 1_8V_SUPPORT [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_1_8V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_0V_SUPPORT [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_MASK                 0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_SHIFT                23
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_0V_SUPPORT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: 3_3V_SUPPORT [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_MASK                 0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_SHIFT                22
+#define BCHP_SDIO_0_CFG_CAP_REG0_3_3V_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSP_RES_SUPPORT [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_MASK             0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_SHIFT            21
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSP_RES_SUPPORT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA_SUPPORT [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_MASK                 0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_SHIFT                20
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SUPPORT_DEFAULT              0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED_SUPPORT [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_MASK           0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_SHIFT          19
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SUPPORT_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2_SUPPORT [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_MASK                0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_SHIFT               18
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SUPPORT_DEFAULT             0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA_SUPPORT [17:17] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_MASK       0x00020000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_SHIFT      17
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SUPPORT_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BL [16:15] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_MASK                       0x00018000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_SHIFT                      15
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BL_DEFAULT                    0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_FREQ [14:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_MASK                    0x00007f80
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_SHIFT                   7
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_FREQ_DEFAULT                 0x00000032
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_UNIT [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_MASK             0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_SHIFT            6
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_UNIT_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_MASK                 0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_SHIFT                0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_FREQ_DEFAULT              0x00000032
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_REG_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_MASK             0x80000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_SHIFT            31
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_REG_OVERRIDE_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [30:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0x7fe00000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   21
+
+/* SDIO_0_CFG :: CAP_REG1 :: CAP_1_stuff [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_MASK                  0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_SHIFT                 20
+#define BCHP_SDIO_0_CFG_CAP_REG1_CAP_1_stuff_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLK_MODE [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_MASK                 0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_SHIFT                19
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLK_MODE_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    18
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [17:10] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x0003fc00
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    10
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODES [09:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_MASK               0x00000300
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_SHIFT              8
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODES_DEFAULT            0x00000002
+
+/* SDIO_0_CFG :: CAP_REG1 :: USE_TUNING [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_MASK                   0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_SHIFT                  7
+#define BCHP_SDIO_0_CFG_CAP_REG1_USE_TUNING_DEFAULT                0x00000001
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_TIMER [06:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_MASK               0x00000078
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_SHIFT              3
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_TIMER_DEFAULT            0x0000000a
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_D_SUPPORT [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_MASK             0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_SHIFT            2
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_D_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_C_SUPPORT [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_MASK             0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_SHIFT            1
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_C_SUPPORT_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: Driver_A_SUPPORT [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_MASK             0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG1_Driver_A_SUPPORT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET100 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_MASK                     0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_SHIFT                    16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET100_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET50 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_MASK                      0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_SHIFT                     0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET50_DEFAULT                   0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET25 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_MASK                      0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_SHIFT                     16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET25_DEFAULT                   0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET12P5 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_MASK                    0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_SHIFT                   0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET12P5_DEFAULT                 0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000003
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT                0x00000028
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_DEFAULT                   0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:04] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xfffffff0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     4
+
+/* SDIO_0_CFG :: TUNING :: TUNING_CMD_SUCCESS_CNT [03:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_MASK         0x0000000f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_SHIFT        0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_CMD_SUCCESS_CNT_DEFAULT      0x00000008
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: SD_VER [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_MASK                        0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_SHIFT                       24
+#define BCHP_SDIO_0_CFG_VERSION_SD_VER_DEFAULT                     0x00000030
+
+/* SDIO_0_CFG :: VERSION :: MMC_VER [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_MASK                       0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_SHIFT                      16
+#define BCHP_SDIO_0_CFG_VERSION_MMC_VER_DEFAULT                    0x00000044
+
+/* SDIO_0_CFG :: VERSION :: REV [15:08] */
+#define BCHP_SDIO_0_CFG_VERSION_REV_MASK                           0x0000ff00
+#define BCHP_SDIO_0_CFG_VERSION_REV_SHIFT                          8
+#define BCHP_SDIO_0_CFG_VERSION_REV_DEFAULT                        0x000000a9
+
+/* SDIO_0_CFG :: VERSION :: A2S_VER [07:00] */
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_MASK                       0x000000ff
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_SHIFT                      0
+#define BCHP_SDIO_0_CFG_VERSION_A2S_VER_DEFAULT                    0x00000001
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..d4ca962cf360
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,6198 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404164 /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040439c /* UART Router select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x73620000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x73620000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000007
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000007
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_sel [03:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_MASK  0x0000000e
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_sel_DEFAULT 0x00000004
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ob_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ds_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_chip_variant_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_alt_prod_base_rev_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ob_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ob_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ds_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ds_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_isdbt_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_isdbt_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_chip_variant [13:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_MASK 0x00003c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_chip_variant_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_alt_prod_base_rev_enable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_alt_prod_base_rev_enable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xffff8000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   15
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl [14:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_MASK 0x00007ffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_pwrdn [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: ldo_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_ldo_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_3_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_2_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xffc00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   22
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff80
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT            0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SDS0_DSEC_TXEN    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SDS0_DSEC_TXOUT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25         5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43        6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28          3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT           0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SDS0_O_DATA_2     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SDS0_O_DATA_1     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SDS0_O_DATA_0     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SDS0_O_CLK        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53        3
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SDS0_O_VALID      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SDS0_O_SYNC       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SDS0_O_DATA_7     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SDS0_O_DATA_6     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SDS0_O_DATA_5     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SDS0_O_DATA_4     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SDS0_O_DATA_3     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK              0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT             28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SDS0_DEMOD_SYNC   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK              0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT             24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SDS0_DEMOD_DATA   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK              0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT             20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SDS0_DEMOD_CLK    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74        5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK              0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT             16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT           0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_RSVD_MPOD_M_SDI   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK              0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT             12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_RSVD_MPOD_M_SDO   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK              0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT             8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_RSVD_MPOD_SCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71        3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK              0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT             4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT           0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_RSVD_MPOD_SCTL    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SDS0_O_ERROR      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70        4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK              0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT             0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT           0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK          2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69        5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DSEC_VCTL   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SDS0_DEMOD_ERR   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK         3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DSEC_SELVTOP 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SDS0_DEMOD_VALID 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK             0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT            28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT           2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK             0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT            24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0             2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP          1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85       5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_DSEC_SELVTOP 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK             0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT            20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT           3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2         4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI        5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO           7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99       8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK             0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT            16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98       5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK             0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT            12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA        1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK             0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT            8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC          5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96       6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK             0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT            4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB           1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0             3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SDS0_DSEC_TXEN   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94       7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK             0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT            0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT          0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93          0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2         2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC        3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0        4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SDS0_DSEC_TXOUT  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93       7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110     3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL         1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109     7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN    3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1        6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT    5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP         6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30        7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1            2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT      6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19       7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105     8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT          4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK      5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO       5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103     6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA       2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_DSEC_VCTL  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC     5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK       6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102     7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_14 - Pinmux control register 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT     3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111     4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_15 - Pinmux control register 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK            0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7        2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1       3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK            0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6        2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK            0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO      1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK            0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT         0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC       1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123     2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK            0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD       3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK            0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK            0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120     5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK            0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT         0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119        0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24      2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2      3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28       4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119     5
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [13:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x00003c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_08_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_08_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_25_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_25_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_40_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_40_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_55_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_55_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_70_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_70_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_85_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_85_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_101_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_101_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xffc00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       22
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       16
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_117_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_117_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffffffc
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       2
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffe0000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 15
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK    0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT   12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT    11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_dl_sw_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_dl_sw_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_MASK   0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_hot_boot_reset_SHIFT  4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK          0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK   0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT  28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK   0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT  27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK         0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT        16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK          0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT         13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK   0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT  11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK        0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT       29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK       0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK        0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT       13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK       0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT      29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK       0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT      13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK  0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_a_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ftm_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_a_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ftm_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         5
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_a_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ftm_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xffffffe0
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xffffffe0
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_a_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ftm_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffe0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 5
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_a_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_a_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ftm_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ftm_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    27
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     33
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   35
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     51
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 4
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 2
+
+/***************************************************************************
+ *UART_ROUTER_SEL - UART Router select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP  1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xfffff000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               12
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xfffffff8
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             3
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK     0x00000010
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT  0x00000001
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED  0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_timer.h b/include/linux/brcmstb/7362a0/bchp_timer.h
new file mode 100644
index 000000000000..65a3318a6373
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_timer.h
@@ -0,0 +1,327 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_timer.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:32p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_TIMER_H__
+#define BCHP_TIMER_H__
+
+/***************************************************************************
+ *TIMER - Watchdog & Programmable Timers
+ ***************************************************************************/
+#define BCHP_TIMER_TIMER_IS                      0x00406680 /* TIMER INTERRUPT STATUS REGISTER */
+#define BCHP_TIMER_TIMER_IE0                     0x00406684 /* TIMER CPU INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_TIMER0_CTRL                   0x00406688 /* TIMER0 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER1_CTRL                   0x0040668c /* TIMER1 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER2_CTRL                   0x00406690 /* TIMER2 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER3_CTRL                   0x00406694 /* TIMER3 CONTROL REGISTER */
+#define BCHP_TIMER_TIMER0_STAT                   0x00406698 /* TIMER0 STATUS REGISTER */
+#define BCHP_TIMER_TIMER1_STAT                   0x0040669c /* TIMER1 STATUS REGISTER */
+#define BCHP_TIMER_TIMER2_STAT                   0x004066a0 /* TIMER2 STATUS REGISTER */
+#define BCHP_TIMER_TIMER3_STAT                   0x004066a4 /* TIMER3 STATUS REGISTER */
+#define BCHP_TIMER_WDTIMEOUT                     0x004066a8 /* WATCHDOG TIMEOUT REGISTER */
+#define BCHP_TIMER_WDCMD                         0x004066ac /* WATCHDOG COMMAND REGISTER */
+#define BCHP_TIMER_WDCHIPRST_CNT                 0x004066b0 /* WATCHDOG CHIP RESET COUNT REGISTER */
+#define BCHP_TIMER_TIMER_IE1                     0x004066b8 /* TIMER PCI INTERRUPT ENABLE REGISTER */
+#define BCHP_TIMER_WDCTRL                        0x004066bc /* WATCHDOG CONTROL REGISTER */
+
+/***************************************************************************
+ *TIMER_IS - TIMER INTERRUPT STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IS :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IS_reserved0_MASK                         0xffffffe0
+#define BCHP_TIMER_TIMER_IS_reserved0_SHIFT                        5
+
+/* TIMER :: TIMER_IS :: WDINT [04:04] */
+#define BCHP_TIMER_TIMER_IS_WDINT_MASK                             0x00000010
+#define BCHP_TIMER_TIMER_IS_WDINT_SHIFT                            4
+#define BCHP_TIMER_TIMER_IS_WDINT_DEFAULT                          0x00000000
+
+/* TIMER :: TIMER_IS :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IS_TMR3TO_MASK                            0x00000008
+#define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT                           3
+#define BCHP_TIMER_TIMER_IS_TMR3TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IS_TMR2TO_MASK                            0x00000004
+#define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT                           2
+#define BCHP_TIMER_TIMER_IS_TMR2TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IS_TMR1TO_MASK                            0x00000002
+#define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT                           1
+#define BCHP_TIMER_TIMER_IS_TMR1TO_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER_IS :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IS_TMR0TO_MASK                            0x00000001
+#define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT                           0
+#define BCHP_TIMER_TIMER_IS_TMR0TO_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE0 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE0_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE0_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE0_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE0_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE0_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE0_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *TIMER0_CTRL - TIMER0 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER0_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER0_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER0_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER0_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER0_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_CTRL - TIMER1 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER1_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER1_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER1_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER1_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER1_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_CTRL - TIMER2 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER2_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER2_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER2_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER2_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER2_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_CTRL - TIMER3 CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_CTRL :: ENA [31:31] */
+#define BCHP_TIMER_TIMER3_CTRL_ENA_MASK                            0x80000000
+#define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT                           31
+#define BCHP_TIMER_TIMER3_CTRL_ENA_DEFAULT                         0x00000000
+
+/* TIMER :: TIMER3_CTRL :: MODE [30:30] */
+#define BCHP_TIMER_TIMER3_CTRL_MODE_MASK                           0x40000000
+#define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT                          30
+#define BCHP_TIMER_TIMER3_CTRL_MODE_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER0_STAT - TIMER0 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER0_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER0_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER0_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER1_STAT - TIMER1 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER1_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER1_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER1_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER2_STAT - TIMER2 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER2_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER2_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER2_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TIMER3_STAT - TIMER3 STATUS REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER3_STAT :: SPARE [31:30] */
+#define BCHP_TIMER_TIMER3_STAT_SPARE_MASK                          0xc0000000
+#define BCHP_TIMER_TIMER3_STAT_SPARE_SHIFT                         30
+
+/* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK                    0x3fffffff
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT                   0
+#define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK                    0xffffffff
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT                   0
+#define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *WDCMD - WATCHDOG COMMAND REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCMD :: WDCMD [31:00] */
+#define BCHP_TIMER_WDCMD_WDCMD_MASK                                0xffffffff
+#define BCHP_TIMER_WDCMD_WDCMD_SHIFT                               0
+#define BCHP_TIMER_WDCMD_WDCMD_DEFAULT                             0x00000000
+
+/***************************************************************************
+ *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK                    0xfc000000
+#define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT                   26
+
+/* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK                0x03ffffff
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT               0
+#define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_DEFAULT             0x02ffffff
+
+/***************************************************************************
+ *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER
+ ***************************************************************************/
+/* TIMER :: TIMER_IE1 :: reserved0 [31:05] */
+#define BCHP_TIMER_TIMER_IE1_reserved0_MASK                        0xffffffe0
+#define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT                       5
+
+/* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK                        0x00000010
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT                       4
+#define BCHP_TIMER_TIMER_IE1_WDINTMASK_DEFAULT                     0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK                           0x00000008
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT                          3
+#define BCHP_TIMER_TIMER_IE1_TMR3TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK                           0x00000004
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT                          2
+#define BCHP_TIMER_TIMER_IE1_TMR2TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK                           0x00000002
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT                          1
+#define BCHP_TIMER_TIMER_IE1_TMR1TO_DEFAULT                        0x00000000
+
+/* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK                           0x00000001
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT                          0
+#define BCHP_TIMER_TIMER_IE1_TMR0TO_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *WDCTRL - WATCHDOG CONTROL REGISTER
+ ***************************************************************************/
+/* TIMER :: WDCTRL :: reserved0 [31:03] */
+#define BCHP_TIMER_WDCTRL_reserved0_MASK                           0xfffffff8
+#define BCHP_TIMER_WDCTRL_reserved0_SHIFT                          3
+
+/* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK                       0x00000004
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT                      2
+#define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_DEFAULT                    0x00000000
+
+/* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK                       0x00000003
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT                      0
+#define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_DEFAULT                    0x00000000
+
+#endif /* #ifndef BCHP_TIMER_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uarta.h b/include/linux/brcmstb/7362a0/bchp_uarta.h
new file mode 100644
index 000000000000..3c5e61a8bb62
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uarta.h
@@ -0,0 +1,394 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:19 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_uarta.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTA_H__
+#define BCHP_UARTA_H__
+
+/***************************************************************************
+ *UARTA - UART A
+ ***************************************************************************/
+#define BCHP_UARTA_RBR                           0x00406800 /* Receive Buffer Register */
+#define BCHP_UARTA_THR                           0x00406800 /* Transmit Holding Register */
+#define BCHP_UARTA_DLH                           0x00406804 /* Divisor Latch High */
+#define BCHP_UARTA_DLL                           0x00406800 /* Divisor Latch Low */
+#define BCHP_UARTA_IER                           0x00406804 /* Interrupt Enable Register */
+#define BCHP_UARTA_IIR                           0x00406808 /* Interrupt Identity Register */
+#define BCHP_UARTA_FCR                           0x00406808 /* FIFO Control Register */
+#define BCHP_UARTA_LCR                           0x0040680c /* Line Control Register */
+#define BCHP_UARTA_MCR                           0x00406810 /* Modem Control Register */
+#define BCHP_UARTA_LSR                           0x00406814 /* Line Status Register */
+#define BCHP_UARTA_MSR                           0x00406818 /* Modem Status Register */
+#define BCHP_UARTA_SCR                           0x0040681c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTA :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTA_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_RBR_reserved0_SHIFT                             8
+
+/* UARTA :: RBR :: RBR [07:00] */
+#define BCHP_UARTA_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTA_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTA_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTA :: THR :: reserved0 [31:08] */
+#define BCHP_UARTA_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_THR_reserved0_SHIFT                             8
+
+/* UARTA :: THR :: THR [07:00] */
+#define BCHP_UARTA_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTA_THR_THR_SHIFT                                   0
+#define BCHP_UARTA_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTA :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTA_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLH_reserved0_SHIFT                             8
+
+/* UARTA :: DLH :: DLH [07:00] */
+#define BCHP_UARTA_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTA_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTA_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTA :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTA_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_DLL_reserved0_SHIFT                             8
+
+/* UARTA :: DLL :: DLL [07:00] */
+#define BCHP_UARTA_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTA_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTA_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTA :: IER :: reserved0 [31:08] */
+#define BCHP_UARTA_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IER_reserved0_SHIFT                             8
+
+/* UARTA :: IER :: PTIME [07:07] */
+#define BCHP_UARTA_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTA_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTA_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: reserved1 [06:04] */
+#define BCHP_UARTA_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTA_IER_reserved1_SHIFT                             4
+
+/* UARTA :: IER :: EDSSI [03:03] */
+#define BCHP_UARTA_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTA_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTA_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ELSI [02:02] */
+#define BCHP_UARTA_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTA_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTA_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTA :: IER :: ETBEI [01:01] */
+#define BCHP_UARTA_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTA_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTA_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTA :: IER :: ERBFI [00:00] */
+#define BCHP_UARTA_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTA_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTA_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTA :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTA_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_IIR_reserved0_SHIFT                             8
+
+/* UARTA :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTA_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTA_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTA_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTA :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTA_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTA_IIR_reserved1_SHIFT                             4
+
+/* UARTA :: IIR :: IID [03:00] */
+#define BCHP_UARTA_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTA_IIR_IID_SHIFT                                   0
+#define BCHP_UARTA_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTA :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTA_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_FCR_reserved0_SHIFT                             8
+
+/* UARTA :: FCR :: RT [07:06] */
+#define BCHP_UARTA_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTA_FCR_RT_SHIFT                                    6
+#define BCHP_UARTA_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTA :: FCR :: TET [05:04] */
+#define BCHP_UARTA_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTA_FCR_TET_SHIFT                                   4
+#define BCHP_UARTA_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTA :: FCR :: DMAM [03:03] */
+#define BCHP_UARTA_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTA_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTA_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTA :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTA_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTA_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTA_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTA_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTA_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTA_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTA :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTA_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTA_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTA_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTA :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTA_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LCR_reserved0_SHIFT                             8
+
+/* UARTA :: LCR :: DLAB [07:07] */
+#define BCHP_UARTA_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTA_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTA_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: BC [06:06] */
+#define BCHP_UARTA_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTA_LCR_BC_SHIFT                                    6
+#define BCHP_UARTA_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTA :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTA_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTA_LCR_reserved1_SHIFT                             5
+
+/* UARTA :: LCR :: EPS [04:04] */
+#define BCHP_UARTA_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTA_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTA_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: PEN [03:03] */
+#define BCHP_UARTA_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTA_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTA_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTA :: LCR :: STOP [02:02] */
+#define BCHP_UARTA_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTA_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTA_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTA :: LCR :: DLS [01:00] */
+#define BCHP_UARTA_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTA_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTA_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTA :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTA_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTA_MCR_reserved0_SHIFT                             7
+
+/* UARTA :: MCR :: SIRE [06:06] */
+#define BCHP_UARTA_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTA_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTA_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: AFCE [05:05] */
+#define BCHP_UARTA_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTA_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTA_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: LB [04:04] */
+#define BCHP_UARTA_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTA_MCR_LB_SHIFT                                    4
+#define BCHP_UARTA_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTA :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTA_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTA_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTA_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTA_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTA_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTA_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTA :: MCR :: RTS [01:01] */
+#define BCHP_UARTA_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTA_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTA_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MCR :: DTR [00:00] */
+#define BCHP_UARTA_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTA_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTA_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTA :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTA_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_LSR_reserved0_SHIFT                             8
+
+/* UARTA :: LSR :: RFE [07:07] */
+#define BCHP_UARTA_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTA_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTA_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTA :: LSR :: TEMT [06:06] */
+#define BCHP_UARTA_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTA_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTA_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: THRE [05:05] */
+#define BCHP_UARTA_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTA_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTA_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTA :: LSR :: BI [04:04] */
+#define BCHP_UARTA_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTA_LSR_BI_SHIFT                                    4
+#define BCHP_UARTA_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: FE [03:03] */
+#define BCHP_UARTA_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTA_LSR_FE_SHIFT                                    3
+#define BCHP_UARTA_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: PE [02:02] */
+#define BCHP_UARTA_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTA_LSR_PE_SHIFT                                    2
+#define BCHP_UARTA_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: OE [01:01] */
+#define BCHP_UARTA_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTA_LSR_OE_SHIFT                                    1
+#define BCHP_UARTA_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTA :: LSR :: DR [00:00] */
+#define BCHP_UARTA_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTA_LSR_DR_SHIFT                                    0
+#define BCHP_UARTA_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTA :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTA_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_MSR_reserved0_SHIFT                             8
+
+/* UARTA :: MSR :: DCD [07:07] */
+#define BCHP_UARTA_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTA_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTA_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: RI [06:06] */
+#define BCHP_UARTA_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTA_MSR_RI_SHIFT                                    6
+#define BCHP_UARTA_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTA :: MSR :: DSR [05:05] */
+#define BCHP_UARTA_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTA_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTA_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: CTS [04:04] */
+#define BCHP_UARTA_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTA_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTA_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTA :: MSR :: DDCD [03:03] */
+#define BCHP_UARTA_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTA_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTA_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: TERI [02:02] */
+#define BCHP_UARTA_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTA_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTA_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DDSR [01:01] */
+#define BCHP_UARTA_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTA_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTA_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTA :: MSR :: DCTS [00:00] */
+#define BCHP_UARTA_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTA_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTA_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTA :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTA_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTA_SCR_reserved0_SHIFT                             8
+
+/* UARTA :: SCR :: SCR [07:00] */
+#define BCHP_UARTA_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTA_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTA_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTA_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uartb.h b/include/linux/brcmstb/7362a0/bchp_uartb.h
new file mode 100644
index 000000000000..8eede697bd3f
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uartb.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:43 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTB_H__
+#define BCHP_UARTB_H__
+
+/***************************************************************************
+ *UARTB - UART B
+ ***************************************************************************/
+#define BCHP_UARTB_RBR                           0x00406840 /* Receive Buffer Register */
+#define BCHP_UARTB_THR                           0x00406840 /* Transmit Holding Register */
+#define BCHP_UARTB_DLH                           0x00406844 /* Divisor Latch High */
+#define BCHP_UARTB_DLL                           0x00406840 /* Divisor Latch Low */
+#define BCHP_UARTB_IER                           0x00406844 /* Interrupt Enable Register */
+#define BCHP_UARTB_IIR                           0x00406848 /* Interrupt Identity Register */
+#define BCHP_UARTB_FCR                           0x00406848 /* FIFO Control Register */
+#define BCHP_UARTB_LCR                           0x0040684c /* Line Control Register */
+#define BCHP_UARTB_MCR                           0x00406850 /* Modem Control Register */
+#define BCHP_UARTB_LSR                           0x00406854 /* Line Status Register */
+#define BCHP_UARTB_MSR                           0x00406858 /* Modem Status Register */
+#define BCHP_UARTB_SCR                           0x0040685c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTB :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTB_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_RBR_reserved0_SHIFT                             8
+
+/* UARTB :: RBR :: RBR [07:00] */
+#define BCHP_UARTB_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTB_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTB_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTB :: THR :: reserved0 [31:08] */
+#define BCHP_UARTB_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_THR_reserved0_SHIFT                             8
+
+/* UARTB :: THR :: THR [07:00] */
+#define BCHP_UARTB_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTB_THR_THR_SHIFT                                   0
+#define BCHP_UARTB_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTB :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTB_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLH_reserved0_SHIFT                             8
+
+/* UARTB :: DLH :: DLH [07:00] */
+#define BCHP_UARTB_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTB_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTB_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTB :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTB_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_DLL_reserved0_SHIFT                             8
+
+/* UARTB :: DLL :: DLL [07:00] */
+#define BCHP_UARTB_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTB_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTB_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTB :: IER :: reserved0 [31:08] */
+#define BCHP_UARTB_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IER_reserved0_SHIFT                             8
+
+/* UARTB :: IER :: PTIME [07:07] */
+#define BCHP_UARTB_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTB_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTB_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: reserved1 [06:04] */
+#define BCHP_UARTB_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTB_IER_reserved1_SHIFT                             4
+
+/* UARTB :: IER :: EDSSI [03:03] */
+#define BCHP_UARTB_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTB_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTB_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ELSI [02:02] */
+#define BCHP_UARTB_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTB_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTB_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTB :: IER :: ETBEI [01:01] */
+#define BCHP_UARTB_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTB_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTB_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTB :: IER :: ERBFI [00:00] */
+#define BCHP_UARTB_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTB_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTB_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTB :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTB_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_IIR_reserved0_SHIFT                             8
+
+/* UARTB :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTB_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTB_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTB_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTB :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTB_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTB_IIR_reserved1_SHIFT                             4
+
+/* UARTB :: IIR :: IID [03:00] */
+#define BCHP_UARTB_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTB_IIR_IID_SHIFT                                   0
+#define BCHP_UARTB_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTB :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTB_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_FCR_reserved0_SHIFT                             8
+
+/* UARTB :: FCR :: RT [07:06] */
+#define BCHP_UARTB_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTB_FCR_RT_SHIFT                                    6
+#define BCHP_UARTB_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTB :: FCR :: TET [05:04] */
+#define BCHP_UARTB_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTB_FCR_TET_SHIFT                                   4
+#define BCHP_UARTB_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTB :: FCR :: DMAM [03:03] */
+#define BCHP_UARTB_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTB_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTB_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTB :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTB_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTB_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTB_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTB_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTB_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTB_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTB :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTB_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTB_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTB_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTB :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTB_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LCR_reserved0_SHIFT                             8
+
+/* UARTB :: LCR :: DLAB [07:07] */
+#define BCHP_UARTB_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTB_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTB_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: BC [06:06] */
+#define BCHP_UARTB_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTB_LCR_BC_SHIFT                                    6
+#define BCHP_UARTB_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTB :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTB_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTB_LCR_reserved1_SHIFT                             5
+
+/* UARTB :: LCR :: EPS [04:04] */
+#define BCHP_UARTB_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTB_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTB_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: PEN [03:03] */
+#define BCHP_UARTB_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTB_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTB_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTB :: LCR :: STOP [02:02] */
+#define BCHP_UARTB_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTB_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTB_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTB :: LCR :: DLS [01:00] */
+#define BCHP_UARTB_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTB_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTB_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTB :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTB_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTB_MCR_reserved0_SHIFT                             7
+
+/* UARTB :: MCR :: SIRE [06:06] */
+#define BCHP_UARTB_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTB_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTB_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: AFCE [05:05] */
+#define BCHP_UARTB_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTB_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTB_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: LB [04:04] */
+#define BCHP_UARTB_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTB_MCR_LB_SHIFT                                    4
+#define BCHP_UARTB_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTB :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTB_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTB_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTB_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTB_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTB_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTB_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTB :: MCR :: RTS [01:01] */
+#define BCHP_UARTB_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTB_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTB_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MCR :: DTR [00:00] */
+#define BCHP_UARTB_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTB_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTB_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTB :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTB_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_LSR_reserved0_SHIFT                             8
+
+/* UARTB :: LSR :: RFE [07:07] */
+#define BCHP_UARTB_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTB_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTB_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTB :: LSR :: TEMT [06:06] */
+#define BCHP_UARTB_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTB_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTB_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: THRE [05:05] */
+#define BCHP_UARTB_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTB_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTB_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTB :: LSR :: BI [04:04] */
+#define BCHP_UARTB_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTB_LSR_BI_SHIFT                                    4
+#define BCHP_UARTB_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: FE [03:03] */
+#define BCHP_UARTB_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTB_LSR_FE_SHIFT                                    3
+#define BCHP_UARTB_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: PE [02:02] */
+#define BCHP_UARTB_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTB_LSR_PE_SHIFT                                    2
+#define BCHP_UARTB_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: OE [01:01] */
+#define BCHP_UARTB_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTB_LSR_OE_SHIFT                                    1
+#define BCHP_UARTB_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTB :: LSR :: DR [00:00] */
+#define BCHP_UARTB_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTB_LSR_DR_SHIFT                                    0
+#define BCHP_UARTB_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTB :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTB_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_MSR_reserved0_SHIFT                             8
+
+/* UARTB :: MSR :: DCD [07:07] */
+#define BCHP_UARTB_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTB_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTB_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: RI [06:06] */
+#define BCHP_UARTB_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTB_MSR_RI_SHIFT                                    6
+#define BCHP_UARTB_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTB :: MSR :: DSR [05:05] */
+#define BCHP_UARTB_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTB_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTB_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: CTS [04:04] */
+#define BCHP_UARTB_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTB_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTB_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTB :: MSR :: DDCD [03:03] */
+#define BCHP_UARTB_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTB_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTB_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: TERI [02:02] */
+#define BCHP_UARTB_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTB_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTB_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DDSR [01:01] */
+#define BCHP_UARTB_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTB_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTB_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTB :: MSR :: DCTS [00:00] */
+#define BCHP_UARTB_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTB_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTB_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTB :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTB_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTB_SCR_reserved0_SHIFT                             8
+
+/* UARTB :: SCR :: SCR [07:00] */
+#define BCHP_UARTB_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTB_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTB_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTB_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_uartc.h b/include/linux/brcmstb/7362a0/bchp_uartc.h
new file mode 100644
index 000000000000..c1f7dad6e0b3
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_uartc.h
@@ -0,0 +1,391 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2013, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Wed Apr 24 17:25:42 2013
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008005
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_UARTC_H__
+#define BCHP_UARTC_H__
+
+/***************************************************************************
+ *UARTC - UART C
+ ***************************************************************************/
+#define BCHP_UARTC_RBR                           0x00406880 /* Receive Buffer Register */
+#define BCHP_UARTC_THR                           0x00406880 /* Transmit Holding Register */
+#define BCHP_UARTC_DLH                           0x00406884 /* Divisor Latch High */
+#define BCHP_UARTC_DLL                           0x00406880 /* Divisor Latch Low */
+#define BCHP_UARTC_IER                           0x00406884 /* Interrupt Enable Register */
+#define BCHP_UARTC_IIR                           0x00406888 /* Interrupt Identity Register */
+#define BCHP_UARTC_FCR                           0x00406888 /* FIFO Control Register */
+#define BCHP_UARTC_LCR                           0x0040688c /* Line Control Register */
+#define BCHP_UARTC_MCR                           0x00406890 /* Modem Control Register */
+#define BCHP_UARTC_LSR                           0x00406894 /* Line Status Register */
+#define BCHP_UARTC_MSR                           0x00406898 /* Modem Status Register */
+#define BCHP_UARTC_SCR                           0x0040689c /* Scratchpad Register */
+
+/***************************************************************************
+ *RBR - Receive Buffer Register
+ ***************************************************************************/
+/* UARTC :: RBR :: reserved0 [31:08] */
+#define BCHP_UARTC_RBR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_RBR_reserved0_SHIFT                             8
+
+/* UARTC :: RBR :: RBR [07:00] */
+#define BCHP_UARTC_RBR_RBR_MASK                                    0x000000ff
+#define BCHP_UARTC_RBR_RBR_SHIFT                                   0
+#define BCHP_UARTC_RBR_RBR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *THR - Transmit Holding Register
+ ***************************************************************************/
+/* UARTC :: THR :: reserved0 [31:08] */
+#define BCHP_UARTC_THR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_THR_reserved0_SHIFT                             8
+
+/* UARTC :: THR :: THR [07:00] */
+#define BCHP_UARTC_THR_THR_MASK                                    0x000000ff
+#define BCHP_UARTC_THR_THR_SHIFT                                   0
+#define BCHP_UARTC_THR_THR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLH - Divisor Latch High
+ ***************************************************************************/
+/* UARTC :: DLH :: reserved0 [31:08] */
+#define BCHP_UARTC_DLH_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLH_reserved0_SHIFT                             8
+
+/* UARTC :: DLH :: DLH [07:00] */
+#define BCHP_UARTC_DLH_DLH_MASK                                    0x000000ff
+#define BCHP_UARTC_DLH_DLH_SHIFT                                   0
+#define BCHP_UARTC_DLH_DLH_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *DLL - Divisor Latch Low
+ ***************************************************************************/
+/* UARTC :: DLL :: reserved0 [31:08] */
+#define BCHP_UARTC_DLL_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_DLL_reserved0_SHIFT                             8
+
+/* UARTC :: DLL :: DLL [07:00] */
+#define BCHP_UARTC_DLL_DLL_MASK                                    0x000000ff
+#define BCHP_UARTC_DLL_DLL_SHIFT                                   0
+#define BCHP_UARTC_DLL_DLL_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *IER - Interrupt Enable Register
+ ***************************************************************************/
+/* UARTC :: IER :: reserved0 [31:08] */
+#define BCHP_UARTC_IER_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IER_reserved0_SHIFT                             8
+
+/* UARTC :: IER :: PTIME [07:07] */
+#define BCHP_UARTC_IER_PTIME_MASK                                  0x00000080
+#define BCHP_UARTC_IER_PTIME_SHIFT                                 7
+#define BCHP_UARTC_IER_PTIME_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: reserved1 [06:04] */
+#define BCHP_UARTC_IER_reserved1_MASK                              0x00000070
+#define BCHP_UARTC_IER_reserved1_SHIFT                             4
+
+/* UARTC :: IER :: EDSSI [03:03] */
+#define BCHP_UARTC_IER_EDSSI_MASK                                  0x00000008
+#define BCHP_UARTC_IER_EDSSI_SHIFT                                 3
+#define BCHP_UARTC_IER_EDSSI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ELSI [02:02] */
+#define BCHP_UARTC_IER_ELSI_MASK                                   0x00000004
+#define BCHP_UARTC_IER_ELSI_SHIFT                                  2
+#define BCHP_UARTC_IER_ELSI_DEFAULT                                0x00000000
+
+/* UARTC :: IER :: ETBEI [01:01] */
+#define BCHP_UARTC_IER_ETBEI_MASK                                  0x00000002
+#define BCHP_UARTC_IER_ETBEI_SHIFT                                 1
+#define BCHP_UARTC_IER_ETBEI_DEFAULT                               0x00000000
+
+/* UARTC :: IER :: ERBFI [00:00] */
+#define BCHP_UARTC_IER_ERBFI_MASK                                  0x00000001
+#define BCHP_UARTC_IER_ERBFI_SHIFT                                 0
+#define BCHP_UARTC_IER_ERBFI_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *IIR - Interrupt Identity Register
+ ***************************************************************************/
+/* UARTC :: IIR :: reserved0 [31:08] */
+#define BCHP_UARTC_IIR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_IIR_reserved0_SHIFT                             8
+
+/* UARTC :: IIR :: FIFOSE [07:06] */
+#define BCHP_UARTC_IIR_FIFOSE_MASK                                 0x000000c0
+#define BCHP_UARTC_IIR_FIFOSE_SHIFT                                6
+#define BCHP_UARTC_IIR_FIFOSE_DEFAULT                              0x00000000
+
+/* UARTC :: IIR :: reserved1 [05:04] */
+#define BCHP_UARTC_IIR_reserved1_MASK                              0x00000030
+#define BCHP_UARTC_IIR_reserved1_SHIFT                             4
+
+/* UARTC :: IIR :: IID [03:00] */
+#define BCHP_UARTC_IIR_IID_MASK                                    0x0000000f
+#define BCHP_UARTC_IIR_IID_SHIFT                                   0
+#define BCHP_UARTC_IIR_IID_DEFAULT                                 0x00000001
+
+/***************************************************************************
+ *FCR - FIFO Control Register
+ ***************************************************************************/
+/* UARTC :: FCR :: reserved0 [31:08] */
+#define BCHP_UARTC_FCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_FCR_reserved0_SHIFT                             8
+
+/* UARTC :: FCR :: RT [07:06] */
+#define BCHP_UARTC_FCR_RT_MASK                                     0x000000c0
+#define BCHP_UARTC_FCR_RT_SHIFT                                    6
+#define BCHP_UARTC_FCR_RT_DEFAULT                                  0x00000000
+
+/* UARTC :: FCR :: TET [05:04] */
+#define BCHP_UARTC_FCR_TET_MASK                                    0x00000030
+#define BCHP_UARTC_FCR_TET_SHIFT                                   4
+#define BCHP_UARTC_FCR_TET_DEFAULT                                 0x00000000
+
+/* UARTC :: FCR :: DMAM [03:03] */
+#define BCHP_UARTC_FCR_DMAM_MASK                                   0x00000008
+#define BCHP_UARTC_FCR_DMAM_SHIFT                                  3
+#define BCHP_UARTC_FCR_DMAM_DEFAULT                                0x00000000
+
+/* UARTC :: FCR :: XFIFOR [02:02] */
+#define BCHP_UARTC_FCR_XFIFOR_MASK                                 0x00000004
+#define BCHP_UARTC_FCR_XFIFOR_SHIFT                                2
+#define BCHP_UARTC_FCR_XFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: RFIFOR [01:01] */
+#define BCHP_UARTC_FCR_RFIFOR_MASK                                 0x00000002
+#define BCHP_UARTC_FCR_RFIFOR_SHIFT                                1
+#define BCHP_UARTC_FCR_RFIFOR_DEFAULT                              0x00000000
+
+/* UARTC :: FCR :: FIFOE [00:00] */
+#define BCHP_UARTC_FCR_FIFOE_MASK                                  0x00000001
+#define BCHP_UARTC_FCR_FIFOE_SHIFT                                 0
+#define BCHP_UARTC_FCR_FIFOE_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *LCR - Line Control Register
+ ***************************************************************************/
+/* UARTC :: LCR :: reserved0 [31:08] */
+#define BCHP_UARTC_LCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LCR_reserved0_SHIFT                             8
+
+/* UARTC :: LCR :: DLAB [07:07] */
+#define BCHP_UARTC_LCR_DLAB_MASK                                   0x00000080
+#define BCHP_UARTC_LCR_DLAB_SHIFT                                  7
+#define BCHP_UARTC_LCR_DLAB_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: BC [06:06] */
+#define BCHP_UARTC_LCR_BC_MASK                                     0x00000040
+#define BCHP_UARTC_LCR_BC_SHIFT                                    6
+#define BCHP_UARTC_LCR_BC_DEFAULT                                  0x00000000
+
+/* UARTC :: LCR :: reserved1 [05:05] */
+#define BCHP_UARTC_LCR_reserved1_MASK                              0x00000020
+#define BCHP_UARTC_LCR_reserved1_SHIFT                             5
+
+/* UARTC :: LCR :: EPS [04:04] */
+#define BCHP_UARTC_LCR_EPS_MASK                                    0x00000010
+#define BCHP_UARTC_LCR_EPS_SHIFT                                   4
+#define BCHP_UARTC_LCR_EPS_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: PEN [03:03] */
+#define BCHP_UARTC_LCR_PEN_MASK                                    0x00000008
+#define BCHP_UARTC_LCR_PEN_SHIFT                                   3
+#define BCHP_UARTC_LCR_PEN_DEFAULT                                 0x00000000
+
+/* UARTC :: LCR :: STOP [02:02] */
+#define BCHP_UARTC_LCR_STOP_MASK                                   0x00000004
+#define BCHP_UARTC_LCR_STOP_SHIFT                                  2
+#define BCHP_UARTC_LCR_STOP_DEFAULT                                0x00000000
+
+/* UARTC :: LCR :: DLS [01:00] */
+#define BCHP_UARTC_LCR_DLS_MASK                                    0x00000003
+#define BCHP_UARTC_LCR_DLS_SHIFT                                   0
+#define BCHP_UARTC_LCR_DLS_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *MCR - Modem Control Register
+ ***************************************************************************/
+/* UARTC :: MCR :: reserved0 [31:07] */
+#define BCHP_UARTC_MCR_reserved0_MASK                              0xffffff80
+#define BCHP_UARTC_MCR_reserved0_SHIFT                             7
+
+/* UARTC :: MCR :: SIRE [06:06] */
+#define BCHP_UARTC_MCR_SIRE_MASK                                   0x00000040
+#define BCHP_UARTC_MCR_SIRE_SHIFT                                  6
+#define BCHP_UARTC_MCR_SIRE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: AFCE [05:05] */
+#define BCHP_UARTC_MCR_AFCE_MASK                                   0x00000020
+#define BCHP_UARTC_MCR_AFCE_SHIFT                                  5
+#define BCHP_UARTC_MCR_AFCE_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: LB [04:04] */
+#define BCHP_UARTC_MCR_LB_MASK                                     0x00000010
+#define BCHP_UARTC_MCR_LB_SHIFT                                    4
+#define BCHP_UARTC_MCR_LB_DEFAULT                                  0x00000000
+
+/* UARTC :: MCR :: OUT2 [03:03] */
+#define BCHP_UARTC_MCR_OUT2_MASK                                   0x00000008
+#define BCHP_UARTC_MCR_OUT2_SHIFT                                  3
+#define BCHP_UARTC_MCR_OUT2_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: OUT1 [02:02] */
+#define BCHP_UARTC_MCR_OUT1_MASK                                   0x00000004
+#define BCHP_UARTC_MCR_OUT1_SHIFT                                  2
+#define BCHP_UARTC_MCR_OUT1_DEFAULT                                0x00000000
+
+/* UARTC :: MCR :: RTS [01:01] */
+#define BCHP_UARTC_MCR_RTS_MASK                                    0x00000002
+#define BCHP_UARTC_MCR_RTS_SHIFT                                   1
+#define BCHP_UARTC_MCR_RTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MCR :: DTR [00:00] */
+#define BCHP_UARTC_MCR_DTR_MASK                                    0x00000001
+#define BCHP_UARTC_MCR_DTR_SHIFT                                   0
+#define BCHP_UARTC_MCR_DTR_DEFAULT                                 0x00000000
+
+/***************************************************************************
+ *LSR - Line Status Register
+ ***************************************************************************/
+/* UARTC :: LSR :: reserved0 [31:08] */
+#define BCHP_UARTC_LSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_LSR_reserved0_SHIFT                             8
+
+/* UARTC :: LSR :: RFE [07:07] */
+#define BCHP_UARTC_LSR_RFE_MASK                                    0x00000080
+#define BCHP_UARTC_LSR_RFE_SHIFT                                   7
+#define BCHP_UARTC_LSR_RFE_DEFAULT                                 0x00000000
+
+/* UARTC :: LSR :: TEMT [06:06] */
+#define BCHP_UARTC_LSR_TEMT_MASK                                   0x00000040
+#define BCHP_UARTC_LSR_TEMT_SHIFT                                  6
+#define BCHP_UARTC_LSR_TEMT_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: THRE [05:05] */
+#define BCHP_UARTC_LSR_THRE_MASK                                   0x00000020
+#define BCHP_UARTC_LSR_THRE_SHIFT                                  5
+#define BCHP_UARTC_LSR_THRE_DEFAULT                                0x00000001
+
+/* UARTC :: LSR :: BI [04:04] */
+#define BCHP_UARTC_LSR_BI_MASK                                     0x00000010
+#define BCHP_UARTC_LSR_BI_SHIFT                                    4
+#define BCHP_UARTC_LSR_BI_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: FE [03:03] */
+#define BCHP_UARTC_LSR_FE_MASK                                     0x00000008
+#define BCHP_UARTC_LSR_FE_SHIFT                                    3
+#define BCHP_UARTC_LSR_FE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: PE [02:02] */
+#define BCHP_UARTC_LSR_PE_MASK                                     0x00000004
+#define BCHP_UARTC_LSR_PE_SHIFT                                    2
+#define BCHP_UARTC_LSR_PE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: OE [01:01] */
+#define BCHP_UARTC_LSR_OE_MASK                                     0x00000002
+#define BCHP_UARTC_LSR_OE_SHIFT                                    1
+#define BCHP_UARTC_LSR_OE_DEFAULT                                  0x00000000
+
+/* UARTC :: LSR :: DR [00:00] */
+#define BCHP_UARTC_LSR_DR_MASK                                     0x00000001
+#define BCHP_UARTC_LSR_DR_SHIFT                                    0
+#define BCHP_UARTC_LSR_DR_DEFAULT                                  0x00000000
+
+/***************************************************************************
+ *MSR - Modem Status Register
+ ***************************************************************************/
+/* UARTC :: MSR :: reserved0 [31:08] */
+#define BCHP_UARTC_MSR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_MSR_reserved0_SHIFT                             8
+
+/* UARTC :: MSR :: DCD [07:07] */
+#define BCHP_UARTC_MSR_DCD_MASK                                    0x00000080
+#define BCHP_UARTC_MSR_DCD_SHIFT                                   7
+#define BCHP_UARTC_MSR_DCD_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: RI [06:06] */
+#define BCHP_UARTC_MSR_RI_MASK                                     0x00000040
+#define BCHP_UARTC_MSR_RI_SHIFT                                    6
+#define BCHP_UARTC_MSR_RI_DEFAULT                                  0x00000000
+
+/* UARTC :: MSR :: DSR [05:05] */
+#define BCHP_UARTC_MSR_DSR_MASK                                    0x00000020
+#define BCHP_UARTC_MSR_DSR_SHIFT                                   5
+#define BCHP_UARTC_MSR_DSR_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: CTS [04:04] */
+#define BCHP_UARTC_MSR_CTS_MASK                                    0x00000010
+#define BCHP_UARTC_MSR_CTS_SHIFT                                   4
+#define BCHP_UARTC_MSR_CTS_DEFAULT                                 0x00000000
+
+/* UARTC :: MSR :: DDCD [03:03] */
+#define BCHP_UARTC_MSR_DDCD_MASK                                   0x00000008
+#define BCHP_UARTC_MSR_DDCD_SHIFT                                  3
+#define BCHP_UARTC_MSR_DDCD_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: TERI [02:02] */
+#define BCHP_UARTC_MSR_TERI_MASK                                   0x00000004
+#define BCHP_UARTC_MSR_TERI_SHIFT                                  2
+#define BCHP_UARTC_MSR_TERI_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DDSR [01:01] */
+#define BCHP_UARTC_MSR_DDSR_MASK                                   0x00000002
+#define BCHP_UARTC_MSR_DDSR_SHIFT                                  1
+#define BCHP_UARTC_MSR_DDSR_DEFAULT                                0x00000000
+
+/* UARTC :: MSR :: DCTS [00:00] */
+#define BCHP_UARTC_MSR_DCTS_MASK                                   0x00000001
+#define BCHP_UARTC_MSR_DCTS_SHIFT                                  0
+#define BCHP_UARTC_MSR_DCTS_DEFAULT                                0x00000000
+
+/***************************************************************************
+ *SCR - Scratchpad Register
+ ***************************************************************************/
+/* UARTC :: SCR :: reserved0 [31:08] */
+#define BCHP_UARTC_SCR_reserved0_MASK                              0xffffff00
+#define BCHP_UARTC_SCR_reserved0_SHIFT                             8
+
+/* UARTC :: SCR :: SCR [07:00] */
+#define BCHP_UARTC_SCR_SCR_MASK                                    0x000000ff
+#define BCHP_UARTC_SCR_SCR_SHIFT                                   0
+#define BCHP_UARTC_SCR_SCR_DEFAULT                                 0x00000000
+
+#endif /* #ifndef BCHP_UARTC_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..e116fa226117
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_usb_ctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_usb_ctrl.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:33p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_SPARE1                     0x00480234 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE2                     0x00480238 /* Spare2 Register for future use */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC_DISABLE [31:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0xf0000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: SRAM_CS_DIS [27:26] */
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_MASK                       0x0c000000
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_SHIFT                      26
+#define BCHP_USB_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [25:13] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03ffe000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      13
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [12:12] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00001000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 12
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: discon_intr_en [11:11] */
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_MASK                    0x00000800
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_SHIFT                   11
+#define BCHP_USB_CTRL_SETUP_discon_intr_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: con_intr_en [10:10] */
+#define BCHP_USB_CTRL_SETUP_con_intr_en_MASK                       0x00000400
+#define BCHP_USB_CTRL_SETUP_con_intr_en_SHIFT                      10
+#define BCHP_USB_CTRL_SETUP_con_intr_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: SOFT_SHUTDOWN [09:09] */
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_SOFT_SHUTDOWN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000003
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                   0x00008000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                  15
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x00007000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000028
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_rdgwordcnt_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_MASK              0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_SHIFT             28
+#define BCHP_USB_CTRL_OBRIDGE_obr_rdgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_SPARE [31:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0xfc000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT               0x0000270a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_MASK                     0x80000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                    31
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:24] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0x7f000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [23:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt2_oe [22:22] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_MASK                0x00400000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_SHIFT               22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt2_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_tstsel [21:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_MASK             0x00200000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_SHIFT            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron2_tstsel [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_MASK             0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_SHIFT            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron2_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: test_clksel [19:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_MASK               0x000c0000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_SHIFT              18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_test_clksel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_tstsel [17:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_MASK             0x00030000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_SHIFT            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_tstsel_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TEST_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_MASK             0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_SHIFT            8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TEST_SEL_DEFAULT          0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               28
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:01] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffffe
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                1
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: FS_DLY_EN [00:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_MASK                    0x00000001
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_SHIFT                   0
+#define BCHP_USB_CTRL_USB_SIMCTL_FS_DLY_EN_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:22] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xffc00000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             22
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CTRLLER_SEL [21:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_MASK                 0x00200000
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_SHIFT                21
+#define BCHP_USB_CTRL_USB_TESTCTL_CTRLLER_SEL_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0xffffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK                0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT               27
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_MASK                0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_SHIFT               26
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE2 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_MASK              0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_SHIFT             25
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK                0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT               24
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PLL_SUSPEND_EN [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_MASK               0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_SHIFT              15
+#define BCHP_USB_CTRL_UTMI_CTL_1_PLL_SUSPEND_EN_DEFAULT            0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                   0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                  11
+#define BCHP_USB_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_LPBACK [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_MASK                   0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_SHIFT                  10
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_LPBACK_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK              0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT             9
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                   0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                  8
+#define BCHP_USB_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SPARE1 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE1_SPARE1_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE2 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE2_SPARE2_BITS_DEFAULT                   0x00000000
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/bchp_wktmr.h b/include/linux/brcmstb/7362a0/bchp_wktmr.h
new file mode 100644
index 000000000000..e0d95f7ebb0c
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/bchp_wktmr.h
@@ -0,0 +1,108 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2012, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on         Tue Jan 17 10:22:18 2012
+ *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
+ *
+ * Compiled with:  RDB Utility          combo_header.pl
+ *                 RDB Parser           3.0
+ *                 unknown              unknown
+ *                 Perl Interpreter     5.008008
+ *                 Operating System     linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: /magnum/basemodules/chp/7360/rdb/a0/bchp_wktmr.h $
+ * 
+ * Hydra_Software_Devel/2   1/17/12 12:38p pntruong
+ * SW7360-8: Synced up with central rdb.
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_WKTMR_H__
+#define BCHP_WKTMR_H__
+
+/***************************************************************************
+ *WKTMR - Wakeup timer
+ ***************************************************************************/
+#define BCHP_WKTMR_EVENT                         0x00408e80 /* Wakeup Timer Register */
+#define BCHP_WKTMR_COUNTER                       0x00408e84 /* Wakeup Counter */
+#define BCHP_WKTMR_ALARM                         0x00408e88 /* Wakeup Timer Alarm */
+#define BCHP_WKTMR_PRESCALER                     0x00408e8c /* Wakeup Timer Prescaler */
+#define BCHP_WKTMR_PRESCALER_VAL                 0x00408e90 /* Wakeup Timer Prescaler Value */
+
+/***************************************************************************
+ *EVENT - Wakeup Timer Register
+ ***************************************************************************/
+/* WKTMR :: EVENT :: reserved0 [31:01] */
+#define BCHP_WKTMR_EVENT_reserved0_MASK                            0xfffffffe
+#define BCHP_WKTMR_EVENT_reserved0_SHIFT                           1
+
+/* WKTMR :: EVENT :: wktmr_alarm_event [00:00] */
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_MASK                    0x00000001
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_SHIFT                   0
+#define BCHP_WKTMR_EVENT_wktmr_alarm_event_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *COUNTER - Wakeup Counter
+ ***************************************************************************/
+/* WKTMR :: COUNTER :: wktmr_counter [31:00] */
+#define BCHP_WKTMR_COUNTER_wktmr_counter_MASK                      0xffffffff
+#define BCHP_WKTMR_COUNTER_wktmr_counter_SHIFT                     0
+#define BCHP_WKTMR_COUNTER_wktmr_counter_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *ALARM - Wakeup Timer Alarm
+ ***************************************************************************/
+/* WKTMR :: ALARM :: wktmr_alarm [31:00] */
+#define BCHP_WKTMR_ALARM_wktmr_alarm_MASK                          0xffffffff
+#define BCHP_WKTMR_ALARM_wktmr_alarm_SHIFT                         0
+#define BCHP_WKTMR_ALARM_wktmr_alarm_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *PRESCALER - Wakeup Timer Prescaler
+ ***************************************************************************/
+/* WKTMR :: PRESCALER :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_reserved0_MASK                        0xfe000000
+#define BCHP_WKTMR_PRESCALER_reserved0_SHIFT                       25
+
+/* WKTMR :: PRESCALER :: wktmr_prescaler [24:00] */
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_MASK                  0x01ffffff
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_SHIFT                 0
+#define BCHP_WKTMR_PRESCALER_wktmr_prescaler_DEFAULT               0x019bfcc0
+
+/***************************************************************************
+ *PRESCALER_VAL - Wakeup Timer Prescaler Value
+ ***************************************************************************/
+/* WKTMR :: PRESCALER_VAL :: reserved0 [31:25] */
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_MASK                    0xfe000000
+#define BCHP_WKTMR_PRESCALER_VAL_reserved0_SHIFT                   25
+
+/* WKTMR :: PRESCALER_VAL :: wktmr_prescaler_val [24:00] */
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_MASK          0x01ffffff
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_SHIFT         0
+#define BCHP_WKTMR_PRESCALER_VAL_wktmr_prescaler_val_DEFAULT       0x00000000
+
+#endif /* #ifndef BCHP_WKTMR_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7362a0/brcmirq.h b/include/linux/brcmstb/7362a0/brcmirq.h
new file mode 100644
index 000000000000..b899a30b2f54
--- /dev/null
+++ b/include/linux/brcmstb/7362a0/brcmirq.h
@@ -0,0 +1,39 @@
+/*
+ * 7360a0 IRQ header file autogenerated by update_bchp.pl
+ * DO NOT EDIT THIS FILE BY HAND.
+ *
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BRCMIRQ_H_
+#define _BRCMIRQ_H_
+
+#define BRCM_IRQ_EHCI0_0	66
+#define BRCM_IRQ_GENET_0_A	25
+#define BRCM_IRQ_GENET_0_B	26
+#define BRCM_IRQ_HIF		31
+#define BRCM_IRQ_HIF_SPI	32
+#define BRCM_IRQ_OHCI0_0	67
+#define BRCM_IRQ_SATA		87
+#define BRCM_IRQ_SDIO0		83
+#define BRCM_IRQ_STANDBY	51
+#define BRCM_IRQ_UARTA		62
+#define BRCM_IRQ_UARTB		63
+#define BRCM_IRQ_UARTC		64
+#define BRCM_IRQLIST_EHCI	{ 66 }
+#define BRCM_IRQLIST_OHCI	{ 67 }
+
+#endif /* _BRCMIRQ_H_ */
diff --git a/include/linux/brcmstb/7364a0/bchp_bspi.h b/include/linux/brcmstb/7364a0/bchp_bspi.h
new file mode 100644
index 000000000000..50fe2179181d
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_bspi.h
@@ -0,0 +1,445 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:40 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_H__
+#define BCHP_BSPI_H__
+
+/***************************************************************************
+ *BSPI - Public BSPI Control Registers
+ ***************************************************************************/
+#define BCHP_BSPI_REVISION_ID                    0x00443200 /* Revision ID */
+#define BCHP_BSPI_SCRATCH                        0x00443204 /* Revision ID */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL               0x00443208 /* Master/Boot SPI Control Register */
+#define BCHP_BSPI_BUSY_STATUS                    0x0044320c /* BSPI Busy Status Register */
+#define BCHP_BSPI_INTR_STATUS                    0x00443210 /* Interrupt Status Register */
+#define BCHP_BSPI_B0_STATUS                      0x00443214 /* Prefetch Buffer 0 Status Register */
+#define BCHP_BSPI_B0_CTRL                        0x00443218 /* Prefetch Buffer 0 Control Register */
+#define BCHP_BSPI_B1_STATUS                      0x0044321c /* Prefetch Buffer 1 Status Register */
+#define BCHP_BSPI_B1_CTRL                        0x00443220 /* Prefetch Buffer 1 Control Register */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL            0x00443224 /* Dual/Single Receive Mode Control Register */
+#define BCHP_BSPI_FLEX_MODE_ENABLE               0x00443228 /* Flexible Control Mode Enable Register */
+#define BCHP_BSPI_BITS_PER_CYCLE                 0x0044322c /* Bits per cycle "b-p-c" Control Register */
+#define BCHP_BSPI_BITS_PER_PHASE                 0x00443230 /* Bits per Phase "b-p-p" Control Register */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE              0x00443234 /* Command and Mode Data Register */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE     0x00443238 /* Bspi FLash upper address byte register */
+#define BCHP_BSPI_BSPI_XOR_VALUE                 0x0044323c /* BSPI FLASH XOR Value Register */
+#define BCHP_BSPI_BSPI_XOR_ENABLE                0x00443240 /* BSPI FLASH XOR Enable Register */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE           0x00443244 /* BSPI Pin  Programmed IO Mode Enable Register */
+#define BCHP_BSPI_BSPI_PIO_IODIR                 0x00443248 /* BSPI Pin  Programmed IO Mode Direction Register */
+#define BCHP_BSPI_BSPI_PIO_DATA                  0x0044324c /* BSPI Pin  Programmed IO Mode Data Register */
+
+/***************************************************************************
+ *REVISION_ID - Revision ID
+ ***************************************************************************/
+/* BSPI :: REVISION_ID :: reserved0 [31:16] */
+#define BCHP_BSPI_REVISION_ID_reserved0_MASK                       0xffff0000
+#define BCHP_BSPI_REVISION_ID_reserved0_SHIFT                      16
+
+/* BSPI :: REVISION_ID :: MAJOR [15:08] */
+#define BCHP_BSPI_REVISION_ID_MAJOR_MASK                           0x0000ff00
+#define BCHP_BSPI_REVISION_ID_MAJOR_SHIFT                          8
+#define BCHP_BSPI_REVISION_ID_MAJOR_DEFAULT                        0x00000004
+
+/* BSPI :: REVISION_ID :: MINOR [07:00] */
+#define BCHP_BSPI_REVISION_ID_MINOR_MASK                           0x000000ff
+#define BCHP_BSPI_REVISION_ID_MINOR_SHIFT                          0
+#define BCHP_BSPI_REVISION_ID_MINOR_DEFAULT                        0x00000002
+
+/***************************************************************************
+ *SCRATCH - Revision ID
+ ***************************************************************************/
+/* BSPI :: SCRATCH :: SCRATCH [31:00] */
+#define BCHP_BSPI_SCRATCH_SCRATCH_MASK                             0xffffffff
+#define BCHP_BSPI_SCRATCH_SCRATCH_SHIFT                            0
+#define BCHP_BSPI_SCRATCH_SCRATCH_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *MAST_N_BOOT_CTRL - Master/Boot SPI Control Register
+ ***************************************************************************/
+/* BSPI :: MAST_N_BOOT_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_reserved0_SHIFT                 1
+
+/* BSPI :: MAST_N_BOOT_CTRL :: mast_n_boot [00:00] */
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_MASK                0x00000001
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_SHIFT               0
+#define BCHP_BSPI_MAST_N_BOOT_CTRL_mast_n_boot_DEFAULT             0x00000000
+
+/***************************************************************************
+ *BUSY_STATUS - BSPI Busy Status Register
+ ***************************************************************************/
+/* BSPI :: BUSY_STATUS :: reserved0 [31:01] */
+#define BCHP_BSPI_BUSY_STATUS_reserved0_MASK                       0xfffffffe
+#define BCHP_BSPI_BUSY_STATUS_reserved0_SHIFT                      1
+
+/* BSPI :: BUSY_STATUS :: busy [00:00] */
+#define BCHP_BSPI_BUSY_STATUS_busy_MASK                            0x00000001
+#define BCHP_BSPI_BUSY_STATUS_busy_SHIFT                           0
+#define BCHP_BSPI_BUSY_STATUS_busy_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *INTR_STATUS - Interrupt Status Register
+ ***************************************************************************/
+/* BSPI :: INTR_STATUS :: reserved0 [31:02] */
+#define BCHP_BSPI_INTR_STATUS_reserved0_MASK                       0xfffffffc
+#define BCHP_BSPI_INTR_STATUS_reserved0_SHIFT                      2
+
+/* BSPI :: INTR_STATUS :: intr_1 [01:01] */
+#define BCHP_BSPI_INTR_STATUS_intr_1_MASK                          0x00000002
+#define BCHP_BSPI_INTR_STATUS_intr_1_SHIFT                         1
+#define BCHP_BSPI_INTR_STATUS_intr_1_DEFAULT                       0x00000000
+
+/* BSPI :: INTR_STATUS :: intr_0 [00:00] */
+#define BCHP_BSPI_INTR_STATUS_intr_0_MASK                          0x00000001
+#define BCHP_BSPI_INTR_STATUS_intr_0_SHIFT                         0
+#define BCHP_BSPI_INTR_STATUS_intr_0_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *B0_STATUS - Prefetch Buffer 0 Status Register
+ ***************************************************************************/
+/* BSPI :: B0_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B0_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B0_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B0_STATUS :: b0_prefetch_active [30:30] */
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B0_STATUS_b0_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B0_STATUS :: b0_full [29:29] */
+#define BCHP_BSPI_B0_STATUS_b0_full_MASK                           0x20000000
+#define BCHP_BSPI_B0_STATUS_b0_full_SHIFT                          29
+#define BCHP_BSPI_B0_STATUS_b0_full_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_empty [28:28] */
+#define BCHP_BSPI_B0_STATUS_b0_empty_MASK                          0x10000000
+#define BCHP_BSPI_B0_STATUS_b0_empty_SHIFT                         28
+#define BCHP_BSPI_B0_STATUS_b0_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B0_STATUS :: b0_miss [27:27] */
+#define BCHP_BSPI_B0_STATUS_b0_miss_MASK                           0x08000000
+#define BCHP_BSPI_B0_STATUS_b0_miss_SHIFT                          27
+#define BCHP_BSPI_B0_STATUS_b0_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B0_STATUS :: b0_hit [26:26] */
+#define BCHP_BSPI_B0_STATUS_b0_hit_MASK                            0x04000000
+#define BCHP_BSPI_B0_STATUS_b0_hit_SHIFT                           26
+#define BCHP_BSPI_B0_STATUS_b0_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B0_STATUS :: b0_address [25:00] */
+#define BCHP_BSPI_B0_STATUS_b0_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B0_STATUS_b0_address_SHIFT                       0
+#define BCHP_BSPI_B0_STATUS_b0_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B0_CTRL - Prefetch Buffer 0 Control Register
+ ***************************************************************************/
+/* BSPI :: B0_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B0_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B0_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B0_CTRL :: b0_flush [00:00] */
+#define BCHP_BSPI_B0_CTRL_b0_flush_MASK                            0x00000001
+#define BCHP_BSPI_B0_CTRL_b0_flush_SHIFT                           0
+#define BCHP_BSPI_B0_CTRL_b0_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *B1_STATUS - Prefetch Buffer 1 Status Register
+ ***************************************************************************/
+/* BSPI :: B1_STATUS :: reserved0 [31:31] */
+#define BCHP_BSPI_B1_STATUS_reserved0_MASK                         0x80000000
+#define BCHP_BSPI_B1_STATUS_reserved0_SHIFT                        31
+
+/* BSPI :: B1_STATUS :: b1_prefetch_active [30:30] */
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_MASK                0x40000000
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_SHIFT               30
+#define BCHP_BSPI_B1_STATUS_b1_prefetch_active_DEFAULT             0x00000000
+
+/* BSPI :: B1_STATUS :: b1_full [29:29] */
+#define BCHP_BSPI_B1_STATUS_b1_full_MASK                           0x20000000
+#define BCHP_BSPI_B1_STATUS_b1_full_SHIFT                          29
+#define BCHP_BSPI_B1_STATUS_b1_full_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_empty [28:28] */
+#define BCHP_BSPI_B1_STATUS_b1_empty_MASK                          0x10000000
+#define BCHP_BSPI_B1_STATUS_b1_empty_SHIFT                         28
+#define BCHP_BSPI_B1_STATUS_b1_empty_DEFAULT                       0x00000001
+
+/* BSPI :: B1_STATUS :: b1_miss [27:27] */
+#define BCHP_BSPI_B1_STATUS_b1_miss_MASK                           0x08000000
+#define BCHP_BSPI_B1_STATUS_b1_miss_SHIFT                          27
+#define BCHP_BSPI_B1_STATUS_b1_miss_DEFAULT                        0x00000000
+
+/* BSPI :: B1_STATUS :: b1_hit [26:26] */
+#define BCHP_BSPI_B1_STATUS_b1_hit_MASK                            0x04000000
+#define BCHP_BSPI_B1_STATUS_b1_hit_SHIFT                           26
+#define BCHP_BSPI_B1_STATUS_b1_hit_DEFAULT                         0x00000000
+
+/* BSPI :: B1_STATUS :: b1_address [25:00] */
+#define BCHP_BSPI_B1_STATUS_b1_address_MASK                        0x03ffffff
+#define BCHP_BSPI_B1_STATUS_b1_address_SHIFT                       0
+#define BCHP_BSPI_B1_STATUS_b1_address_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *B1_CTRL - Prefetch Buffer 1 Control Register
+ ***************************************************************************/
+/* BSPI :: B1_CTRL :: reserved0 [31:01] */
+#define BCHP_BSPI_B1_CTRL_reserved0_MASK                           0xfffffffe
+#define BCHP_BSPI_B1_CTRL_reserved0_SHIFT                          1
+
+/* BSPI :: B1_CTRL :: b1_flush [00:00] */
+#define BCHP_BSPI_B1_CTRL_b1_flush_MASK                            0x00000001
+#define BCHP_BSPI_B1_CTRL_b1_flush_SHIFT                           0
+#define BCHP_BSPI_B1_CTRL_b1_flush_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *STRAP_OVERRIDE_CTRL - Dual/Single Receive Mode Control Register
+ ***************************************************************************/
+/* BSPI :: STRAP_OVERRIDE_CTRL :: reserved0 [31:05] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_MASK               0xffffffe0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_reserved0_SHIFT              5
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: endian_mode [04:04] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_MASK             0x00000010
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_SHIFT            4
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_endian_mode_DEFAULT          0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_quad [03:03] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_MASK               0x00000008
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_SHIFT              3
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_quad_DEFAULT            0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: addr_4byte_n_3byte [02:02] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_MASK      0x00000004
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_SHIFT     2
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte_DEFAULT   0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: data_dual_n_sgl [01:01] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_MASK         0x00000002
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_SHIFT        1
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_data_dual_n_sgl_DEFAULT      0x00000000
+
+/* BSPI :: STRAP_OVERRIDE_CTRL :: override [00:00] */
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_MASK                0x00000001
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_SHIFT               0
+#define BCHP_BSPI_STRAP_OVERRIDE_CTRL_override_DEFAULT             0x00000000
+
+/***************************************************************************
+ *FLEX_MODE_ENABLE - Flexible Control Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: FLEX_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_MASK                  0xfffffffe
+#define BCHP_BSPI_FLEX_MODE_ENABLE_reserved0_SHIFT                 1
+
+/* BSPI :: FLEX_MODE_ENABLE :: bspi_flex_mode_enable [00:00] */
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_MASK      0x00000001
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_SHIFT     0
+#define BCHP_BSPI_FLEX_MODE_ENABLE_bspi_flex_mode_enable_DEFAULT   0x00000000
+
+/***************************************************************************
+ *BITS_PER_CYCLE - Bits per cycle "b-p-c" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_CYCLE :: reserved0 [31:26] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_MASK                    0xfc000000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved0_SHIFT                   26
+
+/* BSPI :: BITS_PER_CYCLE :: cmd_bpc_select [25:24] */
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_MASK               0x03000000
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_CYCLE_cmd_bpc_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved1 [23:18] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_MASK                    0x00fc0000
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved1_SHIFT                   18
+
+/* BSPI :: BITS_PER_CYCLE :: addr_bpc_select [17:16] */
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_MASK              0x00030000
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_CYCLE_addr_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved2 [15:10] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_MASK                    0x0000fc00
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved2_SHIFT                   10
+
+/* BSPI :: BITS_PER_CYCLE :: mode_bpc_select [09:08] */
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_MASK              0x00000300
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_SHIFT             8
+#define BCHP_BSPI_BITS_PER_CYCLE_mode_bpc_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_CYCLE :: reserved3 [07:02] */
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_MASK                    0x000000fc
+#define BCHP_BSPI_BITS_PER_CYCLE_reserved3_SHIFT                   2
+
+/* BSPI :: BITS_PER_CYCLE :: data_bpc_select [01:00] */
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_MASK              0x00000003
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_SHIFT             0
+#define BCHP_BSPI_BITS_PER_CYCLE_data_bpc_select_DEFAULT           0x00000000
+
+/***************************************************************************
+ *BITS_PER_PHASE - Bits per Phase "b-p-p" Control Register
+ ***************************************************************************/
+/* BSPI :: BITS_PER_PHASE :: reserved0 [31:25] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_MASK                    0xfe000000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved0_SHIFT                   25
+
+/* BSPI :: BITS_PER_PHASE :: cmd_bpp_select [24:24] */
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_MASK               0x01000000
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_SHIFT              24
+#define BCHP_BSPI_BITS_PER_PHASE_cmd_bpp_select_DEFAULT            0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved1 [23:17] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_MASK                    0x00fe0000
+#define BCHP_BSPI_BITS_PER_PHASE_reserved1_SHIFT                   17
+
+/* BSPI :: BITS_PER_PHASE :: addr_bpp_select [16:16] */
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_MASK              0x00010000
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_SHIFT             16
+#define BCHP_BSPI_BITS_PER_PHASE_addr_bpp_select_DEFAULT           0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: reserved2 [15:09] */
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_MASK                    0x0000fe00
+#define BCHP_BSPI_BITS_PER_PHASE_reserved2_SHIFT                   9
+
+/* BSPI :: BITS_PER_PHASE :: mode_bpp [08:08] */
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_MASK                     0x00000100
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_SHIFT                    8
+#define BCHP_BSPI_BITS_PER_PHASE_mode_bpp_DEFAULT                  0x00000000
+
+/* BSPI :: BITS_PER_PHASE :: dummy_cycles [07:00] */
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_MASK                 0x000000ff
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_SHIFT                0
+#define BCHP_BSPI_BITS_PER_PHASE_dummy_cycles_DEFAULT              0x00000008
+
+/***************************************************************************
+ *CMD_AND_MODE_BYTE - Command and Mode Data Register
+ ***************************************************************************/
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved0 [31:24] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_MASK                 0xff000000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved0_SHIFT                24
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_mode_byte [23:16] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_MASK            0x00ff0000
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_SHIFT           16
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_mode_byte_DEFAULT         0x00000000
+
+/* BSPI :: CMD_AND_MODE_BYTE :: reserved1 [15:08] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_MASK                 0x0000ff00
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_reserved1_SHIFT                8
+
+/* BSPI :: CMD_AND_MODE_BYTE :: bspi_cmd_byte [07:00] */
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_MASK             0x000000ff
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_SHIFT            0
+#define BCHP_BSPI_CMD_AND_MODE_BYTE_bspi_cmd_byte_DEFAULT          0x0000000b
+
+/***************************************************************************
+ *BSPI_FLASH_UPPER_ADDR_BYTE - Bspi FLash upper address byte register
+ ***************************************************************************/
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_flash_upper_addr [31:24] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_MASK 0xff000000
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_SHIFT 24
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr_DEFAULT 0x00000000
+
+/* BSPI :: BSPI_FLASH_UPPER_ADDR_BYTE :: reserved0 [23:00] */
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_MASK        0x00ffffff
+#define BCHP_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE_reserved0_SHIFT       0
+
+/***************************************************************************
+ *BSPI_XOR_VALUE - BSPI FLASH XOR Value Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_VALUE :: bspi_xor_value [31:20] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_MASK               0xfff00000
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_SHIFT              20
+#define BCHP_BSPI_BSPI_XOR_VALUE_bspi_xor_value_DEFAULT            0x00000e00
+
+/* BSPI :: BSPI_XOR_VALUE :: reserved0 [19:00] */
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_MASK                    0x000fffff
+#define BCHP_BSPI_BSPI_XOR_VALUE_reserved0_SHIFT                   0
+
+/***************************************************************************
+ *BSPI_XOR_ENABLE - BSPI FLASH XOR Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_XOR_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_MASK                   0xfffffffe
+#define BCHP_BSPI_BSPI_XOR_ENABLE_reserved0_SHIFT                  1
+
+/* BSPI :: BSPI_XOR_ENABLE :: bspi_xor_enable [00:00] */
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_MASK             0x00000001
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_SHIFT            0
+#define BCHP_BSPI_BSPI_XOR_ENABLE_bspi_xor_enable_DEFAULT          0x00000001
+
+/***************************************************************************
+ *BSPI_PIO_MODE_ENABLE - BSPI Pin  Programmed IO Mode Enable Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: reserved0 [31:01] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_MASK              0xfffffffe
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_reserved0_SHIFT             1
+
+/* BSPI :: BSPI_PIO_MODE_ENABLE :: bspi_pio_mode [00:00] */
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_MASK          0x00000001
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_SHIFT         0
+#define BCHP_BSPI_BSPI_PIO_MODE_ENABLE_bspi_pio_mode_DEFAULT       0x00000000
+
+/***************************************************************************
+ *BSPI_PIO_IODIR - BSPI Pin  Programmed IO Mode Direction Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_IODIR :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_MASK                    0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_IODIR_reserved0_SHIFT                   3
+
+/* BSPI :: BSPI_PIO_IODIR :: bspi_pio_dir [02:00] */
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_IODIR_bspi_pio_dir_DEFAULT              0x00000003
+
+/***************************************************************************
+ *BSPI_PIO_DATA - BSPI Pin  Programmed IO Mode Data Register
+ ***************************************************************************/
+/* BSPI :: BSPI_PIO_DATA :: reserved0 [31:03] */
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_MASK                     0xfffffff8
+#define BCHP_BSPI_BSPI_PIO_DATA_reserved0_SHIFT                    3
+
+/* BSPI :: BSPI_PIO_DATA :: bspi_pio_data [02:00] */
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_MASK                 0x00000007
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_SHIFT                0
+#define BCHP_BSPI_BSPI_PIO_DATA_bspi_pio_data_DEFAULT              0x00000000
+
+#endif /* #ifndef BCHP_BSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_bspi_raf.h b/include/linux/brcmstb/7364a0/bchp_bspi_raf.h
new file mode 100644
index 000000000000..2c7b8e6c7a14
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_bspi_raf.h
@@ -0,0 +1,162 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:43 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_BSPI_RAF_H__
+#define BCHP_BSPI_RAF_H__
+
+/***************************************************************************
+ *BSPI_RAF - Public Linear Read BSPI Pipe Registers
+ ***************************************************************************/
+#define BCHP_BSPI_RAF_START_ADDR                 0x00443300 /* Physical Starting Address Location in Flash device */
+#define BCHP_BSPI_RAF_NUM_WORDS                  0x00443304 /* Number of Words to be fetched */
+#define BCHP_BSPI_RAF_CTRL                       0x00443308 /* RAF Session Control Register */
+#define BCHP_BSPI_RAF_FULLNESS                   0x0044330c /* Fullness indicator for the read ahead buffer */
+#define BCHP_BSPI_RAF_WATERMARK                  0x00443310 /* Watermark level in the read ahead buffer that triggers an interrupt */
+#define BCHP_BSPI_RAF_STATUS                     0x00443314 /* Linear Read Status Register */
+#define BCHP_BSPI_RAF_READ_DATA                  0x00443318 /* Read data from Raf-buffer */
+#define BCHP_BSPI_RAF_WORD_CNT                   0x0044331c /* Current number of words fetched from Flash */
+#define BCHP_BSPI_RAF_CURR_ADDR                  0x00443320 /* Current read address for the linear read session */
+
+/***************************************************************************
+ *START_ADDR - Physical Starting Address Location in Flash device
+ ***************************************************************************/
+/* BSPI_RAF :: START_ADDR :: START_ADDR [31:00] */
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_MASK                   0xffffffff
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_SHIFT                  0
+#define BCHP_BSPI_RAF_START_ADDR_START_ADDR_DEFAULT                0x00000000
+
+/***************************************************************************
+ *NUM_WORDS - Number of Words to be fetched
+ ***************************************************************************/
+/* BSPI_RAF :: NUM_WORDS :: NumWords [31:00] */
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_MASK                      0xffffffff
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_SHIFT                     0
+#define BCHP_BSPI_RAF_NUM_WORDS_NumWords_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *CTRL - RAF Session Control Register
+ ***************************************************************************/
+/* BSPI_RAF :: CTRL :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_CTRL_reserved0_MASK                          0xfffffffc
+#define BCHP_BSPI_RAF_CTRL_reserved0_SHIFT                         2
+
+/* BSPI_RAF :: CTRL :: CLEAR [01:01] */
+#define BCHP_BSPI_RAF_CTRL_CLEAR_MASK                              0x00000002
+#define BCHP_BSPI_RAF_CTRL_CLEAR_SHIFT                             1
+#define BCHP_BSPI_RAF_CTRL_CLEAR_DEFAULT                           0x00000000
+
+/* BSPI_RAF :: CTRL :: START [00:00] */
+#define BCHP_BSPI_RAF_CTRL_START_MASK                              0x00000001
+#define BCHP_BSPI_RAF_CTRL_START_SHIFT                             0
+#define BCHP_BSPI_RAF_CTRL_START_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *FULLNESS - Fullness indicator for the read ahead buffer
+ ***************************************************************************/
+/* BSPI_RAF :: FULLNESS :: reserved0 [31:07] */
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_MASK                      0xffffff80
+#define BCHP_BSPI_RAF_FULLNESS_reserved0_SHIFT                     7
+
+/* BSPI_RAF :: FULLNESS :: FULLNESS [06:00] */
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_MASK                       0x0000007f
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_SHIFT                      0
+#define BCHP_BSPI_RAF_FULLNESS_FULLNESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *WATERMARK - Watermark level in the read ahead buffer that triggers an interrupt
+ ***************************************************************************/
+/* BSPI_RAF :: WATERMARK :: reserved0 [31:02] */
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_MASK                     0xfffffffc
+#define BCHP_BSPI_RAF_WATERMARK_reserved0_SHIFT                    2
+
+/* BSPI_RAF :: WATERMARK :: FULLNESS_WATERMARK [01:00] */
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_MASK            0x00000003
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT           0
+#define BCHP_BSPI_RAF_WATERMARK_FULLNESS_WATERMARK_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STATUS - Linear Read Status Register
+ ***************************************************************************/
+/* BSPI_RAF :: STATUS :: reserved0 [31:03] */
+#define BCHP_BSPI_RAF_STATUS_reserved0_MASK                        0xfffffff8
+#define BCHP_BSPI_RAF_STATUS_reserved0_SHIFT                       3
+
+/* BSPI_RAF :: STATUS :: FIFO_FULL [02:02] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_MASK                        0x00000004
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_SHIFT                       2
+#define BCHP_BSPI_RAF_STATUS_FIFO_FULL_DEFAULT                     0x00000000
+
+/* BSPI_RAF :: STATUS :: FIFO_EMPTY [01:01] */
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_MASK                       0x00000002
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_SHIFT                      1
+#define BCHP_BSPI_RAF_STATUS_FIFO_EMPTY_DEFAULT                    0x00000001
+
+/* BSPI_RAF :: STATUS :: SESSION_BUSY [00:00] */
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_MASK                     0x00000001
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_SHIFT                    0
+#define BCHP_BSPI_RAF_STATUS_SESSION_BUSY_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *READ_DATA - Read data from Raf-buffer
+ ***************************************************************************/
+/* BSPI_RAF :: READ_DATA :: DATA [31:00] */
+#define BCHP_BSPI_RAF_READ_DATA_DATA_MASK                          0xffffffff
+#define BCHP_BSPI_RAF_READ_DATA_DATA_SHIFT                         0
+#define BCHP_BSPI_RAF_READ_DATA_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *WORD_CNT - Current number of words fetched from Flash
+ ***************************************************************************/
+/* BSPI_RAF :: WORD_CNT :: CURRENT_WORD_COUNT [31:00] */
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK             0xffffffff
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT            0
+#define BCHP_BSPI_RAF_WORD_CNT_CURRENT_WORD_COUNT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CURR_ADDR - Current read address for the linear read session
+ ***************************************************************************/
+/* BSPI_RAF :: CURR_ADDR :: CURRENT_ADDRESS [31:00] */
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK               0xffffffff
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT              0
+#define BCHP_BSPI_RAF_CURR_ADDR_CURRENT_ADDRESS_DEFAULT            0x00000000
+
+#endif /* #ifndef BCHP_BSPI_RAF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_common.h b/include/linux/brcmstb/7364a0/bchp_common.h
new file mode 100644
index 000000000000..4c5aa1eaa1c7
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_common.h
@@ -0,0 +1,4400 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Oct 22 03:11:48 2014
+ *                 Full Compile MD5 Checksum 08e1a7c8931083dc321aebee01be23fc
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              59bd60e4aff5fefc8861b8b125ee07f1
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_COMMON_H__
+#define BCHP_COMMON_H__
+
+/**
+ * m = memory, c = core, r = register, f = field, d = data.
+ */
+#if !defined(GET_FIELD) && !defined(SET_FIELD)
+#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
+#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
+
+#define GET_FIELD(m,c,r,f) \
+((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
+
+#define SET_FIELD(m,c,r,f,d) \
+((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
+
+#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
+#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
+#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
+
+#endif /* GET & SET */
+
+/***************************************************************************
+ *BCM7364_A0
+ ***************************************************************************/
+#define BCHP_PHYSICAL_OFFSET                               0xf0000000
+#define BCHP_REGISTER_START                                0x00100000 /* HEVD_OL_CPU_REGS_0 is first */
+#define BCHP_REGISTER_END                                  0x015e0000 /* MPM_FLASH_MEM is last */
+#define BCHP_REGISTER_SIZE                                 0x00538000 /* Number of registers */
+
+/****************************************************************************
+ * Core instance register start address.
+ ***************************************************************************/
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_START                  0x00100000
+#define BCHP_HEVD_OL_CPU_REGS_0_REG_END                    0x00100108
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_START                   0x00100400
+#define BCHP_HEVD_OL_CPU_DMA_0_REG_END                     0x00100440
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START                 0x00100800
+#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END                   0x00100ffc
+#define BCHP_HEVD_OL_SINT_0_REG_START                      0x00101000
+#define BCHP_HEVD_OL_SINT_0_REG_END                        0x00101028
+#define BCHP_HEVD_OL_LDST_0_REG_START                      0x00108000
+#define BCHP_HEVD_OL_LDST_0_REG_END                        0x0010fffc
+#define BCHP_REG_CABAC2BINS_0_REG_START                    0x00110b00
+#define BCHP_REG_CABAC2BINS_0_REG_END                      0x00110bfc
+#define BCHP_REG_CABAC2BINS2_0_REG_START                   0x00112400
+#define BCHP_REG_CABAC2BINS2_0_REG_END                     0x001127fc
+#define BCHP_HEVD_CABAC_0_REG_START                        0x00113000
+#define BCHP_HEVD_CABAC_0_REG_END                          0x0011307c
+#define BCHP_HEVD_OL_CTL_0_REG_START                       0x00114000
+#define BCHP_HEVD_OL_CTL_0_REG_END                         0x001151fc
+#define BCHP_DECODE_MAIN_0_REG_START                       0x00120100
+#define BCHP_DECODE_MAIN_0_REG_END                         0x001201fc
+#define BCHP_DECODE_MCOM_0_REG_START                       0x00120300
+#define BCHP_DECODE_MCOM_0_REG_END                         0x0012031c
+#define BCHP_DECODE_SPRE_0_REG_START                       0x00120320
+#define BCHP_DECODE_SPRE_0_REG_END                         0x0012033c
+#define BCHP_DECODE_WPRD_0_REG_START                       0x00120340
+#define BCHP_DECODE_WPRD_0_REG_END                         0x0012035c
+#define BCHP_DECODE_DQNT_0_REG_START                       0x00120400
+#define BCHP_DECODE_DQNT_0_REG_END                         0x0012045c
+#define BCHP_DECODE_DQNT_8X8_0_REG_START                   0x00120500
+#define BCHP_DECODE_DQNT_8X8_0_REG_END                     0x0012057c
+#define BCHP_DECODE_VP8_XFRM_0_REG_START                   0x00120600
+#define BCHP_DECODE_VP8_XFRM_0_REG_END                     0x0012060c
+#define BCHP_DECODE_VP6_DCP_0_REG_START                    0x00120620
+#define BCHP_DECODE_VP6_DCP_0_REG_END                      0x0012062c
+#define BCHP_DECODE_XFRM_0_REG_START                       0x00120700
+#define BCHP_DECODE_XFRM_0_REG_END                         0x0012071c
+#define BCHP_DECODE_DBLK_0_REG_START                       0x00120720
+#define BCHP_DECODE_DBLK_0_REG_END                         0x0012073c
+#define BCHP_DECODE_MB_0_REG_START                         0x00120740
+#define BCHP_DECODE_MB_0_REG_END                           0x0012075c
+#define BCHP_DECODE_SINT_0_REG_START                       0x00120c00
+#define BCHP_DECODE_SINT_0_REG_END                         0x00120dfc
+#define BCHP_DECODE_WPTBL_0_REG_START                      0x00123000
+#define BCHP_DECODE_WPTBL_0_REG_END                        0x001231fc
+#define BCHP_HEVD_BE_GLOBAL_0_REG_START                    0x00124000
+#define BCHP_HEVD_BE_GLOBAL_0_REG_END                      0x00124030
+#define BCHP_HEVD_IXFORM_0_REG_START                       0x00124100
+#define BCHP_HEVD_IXFORM_0_REG_END                         0x001241fc
+#define BCHP_HEVD_MCOMP_0_REG_START                        0x00124200
+#define BCHP_HEVD_MCOMP_0_REG_END                          0x001242fc
+#define BCHP_HEVD_SPRED_0_REG_START                        0x00124300
+#define BCHP_HEVD_SPRED_0_REG_END                          0x001243f0
+#define BCHP_HEVD_FILTER_0_REG_START                       0x00124400
+#define BCHP_HEVD_FILTER_0_REG_END                         0x001244fc
+#define BCHP_HEVD_OUTPUT_0_REG_START                       0x00124500
+#define BCHP_HEVD_OUTPUT_0_REG_END                         0x001245fc
+#define BCHP_HEVD_MARKER_0_REG_START                       0x00124f00
+#define BCHP_HEVD_MARKER_0_REG_END                         0x00124f7c
+#define BCHP_HEVD_FE_CTRL_0_REG_START                      0x00125000
+#define BCHP_HEVD_FE_CTRL_0_REG_END                        0x0012507c
+#define BCHP_HEVD_STRM_IN_0_REG_START                      0x00125100
+#define BCHP_HEVD_STRM_IN_0_REG_END                        0x00125118
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START                  0x00125200
+#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END                    0x00125230
+#define BCHP_HEVD_VECGEN_0_REG_START                       0x00125400
+#define BCHP_HEVD_VECGEN_0_REG_END                         0x0012568c
+#define BCHP_DCD_PIPE_CTL_0_REG_START                      0x00126000
+#define BCHP_DCD_PIPE_CTL_0_REG_END                        0x00126404
+#define BCHP_HEVD_PCACHE_0_REG_START                       0x00126800
+#define BCHP_HEVD_PCACHE_0_REG_END                         0x00126838
+#define BCHP_HEVD_PFRI_0_REG_START                         0x00126a00
+#define BCHP_HEVD_PFRI_0_REG_END                           0x00126b58
+#define BCHP_RVC_0_REG_START                               0x00126c00
+#define BCHP_RVC_0_REG_END                                 0x00126c20
+#define BCHP_ILS_REGS_0_REG_START                          0x00127000
+#define BCHP_ILS_REGS_0_REG_END                            0x001270fc
+#define BCHP_ILS_SCALE_ADDR_0_REG_START                    0x00127100
+#define BCHP_ILS_SCALE_ADDR_0_REG_END                      0x0012710c
+#define BCHP_ILS_SPSCALE_FILL_0_REG_START                  0x00127180
+#define BCHP_ILS_SPSCALE_FILL_0_REG_END                    0x00127184
+#define BCHP_ILS_MVSCALE_0_REG_START                       0x00127200
+#define BCHP_ILS_MVSCALE_0_REG_END                         0x0012738c
+#define BCHP_ILB_REGS_0_REG_START                          0x00127400
+#define BCHP_ILB_REGS_0_REG_END                            0x00127410
+#define BCHP_BLD_DECODE_MAIN_0_REG_START                   0x00128100
+#define BCHP_BLD_DECODE_MAIN_0_REG_END                     0x001281fc
+#define BCHP_BLD_DECODE_MCOM_0_REG_START                   0x00128300
+#define BCHP_BLD_DECODE_MCOM_0_REG_END                     0x0012831c
+#define BCHP_BLD_DECODE_SPRE_0_REG_START                   0x00128320
+#define BCHP_BLD_DECODE_SPRE_0_REG_END                     0x0012833c
+#define BCHP_BLD_DECODE_DQNT_0_REG_START                   0x00128400
+#define BCHP_BLD_DECODE_DQNT_0_REG_END                     0x0012845c
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_START               0x00128500
+#define BCHP_BLD_DECODE_DQNT_8X8_0_REG_END                 0x0012857c
+#define BCHP_BLD_DECODE_XFRM_0_REG_START                   0x00128700
+#define BCHP_BLD_DECODE_XFRM_0_REG_END                     0x0012871c
+#define BCHP_BLD_DECODE_DBLK_0_REG_START                   0x00128720
+#define BCHP_BLD_DECODE_DBLK_0_REG_END                     0x0012873c
+#define BCHP_BLD_DECODE_MB_0_REG_START                     0x00128740
+#define BCHP_BLD_DECODE_MB_0_REG_END                       0x0012875c
+#define BCHP_BLD_DECODE_SINT_0_REG_START                   0x00128c00
+#define BCHP_BLD_DECODE_SINT_0_REG_END                     0x00128dfc
+#define BCHP_BLD_DECODE_RVC_0_REG_START                    0x00128e00
+#define BCHP_BLD_DECODE_RVC_0_REG_END                      0x00128efc
+#define BCHP_BLD_BL_CPU_REGS_0_REG_START                   0x0012c000
+#define BCHP_BLD_BL_CPU_REGS_0_REG_END                     0x0012c108
+#define BCHP_BLD_BL_CPU_DMA_0_REG_START                    0x0012c400
+#define BCHP_BLD_BL_CPU_DMA_0_REG_END                      0x0012c440
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_START                  0x0012c800
+#define BCHP_BLD_BL_CPU_DEBUG_0_REG_END                    0x0012cffc
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_START                0x0012d000
+#define BCHP_BLD_DECODE_IP_SHIM_0_REG_END                  0x0012d090
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_START                  0x00130000
+#define BCHP_HEVD_IL_CPU_REGS_0_REG_END                    0x00130108
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_START                   0x00130400
+#define BCHP_HEVD_IL_CPU_DMA_0_REG_END                     0x00130440
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START                 0x00130800
+#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END                   0x00130ffc
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START                 0x00131000
+#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END                   0x0013100c
+#define BCHP_HEVD_IL_LDST_0_REG_START                      0x00134000
+#define BCHP_HEVD_IL_LDST_0_REG_END                        0x00137ffc
+#define BCHP_DECODE_MAIN_2_0_REG_START                     0x00140100
+#define BCHP_DECODE_MAIN_2_0_REG_END                       0x001401fc
+#define BCHP_DECODE_MCOM_2_0_REG_START                     0x00140300
+#define BCHP_DECODE_MCOM_2_0_REG_END                       0x0014031c
+#define BCHP_DECODE_SPRE_2_0_REG_START                     0x00140320
+#define BCHP_DECODE_SPRE_2_0_REG_END                       0x0014033c
+#define BCHP_DECODE_WPRD_2_0_REG_START                     0x00140340
+#define BCHP_DECODE_WPRD_2_0_REG_END                       0x0014035c
+#define BCHP_DECODE_DQNT_2_0_REG_START                     0x00140400
+#define BCHP_DECODE_DQNT_2_0_REG_END                       0x0014045c
+#define BCHP_DECODE_DQNT_8X8_2_0_REG_START                 0x00140500
+#define BCHP_DECODE_DQNT_8X8_2_0_REG_END                   0x0014057c
+#define BCHP_DECODE_VP8_XFRM_2_0_REG_START                 0x00140600
+#define BCHP_DECODE_VP8_XFRM_2_0_REG_END                   0x0014060c
+#define BCHP_DECODE_VP6_DCP_2_0_REG_START                  0x00140620
+#define BCHP_DECODE_VP6_DCP_2_0_REG_END                    0x0014062c
+#define BCHP_DECODE_XFRM_2_0_REG_START                     0x00140700
+#define BCHP_DECODE_XFRM_2_0_REG_END                       0x0014071c
+#define BCHP_DECODE_DBLK_2_0_REG_START                     0x00140720
+#define BCHP_DECODE_DBLK_2_0_REG_END                       0x0014073c
+#define BCHP_DECODE_MB_2_0_REG_START                       0x00140740
+#define BCHP_DECODE_MB_2_0_REG_END                         0x0014075c
+#define BCHP_DECODE_SINT_2_0_REG_START                     0x00140c00
+#define BCHP_DECODE_SINT_2_0_REG_END                       0x00140dfc
+#define BCHP_DECODE_WPTBL_2_0_REG_START                    0x00143000
+#define BCHP_DECODE_WPTBL_2_0_REG_END                      0x001431fc
+#define BCHP_HEVD_BE_GLOBAL_2_0_REG_START                  0x00144000
+#define BCHP_HEVD_BE_GLOBAL_2_0_REG_END                    0x00144030
+#define BCHP_HEVD_IXFORM_2_0_REG_START                     0x00144100
+#define BCHP_HEVD_IXFORM_2_0_REG_END                       0x001441fc
+#define BCHP_HEVD_MCOMP_2_0_REG_START                      0x00144200
+#define BCHP_HEVD_MCOMP_2_0_REG_END                        0x001442fc
+#define BCHP_HEVD_SPRED_2_0_REG_START                      0x00144300
+#define BCHP_HEVD_SPRED_2_0_REG_END                        0x001443f0
+#define BCHP_HEVD_FILTER_2_0_REG_START                     0x00144400
+#define BCHP_HEVD_FILTER_2_0_REG_END                       0x001444fc
+#define BCHP_HEVD_OUTPUT_2_0_REG_START                     0x00144500
+#define BCHP_HEVD_OUTPUT_2_0_REG_END                       0x001445fc
+#define BCHP_HEVD_MARKER_2_0_REG_START                     0x00144f00
+#define BCHP_HEVD_MARKER_2_0_REG_END                       0x00144f7c
+#define BCHP_HEVD_FE_CTRL_2_0_REG_START                    0x00145000
+#define BCHP_HEVD_FE_CTRL_2_0_REG_END                      0x0014507c
+#define BCHP_HEVD_STRM_IN_2_0_REG_START                    0x00145100
+#define BCHP_HEVD_STRM_IN_2_0_REG_END                      0x00145118
+#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_START                0x00145200
+#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_END                  0x00145230
+#define BCHP_HEVD_VECGEN_2_0_REG_START                     0x00145400
+#define BCHP_HEVD_VECGEN_2_0_REG_END                       0x0014568c
+#define BCHP_DCD_PIPE_CTL_2_0_REG_START                    0x00146000
+#define BCHP_DCD_PIPE_CTL_2_0_REG_END                      0x00146404
+#define BCHP_HEVD_PCACHE_2_0_REG_START                     0x00146800
+#define BCHP_HEVD_PCACHE_2_0_REG_END                       0x00146838
+#define BCHP_HEVD_PFRI_2_0_REG_START                       0x00146a00
+#define BCHP_HEVD_PFRI_2_0_REG_END                         0x00146b58
+#define BCHP_RVC_2_0_REG_START                             0x00146c00
+#define BCHP_RVC_2_0_REG_END                               0x00146c20
+#define BCHP_ILS_REGS_2_0_REG_START                        0x00147000
+#define BCHP_ILS_REGS_2_0_REG_END                          0x001470fc
+#define BCHP_ILS_SCALE_ADDR_2_0_REG_START                  0x00147100
+#define BCHP_ILS_SCALE_ADDR_2_0_REG_END                    0x0014710c
+#define BCHP_ILS_SPSCALE_FILL_2_0_REG_START                0x00147180
+#define BCHP_ILS_SPSCALE_FILL_2_0_REG_END                  0x00147184
+#define BCHP_ILS_MVSCALE_2_0_REG_START                     0x00147200
+#define BCHP_ILS_MVSCALE_2_0_REG_END                       0x0014738c
+#define BCHP_ILB_REGS_2_0_REG_START                        0x00147400
+#define BCHP_ILB_REGS_2_0_REG_END                          0x00147410
+#define BCHP_BLD_DECODE_MAIN_2_0_REG_START                 0x00148100
+#define BCHP_BLD_DECODE_MAIN_2_0_REG_END                   0x001481fc
+#define BCHP_BLD_DECODE_MCOM_2_0_REG_START                 0x00148300
+#define BCHP_BLD_DECODE_MCOM_2_0_REG_END                   0x0014831c
+#define BCHP_BLD_DECODE_SPRE_2_0_REG_START                 0x00148320
+#define BCHP_BLD_DECODE_SPRE_2_0_REG_END                   0x0014833c
+#define BCHP_BLD_DECODE_DQNT_2_0_REG_START                 0x00148400
+#define BCHP_BLD_DECODE_DQNT_2_0_REG_END                   0x0014845c
+#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_START             0x00148500
+#define BCHP_BLD_DECODE_DQNT_8X8_2_0_REG_END               0x0014857c
+#define BCHP_BLD_DECODE_XFRM_2_0_REG_START                 0x00148700
+#define BCHP_BLD_DECODE_XFRM_2_0_REG_END                   0x0014871c
+#define BCHP_BLD_DECODE_DBLK_2_0_REG_START                 0x00148720
+#define BCHP_BLD_DECODE_DBLK_2_0_REG_END                   0x0014873c
+#define BCHP_BLD_DECODE_MB_2_0_REG_START                   0x00148740
+#define BCHP_BLD_DECODE_MB_2_0_REG_END                     0x0014875c
+#define BCHP_BLD_DECODE_SINT_2_0_REG_START                 0x00148c00
+#define BCHP_BLD_DECODE_SINT_2_0_REG_END                   0x00148dfc
+#define BCHP_BLD_DECODE_RVC_2_0_REG_START                  0x00148e00
+#define BCHP_BLD_DECODE_RVC_2_0_REG_END                    0x00148efc
+#define BCHP_BLD_BL_CPU_REGS_2_0_REG_START                 0x0014c000
+#define BCHP_BLD_BL_CPU_REGS_2_0_REG_END                   0x0014c108
+#define BCHP_BLD_BL_CPU_DMA_2_0_REG_START                  0x0014c400
+#define BCHP_BLD_BL_CPU_DMA_2_0_REG_END                    0x0014c440
+#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_START                0x0014c800
+#define BCHP_BLD_BL_CPU_DEBUG_2_0_REG_END                  0x0014cffc
+#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_START              0x0014d000
+#define BCHP_BLD_DECODE_IP_SHIM_2_0_REG_END                0x0014d090
+#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_START                0x00150000
+#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_END                  0x00150108
+#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_START                 0x00150400
+#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_END                   0x00150440
+#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_START               0x00150800
+#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_END                 0x00150ffc
+#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_START               0x00151000
+#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_END                 0x0015100c
+#define BCHP_HEVD_IL_LDST_2_0_REG_START                    0x00154000
+#define BCHP_HEVD_IL_LDST_2_0_REG_END                      0x00157ffc
+#define BCHP_HVD_INTR2_0_REG_START                         0x00180000
+#define BCHP_HVD_INTR2_0_REG_END                           0x0018002c
+#define BCHP_HVD_RGR_0_REG_START                           0x00180400
+#define BCHP_HVD_RGR_0_REG_END                             0x00180410
+#define BCHP_VICH_0_REG_START                              0x001a0000
+#define BCHP_VICH_0_REG_END                                0x001a008b
+#define BCHP_SCPU_LOCALRAM_REG_START                       0x00300000
+#define BCHP_SCPU_LOCALRAM_REG_END                         0x0030fffc
+#define BCHP_SCPU_GLOBALRAM_REG_START                      0x00310000
+#define BCHP_SCPU_GLOBALRAM_REG_END                        0x003103fc
+#define BCHP_SCPU_MISB_BRIDGE_REG_START                    0x00310400
+#define BCHP_SCPU_MISB_BRIDGE_REG_END                      0x00310450
+#define BCHP_SCPU_RGR_BRIDGE_REG_START                     0x00310460
+#define BCHP_SCPU_RGR_BRIDGE_REG_END                       0x00310470
+#define BCHP_SCPU_INTR1_REG_START                          0x00310480
+#define BCHP_SCPU_INTR1_REG_END                            0x00310498
+#define BCHP_INTERNAL_INTR2_REG_START                      0x003104c0
+#define BCHP_INTERNAL_INTR2_REG_END                        0x003104ec
+#define BCHP_BSP_IPI_INTR2_REG_START                       0x00310500
+#define BCHP_BSP_IPI_INTR2_REG_END                         0x0031052c
+#define BCHP_SCPU_HW_INTR2_REG_START                       0x00310540
+#define BCHP_SCPU_HW_INTR2_REG_END                         0x0031056c
+#define BCHP_CPU_IPI_INTR2_REG_START                       0x00311000
+#define BCHP_CPU_IPI_INTR2_REG_END                         0x0031102c
+#define BCHP_SCPU_HOST_INTR2_REG_START                     0x00311040
+#define BCHP_SCPU_HOST_INTR2_REG_END                       0x0031106c
+#define BCHP_SCPU_TOP_CTRL_REG_START                       0x00312000
+#define BCHP_SCPU_TOP_CTRL_REG_END                         0x00312008
+#define BCHP_SCPU_HDMI_CTRL_REG_START                      0x00312080
+#define BCHP_SCPU_HDMI_CTRL_REG_END                        0x00312084
+#define BCHP_SCPU_SEC_TIME_REG_START                       0x00312100
+#define BCHP_SCPU_SEC_TIME_REG_END                         0x00312114
+#define BCHP_SAGE_UART_REG_START                           0x00312200
+#define BCHP_SAGE_UART_REG_END                             0x0031221c
+#define BCHP_SCPU_PM_REG_START                             0x00312980
+#define BCHP_SCPU_PM_REG_END                               0x00312988
+#define BCHP_SCPU_TIMER_REG_START                          0x00312e80
+#define BCHP_SCPU_TIMER_REG_END                            0x00312ebc
+#define BCHP_BSP_CMDBUF_REG_START                          0x0032c800
+#define BCHP_BSP_CMDBUF_REG_END                            0x0032cffc
+#define BCHP_BSP_GLB_CONTROL_REG_START                     0x0032d000
+#define BCHP_BSP_GLB_CONTROL_REG_END                       0x0032d0b0
+#define BCHP_BSP_PKL_REG_START                             0x0032d300
+#define BCHP_BSP_PKL_REG_END                               0x0032d37c
+#define BCHP_BSP_CONTROL_INTR2_REG_START                   0x0032d800
+#define BCHP_BSP_CONTROL_INTR2_REG_END                     0x0032d82c
+#define BCHP_BSP_VISTA_GENACC_REG_START                    0x0032d900
+#define BCHP_BSP_VISTA_GENACC_REG_END                      0x0032d9fc
+#define BCHP_BSP_OTP_SCRATCH_REG_START                     0x0032e000
+#define BCHP_BSP_OTP_SCRATCH_REG_END                       0x0032fffc
+#define BCHP_XPT_SECURITY_REG_START                        0x00360000
+#define BCHP_XPT_SECURITY_REG_END                          0x0037fffc
+#define BCHP_SECTOP_GRB_REG_START                          0x00380000
+#define BCHP_SECTOP_GRB_REG_END                            0x0038000c
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START             0x00380080
+#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END               0x003800ac
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START             0x00380100
+#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END               0x0038012c
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START             0x00380180
+#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END               0x003801ac
+#define BCHP_XPT_SECURITY_NS_REG_START                     0x00380200
+#define BCHP_XPT_SECURITY_NS_REG_END                       0x003802c8
+#define BCHP_SUN_GISB_ARB_REG_START                        0x00400000
+#define BCHP_SUN_GISB_ARB_REG_END                          0x004007fc
+#define BCHP_SUN_GR_REG_START                              0x00401000
+#define BCHP_SUN_GR_REG_END                                0x0040100c
+#define BCHP_SSP_RG_REG_START                              0x00401200
+#define BCHP_SSP_RG_REG_END                                0x0040120c
+#define BCHP_SUN_RG_REG_START                              0x00401400
+#define BCHP_SUN_RG_REG_END                                0x0040140c
+#define BCHP_RF4CE_GR_REG_START                            0x00401600
+#define BCHP_RF4CE_GR_REG_END                              0x0040160c
+#define BCHP_TPCAP_REG_START                               0x00401800
+#define BCHP_TPCAP_REG_END                                 0x0040189c
+#define BCHP_SUN_L2_REG_START                              0x00403000
+#define BCHP_SUN_L2_REG_END                                0x00403044
+#define BCHP_SUN_TOP_CTRL_REG_START                        0x00404000
+#define BCHP_SUN_TOP_CTRL_REG_END                          0x0040452c
+#define BCHP_BBSI_RG_REG_START                             0x00405c00
+#define BCHP_BBSI_RG_REG_END                               0x00405c0c
+#define BCHP_MPM_TOP_GR_REG_START                          0x00406000
+#define BCHP_MPM_TOP_GR_REG_END                            0x0040600c
+#define BCHP_PWM_REG_START                                 0x00408000
+#define BCHP_PWM_REG_END                                   0x00408024
+#define BCHP_PWMB_REG_START                                0x00409000
+#define BCHP_PWMB_REG_END                                  0x00409024
+#define BCHP_IRB_REG_START                                 0x0040a000
+#define BCHP_IRB_REG_END                                   0x0040a138
+#define BCHP_BSCA_REG_START                                0x0040a200
+#define BCHP_BSCA_REG_END                                  0x0040a254
+#define BCHP_BSCD_REG_START                                0x0040a280
+#define BCHP_BSCD_REG_END                                  0x0040a2d4
+#define BCHP_GIO_REG_START                                 0x0040a300
+#define BCHP_GIO_REG_END                                   0x0040a39c
+#define BCHP_PM_REG_START                                  0x0040a400
+#define BCHP_PM_REG_END                                    0x0040a408
+#define BCHP_TIMER_REG_START                               0x0040a440
+#define BCHP_TIMER_REG_END                                 0x0040a47c
+#define BCHP_IRQ0_REG_START                                0x0040a480
+#define BCHP_IRQ0_REG_END                                  0x0040a484
+#define BCHP_IRQ1_REG_START                                0x0040a4c0
+#define BCHP_IRQ1_REG_END                                  0x0040a4c4
+#define BCHP_CTK_REG_START                                 0x0040a800
+#define BCHP_CTK_REG_END                                   0x0040a978
+#define BCHP_TMON_REG_START                                0x0040a980
+#define BCHP_TMON_REG_END                                  0x0040a9d4
+#define BCHP_UPG_AUX_INTR2_REG_START                       0x0040aa00
+#define BCHP_UPG_AUX_INTR2_REG_END                         0x0040aa2c
+#define BCHP_MCIF_REG_START                                0x0040aa40
+#define BCHP_MCIF_REG_END                                  0x0040aa68
+#define BCHP_MCIF_INTR2_REG_START                          0x0040aa80
+#define BCHP_MCIF_INTR2_REG_END                            0x0040aac4
+#define BCHP_SCA_REG_START                                 0x0040ac00
+#define BCHP_SCA_REG_END                                   0x0040acfc
+#define BCHP_SCB_REG_START                                 0x0040ad00
+#define BCHP_SCB_REG_END                                   0x0040adfc
+#define BCHP_SCIRQ0_REG_START                              0x0040ae00
+#define BCHP_SCIRQ0_REG_END                                0x0040ae04
+#define BCHP_SCIRQ1_REG_START                              0x0040ae40
+#define BCHP_SCIRQ1_REG_END                                0x0040ae44
+#define BCHP_SCIRQ_SCPU_REG_START                          0x0040ae80
+#define BCHP_SCIRQ_SCPU_REG_END                            0x0040ae84
+#define BCHP_UARTA_REG_START                               0x0040b000
+#define BCHP_UARTA_REG_END                                 0x0040b01c
+#define BCHP_UARTB_REG_START                               0x0040b040
+#define BCHP_UARTB_REG_END                                 0x0040b05c
+#define BCHP_UARTC_REG_START                               0x0040b080
+#define BCHP_UARTC_REG_END                                 0x0040b09c
+#define BCHP_UPG_UART_DMA_REG_START                        0x0040b0c0
+#define BCHP_UPG_UART_DMA_REG_END                          0x0040b0f0
+#define BCHP_AON_CTRL_REG_START                            0x00410000
+#define BCHP_AON_CTRL_REG_END                              0x004103fc
+#define BCHP_AON_L2_REG_START                              0x00410600
+#define BCHP_AON_L2_REG_END                                0x0041062c
+#define BCHP_AON_PM_L2_REG_START                           0x00410640
+#define BCHP_AON_PM_L2_REG_END                             0x0041066c
+#define BCHP_AON_PIN_CTRL_REG_START                        0x00410700
+#define BCHP_AON_PIN_CTRL_REG_END                          0x00410714
+#define BCHP_AON_HDMI_TX_REG_START                         0x00410800
+#define BCHP_AON_HDMI_TX_REG_END                           0x004108ac
+#define BCHP_AON_HDMI_RX_REG_START                         0x00411200
+#define BCHP_AON_HDMI_RX_REG_END                           0x004112d4
+#define BCHP_CNTControlBase_REG_START                      0x00412000
+#define BCHP_CNTControlBase_REG_END                        0x00412ffc
+#define BCHP_CNTReadBase_REG_START                         0x00414000
+#define BCHP_CNTReadBase_REG_END                           0x00414ffc
+#define BCHP_MSPI_REG_START                                0x00416000
+#define BCHP_MSPI_REG_END                                  0x0041617c
+#define BCHP_LDK_REG_START                                 0x00417000
+#define BCHP_LDK_REG_END                                   0x0041703c
+#define BCHP_PM_AON_REG_START                              0x00417040
+#define BCHP_PM_AON_REG_END                                0x00417048
+#define BCHP_ICAP_REG_START                                0x00417080
+#define BCHP_ICAP_REG_END                                  0x004170bc
+#define BCHP_KBD1_REG_START                                0x004170c0
+#define BCHP_KBD1_REG_END                                  0x004170fc
+#define BCHP_KBD2_REG_START                                0x00417100
+#define BCHP_KBD2_REG_END                                  0x0041713c
+#define BCHP_KBD3_REG_START                                0x00417140
+#define BCHP_KBD3_REG_END                                  0x0041717c
+#define BCHP_BSCB_REG_START                                0x00417180
+#define BCHP_BSCB_REG_END                                  0x004171d4
+#define BCHP_BSCC_REG_START                                0x00417200
+#define BCHP_BSCC_REG_END                                  0x00417254
+#define BCHP_IRQ0_AON_REG_START                            0x00417280
+#define BCHP_IRQ0_AON_REG_END                              0x00417284
+#define BCHP_IRQ1_AON_REG_START                            0x004172c0
+#define BCHP_IRQ1_AON_REG_END                              0x004172c4
+#define BCHP_GIO_AON_REG_START                             0x00417300
+#define BCHP_GIO_AON_REG_END                               0x0041733c
+#define BCHP_UPG_AUX_AON_INTR2_REG_START                   0x00417400
+#define BCHP_UPG_AUX_AON_INTR2_REG_END                     0x0041742c
+#define BCHP_WKTMR_REG_START                               0x00417480
+#define BCHP_WKTMR_REG_END                                 0x00417490
+#define BCHP_BICAP_REG_START                               0x004174c0
+#define BCHP_BICAP_REG_END                                 0x004174f8
+#define BCHP_SYS_GISB_ARB_SEC_REG_START                    0x0041e000
+#define BCHP_SYS_GISB_ARB_SEC_REG_END                      0x0041e7fc
+#define BCHP_SYS_TOP_CTRL_SEC_REG_START                    0x0041e800
+#define BCHP_SYS_TOP_CTRL_SEC_REG_END                      0x0041e808
+#define BCHP_AON_CTRL_SECURE_REG_START                     0x0041e900
+#define BCHP_AON_CTRL_SECURE_REG_END                       0x0041e97c
+#define BCHP_BOOTSRAM_SECURE_REG_START                     0x00420000
+#define BCHP_BOOTSRAM_SECURE_REG_END                       0x0042fffc
+#define BCHP_ITCH0_REG_START                               0x00430000
+#define BCHP_ITCH0_REG_END                                 0x00430000
+#define BCHP_HIF_SECURE_CTRL_REG_START                     0x00430400
+#define BCHP_HIF_SECURE_CTRL_REG_END                       0x00430400
+#define BCHP_HIF_SECURE_BSPI_REG_START                     0x00430500
+#define BCHP_HIF_SECURE_BSPI_REG_END                       0x00430500
+#define BCHP_HIF_SECURE_LR_SPI_REG_START                   0x00430600
+#define BCHP_HIF_SECURE_LR_SPI_REG_END                     0x00430600
+#define BCHP_NAND_SECURE_REG_START                         0x00430800
+#define BCHP_NAND_SECURE_REG_END                           0x00430800
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START       0x00430c00
+#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END         0x00430c00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START               0x00430e00
+#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END                 0x00430ffc
+#define BCHP_HIF_CONTINUATION_SECURE_REG_START             0x00431000
+#define BCHP_HIF_CONTINUATION_SECURE_REG_END               0x00431004
+#define BCHP_SDIO_0_HOST_REG_START                         0x00440000
+#define BCHP_SDIO_0_HOST_REG_END                           0x004400fc
+#define BCHP_SDIO_0_CFG_REG_START                          0x00440100
+#define BCHP_SDIO_0_CFG_REG_END                            0x004401fc
+#define BCHP_SDIO_1_HOST_REG_START                         0x00440200
+#define BCHP_SDIO_1_HOST_REG_END                           0x004402fc
+#define BCHP_SDIO_1_CFG_REG_START                          0x00440300
+#define BCHP_SDIO_1_CFG_REG_END                            0x004403fc
+#define BCHP_SDIO_1_BOOT_REG_START                         0x00440400
+#define BCHP_SDIO_1_BOOT_REG_END                           0x0044043c
+#define BCHP_EBI_REG_START                                 0x00440800
+#define BCHP_EBI_REG_END                                   0x00440bfc
+#define BCHP_HIF_INTR2_REG_START                           0x00441000
+#define BCHP_HIF_INTR2_REG_END                             0x0044102c
+#define BCHP_IPI0_INTR2_REG_START                          0x00441100
+#define BCHP_IPI0_INTR2_REG_END                            0x0044112c
+#define BCHP_IPI1_INTR2_REG_START                          0x00441200
+#define BCHP_IPI1_INTR2_REG_END                            0x0044122c
+#define BCHP_HIF_CPU_INTR1_REG_START                       0x00441500
+#define BCHP_HIF_CPU_INTR1_REG_END                         0x0044153c
+#define BCHP_PCI_PCIE_INTR1_REG_START                      0x00441600
+#define BCHP_PCI_PCIE_INTR1_REG_END                        0x0044163c
+#define BCHP_HIF_RGR2_REG_START                            0x00441700
+#define BCHP_HIF_RGR2_REG_END                              0x00441710
+#define BCHP_HIF_SPI_INTR2_REG_START                       0x00441a00
+#define BCHP_HIF_SPI_INTR2_REG_END                         0x00441a2c
+#define BCHP_HIF_TOP_CTRL_REG_START                        0x00442000
+#define BCHP_HIF_TOP_CTRL_REG_END                          0x0044203c
+#define BCHP_HIF_CPUBIUARCH_REG_START                      0x00442200
+#define BCHP_HIF_CPUBIUARCH_REG_END                        0x004423fc
+#define BCHP_HIF_CPUBIUCTRL_REG_START                      0x00442400
+#define BCHP_HIF_CPUBIUCTRL_REG_END                        0x004427fc
+#define BCHP_NAND_REG_START                                0x00442800
+#define BCHP_NAND_REG_END                                  0x00442dfc
+#define BCHP_FLASH_DMA_REG_START                           0x00443000
+#define BCHP_FLASH_DMA_REG_END                             0x00443028
+#define BCHP_BSPI_REG_START                                0x00443200
+#define BCHP_BSPI_REG_END                                  0x0044324c
+#define BCHP_BSPI_RAF_REG_START                            0x00443300
+#define BCHP_BSPI_RAF_REG_END                              0x00443320
+#define BCHP_HIF_MSPI_REG_START                            0x00443400
+#define BCHP_HIF_MSPI_REG_END                              0x00443584
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START          0x00443600
+#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END            0x00443604
+#define BCHP_BOOTSRAM_TM_REG_START                         0x00450000
+#define BCHP_BOOTSRAM_TM_REG_END                           0x0045fffc
+#define BCHP_HIF_CONTINUATION_REG_START                    0x00462000
+#define BCHP_HIF_CONTINUATION_REG_END                      0x0046200c
+#define BCHP_RFM_SYSCLK_REG_START                          0x0046c000
+#define BCHP_RFM_SYSCLK_REG_END                            0x0046c124
+#define BCHP_RFM_CLK27_REG_START                           0x0046c000
+#define BCHP_RFM_CLK27_REG_END                             0x0046c470
+#define BCHP_RFM_L2_REG_START                              0x0046cc00
+#define BCHP_RFM_L2_REG_END                                0x0046cc2c
+#define BCHP_RFM_GRB_REG_START                             0x0046d000
+#define BCHP_RFM_GRB_REG_END                               0x0046d00c
+#define BCHP_USB_CAPS_REG_START                            0x00480000
+#define BCHP_USB_CAPS_REG_END                              0x0048002c
+#define BCHP_USB_GR_BRIDGE_REG_START                       0x00480100
+#define BCHP_USB_GR_BRIDGE_REG_END                         0x0048010c
+#define BCHP_USB_INTR2_REG_START                           0x00480180
+#define BCHP_USB_INTR2_REG_END                             0x004801ac
+#define BCHP_USB_CTRL_REG_START                            0x00480200
+#define BCHP_USB_CTRL_REG_END                              0x004802fc
+#define BCHP_USB_EHCI_REG_START                            0x00480300
+#define BCHP_USB_EHCI_REG_END                              0x004803a4
+#define BCHP_USB_OHCI_REG_START                            0x00480400
+#define BCHP_USB_OHCI_REG_END                              0x00480454
+#define BCHP_USB_EHCI1_REG_START                           0x00480500
+#define BCHP_USB_EHCI1_REG_END                             0x004805a4
+#define BCHP_USB_OHCI1_REG_START                           0x00480600
+#define BCHP_USB_OHCI1_REG_END                             0x00480654
+#define BCHP_USB_XHCI_REG_START                            0x00481000
+#define BCHP_USB_XHCI_REG_END                              0x004818c4
+#define BCHP_USB_XHCI_EC_REG_START                         0x00481940
+#define BCHP_USB_XHCI_EC_REG_END                           0x00481fc0
+#define BCHP_AVS_CPU_PROG_MEM_REG_START                    0x004c0000
+#define BCHP_AVS_CPU_PROG_MEM_REG_END                      0x004c2ffc
+#define BCHP_AVS_CPU_DATA_MEM_REG_START                    0x004c4000
+#define BCHP_AVS_CPU_DATA_MEM_REG_END                      0x004c4bfc
+#define BCHP_AVS_CPU_CORE_REGS_REG_START                   0x004c8000
+#define BCHP_AVS_CPU_CORE_REGS_REG_END                     0x004c80fc
+#define BCHP_AVS_CPU_AUX_REGS_REG_START                    0x004ca000
+#define BCHP_AVS_CPU_AUX_REGS_REG_END                      0x004cb058
+#define BCHP_AVS_UART_REG_START                            0x004d0000
+#define BCHP_AVS_UART_REG_END                              0x004d0ffc
+#define BCHP_AVS_CPU_L2_REG_START                          0x004d1100
+#define BCHP_AVS_CPU_L2_REG_END                            0x004d112c
+#define BCHP_AVS_HOST_L2_REG_START                         0x004d1200
+#define BCHP_AVS_HOST_L2_REG_END                           0x004d1244
+#define BCHP_AVS_CPU_CTRL_REG_START                        0x004d1300
+#define BCHP_AVS_CPU_CTRL_REG_END                          0x004d1330
+#define BCHP_AVS_BSTI_REG_START                            0x004d1400
+#define BCHP_AVS_BSTI_REG_END                              0x004d1404
+#define BCHP_AVS_TMON_REG_START                            0x004d1500
+#define BCHP_AVS_TMON_REG_END                              0x004d1524
+#define BCHP_AVS_TOP_CTRL_REG_START                        0x004d1800
+#define BCHP_AVS_TOP_CTRL_REG_END                          0x004d1914
+#define BCHP_AVS_HW_MNTR_REG_START                         0x004d2000
+#define BCHP_AVS_HW_MNTR_REG_END                           0x004d20c8
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START                 0x004d2100
+#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END                   0x004d2124
+#define BCHP_AVS_RO_REGISTERS_0_REG_START                  0x004d2200
+#define BCHP_AVS_RO_REGISTERS_0_REG_END                    0x004d22e0
+#define BCHP_AVS_RO_REGISTERS_1_REG_START                  0x004d2800
+#define BCHP_AVS_RO_REGISTERS_1_REG_END                    0x004d2804
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START                0x004d2d00
+#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END                  0x004d2dfc
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START                0x004d2e00
+#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END                  0x004d2efc
+#define BCHP_AVS_WDOG_REG_START                            0x004d3000
+#define BCHP_AVS_WDOG_REG_END                              0x004d3ffc
+#define BCHP_AVS_PMB_S_000_REG_START                       0x004d4000
+#define BCHP_AVS_PMB_S_000_REG_END                         0x004d4024
+#define BCHP_AVS_PMB_S_001_REG_START                       0x004d4040
+#define BCHP_AVS_PMB_S_001_REG_END                         0x004d4064
+#define BCHP_AVS_PMB_S_002_REG_START                       0x004d4080
+#define BCHP_AVS_PMB_S_002_REG_END                         0x004d40a4
+#define BCHP_AVS_PMB_S_003_REG_START                       0x004d40c0
+#define BCHP_AVS_PMB_S_003_REG_END                         0x004d40e4
+#define BCHP_AVS_PMB_S_004_REG_START                       0x004d4100
+#define BCHP_AVS_PMB_S_004_REG_END                         0x004d4124
+#define BCHP_AVS_PMB_S_005_REG_START                       0x004d4140
+#define BCHP_AVS_PMB_S_005_REG_END                         0x004d4164
+#define BCHP_AVS_PMB_S_006_REG_START                       0x004d4180
+#define BCHP_AVS_PMB_S_006_REG_END                         0x004d41a4
+#define BCHP_AVS_PMB_S_007_REG_START                       0x004d41c0
+#define BCHP_AVS_PMB_S_007_REG_END                         0x004d41e4
+#define BCHP_AVS_PMB_S_008_REG_START                       0x004d4200
+#define BCHP_AVS_PMB_S_008_REG_END                         0x004d4224
+#define BCHP_AVS_PMB_S_009_REG_START                       0x004d4240
+#define BCHP_AVS_PMB_S_009_REG_END                         0x004d4264
+#define BCHP_AVS_PMB_S_010_REG_START                       0x004d4280
+#define BCHP_AVS_PMB_S_010_REG_END                         0x004d42a4
+#define BCHP_AVS_PMB_S_011_REG_START                       0x004d42c0
+#define BCHP_AVS_PMB_S_011_REG_END                         0x004d42e4
+#define BCHP_AVS_PMB_S_012_REG_START                       0x004d4300
+#define BCHP_AVS_PMB_S_012_REG_END                         0x004d4324
+#define BCHP_AVS_PMB_S_013_REG_START                       0x004d4340
+#define BCHP_AVS_PMB_S_013_REG_END                         0x004d4364
+#define BCHP_AVS_PMB_S_014_REG_START                       0x004d4380
+#define BCHP_AVS_PMB_S_014_REG_END                         0x004d43a4
+#define BCHP_AVS_PMB_S_015_REG_START                       0x004d43c0
+#define BCHP_AVS_PMB_S_015_REG_END                         0x004d43e4
+#define BCHP_AVS_PMB_S_016_REG_START                       0x004d4400
+#define BCHP_AVS_PMB_S_016_REG_END                         0x004d4424
+#define BCHP_AVS_PMB_S_017_REG_START                       0x004d4440
+#define BCHP_AVS_PMB_S_017_REG_END                         0x004d4464
+#define BCHP_AVS_PMB_S_018_REG_START                       0x004d4480
+#define BCHP_AVS_PMB_S_018_REG_END                         0x004d44a4
+#define BCHP_AVS_PMB_S_019_REG_START                       0x004d44c0
+#define BCHP_AVS_PMB_S_019_REG_END                         0x004d44e4
+#define BCHP_AVS_PMB_S_020_REG_START                       0x004d4500
+#define BCHP_AVS_PMB_S_020_REG_END                         0x004d4524
+#define BCHP_AVS_PMB_S_021_REG_START                       0x004d4540
+#define BCHP_AVS_PMB_S_021_REG_END                         0x004d4564
+#define BCHP_AVS_PMB_S_022_REG_START                       0x004d4580
+#define BCHP_AVS_PMB_S_022_REG_END                         0x004d45a4
+#define BCHP_AVS_PMB_S_023_REG_START                       0x004d45c0
+#define BCHP_AVS_PMB_S_023_REG_END                         0x004d45e4
+#define BCHP_AVS_PMB_S_024_REG_START                       0x004d4600
+#define BCHP_AVS_PMB_S_024_REG_END                         0x004d4624
+#define BCHP_AVS_PMB_REGISTERS_REG_START                   0x004d6000
+#define BCHP_AVS_PMB_REGISTERS_REG_END                     0x004d6008
+#define BCHP_CLKGEN_REG_START                              0x004e0000
+#define BCHP_CLKGEN_REG_END                                0x004e06b8
+#define BCHP_VCXO_0_RM_REG_START                           0x004e2800
+#define BCHP_VCXO_0_RM_REG_END                             0x004e2838
+#define BCHP_VCXO_1_RM_REG_START                           0x004e2880
+#define BCHP_VCXO_1_RM_REG_END                             0x004e28b8
+#define BCHP_CLKGEN_GR_REG_START                           0x004e3000
+#define BCHP_CLKGEN_GR_REG_END                             0x004e300c
+#define BCHP_CLKGEN_INTR2_REG_START                        0x004e4800
+#define BCHP_CLKGEN_INTR2_REG_END                          0x004e4844
+#define BCHP_AVS_RANGE_BLOCKER_REG_START                   0x004e5000
+#define BCHP_AVS_RANGE_BLOCKER_REG_END                     0x004e5058
+#define BCHP_PROD_OTP_GRB_REG_START                        0x004e6000
+#define BCHP_PROD_OTP_GRB_REG_END                          0x004e600c
+#define BCHP_JTAG_OTP_REG_START                            0x004e6100
+#define BCHP_JTAG_OTP_REG_END                              0x004e615c
+#define BCHP_MFD_0_REG_START                               0x00600000
+#define BCHP_MFD_0_REG_END                                 0x006001fc
+#define BCHP_MFD_1_REG_START                               0x00600400
+#define BCHP_MFD_1_REG_END                                 0x006005fc
+#define BCHP_VFD_0_REG_START                               0x00600800
+#define BCHP_VFD_0_REG_END                                 0x006009fc
+#define BCHP_VFD_1_REG_START                               0x00600c00
+#define BCHP_VFD_1_REG_END                                 0x00600dfc
+#define BCHP_RDC_REG_START                                 0x00601000
+#define BCHP_RDC_REG_END                                   0x00601cfc
+#define BCHP_BVNF_INTR2_0_REG_START                        0x00602000
+#define BCHP_BVNF_INTR2_0_REG_END                          0x0060202c
+#define BCHP_BVNF_INTR2_1_REG_START                        0x00602100
+#define BCHP_BVNF_INTR2_1_REG_END                          0x0060212c
+#define BCHP_BVNF_INTR2_3_REG_START                        0x00602300
+#define BCHP_BVNF_INTR2_3_REG_END                          0x0060232c
+#define BCHP_BVNF_INTR2_5_REG_START                        0x00602500
+#define BCHP_BVNF_INTR2_5_REG_END                          0x0060252c
+#define BCHP_BVNF_INTR2_6_REG_START                        0x00602600
+#define BCHP_BVNF_INTR2_6_REG_END                          0x0060262c
+#define BCHP_BVNF_INTR2_7_REG_START                        0x00602700
+#define BCHP_BVNF_INTR2_7_REG_END                          0x0060272c
+#define BCHP_BVNF_INTR2_9_REG_START                        0x00602900
+#define BCHP_BVNF_INTR2_9_REG_END                          0x0060292c
+#define BCHP_BVNF_INTR2_15_REG_START                       0x00602f00
+#define BCHP_BVNF_INTR2_15_REG_END                         0x00602f2c
+#define BCHP_BVNF_INTR2_16_REG_START                       0x00603000
+#define BCHP_BVNF_INTR2_16_REG_END                         0x0060302c
+#define BCHP_BVNF_INTR2_18_REG_START                       0x00603200
+#define BCHP_BVNF_INTR2_18_REG_END                         0x0060322c
+#define BCHP_FMISC_REG_START                               0x00604000
+#define BCHP_FMISC_REG_END                                 0x0060401c
+#define BCHP_SCL_0_REG_START                               0x00620000
+#define BCHP_SCL_0_REG_END                                 0x006203fc
+#define BCHP_SCL_1_REG_START                               0x00620400
+#define BCHP_SCL_1_REG_END                                 0x006207fc
+#define BCHP_VNET_F_REG_START                              0x00620800
+#define BCHP_VNET_F_REG_END                                0x006209fc
+#define BCHP_VNET_B_REG_START                              0x00620a00
+#define BCHP_VNET_B_REG_END                                0x00620bfc
+#define BCHP_MMISC_REG_START                               0x00621000
+#define BCHP_MMISC_REG_END                                 0x0062101c
+#define BCHP_LBOX_0_REG_START                              0x00622000
+#define BCHP_LBOX_0_REG_END                                0x00622070
+#define BCHP_DNR_0_REG_START                               0x00622200
+#define BCHP_DNR_0_REG_END                                 0x006222a4
+#define BCHP_DNR_1_REG_START                               0x00622400
+#define BCHP_DNR_1_REG_END                                 0x006224a4
+#define BCHP_XSRC_0_REG_START                              0x00622800
+#define BCHP_XSRC_0_REG_END                                0x00622888
+#define BCHP_BVNM_INTR2_0_REG_START                        0x00622c00
+#define BCHP_BVNM_INTR2_0_REG_END                          0x00622c2c
+#define BCHP_DMISC_REG_START                               0x00640000
+#define BCHP_DMISC_REG_END                                 0x0064001c
+#define BCHP_MVP_TOP_0_REG_START                           0x00650000
+#define BCHP_MVP_TOP_0_REG_END                             0x00650038
+#define BCHP_SIOB_0_REG_START                              0x00650200
+#define BCHP_SIOB_0_REG_END                                0x006502fc
+#define BCHP_HSCL_0_REG_START                              0x00650400
+#define BCHP_HSCL_0_REG_END                                0x006507fc
+#define BCHP_MDI_TOP_0_REG_START                           0x00652000
+#define BCHP_MDI_TOP_0_REG_END                             0x006520fc
+#define BCHP_MDI_PPB_0_REG_START                           0x00652800
+#define BCHP_MDI_PPB_0_REG_END                             0x00652bfc
+#define BCHP_MDI_FCN_0_REG_START                           0x00652c00
+#define BCHP_MDI_FCN_0_REG_END                             0x00652ffc
+#define BCHP_CAP_0_REG_START                               0x00680000
+#define BCHP_CAP_0_REG_END                                 0x0068010c
+#define BCHP_CAP_1_REG_START                               0x00680200
+#define BCHP_CAP_1_REG_END                                 0x0068030c
+#define BCHP_GFD_0_REG_START                               0x00680400
+#define BCHP_GFD_0_REG_END                                 0x0068062c
+#define BCHP_GFD_1_REG_START                               0x00680800
+#define BCHP_GFD_1_REG_END                                 0x00680a2c
+#define BCHP_CMP_0_REG_START                               0x00681000
+#define BCHP_CMP_0_REG_END                                 0x006814c0
+#define BCHP_CMP_1_REG_START                               0x00681800
+#define BCHP_CMP_1_REG_END                                 0x00681a60
+#define BCHP_TNT_CMP_0_V0_REG_START                        0x00682000
+#define BCHP_TNT_CMP_0_V0_REG_END                          0x006820a4
+#define BCHP_MASK_0_REG_START                              0x00682400
+#define BCHP_MASK_0_REG_END                                0x00682420
+#define BCHP_PEP_CMP_0_V0_REG_START                        0x00684000
+#define BCHP_PEP_CMP_0_V0_REG_END                          0x00685284
+#define BCHP_BVNB_INTR2_REG_START                          0x00686000
+#define BCHP_BVNB_INTR2_REG_END                            0x0068602c
+#define BCHP_BMISC_REG_START                               0x00686400
+#define BCHP_BMISC_REG_END                                 0x0068641c
+#define BCHP_MISC_REG_START                                0x006a0000
+#define BCHP_MISC_REG_END                                  0x006a0098
+#define BCHP_IT_0_REG_START                                0x006a1000
+#define BCHP_IT_0_REG_END                                  0x006a17fc
+#define BCHP_IT_1_REG_START                                0x006a2000
+#define BCHP_IT_1_REG_END                                  0x006a27fc
+#define BCHP_VF_0_REG_START                                0x006a3000
+#define BCHP_VF_0_REG_END                                  0x006a3134
+#define BCHP_SECAM_0_REG_START                             0x006a3200
+#define BCHP_SECAM_0_REG_END                               0x006a3214
+#define BCHP_SM_0_REG_START                                0x006a3280
+#define BCHP_SM_0_REG_END                                  0x006a32ac
+#define BCHP_SDSRC_0_REG_START                             0x006a3300
+#define BCHP_SDSRC_0_REG_END                               0x006a330c
+#define BCHP_HDSRC_0_REG_START                             0x006a3320
+#define BCHP_HDSRC_0_REG_END                               0x006a333c
+#define BCHP_CSC_0_REG_START                               0x006a3380
+#define BCHP_CSC_0_REG_END                                 0x006a33b0
+#define BCHP_RM_0_REG_START                                0x006a3400
+#define BCHP_RM_0_REG_END                                  0x006a3430
+#define BCHP_RM_1_REG_START                                0x006a3440
+#define BCHP_RM_1_REG_END                                  0x006a3470
+#define BCHP_ANA_DEBUG_0_REG_START                         0x006a3500
+#define BCHP_ANA_DEBUG_0_REG_END                           0x006a3544
+#define BCHP_GRPD_0_REG_START                              0x006a3600
+#define BCHP_GRPD_0_REG_END                                0x006a36ec
+#define BCHP_DVI_MISC_0_REG_START                          0x006a3700
+#define BCHP_DVI_MISC_0_REG_END                            0x006a3700
+#define BCHP_DVI_DTG_0_REG_START                           0x006a4000
+#define BCHP_DVI_DTG_0_REG_END                             0x006a4488
+#define BCHP_DVI_DTG_RM_0_REG_START                        0x006a4800
+#define BCHP_DVI_DTG_RM_0_REG_END                          0x006a4830
+#define BCHP_DVI_CSC_0_REG_START                           0x006a4900
+#define BCHP_DVI_CSC_0_REG_END                             0x006a4930
+#define BCHP_DVI_FC_0_REG_START                            0x006a4a00
+#define BCHP_DVI_FC_0_REG_END                              0x006a4a04
+#define BCHP_DVI_DVF_0_REG_START                           0x006a4b00
+#define BCHP_DVI_DVF_0_REG_END                             0x006a4b18
+#define BCHP_DVI_DEBUG_0_REG_START                         0x006a4c00
+#define BCHP_DVI_DEBUG_0_REG_END                           0x006a4c44
+#define BCHP_ITU656_DTG_0_REG_START                        0x006a5000
+#define BCHP_ITU656_DTG_0_REG_END                          0x006a5488
+#define BCHP_ITU656_CSC_0_REG_START                        0x006a5600
+#define BCHP_ITU656_CSC_0_REG_END                          0x006a5630
+#define BCHP_ITU656_DVF_0_REG_START                        0x006a5700
+#define BCHP_ITU656_DVF_0_REG_END                          0x006a5718
+#define BCHP_ITU656_0_REG_START                            0x006a5800
+#define BCHP_ITU656_0_REG_END                              0x006a5820
+#define BCHP_VEC_CFG_REG_START                             0x006a5c00
+#define BCHP_VEC_CFG_REG_END                               0x006a5d2c
+#define BCHP_VIDEO_ENC_INTR2_REG_START                     0x006a6000
+#define BCHP_VIDEO_ENC_INTR2_REG_END                       0x006a602c
+#define BCHP_VIDEO_ENC_TPG_0_REG_START                     0x006a6200
+#define BCHP_VIDEO_ENC_TPG_0_REG_END                       0x006a6320
+#define BCHP_VIDEO_ENC_STG_0_REG_START                     0x006a6400
+#define BCHP_VIDEO_ENC_STG_0_REG_END                       0x006a645c
+#define BCHP_DSCL_0_REG_START                              0x006a6800
+#define BCHP_DSCL_0_REG_END                                0x006a6bfc
+#define BCHP_VIDEO_ENC_DECIM_0_REG_START                   0x006a7000
+#define BCHP_VIDEO_ENC_DECIM_0_REG_END                     0x006a7008
+#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_START                 0x006a7100
+#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_END                   0x006a712c
+#define BCHP_DVP_TVG_0_REG_START                           0x006a7200
+#define BCHP_DVP_TVG_0_REG_END                             0x006a7288
+#define BCHP_VBI_ENC_REG_START                             0x006a8000
+#define BCHP_VBI_ENC_REG_END                               0x006a8074
+#define BCHP_CCE_0_REG_START                               0x006a8400
+#define BCHP_CCE_0_REG_END                                 0x006a8458
+#define BCHP_WSE_0_REG_START                               0x006a8500
+#define BCHP_WSE_0_REG_END                                 0x006a8514
+#define BCHP_CGMSAE_0_REG_START                            0x006a8600
+#define BCHP_CGMSAE_0_REG_END                              0x006a8658
+#define BCHP_TTE_0_REG_START                               0x006a8700
+#define BCHP_TTE_0_REG_END                                 0x006a8728
+#define BCHP_GSE_0_REG_START                               0x006a8800
+#define BCHP_GSE_0_REG_END                                 0x006a8880
+#define BCHP_AMOLE_0_REG_START                             0x006a8900
+#define BCHP_AMOLE_0_REG_END                               0x006a898c
+#define BCHP_CCE_ANCIL_0_REG_START                         0x006a8a00
+#define BCHP_CCE_ANCIL_0_REG_END                           0x006a8a54
+#define BCHP_WSE_ANCIL_0_REG_START                         0x006a8b00
+#define BCHP_WSE_ANCIL_0_REG_END                           0x006a8b0c
+#define BCHP_TTE_ANCIL_0_REG_START                         0x006a8c00
+#define BCHP_TTE_ANCIL_0_REG_END                           0x006a8c28
+#define BCHP_GSE_ANCIL_0_REG_START                         0x006a8d00
+#define BCHP_GSE_ANCIL_0_REG_END                           0x006a8d80
+#define BCHP_AMOLE_ANCIL_0_REG_START                       0x006a8e00
+#define BCHP_AMOLE_ANCIL_0_REG_END                         0x006a8e8c
+#define BCHP_ANCI656_ANCIL_0_REG_START                     0x006a8f00
+#define BCHP_ANCI656_ANCIL_0_REG_END                       0x006a8f24
+#define BCHP_VICE2_VIP_0_0_REG_START                       0x006af000
+#define BCHP_VICE2_VIP_0_0_REG_END                         0x006af224
+#define BCHP_VICE2_VIP_TOP_REG_START                       0x006af800
+#define BCHP_VICE2_VIP_TOP_REG_END                         0x006af80c
+#define BCHP_DVP_HR_REG_START                              0x006b0000
+#define BCHP_DVP_HR_REG_END                                0x006b03fc
+#define BCHP_DVP_HR_INTR2_REG_START                        0x006b0400
+#define BCHP_DVP_HR_INTR2_REG_END                          0x006b042c
+#define BCHP_DVP_HR_KEY_RAM_REG_START                      0x006b0600
+#define BCHP_DVP_HR_KEY_RAM_REG_END                        0x006b0614
+#define BCHP_HDMI_RX_FE_SHARED_REG_START                   0x006b0800
+#define BCHP_HDMI_RX_FE_SHARED_REG_END                     0x006b090c
+#define BCHP_HDMI_RX_SHARED_REG_START                      0x006b0c00
+#define BCHP_HDMI_RX_SHARED_REG_END                        0x006b0c28
+#define BCHP_HDMI_RX_FE_0_REG_START                        0x006b1000
+#define BCHP_HDMI_RX_FE_0_REG_END                          0x006b11fc
+#define BCHP_HDMI_RX_EQ_0_REG_START                        0x006b1200
+#define BCHP_HDMI_RX_EQ_0_REG_END                          0x006b13fc
+#define BCHP_HDMI_RX_0_REG_START                           0x006b2000
+#define BCHP_HDMI_RX_0_REG_END                             0x006b27fc
+#define BCHP_HDCP2_RX_0_REG_START                          0x006b2800
+#define BCHP_HDCP2_RX_0_REG_END                            0x006b29fc
+#define BCHP_HDMI_RX_INTR2_0_REG_START                     0x006b2a00
+#define BCHP_HDMI_RX_INTR2_0_REG_END                       0x006b2a2c
+#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_START               0x006b2a40
+#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_END                 0x006b2a6c
+#define BCHP_HDMI_RX_HAE_INTR2_0_REG_START                 0x006b2a80
+#define BCHP_HDMI_RX_HAE_INTR2_0_REG_END                   0x006b2aac
+#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_START                0x006b2ac0
+#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_END                  0x006b2ad4
+#define BCHP_HD_DVI_0_REG_START                            0x006b4000
+#define BCHP_HD_DVI_0_REG_END                              0x006b427c
+#define BCHP_DVP_HR_TMR_REG_START                          0x006b4cc0
+#define BCHP_DVP_HR_TMR_REG_END                            0x006b4cfc
+#define BCHP_DVP_HT_REG_START                              0x006b8000
+#define BCHP_DVP_HT_REG_END                                0x006b8114
+#define BCHP_HDMI_REG_START                                0x006b8800
+#define BCHP_HDMI_REG_END                                  0x006b8afc
+#define BCHP_HDMI_TX_AUTO_I2C_REG_START                    0x006b8b00
+#define BCHP_HDMI_TX_AUTO_I2C_REG_END                      0x006b8dfc
+#define BCHP_HDMI_TX_PHY_REG_START                         0x006b8e00
+#define BCHP_HDMI_TX_PHY_REG_END                           0x006b8e7c
+#define BCHP_HDMI_RM_REG_START                             0x006b8e80
+#define BCHP_HDMI_RM_REG_END                               0x006b8eb8
+#define BCHP_HDMI_TX_INTR2_REG_START                       0x006b8f00
+#define BCHP_HDMI_TX_INTR2_REG_END                         0x006b8f2c
+#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_START                0x006b8f80
+#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_END                  0x006b8fac
+#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_START                0x006b9000
+#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_END                  0x006b902c
+#define BCHP_HDMI_TX_HAE_INTR2_0_REG_START                 0x006b9080
+#define BCHP_HDMI_TX_HAE_INTR2_0_REG_END                   0x006b90ac
+#define BCHP_HDMI_RAM_REG_START                            0x006b9100
+#define BCHP_HDMI_RAM_REG_END                              0x006b92fc
+#define BCHP_BVN_RGR_REG_START                             0x006c0000
+#define BCHP_BVN_RGR_REG_END                               0x006c0010
+#define BCHP_MEMC_GEN_0_REG_START                          0x00900000
+#define BCHP_MEMC_GEN_0_REG_END                            0x009007fc
+#define BCHP_MEMC_EDIS_0_0_REG_START                       0x00900800
+#define BCHP_MEMC_EDIS_0_0_REG_END                         0x009008fc
+#define BCHP_MEMC_EDIS_0_1_REG_START                       0x00900a00
+#define BCHP_MEMC_EDIS_0_1_REG_END                         0x00900afc
+#define BCHP_MEMC_ARC_0_REG_START                          0x00900c00
+#define BCHP_MEMC_ARC_0_REG_END                            0x00900f74
+#define BCHP_MEMC_ARB_0_REG_START                          0x00901000
+#define BCHP_MEMC_ARB_0_REG_END                            0x009014cc
+#define BCHP_MEMC_DDR_0_REG_START                          0x00902000
+#define BCHP_MEMC_DDR_0_REG_END                            0x009027fc
+#define BCHP_MEMC_L2_0_0_REG_START                         0x00903000
+#define BCHP_MEMC_L2_0_0_REG_END                           0x00903044
+#define BCHP_MEMC_L2_0_1_REG_START                         0x00903200
+#define BCHP_MEMC_L2_0_1_REG_END                           0x00903244
+#define BCHP_MEMC_L2_0_2_REG_START                         0x00903400
+#define BCHP_MEMC_L2_0_2_REG_END                           0x00903444
+#define BCHP_MEMC_TRACELOG_0_0_REG_START                   0x00903800
+#define BCHP_MEMC_TRACELOG_0_0_REG_END                     0x009039fc
+#define BCHP_MEMC_RGRB_0_REG_START                         0x00904000
+#define BCHP_MEMC_RGRB_0_REG_END                           0x00904010
+#define BCHP_MEMC_MISC_0_REG_START                         0x00905000
+#define BCHP_MEMC_MISC_0_REG_END                           0x00905010
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START            0x00906000
+#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END              0x00906218
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START             0x00906400
+#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END               0x00906518
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START             0x00906600
+#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END               0x00906718
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START             0x00906800
+#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END               0x00906918
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START             0x00906a00
+#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END               0x00906b18
+#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START                0x00906c00
+#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END                  0x00906d18
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START                 0x00908000
+#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END                   0x009080e0
+#define BCHP_MEMC_SENTINEL_0_0_REG_START                   0x00940000
+#define BCHP_MEMC_SENTINEL_0_0_REG_END                     0x0097fffc
+#define BCHP_S_MEMC_0_REG_START                            0x00980000
+#define BCHP_S_MEMC_0_REG_END                              0x00980780
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
+#define BCHP_XPT_BUS_IF_REG_START                          0x00a00080
+#define BCHP_XPT_BUS_IF_REG_END                            0x00a000fc
+#define BCHP_XPT_XMEMIF_REG_START                          0x00a00100
+#define BCHP_XPT_XMEMIF_REG_END                            0x00a001fc
+#define BCHP_XPT_PMU_REG_START                             0x00a00200
+#define BCHP_XPT_PMU_REG_END                               0x00a00218
+#define BCHP_XPT_GR_REG_START                              0x00a00300
+#define BCHP_XPT_GR_REG_END                                0x00a0030c
+#define BCHP_XPT_RMX0_IO_REG_START                         0x00a00400
+#define BCHP_XPT_RMX0_IO_REG_END                           0x00a00420
+#define BCHP_XPT_RMX1_IO_REG_START                         0x00a00500
+#define BCHP_XPT_RMX1_IO_REG_END                           0x00a00520
+#define BCHP_XPT_WAKEUP_REG_START                          0x00a01000
+#define BCHP_XPT_WAKEUP_REG_END                            0x00a01fbc
+#define BCHP_XPT_DPCR0_REG_START                           0x00a02000
+#define BCHP_XPT_DPCR0_REG_END                             0x00a02078
+#define BCHP_XPT_DPCR1_REG_START                           0x00a02080
+#define BCHP_XPT_DPCR1_REG_END                             0x00a020f8
+#define BCHP_XPT_DPCR2_REG_START                           0x00a02100
+#define BCHP_XPT_DPCR2_REG_END                             0x00a02178
+#define BCHP_XPT_DPCR3_REG_START                           0x00a02180
+#define BCHP_XPT_DPCR3_REG_END                             0x00a021f8
+#define BCHP_XPT_DPCR4_REG_START                           0x00a02200
+#define BCHP_XPT_DPCR4_REG_END                             0x00a02278
+#define BCHP_XPT_DPCR5_REG_START                           0x00a02280
+#define BCHP_XPT_DPCR5_REG_END                             0x00a022f8
+#define BCHP_XPT_DPCR6_REG_START                           0x00a02300
+#define BCHP_XPT_DPCR6_REG_END                             0x00a02378
+#define BCHP_XPT_DPCR7_REG_START                           0x00a02380
+#define BCHP_XPT_DPCR7_REG_END                             0x00a023f8
+#define BCHP_XPT_DPCR8_REG_START                           0x00a02400
+#define BCHP_XPT_DPCR8_REG_END                             0x00a02478
+#define BCHP_XPT_DPCR9_REG_START                           0x00a02480
+#define BCHP_XPT_DPCR9_REG_END                             0x00a024f8
+#define BCHP_XPT_DPCR10_REG_START                          0x00a02500
+#define BCHP_XPT_DPCR10_REG_END                            0x00a02578
+#define BCHP_XPT_DPCR11_REG_START                          0x00a02580
+#define BCHP_XPT_DPCR11_REG_END                            0x00a025f8
+#define BCHP_XPT_DPCR12_REG_START                          0x00a02600
+#define BCHP_XPT_DPCR12_REG_END                            0x00a02678
+#define BCHP_XPT_DPCR13_REG_START                          0x00a02680
+#define BCHP_XPT_DPCR13_REG_END                            0x00a026f8
+#define BCHP_XPT_DPCR_PP_REG_START                         0x00a02800
+#define BCHP_XPT_DPCR_PP_REG_END                           0x00a02804
+#define BCHP_XPT_PSUB_REG_START                            0x00a02a00
+#define BCHP_XPT_PSUB_REG_END                              0x00a02b88
+#define BCHP_XPT_MPOD_REG_START                            0x00a02c00
+#define BCHP_XPT_MPOD_REG_END                              0x00a02c20
+#define BCHP_XPT_RMX0_REG_START                            0x00a02d00
+#define BCHP_XPT_RMX0_REG_END                              0x00a02d10
+#define BCHP_XPT_RMX1_REG_START                            0x00a02e00
+#define BCHP_XPT_RMX1_REG_END                              0x00a02e10
+#define BCHP_XPT_RSBUFF_REG_START                          0x00a04000
+#define BCHP_XPT_RSBUFF_REG_END                            0x00a054fc
+#define BCHP_XPT_XCBUFF_REG_START                          0x00a06000
+#define BCHP_XPT_XCBUFF_REG_END                            0x00a07e9c
+#define BCHP_XPT_PCROFFSET_REG_START                       0x00a08000
+#define BCHP_XPT_PCROFFSET_REG_END                         0x00a0aafc
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START           0x00a0c000
+#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END             0x00a0ea04
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START            0x00a0f000
+#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END              0x00a0f9fc
+#define BCHP_XPT_TSIO_INTR_L2_REG_START                    0x00a0fc00
+#define BCHP_XPT_TSIO_INTR_L2_REG_END                      0x00a0fc2c
+#define BCHP_XPT_FULL_PID_PARSER_REG_START                 0x00a10000
+#define BCHP_XPT_FULL_PID_PARSER_REG_END                   0x00a14050
+#define BCHP_XPT_FE_REG_START                              0x00a20000
+#define BCHP_XPT_FE_REG_END                                0x00a25ffc
+#define BCHP_XPT_MSG_REG_START                             0x00a30000
+#define BCHP_XPT_MSG_REG_END                               0x00a3ca14
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb1c
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb20
+#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END  0x00a3fb3c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb5c
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb60
+#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END  0x00a3fb7c
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START             0x00a3fb80
+#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END               0x00a3fbac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START   0x00a3fc00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END     0x00a3fc2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START   0x00a3fc40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END     0x00a3fc6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START   0x00a3fc80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END     0x00a3fcac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START  0x00a3fcc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END    0x00a3fcec
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x00a3fd00
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END   0x00a3fd2c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x00a3fd40
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END   0x00a3fd6c
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x00a3fd80
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END   0x00a3fdac
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x00a3fdc0
+#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END   0x00a3fdec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START      0x00a3fe00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END        0x00a3fe2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START      0x00a3fe40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END        0x00a3fe6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START      0x00a3fe80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END        0x00a3feac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START     0x00a3fec0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END       0x00a3feec
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START    0x00a3ff00
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END      0x00a3ff2c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START    0x00a3ff40
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END      0x00a3ff6c
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START    0x00a3ff80
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END      0x00a3ffac
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START    0x00a3ffc0
+#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END      0x00a3ffec
+#define BCHP_XPT_RAVE_REG_START                            0x00a40000
+#define BCHP_XPT_RAVE_REG_END                              0x00a4e178
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START        0x00a4f000
+#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END          0x00a4f01c
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START        0x00a4f020
+#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END          0x00a4f03c
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START               0x00a4f040
+#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END                 0x00a4f06c
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START  0x00a4f080
+#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END    0x00a4f0ac
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START  0x00a4f0c0
+#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END    0x00a4f0ec
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f100
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END   0x00a4f12c
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f140
+#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END   0x00a4f16c
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START  0x00a4f180
+#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END    0x00a4f1ac
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START  0x00a4f1c0
+#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END    0x00a4f1ec
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START   0x00a4f200
+#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END     0x00a4f22c
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START   0x00a4f240
+#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END     0x00a4f26c
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f280
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f2ac
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f2c0
+#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f2ec
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f300
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f32c
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f340
+#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f36c
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START     0x00a4f380
+#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END       0x00a4f3ac
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START     0x00a4f3c0
+#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END       0x00a4f3ec
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START   0x00a4f400
+#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END     0x00a4f42c
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START   0x00a4f440
+#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END     0x00a4f46c
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f480
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f4ac
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f4c0
+#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f4ec
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f500
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f52c
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f540
+#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f56c
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f580
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f5ac
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f5c0
+#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f5ec
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f600
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f62c
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f640
+#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f66c
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f680
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f6ac
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f6c0
+#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f6ec
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f700
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f72c
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f740
+#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f76c
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x00a4f780
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x00a4f7ac
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x00a4f7c0
+#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x00a4f7ec
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x00a4f800
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x00a4f82c
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x00a4f840
+#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x00a4f86c
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START       0x00a4ff80
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END         0x00a4ffac
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START      0x00a4ffc0
+#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END        0x00a4ffec
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
+#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END   0x00a6001c
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
+#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END   0x00a6003c
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START   0x00a60040
+#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END     0x00a6006c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
+#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START    0x00a600c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END      0x00a600ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START    0x00a60140
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END      0x00a6016c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
+#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
+#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
+#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
+#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
+#define BCHP_XPT_MEMDMA_MCPB_REG_START                     0x00a60800
+#define BCHP_XPT_MEMDMA_MCPB_REG_END                       0x00a60b98
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START                 0x00a60c00
+#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END                   0x00a60d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START                 0x00a60e00
+#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END                   0x00a60f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START                 0x00a61000
+#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END                   0x00a6115c
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START                 0x00a61200
+#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END                   0x00a6135c
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START                 0x00a61400
+#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END                   0x00a6155c
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START                 0x00a61600
+#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END                   0x00a6175c
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START                 0x00a61800
+#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END                   0x00a6195c
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START                 0x00a61a00
+#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END                   0x00a61b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START                 0x00a61c00
+#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END                   0x00a61d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START                 0x00a61e00
+#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END                   0x00a61f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START                0x00a62000
+#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END                  0x00a6215c
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START                0x00a62200
+#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END                  0x00a6235c
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START                0x00a62400
+#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END                  0x00a6255c
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START                0x00a62600
+#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END                  0x00a6275c
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START                0x00a62800
+#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END                  0x00a6295c
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START                0x00a62a00
+#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END                  0x00a62b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START                0x00a62c00
+#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END                  0x00a62d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START                0x00a62e00
+#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END                  0x00a62f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START                0x00a63000
+#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END                  0x00a6315c
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START                0x00a63200
+#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END                  0x00a6335c
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START                0x00a63400
+#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END                  0x00a6355c
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START                0x00a63600
+#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END                  0x00a6375c
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START                0x00a63800
+#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END                  0x00a6395c
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START                0x00a63a00
+#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END                  0x00a63b5c
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START                0x00a63c00
+#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END                  0x00a63d5c
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START                0x00a63e00
+#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END                  0x00a63f5c
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START                0x00a64000
+#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END                  0x00a6415c
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START                0x00a64200
+#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END                  0x00a6435c
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START                0x00a64400
+#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END                  0x00a6455c
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START                0x00a64600
+#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END                  0x00a6475c
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START                0x00a64800
+#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END                  0x00a6495c
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START                0x00a64a00
+#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END                  0x00a64b5c
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START        0x00a68000
+#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END          0x00a6801c
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START        0x00a68020
+#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END          0x00a6803c
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START       0x00a68040
+#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END         0x00a6805c
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START                0x00a68100
+#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END                  0x00a68144
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START           0x00a68200
+#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END             0x00a68244
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START          0x00a68300
+#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END            0x00a68344
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START                 0x00a68400
+#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END                   0x00a68444
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_START                 0x00a68500
+#define BCHP_XPT_WDMA_PM_CONTROL_REG_END                   0x00a68510
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_START                 0x00a68600
+#define BCHP_XPT_WDMA_PM_RESULTS_REG_END                   0x00a68658
+#define BCHP_XPT_WDMA_REGS_REG_START                       0x00a69000
+#define BCHP_XPT_WDMA_REGS_REG_END                         0x00a69068
+#define BCHP_XPT_WDMA_CH0_REG_START                        0x00a6a000
+#define BCHP_XPT_WDMA_CH0_REG_END                          0x00a6a0fc
+#define BCHP_XPT_WDMA_CH1_REG_START                        0x00a6a100
+#define BCHP_XPT_WDMA_CH1_REG_END                          0x00a6a1fc
+#define BCHP_XPT_WDMA_CH2_REG_START                        0x00a6a200
+#define BCHP_XPT_WDMA_CH2_REG_END                          0x00a6a2fc
+#define BCHP_XPT_WDMA_CH3_REG_START                        0x00a6a300
+#define BCHP_XPT_WDMA_CH3_REG_END                          0x00a6a3fc
+#define BCHP_XPT_WDMA_CH4_REG_START                        0x00a6a400
+#define BCHP_XPT_WDMA_CH4_REG_END                          0x00a6a4fc
+#define BCHP_XPT_WDMA_CH5_REG_START                        0x00a6a500
+#define BCHP_XPT_WDMA_CH5_REG_END                          0x00a6a5fc
+#define BCHP_XPT_WDMA_CH6_REG_START                        0x00a6a600
+#define BCHP_XPT_WDMA_CH6_REG_END                          0x00a6a6fc
+#define BCHP_XPT_WDMA_CH7_REG_START                        0x00a6a700
+#define BCHP_XPT_WDMA_CH7_REG_END                          0x00a6a7fc
+#define BCHP_XPT_WDMA_CH8_REG_START                        0x00a6a800
+#define BCHP_XPT_WDMA_CH8_REG_END                          0x00a6a8fc
+#define BCHP_XPT_WDMA_CH9_REG_START                        0x00a6a900
+#define BCHP_XPT_WDMA_CH9_REG_END                          0x00a6a9fc
+#define BCHP_XPT_WDMA_CH10_REG_START                       0x00a6aa00
+#define BCHP_XPT_WDMA_CH10_REG_END                         0x00a6aafc
+#define BCHP_XPT_WDMA_CH11_REG_START                       0x00a6ab00
+#define BCHP_XPT_WDMA_CH11_REG_END                         0x00a6abfc
+#define BCHP_XPT_WDMA_CH12_REG_START                       0x00a6ac00
+#define BCHP_XPT_WDMA_CH12_REG_END                         0x00a6acfc
+#define BCHP_XPT_WDMA_CH13_REG_START                       0x00a6ad00
+#define BCHP_XPT_WDMA_CH13_REG_END                         0x00a6adfc
+#define BCHP_XPT_WDMA_CH14_REG_START                       0x00a6ae00
+#define BCHP_XPT_WDMA_CH14_REG_END                         0x00a6aefc
+#define BCHP_XPT_WDMA_CH15_REG_START                       0x00a6af00
+#define BCHP_XPT_WDMA_CH15_REG_END                         0x00a6affc
+#define BCHP_XPT_WDMA_CH16_REG_START                       0x00a6b000
+#define BCHP_XPT_WDMA_CH16_REG_END                         0x00a6b0fc
+#define BCHP_XPT_WDMA_CH17_REG_START                       0x00a6b100
+#define BCHP_XPT_WDMA_CH17_REG_END                         0x00a6b1fc
+#define BCHP_XPT_WDMA_CH18_REG_START                       0x00a6b200
+#define BCHP_XPT_WDMA_CH18_REG_END                         0x00a6b2fc
+#define BCHP_XPT_WDMA_CH19_REG_START                       0x00a6b300
+#define BCHP_XPT_WDMA_CH19_REG_END                         0x00a6b3fc
+#define BCHP_XPT_WDMA_CH20_REG_START                       0x00a6b400
+#define BCHP_XPT_WDMA_CH20_REG_END                         0x00a6b4fc
+#define BCHP_XPT_WDMA_CH21_REG_START                       0x00a6b500
+#define BCHP_XPT_WDMA_CH21_REG_END                         0x00a6b5fc
+#define BCHP_XPT_WDMA_CH22_REG_START                       0x00a6b600
+#define BCHP_XPT_WDMA_CH22_REG_END                         0x00a6b6fc
+#define BCHP_XPT_WDMA_CH23_REG_START                       0x00a6b700
+#define BCHP_XPT_WDMA_CH23_REG_END                         0x00a6b7fc
+#define BCHP_XPT_WDMA_CH24_REG_START                       0x00a6b800
+#define BCHP_XPT_WDMA_CH24_REG_END                         0x00a6b8fc
+#define BCHP_XPT_WDMA_CH25_REG_START                       0x00a6b900
+#define BCHP_XPT_WDMA_CH25_REG_END                         0x00a6b9fc
+#define BCHP_XPT_WDMA_CH26_REG_START                       0x00a6ba00
+#define BCHP_XPT_WDMA_CH26_REG_END                         0x00a6bafc
+#define BCHP_XPT_WDMA_CH27_REG_START                       0x00a6bb00
+#define BCHP_XPT_WDMA_CH27_REG_END                         0x00a6bbfc
+#define BCHP_XPT_WDMA_CH28_REG_START                       0x00a6bc00
+#define BCHP_XPT_WDMA_CH28_REG_END                         0x00a6bcfc
+#define BCHP_XPT_WDMA_CH29_REG_START                       0x00a6bd00
+#define BCHP_XPT_WDMA_CH29_REG_END                         0x00a6bdfc
+#define BCHP_XPT_WDMA_CH30_REG_START                       0x00a6be00
+#define BCHP_XPT_WDMA_CH30_REG_END                         0x00a6befc
+#define BCHP_XPT_WDMA_CH31_REG_START                       0x00a6bf00
+#define BCHP_XPT_WDMA_CH31_REG_END                         0x00a6bffc
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_START                   0x00a6ff00
+#define BCHP_XPT_MEMDMA_XMEMIF_REG_END                     0x00a6fffc
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START        0x00a70000
+#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END          0x00a7001c
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START        0x00a70020
+#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END          0x00a7003c
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START          0x00a70040
+#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END            0x00a7006c
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START    0x00a70080
+#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END      0x00a700ac
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START           0x00a700c0
+#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END             0x00a700ec
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
+#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END   0x00a7012c
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START           0x00a70140
+#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END             0x00a7016c
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START   0x00a70180
+#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END     0x00a701ac
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
+#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a701ec
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
+#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
+#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
+#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START  0x00a702c0
+#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END    0x00a702ec
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
+#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
+#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
+#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
+#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
+#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
+#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
+#define BCHP_XPT_MCPB_REG_START                            0x00a70800
+#define BCHP_XPT_MCPB_REG_END                              0x00a70b98
+#define BCHP_XPT_MCPB_CH0_REG_START                        0x00a70c00
+#define BCHP_XPT_MCPB_CH0_REG_END                          0x00a70d5c
+#define BCHP_XPT_MCPB_CH1_REG_START                        0x00a70e00
+#define BCHP_XPT_MCPB_CH1_REG_END                          0x00a70f5c
+#define BCHP_XPT_MCPB_CH2_REG_START                        0x00a71000
+#define BCHP_XPT_MCPB_CH2_REG_END                          0x00a7115c
+#define BCHP_XPT_MCPB_CH3_REG_START                        0x00a71200
+#define BCHP_XPT_MCPB_CH3_REG_END                          0x00a7135c
+#define BCHP_XPT_MCPB_CH4_REG_START                        0x00a71400
+#define BCHP_XPT_MCPB_CH4_REG_END                          0x00a7155c
+#define BCHP_XPT_MCPB_CH5_REG_START                        0x00a71600
+#define BCHP_XPT_MCPB_CH5_REG_END                          0x00a7175c
+#define BCHP_XPT_MCPB_CH6_REG_START                        0x00a71800
+#define BCHP_XPT_MCPB_CH6_REG_END                          0x00a7195c
+#define BCHP_XPT_MCPB_CH7_REG_START                        0x00a71a00
+#define BCHP_XPT_MCPB_CH7_REG_END                          0x00a71b5c
+#define BCHP_XPT_MCPB_CH8_REG_START                        0x00a71c00
+#define BCHP_XPT_MCPB_CH8_REG_END                          0x00a71d5c
+#define BCHP_XPT_MCPB_CH9_REG_START                        0x00a71e00
+#define BCHP_XPT_MCPB_CH9_REG_END                          0x00a71f5c
+#define BCHP_XPT_MCPB_CH10_REG_START                       0x00a72000
+#define BCHP_XPT_MCPB_CH10_REG_END                         0x00a7215c
+#define BCHP_XPT_MCPB_CH11_REG_START                       0x00a72200
+#define BCHP_XPT_MCPB_CH11_REG_END                         0x00a7235c
+#define BCHP_XPT_MCPB_CH12_REG_START                       0x00a72400
+#define BCHP_XPT_MCPB_CH12_REG_END                         0x00a7255c
+#define BCHP_XPT_MCPB_CH13_REG_START                       0x00a72600
+#define BCHP_XPT_MCPB_CH13_REG_END                         0x00a7275c
+#define BCHP_XPT_MCPB_CH14_REG_START                       0x00a72800
+#define BCHP_XPT_MCPB_CH14_REG_END                         0x00a7295c
+#define BCHP_XPT_MCPB_CH15_REG_START                       0x00a72a00
+#define BCHP_XPT_MCPB_CH15_REG_END                         0x00a72b5c
+#define BCHP_XPT_MCPB_CH16_REG_START                       0x00a72c00
+#define BCHP_XPT_MCPB_CH16_REG_END                         0x00a72d5c
+#define BCHP_XPT_MCPB_CH17_REG_START                       0x00a72e00
+#define BCHP_XPT_MCPB_CH17_REG_END                         0x00a72f5c
+#define BCHP_XPT_MCPB_CH18_REG_START                       0x00a73000
+#define BCHP_XPT_MCPB_CH18_REG_END                         0x00a7315c
+#define BCHP_XPT_MCPB_CH19_REG_START                       0x00a73200
+#define BCHP_XPT_MCPB_CH19_REG_END                         0x00a7335c
+#define BCHP_XPT_MCPB_CH20_REG_START                       0x00a73400
+#define BCHP_XPT_MCPB_CH20_REG_END                         0x00a7355c
+#define BCHP_XPT_MCPB_CH21_REG_START                       0x00a73600
+#define BCHP_XPT_MCPB_CH21_REG_END                         0x00a7375c
+#define BCHP_XPT_MCPB_CH22_REG_START                       0x00a73800
+#define BCHP_XPT_MCPB_CH22_REG_END                         0x00a7395c
+#define BCHP_XPT_MCPB_CH23_REG_START                       0x00a73a00
+#define BCHP_XPT_MCPB_CH23_REG_END                         0x00a73b5c
+#define BCHP_XPT_MCPB_CH24_REG_START                       0x00a73c00
+#define BCHP_XPT_MCPB_CH24_REG_END                         0x00a73d5c
+#define BCHP_XPT_MCPB_CH25_REG_START                       0x00a73e00
+#define BCHP_XPT_MCPB_CH25_REG_END                         0x00a73f5c
+#define BCHP_XPT_MCPB_CH26_REG_START                       0x00a74000
+#define BCHP_XPT_MCPB_CH26_REG_END                         0x00a7415c
+#define BCHP_XPT_MCPB_CH27_REG_START                       0x00a74200
+#define BCHP_XPT_MCPB_CH27_REG_END                         0x00a7435c
+#define BCHP_XPT_MCPB_CH28_REG_START                       0x00a74400
+#define BCHP_XPT_MCPB_CH28_REG_END                         0x00a7455c
+#define BCHP_XPT_MCPB_CH29_REG_START                       0x00a74600
+#define BCHP_XPT_MCPB_CH29_REG_END                         0x00a7475c
+#define BCHP_XPT_MCPB_CH30_REG_START                       0x00a74800
+#define BCHP_XPT_MCPB_CH30_REG_END                         0x00a7495c
+#define BCHP_XPT_MCPB_CH31_REG_START                       0x00a74a00
+#define BCHP_XPT_MCPB_CH31_REG_END                         0x00a74b5c
+#define BCHP_XPT_XPU_REG_START                             0x00a78000
+#define BCHP_XPT_XPU_REG_END                               0x00a7c7fc
+#define BCHP_XPT_SECURE_BUS_IF_REG_START                   0x00a7f000
+#define BCHP_XPT_SECURE_BUS_IF_REG_END                     0x00a7f000
+#define BCHP_GENET_0_SYS_REG_START                         0x00b60000
+#define BCHP_GENET_0_SYS_REG_END                           0x00b60010
+#define BCHP_GENET_0_GR_BRIDGE_REG_START                   0x00b60040
+#define BCHP_GENET_0_GR_BRIDGE_REG_END                     0x00b6004c
+#define BCHP_GENET_0_EXT_REG_START                         0x00b60080
+#define BCHP_GENET_0_EXT_REG_END                           0x00b600b4
+#define BCHP_GENET_0_INTRL2_0_REG_START                    0x00b60200
+#define BCHP_GENET_0_INTRL2_0_REG_END                      0x00b6022c
+#define BCHP_GENET_0_INTRL2_1_REG_START                    0x00b60240
+#define BCHP_GENET_0_INTRL2_1_REG_END                      0x00b6026c
+#define BCHP_GENET_0_RBUF_REG_START                        0x00b60300
+#define BCHP_GENET_0_RBUF_REG_END                          0x00b603b4
+#define BCHP_GENET_0_TBUF_REG_START                        0x00b60600
+#define BCHP_GENET_0_TBUF_REG_END                          0x00b60628
+#define BCHP_GENET_0_UMAC_REG_START                        0x00b60800
+#define BCHP_GENET_0_UMAC_REG_END                          0x00b60ed8
+#define BCHP_GENET_0_RDMA_REG_START                        0x00b62000
+#define BCHP_GENET_0_RDMA_REG_END                          0x00b630d4
+#define BCHP_GENET_0_TDMA_REG_START                        0x00b64000
+#define BCHP_GENET_0_TDMA_REG_END                          0x00b65084
+#define BCHP_GENET_0_HFB_REG_START                         0x00b68000
+#define BCHP_GENET_0_HFB_REG_END                           0x00b6fc48
+#define BCHP_GENET_1_SYS_REG_START                         0x00b80000
+#define BCHP_GENET_1_SYS_REG_END                           0x00b80010
+#define BCHP_GENET_1_GR_BRIDGE_REG_START                   0x00b80040
+#define BCHP_GENET_1_GR_BRIDGE_REG_END                     0x00b8004c
+#define BCHP_GENET_1_EXT_REG_START                         0x00b80080
+#define BCHP_GENET_1_EXT_REG_END                           0x00b800b4
+#define BCHP_GENET_1_INTRL2_0_REG_START                    0x00b80200
+#define BCHP_GENET_1_INTRL2_0_REG_END                      0x00b8022c
+#define BCHP_GENET_1_INTRL2_1_REG_START                    0x00b80240
+#define BCHP_GENET_1_INTRL2_1_REG_END                      0x00b8026c
+#define BCHP_GENET_1_RBUF_REG_START                        0x00b80300
+#define BCHP_GENET_1_RBUF_REG_END                          0x00b803b4
+#define BCHP_GENET_1_TBUF_REG_START                        0x00b80600
+#define BCHP_GENET_1_TBUF_REG_END                          0x00b80628
+#define BCHP_GENET_1_UMAC_REG_START                        0x00b80800
+#define BCHP_GENET_1_UMAC_REG_END                          0x00b80ed8
+#define BCHP_GENET_1_RDMA_REG_START                        0x00b82000
+#define BCHP_GENET_1_RDMA_REG_END                          0x00b830d4
+#define BCHP_GENET_1_TDMA_REG_START                        0x00b84000
+#define BCHP_GENET_1_TDMA_REG_END                          0x00b85084
+#define BCHP_GENET_1_HFB_REG_START                         0x00b88000
+#define BCHP_GENET_1_HFB_REG_END                           0x00b8fc48
+#define BCHP_SID_REG_START                                 0x00bc0100
+#define BCHP_SID_REG_END                                   0x00bc019c
+#define BCHP_SID_RLE_REG_START                             0x00bc0300
+#define BCHP_SID_RLE_REG_END                               0x00bc039c
+#define BCHP_SID_DQ_REG_START                              0x00bc0400
+#define BCHP_SID_DQ_REG_END                                0x00bc04bc
+#define BCHP_SID_STRM_REG_START                            0x00bc0800
+#define BCHP_SID_STRM_REG_END                              0x00bc087c
+#define BCHP_SID_OUTPUT_REG_START                          0x00bc0c00
+#define BCHP_SID_OUTPUT_REG_END                            0x00bc0c40
+#define BCHP_SID_ARC_REG_START                             0x00bc0f00
+#define BCHP_SID_ARC_REG_END                               0x00bc0f3c
+#define BCHP_SID_ARCDMA_REG_START                          0x00bc1800
+#define BCHP_SID_ARCDMA_REG_END                            0x00bc1840
+#define BCHP_SID_DMARAM_REG_START                          0x00bc1a00
+#define BCHP_SID_DMARAM_REG_END                            0x00bc1bfc
+#define BCHP_SID_PEEK_BITS_REG_START                       0x00bc2b00
+#define BCHP_SID_PEEK_BITS_REG_END                         0x00bc2b3c
+#define BCHP_SID_EXTRACT_BITS_REG_START                    0x00bc2b40
+#define BCHP_SID_EXTRACT_BITS_REG_END                      0x00bc2b7c
+#define BCHP_SID_HUFF_SYMB_REG_START                       0x00bc3000
+#define BCHP_SID_HUFF_SYMB_REG_END                         0x00bc37fc
+#define BCHP_SID_HUFF_CODE_REG_START                       0x00bc3900
+#define BCHP_SID_HUFF_CODE_REG_END                         0x00bc39fc
+#define BCHP_SID_SYMB_REG_START                            0x00bc3a00
+#define BCHP_SID_SYMB_REG_END                              0x00bc3a10
+#define BCHP_SID_SYMB_JPEG_REG_START                       0x00bc3a80
+#define BCHP_SID_SYMB_JPEG_REG_END                         0x00bc3a8c
+#define BCHP_SID_BIGRAM_REG_START                          0x00bc8000
+#define BCHP_SID_BIGRAM_REG_END                            0x00bcfffc
+#define BCHP_SID_ARC_DBG_REG_START                         0x00bd1000
+#define BCHP_SID_ARC_DBG_REG_END                           0x00bd1010
+#define BCHP_SID_ARC_CORE_REG_START                        0x00bd5000
+#define BCHP_SID_ARC_CORE_REG_END                          0x00bd5014
+#define BCHP_SID_GR_REG_START                              0x00be0000
+#define BCHP_SID_GR_REG_END                                0x00be000c
+#define BCHP_SID_L2_REG_START                              0x00be0100
+#define BCHP_SID_L2_REG_END                                0x00be012c
+#define BCHP_SICH_REG_START                                0x00be2000
+#define BCHP_SICH_REG_END                                  0x00be203c
+#define BCHP_M2MC_REG_START                                0x00be4000
+#define BCHP_M2MC_REG_END                                  0x00be47fc
+#define BCHP_M2MC_L2_REG_START                             0x00be5000
+#define BCHP_M2MC_L2_REG_END                               0x00be502c
+#define BCHP_M2MC_GR_REG_START                             0x00be5800
+#define BCHP_M2MC_GR_REG_END                               0x00be580c
+#define BCHP_V3D_CTL_REG_START                             0x00bea000
+#define BCHP_V3D_CTL_REG_END                               0x00bea040
+#define BCHP_V3D_CLE_REG_START                             0x00bea100
+#define BCHP_V3D_CLE_REG_END                               0x00bea138
+#define BCHP_V3D_PTB_REG_START                             0x00bea300
+#define BCHP_V3D_PTB_REG_END                               0x00bea310
+#define BCHP_V3D_QPS_REG_START                             0x00bea400
+#define BCHP_V3D_QPS_REG_END                               0x00bea43c
+#define BCHP_V3D_VPM_REG_START                             0x00bea500
+#define BCHP_V3D_VPM_REG_END                               0x00bea504
+#define BCHP_V3D_PCTR_REG_START                            0x00bea600
+#define BCHP_V3D_PCTR_REG_END                              0x00bea6fc
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_START                   0x00bea800
+#define BCHP_V3D_TOP_GR_BRIDGE_REG_END                     0x00bea80c
+#define BCHP_V3D_GCA_REG_START                             0x00beaa00
+#define BCHP_V3D_GCA_REG_END                               0x00beaa64
+#define BCHP_V3D_DBG_REG_START                             0x00beae00
+#define BCHP_V3D_DBG_REG_END                               0x00beaf20
+#define BCHP_RAAGA_DSP_SEC0_REG_START                      0x00bf0000
+#define BCHP_RAAGA_DSP_SEC0_REG_END                        0x00bf0000
+#define BCHP_RAAGA_DSP_RGR_REG_START                       0x00c00000
+#define BCHP_RAAGA_DSP_RGR_REG_END                         0x00c00008
+#define BCHP_RAAGA_DSP_MISC_REG_START                      0x00c20000
+#define BCHP_RAAGA_DSP_MISC_REG_END                        0x00c2044c
+#define BCHP_RAAGA_DSP_TIMERS_REG_START                    0x00c21000
+#define BCHP_RAAGA_DSP_TIMERS_REG_END                      0x00c21058
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START             0x00c21080
+#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END               0x00c2108c
+#define BCHP_RAAGA_DSP_PERI_SW_REG_START                   0x00c21100
+#define BCHP_RAAGA_DSP_PERI_SW_REG_END                     0x00c21154
+#define BCHP_RAAGA_DSP_DMA_REG_START                       0x00c21400
+#define BCHP_RAAGA_DSP_DMA_REG_END                         0x00c21678
+#define BCHP_RAAGA_DSP_ESR_SI_REG_START                    0x00c22000
+#define BCHP_RAAGA_DSP_ESR_SI_REG_END                      0x00c22014
+#define BCHP_RAAGA_DSP_INTH_REG_START                      0x00c22200
+#define BCHP_RAAGA_DSP_INTH_REG_END                        0x00c2222c
+#define BCHP_RAAGA_DSP_TIMER_INT_REG_START                 0x00c22400
+#define BCHP_RAAGA_DSP_TIMER_INT_REG_END                   0x00c22414
+#define BCHP_RAAGA_DSP_ERROR_INT_REG_START                 0x00c22600
+#define BCHP_RAAGA_DSP_ERROR_INT_REG_END                   0x00c22614
+#define BCHP_RAAGA_DSP_FW_INTH_REG_START                   0x00c22800
+#define BCHP_RAAGA_DSP_FW_INTH_REG_END                     0x00c2282c
+#define BCHP_RAAGA_DSP_FW_CFG_REG_START                    0x00c23000
+#define BCHP_RAAGA_DSP_FW_CFG_REG_END                      0x00c2357c
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START             0x00c30000
+#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END               0x00c3bffc
+#define BCHP_RAAGA_AX_MISC_REG_START                       0x00c40000
+#define BCHP_RAAGA_AX_MISC_REG_END                         0x00c40004
+#define BCHP_RAAGA_AX_INTR_AGGR_REG_START                  0x00c40100
+#define BCHP_RAAGA_AX_INTR_AGGR_REG_END                    0x00c40144
+#define BCHP_RAAGA_AX_RXI_ARB_REG_START                    0x00c40200
+#define BCHP_RAAGA_AX_RXI_ARB_REG_END                      0x00c40248
+#define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_START              0x00c40300
+#define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_END                0x00c40314
+#define BCHP_RAAGA_AX_EC_WATCHDOG_REG_START                0x00c40400
+#define BCHP_RAAGA_AX_EC_WATCHDOG_REG_END                  0x00c40414
+#define BCHP_RAAGA_AX_ME_WATCHDOG_REG_START                0x00c40500
+#define BCHP_RAAGA_AX_ME_WATCHDOG_REG_END                  0x00c40514
+#define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_START             0x00c40600
+#define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_END               0x00c40614
+#define BCHP_RAAGA_AX_DBLK_REG_START                       0x00c41000
+#define BCHP_RAAGA_AX_DBLK_REG_END                         0x00c411fc
+#define BCHP_RAAGA_AX_EC_REG_START                         0x00c42000
+#define BCHP_RAAGA_AX_EC_REG_END                           0x00c42158
+#define BCHP_RAAGA_AX_ME_REG_START                         0x00c43000
+#define BCHP_RAAGA_AX_ME_REG_END                           0x00c4321c
+#define BCHP_RAAGA_AX_GENAX_REG_START                      0x00c44000
+#define BCHP_RAAGA_AX_GENAX_REG_END                        0x00c44650
+#define BCHP_AUD_MISC_REG_START                            0x00c80000
+#define BCHP_AUD_MISC_REG_END                              0x00c80120
+#define BCHP_AUD_INTH_REG_START                            0x00c80800
+#define BCHP_AUD_INTH_REG_END                              0x00c8082c
+#define BCHP_AUD_FMM_BF_CTRL_REG_START                     0x00ca0000
+#define BCHP_AUD_FMM_BF_CTRL_REG_END                       0x00ca0d3c
+#define BCHP_AUD_FMM_BF_ESR_REG_START                      0x00ca1000
+#define BCHP_AUD_FMM_BF_ESR_REG_END                        0x00ca1074
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_START                   0x00ca2000
+#define BCHP_AUD_FMM_SRC_CTRL0_REG_END                     0x00ca2bfc
+#define BCHP_AUD_FMM_SRC_ESR0_REG_START                    0x00ca3000
+#define BCHP_AUD_FMM_SRC_ESR0_REG_END                      0x00ca3014
+#define BCHP_AUD_FMM_DP_CTRL0_REG_START                    0x00ca4000
+#define BCHP_AUD_FMM_DP_CTRL0_REG_END                      0x00ca612c
+#define BCHP_AUD_FMM_DP_ESR0_REG_START                     0x00ca7c00
+#define BCHP_AUD_FMM_DP_ESR0_REG_END                       0x00ca7c2c
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START        0x00cb0000
+#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END          0x00cb0084
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START             0x00cb0100
+#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END               0x00cb0184
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START               0x00cb0200
+#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END                 0x00cb02b4
+#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_START               0x00cb0300
+#define BCHP_AUD_FMM_IOP_OUT_MAI_1_REG_END                 0x00cb03b4
+#define BCHP_HIFIDAC_CTRL_0_REG_START                      0x00cb0800
+#define BCHP_HIFIDAC_CTRL_0_REG_END                        0x00cb09fc
+#define BCHP_HIFIDAC_RM_0_REG_START                        0x00cb0a00
+#define BCHP_HIFIDAC_RM_0_REG_END                          0x00cb0a30
+#define BCHP_HIFIDAC_ESR_0_REG_START                       0x00cb0b00
+#define BCHP_HIFIDAC_ESR_0_REG_END                         0x00cb0b14
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START          0x00cb0c00
+#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END            0x00cb0c98
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_START                   0x00cb0d00
+#define BCHP_AUD_FMM_IOP_PLL_0_REG_END                     0x00cb0d88
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_START                   0x00cb0e00
+#define BCHP_AUD_FMM_IOP_PLL_1_REG_END                     0x00cb0e88
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_START                   0x00cb0f00
+#define BCHP_AUD_FMM_IOP_NCO_0_REG_END                     0x00cb0f30
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_START                   0x00cb1000
+#define BCHP_AUD_FMM_IOP_NCO_1_REG_END                     0x00cb1030
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_START                   0x00cb1100
+#define BCHP_AUD_FMM_IOP_NCO_2_REG_END                     0x00cb1130
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_START                   0x00cb1200
+#define BCHP_AUD_FMM_IOP_NCO_3_REG_END                     0x00cb1230
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_START                   0x00cb1300
+#define BCHP_AUD_FMM_IOP_NCO_4_REG_END                     0x00cb1330
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START              0x00cb1400
+#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END                0x00cb1524
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START             0x00cb1600
+#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END               0x00cb165c
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START              0x00cb1800
+#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END                0x00cb18fc
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START               0x00cb2000
+#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END                 0x00cb20ac
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START         0x00cb2800
+#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END           0x00cb2864
+#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START                  0x00cb2900
+#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END                    0x00cb2964
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START       0x00cb4000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END         0x00cb41fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START       0x00cb4400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END         0x00cb4414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START           0x00cb6000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END             0x00cb7bfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START            0x00cb7d00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END              0x00cb7d14
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_START       0x00cb8000
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_END         0x00cb81fc
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_START       0x00cb8400
+#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_END         0x00cb8414
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_START           0x00cba000
+#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_END             0x00cbbbfc
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_START            0x00cbbd00
+#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_END              0x00cbbd14
+#define BCHP_AUD_FMM_IOP_MISC_REG_START                    0x00cbc100
+#define BCHP_AUD_FMM_IOP_MISC_REG_END                      0x00cbc154
+#define BCHP_DATA_MEM_REG_START                            0x00e00000
+#define BCHP_DATA_MEM_REG_END                              0x00e47ffc
+#define BCHP_CNTL_MEM_REG_START                            0x00f20000
+#define BCHP_CNTL_MEM_REG_END                              0x00f67ffc
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START                0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END                  0x00fc0000
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START                0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END                  0x00fc0010
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START                0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END                  0x00fc0020
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START                0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END                  0x00fc0030
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START                0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END                  0x00fc0040
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START                0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END                  0x00fc0050
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START                0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END                  0x00fc0060
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START                0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END                  0x00fc0070
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START                0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END                  0x00fc0080
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START                0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END                  0x00fc0090
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START               0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END                 0x00fc00a0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START               0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END                 0x00fc00b0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START               0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END                 0x00fc00c0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START               0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END                 0x00fc00d0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START               0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END                 0x00fc00e0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START               0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END                 0x00fc00f0
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START               0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END                 0x00fc0100
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START               0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END                 0x00fc0110
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START               0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END                 0x00fc0120
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START               0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END                 0x00fc0130
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START                  0x00fc0800
+#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END                    0x00fc0800
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START                 0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END                   0x00fc4000
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START                 0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END                   0x00fc4010
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START                 0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END                   0x00fc4020
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START                 0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END                   0x00fc4030
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START                 0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END                   0x00fc4040
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START                 0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END                   0x00fc4050
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START                 0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END                   0x00fc4060
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START                 0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END                   0x00fc4070
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START                 0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END                   0x00fc4080
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START                 0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END                   0x00fc4090
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START                0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END                  0x00fc40a0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START                0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END                  0x00fc40b0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START                0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END                  0x00fc40c0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START                0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END                  0x00fc40d0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START                0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END                  0x00fc40e0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START                0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END                  0x00fc40f0
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START                0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END                  0x00fc4100
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START                0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END                  0x00fc4110
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START                0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END                  0x00fc4120
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START                0x00fc4130
+#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END                  0x00fc4130
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START               0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END                 0x00fc4200
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START               0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END                 0x00fc4210
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START               0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END                 0x00fc4220
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START               0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END                 0x00fc4230
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START               0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END                 0x00fc4240
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START               0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END                 0x00fc4250
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START               0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END                 0x00fc4260
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START               0x00fc4270
+#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END                 0x00fc4270
+#define BCHP_DMA_AHB_CMD_TX0_REG_START                     0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX0_REG_END                       0x00fc4800
+#define BCHP_DMA_AHB_CMD_TX1_REG_START                     0x00fc4a00
+#define BCHP_DMA_AHB_CMD_TX1_REG_END                       0x00fc4a00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_START                   0x00fc4c00
+#define BCHP_DMA_AHB_CMD_CONF0_REG_END                     0x00fc4c00
+#define BCHP_MAC_AHB_REG_START                             0x00fc5000
+#define BCHP_MAC_AHB_REG_END                               0x00fc500c
+#define BCHP_LLM_AHB_REG_START                             0x00fc8000
+#define BCHP_LLM_AHB_REG_END                               0x00fc805c
+#define BCHP_PHY_REG_START                                 0x00fe0000
+#define BCHP_PHY_REG_END                                   0x00fe47fc
+#define BCHP_ECL_REG_START                                 0x00fe8000
+#define BCHP_ECL_REG_END                                   0x00fecb20
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START         0x00fed000
+#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END           0x00fed014
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START      0x00fed040
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END        0x00fed06c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START      0x00fed080
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END        0x00fed0ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START      0x00fed0c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END        0x00fed0ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START      0x00fed100
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END        0x00fed12c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START      0x00fed140
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END        0x00fed16c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START      0x00fed180
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END        0x00fed1ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START      0x00fed1c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END        0x00fed1ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START      0x00fed200
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END        0x00fed22c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START      0x00fed240
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END        0x00fed26c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START      0x00fed280
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END        0x00fed2ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START     0x00fed2c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END       0x00fed2ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START     0x00fed300
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END       0x00fed32c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START     0x00fed340
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END       0x00fed36c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START     0x00fed380
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END       0x00fed3ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START     0x00fed3c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END       0x00fed3ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START     0x00fed400
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END       0x00fed42c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START     0x00fed440
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END       0x00fed46c
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START     0x00fed480
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END       0x00fed4ac
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START     0x00fed4c0
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END       0x00fed4ec
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START     0x00fed500
+#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END       0x00fed52c
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START                0x00fed800
+#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END                  0x00fed828
+#define BCHP_GMII_REG_START                                0x00fedc00
+#define BCHP_GMII_REG_END                                  0x00fedc58
+#define BCHP_MAC_APB_REG_START                             0x00ff0000
+#define BCHP_MAC_APB_REG_END                               0x00ff14fc
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START         0x00ff4000
+#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END           0x00ff4014
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START      0x00ff4040
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END        0x00ff406c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START      0x00ff4080
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END        0x00ff40ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START      0x00ff40c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END        0x00ff40ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START      0x00ff4100
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END        0x00ff412c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START      0x00ff4140
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END        0x00ff416c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START      0x00ff4180
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END        0x00ff41ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START      0x00ff41c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END        0x00ff41ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START      0x00ff4200
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END        0x00ff422c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START      0x00ff4240
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END        0x00ff426c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START      0x00ff4280
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END        0x00ff42ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START     0x00ff42c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END       0x00ff42ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START     0x00ff4300
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END       0x00ff432c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START     0x00ff4340
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END       0x00ff436c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START     0x00ff4380
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END       0x00ff43ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START     0x00ff43c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END       0x00ff43ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START     0x00ff4400
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END       0x00ff442c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START     0x00ff4440
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END       0x00ff446c
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START     0x00ff4480
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END       0x00ff44ac
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START     0x00ff44c0
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END       0x00ff44ec
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START     0x00ff4500
+#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END       0x00ff452c
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START           0x00ff4800
+#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END             0x00ff4814
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START        0x00ff4840
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END          0x00ff486c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START        0x00ff4880
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END          0x00ff48ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START        0x00ff48c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END          0x00ff48ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START        0x00ff4900
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END          0x00ff492c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START        0x00ff4940
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END          0x00ff496c
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START        0x00ff4980
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END          0x00ff49ac
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START        0x00ff49c0
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END          0x00ff49ec
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START        0x00ff4a00
+#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END          0x00ff4a2c
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START               0x00ff6000
+#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END                 0x00ff6028
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START               0x00ff6400
+#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END                 0x00ff6428
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START           0x00ff6800
+#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END             0x00ff6828
+#define BCHP_MOCA_INTC_L2_HI_REG_START                     0x00ff8000
+#define BCHP_MOCA_INTC_L2_HI_REG_END                       0x00ff8584
+#define BCHP_MOCA_INTC_L2_LO_REG_START                     0x00ff8800
+#define BCHP_MOCA_INTC_L2_LO_REG_END                       0x00ff8d84
+#define BCHP_LLM_APB_REG_START                             0x00ffc000
+#define BCHP_LLM_APB_REG_END                               0x00ffd00c
+#define BCHP_TRX_REG_START                                 0x00ffe000
+#define BCHP_TRX_REG_END                                   0x00ffe1fc
+#define BCHP_MOCA_TIMER_REG_START                          0x00ffe400
+#define BCHP_MOCA_TIMER_REG_END                            0x00ffe4ec
+#define BCHP_MOCA_GPIO_REG_START                           0x00ffe800
+#define BCHP_MOCA_GPIO_REG_END                             0x00ffe818
+#define BCHP_EXTRAS_REG_START                              0x00ffec00
+#define BCHP_EXTRAS_REG_END                                0x00ffed18
+#define BCHP_MOCA_BSC_REG_START                            0x00fff000
+#define BCHP_MOCA_BSC_REG_END                              0x00fff058
+#define BCHP_MOCA_HOSTM2M_REG_START                        0x00fffc00
+#define BCHP_MOCA_HOSTM2M_REG_END                          0x00fffc14
+#define BCHP_AHB_M2M_DMA_REG_START                         0x00fffc20
+#define BCHP_AHB_M2M_DMA_REG_END                           0x00fffc2c
+#define BCHP_MOCA_L2_REG_START                             0x00fffc40
+#define BCHP_MOCA_L2_REG_END                               0x00fffc6c
+#define BCHP_MOCA_GR_BRIDGE_REG_START                      0x00fffc80
+#define BCHP_MOCA_GR_BRIDGE_REG_END                        0x00fffc8c
+#define BCHP_MOCA_HOSTMISC_REG_START                       0x00fffd00
+#define BCHP_MOCA_HOSTMISC_REG_END                         0x00fffd9c
+#define BCHP_LEAP_ROM_REG_START                            0x01000000
+#define BCHP_LEAP_ROM_REG_END                              0x01007ffc
+#define BCHP_LEAP_PROG0_MEM_REG_START                      0x01040000
+#define BCHP_LEAP_PROG0_MEM_REG_END                        0x01047ffc
+#define BCHP_LEAP_CPU_CORE_REGS_REG_START                  0x010a0000
+#define BCHP_LEAP_CPU_CORE_REGS_REG_END                    0x010a00fc
+#define BCHP_LEAP_CPU_AUX_REGS_REG_START                   0x010c0000
+#define BCHP_LEAP_CPU_AUX_REGS_REG_END                     0x010c10c4
+#define BCHP_LEAP_HAB_MEM_REG_START                        0x010c8000
+#define BCHP_LEAP_HAB_MEM_REG_END                          0x010c83fc
+#define BCHP_LEAP_UART_REG_START                           0x010c9000
+#define BCHP_LEAP_UART_REG_END                             0x010c9ffc
+#define BCHP_LEAP_WDG_REG_START                            0x010ca000
+#define BCHP_LEAP_WDG_REG_END                              0x010caffc
+#define BCHP_LEAP_CTRL_REG_START                           0x01100000
+#define BCHP_LEAP_CTRL_REG_END                             0x01100310
+#define BCHP_LEAP_L1_REG_START                             0x01100400
+#define BCHP_LEAP_L1_REG_END                               0x01100418
+#define BCHP_LEAP_L2_REG_START                             0x01100500
+#define BCHP_LEAP_L2_REG_END                               0x01100514
+#define BCHP_LEAP_HOST_L1_REG_START                        0x01100600
+#define BCHP_LEAP_HOST_L1_REG_END                          0x01100618
+#define BCHP_LEAP_HOST_L2_REG_START                        0x01100700
+#define BCHP_LEAP_HOST_L2_REG_END                          0x0110072c
+#define BCHP_LEAP_CTRL_MISC_REG_START                      0x01100800
+#define BCHP_LEAP_CTRL_MISC_REG_END                        0x01100848
+#define BCHP_LEAP_ROM_PATCH_REG_START                      0x01100a00
+#define BCHP_LEAP_ROM_PATCH_REG_END                        0x01100a3c
+#define BCHP_LEAP_RGR_BRIDGE_REG_START                     0x01100b00
+#define BCHP_LEAP_RGR_BRIDGE_REG_END                       0x01100b10
+#define BCHP_FTM_UART_REG_START                            0x01210000
+#define BCHP_FTM_UART_REG_END                              0x012100fc
+#define BCHP_FTM_PHY_REG_START                             0x01210000
+#define BCHP_FTM_PHY_REG_END                               0x012101fc
+#define BCHP_FTM_PHY_ANA_REG_START                         0x01210000
+#define BCHP_FTM_PHY_ANA_REG_END                           0x01210208
+#define BCHP_FTM_SKIT_REG_START                            0x01210000
+#define BCHP_FTM_SKIT_REG_END                              0x01210248
+#define BCHP_FTM_INTR2_REG_START                           0x01210000
+#define BCHP_FTM_INTR2_REG_END                             0x0121032c
+#define BCHP_FTM_SW_SPARE_REG_START                        0x01210000
+#define BCHP_FTM_SW_SPARE_REG_END                          0x01210334
+#define BCHP_SDS_DSEC_0_REG_START                          0x01218000
+#define BCHP_SDS_DSEC_0_REG_END                            0x012180d4
+#define BCHP_SDS_DSEC_INTR2_0_REG_START                    0x01218100
+#define BCHP_SDS_DSEC_INTR2_0_REG_END                      0x0121812c
+#define BCHP_SDS_DSEC_GR_BRIDGE_0_REG_START                0x01218140
+#define BCHP_SDS_DSEC_GR_BRIDGE_0_REG_END                  0x0121814c
+#define BCHP_SDS_DSEC_AP_0_REG_START                       0x01218150
+#define BCHP_SDS_DSEC_AP_0_REG_END                         0x01218158
+#define BCHP_SDS_DSEC_1_REG_START                          0x01219000
+#define BCHP_SDS_DSEC_1_REG_END                            0x012190d4
+#define BCHP_SDS_DSEC_INTR2_1_REG_START                    0x01219100
+#define BCHP_SDS_DSEC_INTR2_1_REG_END                      0x0121912c
+#define BCHP_SDS_DSEC_GR_BRIDGE_1_REG_START                0x01219140
+#define BCHP_SDS_DSEC_GR_BRIDGE_1_REG_END                  0x0121914c
+#define BCHP_SDS_DSEC_AP_1_REG_START                       0x01219150
+#define BCHP_SDS_DSEC_AP_1_REG_END                         0x01219158
+#define BCHP_SDS_DSEC_2_REG_START                          0x0121a000
+#define BCHP_SDS_DSEC_2_REG_END                            0x0121a0d4
+#define BCHP_SDS_DSEC_INTR2_2_REG_START                    0x0121a100
+#define BCHP_SDS_DSEC_INTR2_2_REG_END                      0x0121a12c
+#define BCHP_SDS_DSEC_GR_BRIDGE_2_REG_START                0x0121a140
+#define BCHP_SDS_DSEC_GR_BRIDGE_2_REG_END                  0x0121a14c
+#define BCHP_SDS_DSEC_AP_2_REG_START                       0x0121a150
+#define BCHP_SDS_DSEC_AP_2_REG_END                         0x0121a158
+#define BCHP_SDS_DSEC_3_REG_START                          0x0121b000
+#define BCHP_SDS_DSEC_3_REG_END                            0x0121b0d4
+#define BCHP_SDS_DSEC_INTR2_3_REG_START                    0x0121b100
+#define BCHP_SDS_DSEC_INTR2_3_REG_END                      0x0121b12c
+#define BCHP_SDS_DSEC_GR_BRIDGE_3_REG_START                0x0121b140
+#define BCHP_SDS_DSEC_GR_BRIDGE_3_REG_END                  0x0121b14c
+#define BCHP_SDS_DSEC_AP_3_REG_START                       0x0121b150
+#define BCHP_SDS_DSEC_AP_3_REG_END                         0x0121b158
+#define BCHP_STB_CHAN_CTRL_REG_START                       0x0121c000
+#define BCHP_STB_CHAN_CTRL_REG_END                         0x0121c03c
+#define BCHP_STB_CHAN_CH0_REG_START                        0x0121c100
+#define BCHP_STB_CHAN_CH0_REG_END                          0x0121c1ec
+#define BCHP_STB_CHAN_CH1_REG_START                        0x0121c200
+#define BCHP_STB_CHAN_CH1_REG_END                          0x0121c2ec
+#define BCHP_AIF_MDAC_CAL_SAT_CORE0_REG_START              0x01224000
+#define BCHP_AIF_MDAC_CAL_SAT_CORE0_REG_END                0x01224118
+#define BCHP_AIF_MDAC_CAL_SAT_CORE_INTR2_0_REG_START       0x01224800
+#define BCHP_AIF_MDAC_CAL_SAT_CORE_INTR2_0_REG_END         0x0122482c
+#define BCHP_BAC_MSPI_REG_START                            0x01225000
+#define BCHP_BAC_MSPI_REG_END                              0x01225018
+#define BCHP_AIF_MDAC_CAL_SAT_BAC_REG_START                0x01225800
+#define BCHP_AIF_MDAC_CAL_SAT_BAC_REG_END                  0x01225810
+#define BCHP_AIF_MDAC_CAL_SAT_ANA_REG_START                0x01226000
+#define BCHP_AIF_MDAC_CAL_SAT_ANA_REG_END                  0x01226094
+#define BCHP_AIF_WB_SAT_CORE0_0_REG_START                  0x01230000
+#define BCHP_AIF_WB_SAT_CORE0_0_REG_END                    0x01230474
+#define BCHP_AIF_WB_SAT_CORE_INTR2_0_0_REG_START           0x01230800
+#define BCHP_AIF_WB_SAT_CORE_INTR2_0_0_REG_END             0x0123082c
+#define BCHP_AIF_WB_SAT_ANA_0_REG_START                    0x01231000
+#define BCHP_AIF_WB_SAT_ANA_0_REG_END                      0x012310c0
+#define BCHP_SDS_CG_0_REG_START                            0x01240000
+#define BCHP_SDS_CG_0_REG_END                              0x0124003c
+#define BCHP_SDS_FE_0_REG_START                            0x01240080
+#define BCHP_SDS_FE_0_REG_END                              0x012400bc
+#define BCHP_SDS_BL_0_REG_START                            0x01240140
+#define BCHP_SDS_BL_0_REG_END                              0x01240160
+#define BCHP_SDS_CL_0_REG_START                            0x01240180
+#define BCHP_SDS_CL_0_REG_END                              0x012401fc
+#define BCHP_SDS_EQ_0_REG_START                            0x01240200
+#define BCHP_SDS_EQ_0_REG_END                              0x0124028c
+#define BCHP_SDS_HP_0_REG_START                            0x01240300
+#define BCHP_SDS_HP_0_REG_END                              0x012403e8
+#define BCHP_SDS_VIT_0_REG_START                           0x01240400
+#define BCHP_SDS_VIT_0_REG_END                             0x01240428
+#define BCHP_SDS_FEC_0_REG_START                           0x01240440
+#define BCHP_SDS_FEC_0_REG_END                             0x01240454
+#define BCHP_SDS_OI_0_REG_START                            0x01240480
+#define BCHP_SDS_OI_0_REG_END                              0x012404cc
+#define BCHP_SDS_SNR_0_REG_START                           0x01240500
+#define BCHP_SDS_SNR_0_REG_END                             0x01240518
+#define BCHP_SDS_BERT_0_REG_START                          0x01240540
+#define BCHP_SDS_BERT_0_REG_END                            0x01240568
+#define BCHP_SDS_DFT_0_REG_START                           0x01240580
+#define BCHP_SDS_DFT_0_REG_END                             0x012405a8
+#define BCHP_SDS_CWC_0_REG_START                           0x01240600
+#define BCHP_SDS_CWC_0_REG_END                             0x01240694
+#define BCHP_SDS_MISC_0_REG_START                          0x01240700
+#define BCHP_SDS_MISC_0_REG_END                            0x01240798
+#define BCHP_SDS_INTR2_0_0_REG_START                       0x01240a00
+#define BCHP_SDS_INTR2_0_0_REG_END                         0x01240a2c
+#define BCHP_SDS_GR_BRIDGE_0_REG_START                     0x01240c00
+#define BCHP_SDS_GR_BRIDGE_0_REG_END                       0x01240c0c
+#define BCHP_SDS_CG_1_REG_START                            0x01241000
+#define BCHP_SDS_CG_1_REG_END                              0x0124103c
+#define BCHP_SDS_FE_1_REG_START                            0x01241080
+#define BCHP_SDS_FE_1_REG_END                              0x012410bc
+#define BCHP_SDS_BL_1_REG_START                            0x01241140
+#define BCHP_SDS_BL_1_REG_END                              0x01241160
+#define BCHP_SDS_CL_1_REG_START                            0x01241180
+#define BCHP_SDS_CL_1_REG_END                              0x012411fc
+#define BCHP_SDS_EQ_1_REG_START                            0x01241200
+#define BCHP_SDS_EQ_1_REG_END                              0x0124128c
+#define BCHP_SDS_HP_1_REG_START                            0x01241300
+#define BCHP_SDS_HP_1_REG_END                              0x012413e8
+#define BCHP_SDS_VIT_1_REG_START                           0x01241400
+#define BCHP_SDS_VIT_1_REG_END                             0x01241428
+#define BCHP_SDS_FEC_1_REG_START                           0x01241440
+#define BCHP_SDS_FEC_1_REG_END                             0x01241454
+#define BCHP_SDS_OI_1_REG_START                            0x01241480
+#define BCHP_SDS_OI_1_REG_END                              0x012414cc
+#define BCHP_SDS_SNR_1_REG_START                           0x01241500
+#define BCHP_SDS_SNR_1_REG_END                             0x01241518
+#define BCHP_SDS_BERT_1_REG_START                          0x01241540
+#define BCHP_SDS_BERT_1_REG_END                            0x01241568
+#define BCHP_SDS_DFT_1_REG_START                           0x01241580
+#define BCHP_SDS_DFT_1_REG_END                             0x012415a8
+#define BCHP_SDS_CWC_1_REG_START                           0x01241600
+#define BCHP_SDS_CWC_1_REG_END                             0x01241694
+#define BCHP_SDS_MISC_1_REG_START                          0x01241700
+#define BCHP_SDS_MISC_1_REG_END                            0x01241798
+#define BCHP_SDS_INTR2_0_1_REG_START                       0x01241a00
+#define BCHP_SDS_INTR2_0_1_REG_END                         0x01241a2c
+#define BCHP_SDS_GR_BRIDGE_1_REG_START                     0x01241c00
+#define BCHP_SDS_GR_BRIDGE_1_REG_END                       0x01241c0c
+#define BCHP_TFEC_0_REG_START                              0x01248000
+#define BCHP_TFEC_0_REG_END                                0x01248060
+#define BCHP_TFEC_MISC_0_REG_START                         0x01248100
+#define BCHP_TFEC_MISC_0_REG_END                           0x01248108
+#define BCHP_TFEC_INTR2_0_REG_START                        0x01248200
+#define BCHP_TFEC_INTR2_0_REG_END                          0x0124822c
+#define BCHP_TFEC_GR_BRIDGE_0_REG_START                    0x01248300
+#define BCHP_TFEC_GR_BRIDGE_0_REG_END                      0x0124830c
+#define BCHP_TFEC_1_REG_START                              0x01249000
+#define BCHP_TFEC_1_REG_END                                0x01249060
+#define BCHP_TFEC_MISC_1_REG_START                         0x01249100
+#define BCHP_TFEC_MISC_1_REG_END                           0x01249108
+#define BCHP_TFEC_INTR2_1_REG_START                        0x01249200
+#define BCHP_TFEC_INTR2_1_REG_END                          0x0124922c
+#define BCHP_TFEC_GR_BRIDGE_1_REG_START                    0x01249300
+#define BCHP_TFEC_GR_BRIDGE_1_REG_END                      0x0124930c
+#define BCHP_AFECNX_GLOBAL_0_REG_START                     0x01250000
+#define BCHP_AFECNX_GLOBAL_0_REG_END                       0x01250010
+#define BCHP_AFECNX_0_REG_START                            0x01250100
+#define BCHP_AFECNX_0_REG_END                              0x01250144
+#define BCHP_AFEC0_0_REG_START                             0x01251000
+#define BCHP_AFEC0_0_REG_END                               0x01251a0c
+#define BCHP_AFEC1_0_REG_START                             0x01252000
+#define BCHP_AFEC1_0_REG_END                               0x01252a0c
+#define BCHP_AFEC0_INTR_0_REG_START                        0x01253000
+#define BCHP_AFEC0_INTR_0_REG_END                          0x0125302c
+#define BCHP_AFEC1_INTR_0_REG_START                        0x01253400
+#define BCHP_AFEC1_INTR_0_REG_END                          0x0125342c
+#define BCHP_AFEC_GLOBAL_INTR_0_REG_START                  0x01253800
+#define BCHP_AFEC_GLOBAL_INTR_0_REG_END                    0x0125382c
+#define BCHP_AFEC_GR_BRIDGE_0_REG_START                    0x01254000
+#define BCHP_AFEC_GR_BRIDGE_0_REG_END                      0x0125400c
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_START              0x01270200
+#define BCHP_DEMOD_XPT_MTSIF_TX0_IO_REG_END                0x01270204
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_START              0x01270300
+#define BCHP_DEMOD_XPT_MTSIF_TX1_IO_REG_END                0x01270304
+#define BCHP_DEMOD_XPT_WAKEUP_REG_START                    0x01271000
+#define BCHP_DEMOD_XPT_WAKEUP_REG_END                      0x01271fbc
+#define BCHP_DEMOD_XPT_FE_REG_START                        0x01272000
+#define BCHP_DEMOD_XPT_FE_REG_END                          0x012737fc
+#define BCHP_DS_TOPM_REG_START                             0x01282000
+#define BCHP_DS_TOPM_REG_END                               0x01282068
+#define BCHP_DS_TOPS_REG_START                             0x01283000
+#define BCHP_DS_TOPS_REG_END                               0x0128309c
+#define BCHP_DS_REG_START                                  0x01284000
+#define BCHP_DS_REG_END                                    0x0128509c
+#define BCHP_T2_BICM_SYS_REG_START                         0x01290000
+#define BCHP_T2_BICM_SYS_REG_END                           0x0129001c
+#define BCHP_T2_BICM_INTR2_0_REG_START                     0x01290200
+#define BCHP_T2_BICM_INTR2_0_REG_END                       0x0129022c
+#define BCHP_T2_BICM_INTR2_1_REG_START                     0x01290300
+#define BCHP_T2_BICM_INTR2_1_REG_END                       0x0129032c
+#define BCHP_T2_BICM_CORE_REG_START                        0x01290400
+#define BCHP_T2_BICM_CORE_REG_END                          0x0129068c
+#define BCHP_T2_INTR_REG_START                             0x012a0000
+#define BCHP_T2_INTR_REG_END                               0x012a002c
+#define BCHP_T2_INTR_OI_REG_START                          0x012a0200
+#define BCHP_T2_INTR_OI_REG_END                            0x012a022c
+#define BCHP_T2_GLB_REG_START                              0x012a0400
+#define BCHP_T2_GLB_REG_END                                0x012a04c4
+#define BCHP_T2_FE_REG_START                               0x012a0600
+#define BCHP_T2_FE_REG_END                                 0x012a069c
+#define BCHP_T2_OFDM_REG_START                             0x012a0800
+#define BCHP_T2_OFDM_REG_END                               0x012a0c88
+#define BCHP_T2_FEC_REG_START                              0x012a1000
+#define BCHP_T2_FEC_REG_END                                0x012a10d0
+#define BCHP_T2_OI_REG_START                               0x012a1200
+#define BCHP_T2_OI_REG_END                                 0x012a13b8
+#define BCHP_UFE_AFE_REG_START                             0x012b0000
+#define BCHP_UFE_AFE_REG_END                               0x012b0108
+#define BCHP_SDADC_REG_START                               0x012b0200
+#define BCHP_SDADC_REG_END                                 0x012b0210
+#define BCHP_UFE_MISC_REG_START                            0x012b0600
+#define BCHP_UFE_MISC_REG_END                              0x012b06dc
+#define BCHP_UFE_GR_BRIDGE_REG_START                       0x012b0700
+#define BCHP_UFE_GR_BRIDGE_REG_END                         0x012b070c
+#define BCHP_UFE_MISC2_REG_START                           0x012b0780
+#define BCHP_UFE_MISC2_REG_END                             0x012b07ec
+#define BCHP_UFE_REG_START                                 0x012b0800
+#define BCHP_UFE_REG_END                                   0x012b0868
+#define BCHP_UFE_SAW_REG_START                             0x012b0900
+#define BCHP_UFE_SAW_REG_END                               0x012b0980
+#define BCHP_HRC_REG_START                                 0x012b1000
+#define BCHP_HRC_REG_END                                   0x012b1018
+#define BCHP_DFE_MISCDEC_REG_START                         0x0133c000
+#define BCHP_DFE_MISCDEC_REG_END                           0x0133c18c
+#define BCHP_DFE_UCDEC_REG_START                           0x0133c200
+#define BCHP_DFE_UCDEC_REG_END                             0x0133c2fc
+#define BCHP_DFE_AGCDEC_REG_START                          0x0133c340
+#define BCHP_DFE_AGCDEC_REG_END                            0x0133c7e8
+#define BCHP_DFE_FEDEC_REG_START                           0x0133c800
+#define BCHP_DFE_FEDEC_REG_END                             0x0133cbb8
+#define BCHP_DFE_EQDEC_REG_START                           0x0133cc00
+#define BCHP_DFE_EQDEC_REG_END                             0x0133ced4
+#define BCHP_DFE_FECDEC_REG_START                          0x0133d000
+#define BCHP_DFE_FECDEC_REG_END                            0x0133d0bc
+#define BCHP_DFE_OFSDEC_REG_START                          0x0133d200
+#define BCHP_DFE_OFSDEC_REG_END                            0x0133d234
+#define BCHP_DFE_BERTDEC_REG_START                         0x0133d300
+#define BCHP_DFE_BERTDEC_REG_END                           0x0133d32c
+#define BCHP_DFE_NTSCDEC_REG_START                         0x0133d400
+#define BCHP_DFE_NTSCDEC_REG_END                           0x0133d77c
+#define BCHP_DFE_MFDEC_REG_START                           0x0133e000
+#define BCHP_DFE_MFDEC_REG_END                             0x0133fffc
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_START                 0x01400000
+#define BCHP_RF4CE_CPU_PROG0_MEM_REG_END                   0x0141fffc
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_START                 0x01420000
+#define BCHP_RF4CE_CPU_PROG1_MEM_REG_END                   0x0143fffc
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_START                  0x01440000
+#define BCHP_RF4CE_CPU_DATA_MEM_REG_END                    0x01447ffc
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_START                 0x01450000
+#define BCHP_RF4CE_CPU_CORE_REGS_REG_END                   0x014500fc
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_START                  0x01451000
+#define BCHP_RF4CE_CPU_AUX_REGS_REG_END                    0x01451a08
+#define BCHP_RF4CE_CPU_UART_REG_START                      0x01452000
+#define BCHP_RF4CE_CPU_UART_REG_END                        0x01452ffc
+#define BCHP_RF4CE_CPU_WDG_REG_START                       0x01453000
+#define BCHP_RF4CE_CPU_WDG_REG_END                         0x01453ffc
+#define BCHP_RF4CE_CPU_CTRL_REG_START                      0x01480000
+#define BCHP_RF4CE_CPU_CTRL_REG_END                        0x0148008c
+#define BCHP_RF4CE_CPU_L2_REG_START                        0x01480300
+#define BCHP_RF4CE_CPU_L2_REG_END                          0x01480314
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_START               0x01480500
+#define BCHP_RF4CE_CPU_HOST_STB_L2_REG_END                 0x0148052c
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_START                0x01480800
+#define BCHP_RF4CE_CPU_HOST_CM_L2_REG_END                  0x0148082c
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_START                0x01480a00
+#define BCHP_RF4CE_CPU_HOST_RG_L2_REG_END                  0x01480a2c
+#define BCHP_TX_REG_START                                  0x014c0000
+#define BCHP_TX_REG_END                                    0x014c0020
+#define BCHP_RX_REG_START                                  0x014d0000
+#define BCHP_RX_REG_END                                    0x014d01e0
+#define BCHP_RF_REG_START                                  0x014e0000
+#define BCHP_RF_REG_END                                    0x014e0098
+#define BCHP_VCOCAL_REG_START                              0x014e0100
+#define BCHP_VCOCAL_REG_END                                0x014e0174
+#define BCHP_KVCO_REG_START                                0x014e0200
+#define BCHP_KVCO_REG_END                                  0x014e0224
+#define BCHP_PA_REG_START                                  0x014e0300
+#define BCHP_PA_REG_END                                    0x014e0314
+#define BCHP_MAC_REG_START                                 0x014e0400
+#define BCHP_MAC_REG_END                                   0x014e0564
+#define BCHP_PWR_MGT_L2_REG_START                          0x014e0600
+#define BCHP_PWR_MGT_L2_REG_END                            0x014e0614
+#define BCHP_MISC_L2_REG_START                             0x014e0700
+#define BCHP_MISC_L2_REG_END                               0x014e0714
+#define BCHP_IQCAL_CCA_CCM_L2_REG_START                    0x014e0800
+#define BCHP_IQCAL_CCA_CCM_L2_REG_END                      0x014e0814
+#define BCHP_SYMCNT6_L2_REG_START                          0x014e0900
+#define BCHP_SYMCNT6_L2_REG_END                            0x014e0914
+#define BCHP_TX_DONE_L2_REG_START                          0x014e0a00
+#define BCHP_TX_DONE_L2_REG_END                            0x014e0a14
+#define BCHP_RX_DONE_L2_REG_START                          0x014e0b00
+#define BCHP_RX_DONE_L2_REG_END                            0x014e0b14
+#define BCHP_RX_START_L2_REG_START                         0x014e0c00
+#define BCHP_RX_START_L2_REG_END                           0x014e0c14
+#define BCHP_SYMCNT7_L2_REG_START                          0x014e0d00
+#define BCHP_SYMCNT7_L2_REG_END                            0x014e0d14
+#define BCHP_GCI_0_REG_START                               0x014e1000
+#define BCHP_GCI_0_REG_END                                 0x014e120c
+#define BCHP_GCI_1_REG_START                               0x014e1400
+#define BCHP_GCI_1_REG_END                                 0x014e1604
+#define BCHP_GCI_2_REG_START                               0x014e1800
+#define BCHP_GCI_2_REG_END                                 0x014e1a04
+#define BCHP_MPM_CPU_PROG_MEM_REG_START                    0x01500000
+#define BCHP_MPM_CPU_PROG_MEM_REG_END                      0x0150fffc
+#define BCHP_MPM_CPU_DATA_MEM_REG_START                    0x01510000
+#define BCHP_MPM_CPU_DATA_MEM_REG_END                      0x01513ffc
+#define BCHP_MPM_CPU_CORE_REGS_REG_START                   0x01520000
+#define BCHP_MPM_CPU_CORE_REGS_REG_END                     0x015200fc
+#define BCHP_MPM_CPU_AUX_REGS_REG_START                    0x01522000
+#define BCHP_MPM_CPU_AUX_REGS_REG_END                      0x01523058
+#define BCHP_MPM_UART_REG_START                            0x01580000
+#define BCHP_MPM_UART_REG_END                              0x01580ffc
+#define BCHP_MPM_WDOG_REG_START                            0x01581000
+#define BCHP_MPM_WDOG_REG_END                              0x01581ffc
+#define BCHP_MPM_CPU_L1_REG_START                          0x01582000
+#define BCHP_MPM_CPU_L1_REG_END                            0x01582018
+#define BCHP_MPM_CPU_L2_REG_START                          0x01582100
+#define BCHP_MPM_CPU_L2_REG_END                            0x0158212c
+#define BCHP_MPM_HOST_L2_REG_START                         0x01582200
+#define BCHP_MPM_HOST_L2_REG_END                           0x0158222c
+#define BCHP_MPM_CPU_CTRL_REG_START                        0x01582300
+#define BCHP_MPM_CPU_CTRL_REG_END                          0x01582344
+#define BCHP_MPM_PM_L2_REG_START                           0x01582400
+#define BCHP_MPM_PM_L2_REG_END                             0x0158242c
+#define BCHP_MPM_RANGE_BLOCKER_REG_START                   0x01582500
+#define BCHP_MPM_RANGE_BLOCKER_REG_END                     0x01582554
+#define BCHP_MPM_BSPI_REG_START                            0x01582600
+#define BCHP_MPM_BSPI_REG_END                              0x0158264c
+#define BCHP_MPM_MSPI_REG_START                            0x01582800
+#define BCHP_MPM_MSPI_REG_END                              0x01582984
+#define BCHP_DVP_MT_AON_TOP_REG_START                      0x01583000
+#define BCHP_DVP_MT_AON_TOP_REG_END                        0x0158300c
+#define BCHP_CBUS_INTR2_0_REG_START                        0x01583800
+#define BCHP_CBUS_INTR2_0_REG_END                          0x0158382c
+#define BCHP_CBUS_INTR2_1_REG_START                        0x01583880
+#define BCHP_CBUS_INTR2_1_REG_END                          0x015838ac
+#define BCHP_MT_CBUS_REG_START                             0x01583a00
+#define BCHP_MT_CBUS_REG_END                               0x01583afc
+#define BCHP_MT_MSC_REQ_REG_START                          0x01583b00
+#define BCHP_MT_MSC_REQ_REG_END                            0x01583b6c
+#define BCHP_MT_MSC_RESP_REG_START                         0x01583c00
+#define BCHP_MT_MSC_RESP_REG_END                           0x01583cac
+#define BCHP_MT_DDC_REQ_REG_START                          0x01583d00
+#define BCHP_MT_DDC_REQ_REG_END                            0x01583d6c
+#define BCHP_MPM_FLASH_MEM_REG_START                       0x015c0000
+#define BCHP_MPM_FLASH_MEM_REG_END                         0x015dfffc
+
+
+/***************************************************************************
+ *AUD_FMM_MS_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
+ ***************************************************************************/
+/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK  0xffffffff
+#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
+
+/***************************************************************************
+ *AUD_FMM_OP_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
+ ***************************************************************************/
+/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_MFD_8B
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_MFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_MFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_MFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *BVN_MVFD_VFD_8B
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* BVN_MVFD_VFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD_DCXG_NO_4K
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_DCXG_NO_4K :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_DCXG_NO_4K_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_GFD_DCXG_NO_4K_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *GFD_HSCL_ONLY
+ ***************************************************************************/
+/***************************************************************************
+ *DRAM_DATA_STRUCTURE - DRAM Data Structure
+ ***************************************************************************/
+/* GFD_HSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
+#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
+#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
+
+/***************************************************************************
+ *HIFIDAC_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_02_MUTE_USAGE - Mute usage
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
+ ***************************************************************************/
+/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *M2MC
+ ***************************************************************************/
+/***************************************************************************
+ *TYPE_CLUT_COLOR_DATA - color data for color look up table
+ ***************************************************************************/
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK                  0xff000000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT                 24
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK                    0x00ff0000
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT                   16
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK                  0x0000ff00
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT                 8
+
+/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK                   0x000000ff
+#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT                  0
+
+/***************************************************************************
+ *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK          0xffffffff
+#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT         0
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK              0xf0000000
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT             28
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK          0x0fffffe0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT         5
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK              0x0000001e
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT             1
+
+/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK           0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT          0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid   0
+#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
+
+/***************************************************************************
+ *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
+ ***************************************************************************/
+/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK              0xffff8000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT             15
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK   0x00004000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT  14
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK   0x00002000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT  13
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK         0x00000800
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT        11
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE   1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE  0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK  0x00000400
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK  0x00000200
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK          0x00000100
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT         8
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE   0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK   0x00000020
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT  5
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK     0x00000002
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT    1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK     0x00000001
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT    0
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
+#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
+
+/***************************************************************************
+ *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK        0xffffffff
+#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT       0
+
+/***************************************************************************
+ *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK         0xffffffff
+#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT        0
+
+/***************************************************************************
+ *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK  0xffffffff
+#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
+#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
+
+/***************************************************************************
+ *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
+ ***************************************************************************/
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK              0xe0000000
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT             29
+
+/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK      0x1fffffff
+#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT     0
+
+/***************************************************************************
+ *RAAGA_AX_MISC
+ ***************************************************************************/
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG0 - Cluster Package Data Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG0 :: ADDRESS_UPLEFTMB [63:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_UPLEFTMB_MASK 0xffffffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_UPLEFTMB_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG0 :: ADDRESS_LEFTMB [31:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_LEFTMB_MASK 0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG0_ADDRESS_LEFTMB_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG1 - Cluster Package Data Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: OFFSET_REFERENCE [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_REFERENCE_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_REFERENCE_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: OFFSET_BVN_INPUT [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_BVN_INPUT_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_OFFSET_BVN_INPUT_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG1 :: ADDRESS_MBINFO [31:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_ADDRESS_MBINFO_MASK 0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG1_ADDRESS_MBINFO_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG2 - Cluster Package Data Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_TEMPORAL_LEFT [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_LEFT_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_LEFT_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_TEMPORAL_UPLEFT [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_UPLEFT_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_TEMPORAL_UPLEFT_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_SPATIAL_LEFT [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_LEFT_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_LEFT_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG2 :: OFFSET_MV_SPATIAL_UPLEFT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_UPLEFT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG2_OFFSET_MV_SPATIAL_UPLEFT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG3 - Cluster Package Data Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_SCALEFACTOR [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_SCALEFACTOR_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_SCALEFACTOR_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_PRED_PIXELS [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_PRED_PIXELS_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_PRED_PIXELS_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_INPUT_420 [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_INPUT_420_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_INPUT_420_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG3 :: OFFSET_MV_TEMPORAL_DOWNLEFT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_MV_TEMPORAL_DOWNLEFT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG3_OFFSET_MV_TEMPORAL_DOWNLEFT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG4 - Cluster Package Data Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_CB_READ [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_CB_READ_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_CB_READ_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_LUMA_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_INTRA_LUMA_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_INTRA_LUMA_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG4 :: OFFSET_CHROMA_REF [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_CHROMA_REF_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG4_OFFSET_CHROMA_REF_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG5 - Cluster Package Data Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_QUANT_OUTPUT [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_QUANT_OUTPUT_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_QUANT_OUTPUT_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CR_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CR_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CR_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG5 :: OFFSET_INTRA_CB_WRITE [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CB_WRITE_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG5_OFFSET_INTRA_CB_WRITE_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG6 - Cluster Package Data Structure Register 6
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_CR_TOP_WRITE [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CR_TOP_WRITE_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CR_TOP_WRITE_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_CB_TOP_WRITE [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CB_TOP_WRITE_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_CB_TOP_WRITE_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_LUMA_TOP_WRITE [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_LUMA_TOP_WRITE_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_LUMA_TOP_WRITE_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG6 :: OFFSET_DEBLOCK_INPUT [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_INPUT_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG6_OFFSET_DEBLOCK_INPUT_SHIFT 0
+
+/***************************************************************************
+ *CLUSTER_PACKAGE_REG7 - Cluster Package Data Structure Register 7
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_OUTPUT_INDEX [63:48] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_OUTPUT_INDEX_MASK 0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_OUTPUT_INDEX_SHIFT 48
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_CR_TOP_READ [47:32] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CR_TOP_READ_MASK 0x0000ffff00000000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CR_TOP_READ_SHIFT 32
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_CB_TOP_READ [31:16] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CB_TOP_READ_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_CB_TOP_READ_SHIFT 16
+
+/* RAAGA_AX_MISC :: CLUSTER_PACKAGE_REG7 :: OFFSET_DEBLOCK_LUMA_TOP_READ [15:00] */
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_LUMA_TOP_READ_MASK 0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_CLUSTER_PACKAGE_REG7_OFFSET_DEBLOCK_LUMA_TOP_READ_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG0 - Private MB Info Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: reserved0 [63:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_reserved0_MASK     0xfff0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_reserved0_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_MODE_LUMA [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_MODE_LUMA_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_MODE_LUMA_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_COLUMN_NUMBER [47:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_COLUMN_NUMBER_MASK 0x0000ff0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_COLUMN_NUMBER_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: MB_ROW_NUMBER [39:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_ROW_NUMBER_MASK 0x000000ff00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_MB_ROW_NUMBER_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG0 :: BEST_SAD [31:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_BEST_SAD_MASK      0x00000000ffffffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG0_BEST_SAD_SHIFT     0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG1 - Private MB Info Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_7 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_7_MASK  0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_7_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_6 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_6_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_6_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_5 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_5_MASK  0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_5_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_4 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_4_MASK  0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_4_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_3_MASK  0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_3_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_2_MASK  0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_2_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_1_MASK  0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_1_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG1 :: I4X4_PMODE_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_0_MASK  0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG1_I4X4_PMODE_0_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG2 - Private MB Info Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_15 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_15_MASK 0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_15_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_14 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_14_MASK 0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_14_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_13 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_13_MASK 0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_13_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_12 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_12_MASK 0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_12_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_11 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_11_MASK 0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_11_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_10 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_10_MASK 0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_10_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_9 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_9_MASK  0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_9_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG2 :: I4X4_PMODE_8 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_8_MASK  0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG2_I4X4_PMODE_8_SHIFT 0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG3 - Private MB Info Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_7 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_7_MASK   0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_7_SHIFT  56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_6 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_6_MASK   0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_6_SHIFT  48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_5 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_5_MASK   0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_5_SHIFT  40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_4 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_4_MASK   0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_4_SHIFT  32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_3_MASK   0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_3_SHIFT  24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_2_MASK   0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_2_SHIFT  16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_1_MASK   0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_1_SHIFT  8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG3 :: I4X4_MODE_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_0_MASK   0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG3_I4X4_MODE_0_SHIFT  0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG4 - Private MB Info Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved0_MASK     0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved0_SHIFT    60
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_15 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_15_MASK  0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_15_SHIFT 56
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved1_MASK     0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved1_SHIFT    52
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_14 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_14_MASK  0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_14_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved2_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved2_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_13 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_13_MASK  0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_13_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved3_MASK     0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved3_SHIFT    36
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_12 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_12_MASK  0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_12_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved4_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved4_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_11 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_11_MASK  0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_11_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved5_MASK     0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved5_SHIFT    20
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_10 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_10_MASK  0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_10_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved6_MASK     0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved6_SHIFT    12
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_9 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_9_MASK   0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_9_SHIFT  8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved7_MASK     0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_reserved7_SHIFT    4
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG4 :: I4X4_MODE_8 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_8_MASK   0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG4_I4X4_MODE_8_SHIFT  0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG5 - Private MB Info Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: LAMBDA_GENAX [63:48] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_GENAX_MASK  0xffff000000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_GENAX_SHIFT 48
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved0 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved0_MASK     0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved0_SHIFT    44
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_Y_COUNT [43:40] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_COUNT_MASK 0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_COUNT_SHIFT 40
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved1 [39:33] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved1_MASK     0x000000fe00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved1_SHIFT    33
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_Y_DIR [32:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_DIR_MASK 0x0000000100000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_Y_DIR_SHIFT 32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved2 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved2_MASK     0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved2_SHIFT    28
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_X_COUNT [27:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_COUNT_MASK 0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_COUNT_SHIFT 24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: reserved3 [23:17] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved3_MASK     0x0000000000fe0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_reserved3_SHIFT    17
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: MC_CHROMA_SHIFT_X_DIR [16:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_DIR_MASK 0x0000000000010000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_MC_CHROMA_SHIFT_X_DIR_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG5 :: LAMBDA [15:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_MASK        0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG5_LAMBDA_SHIFT       0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG6 - Private MB Info Structure Register 6
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved0 [63:38] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved0_MASK     0xffffffc000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved0_SHIFT    38
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_2 [37:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_2_MASK      0x0000003f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_2_SHIFT     32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved1 [31:30] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved1_MASK     0x00000000c0000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved1_SHIFT    30
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_1 [29:24] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_1_MASK      0x000000003f000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_1_SHIFT     24
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: reserved2 [23:22] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved2_MASK     0x0000000000c00000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_reserved2_SHIFT    22
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: UP_QPS_0 [21:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_0_MASK      0x00000000003f0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_UP_QPS_0_SHIFT     16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: LUMA_VARIANCE [15:08] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_VARIANCE_MASK 0x000000000000ff00
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_VARIANCE_SHIFT 8
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG6 :: LUMA_MEAN [07:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_MEAN_MASK     0x00000000000000ff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG6_LUMA_MEAN_SHIFT    0
+
+/***************************************************************************
+ *PRIVATE_MB_INFO_REG7 - Private MB Info Structure Register 7
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: reserved0 [63:38] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_reserved0_MASK     0xffffffc000000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_reserved0_SHIFT    38
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: AVE_QPS [37:32] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVE_QPS_MASK       0x0000003f00000000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVE_QPS_SHIFT      32
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: AVG_ZONAL_BITS [31:16] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVG_ZONAL_BITS_MASK 0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_AVG_ZONAL_BITS_SHIFT 16
+
+/* RAAGA_AX_MISC :: PRIVATE_MB_INFO_REG7 :: TEXTURE_BITS [15:00] */
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_TEXTURE_BITS_MASK  0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PRIVATE_MB_INFO_REG7_TEXTURE_BITS_SHIFT 0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG0 - Public MB Info Structure Register 0
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved0 [63:62] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved0_MASK      0xc000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved0_SHIFT     62
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: INTRA_QP [61:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_INTRA_QP_MASK       0x3f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_INTRA_QP_SHIFT      56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved1 [55:54] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved1_MASK      0x00c0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved1_SHIFT     54
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: QP [53:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_QP_MASK             0x003f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_QP_SHIFT            48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved2 [47:46] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved2_MASK      0x0000c00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved2_SHIFT     46
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: CBP [45:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBP_MASK            0x00003f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBP_SHIFT           40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved3_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved3_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: MB_MODE_CHROMA [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_MB_MODE_CHROMA_MASK 0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_MB_MODE_CHROMA_SHIFT 32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: reserved4 [31:27] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved4_MASK      0x00000000f8000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_reserved4_SHIFT     27
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG0 :: CBF [26:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBF_MASK            0x0000000007ffffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG0_CBF_SHIFT           0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG1 - Public MB Info Structure Register 1
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: reserved0 [63:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_reserved0_MASK      0xffffffff00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_reserved0_SHIFT     32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: MVD_Y [31:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_Y_MASK          0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_Y_SHIFT         16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG1 :: MVD_X [15:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_X_MASK          0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG1_MVD_X_SHIFT         0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG2 - Public MB Info Structure Register 2
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved0 [63:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved0_MASK      0xffe0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved0_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MB_TYPE [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_MASK        0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_SHIFT       48
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_I4X4        0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_I16X16      1
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_P16X16      2
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_PSKIP       3
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_IPCM        5
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_TYPE_DUMMY       31
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved1 [47:41] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved1_MASK      0x0000fe0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved1_SHIFT     41
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MB_AVAILABLE [40:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_AVAILABLE_MASK   0x0000010000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MB_AVAILABLE_SHIFT  40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: reserved2 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved2_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_reserved2_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: REF_ID [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_REF_ID_MASK         0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_REF_ID_SHIFT        32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MV_Y [31:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_Y_MASK           0x00000000ffff0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_Y_SHIFT          16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG2 :: MV_X [15:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_X_MASK           0x000000000000ffff
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG2_MV_X_SHIFT          0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG3 - Public MB Info Structure Register 3
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved0 [63:61] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved0_MASK      0xe000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved0_SHIFT     61
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_7 [60:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_7_MASK     0x1f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_7_SHIFT    56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved1 [55:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved1_MASK      0x00e0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved1_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_6 [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_6_MASK     0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_6_SHIFT    48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved2 [47:45] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved2_MASK      0x0000e00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved2_SHIFT     45
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_5 [44:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_5_MASK     0x00001f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_5_SHIFT    40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved3 [39:37] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved3_MASK      0x000000e000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved3_SHIFT     37
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_4 [36:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_4_MASK     0x0000001f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_4_SHIFT    32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved4 [31:29] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved4_MASK      0x00000000e0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved4_SHIFT     29
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_3 [28:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_3_MASK     0x000000001f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_3_SHIFT    24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved5 [23:21] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved5_MASK      0x0000000000e00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved5_SHIFT     21
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_2 [20:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_2_MASK     0x00000000001f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_2_SHIFT    16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved6 [15:13] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved6_MASK      0x000000000000e000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved6_SHIFT     13
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_1 [12:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_1_MASK     0x0000000000001f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_1_SHIFT    8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: reserved7 [07:05] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved7_MASK      0x00000000000000e0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_reserved7_SHIFT     5
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG3 :: COEFFNUM_0 [04:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_0_MASK     0x000000000000001f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG3_COEFFNUM_0_SHIFT    0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG4 - Public MB Info Structure Register 4
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved0 [63:61] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved0_MASK      0xe000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved0_SHIFT     61
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_15 [60:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_15_MASK    0x1f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_15_SHIFT   56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved1 [55:53] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved1_MASK      0x00e0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved1_SHIFT     53
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_14 [52:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_14_MASK    0x001f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_14_SHIFT   48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved2 [47:45] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved2_MASK      0x0000e00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved2_SHIFT     45
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_13 [44:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_13_MASK    0x00001f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_13_SHIFT   40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved3 [39:37] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved3_MASK      0x000000e000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved3_SHIFT     37
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_12 [36:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_12_MASK    0x0000001f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_12_SHIFT   32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved4 [31:29] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved4_MASK      0x00000000e0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved4_SHIFT     29
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_11 [28:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_11_MASK    0x000000001f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_11_SHIFT   24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved5 [23:21] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved5_MASK      0x0000000000e00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved5_SHIFT     21
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_10 [20:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_10_MASK    0x00000000001f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_10_SHIFT   16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved6 [15:13] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved6_MASK      0x000000000000e000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved6_SHIFT     13
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_9 [12:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_9_MASK     0x0000000000001f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_9_SHIFT    8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: reserved7 [07:05] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved7_MASK      0x00000000000000e0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_reserved7_SHIFT     5
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG4 :: COEFFNUM_8 [04:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_8_MASK     0x000000000000001f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG4_COEFFNUM_8_SHIFT    0
+
+/***************************************************************************
+ *PUBLIC_MB_INFO_REG5 - Public MB Info Structure Register 5
+ ***************************************************************************/
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved0 [63:60] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved0_MASK      0xf000000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved0_SHIFT     60
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_3 [59:56] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_3_MASK         0x0f00000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_3_SHIFT        56
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved1 [55:52] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved1_MASK      0x00f0000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved1_SHIFT     52
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_2 [51:48] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_2_MASK         0x000f000000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_2_SHIFT        48
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved2 [47:44] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved2_MASK      0x0000f00000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved2_SHIFT     44
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_1 [43:40] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_1_MASK         0x00000f0000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_1_SHIFT        40
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved3 [39:36] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved3_MASK      0x000000f000000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved3_SHIFT     36
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: LEFT_0 [35:32] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_0_MASK         0x0000000f00000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_LEFT_0_SHIFT        32
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved4 [31:28] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved4_MASK      0x00000000f0000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved4_SHIFT     28
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_3 [27:24] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_3_MASK          0x000000000f000000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_3_SHIFT         24
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved5 [23:20] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved5_MASK      0x0000000000f00000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved5_SHIFT     20
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_2 [19:16] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_2_MASK          0x00000000000f0000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_2_SHIFT         16
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved6 [15:12] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved6_MASK      0x000000000000f000
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved6_SHIFT     12
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_1 [11:08] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_1_MASK          0x0000000000000f00
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_1_SHIFT         8
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: reserved7 [07:04] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved7_MASK      0x00000000000000f0
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_reserved7_SHIFT     4
+
+/* RAAGA_AX_MISC :: PUBLIC_MB_INFO_REG5 :: TOP_0 [03:00] */
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_0_MASK          0x000000000000000f
+#define BCHP_RAAGA_AX_MISC_PUBLIC_MB_INFO_REG5_TOP_0_SHIFT         0
+
+/***************************************************************************
+ *RAAGA_REGSET_DSP_CFG
+ ***************************************************************************/
+/***************************************************************************
+ *AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
+
+/***************************************************************************
+ *AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
+
+/***************************************************************************
+ *AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK    0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off     0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On      1
+
+/***************************************************************************
+ *AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
+
+/***************************************************************************
+ *AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
+
+/***************************************************************************
+ *AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK  0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt  1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo  2
+
+/***************************************************************************
+ *AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
+
+/***************************************************************************
+ *AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
+
+/***************************************************************************
+ *AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK       0xffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT      0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
+
+/***************************************************************************
+ *AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
+
+/***************************************************************************
+ *AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK  0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
+
+/***************************************************************************
+ *AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK     0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT    0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo   2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono     1
+
+/***************************************************************************
+ *AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
+
+/***************************************************************************
+ *LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
+#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
+
+/***************************************************************************
+ *MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK    0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT   0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono    1
+
+/***************************************************************************
+ *MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
+ ***************************************************************************/
+/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK   0xffffffff
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT  0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
+#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
+
+/***************************************************************************
+ *RDC
+ ***************************************************************************/
+/***************************************************************************
+ *RUL - RUL Command.
+ ***************************************************************************/
+/* RDC :: RUL :: opcode [31:24] */
+#define BCHP_RDC_RUL_opcode_MASK                                   0xff000000
+#define BCHP_RDC_RUL_opcode_SHIFT                                  24
+#define BCHP_RDC_RUL_opcode_NOP                                    0
+#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM                          1
+#define BCHP_RDC_RUL_opcode_REG_WRITE                              2
+#define BCHP_RDC_RUL_opcode_REG_READ                               3
+#define BCHP_RDC_RUL_opcode_LOAD_IMM                               4
+#define BCHP_RDC_RUL_opcode_WINDOW_WRITE                           5
+#define BCHP_RDC_RUL_opcode_BLOCK_WRITE                            6
+#define BCHP_RDC_RUL_opcode_WINDOW_COPY                            7
+#define BCHP_RDC_RUL_opcode_BLOCK_COPY                             8
+#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK                        9
+#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW                        10
+#define BCHP_RDC_RUL_opcode_AND                                    11
+#define BCHP_RDC_RUL_opcode_AND_IMM                                12
+#define BCHP_RDC_RUL_opcode_OR                                     13
+#define BCHP_RDC_RUL_opcode_OR_IMM                                 14
+#define BCHP_RDC_RUL_opcode_XOR                                    15
+#define BCHP_RDC_RUL_opcode_XOR_IMM                                16
+#define BCHP_RDC_RUL_opcode_NOT                                    17
+#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT                           18
+#define BCHP_RDC_RUL_opcode_SUM                                    19
+#define BCHP_RDC_RUL_opcode_SUM_IMM                                20
+#define BCHP_RDC_RUL_opcode_COND_SKIP                              21
+#define BCHP_RDC_RUL_opcode_SKIP                                   22
+#define BCHP_RDC_RUL_opcode_EXIT                                   23
+#define BCHP_RDC_RUL_opcode_WAIT_EOP                               24
+#define BCHP_RDC_RUL_opcode_PLACEHOLDER                            255
+
+/* RDC :: RUL :: reserved0 [23:23] */
+#define BCHP_RDC_RUL_reserved0_MASK                                0x00800000
+#define BCHP_RDC_RUL_reserved0_SHIFT                               23
+
+/* union - case rdc_args [22:00] */
+/* RDC :: RUL :: rdc_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_rdc_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: rdc_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_rdc_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_rdc_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: rdc_args :: src2 [11:06] */
+#define BCHP_RDC_RUL_rdc_args_src2_MASK                            0x00000fc0
+#define BCHP_RDC_RUL_rdc_args_src2_SHIFT                           6
+
+/* RDC :: RUL :: rdc_args :: dest [05:00] */
+#define BCHP_RDC_RUL_rdc_args_dest_MASK                            0x0000003f
+#define BCHP_RDC_RUL_rdc_args_dest_SHIFT                           0
+
+/* union - case reg_args [22:00] */
+/* RDC :: RUL :: reg_args :: rotation [22:18] */
+#define BCHP_RDC_RUL_reg_args_rotation_MASK                        0x007c0000
+#define BCHP_RDC_RUL_reg_args_rotation_SHIFT                       18
+
+/* RDC :: RUL :: reg_args :: src1 [17:12] */
+#define BCHP_RDC_RUL_reg_args_src1_MASK                            0x0003f000
+#define BCHP_RDC_RUL_reg_args_src1_SHIFT                           12
+
+/* RDC :: RUL :: reg_args :: count [11:00] */
+#define BCHP_RDC_RUL_reg_args_count_MASK                           0x00000fff
+#define BCHP_RDC_RUL_reg_args_count_SHIFT                          0
+
+/* union - case eop_args [22:00] */
+/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
+#define BCHP_RDC_RUL_eop_args_reserved0_MASK                       0x007fff00
+#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT                      8
+
+/* RDC :: RUL :: eop_args :: eop [07:00] */
+#define BCHP_RDC_RUL_eop_args_eop_MASK                             0x000000ff
+#define BCHP_RDC_RUL_eop_args_eop_SHIFT                            0
+
+/***************************************************************************
+ *EOP_ID_256 - EOP_ID
+ ***************************************************************************/
+/* RDC :: EOP_ID_256 :: eop_id [255:00] */
+#define BCHP_RDC_EOP_ID_256_eop_id_MASK                            0x0000000000000000000000000000000000000000000000000000000000000000
+#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT                           0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0                    0
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1                    1
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2                    2
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3                    3
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4                    4
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5                    5
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6                    6
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7                    7
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0                    8
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1                    9
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2                    10
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3                    11
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4                    12
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5                    13
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6                    14
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7                    15
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0                    16
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1                    17
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2                    18
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3                    19
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4                    20
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5                    21
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6                    22
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7                    23
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0                   24
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1                   25
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2                   26
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3                   27
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4                   28
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5                   29
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6                   30
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0                    31
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0                   32
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1                   33
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2                   34
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3                   35
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4                   36
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5                   37
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6                   38
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7                   39
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0                    40
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0                   41
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be                    42
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0                   43
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_0                   44
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_1                   45
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0               46
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1               47
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0                    48
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1                    49
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2                    50
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3                    51
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4                    52
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5                    53
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6                    54
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7                    55
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8                    56
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9                    57
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10                   58
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11                   59
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12                   60
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13                   61
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2               62
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3               63
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0                           64
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1                           65
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2                           66
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3                           67
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4                           68
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5                           69
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6                           70
+#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7                           71
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0                           72
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1                           73
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2                           74
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3                           75
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4                           76
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5                           77
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6                           78
+#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7                           79
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_0                           80
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_1                           81
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_2                           82
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_3                           83
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_4                           84
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_5                           85
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_6                           86
+#define BCHP_RDC_EOP_ID_256_eop_id_cap_7                           87
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0                           88
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1                           89
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2                           90
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3                           91
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4                           92
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5                           93
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6                           94
+#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7                           95
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_0                           96
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_1                           97
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_2                           98
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_3                           99
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_4                           100
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_5                           101
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_6                           102
+#define BCHP_RDC_EOP_ID_256_eop_id_scl_7                           103
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_0                          104
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_1                          105
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_2                          106
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_3                          107
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_4                          108
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_5                          109
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_6                          110
+#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_7                          111
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0                           112
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1                           113
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2                           114
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3                           115
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4                           116
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5                           117
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6                           118
+#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7                           119
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0                           120
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1                           121
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2                           122
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3                           123
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4                           124
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5                           125
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6                           126
+#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7                           127
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0                           128
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1                           129
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2                           130
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3                           131
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4                           132
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5                           133
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6                           134
+#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7                           135
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0                        136
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1                        137
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2                        138
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3                        139
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4                        140
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5                        141
+#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6                        142
+#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0                           143
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_0                           144
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_1                           145
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_2                           146
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_3                           147
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_4                           148
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_5                           149
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_6                           150
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_7                           151
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0                          152
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1                          153
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2                          154
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3                          155
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4                          156
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5                          157
+#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6                          158
+#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0                           159
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_0                           160
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_1                           161
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_2                           162
+#define BCHP_RDC_EOP_ID_256_eop_id_crc_3                           163
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_0                          164
+#define BCHP_RDC_EOP_ID_256_eop_id_hist_1                          165
+#define BCHP_RDC_EOP_ID_256_eop_id_psm_0                           166
+#define BCHP_RDC_EOP_ID_256_eop_id_plm_0                           167
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0                    168
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1                    169
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2                    170
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3                    171
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4                    172
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5                    173
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6                    174
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7                    175
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0                    176
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1                    177
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2                    178
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3                    179
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0                   180
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1                   181
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0                    182
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0                    183
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0                 184
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0                 185
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0                 186
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0                 187
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0                 188
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0                 189
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0                 190
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0                 191
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1                 192
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1                 193
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1                 194
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1                 195
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1                 196
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1                 197
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1                 198
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1                 199
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0                   200
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1                   201
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2                   202
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3                   203
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4                   204
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5                   205
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6                   206
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7                   207
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0                   208
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0                    209
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0               210
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1               211
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2               212
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3               213
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4               214
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5               215
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0               216
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1               217
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2               218
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3               219
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4               220
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5               221
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6               222
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7               223
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8               224
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9               225
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10              226
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11              227
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12              228
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13              229
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_14              230
+#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9               231
+#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0                           232
+#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0                          233
+#define BCHP_RDC_EOP_ID_256_eop_id_v0_be                           234
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0                      235
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_1                      236
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2                      237
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3                      238
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4                      239
+#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0                          240
+#define BCHP_RDC_EOP_ID_256_eop_id_frc_0                           241
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0                          242
+#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0                          243
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5                      244
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6                      245
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7                      246
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8                      247
+#define BCHP_RDC_EOP_ID_256_eop_id_tntd_0                          248
+#define BCHP_RDC_EOP_ID_256_eop_id_vec_hddvi_0_passthr             249
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11                     250
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12                     251
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13                     252
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14                     253
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15                     254
+#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16                     255
+
+/***************************************************************************
+ *SPDIF_RCVR_CTRL
+ ***************************************************************************/
+/***************************************************************************
+ *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
+ ***************************************************************************/
+/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
+#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
+
+/***************************************************************************
+ *XPT_RAVE
+ ***************************************************************************/
+/***************************************************************************
+ *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
+
+/***************************************************************************
+ *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
+
+/***************************************************************************
+ *NOTEC_PES_LAYER_SELECTION - PES Layer Selection
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
+ ***************************************************************************/
+/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
+
+/***************************************************************************
+ *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
+
+/***************************************************************************
+ *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
+ ***************************************************************************/
+/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
+#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
+
+#endif /* #ifndef BCHP_COMMON_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_ebi.h b/include/linux/brcmstb/7364a0/bchp_ebi.h
new file mode 100644
index 000000000000..30650bea8cf8
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_ebi.h
@@ -0,0 +1,2007 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:38 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_EBI_H__
+#define BCHP_EBI_H__
+
+/***************************************************************************
+ *EBI - EBI Registers
+ ***************************************************************************/
+#define BCHP_EBI_CS_BASE_HI_0                    0x00440800 /* Upper 8-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_BASE_0                       0x00440804 /* Lower 32-bit of EBI CS Base 0 Register */
+#define BCHP_EBI_CS_CONFIG_0                     0x00440808 /* EBI CS Config 0 Register */
+#define BCHP_EBI_CS_BASE_HI_1                    0x0044080c /* Upper 8-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_BASE_1                       0x00440810 /* Lower 32-bit of EBI CS Base 1 Register */
+#define BCHP_EBI_CS_CONFIG_1                     0x00440814 /* EBI CS Config 1 Register */
+#define BCHP_EBI_CS_BASE_HI_2                    0x00440818 /* Upper 8-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_BASE_2                       0x0044081c /* Lower 32-bit of EBI CS Base 2 Register */
+#define BCHP_EBI_CS_CONFIG_2                     0x00440820 /* EBI CS Config 2 Register */
+#define BCHP_EBI_CS_BASE_HI_3                    0x00440824 /* Upper 8-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_BASE_3                       0x00440828 /* Lower 32-bit of EBI CS Base 3 Register */
+#define BCHP_EBI_CS_CONFIG_3                     0x0044082c /* EBI CS Config 3 Register */
+#define BCHP_EBI_CS_BASE_HI_4                    0x00440830 /* Upper 8-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_BASE_4                       0x00440834 /* Lower 32-bit of EBI CS Base 4 Register */
+#define BCHP_EBI_CS_CONFIG_4                     0x00440838 /* EBI CS Config 4 Register */
+#define BCHP_EBI_CS_BASE_HI_5                    0x0044083c /* Upper 8-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_BASE_5                       0x00440840 /* Lower 32-bit of EBI CS Base 5 Register */
+#define BCHP_EBI_CS_CONFIG_5                     0x00440844 /* EBI CS Config 5 Register */
+#define BCHP_EBI_CS_BASE_HI_6                    0x00440848 /* Upper 8-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_BASE_6                       0x0044084c /* Lower 32-bit of EBI CS Base 6 Register */
+#define BCHP_EBI_CS_CONFIG_6                     0x00440850 /* EBI CS Config 6 Register */
+#define BCHP_EBI_BURST_CFG_0                     0x00440860 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_1                     0x00440864 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_2                     0x00440868 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_3                     0x0044086c /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_4                     0x00440870 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_5                     0x00440874 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_BURST_CFG_6                     0x00440878 /* EBI Synchronous Intel StrataFlash Burst Configure Register */
+#define BCHP_EBI_ECR                             0x00440900 /* EBI Configuration Register */
+#define BCHP_EBI_CS_TRISTATE_CFG                 0x00440918 /* EBI CS Tristate Configuration Register */
+#define BCHP_EBI_CS_SPI_SELECT                   0x00440920 /* SPI CS Select */
+#define BCHP_EBI_ARRAY_ADDRESS                   0x004409f0 /* EBI Data Array Address */
+
+/***************************************************************************
+ *CS_BASE_HI_0 - Upper 8-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_0 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_0_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_0 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_0_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_0 - Lower 32-bit of EBI CS Base 0 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_0 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_0_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_0_base_addr_SHIFT                         13
+
+/* EBI :: CS_BASE_0 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_0_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_0_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_0 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_0_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_0_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_0_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_0_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_0_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_0_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_0_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_0_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_0_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_0_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_0_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_0_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_0 - EBI CS Config 0 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_0 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_0_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_0_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_0_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_0_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_0_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_0_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_0_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_0 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_0_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_0_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_0_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_0 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_0_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_0_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_0_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_0_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_0_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_0_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_0_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_0_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_0_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_0_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_0_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_0_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_0_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_0_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_0 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_0_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_0_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_0_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_0_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_0_le_SHIFT                              10
+
+/* EBI :: CS_CONFIG_0 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_0_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_0_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_0_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_0_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_0 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_0_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_0_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_0_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_0_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_0_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_0_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_0 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_0_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_0_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_0_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_0 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_0_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_0_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_0_dest_size_SHIFT                       4
+
+/* EBI :: CS_CONFIG_0 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_0_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_0_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_0 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_0_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_0_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_0_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_0 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_0_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_0_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_0_enable_DEFAULT                        0x00000001
+
+/***************************************************************************
+ *CS_BASE_HI_1 - Upper 8-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_1 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_1_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_1 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_1_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_1 - Lower 32-bit of EBI CS Base 1 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_1 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_1_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_1_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_1_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_1 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_1_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_1_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_1 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_1_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_1_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_1_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_1_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_1_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_1_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_1_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_1_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_1_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_1_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_1_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_1_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_1_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_1 - EBI CS Config 1 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_1 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_1_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_1_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_1_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_1_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_1_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_1_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_1_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_1_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_1_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_1_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_1 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_1_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_1_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_1_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_1_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_1_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_1_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_1_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_1_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_1_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_1_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_1_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_1_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_1_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_1_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_1_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_1_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_1_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_1_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_1_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_1_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_1 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_1_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_1_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_1_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_1_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_1 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_1_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_1_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_1_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_1_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_1_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_1_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_1 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_1_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_1_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_1_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_1 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_1_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_1_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_1_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_1_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_1_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_1_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_1 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_1_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_1_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_1_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_1 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_1_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_1_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_1_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_2 - Upper 8-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_2 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_2_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_2 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_2_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_2 - Lower 32-bit of EBI CS Base 2 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_2 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_2_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_2_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_2_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_2 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_2_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_2_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_2 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_2_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_2_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_2_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_2_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_2_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_2_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_2_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_2_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_2_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_2_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_2_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_2_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_2_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_2 - EBI CS Config 2 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_2 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_2_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_2_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_2_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_2_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_2_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_2_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_2_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_2_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_2_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_2_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_2 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_2_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_2_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_2_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_2_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_2_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_2_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_2_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_2_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_2_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_2_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_2_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_2_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_2_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_2_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_2_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_2_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_2_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_2_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_2_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_2_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_2 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_2_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_2_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_2_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_2_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_2 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_2_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_2_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_2_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_2_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_2_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_2_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_2 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_2_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_2_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_2_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_2 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_2_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_2_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_2_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_2_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_2_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_2_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_2 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_2_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_2_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_2_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_2 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_2_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_2_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_2_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_3 - Upper 8-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_3 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_3_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_3 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_3_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_3 - Lower 32-bit of EBI CS Base 3 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_3 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_3_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_3_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_3_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_3 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_3_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_3_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_3 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_3_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_3_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_3_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_3_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_3_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_3_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_3_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_3_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_3_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_3_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_3_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_3_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_3_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_3 - EBI CS Config 3 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_3 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_3_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_3_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_3_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_3_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_3_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_3_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_3_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_3_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_3_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_3_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_3 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_3_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_3_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_3_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_3_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_3_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_3_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_3_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_3_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_3_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_3_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_3_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_3_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_3_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_3_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_3_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_3_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_3_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_3_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_3_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_3_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_3 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_3_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_3_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_3_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_3_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_3 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_3_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_3_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_3_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_3_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_3_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_3_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_3 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_3_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_3_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_3_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_3 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_3_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_3_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_3_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_3_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_3_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_3_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_3 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_3_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_3_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_3_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_3 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_3_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_3_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_3_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_4 - Upper 8-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_4 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_4_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_4 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_4_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_4 - Lower 32-bit of EBI CS Base 4 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_4 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_4_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_4_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_4_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_4 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_4_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_4_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_4 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_4_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_4_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_4_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_4_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_4_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_4_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_4_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_4_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_4_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_4_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_4_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_4_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_4_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_4 - EBI CS Config 4 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_4 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_4_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_4_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_4_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_4_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_4_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_4_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_4_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_4_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_4_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_4_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_4 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_4_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_4_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_4_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_4_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_4_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_4_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_4_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_4_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_4_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_4_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_4_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_4_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_4_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_4_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_4_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_4_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_4_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_4_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_4_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_4_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_4 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_4_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_4_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_4_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_4_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_4 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_4_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_4_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_4_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_4_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_4_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_4_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_4 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_4_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_4_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_4_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_4 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_4_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_4_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_4_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_4_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_4_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_4_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_4 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_4_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_4_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_4_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_4 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_4_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_4_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_4_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_5 - Upper 8-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_5 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_5_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_5 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_5_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_5 - Lower 32-bit of EBI CS Base 5 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_5 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_5_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_5_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_5_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_5 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_5_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_5_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_5 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_5_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_5_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_5_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_5_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_5_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_5_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_5_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_5_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_5_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_5_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_5_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_5_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_5_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_5 - EBI CS Config 5 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_5 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_5_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_5_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_5_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_5_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_5_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_5_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_5_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_5_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_5_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_5_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_5 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_5_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_5_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_5_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_5_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_5_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_5_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_5_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_5_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_5_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_5_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_5_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_5_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_5_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_5_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_5_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_5_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_5_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_5_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_5_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_5_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_5 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_5_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_5_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_5_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_5_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_5 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_5_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_5_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_5_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_5_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_5_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_5_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_5 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_5_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_5_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_5_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_5 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_5_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_5_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_5_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_5_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_5_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_5_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_5 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_5_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_5_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_5_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_5 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_5_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_5_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_5_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *CS_BASE_HI_6 - Upper 8-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_HI_6 :: reserved0 [31:08] */
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_MASK                       0xffffff00
+#define BCHP_EBI_CS_BASE_HI_6_reserved0_SHIFT                      8
+
+/* EBI :: CS_BASE_HI_6 :: base_addr_hi [07:00] */
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_MASK                    0x000000ff
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_SHIFT                   0
+#define BCHP_EBI_CS_BASE_HI_6_base_addr_hi_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *CS_BASE_6 - Lower 32-bit of EBI CS Base 6 Register
+ ***************************************************************************/
+/* EBI :: CS_BASE_6 :: base_addr [31:13] */
+#define BCHP_EBI_CS_BASE_6_base_addr_MASK                          0xffffe000
+#define BCHP_EBI_CS_BASE_6_base_addr_SHIFT                         13
+#define BCHP_EBI_CS_BASE_6_base_addr_DEFAULT                       0x00000000
+
+/* EBI :: CS_BASE_6 :: reserved0 [12:04] */
+#define BCHP_EBI_CS_BASE_6_reserved0_MASK                          0x00001ff0
+#define BCHP_EBI_CS_BASE_6_reserved0_SHIFT                         4
+
+/* EBI :: CS_BASE_6 :: size [03:00] */
+#define BCHP_EBI_CS_BASE_6_size_MASK                               0x0000000f
+#define BCHP_EBI_CS_BASE_6_size_SHIFT                              0
+#define BCHP_EBI_CS_BASE_6_size_DEFAULT                            0x00000000
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8KB                           0
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16KB                          1
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32KB                          2
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64KB                          3
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128KB                         4
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256KB                         5
+#define BCHP_EBI_CS_BASE_6_size_SIZE_512KB                         6
+#define BCHP_EBI_CS_BASE_6_size_SIZE_1MB                           7
+#define BCHP_EBI_CS_BASE_6_size_SIZE_2MB                           8
+#define BCHP_EBI_CS_BASE_6_size_SIZE_4MB                           9
+#define BCHP_EBI_CS_BASE_6_size_SIZE_8MB                           10
+#define BCHP_EBI_CS_BASE_6_size_SIZE_16MB                          11
+#define BCHP_EBI_CS_BASE_6_size_SIZE_32MB                          12
+#define BCHP_EBI_CS_BASE_6_size_SIZE_64MB                          13
+#define BCHP_EBI_CS_BASE_6_size_SIZE_128MB                         14
+#define BCHP_EBI_CS_BASE_6_size_SIZE_256MB                         15
+
+/***************************************************************************
+ *CS_CONFIG_6 - EBI CS Config 6 Register
+ ***************************************************************************/
+/* EBI :: CS_CONFIG_6 :: mem_io [31:31] */
+#define BCHP_EBI_CS_CONFIG_6_mem_io_MASK                           0x80000000
+#define BCHP_EBI_CS_CONFIG_6_mem_io_SHIFT                          31
+#define BCHP_EBI_CS_CONFIG_6_mem_io_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ta_wait [30:30] */
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_MASK                          0x40000000
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_SHIFT                         30
+#define BCHP_EBI_CS_CONFIG_6_ta_wait_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wp [29:29] */
+#define BCHP_EBI_CS_CONFIG_6_wp_MASK                               0x20000000
+#define BCHP_EBI_CS_CONFIG_6_wp_SHIFT                              29
+#define BCHP_EBI_CS_CONFIG_6_wp_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: wait_count [28:24] */
+#define BCHP_EBI_CS_CONFIG_6_wait_count_MASK                       0x1f000000
+#define BCHP_EBI_CS_CONFIG_6_wait_count_SHIFT                      24
+#define BCHP_EBI_CS_CONFIG_6_wait_count_DEFAULT                    0x00000007
+
+/* EBI :: CS_CONFIG_6 :: t_hold [23:20] */
+#define BCHP_EBI_CS_CONFIG_6_t_hold_MASK                           0x00f00000
+#define BCHP_EBI_CS_CONFIG_6_t_hold_SHIFT                          20
+#define BCHP_EBI_CS_CONFIG_6_t_hold_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: t_setup [19:16] */
+#define BCHP_EBI_CS_CONFIG_6_t_setup_MASK                          0x000f0000
+#define BCHP_EBI_CS_CONFIG_6_t_setup_SHIFT                         16
+#define BCHP_EBI_CS_CONFIG_6_t_setup_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: cs_hold [15:15] */
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_MASK                          0x00008000
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_SHIFT                         15
+#define BCHP_EBI_CS_CONFIG_6_cs_hold_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: split_cs [14:14] */
+#define BCHP_EBI_CS_CONFIG_6_split_cs_MASK                         0x00004000
+#define BCHP_EBI_CS_CONFIG_6_split_cs_SHIFT                        14
+#define BCHP_EBI_CS_CONFIG_6_split_cs_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: mask_en [13:13] */
+#define BCHP_EBI_CS_CONFIG_6_mask_en_MASK                          0x00002000
+#define BCHP_EBI_CS_CONFIG_6_mask_en_SHIFT                         13
+#define BCHP_EBI_CS_CONFIG_6_mask_en_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ne_sample [12:12] */
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_MASK                        0x00001000
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_SHIFT                       12
+#define BCHP_EBI_CS_CONFIG_6_ne_sample_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: m68k [11:11] */
+#define BCHP_EBI_CS_CONFIG_6_m68k_MASK                             0x00000800
+#define BCHP_EBI_CS_CONFIG_6_m68k_SHIFT                            11
+#define BCHP_EBI_CS_CONFIG_6_m68k_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: le [10:10] */
+#define BCHP_EBI_CS_CONFIG_6_le_MASK                               0x00000400
+#define BCHP_EBI_CS_CONFIG_6_le_SHIFT                              10
+#define BCHP_EBI_CS_CONFIG_6_le_DEFAULT                            0x00000000
+
+/* EBI :: CS_CONFIG_6 :: fast_read [09:09] */
+#define BCHP_EBI_CS_CONFIG_6_fast_read_MASK                        0x00000200
+#define BCHP_EBI_CS_CONFIG_6_fast_read_SHIFT                       9
+#define BCHP_EBI_CS_CONFIG_6_fast_read_DEFAULT                     0x00000000
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Normal                      0
+#define BCHP_EBI_CS_CONFIG_6_fast_read_Fast_Read_Enable            1
+
+/* EBI :: CS_CONFIG_6 :: size_sel [08:08] */
+#define BCHP_EBI_CS_CONFIG_6_size_sel_MASK                         0x00000100
+#define BCHP_EBI_CS_CONFIG_6_size_sel_SHIFT                        8
+#define BCHP_EBI_CS_CONFIG_6_size_sel_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: sync [07:07] */
+#define BCHP_EBI_CS_CONFIG_6_sync_MASK                             0x00000080
+#define BCHP_EBI_CS_CONFIG_6_sync_SHIFT                            7
+#define BCHP_EBI_CS_CONFIG_6_sync_DEFAULT                          0x00000000
+
+/* EBI :: CS_CONFIG_6 :: polarity [06:06] */
+#define BCHP_EBI_CS_CONFIG_6_polarity_MASK                         0x00000040
+#define BCHP_EBI_CS_CONFIG_6_polarity_SHIFT                        6
+#define BCHP_EBI_CS_CONFIG_6_polarity_DEFAULT                      0x00000000
+
+/* EBI :: CS_CONFIG_6 :: we_ctl [05:05] */
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_MASK                           0x00000020
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_SHIFT                          5
+#define BCHP_EBI_CS_CONFIG_6_we_ctl_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: dest_size [04:04] */
+#define BCHP_EBI_CS_CONFIG_6_dest_size_MASK                        0x00000010
+#define BCHP_EBI_CS_CONFIG_6_dest_size_SHIFT                       4
+#define BCHP_EBI_CS_CONFIG_6_dest_size_DEFAULT                     0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ms_inh [03:03] */
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_MASK                           0x00000008
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_SHIFT                          3
+#define BCHP_EBI_CS_CONFIG_6_ms_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: ls_inh [02:02] */
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_MASK                           0x00000004
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_SHIFT                          2
+#define BCHP_EBI_CS_CONFIG_6_ls_inh_DEFAULT                        0x00000000
+
+/* EBI :: CS_CONFIG_6 :: bcachen [01:01] */
+#define BCHP_EBI_CS_CONFIG_6_bcachen_MASK                          0x00000002
+#define BCHP_EBI_CS_CONFIG_6_bcachen_SHIFT                         1
+#define BCHP_EBI_CS_CONFIG_6_bcachen_DEFAULT                       0x00000000
+
+/* EBI :: CS_CONFIG_6 :: enable [00:00] */
+#define BCHP_EBI_CS_CONFIG_6_enable_MASK                           0x00000001
+#define BCHP_EBI_CS_CONFIG_6_enable_SHIFT                          0
+#define BCHP_EBI_CS_CONFIG_6_enable_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *BURST_CFG_0 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_0 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_0_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_0_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_0_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_0_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_0_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_0 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_0_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_0 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_0_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_0_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_0_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_0 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_0_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_0 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_0_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_0_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_0_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_0_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_0 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_0_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_0 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_0_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_0 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_0_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_0_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_0 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_0_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_0_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_0_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_0 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_0_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_0_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_0 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_0_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_0_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_0_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_0 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_0_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_0_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_0_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_1 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_1 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_1_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_1_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_1_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_1_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_1_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_1 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_1_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_1 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_1_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_1_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_1_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_1 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_1_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_1 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_1_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_1_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_1_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_1_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_1 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_1_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_1 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_1_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_1 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_1_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_1_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_1 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_1_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_1_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_1_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_1 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_1_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_1_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_1 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_1_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_1_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_1_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_1 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_1_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_1_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_1_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_2 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_2 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_2_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_2_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_2_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_2_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_2_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_2 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_2_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_2 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_2_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_2_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_2_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_2 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_2_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_2 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_2_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_2_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_2_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_2_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_2 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_2_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_2 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_2_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_2 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_2_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_2_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_2 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_2_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_2_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_2_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_2 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_2_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_2_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_2 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_2_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_2_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_2_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_2 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_2_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_2_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_2_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_3 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_3 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_3_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_3_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_3_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_3_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_3_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_3 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_3_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_3 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_3_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_3_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_3_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_3 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_3_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_3 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_3_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_3_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_3_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_3_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_3 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_3_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_3 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_3_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_3 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_3_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_3_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_3 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_3_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_3_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_3_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_3 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_3_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_3_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_3 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_3_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_3_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_3_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_3 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_3_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_3_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_3_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_4 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_4 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_4_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_4_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_4_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_4_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_4_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_4 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_4_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_4 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_4_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_4_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_4_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_4 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_4_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_4 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_4_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_4_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_4_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_4_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_4 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_4_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_4 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_4_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_4 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_4_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_4_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_4 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_4_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_4_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_4_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_4 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_4_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_4_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_4 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_4_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_4_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_4_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_4 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_4_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_4_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_4_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_5 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_5 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_5_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_5_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_5_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_5_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_5_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_5 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_5_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_5 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_5_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_5_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_5_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_5 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_5_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_5 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_5_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_5_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_5_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_5_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_5 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_5_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_5 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_5_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_5 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_5_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_5_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_5 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_5_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_5_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_5_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_5 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_5_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_5_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_5 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_5_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_5_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_5_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_5 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_5_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_5_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_5_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *BURST_CFG_6 - EBI Synchronous Intel StrataFlash Burst Configure Register
+ ***************************************************************************/
+/* EBI :: BURST_CFG_6 :: prefetch_enable [31:31] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_MASK                  0x80000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_SHIFT                 31
+#define BCHP_EBI_BURST_CFG_6_prefetch_enable_DEFAULT               0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_enable [30:30] */
+#define BCHP_EBI_BURST_CFG_6_page_enable_MASK                      0x40000000
+#define BCHP_EBI_BURST_CFG_6_page_enable_SHIFT                     30
+#define BCHP_EBI_BURST_CFG_6_page_enable_DEFAULT                   0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_abort_enable [29:29] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_MASK              0x20000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_SHIFT             29
+#define BCHP_EBI_BURST_CFG_6_pfetch_abort_enable_DEFAULT           0x00000000
+
+/* EBI :: BURST_CFG_6 :: page_latch_enable [28:28] */
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_MASK                0x10000000
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_SHIFT               28
+#define BCHP_EBI_BURST_CFG_6_page_latch_enable_DEFAULT             0x00000000
+
+/* EBI :: BURST_CFG_6 :: pfetch_wrap_enable [27:27] */
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_MASK               0x08000000
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_SHIFT              27
+#define BCHP_EBI_BURST_CFG_6_pfetch_wrap_enable_DEFAULT            0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved0 [26:24] */
+#define BCHP_EBI_BURST_CFG_6_reserved0_MASK                        0x07000000
+#define BCHP_EBI_BURST_CFG_6_reserved0_SHIFT                       24
+
+/* EBI :: BURST_CFG_6 :: prefetch_size [23:22] */
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_MASK                    0x00c00000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SHIFT                   22
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_DEFAULT                 0x00000000
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_4_BYTES            0
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_8_BYTES            1
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_16_BYTES           2
+#define BCHP_EBI_BURST_CFG_6_prefetch_size_SIZE_32_BYTES           3
+
+/* EBI :: BURST_CFG_6 :: page_size [21:20] */
+#define BCHP_EBI_BURST_CFG_6_page_size_MASK                        0x00300000
+#define BCHP_EBI_BURST_CFG_6_page_size_SHIFT                       20
+#define BCHP_EBI_BURST_CFG_6_page_size_DEFAULT                     0x00000000
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_4_BYTES                0
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_8_BYTES                1
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_16_BYTES               2
+#define BCHP_EBI_BURST_CFG_6_page_size_SIZE_32_BYTES               3
+
+/* EBI :: BURST_CFG_6 :: page_wait_count [19:16] */
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_MASK                  0x000f0000
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_SHIFT                 16
+#define BCHP_EBI_BURST_CFG_6_page_wait_count_DEFAULT               0x00000001
+
+/* EBI :: BURST_CFG_6 :: burst_cyc_disable [15:15] */
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_MASK                0x00008000
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_SHIFT               15
+#define BCHP_EBI_BURST_CFG_6_burst_cyc_disable_DEFAULT             0x00000001
+
+/* EBI :: BURST_CFG_6 :: reserved1 [14:08] */
+#define BCHP_EBI_BURST_CFG_6_reserved1_MASK                        0x00007f00
+#define BCHP_EBI_BURST_CFG_6_reserved1_SHIFT                       8
+
+/* EBI :: BURST_CFG_6 :: burst_latency [07:04] */
+#define BCHP_EBI_BURST_CFG_6_burst_latency_MASK                    0x000000f0
+#define BCHP_EBI_BURST_CFG_6_burst_latency_SHIFT                   4
+#define BCHP_EBI_BURST_CFG_6_burst_latency_DEFAULT                 0x00000000
+
+/* EBI :: BURST_CFG_6 :: reserved2 [03:02] */
+#define BCHP_EBI_BURST_CFG_6_reserved2_MASK                        0x0000000c
+#define BCHP_EBI_BURST_CFG_6_reserved2_SHIFT                       2
+
+/* EBI :: BURST_CFG_6 :: data_hold [01:01] */
+#define BCHP_EBI_BURST_CFG_6_data_hold_MASK                        0x00000002
+#define BCHP_EBI_BURST_CFG_6_data_hold_SHIFT                       1
+#define BCHP_EBI_BURST_CFG_6_data_hold_DEFAULT                     0x00000000
+
+/* EBI :: BURST_CFG_6 :: burst_16 [00:00] */
+#define BCHP_EBI_BURST_CFG_6_burst_16_MASK                         0x00000001
+#define BCHP_EBI_BURST_CFG_6_burst_16_SHIFT                        0
+#define BCHP_EBI_BURST_CFG_6_burst_16_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *ECR - EBI Configuration Register
+ ***************************************************************************/
+/* EBI :: ECR :: reserved0 [31:28] */
+#define BCHP_EBI_ECR_reserved0_MASK                                0xf0000000
+#define BCHP_EBI_ECR_reserved0_SHIFT                               28
+
+/* EBI :: ECR :: Ebi_Byte_Swap [27:27] */
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_MASK                            0x08000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_SHIFT                           27
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_DEFAULT                         0x00000000
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_32_16_and_8_bit_Xfers 0
+#define BCHP_EBI_ECR_Ebi_Byte_Swap_Byte_Swap_For_8_bit_Xfers_Only  1
+
+/* EBI :: ECR :: reserved1 [26:26] */
+#define BCHP_EBI_ECR_reserved1_MASK                                0x04000000
+#define BCHP_EBI_ECR_reserved1_SHIFT                               26
+
+/* EBI :: ECR :: Flag_32bit_Xfer [25:25] */
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_MASK                          0x02000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_SHIFT                         25
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_DEFAULT                       0x00000000
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_10         0
+#define BCHP_EBI_ECR_Flag_32bit_Xfer_Code_32bit_Xfer_as_00         1
+
+/* EBI :: ECR :: reserved2 [24:11] */
+#define BCHP_EBI_ECR_reserved2_MASK                                0x01fff800
+#define BCHP_EBI_ECR_reserved2_SHIFT                               11
+
+/* EBI :: ECR :: timeout_count [10:00] */
+#define BCHP_EBI_ECR_timeout_count_MASK                            0x000007ff
+#define BCHP_EBI_ECR_timeout_count_SHIFT                           0
+#define BCHP_EBI_ECR_timeout_count_DEFAULT                         0x00000400
+
+/***************************************************************************
+ *CS_TRISTATE_CFG - EBI CS Tristate Configuration Register
+ ***************************************************************************/
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rdb [31:31] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_MASK             0x80000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_SHIFT            31
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rdb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_dsb [30:30] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_MASK             0x40000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_SHIFT            30
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_dsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsb [29:29] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_MASK             0x20000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_SHIFT            29
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_rwb [28:28] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_MASK             0x10000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_SHIFT            28
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_rwb_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we1b [27:27] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_MASK            0x08000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_SHIFT           27
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we1b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_we0b [26:26] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_MASK            0x04000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_SHIFT           26
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_we0b_DEFAULT         0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize1b [25:25] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_MASK         0x02000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_SHIFT        25
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize1b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_tsize0b [24:24] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_MASK         0x01000000
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_SHIFT        24
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_tsize0b_DEFAULT      0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: reserved0 [23:07] */
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_MASK                    0x00ffff80
+#define BCHP_EBI_CS_TRISTATE_CFG_reserved0_SHIFT                   7
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs6 [06:06] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_MASK             0x00000040
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_SHIFT            6
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs6_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs5 [05:05] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_MASK             0x00000020
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_SHIFT            5
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs5_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs4 [04:04] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_MASK             0x00000010
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_SHIFT            4
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs4_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs3 [03:03] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_MASK             0x00000008
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_SHIFT            3
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs3_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs2 [02:02] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_MASK             0x00000004
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_SHIFT            2
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs2_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs1 [01:01] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_MASK             0x00000002
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_SHIFT            1
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs1_DEFAULT          0x00000000
+
+/* EBI :: CS_TRISTATE_CFG :: tristate_ebi_cs0 [00:00] */
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_MASK             0x00000001
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_SHIFT            0
+#define BCHP_EBI_CS_TRISTATE_CFG_tristate_ebi_cs0_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CS_SPI_SELECT - SPI CS Select
+ ***************************************************************************/
+/* EBI :: CS_SPI_SELECT :: reserved0 [31:15] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_MASK                      0xffff8000
+#define BCHP_EBI_CS_SPI_SELECT_reserved0_SHIFT                     15
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_6_USES_SPI [14:14] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_MASK              0x00004000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_SHIFT             14
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_6_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_5_USES_SPI [13:13] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_MASK              0x00002000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_SHIFT             13
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_5_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_4_USES_SPI [12:12] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_MASK              0x00001000
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_SHIFT             12
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_4_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_3_USES_SPI [11:11] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_MASK              0x00000800
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_SHIFT             11
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_3_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_2_USES_SPI [10:10] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_MASK              0x00000400
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_SHIFT             10
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_2_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_1_USES_SPI [09:09] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_MASK              0x00000200
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_SHIFT             9
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_1_USES_SPI_DEFAULT           0x00000000
+
+/* EBI :: CS_SPI_SELECT :: EBI_CS_0_USES_SPI [08:08] */
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_MASK              0x00000100
+#define BCHP_EBI_CS_SPI_SELECT_EBI_CS_0_USES_SPI_SHIFT             8
+
+/* EBI :: CS_SPI_SELECT :: reserved1 [07:07] */
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_MASK                      0x00000080
+#define BCHP_EBI_CS_SPI_SELECT_reserved1_SHIFT                     7
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_6_SEL [06:06] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_MASK               0x00000040
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_SHIFT              6
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_6_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_5_SEL [05:05] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_MASK               0x00000020
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_SHIFT              5
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_5_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_4_SEL [04:04] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_MASK               0x00000010
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_SHIFT              4
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_4_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_3_SEL [03:03] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_MASK               0x00000008
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_SHIFT              3
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_3_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_2_SEL [02:02] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_MASK               0x00000004
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_SHIFT              2
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_2_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_1_SEL [01:01] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_MASK               0x00000002
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_SHIFT              1
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_1_SEL_DEFAULT            0x00000000
+
+/* EBI :: CS_SPI_SELECT :: SPI_EBI_CS_0_SEL [00:00] */
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_MASK               0x00000001
+#define BCHP_EBI_CS_SPI_SELECT_SPI_EBI_CS_0_SEL_SHIFT              0
+
+/***************************************************************************
+ *ARRAY_ADDRESS - EBI Data Array Address
+ ***************************************************************************/
+/* EBI :: ARRAY_ADDRESS :: ADDRESS [31:09] */
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_MASK                        0xfffffe00
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_SHIFT                       9
+#define BCHP_EBI_ARRAY_ADDRESS_ADDRESS_DEFAULT                     0x00000000
+
+/* EBI :: ARRAY_ADDRESS :: reserved0 [08:03] */
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_MASK                      0x000001f8
+#define BCHP_EBI_ARRAY_ADDRESS_reserved0_SHIFT                     3
+
+/* EBI :: ARRAY_ADDRESS :: CS_SEL [02:00] */
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_MASK                         0x00000007
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_SHIFT                        0
+#define BCHP_EBI_ARRAY_ADDRESS_CS_SEL_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_BASE                            0x00440a00
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_START                           0
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_END                             127
+#define BCHP_EBI_DATA_ARRAYi_ARRAY_ELEMENT_SIZE                    32
+
+/***************************************************************************
+ *DATA_ARRAY%i - EBI Data Array Read/Write Access
+ ***************************************************************************/
+/* EBI :: DATA_ARRAYi :: WORD [31:00] */
+#define BCHP_EBI_DATA_ARRAYi_WORD_MASK                             0xffffffff
+#define BCHP_EBI_DATA_ARRAYi_WORD_SHIFT                            0
+
+
+#endif /* #ifndef BCHP_EBI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_hif_intr2.h b/include/linux/brcmstb/7364a0/bchp_hif_intr2.h
new file mode 100644
index 000000000000..25bd66d2ecac
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_hif_intr2.h
@@ -0,0 +1,1442 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:41 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_INTR2_H__
+#define BCHP_HIF_INTR2_H__
+
+/***************************************************************************
+ *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
+ ***************************************************************************/
+#define BCHP_HIF_INTR2_CPU_STATUS                0x00441000 /* CPU interrupt Status Register */
+#define BCHP_HIF_INTR2_CPU_SET                   0x00441004 /* CPU interrupt Set Register */
+#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00441008 /* CPU interrupt Clear Register */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0044100c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00441010 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00441014 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_INTR2_PCI_STATUS                0x00441018 /* PCI interrupt Status Register */
+#define BCHP_HIF_INTR2_PCI_SET                   0x0044101c /* PCI interrupt Set Register */
+#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00441020 /* PCI interrupt Clear Register */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00441024 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00441028 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0044102c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0x30000000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00080000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  19
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK                   0x00030000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT                  16
+
+/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK                   0x00004000
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT                  14
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved4_SHIFT                  6
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_STATUS :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved5_MASK                   0x0000000e
+#define BCHP_HIF_INTR2_CPU_STATUS_reserved5_SHIFT                  1
+
+/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0x30000000
+#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00080000
+#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     19
+
+/* HIF_INTR2 :: CPU_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_CPU_SET_ITCH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK                      0x00030000
+#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT                     16
+
+/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK                      0x00004000
+#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT                     14
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_CPU_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved4_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_CPU_SET_reserved4_SHIFT                     6
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_SET :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_SET_reserved5_MASK                      0x0000000e
+#define BCHP_HIF_INTR2_CPU_SET_reserved5_SHIFT                     1
+
+/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0x30000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00080000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   19
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK                    0x00030000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT                   16
+
+/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK                    0x00004000
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT                   14
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved4_SHIFT                   6
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_CLEAR :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved5_MASK                    0x0000000e
+#define BCHP_HIF_INTR2_CPU_CLEAR_reserved5_SHIFT                   1
+
+/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             19
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK              0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT             14
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT             6
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_MASK              0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved4_SHIFT             1
+
+/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                19
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK                 0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT                14
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT                6
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_SET :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_MASK                 0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved4_SHIFT                1
+
+/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0x30000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00080000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              19
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK               0x00004000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT              14
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT              6
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_MASK               0x0000000e
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved4_SHIFT              1
+
+/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK          0x80000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT         31
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK            0x40000000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT           30
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0x30000000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  28
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
+#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00080000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  19
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_MASK                0x00040000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_SHIFT               18
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH_WR_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK                   0x00030000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT                  16
+
+/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK               0x00008000
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT              15
+#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK                   0x00004000
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT                  14
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK         0x00002000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT        13
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_MASK        0x00001000
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT       12
+#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_MASK                   0x00000fc0
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved4_SHIFT                  6
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
+#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_STATUS :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved5_MASK                   0x0000000e
+#define BCHP_HIF_INTR2_PCI_STATUS_reserved5_SHIFT                  1
+
+/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
+#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK             0x80000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT            31
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK               0x40000000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT              30
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0x30000000
+#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     28
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
+#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
+#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
+#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
+#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
+#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
+#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00080000
+#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     19
+
+/* HIF_INTR2 :: PCI_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_MASK                   0x00040000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_SHIFT                  18
+#define BCHP_HIF_INTR2_PCI_SET_ITCH_WR_INTR_DEFAULT                0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK                      0x00030000
+#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT                     16
+
+/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK                  0x00008000
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT                 15
+#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT               0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK                      0x00004000
+#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT                     14
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK            0x00002000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT           13
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_MASK           0x00001000
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_SHIFT          12
+#define BCHP_HIF_INTR2_PCI_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved4_MASK                      0x00000fc0
+#define BCHP_HIF_INTR2_PCI_SET_reserved4_SHIFT                     6
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
+#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_SET :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_SET_reserved5_MASK                      0x0000000e
+#define BCHP_HIF_INTR2_PCI_SET_reserved5_SHIFT                     1
+
+/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
+#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK           0x80000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT          31
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK             0x40000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT            30
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0x30000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   28
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
+#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00080000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   19
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_MASK                 0x00040000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_SHIFT                18
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH_WR_INTR_DEFAULT              0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [17:16] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK                    0x00030000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT                   16
+
+/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT               15
+#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [14:14] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK                    0x00004000
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT                   14
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK          0x00002000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT         13
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK         0x00001000
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT        12
+#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT      0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved4 [11:06] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_MASK                    0x00000fc0
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved4_SHIFT                   6
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
+#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_CLEAR :: reserved5 [03:01] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved5_MASK                    0x0000000e
+#define BCHP_HIF_INTR2_PCI_CLEAR_reserved5_SHIFT                   1
+
+/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
+#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK     0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT    31
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK       0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT      30
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             28
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             19
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_MASK           0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_SHIFT          18
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH_WR_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK       0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT      17
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK           0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT          16
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK              0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT             14
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK    0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT   13
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_MASK   0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_SHIFT  12
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK              0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT             6
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_MASK              0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved4_SHIFT             1
+
+/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
+#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK        0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT       31
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK          0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT         30
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_DEFAULT       0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                28
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
+#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                19
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_MASK              0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_SHIFT             18
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH_WR_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK          0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT         17
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK              0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT             16
+#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_DEFAULT           0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT            15
+#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK                 0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT                14
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK       0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT      13
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_MASK      0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_SHIFT     12
+#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RGR_BRIDGE_INTR_DEFAULT   0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK                 0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT                6
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
+#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_SET :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_MASK                 0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved4_SHIFT                1
+
+/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
+#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK      0x80000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT     31
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK        0x40000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT       30
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_DEFAULT     0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [29:28] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0x30000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              28
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [19:19] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00080000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              19
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH_WR_INTR [18:18] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_MASK            0x00040000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_SHIFT           18
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH_WR_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK        0x00020000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT       17
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_DEFAULT     0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK            0x00010000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT           16
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_DEFAULT         0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [14:14] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK               0x00004000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT              14
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK     0x00002000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT    13
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_DEFAULT  0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RGR_BRIDGE_INTR [12:12] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_MASK    0x00001000
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_SHIFT   12
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RGR_BRIDGE_INTR_DEFAULT 0x00000001
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [11:06] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK               0x00000fc0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT              6
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved4 [03:01] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_MASK               0x0000000e
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved4_SHIFT              1
+
+/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
+#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001
+
+#endif /* #ifndef BCHP_HIF_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_hif_mspi.h b/include/linux/brcmstb/7364a0/bchp_hif_mspi.h
new file mode 100644
index 000000000000..5a055f26cccc
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_hif_mspi.h
@@ -0,0 +1,1291 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:39 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_MSPI_H__
+#define BCHP_HIF_MSPI_H__
+
+/***************************************************************************
+ *HIF_MSPI - Public MSPI Registers
+ ***************************************************************************/
+#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00443400 /* SPCR0_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00443404 /* SPCR0_MSB Register */
+#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00443408 /* SPCR1_LSB REGISTER */
+#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0044340c /* SPCR1_MSB REGISTER */
+#define BCHP_HIF_MSPI_NEWQP                      0x00443410 /* NEWQP REGISTER */
+#define BCHP_HIF_MSPI_ENDQP                      0x00443414 /* ENDQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR2                      0x00443418 /* SPCR2 REGISTER */
+#define BCHP_HIF_MSPI_MSPI_STATUS                0x00443420 /* MSPI STATUS REGISTER */
+#define BCHP_HIF_MSPI_CPTQP                      0x00443424 /* CPTQP REGISTER */
+#define BCHP_HIF_MSPI_SPCR3                      0x00443428 /* SPCR3 REGISTER */
+#define BCHP_HIF_MSPI_REVISION                   0x0044342c /* REVISION ID REGISTER */
+#define BCHP_HIF_MSPI_TXRAM00                    0x00443440 /* Most significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM01                    0x00443444 /* Least significant byte of TXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_TXRAM02                    0x00443448 /* Most significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM03                    0x0044344c /* Least significant byte of TXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_TXRAM04                    0x00443450 /* Most significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM05                    0x00443454 /* Least significant byte of TXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_TXRAM06                    0x00443458 /* Most significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM07                    0x0044345c /* Least significant byte of TXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_TXRAM08                    0x00443460 /* Most significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM09                    0x00443464 /* Least significant byte of TXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_TXRAM10                    0x00443468 /* Most significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM11                    0x0044346c /* Least significant byte of TXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_TXRAM12                    0x00443470 /* Most significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM13                    0x00443474 /* Least significant byte of TXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_TXRAM14                    0x00443478 /* Most significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM15                    0x0044347c /* Least significant byte of TXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_TXRAM16                    0x00443480 /* Most significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM17                    0x00443484 /* Least significant byte of TXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_TXRAM18                    0x00443488 /* Most significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM19                    0x0044348c /* Least significant byte of TXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_TXRAM20                    0x00443490 /* Most significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM21                    0x00443494 /* Least significant byte of TXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_TXRAM22                    0x00443498 /* Most significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM23                    0x0044349c /* Least significant byte of TXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_TXRAM24                    0x004434a0 /* Most significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM25                    0x004434a4 /* Least significant byte of TXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_TXRAM26                    0x004434a8 /* Most significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM27                    0x004434ac /* Least significant byte of TXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_TXRAM28                    0x004434b0 /* Most significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM29                    0x004434b4 /* Least significant byte of TXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_TXRAM30                    0x004434b8 /* Most significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_TXRAM31                    0x004434bc /* Least significant byte of TXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM00                    0x004434c0 /* Most significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM01                    0x004434c4 /* Least significant byte of RXRAM[0] (queue pointer = 0) */
+#define BCHP_HIF_MSPI_RXRAM02                    0x004434c8 /* Most significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM03                    0x004434cc /* Least significant byte of RXRAM[1] (queue pointer = 1) */
+#define BCHP_HIF_MSPI_RXRAM04                    0x004434d0 /* Most significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM05                    0x004434d4 /* Least significant byte of RXRAM[2] (queue pointer = 2) */
+#define BCHP_HIF_MSPI_RXRAM06                    0x004434d8 /* Most significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM07                    0x004434dc /* Least significant byte of RXRAM[3] (queue pointer = 3) */
+#define BCHP_HIF_MSPI_RXRAM08                    0x004434e0 /* Most significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM09                    0x004434e4 /* Least significant byte of RXRAM[4] (queue pointer = 4) */
+#define BCHP_HIF_MSPI_RXRAM10                    0x004434e8 /* Most significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM11                    0x004434ec /* Least significant byte of RXRAM[5] (queue pointer = 5) */
+#define BCHP_HIF_MSPI_RXRAM12                    0x004434f0 /* Most significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM13                    0x004434f4 /* Least significant byte of RXRAM[6] (queue pointer = 6) */
+#define BCHP_HIF_MSPI_RXRAM14                    0x004434f8 /* Most significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM15                    0x004434fc /* Least significant byte of RXRAM[7] (queue pointer = 7) */
+#define BCHP_HIF_MSPI_RXRAM16                    0x00443500 /* Most significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM17                    0x00443504 /* Least significant byte of RXRAM[8] (queue pointer = 8) */
+#define BCHP_HIF_MSPI_RXRAM18                    0x00443508 /* Most significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM19                    0x0044350c /* Least significant byte of RXRAM[9] (queue pointer = 9) */
+#define BCHP_HIF_MSPI_RXRAM20                    0x00443510 /* Most significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM21                    0x00443514 /* Least significant byte of RXRAM[10] (queue pointer = 10) */
+#define BCHP_HIF_MSPI_RXRAM22                    0x00443518 /* Most significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM23                    0x0044351c /* Least significant byte of RXRAM[11] (queue pointer = 11) */
+#define BCHP_HIF_MSPI_RXRAM24                    0x00443520 /* Most significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM25                    0x00443524 /* Least significant byte of RXRAM[12] (queue pointer = 12) */
+#define BCHP_HIF_MSPI_RXRAM26                    0x00443528 /* Most significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM27                    0x0044352c /* Least significant byte of RXRAM[13] (queue pointer = 13) */
+#define BCHP_HIF_MSPI_RXRAM28                    0x00443530 /* Most significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM29                    0x00443534 /* Least significant byte of RXRAM[14] (queue pointer = 14) */
+#define BCHP_HIF_MSPI_RXRAM30                    0x00443538 /* Most significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_RXRAM31                    0x0044353c /* Least significant byte of RXRAM[15] (queue pointer = 15) */
+#define BCHP_HIF_MSPI_CDRAM00                    0x00443540 /* 8-bit command (queue pointer = 0) */
+#define BCHP_HIF_MSPI_CDRAM01                    0x00443544 /* 8-bit command (queue pointer = 1) */
+#define BCHP_HIF_MSPI_CDRAM02                    0x00443548 /* 8-bit command (queue pointer = 2) */
+#define BCHP_HIF_MSPI_CDRAM03                    0x0044354c /* 8-bit command (queue pointer = 3) */
+#define BCHP_HIF_MSPI_CDRAM04                    0x00443550 /* 8-bit command (queue pointer = 4) */
+#define BCHP_HIF_MSPI_CDRAM05                    0x00443554 /* 8-bit command (queue pointer = 5) */
+#define BCHP_HIF_MSPI_CDRAM06                    0x00443558 /* 8-bit command (queue pointer = 6) */
+#define BCHP_HIF_MSPI_CDRAM07                    0x0044355c /* 8-bit command (queue pointer = 7) */
+#define BCHP_HIF_MSPI_CDRAM08                    0x00443560 /* 8-bit command (queue pointer = 8) */
+#define BCHP_HIF_MSPI_CDRAM09                    0x00443564 /* 8-bit command (queue pointer = 9) */
+#define BCHP_HIF_MSPI_CDRAM10                    0x00443568 /* 8-bit command (queue pointer = a) */
+#define BCHP_HIF_MSPI_CDRAM11                    0x0044356c /* 8-bit command (queue pointer = b) */
+#define BCHP_HIF_MSPI_CDRAM12                    0x00443570 /* 8-bit command (queue pointer = c) */
+#define BCHP_HIF_MSPI_CDRAM13                    0x00443574 /* 8-bit command (queue pointer = d) */
+#define BCHP_HIF_MSPI_CDRAM14                    0x00443578 /* 8-bit command (queue pointer = e) */
+#define BCHP_HIF_MSPI_CDRAM15                    0x0044357c /* 8-bit command (queue pointer = f) */
+#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00443580 /* Control bit to lock group of write commands */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00443584 /* Debug bit to mask the generation of flush signals from Mspi */
+
+/***************************************************************************
+ *SPCR0_LSB - SPCR0_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR0_MSB - SPCR0_MSB Register
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xfffffe00
+#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    9
+
+/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [08:08] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000100
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              8
+#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0x00000000
+
+/* union - case data_reg_8 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: reserved0 [07:06] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_MASK          0x000000c0
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_reserved0_SHIFT         6
+
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_8 :: BITS [05:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_MASK               0x0000003c
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_SHIFT              2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_8_BITS_DEFAULT            0x00000000
+
+/* union - case data_reg_32 [07:02] */
+/* HIF_MSPI :: SPCR0_MSB :: data_reg_32 :: BITS [07:02] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_MASK              0x000000fc
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_SHIFT             2
+#define BCHP_HIF_MSPI_SPCR0_MSB_data_reg_32_BITS_DEFAULT           0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0x00000000
+
+/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
+#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *SPCR1_LSB - SPCR1_LSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
+#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *SPCR1_MSB - SPCR1_MSB REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
+#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8
+
+/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
+#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *NEWQP - NEWQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: NEWQP :: newqp [03:00] */
+#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
+#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *ENDQP - ENDQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: ENDQP :: endqp [03:00] */
+#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
+#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR2 - SPCR2 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
+#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8
+
+/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
+#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spe [06:06] */
+#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
+#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
+#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
+#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
+#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
+#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wren [04:04] */
+#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
+#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
+#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
+#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
+#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
+#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0x00000000
+
+/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
+#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
+#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
+#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0x00000000
+
+/* HIF_MSPI :: SPCR2 :: hie [01:01] */
+#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
+#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
+#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0x00000000
+
+/* HIF_MSPI :: SPCR2 :: halt [00:00] */
+#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
+#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
+#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *MSPI_STATUS - MSPI STATUS REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
+#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2
+
+/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
+#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0x00000000
+
+/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
+#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *CPTQP - CPTQP REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
+#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
+#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4
+
+/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
+#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
+#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
+#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0x00000000
+
+/***************************************************************************
+ *SPCR3 - SPCR3 REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: SPCR3 :: reserved0 [31:10] */
+#define BCHP_HIF_MSPI_SPCR3_reserved0_MASK                         0xfffffc00
+#define BCHP_HIF_MSPI_SPCR3_reserved0_SHIFT                        10
+
+/* HIF_MSPI :: SPCR3 :: cpharx [09:09] */
+#define BCHP_HIF_MSPI_SPCR3_cpharx_MASK                            0x00000200
+#define BCHP_HIF_MSPI_SPCR3_cpharx_SHIFT                           9
+#define BCHP_HIF_MSPI_SPCR3_cpharx_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: data_reg_size [08:08] */
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_MASK                     0x00000100
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_SHIFT                    8
+#define BCHP_HIF_MSPI_SPCR3_data_reg_size_DEFAULT                  0x00000000
+
+/* HIF_MSPI :: SPCR3 :: hdouttype [07:07] */
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_MASK                         0x00000080
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_SHIFT                        7
+#define BCHP_HIF_MSPI_SPCR3_hdouttype_DEFAULT                      0x00000000
+
+/* HIF_MSPI :: SPCR3 :: halfduplex [06:06] */
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_MASK                        0x00000040
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_SHIFT                       6
+#define BCHP_HIF_MSPI_SPCR3_halfduplex_DEFAULT                     0x00000000
+
+/* HIF_MSPI :: SPCR3 :: txramdam [05:04] */
+#define BCHP_HIF_MSPI_SPCR3_txramdam_MASK                          0x00000030
+#define BCHP_HIF_MSPI_SPCR3_txramdam_SHIFT                         4
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_txramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: rxramdam [03:02] */
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_MASK                          0x0000000c
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_SHIFT                         2
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DEFAULT                       0x00000000
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_8B                        0
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_16B                       1
+#define BCHP_HIF_MSPI_SPCR3_rxramdam_DAM_32B                       2
+
+/* HIF_MSPI :: SPCR3 :: fastdt [01:01] */
+#define BCHP_HIF_MSPI_SPCR3_fastdt_MASK                            0x00000002
+#define BCHP_HIF_MSPI_SPCR3_fastdt_SHIFT                           1
+#define BCHP_HIF_MSPI_SPCR3_fastdt_DEFAULT                         0x00000000
+
+/* HIF_MSPI :: SPCR3 :: fastbr [00:00] */
+#define BCHP_HIF_MSPI_SPCR3_fastbr_MASK                            0x00000001
+#define BCHP_HIF_MSPI_SPCR3_fastbr_SHIFT                           0
+#define BCHP_HIF_MSPI_SPCR3_fastbr_DEFAULT                         0x00000000
+
+/***************************************************************************
+ *REVISION - REVISION ID REGISTER
+ ***************************************************************************/
+/* HIF_MSPI :: REVISION :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_REVISION_reserved0_MASK                      0xffffff00
+#define BCHP_HIF_MSPI_REVISION_reserved0_SHIFT                     8
+
+/* HIF_MSPI :: REVISION :: major [07:04] */
+#define BCHP_HIF_MSPI_REVISION_major_MASK                          0x000000f0
+#define BCHP_HIF_MSPI_REVISION_major_SHIFT                         4
+#define BCHP_HIF_MSPI_REVISION_major_DEFAULT                       0x00000001
+
+/* HIF_MSPI :: REVISION :: minor [03:00] */
+#define BCHP_HIF_MSPI_REVISION_minor_MASK                          0x0000000f
+#define BCHP_HIF_MSPI_REVISION_minor_SHIFT                         0
+#define BCHP_HIF_MSPI_REVISION_minor_DEFAULT                       0x00000005
+
+/***************************************************************************
+ *TXRAM00 - Most significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM01 - Least significant byte of TXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM02 - Most significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM03 - Least significant byte of TXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM04 - Most significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM05 - Least significant byte of TXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM06 - Most significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM07 - Least significant byte of TXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM08 - Most significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM09 - Least significant byte of TXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM10 - Most significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM11 - Least significant byte of TXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM12 - Most significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM13 - Least significant byte of TXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM14 - Most significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM15 - Least significant byte of TXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM16 - Most significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM17 - Least significant byte of TXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM18 - Most significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM19 - Least significant byte of TXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM20 - Most significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM21 - Least significant byte of TXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM22 - Most significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM23 - Least significant byte of TXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM24 - Most significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM25 - Least significant byte of TXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM26 - Most significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM27 - Least significant byte of TXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM28 - Most significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM29 - Least significant byte of TXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM30 - Most significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0
+
+/***************************************************************************
+ *TXRAM31 - Least significant byte of TXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
+#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM00 - Most significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM01 - Least significant byte of RXRAM[0] (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM02 - Most significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM03 - Least significant byte of RXRAM[1] (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM04 - Most significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM05 - Least significant byte of RXRAM[2] (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM06 - Most significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM07 - Least significant byte of RXRAM[3] (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM08 - Most significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM09 - Least significant byte of RXRAM[4] (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM10 - Most significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM11 - Least significant byte of RXRAM[5] (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM12 - Most significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM13 - Least significant byte of RXRAM[6] (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM14 - Most significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM15 - Least significant byte of RXRAM[7] (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM16 - Most significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM17 - Least significant byte of RXRAM[8] (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM18 - Most significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM19 - Least significant byte of RXRAM[9] (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM20 - Most significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM21 - Least significant byte of RXRAM[10] (queue pointer = 10)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM22 - Most significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM23 - Least significant byte of RXRAM[11] (queue pointer = 11)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM24 - Most significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM25 - Least significant byte of RXRAM[12] (queue pointer = 12)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM26 - Most significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM27 - Least significant byte of RXRAM[13] (queue pointer = 13)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM28 - Most significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM29 - Least significant byte of RXRAM[14] (queue pointer = 14)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM30 - Most significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0
+
+/***************************************************************************
+ *RXRAM31 - Least significant byte of RXRAM[15] (queue pointer = 15)
+ ***************************************************************************/
+/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
+#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8
+
+/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
+#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
+#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM00 - 8-bit command (queue pointer = 0)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM00 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM00 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM01 - 8-bit command (queue pointer = 1)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM01 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM01 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM02 - 8-bit command (queue pointer = 2)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM02 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM02 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM03 - 8-bit command (queue pointer = 3)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM03 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM03 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM04 - 8-bit command (queue pointer = 4)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM04 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM04 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM05 - 8-bit command (queue pointer = 5)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM05 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM05 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM06 - 8-bit command (queue pointer = 6)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM06 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM06 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM07 - 8-bit command (queue pointer = 7)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM07 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM07 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM08 - 8-bit command (queue pointer = 8)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM08 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM08 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM09 - 8-bit command (queue pointer = 9)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM09 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM09 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM10 - 8-bit command (queue pointer = a)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM10 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM10 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM11 - 8-bit command (queue pointer = b)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM11 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM11 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM12 - 8-bit command (queue pointer = c)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM12 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM12 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM13 - 8-bit command (queue pointer = d)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM13 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM13 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM14 - 8-bit command (queue pointer = e)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM14 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM14 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0
+
+/***************************************************************************
+ *CDRAM15 - 8-bit command (queue pointer = f)
+ ***************************************************************************/
+/* HIF_MSPI :: CDRAM15 :: reserved0 [31:09] */
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xfffffe00
+#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      9
+
+/* HIF_MSPI :: CDRAM15 :: cdram [08:00] */
+#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000001ff
+#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0
+
+/***************************************************************************
+ *WRITE_LOCK - Control bit to lock group of write commands
+ ***************************************************************************/
+/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
+#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1
+
+/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
+#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
+ ***************************************************************************/
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1
+
+/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
+#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0x00000000
+
+#endif /* #ifndef BCHP_HIF_MSPI_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_hif_spi_intr2.h b/include/linux/brcmstb/7364a0/bchp_hif_spi_intr2.h
new file mode 100644
index 000000000000..760de64aeec1
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_hif_spi_intr2.h
@@ -0,0 +1,566 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:38 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_HIF_SPI_INTR2_H__
+#define BCHP_HIF_SPI_INTR2_H__
+
+/***************************************************************************
+ *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
+ ***************************************************************************/
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00441a00 /* CPU interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00441a04 /* CPU interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00441a08 /* CPU interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00441a0c /* CPU interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00441a10 /* CPU interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00441a14 /* CPU interrupt Mask Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00441a18 /* PCI interrupt Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00441a1c /* PCI interrupt Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00441a20 /* PCI interrupt Clear Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00441a24 /* PCI interrupt Mask Status Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00441a28 /* PCI interrupt Mask Set Register */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00441a2c /* PCI interrupt Mask Clear Register */
+
+/***************************************************************************
+ *CPU_STATUS - CPU interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_SET - CPU interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_CLEAR - CPU interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_STATUS - CPU interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_SET - CPU interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_STATUS - PCI interrupt Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_SET - PCI interrupt Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
+#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
+#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_CLEAR - PCI interrupt Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_STATUS - PCI interrupt Mask Status Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_SET - PCI interrupt Mask Set Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
+ ***************************************************************************/
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000
+
+/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
+#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_irq0.h b/include/linux/brcmstb/7364a0/bchp_irq0.h
new file mode 100644
index 000000000000..4b6ad1e53027
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_irq0.h
@@ -0,0 +1,166 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:42 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_IRQ0_H__
+#define BCHP_IRQ0_H__
+
+/***************************************************************************
+ *IRQ0 - Level 2 CPU Interrupt Enable/Status
+ ***************************************************************************/
+#define BCHP_IRQ0_IRQEN                          0x0040a480 /* Interrupt Enable */
+#define BCHP_IRQ0_IRQSTAT                        0x0040a484 /* Interrupt Status */
+
+/***************************************************************************
+ *IRQEN - Interrupt Enable
+ ***************************************************************************/
+/* IRQ0 :: IRQEN :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQEN_reserved0_MASK                             0xfffffc00
+#define BCHP_IRQ0_IRQEN_reserved0_SHIFT                            10
+
+/* IRQ0 :: IRQEN :: irb_irqen [09:09] */
+#define BCHP_IRQ0_IRQEN_irb_irqen_MASK                             0x00000200
+#define BCHP_IRQ0_IRQEN_irb_irqen_SHIFT                            9
+#define BCHP_IRQ0_IRQEN_irb_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: gio_irqen [08:08] */
+#define BCHP_IRQ0_IRQEN_gio_irqen_MASK                             0x00000100
+#define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT                            8
+#define BCHP_IRQ0_IRQEN_gio_irqen_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQEN :: iicd_irqen [07:07] */
+#define BCHP_IRQ0_IRQEN_iicd_irqen_MASK                            0x00000080
+#define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT                           7
+#define BCHP_IRQ0_IRQEN_iicd_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: iica_irqen [06:06] */
+#define BCHP_IRQ0_IRQEN_iica_irqen_MASK                            0x00000040
+#define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT                           6
+#define BCHP_IRQ0_IRQEN_iica_irqen_DEFAULT                         0x00000000
+
+/* IRQ0 :: IRQEN :: uc_irqen [05:05] */
+#define BCHP_IRQ0_IRQEN_uc_irqen_MASK                              0x00000020
+#define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT                             5
+#define BCHP_IRQ0_IRQEN_uc_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ub_irqen [04:04] */
+#define BCHP_IRQ0_IRQEN_ub_irqen_MASK                              0x00000010
+#define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT                             4
+#define BCHP_IRQ0_IRQEN_ub_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: ua_irqen [03:03] */
+#define BCHP_IRQ0_IRQEN_ua_irqen_MASK                              0x00000008
+#define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT                             3
+#define BCHP_IRQ0_IRQEN_ua_irqen_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQEN :: uartc_irqen [02:02] */
+#define BCHP_IRQ0_IRQEN_uartc_irqen_MASK                           0x00000004
+#define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT                          2
+#define BCHP_IRQ0_IRQEN_uartc_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uartb_irqen [01:01] */
+#define BCHP_IRQ0_IRQEN_uartb_irqen_MASK                           0x00000002
+#define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT                          1
+#define BCHP_IRQ0_IRQEN_uartb_irqen_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQEN :: uarta_irqen [00:00] */
+#define BCHP_IRQ0_IRQEN_uarta_irqen_MASK                           0x00000001
+#define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT                          0
+#define BCHP_IRQ0_IRQEN_uarta_irqen_DEFAULT                        0x00000000
+
+/***************************************************************************
+ *IRQSTAT - Interrupt Status
+ ***************************************************************************/
+/* IRQ0 :: IRQSTAT :: reserved0 [31:10] */
+#define BCHP_IRQ0_IRQSTAT_reserved0_MASK                           0xfffffc00
+#define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT                          10
+
+/* IRQ0 :: IRQSTAT :: irbirq [09:09] */
+#define BCHP_IRQ0_IRQSTAT_irbirq_MASK                              0x00000200
+#define BCHP_IRQ0_IRQSTAT_irbirq_SHIFT                             9
+#define BCHP_IRQ0_IRQSTAT_irbirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: gioirq [08:08] */
+#define BCHP_IRQ0_IRQSTAT_gioirq_MASK                              0x00000100
+#define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT                             8
+#define BCHP_IRQ0_IRQSTAT_gioirq_DEFAULT                           0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicdirq [07:07] */
+#define BCHP_IRQ0_IRQSTAT_iicdirq_MASK                             0x00000080
+#define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT                            7
+#define BCHP_IRQ0_IRQSTAT_iicdirq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: iicairq [06:06] */
+#define BCHP_IRQ0_IRQSTAT_iicairq_MASK                             0x00000040
+#define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT                            6
+#define BCHP_IRQ0_IRQSTAT_iicairq_DEFAULT                          0x00000000
+
+/* IRQ0 :: IRQSTAT :: ucirq [05:05] */
+#define BCHP_IRQ0_IRQSTAT_ucirq_MASK                               0x00000020
+#define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT                              5
+#define BCHP_IRQ0_IRQSTAT_ucirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: ubirq [04:04] */
+#define BCHP_IRQ0_IRQSTAT_ubirq_MASK                               0x00000010
+#define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT                              4
+#define BCHP_IRQ0_IRQSTAT_ubirq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uairq [03:03] */
+#define BCHP_IRQ0_IRQSTAT_uairq_MASK                               0x00000008
+#define BCHP_IRQ0_IRQSTAT_uairq_SHIFT                              3
+#define BCHP_IRQ0_IRQSTAT_uairq_DEFAULT                            0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartc_irq [02:02] */
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK                           0x00000004
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT                          2
+#define BCHP_IRQ0_IRQSTAT_uartc_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uartb_irq [01:01] */
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK                           0x00000002
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT                          1
+#define BCHP_IRQ0_IRQSTAT_uartb_irq_DEFAULT                        0x00000000
+
+/* IRQ0 :: IRQSTAT :: uarta_irq [00:00] */
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK                           0x00000001
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT                          0
+#define BCHP_IRQ0_IRQSTAT_uarta_irq_DEFAULT                        0x00000000
+
+#endif /* #ifndef BCHP_IRQ0_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_nand.h b/include/linux/brcmstb/7364a0/bchp_nand.h
new file mode 100644
index 000000000000..7afb1f9ada10
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_nand.h
@@ -0,0 +1,3757 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:40 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_NAND_H__
+#define BCHP_NAND_H__
+
+/***************************************************************************
+ *NAND - Nand Flash Control Registers
+ ***************************************************************************/
+#define BCHP_NAND_REVISION                       0x00442800 /* NAND Revision */
+#define BCHP_NAND_CMD_START                      0x00442804 /* Nand Flash Command Start */
+#define BCHP_NAND_CMD_EXT_ADDRESS                0x00442808 /* Nand Flash Command Extended Address */
+#define BCHP_NAND_CMD_ADDRESS                    0x0044280c /* Nand Flash Command Address */
+#define BCHP_NAND_CMD_END_ADDRESS                0x00442810 /* Nand Flash Command End Address */
+#define BCHP_NAND_INTFC_STATUS                   0x00442814 /* Nand Flash Interface Status */
+#define BCHP_NAND_CS_NAND_SELECT                 0x00442818 /* Nand Flash EBI CS Select */
+#define BCHP_NAND_CS_NAND_XOR                    0x0044281c /* Nand Flash EBI CS XOR masking on CPU address Control */
+#define BCHP_NAND_LL_OP                          0x00442820 /* Nand Flash Low Level Operation */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x00442824 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x00442828 /* Nand Flash Multiplane base address */
+#define BCHP_NAND_ACC_CONTROL_CS0                0x00442850 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS0                 0x00442854 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS0                     0x00442858 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS0                   0x0044285c /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS0                   0x00442860 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS1                0x00442864 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS1                 0x00442868 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS1                     0x0044286c /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS1                   0x00442870 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS1                   0x00442874 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS2                0x00442878 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS2                 0x0044287c /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS2                     0x00442880 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS2                   0x00442884 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS2                   0x00442888 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS3                0x0044288c /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS3                 0x00442890 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS3                     0x00442894 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS3                   0x00442898 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS3                   0x0044289c /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS4                0x004428a0 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS4                 0x004428a4 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS4                     0x004428a8 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS4                   0x004428ac /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS4                   0x004428b0 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS5                0x004428b4 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS5                 0x004428b8 /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS5                     0x004428bc /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS5                   0x004428c0 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS5                   0x004428c4 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_ACC_CONTROL_CS6                0x004428c8 /* Nand Flash Access Control */
+#define BCHP_NAND_CONFIG_EXT_CS6                 0x004428cc /* Nand Flash Config Extension */
+#define BCHP_NAND_CONFIG_CS6                     0x004428d0 /* Nand Flash Config */
+#define BCHP_NAND_TIMING_1_CS6                   0x004428d4 /* Nand Flash Timing Parameters 1 */
+#define BCHP_NAND_TIMING_2_CS6                   0x004428d8 /* Nand Flash Timing Parameters 2 */
+#define BCHP_NAND_CORR_STAT_THRESHOLD            0x004428dc /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x004428e0 /* Correctable Error Reporting Threshold */
+#define BCHP_NAND_BLK_WR_PROTECT                 0x004428e4 /* Block Write Protect Enable and Size for EBI_CS0b */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x004428e8 /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x004428ec /* Nand Flash Multiplane Customized Opcodes */
+#define BCHP_NAND_MULTIPLANE_CTRL                0x004428f0 /* Nand Flash Multiplane Control */
+#define BCHP_NAND_UNCORR_ERROR_COUNT             0x004428fc /* Read Uncorrectable Event Count */
+#define BCHP_NAND_CORR_ERROR_COUNT               0x00442900 /* Read Error Count */
+#define BCHP_NAND_READ_ERROR_COUNT               0x00442904 /* Read Error Count */
+#define BCHP_NAND_BLOCK_LOCK_STATUS              0x00442908 /* Nand Flash Block Lock Status */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x0044290c /* ECC Correctable Error Extended Address */
+#define BCHP_NAND_ECC_CORR_ADDR                  0x00442910 /* ECC Correctable Error Address */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x00442914 /* ECC Uncorrectable Error Extended Address */
+#define BCHP_NAND_ECC_UNC_ADDR                   0x00442918 /* ECC Uncorrectable Error Address */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x0044291c /* Flash Read Data Extended Address */
+#define BCHP_NAND_FLASH_READ_ADDR                0x00442920 /* Flash Read Data Address */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x00442924 /* Page Program Extended Address */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x00442928 /* Page Program Address */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x0044292c /* Copy Back Extended Address */
+#define BCHP_NAND_COPY_BACK_ADDR                 0x00442930 /* Copy Back Address */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x00442934 /* Block Erase Extended Address */
+#define BCHP_NAND_BLOCK_ERASE_ADDR               0x00442938 /* Block Erase Address */
+#define BCHP_NAND_INV_READ_EXT_ADDR              0x0044293c /* Flash Invalid Data Extended Address */
+#define BCHP_NAND_INV_READ_ADDR                  0x00442940 /* Flash Invalid Data Address */
+#define BCHP_NAND_INIT_STATUS                    0x00442944 /* Initialization status */
+#define BCHP_NAND_ONFI_STATUS                    0x00442948 /* ONFI Status */
+#define BCHP_NAND_ONFI_DEBUG_DATA                0x0044294c /* ONFI Debug Data */
+#define BCHP_NAND_SEMAPHORE                      0x00442950 /* Semaphore */
+#define BCHP_NAND_FLASH_DEVICE_ID                0x00442994 /* Nand Flash Device ID */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x00442998 /* Nand Flash Extended Device ID */
+#define BCHP_NAND_LL_RDDATA                      0x0044299c /* Nand Flash Low Level Read Data */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x00442a00 /* Nand Flash Spare Area Read Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x00442a04 /* Nand Flash Spare Area Read Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x00442a08 /* Nand Flash Spare Area Read Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x00442a0c /* Nand Flash Spare Area Read Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x00442a10 /* Nand Flash Spare Area Read Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x00442a14 /* Nand Flash Spare Area Read Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x00442a18 /* Nand Flash Spare Area Read Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x00442a1c /* Nand Flash Spare Area Read Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x00442a20 /* Nand Flash Spare Area Read Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x00442a24 /* Nand Flash Spare Area Read Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x00442a28 /* Nand Flash Spare Area Read Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x00442a2c /* Nand Flash Spare Area Read Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x00442a30 /* Nand Flash Spare Area Read Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x00442a34 /* Nand Flash Spare Area Read Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x00442a38 /* Nand Flash Spare Area Read Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x00442a3c /* Nand Flash Spare Area Read Bytes 60-63 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x00442a80 /* Nand Flash Spare Area Write Bytes 0-3 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x00442a84 /* Nand Flash Spare Area Write Bytes 4-7 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x00442a88 /* Nand Flash Spare Area Write Bytes 8-11 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x00442a8c /* Nand Flash Spare Area Write Bytes 12-15 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x00442a90 /* Nand Flash Spare Area Write Bytes 16-19 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x00442a94 /* Nand Flash Spare Area Write Bytes 20-23 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x00442a98 /* Nand Flash Spare Area Write Bytes 24-27 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x00442a9c /* Nand Flash Spare Area Write Bytes 28-31 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x00442aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x00442aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x00442aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x00442aac /* Nand Flash Spare Area Write Bytes 44-47 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x00442ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x00442ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x00442ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x00442abc /* Nand Flash Spare Area Write Bytes 60-63 */
+#define BCHP_NAND_DDR_TIMING                     0x00442ac0 /* Nand Flash DDR TIMING */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL             0x00442ac4 /* Nand Flash Calibration Control for Master DLL */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD          0x00442ac8 /* Nand Flash Calibration Period */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT            0x00442acc /* Nand Flash Calibration Status for Master DLL */
+#define BCHP_NAND_DDR_NCDL_MODE                  0x00442ad0 /* Nand Flash NCDL mode for Slave DLLs */
+#define BCHP_NAND_DDR_NCDL_OFFSET                0x00442ad4 /* Nand Flash NCDL offset for Slave DLLs */
+#define BCHP_NAND_DDR_PHY_CTL                    0x00442ad8 /* Nand Flash DDR PHY CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_CTL               0x00442adc /* Nand Flash DDR PHY BIST CONTROL */
+#define BCHP_NAND_DDR_PHY_BIST_STAT              0x00442ae0 /* Nand Flash DDR PHY BIST STATUS */
+#define BCHP_NAND_DDR_DIAG_STAT0                 0x00442ae4 /* Nand Flash DDR DIAG STATUS0 */
+#define BCHP_NAND_DDR_DIAG_STAT1                 0x00442ae8 /* Nand Flash DDR DIAG STATUS1 */
+
+/***************************************************************************
+ *REVISION - NAND Revision
+ ***************************************************************************/
+/* NAND :: REVISION :: reserved0 [31:16] */
+#define BCHP_NAND_REVISION_reserved0_MASK                          0xffff0000
+#define BCHP_NAND_REVISION_reserved0_SHIFT                         16
+
+/* NAND :: REVISION :: MAJOR [15:08] */
+#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
+#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
+#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000007
+
+/* NAND :: REVISION :: MINOR [07:00] */
+#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
+#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
+#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000001
+
+/***************************************************************************
+ *CMD_START - Nand Flash Command Start
+ ***************************************************************************/
+/* NAND :: CMD_START :: reserved0 [31:05] */
+#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
+#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5
+
+/* NAND :: CMD_START :: OPCODE [04:00] */
+#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
+#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
+#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
+#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
+#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
+#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
+#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
+#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
+#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
+#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
+#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
+#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
+#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
+#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
+#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
+#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21
+
+/***************************************************************************
+ *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
+ ***************************************************************************/
+/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
+#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19
+
+/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
+#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000
+
+/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
+#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *CMD_ADDRESS - Nand Flash Command Address
+ ***************************************************************************/
+/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
+#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000
+
+/***************************************************************************
+ *CMD_END_ADDRESS - Nand Flash Command End Address
+ ***************************************************************************/
+/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
+#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *INTFC_STATUS - Nand Flash Interface Status
+ ***************************************************************************/
+/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
+#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31
+
+/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
+#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30
+
+/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
+#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29
+
+/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
+#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28
+
+/* NAND :: INTFC_STATUS :: ERASED [27:27] */
+#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
+#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27
+
+/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
+#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26
+
+/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
+#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
+#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8
+
+/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
+#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *CS_NAND_SELECT - Nand Flash EBI CS Select
+ ***************************************************************************/
+/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
+#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
+#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30
+
+/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK                      0x20000000
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT                     29
+#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT                   0x00000001
+
+/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
+#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000
+
+/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x0fff0000
+#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   16
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000
+
+/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
+#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0
+
+/***************************************************************************
+ *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
+ ***************************************************************************/
+/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK                0x80000000
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT               31
+#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT             0x00000000
+
+/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
+#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
+#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK               0x00000080
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT              7
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK               0x00000040
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT              6
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK               0x00000020
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT              5
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK               0x00000010
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT              4
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK               0x00000008
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT              3
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK               0x00000004
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT              2
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK               0x00000002
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT              1
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT            0x00000000
+
+/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK               0x00000001
+#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT              0
+
+/***************************************************************************
+ *LL_OP - Nand Flash Low Level Operation
+ ***************************************************************************/
+/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
+#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
+#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
+#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000
+
+/* NAND :: LL_OP :: reserved0 [30:20] */
+#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
+#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20
+
+/* NAND :: LL_OP :: CLE [19:19] */
+#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
+#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
+#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: ALE [18:18] */
+#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
+#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
+#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000
+
+/* NAND :: LL_OP :: WE [17:17] */
+#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
+#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
+#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: RE [16:16] */
+#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
+#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
+#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000
+
+/* NAND :: LL_OP :: DATA [15:00] */
+#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
+#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
+#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16
+
+/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
+#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000
+
+/***************************************************************************
+ *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
+ ***************************************************************************/
+/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
+#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *ACC_CONTROL_CS0 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS0 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS0 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS0_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS0 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS0_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS0 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS0_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS0 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS0 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS0 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS0 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS0 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS0 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS0 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS0_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS0_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS0_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS0_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS0_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS1 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS1 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS1 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS1_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS1 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS1_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS1 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS1_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS1 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS1 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS1 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS1 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS1 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS1 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS1 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS1_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS1_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS1_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS1_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS1_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS2 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS2 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS2 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS2_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS2 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS2_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS2 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS2_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS2 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS2 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS2 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS2 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS2 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS2 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS2 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS2_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS2_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS2_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS2_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS2_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS3 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS3 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS3 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS3_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS3 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS3_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS3 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS3_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS3 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS3 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS3 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS3 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS3 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS3 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS3 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS3_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS3_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS3_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS3_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS3_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS4 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS4 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS4 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS4_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS4 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS4_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS4 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS4_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS4 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS4 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS4 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS4 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS4 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS4 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS4 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS4_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS4_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS4_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS4_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS4_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS5 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS5 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS5 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS5_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS5 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS5_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS5 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS5_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS5 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS5 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS5 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS5 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS5 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS5 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS5 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS5_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS5_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS5_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS5_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS5_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *ACC_CONTROL_CS6 - Nand Flash Access Control
+ ***************************************************************************/
+/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK                   0x80000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT                  31
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK                   0x40000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT                  30
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT                0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK                     0x20000000
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT                    29
+#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT                  0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK                   0x10000000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT                  28
+
+/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK            0x08000000
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT           27
+#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT         0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK             0x04000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT            26
+#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT          0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK               0x02000000
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT              25
+#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT            0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK                 0x01000000
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT                24
+#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT              0x00000001
+
+/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK                 0x00800000
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT                23
+#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT              0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK               0x00400000
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT              22
+#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT            0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK                   0x00200000
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT                  21
+
+/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK                   0x001f0000
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT                  16
+#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT                0x0000000f
+
+/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK                   0x0000ff00
+#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT                  8
+
+/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK              0x00000080
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT             7
+#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT           0x00000000
+
+/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK             0x0000007f
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT            0
+#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT          0x00000010
+
+/***************************************************************************
+ *CONFIG_EXT_CS6 - Nand Flash Config Extension
+ ***************************************************************************/
+/* NAND :: CONFIG_EXT_CS6 :: reserved0 [31:12] */
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_MASK                    0xfffff000
+#define BCHP_NAND_CONFIG_EXT_CS6_reserved0_SHIFT                   12
+
+/* NAND :: CONFIG_EXT_CS6 :: BLOCK_SIZE [11:04] */
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_MASK                   0x00000ff0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_SHIFT                  4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8KB            0
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_16KB           1
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_32KB           2
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_64KB           3
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_128KB          4
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_256KB          5
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_512KB          6
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_1024KB         7
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_2048KB         8
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_4096KB         9
+#define BCHP_NAND_CONFIG_EXT_CS6_BLOCK_SIZE_BK_SIZE_8192KB         10
+
+/* NAND :: CONFIG_EXT_CS6 :: PAGE_SIZE [03:00] */
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_MASK                    0x0000000f
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_SHIFT                   0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_512             0
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_1KB             1
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_2KB             2
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_4KB             3
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_8KB             4
+#define BCHP_NAND_CONFIG_EXT_CS6_PAGE_SIZE_PG_SIZE_16KB            5
+
+/***************************************************************************
+ *CONFIG_CS6 - Nand Flash Config
+ ***************************************************************************/
+/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK                      0x80000000
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT                     31
+#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT                   0x00000000
+
+/* NAND :: CONFIG_CS6 :: reserved0 [30:28] */
+#define BCHP_NAND_CONFIG_CS6_reserved0_MASK                        0x70000000
+#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT                       28
+
+/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK                      0x0f000000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT                     24
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB              1
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB             2
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB             3
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB             4
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB            5
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB            6
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB            7
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB              8
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB              9
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB              10
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB              11
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB             12
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB             13
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB             14
+#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB            15
+
+/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK                     0x00800000
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT                    23
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8              0
+#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16             1
+
+/* NAND :: CONFIG_CS6 :: reserved1 [22:19] */
+#define BCHP_NAND_CONFIG_CS6_reserved1_MASK                        0x00780000
+#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT                       19
+
+/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK                    0x00070000
+#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT                   16
+
+/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
+#define BCHP_NAND_CONFIG_CS6_reserved2_MASK                        0x00008000
+#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT                       15
+
+/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK                    0x00007000
+#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT                   12
+
+/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
+#define BCHP_NAND_CONFIG_CS6_reserved3_MASK                        0x00000800
+#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT                       11
+
+/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK                    0x00000700
+#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT                   8
+
+/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
+#define BCHP_NAND_CONFIG_CS6_reserved4_MASK                        0x000000ff
+#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT                       0
+
+/***************************************************************************
+ *TIMING_1_CS6 - Nand Flash Timing Parameters 1
+ ***************************************************************************/
+/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
+#define BCHP_NAND_TIMING_1_CS6_tWP_MASK                            0xf0000000
+#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT                           28
+#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT                         0x00000006
+
+/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
+#define BCHP_NAND_TIMING_1_CS6_tWH_MASK                            0x0f000000
+#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT                           24
+#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT                         0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
+#define BCHP_NAND_TIMING_1_CS6_tRP_MASK                            0x00f00000
+#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT                           20
+#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT                         0x00000007
+
+/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
+#define BCHP_NAND_TIMING_1_CS6_tREH_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT                          16
+#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
+#define BCHP_NAND_TIMING_1_CS6_tCS_MASK                            0x0000f000
+#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT                           12
+#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT                         0x00000008
+
+/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
+#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK                           0x00000f00
+#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT                          8
+#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT                        0x00000004
+
+/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
+#define BCHP_NAND_TIMING_1_CS6_tALH_MASK                           0x000000f0
+#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT                          4
+#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT                        0x00000005
+
+/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
+#define BCHP_NAND_TIMING_1_CS6_tADL_MASK                           0x0000000f
+#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT                          0
+#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT                        0x0000000b
+
+/***************************************************************************
+ *TIMING_2_CS6 - Nand Flash Timing Parameters 2
+ ***************************************************************************/
+/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK                     0x80000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT                    31
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT                  0x00000000
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108                  0
+#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216                  1
+
+/* NAND :: TIMING_2_CS6 :: reserved0 [30:20] */
+#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK                      0x7ff00000
+#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT                     20
+
+/* NAND :: TIMING_2_CS6 :: tCCS [19:16] */
+#define BCHP_NAND_TIMING_2_CS6_tCCS_MASK                           0x000f0000
+#define BCHP_NAND_TIMING_2_CS6_tCCS_SHIFT                          16
+#define BCHP_NAND_TIMING_2_CS6_tCCS_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: reserved1 [15:13] */
+#define BCHP_NAND_TIMING_2_CS6_reserved1_MASK                      0x0000e000
+#define BCHP_NAND_TIMING_2_CS6_reserved1_SHIFT                     13
+
+/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
+#define BCHP_NAND_TIMING_2_CS6_tWB_MASK                            0x00001e00
+#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT                           9
+#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT                         0x0000000f
+
+/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
+#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK                           0x000001f0
+#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT                          4
+#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT                        0x00000009
+
+/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
+#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK                          0x0000000f
+#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT                         0
+#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT                       0x00000006
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001
+
+/***************************************************************************
+ *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
+ ***************************************************************************/
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xfffff000
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          12
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001
+
+/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
+#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001
+
+/***************************************************************************
+ *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
+ ***************************************************************************/
+/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
+#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080
+
+/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
+#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010
+
+/***************************************************************************
+ *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customized Opcodes
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000
+
+/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
+#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000
+
+/***************************************************************************
+ *MULTIPLANE_CTRL - Nand Flash Multiplane Control
+ ***************************************************************************/
+/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
+#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
+#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000
+
+/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
+#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0
+
+/***************************************************************************
+ *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
+ ***************************************************************************/
+/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
+#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *CORR_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *READ_ERROR_COUNT - Read Error Count
+ ***************************************************************************/
+/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
+#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000
+
+/***************************************************************************
+ *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
+ ***************************************************************************/
+/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
+#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8
+
+/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
+#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *ECC_CORR_ADDR - ECC Correctable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19
+
+/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000
+
+/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
+#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000
+
+/***************************************************************************
+ *ECC_UNC_ADDR - ECC Uncorrectable Error Address
+ ***************************************************************************/
+/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
+#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19
+
+/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000
+
+/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
+#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000
+
+/***************************************************************************
+ *FLASH_READ_ADDR - Flash Read Data Address
+ ***************************************************************************/
+/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
+#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000
+
+/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
+#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000
+
+/***************************************************************************
+ *PROGRAM_PAGE_ADDR - Page Program Address
+ ***************************************************************************/
+/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
+#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000
+
+/***************************************************************************
+ *COPY_BACK_EXT_ADDR - Copy Back Extended Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19
+
+/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000
+
+/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
+#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000
+
+/***************************************************************************
+ *COPY_BACK_ADDR - Copy Back Address
+ ***************************************************************************/
+/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
+#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000
+
+/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
+#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000
+
+/***************************************************************************
+ *BLOCK_ERASE_ADDR - Block Erase Address
+ ***************************************************************************/
+/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
+#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
+ ***************************************************************************/
+/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
+#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19
+
+/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
+#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000
+
+/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
+#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000
+
+/***************************************************************************
+ *INV_READ_ADDR - Flash Invalid Data Address
+ ***************************************************************************/
+/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
+#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *INIT_STATUS - Initialization status
+ ***************************************************************************/
+/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
+#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31
+
+/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
+#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30
+
+/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
+#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29
+
+/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
+#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28
+
+/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
+#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27
+
+/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
+#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26
+
+/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
+#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25
+
+/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
+#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24
+
+/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
+#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23
+
+/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
+#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22
+
+/* NAND :: INIT_STATUS :: reserved0 [21:00] */
+#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
+#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0
+
+/***************************************************************************
+ *ONFI_STATUS - ONFI Status
+ ***************************************************************************/
+/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
+#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000
+
+/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
+#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27
+
+/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
+#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
+#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4
+
+/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
+#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1
+
+/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
+#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0
+
+/***************************************************************************
+ *ONFI_DEBUG_DATA - ONFI Debug Data
+ ***************************************************************************/
+/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
+#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0
+
+/***************************************************************************
+ *SEMAPHORE - Semaphore
+ ***************************************************************************/
+/* NAND :: SEMAPHORE :: reserved0 [31:08] */
+#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
+#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8
+
+/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
+#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *FLASH_DEVICE_ID - Nand Flash Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8
+
+/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0
+
+/***************************************************************************
+ *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
+ ***************************************************************************/
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8
+
+/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
+#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0
+
+/***************************************************************************
+ *LL_RDDATA - Nand Flash Low Level Read Data
+ ***************************************************************************/
+/* NAND :: LL_RDDATA :: reserved0 [31:16] */
+#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
+#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16
+
+/* NAND :: LL_RDDATA :: DATA [15:00] */
+#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
+#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
+#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
+ ***************************************************************************/
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff
+
+/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
+#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff
+
+/***************************************************************************
+ *DDR_TIMING - Nand Flash DDR TIMING
+ ***************************************************************************/
+/* NAND :: DDR_TIMING :: reserved0 [31:28] */
+#define BCHP_NAND_DDR_TIMING_reserved0_MASK                        0xf0000000
+#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT                       28
+
+/* NAND :: DDR_TIMING :: tCCS [27:24] */
+#define BCHP_NAND_DDR_TIMING_tCCS_MASK                             0x0f000000
+#define BCHP_NAND_DDR_TIMING_tCCS_SHIFT                            24
+#define BCHP_NAND_DDR_TIMING_tCCS_DEFAULT                          0x00000008
+
+/* NAND :: DDR_TIMING :: tCAD [23:20] */
+#define BCHP_NAND_DDR_TIMING_tCAD_MASK                             0x00f00000
+#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT                            20
+#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT                          0x00000004
+
+/* NAND :: DDR_TIMING :: reserved1 [19:17] */
+#define BCHP_NAND_DDR_TIMING_reserved1_MASK                        0x000e0000
+#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT                       17
+
+/* NAND :: DDR_TIMING :: tWHR [16:12] */
+#define BCHP_NAND_DDR_TIMING_tWHR_MASK                             0x0001f000
+#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT                            12
+#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT                          0x00000014
+
+/* NAND :: DDR_TIMING :: tCS [11:08] */
+#define BCHP_NAND_DDR_TIMING_tCS_MASK                              0x00000f00
+#define BCHP_NAND_DDR_TIMING_tCS_SHIFT                             8
+#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT                           0x00000002
+
+/* NAND :: DDR_TIMING :: tWB [07:04] */
+#define BCHP_NAND_DDR_TIMING_tWB_MASK                              0x000000f0
+#define BCHP_NAND_DDR_TIMING_tWB_SHIFT                             4
+#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT                           0x0000000f
+
+/* NAND :: DDR_TIMING :: tADL [03:00] */
+#define BCHP_NAND_DDR_TIMING_tADL_MASK                             0x0000000f
+#define BCHP_NAND_DDR_TIMING_tADL_SHIFT                            0
+#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT                          0x00000007
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK                0xfffffff0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT               4
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK           0x00000008
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT          3
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT        0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK             0x00000004
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT            2
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT          0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK               0x00000002
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT              1
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT            0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK                 0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT                0
+#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK             0xfff00000
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT            20
+
+/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK          0x000fffff
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT         0
+#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT       0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK               0xffff0000
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT              16
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK              0x0000ff00
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT             8
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT           0x00000000
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK               0x000000fe
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT              1
+
+/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK              0x00000001
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT             0
+#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT           0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK                     0xffffffe0
+#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT                    5
+
+/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK                        0x00000010
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT                       4
+#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT                     0x00000000
+
+/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK                     0x0000000e
+#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT                    1
+
+/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK                        0x00000001
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT                       0
+#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
+ ***************************************************************************/
+/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK                   0xfe000000
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT                  25
+
+/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK                  0x01ff0000
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT                 16
+#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT               0x00000000
+
+/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK                   0x0000fe00
+#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT                  9
+
+/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK                  0x000001ff
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT                 0
+#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT               0x00000000
+
+/***************************************************************************
+ *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK                       0xfffffffc
+#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT                      2
+
+/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK                        0x00000002
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT                       1
+#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT                     0x00000000
+
+/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK                       0x00000001
+#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT                      0
+
+/***************************************************************************
+ *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK                  0xffffffe0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT                 5
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK                   0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT                  4
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT                0x00000000
+
+/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK                  0x0000000e
+#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT                 1
+
+/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT                0
+#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT              0x00000000
+
+/***************************************************************************
+ *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
+ ***************************************************************************/
+/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK                 0xffffff80
+#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT                7
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK          0x00000040
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT         6
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK          0x00000020
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT         5
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK          0x00000010
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT         4
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK          0x00000008
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT         3
+
+/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK               0x00000004
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT              2
+
+/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK               0x00000002
+#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT              1
+
+/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK                 0x00000001
+#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT                0
+
+/***************************************************************************
+ *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
+ ***************************************************************************/
+/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK                  0xffffffff
+#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT                 0
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x00442c00
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
+#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32
+
+/***************************************************************************
+ *FLASH_CACHE%i - Flash Cache Buffer Read Access
+ ***************************************************************************/
+/* NAND :: FLASH_CACHEi :: WORD [31:00] */
+#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
+#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0
+
+
+#endif /* #ifndef BCHP_NAND_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_sdio_0_cfg.h b/include/linux/brcmstb/7364a0/bchp_sdio_0_cfg.h
new file mode 100644
index 000000000000..fa82bff95400
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_sdio_0_cfg.h
@@ -0,0 +1,827 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Thu Sep  4 03:29:02 2014
+ *                 Full Compile MD5 Checksum 1782df3043f929698a3869b835cd123a
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              6296cc47ae2b74764e7827f243438799
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SDIO_0_CFG_H__
+#define BCHP_SDIO_0_CFG_H__
+
+/***************************************************************************
+ *SDIO_0_CFG - SDIO (CARD) Configuration Registers
+ ***************************************************************************/
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00440100 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00440104 /* SDIO EMMC Control Register */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00440108 /* SDIO TP_OUT Control Register */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE         0x0044010c /* SDIO CAPABILITIES override Register */
+#define BCHP_SDIO_0_CFG_CAP_REG0                 0x00440110 /* SDIO CAPABILITIES override Register[31:0] */
+#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00440114 /* SDIO CAPABILITIES override Register[63:32] */
+#define BCHP_SDIO_0_CFG_PRESET1                  0x00440118 /* SDIO PRESET_INIT/PRESET_DS override Register */
+#define BCHP_SDIO_0_CFG_PRESET2                  0x0044011c /* SDIO PRESET_HS/PRESET_SDR12 override Register */
+#define BCHP_SDIO_0_CFG_PRESET3                  0x00440120 /* SDIO PRESET_SDR25/PRESET_SDR50 override Register */
+#define BCHP_SDIO_0_CFG_PRESET4                  0x00440124 /* SDIO PRESET_SDR104/PRESET_DDR50 override Register */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x00440128 /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x0044012c /* SDIO Clock delay register */
+#define BCHP_SDIO_0_CFG_IP_DLY                   0x00440130 /* SDIO Host input delay register */
+#define BCHP_SDIO_0_CFG_OP_DLY                   0x00440134 /* SDIO Host output delay register */
+#define BCHP_SDIO_0_CFG_TUNING                   0x00440138 /* SDIO Host tuning configuration register */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0044013c /* SDIO Host 1p8V control logic select register */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY            0x00440140 /* Debug TAP delay setting register */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS  0x00440144 /* Debug A2S Bridge Status */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x00440148 /* Debug register to read AHB req start address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR   0x0044014c /* Debug register to read AHB req end address (32b) */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x00440150 /* Disable Client Init */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL               0x00440154 /* SD Pin Select */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT              0x00440158 /* Max Current Override */
+#define BCHP_SDIO_0_CFG_VERSION                  0x004401f0 /* SDIO VERSION Register */
+#define BCHP_SDIO_0_CFG_SCRATCH                  0x004401fc /* SDIO Scratch Register */
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK             0x0ffc0000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT            18
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK        0x00020000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT       17
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT     0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK             0x000003fc
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT            2
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK          0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT         0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT       0x00000003
+
+/***************************************************************************
+ *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000
+
+/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
+#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000
+
+/***************************************************************************
+ *TP_OUT_SEL - SDIO TP_OUT Control Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000003
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
+#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000
+
+/***************************************************************************
+ *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK            0xfffffffe
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT           1
+
+/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK     0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT    0
+#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0xc0000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   30
+#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK                     0x20000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT                    29
+#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK                0x10000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT               28
+#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK                    0x08000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT                   27
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK                 0x04000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT                26
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK                 0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT                25
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK                 0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT                24
+#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK               0x00800000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT              23
+#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK                         0x00400000
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT                        22
+#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT                      0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK                   0x00200000
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT                  21
+#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK                    0x00100000
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT                   20
+
+/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK                        0x00080000
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT                       19
+#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK               0x00040000
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT              18
+#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK                0x00030000
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT               16
+#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK                0x0000ff00
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT               8
+#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK                 0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT                7
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK                    0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT                   6
+
+/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK             0x0000003f
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT            0
+#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT          0x00000000
+
+/***************************************************************************
+ *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
+ ***************************************************************************/
+/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0xfc000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   26
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK               0x02000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT              25
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT            0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x01000000
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    24
+#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x00ff0000
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    16
+#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK                0x0000c000
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT               14
+#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK                   0x00002000
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT                  13
+#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK                    0x00001000
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT                   12
+
+/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK                  0x00000f00
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT                 8
+#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK                    0x00000080
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT                   7
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK                     0x00000040
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT                    6
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK                     0x00000020
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT                    5
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK                     0x00000010
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT                    4
+#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT                  0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT                   3
+
+/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK                        0x00000004
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT                       2
+#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT                     0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK                       0x00000002
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT                      1
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT                    0x00000000
+
+/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK                        0x00000001
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT                       0
+#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT                     0x00000000
+
+/***************************************************************************
+ *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK                   0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT                  16
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT                0x00000000
+
+/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT                  0x00000001
+
+/***************************************************************************
+ *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK                     0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT                    0
+#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT                  0x00000003
+
+/***************************************************************************
+ *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK                  0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT                 0
+#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT               0x00000003
+
+/***************************************************************************
+ *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT             31
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT           0x00000000
+
+/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK                     0x60000000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT                    29
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK                  0x1fff0000
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT                 16
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT               0x00000002
+
+/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK                     0x0000e000
+#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT                    13
+
+/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK                 0x00001fff
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT                0
+#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT              0x00000003
+
+/***************************************************************************
+ *SD_CLOCK_DELAY - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f
+
+/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
+#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f
+
+/***************************************************************************
+ *SD_PAD_DRV - SDIO Clock delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3
+
+/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
+#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005
+
+/***************************************************************************
+ *IP_DLY - SDIO Host input delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
+#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6
+
+/* SDIO_0_CFG :: IP_DLY :: reserved_for_padding2 [05:05] */
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_MASK          0x00000020
+#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_SHIFT         5
+
+/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000001f
+#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *OP_DLY - SDIO Host output delay register
+ ***************************************************************************/
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31
+
+/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18
+
+/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
+#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4
+
+/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
+#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0
+
+/***************************************************************************
+ *TUNING - SDIO Host tuning configuration register
+ ***************************************************************************/
+/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xffffffc0
+#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     6
+
+/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK                   0x0000003f
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT                  0
+#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT                0x00000020
+
+/***************************************************************************
+ *VOLT_CTRL - SDIO Host 1p8V control logic select register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5
+
+/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000
+
+/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
+#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000
+
+/***************************************************************************
+ *DEBUG_TAP_DLY - Debug TAP delay setting register
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK               0xfffff000
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT              12
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK      0x00000f00
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT     8
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK               0x00000080
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT              7
+
+/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK      0x0000007f
+#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT     0
+
+/***************************************************************************
+ *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK     0x60000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT    29
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK  0x10000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK     0x0e000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT    25
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK     0x0000ff80
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT    7
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK     0x00000070
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT    4
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK     0x00000008
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT    3
+
+/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK     0x00000007
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT    0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK   0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT  0
+
+/***************************************************************************
+ *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK       0xffffffff
+#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT      0
+
+/***************************************************************************
+ *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
+ ***************************************************************************/
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK   0xfffffffe
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT  1
+
+/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
+#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SD_PIN_SEL - SD Pin Select
+ ***************************************************************************/
+/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK                  0xfffffffc
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT                 2
+
+/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK                    0x00000003
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT                   0
+#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *MAX_CURRENT - Max Current Override
+ ***************************************************************************/
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK                  0x80000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT                 31
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT               0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK                 0x7f000000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT                24
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK             0x00ff0000
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT            16
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK             0x0000ff00
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT            8
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT          0x00000000
+
+/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK             0x000000ff
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT            0
+#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT          0x00000000
+
+/***************************************************************************
+ *VERSION - SDIO VERSION Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK                     0xff000000
+#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT                    24
+
+/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK                      0x00ff0000
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT                     16
+#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT                   0x00000003
+
+/* SDIO_0_CFG :: VERSION :: IP_VERSION [15:00] */
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_MASK                    0x0000ffff
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_SHIFT                   0
+#define BCHP_SDIO_0_CFG_VERSION_IP_VERSION_DEFAULT                 0x00001170
+
+/***************************************************************************
+ *SCRATCH - SDIO Scratch Register
+ ***************************************************************************/
+/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
+#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000
+
+#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_sun_top_ctrl.h b/include/linux/brcmstb/7364a0/bchp_sun_top_ctrl.h
new file mode 100644
index 000000000000..0703c1782d6a
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_sun_top_ctrl.h
@@ -0,0 +1,7485 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:43 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_SUN_TOP_CTRL_H__
+#define BCHP_SUN_TOP_CTRL_H__
+
+/***************************************************************************
+ *SUN_TOP_CTRL - Top Control registers
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID         0x00404000 /* Chip family ID */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID             0x00404004 /* Product Revision ID */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3       0x004040bc /* General status register 3 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4       0x004040c0 /* General status register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404138 /* Pad pull-up/pull-down control register 0 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x0040413c /* Pad pull-up/pull-down control register 1 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404140 /* Pad pull-up/pull-down control register 2 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404144 /* Pad pull-up/pull-down control register 3 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404148 /* Pad pull-up/pull-down control register 4 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x0040414c /* Pad pull-up/pull-down control register 5 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404150 /* Pad pull-up/pull-down control register 6 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404154 /* Pad pull-up/pull-down control register 7 */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404158 /* Pad pull-up/pull-down control register 8 */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x0040415c /* Bypass clock unselect register 0 */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404300 /* Reset control */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE    0x00404304 /* Reset source enable */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET        0x00404308 /* Software master reset */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION     0x0040430c /* Hardware reset extension */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR          0x00404310 /* Reset Monitor */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404314 /* Reset history */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET          0x00404318 /* Software init 0 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR        0x0040431c /* Software init 0 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS       0x00404320 /* Software init 0 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR  0x00404324 /* Security software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET          0x00404330 /* Software init 1 set */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR        0x00404334 /* Software init 1 clear */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS       0x00404338 /* Software init 1 status */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR  0x0040433c /* Security software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404364 /* Scratch register */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404368 /* Spare control bits reserved for future use */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404380 /* Test port control */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404384 /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404388 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040438c /* Testport peek register */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404390 /* Testport poke register */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404394 /* EJTAG input bus enables */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404398 /* EJTAG output select */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL             0x004043a0 /* VTRAP Control */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS           0x004043a4 /* VTRAP Status */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0      0x004043a8 /* UART Router select 0 */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1      0x004043ac /* UART Router select 1 */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404400 /* Serial Slave Port configuration register */
+#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404420 /* SERS Revision Register */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404424 /* SERS Configuration Register */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404514 /* Block select for RO testmode */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION     0x00404518 /* Test configuration */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2      0x0040451c /* OTP option test register */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2    0x00404520 /* OTP option status register */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6         0x00404528 /* General control register 6 */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7         0x0040452c /* General control register 7 */
+
+/***************************************************************************
+ *CHIP_FAMILY_ID - Chip family ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT    0x73640000
+
+/***************************************************************************
+ *PRODUCT_ID - Product Revision ID
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK               0xffffffff
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT            0x73640000
+
+/***************************************************************************
+ *BSP_FEATURE_TABLE_ADDR - BSP feature table address
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_0 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:07] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffff80
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            7
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [06:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK      0x0000007c
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT   0x00000018
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [01:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK            0x00000003
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT         0x00000000
+
+/***************************************************************************
+ *STRAP_VALUE_1 - Strapping values
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xffffffe0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            5
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias_enc [04:03] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_MASK  0x00000018
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_enc_DEFAULT 0x00000002
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_powerup [02:02] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_powerup_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_mhl_flash_boot [01:01] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_mhl_flash_boot_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK     0x00000001
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT  0x00000001
+
+/***************************************************************************
+ *BOND_STATUS - Bond option value register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1
+
+/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0
+
+/***************************************************************************
+ *OTP_OPTION_TEST_0 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_2 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_3 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_reserved_6 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_reserved_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0x001fe000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [11:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK         0x00000c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT        10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_1 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_capsense_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_directv_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_9 [25:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_MASK 0x03800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_ldpc_disable [22:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_MASK 0x00600000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_4 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_4_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tfec_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_0_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tuner_disable [10:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hevc_10_bit_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hevc_10_bit_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_5 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_func_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_func_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p1_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb_p0_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb_p0_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_reserved_1 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_reserved_1_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_0 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_2 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_2_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_2_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_3 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_3_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_reserved_6 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_6_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_reserved_6_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0x001fe000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [11:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK       0x00000c00
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT      10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_1 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_capsense_disable [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_SHIFT 31
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 30
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_directv_disable [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_SHIFT 29
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 28
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 27
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 26
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_9 [25:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_9_MASK 0x03800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_9_SHIFT 23
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_ldpc_disable [22:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_MASK 0x00600000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_SHIFT 21
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_4 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_4_SHIFT 20
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tfec_disable [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_SHIFT 19
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 18
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 17
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 16
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 15
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_1_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_0_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tuner_disable [10:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hevc_10_bit_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hevc_10_bit_disable_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_5 [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_5_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_5_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_func_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_func_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_func_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p1_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p1_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb_p0_disable [01:01] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb_p0_disable_SHIFT 1
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_reserved_1 [00:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_reserved_1_SHIFT 0
+
+/***************************************************************************
+ *SEMAPHORE_0 - Semaphore channel 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_1 - Semaphore channel 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_2 - Semaphore channel 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_3 - Semaphore channel 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_4 - Semaphore channel 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_5 - Semaphore channel 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_6 - Semaphore channel 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_7 - Semaphore channel 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_8 - Semaphore channel 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_9 - Semaphore channel 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT       0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_10 - Semaphore channel 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_11 - Semaphore channel 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_12 - Semaphore channel 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_13 - Semaphore channel 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_14 - Semaphore channel 14
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SEMAPHORE_15 - Semaphore channel 15
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8
+
+/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT      0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_0 - General watchdog timer 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GEN_WATCHDOG_1 - General watchdog timer 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_0 - General control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: bert_pinmux_ctrl [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_alt_pin_sel [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_MASK    0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_SHIFT   9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_alt_pin_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: rgmii_swap [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_rgmii_swap_DEFAULT        0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_1 - General control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xfffffff0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           4
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_edge_sel [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_en [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_2 - General control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_3 - General control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_4 - General control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_5 - General control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT   0x00000000
+
+/***************************************************************************
+ *GENERAL_STATUS_0 - General status register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         8
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK  0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: sat_wbafe_pll_lock [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_sat_wbafe_pll_lock_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_sat_wbafe_pll_lock_SHIFT 2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT    1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_1 - General status register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT   1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT   0
+
+/***************************************************************************
+ *GENERAL_STATUS_2 - General status register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         2
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK  0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1
+
+/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK  0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xfff00000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   20
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_19_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_18_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_16_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_6 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000007
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xff000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   24
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_023 [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_023_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_022 [22:22] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_022_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_021 [21:21] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_021_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_020 [20:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_020_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_019 [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_019_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_018 [18:18] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_018_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_017 [17:17] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_017_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_016 [16:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_016_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_015 [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_015_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_014 [14:14] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_014_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_013 [13:13] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_013_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_012 [12:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_012_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_011 [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_011_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_010 [10:10] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_010_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_009 [09:09] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_009_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_008 [08:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_008_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_007 [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_007_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_006 [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_006_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_005 [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_005_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_004 [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_004_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_003 [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_003_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_002 [02:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_002_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_001 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_001_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_000 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_000_DEFAULT 0x00000001
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xf0000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   28
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xffffff00
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   8
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7
+
+/***************************************************************************
+ *GENERAL_STATUS_3 - General status register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_STATUS_4 - General status register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0
+
+/***************************************************************************
+ *PIN_MUX_CTRL_0 - Pinmux control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_dsb [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_ONOFF_EBI_DSB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_SD_CARD1_LED 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_dsb_TSPI_S1_MOSI 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_tsb [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_MASK        0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_ONOFF_EBI_TSB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_SD_CARD1_PRES 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_tsb_TSPI_S1_MISO 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_rdb [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_MASK        0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_SHIFT       20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_DEFAULT     0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_ONOFF_EBI_RDB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_SD_CARD1_CLK_IN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_rdb_TSPI_S1_SCK 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_we0b [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_ONOFF_EBI_WE0B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_SD_CARD1_CLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_we0b_TSPI_S0_SS0B 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_nand_rbb [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_MASK   0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_SHIFT  12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_ONOFF_EBI_NAND_RBB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_SD_CARD1_CMD 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_nand_rbb_TSPI_S0_MOSI 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_cs2b [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_ONOFF_EBI_CS2B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs2b_TSPI_S0_MISO 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_ebi_cs1b [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_ONOFF_EBI_CS1B 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_ebi_cs1b_TSPI_S0_SCK 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: onoff_aud0_spdif [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_MASK     0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_ONOFF_AUD0_SPDIF 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_onoff_aud0_spdif_TP_OUT_26 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_1 - Pinmux control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_7 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_MASK     0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_SHIFT    28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_ONOFF_EBI_DATA_7 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_7_TSPI_S3_MOSI 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_6 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_MASK     0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_ONOFF_EBI_DATA_6 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_6_TSPI_S3_MISO 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_5 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_MASK     0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_ONOFF_EBI_DATA_5 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_5_TSPI_S3_SCK 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_4 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_MASK     0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_ONOFF_EBI_DATA_4 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_4_TSPI_S2_SS0B 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_3 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_MASK     0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_ONOFF_EBI_DATA_3 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_SD_CARD1_DAT3 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_3_TSPI_S2_MOSI 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_2 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_MASK     0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_ONOFF_EBI_DATA_2 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_SD_CARD1_DAT2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_2_TSPI_S2_MISO 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_1 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_MASK     0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_SHIFT    4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_ONOFF_EBI_DATA_1 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_SD_CARD1_DAT1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_1_TSPI_S2_SCK 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: onoff_ebi_data_0 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_MASK     0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_SHIFT    0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_DEFAULT  0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_ONOFF_EBI_DATA_0 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_SD_CARD1_DAT0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_onoff_ebi_data_0_TSPI_S1_SS0B 2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_2 - Pinmux control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_gpio_000 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_ONOFF_GPIO_000 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_CHIP2CI_MDO_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_EXT_IRQB_4 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_RMXP_DATA0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_RMX_DATA0  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_DFE_MPEG_DOUT0 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_TP_OUT_09  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_gpio_000_PM_GPIO_000 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ir_out [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_MASK         0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_SHIFT        24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_DEFAULT      0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_ONOFF_IR_OUT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ir_out_TP_OUT_25    1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_sgpio_01 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_ONOFF_SGPIO_01 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_MOCA_BSC_SDA 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_01_BSC_M3_SDA 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_sgpio_00 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_ONOFF_SGPIO_00 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_MOCA_BSC_SCL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_sgpio_00_BSC_M3_SCL 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_emmc_clk [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_ONOFF_EMMC_CLK 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_clk_PM_EMMC_CLK 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_emmc_cmd [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_ONOFF_EMMC_CMD 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_emmc_cmd_PM_EMMC_CMD 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_nand_dqs [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_MASK   0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_SHIFT  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_ONOFF_EBI_NAND_DQS 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_dqs_SD_CARD1_PWR0 1
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: onoff_ebi_nand_wpb [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_ONOFF_EBI_NAND_WPB 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_SD_CARD1_WPROT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_onoff_ebi_nand_wpb_TSPI_S3_SS0B 2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_3 - Pinmux control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_008 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_ONOFF_GPIO_008 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_CHIP2CI_MOSTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_RMXP_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_RMX_SYNC0  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_DFE_MPEG_SYNC 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_MTSIF1_RX_DATA_2_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_TP_IN_08   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_008_PM_GPIO_008 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_007 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_ONOFF_GPIO_007 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_CHIP2CI_MDO_7 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_USB1_PWRFLT_SEC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_RMXP_DATA7 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_RMX_PAUSE0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_DFE_MPEG_DOUT7 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_MTSIF1_RX_DATA_1_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_TP_IN_07   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_007_PM_GPIO_007 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_006 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_ONOFF_GPIO_006 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_CHIP2CI_MDO_6 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_USB1_PWRON_SEC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_RMXP_DATA6 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_DFE_MPEG_DOUT6 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_MTSIF1_RX_DATA_0_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_TP_IN_06   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_006_PM_GPIO_006 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_005 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_ONOFF_GPIO_005 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_CHIP2CI_MDO_5 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_USB0_PWRFLT_SEC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_RMXP_DATA5 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_RMX_CLK1   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_DFE_MPEG_DOUT5 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_SDS_BERT_CLK_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_TP_IN_05   7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_005_PM_GPIO_005 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_004 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_ONOFF_GPIO_004 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_CHIP2CI_MDO_4 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_USB0_PWRON_SEC 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_RMXP_DATA4 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_RMX_VALID1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_DFE_MPEG_DOUT4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_TP_OUT_13  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_004_PM_GPIO_004 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_003 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_ONOFF_GPIO_003 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_CHIP2CI_MDO_3 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_EXT_IRQB_7 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_RMXP_DATA3 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_RMX_SYNC1  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_DFE_MPEG_DOUT3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_TP_OUT_12  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_003_PM_GPIO_003 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_002 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_ONOFF_GPIO_002 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_CHIP2CI_MDO_2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_EXT_IRQB_6 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_RMXP_DATA2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_RMX_PAUSE1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_DFE_MPEG_DOUT2 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_TP_OUT_11  6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_002_PM_GPIO_002 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: onoff_gpio_001 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_ONOFF_GPIO_001 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_CHIP2CI_MDO_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_EXT_IRQB_5 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_RMXP_DATA1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_RMX_DATA1  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_DFE_MPEG_DOUT1 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_SDS_BERT_DATA_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_TP_OUT_10  7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_onoff_gpio_001_PM_GPIO_001 8
+
+/***************************************************************************
+ *PIN_MUX_CTRL_4 - Pinmux control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_016 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_ONOFF_GPIO_016 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_CI2CHIP_MDI_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PPKT_DATA0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PKT0_DATA  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_DFE_GPIO_0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_TP_IN_16   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_016_PM_GPIO_016 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_015 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_ONOFF_GPIO_015 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_CI2CHIP_MICLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_PPKT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_MTSIF1_RX_SYNC_ALT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_TP_IN_15   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_015_PM_GPIO_015 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_014 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_ONOFF_GPIO_014 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_CI2CHIP_MCLKI 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PPKT_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PKT0_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_MTSIF1_RX_CLK_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_TP_IN_14   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_014_PM_GPIO_014 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_013 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_ONOFF_GPIO_013 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_CI2CHIP_MIVAL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PPKT_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PKT0_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_MTSIF1_RX_DATA_7_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_TP_IN_13   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_013_PM_GPIO_013 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_012 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_ONOFF_GPIO_012 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_CI2CHIP_MISTRT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PPKT_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PKT0_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_DFE_MPEG_SER_MODE 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_MTSIF1_RX_DATA_6_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_TP_IN_12   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_012_PM_GPIO_012 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_011 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_ONOFF_GPIO_011 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_CHIP2CI_MOCLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_EXT_USB_HUB_CLK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_RMXP_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_DFE_MPEG_CLK 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_MTSIF1_RX_DATA_5_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_TP_IN_11   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_011_PM_GPIO_011 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_010 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_ONOFF_GPIO_010 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_CHIP2CI_MCLKO 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_RMXP_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_RMX_CLK0   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_DFE_MPEG_ERR 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_MTSIF1_RX_DATA_4_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_TP_IN_10   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_010_PM_GPIO_010 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: onoff_gpio_009 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_ONOFF_GPIO_009 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_CHIP2CI_MOVAL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_RMXP_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_RMX_VALID0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_DFE_MPEG_DATA_EN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_MTSIF1_RX_DATA_3_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_TP_IN_09   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_onoff_gpio_009_PM_GPIO_009 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_5 - Pinmux control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_024 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_ONOFF_GPIO_024 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_EBI_ADDR_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_RMXP_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_CHIP2POD_MCLKO 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_TP_IN_24   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_024_PM_GPIO_024 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_023 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_ONOFF_GPIO_023 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_CI2CHIP_MDI_7 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PPKT_DATA7 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PKT1_VALID 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_DFE_GPIO_7 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_TP_IN_23   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_023_PM_GPIO_023 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_022 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_ONOFF_GPIO_022 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_CI2CHIP_MDI_6 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PPKT_DATA6 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PKT1_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_DFE_GPIO_6 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_TP_IN_22   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_022_PM_GPIO_022 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_021 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_ONOFF_GPIO_021 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_CI2CHIP_MDI_5 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PPKT_DATA5 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PKT1_SYNC  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_DFE_GPIO_5 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_TP_IN_21   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_021_PM_GPIO_021 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_020 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_ONOFF_GPIO_020 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_CI2CHIP_MDI_4 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PPKT_DATA4 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PKT0_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PKT3_SYNC  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_DFE_GPIO_4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_TP_IN_20   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_020_PM_GPIO_020 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_019 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_ONOFF_GPIO_019 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_CI2CHIP_MDI_3 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PPKT_DATA3 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PKT1_ERROR 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PKT3_DATA  4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_DFE_GPIO_3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_TP_IN_19   6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_019_PM_GPIO_019 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_018 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_ONOFF_GPIO_018 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_CI2CHIP_MDI_2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PPKT_DATA2 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PKT3_CLK   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_DFE_GPIO_2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_TP_IN_18   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_018_PM_GPIO_018 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: onoff_gpio_017 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_ONOFF_GPIO_017 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_CI2CHIP_MDI_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PPKT_DATA1 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PKT1_DATA  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_DFE_GPIO_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_TP_IN_17   5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_onoff_gpio_017_PM_GPIO_017 6
+
+/***************************************************************************
+ *PIN_MUX_CTRL_6 - Pinmux control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_032 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_ONOFF_GPIO_032 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_EBI_ADDR_8 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_SC1_IO     2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_MTSIF1_RX_DATA_3 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_AUD_FS_CLK0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_032_PM_GPIO_032 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_031 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_ONOFF_GPIO_031 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_EBI_ADDR_7 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_SC1_RST    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_MTSIF1_RX_DATA_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_UART_CTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_031_PM_GPIO_031 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_030 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_ONOFF_GPIO_030 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_EBI_ADDR_6 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_SC1_CLK    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_MTSIF1_RX_DATA_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_UART_TXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_030_PM_GPIO_030 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_029 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_ONOFF_GPIO_029 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_EBI_ADDR_5 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_SC1_VCC    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_MTSIF1_RX_DATA_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_UART_RTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_029_PM_GPIO_029 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_028 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_ONOFF_GPIO_028 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_EBI_ADDR_4 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_CHIP2POD_SCTL0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_MTSIF1_ATS_RESET_ALT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_TP_IN_28   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_028_PM_GPIO_028 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_027 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_ONOFF_GPIO_027 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_EBI_ADDR_3 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_CHIP2POD_SDO0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_MTSIF1_ATS_INC_ALT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_TP_IN_27   4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_027_PM_GPIO_027 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_026 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_ONOFF_GPIO_026 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_EBI_ADDR_2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_POD2CHIP_SDI0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_TP_IN_26   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_026_PM_GPIO_026 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: onoff_gpio_025 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_ONOFF_GPIO_025 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_EBI_ADDR_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_CHIP2POD_SCLK0 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_TP_IN_25   3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_onoff_gpio_025_PM_GPIO_025 4
+
+/***************************************************************************
+ *PIN_MUX_CTRL_7 - Pinmux control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_040 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_ONOFF_GPIO_040 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_EBI_WAITB  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_TSIO_VCTRL 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_MTSIF1_ATS_RESET 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_040_PM_GPIO_040 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_039 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_ONOFF_GPIO_039 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_EBI_RWB    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_I2S_LR0_IN 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_MTSIF1_ATS_INC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_039_PM_GPIO_039 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_038 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_ONOFF_GPIO_038 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_EBI_ADDR_14 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_I2S_CLK0_IN 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_MTSIF1_RX_SYNC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_038_PM_GPIO_038 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_037 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_ONOFF_GPIO_037 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_EBI_ADDR_13 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_I2S_DATA0_IN 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_MTSIF1_RX_CLK 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_037_PM_GPIO_037 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_036 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_ONOFF_GPIO_036 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_EBI_ADDR_12 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_SC1_VPP    2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_MTSIF1_RX_DATA_7 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_I2S_LR0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_036_PM_GPIO_036 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_035 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_ONOFF_GPIO_035 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_EBI_ADDR_11 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_SC1_AUX2   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_MTSIF1_RX_DATA_6 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_I2S_DATA0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_035_PM_GPIO_035 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_034 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_ONOFF_GPIO_034 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_EBI_ADDR_10 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_SC1_AUX1   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_MTSIF1_RX_DATA_5 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_I2S_CLK0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_034_PM_GPIO_034 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: onoff_gpio_033 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_ONOFF_GPIO_033 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_EBI_ADDR_9 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_SC1_PRES   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_MTSIF1_RX_DATA_4 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_UART_RXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_onoff_gpio_033_PM_GPIO_033 5
+
+/***************************************************************************
+ *PIN_MUX_CTRL_8 - Pinmux control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_048 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_ONOFF_GPIO_048 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_EBI_DATA13 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_048_PM_GPIO_048 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_047 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_ONOFF_GPIO_047 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_EBI_DATA12 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_047_PM_GPIO_047 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_046 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_ONOFF_GPIO_046 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_EBI_DATA11 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_046_PM_GPIO_046 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_045 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_ONOFF_GPIO_045 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_EBI_DATA10 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_045_PM_GPIO_045 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_044 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_ONOFF_GPIO_044 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_EBI_DATA9  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_044_PM_GPIO_044 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_043 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_ONOFF_GPIO_043 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_EBI_DATA8  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_043_PM_GPIO_043 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_gpio_042 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_ONOFF_GPIO_042 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_EBI_WE1B   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_gpio_042_PM_GPIO_042 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: onoff_rsvd_gpio_041 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_MASK  0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_ONOFF_RSVD_GPIO_041 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_onoff_rsvd_gpio_041_PM_GPIO_041 1
+
+/***************************************************************************
+ *PIN_MUX_CTRL_9 - Pinmux control register 9
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_087 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_MASK       0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_ONOFF_GPIO_087 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_SC0_AUX1   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_PKT3_CLK_ALT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_I2S_CLK0_OUT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_I2S_CLK0_IN 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_CPU_TRACE_DATA13 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_087_TP_IN_03   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_086 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_MASK       0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_ONOFF_GPIO_086 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SC0_VCC    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_PKT2_VALID 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_SPI_M_MOSI 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_UART_RXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_CPU_TRACE_DATA8 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_ALT_TP_IN_01 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_086_PM_GPIO_086 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_085 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_MASK       0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_DEFAULT    0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_ONOFF_GPIO_085 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SC0_PRES   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_PKT2_ERROR 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_SPI_M_SS1B 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_AUD_FS_CLK0 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_CPU_TRACE_DATA12 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_085_TP_IN_02   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_084 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_MASK       0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SHIFT      16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_DEFAULT    0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_ONOFF_GPIO_084 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SC0_RST    1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_PKT2_SYNC  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_SPI_M_SS0B 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_UART_CTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_CPU_TRACE_DATA10 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_084_TP_IN_01   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_083 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_MASK       0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_DEFAULT    0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_ONOFF_GPIO_083 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SC0_CLK_OUT 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_PKT2_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_SPI_M_SCK  3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_UART_TXD_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_CPU_TRACE_DATA9 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_083_ALT_TP_OUT_01 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_082 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_MASK       0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SHIFT      8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_DEFAULT    0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_ONOFF_GPIO_082 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SC0_IO     1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_PKT2_CLK   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_SPI_M_MISO 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_UART_RTS_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_CPU_TRACE_DATA11 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_082_TP_IN_00   6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_050 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_MASK       0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_ONOFF_GPIO_050 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_EBI_DATA15 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_050_PM_GPIO_050 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: onoff_gpio_049 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_MASK       0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_SHIFT      0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_DEFAULT    0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_ONOFF_GPIO_049 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_EBI_DATA14 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_onoff_gpio_049_PM_GPIO_049 2
+
+/***************************************************************************
+ *PIN_MUX_CTRL_10 - Pinmux control register 10
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_099 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_ONOFF_GPIO_099 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MII_RXDV_RGMII_RXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_VO_656_1  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_MTSIF0_RX_DATA_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_SD_CARD0_CMD 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_CPU_TRACE_DATA0 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_TP_OUT_16 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_099_PM_GPIO_099 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_098 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_ONOFF_GPIO_098 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_RGMII_RX_CLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_VO_656_0  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_EXT_SC_CLK 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_MTSIF0_RX_CLK 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_SD_CARD0_CLK_IN 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_CPU_TRACE_CLK 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_TP_OUT_15 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_098_PM_GPIO_098 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_097 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_MASK 0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_ONOFF_RSVD_GPIO_097 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_SC1_VPP 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_097_PM_GPIO_097 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_096 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_MASK 0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_ONOFF_RSVD_GPIO_096 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_SC1_AUX2 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_096_PM_GPIO_096 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_095 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_MASK 0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_ONOFF_RSVD_GPIO_095 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_SC1_AUX1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_095_PM_GPIO_095 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_rsvd_gpio_094 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_MASK 0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_ONOFF_RSVD_GPIO_094 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_SC1_VCC 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_rsvd_gpio_094_PM_GPIO_094 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_089 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_DEFAULT   0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_ONOFF_GPIO_089 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_SC0_VPP   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_RGMII_RX_OK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_PKT3_SYNC_ALT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_I2S_LR0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_I2S_LR0_IN 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_CPU_TRACE_DATA15 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_089_TP_IN_31  7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: onoff_gpio_088 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_ONOFF_GPIO_088 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_SC0_AUX2  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_RGMII_START_STOP 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_PKT3_DATA_ALT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_I2S_DATA0_OUT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_I2S_DATA0_IN 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_CPU_TRACE_DATA14 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_onoff_gpio_088_TP_IN_04  7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_11 - Pinmux control register 11
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_107 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_ONOFF_GPIO_107 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_RGMII_TXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_TTX_REQ   2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_UART_CTS_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_MTSIF0_RX_DATA_7 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_USB1_PWRON_SEC_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_TP_OUT_24 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_107_PM_GPIO_107 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_106 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_ONOFF_GPIO_106 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_RGMII_TXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_VO_656_CLK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_UART_RTS_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_USB0_PWRFLT_SEC_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_CPU_TRACE_DATA7 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_TP_OUT_23 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_106_PM_GPIO_106 7
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_105 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_ONOFF_GPIO_105 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MII_TXEN_RGMII_TXCTL 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_VO_656_7  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_UART_RTS_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_MTSIF0_RX_DATA_4 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_USB0_PWRON_SEC_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_CPU_TRACE_DATA6 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_TP_OUT_22 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_105_PM_GPIO_105 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_104 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_ONOFF_GPIO_104 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_RGMII_TX_CLK 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_VO_656_6  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_UART_CTS_1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_MTSIF0_RX_DATA_3 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_SD_CARD0_DAT3 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_CPU_TRACE_DATA5 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_TP_OUT_21 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_104_PM_GPIO_104 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_103 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_ONOFF_GPIO_103 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_RGMII_RXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_VO_656_5  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_UART_CTS_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_MTSIF0_RX_SYNC 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_SD_CARD0_CLK 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_CPU_TRACE_DATA1 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_TP_OUT_20 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_103_PM_GPIO_103 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_102 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_ONOFF_GPIO_102 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_RGMII_RXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_VO_656_4  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_UART_RTS_0 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_MTSIF0_RX_DATA_1 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_SD_CARD0_DAT0 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_CPU_TRACE_DATA2 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_TP_OUT_19 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_102_PM_GPIO_102 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_101 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_ONOFF_GPIO_101 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_RGMII_RXD_02 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_VO_656_3  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_SD_CARD0_DAT1 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_CPU_TRACE_DATA3 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_TP_OUT_18 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_101_PM_GPIO_101 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: onoff_gpio_100 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_ONOFF_GPIO_100 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_RGMII_RXD_03 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_VO_656_2  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_MTSIF0_RX_DATA_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_SD_CARD0_DAT2 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_CPU_TRACE_DATA4 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_TP_OUT_17 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_onoff_gpio_100_PM_GPIO_100 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_12 - Pinmux control register 12
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_115 [31:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MASK      0xf0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SHIFT     28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_ONOFF_GPIO_115 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MII_COL   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SPI_M_SS1B 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_MTSIF0_ATS_RESET 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_RMX_PAUSE0_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_SDS_BERT_DATA 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_PKT2_VALID_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_TP_OUT_28 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_115_PM_GPIO_115 8
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_114 [27:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MASK      0x0f000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_ONOFF_GPIO_114 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MII_CRS   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SPI_M_MISO 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_MTSIF0_ATS_INC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_RMX_VALID0_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_SDS_BERT_CLK 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_PKT2_ERROR_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_UART_RXD_2 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_ALT_TP_IN_02 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_114_PM_GPIO_114 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_113 [23:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_MASK      0x00f00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SHIFT     20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_ONOFF_GPIO_113 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_MII_TX_ERR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SPI_M_SS0B 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_I2S_DATA0_OUT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_RMX_DATA0_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_SD_CARD0_PWR0 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_PKT2_DATA_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_UART_RTS_2 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_TP_OUT_27 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_113_PM_GPIO_113 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_112 [19:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_MASK      0x000f0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_ONOFF_GPIO_112 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_MII_RX_ERR 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SPI_M_MOSI 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_I2S_CLK0_OUT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_RMX_CLK0_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_SD_CARD0_WPROT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_PKT2_CLK_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_UART_TXD_2 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_ALT_TP_OUT_02 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_112_PM_GPIO_112 9
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_111 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_ONOFF_GPIO_111 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MII_MDC   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SPI_S_SS0B 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_MTSIF0_ATS_RESET 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_SD_CARD0_LED 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_VEC_VSYNC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_111_PM_GPIO_111 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_110 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_ONOFF_GPIO_110 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MII_MDIO  1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SPI_S_MISO 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_MTSIF0_ATS_INC 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_SD_CARD0_PRES 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_VEC_HSYNC 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_110_PM_GPIO_110 6
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_109 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_ONOFF_GPIO_109 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_RGMII_TXD_00 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_UART_RXD_2 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_MTSIF0_RX_DATA_5 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_ALT_TP_IN_03 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_109_PM_GPIO_109 5
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: onoff_gpio_108 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_ONOFF_GPIO_108 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_RGMII_TXD_01 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_TTX_DATA  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_UART_TXD_2 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_MTSIF0_RX_DATA_6 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_USB1_PWRFLT_SEC_ALT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_ALT_TP_OUT_03 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_onoff_gpio_108_PM_GPIO_108 7
+
+/***************************************************************************
+ *PIN_MUX_CTRL_13 - Pinmux control register 13
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_MASK           0xffff0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_SHIFT          16
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_124 [15:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_MASK      0x0000f000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_ONOFF_GPIO_124 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_UART_RTS_1 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_124_PM_GPIO_124 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_118 [11:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_MASK      0x00000f00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_SHIFT     8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_ONOFF_GPIO_118 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_UART_TXD_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_TEST_THP  2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_ALT_TP_OUT_00 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_118_PM_GPIO_118 4
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_117 [07:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_MASK      0x000000f0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_SHIFT     4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_ONOFF_GPIO_117 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_UART_RXD_0 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_ALT_TP_IN_00 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_117_PM_GPIO_117 3
+
+/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: onoff_gpio_116 [03:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_MASK      0x0000000f
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_DEFAULT   0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_ONOFF_GPIO_116 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_MII_IRQ   1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SPI_M_SCK 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_I2S_LR0_OUT 3
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_RMX_SYNC0_ALT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_SD_CARD0_VOLT 5
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_PKT2_SYNC_ALT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_UART_CTS_2 7
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_TP_OUT_29 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_onoff_gpio_116_PM_GPIO_116 9
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_data_1_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_1_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_data_0_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_data_0_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_dsb_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_dsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_tsb_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_tsb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_rdb_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_rdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_we0b_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_we0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_nand_rbb_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_nand_rbb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs2b_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs2b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs1b_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs1b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: onoff_ebi_cs0b_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_onoff_ebi_cs0b_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [09:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x000003ff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_wpb_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_holdb_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_holdb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_mosi_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_mosi_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_miso_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_miso_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_sf_sck_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_sf_sck_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_emmc_clk_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_clk_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_emmc_cmd_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_emmc_cmd_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_nand_dqs_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_dqs_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_nand_wpb_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_nand_wpb_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_7_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_7_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_6_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_6_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_5_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_5_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_4_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_4_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_3_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_3_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: onoff_ebi_data_2_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_onoff_ebi_data_2_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_003_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_003_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_002_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_002_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_001_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_001_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: onoff_gpio_000_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_onoff_gpio_000_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [21:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x003fffff
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_018_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_018_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_017_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_017_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_016_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_016_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_015_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_015_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_014_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_014_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_013_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_013_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_012_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_012_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_011_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_011_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_010_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_010_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_009_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_009_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_008_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_008_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_007_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_007_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_006_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_006_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_005_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_005_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: onoff_gpio_004_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_onoff_gpio_004_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_033_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_033_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_032_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_032_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_031_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_031_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_030_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_030_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_029_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_029_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_028_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_028_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_027_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_027_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_026_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_026_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_025_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_025_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_024_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_024_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_023_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_023_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_022_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_022_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_021_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_021_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_020_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_020_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: onoff_gpio_019_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_onoff_gpio_019_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_048_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_048_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_047_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_047_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_046_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_046_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_045_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_045_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_044_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_044_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_043_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_043_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_042_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_042_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_040_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_040_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_039_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_039_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_038_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_038_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_037_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_037_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_036_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_036_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_035_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_035_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: onoff_gpio_034_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_onoff_gpio_034_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_098_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_098_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved0 [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_MASK        0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_SHIFT       26
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_096_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_096_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_095_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_095_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_rsvd_gpio_094_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_rsvd_gpio_094_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved1 [19:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_MASK        0x000fc000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_SHIFT       14
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_086_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_086_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved2 [11:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved2_MASK        0x00000ff0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved2_SHIFT       4
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_050_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_050_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: onoff_gpio_049_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_onoff_gpio_049_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_113_pad_ctrl [29:28] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_MASK 0x30000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_113_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_112_pad_ctrl [27:26] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_MASK 0x0c000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_112_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_111_pad_ctrl [25:24] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_MASK 0x03000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_111_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_110_pad_ctrl [23:22] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_MASK 0x00c00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_110_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_109_pad_ctrl [21:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_MASK 0x00300000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_109_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_108_pad_ctrl [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_108_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_107_pad_ctrl [17:16] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_MASK 0x00030000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_107_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_106_pad_ctrl [15:14] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_MASK 0x0000c000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_106_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_105_pad_ctrl [13:12] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_MASK 0x00003000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_105_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_104_pad_ctrl [11:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_MASK 0x00000c00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_104_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_103_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_103_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_102_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_102_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_101_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_101_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_100_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_100_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: onoff_gpio_099_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_onoff_gpio_099_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:20] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK        0xfff00000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT       20
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [19:18] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x000c0000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [17:10] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK        0x0003fc00
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT       10
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_118_pad_ctrl [09:08] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_MASK 0x00000300
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_118_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_117_pad_ctrl [07:06] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_MASK 0x000000c0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_117_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_116_pad_ctrl [05:04] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_MASK 0x00000030
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_116_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_115_pad_ctrl [03:02] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_MASK 0x0000000c
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_115_pad_ctrl_PULL_UP 2
+
+/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: onoff_gpio_114_pad_ctrl [01:00] */
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_NONE 0
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_DOWN 1
+#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_onoff_gpio_114_pad_ctrl_PULL_UP 2
+
+/***************************************************************************
+ *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xffffff00
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       8
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_ir_in0 [07:07] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_ir_in0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_fp_4sec_resetb [06:06] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_fp_4sec_resetb_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_gpio_108 [05:05] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_gpio_108_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_clk_out1 [04:04] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_clk_out0 [03:03] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_clk_out0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_emmc_clk [02:02] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_clk_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_emmc_cmd [01:01] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_emmc_cmd_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_onoff_usb0_pwron [00:00] */
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_onoff_usb0_pwron_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_CTRL - Reset control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0xfffffffe
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               1
+
+/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT   0x00000000
+
+/***************************************************************************
+ *RESET_SOURCE_ENABLE - Reset source enable
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK       0xfffffc00
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT      10
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_MASTER_RESET - Software master reset
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK           0xfffffffe
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT          1
+
+/* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000
+
+/***************************************************************************
+ *HW_RESET_EXTENSION - Hardware reset extension
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK        0xf0000000
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT       28
+
+/* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000
+
+/***************************************************************************
+ *RESET_MONITOR - Reset Monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK             0xffffff00
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT            8
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT  7
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT   6
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT   4
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0
+
+/***************************************************************************
+ *RESET_HISTORY - Reset history
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:21] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xffe00000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            21
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: mpm_reset [20:20] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_MASK             0x00100000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_mpm_reset_SHIFT            20
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 19
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 18
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 17
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 16
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK  0x00008000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK  0x00004000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK  0x00002000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK   0x00001000
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT  12
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT       11
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT     10
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK       0x00000200
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT      9
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1
+
+/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0
+
+/***************************************************************************
+ *SW_INIT_0_SET - Software init 0 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK           0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT          31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK   0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT  30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_MASK   0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_SHIFT  29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK          0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT         28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK        0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT       27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK        0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT       26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK   0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK          0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT         24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK   0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT  22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK          0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT         21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK   0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK           0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT          18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK   0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT  17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK        0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT       16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK           0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT          15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK           0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT          14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK          0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT         12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK        0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT       11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK        0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT       10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK           0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT          9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK           0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT          8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK           0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT          6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK    0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT   4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK    0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT   3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK           0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT          1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK      0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT     0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT   0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_CLEAR - Software init 0 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK         0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT        31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK        0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT       28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK      0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT     27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK      0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT     26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK        0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT       21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK      0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT     16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK         0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT        15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK         0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT        14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK      0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT     11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK      0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT     10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK         0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT        9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK         0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT        8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK  0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK         0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT        6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK  0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK  0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK     0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT    2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK         0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT        1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK    0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SW_INIT_0_STATUS - Software init 0 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK        0x80000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT       31
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_29_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK       0x10000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT      28
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK     0x08000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT    27
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK     0x04000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT    26
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK       0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT      24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK        0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT       18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK        0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT       15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK        0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT       14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK       0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT      12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK     0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT    11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK     0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK        0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT       9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK        0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT       8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK        0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT       6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK    0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT   2
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK        0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT       1
+
+/* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK   0x80000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT  31
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK  0x10000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK  0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK  0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK   0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT  18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK   0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT  15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT  14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK  0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK   0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT  9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT  8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT  6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK   0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT  1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_29_SHIFT 29
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_1_SET - Software init 1 set
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK             0xfc000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT            26
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK        0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT       25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK        0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT       24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK     0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT    23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_MASK       0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_SHIFT      22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_rcvr_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_MASK       0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_SHIFT      21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_t2_bicm_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_MASK       0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_SHIFT      20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ufe_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK         0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT        19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK         0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT        18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_MASK       0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_SHIFT      17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_mpm_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK     0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT    16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK       0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT      15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_MASK      0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_SHIFT     14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_MASK      0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_SHIFT     13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_dfe_core_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_MASK        0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_SHIFT       12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_MASK  0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_MASK     0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_SHIFT    8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_MASK      0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_SHIFT     7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_MASK      0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_SHIFT     6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_MASK       0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_SHIFT      5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_MASK          0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_SHIFT         4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_MASK           0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_SHIFT          3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vip_sw_init_DEFAULT        0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK          0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT         2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK       0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT      1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK           0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT          0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT        0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_CLEAR - Software init 1 clear
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK           0xfc000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT          26
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK      0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT     25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK      0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT     24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK   0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT  23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_MASK     0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_SHIFT    22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_rcvr_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_MASK     0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_SHIFT    21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_t2_bicm_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_MASK     0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_SHIFT    20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ufe_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK       0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT      19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK       0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT      18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT    0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_MASK     0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_SHIFT    17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_mpm_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK   0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT  16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK     0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT    15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_MASK    0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_SHIFT   14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_MASK    0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_SHIFT   13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_dfe_core_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_MASK      0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_SHIFT     12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_MASK   0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_SHIFT  8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_MASK    0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_SHIFT   7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_MASK    0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_SHIFT   6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_MASK     0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_SHIFT    5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_MASK        0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_SHIFT       4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_MASK         0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_SHIFT        3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vip_sw_init_DEFAULT      0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK        0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT       2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT     0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK     0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT    1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK         0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT        0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT      0x00000000
+
+/***************************************************************************
+ *SW_INIT_1_STATUS - Software init 1 status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK          0xfc000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT         26
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK     0x02000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT    25
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK     0x01000000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT    24
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK  0x00800000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_MASK    0x00400000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_rcvr_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_MASK    0x00200000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_SHIFT   21
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_t2_bicm_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_MASK    0x00100000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ufe_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK      0x00080000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT     19
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT   0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK      0x00040000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT     18
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT   0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_MASK    0x00020000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK  0x00010000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK    0x00008000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_MASK   0x00004000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_SHIFT  14
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_MASK   0x00002000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_SHIFT  13
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_dfe_core_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_MASK     0x00001000
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_SHIFT    12
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top_sw_init_DEFAULT  0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_MASK  0x00000100
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_MASK   0x00000080
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_SHIFT  7
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_MASK   0x00000040
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_SHIFT  6
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_MASK    0x00000020
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_MASK       0x00000010
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_SHIFT      4
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_MASK        0x00000008
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_SHIFT       3
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vip_sw_init_DEFAULT     0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK       0x00000004
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT      2
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT    0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK    0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT   1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK     0xfc000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT    26
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_MASK  0x00000010
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_MASK   0x00000008
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vip_sw_init_SHIFT  3
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK  0x00000004
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK   0x00000001
+#define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT  0
+
+/***************************************************************************
+ *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xfc000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 26
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK   0xfc000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT  26
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 25
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 24
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 23
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_rcvr_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_rcvr_sw_init_SHIFT 22
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_bicm_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_t2_bicm_sw_init_SHIFT 21
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ufe_top_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ufe_top_sw_init_SHIFT 20
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 19
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 18
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_mpm_top_sw_init_SHIFT 17
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 16
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 15
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 14
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dfe_core_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_dfe_core_sw_init_SHIFT 13
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top_sw_init_SHIFT 12
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 11
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 10
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 9
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 8
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top_sw_init_SHIFT 7
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top_sw_init_SHIFT 6
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 5
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 4
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vip_sw_init_SHIFT 3
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 2
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 1
+
+/* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0
+
+/***************************************************************************
+ *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK  0xfffffffc
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xfc000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 26
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_rcvr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_t2_bicm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ufe_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_dfe_core_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK  0xf0000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_29_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:26] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xfc000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 26
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [25:25] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [24:24] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [23:23] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: t2_rcvr_sw_init [22:22] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_rcvr_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: t2_bicm_sw_init [21:21] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_t2_bicm_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ufe_top_sw_init [20:20] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ufe_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [19:19] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [18:18] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: mpm_top_sw_init [17:17] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_mpm_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [16:16] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [15:15] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hdmi_aon_sw_init [14:14] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: dfe_core_sw_init [13:13] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_dfe_core_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ds_top_sw_init [12:12] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: stb_chan_top_sw_init [11:11] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [10:10] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [09:09] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec0_sw_init [08:08] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top_sw_init [07:07] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top_sw_init [06:06] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: fsk_top_sw_init [05:05] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: leap_sw_init [04:04] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vip_sw_init [03:03] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vip_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [02:02] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [01:01] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UNCLEARED_SCRATCH - Scratch register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SPARE_CTRL - Spare control bits reserved for future use
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT         0x00000001
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0
+#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT         0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTRL - Test port control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0  0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP  1
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UFE_TOP 2
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_T2_BICM 3
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_T2_RCVR 4
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MPM_TOP 9
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 10
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DFE_CORE 11
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_MDAC_CAL_TOP 12
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP 13
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_STB_CHAN_TOP 15
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS     16
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     17
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON     18
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     19
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVS     20
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     21
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     22
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     23
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0    25
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0  28
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     30
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   31
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1  34
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0    38
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    40
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 41
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     42
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FSK_TOP 43
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  44
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  45
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R  46
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T  47
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC 60
+
+/***************************************************************************
+ *TEST_PORT_OUT_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_OUT_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_PORT_IN_PEEK - Testport peek register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0
+
+/***************************************************************************
+ *TEST_PORT_IN_POKE - Testport poke register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000
+
+/***************************************************************************
+ *EJTAG_INPUT_EN - EJTAG input bus enables
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:10] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffc00
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           10
+
+/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [09:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x000003ff
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_LEAP_CPU_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MPM_CPU_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 512
+
+/***************************************************************************
+ *EJTAG_OUTPUT_SEL - EJTAG output select
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         4
+
+/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x0000000f
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 4
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_LEAP_CPU 5
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 6
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MPM_CPU 7
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 8
+#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 9
+
+/***************************************************************************
+ *VTRAP_CTRL - VTRAP Control
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK                0xff800000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT               23
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000
+
+/***************************************************************************
+ *VTRAP_STATUS - VTRAP Status
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK              0xffffffe0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT             5
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000
+
+/***************************************************************************
+ *UART_ROUTER_SEL_0 - UART Router select 0
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK    0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT   25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK    0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT   20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU    8
+
+/***************************************************************************
+ *UART_ROUTER_SEL_1 - UART Router select 1
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK         0xc0000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT        30
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK   0x3e000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT  25
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID    4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_LEAP   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU   8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK   0x01f00000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT  20
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID    4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_LEAP   6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU   8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK    0x000f8000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT   15
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK    0x00007c00
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT   10
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK    0x000003e0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT   5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU    8
+
+/* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK    0x0000001f
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT   0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU  0
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID     4
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 5
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_LEAP    6
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 7
+#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU    8
+
+/***************************************************************************
+ *SSP_CONFIG - Serial Slave Port configuration register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT        0x00000004
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT         0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT           0x00000000
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1
+
+/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT     0x00000001
+
+/***************************************************************************
+ *SERS_REV - SERS Revision Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16
+
+/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8
+#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0
+#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT     0x00000000
+
+/***************************************************************************
+ *SERS_CFG - SERS Configuration Register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT       0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT                0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1
+
+/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT           0x00000000
+
+/* union - case mapped_buffer_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000
+
+/* union - case cmd_fifo_mode [26:08] */
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT  0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT                 0x00000000
+
+/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0
+#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT            0x00000000
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404428
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32
+
+/***************************************************************************
+ *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0
+
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404448
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32
+
+/***************************************************************************
+ *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
+#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0
+
+
+/***************************************************************************
+ *RO_TEST_BLOCK_SEL - Block select for RO testmode
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xfffc0000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        18
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048
+
+/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2
+#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3
+
+/***************************************************************************
+ *TEST_CONFIGURATION - Test configuration
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK        0xfffffff0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT       4
+
+/* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_TEST_2 - OTP option test register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_16 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_15 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_14 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_13 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_12 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_11 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_10 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_9 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_8 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_7 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_6 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_5 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_3 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_2 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_reserved_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_SHIFT 14
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_reserved_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_audio_2_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_SHIFT 13
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_audio_2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_flash_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_SHIFT 12
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_flash_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_mpm_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_SHIFT 11
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_mpm_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_mhl_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_SHIFT 10
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_mhl_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_gphy_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_SHIFT 9
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_gphy_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_hevc_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_SHIFT 8
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_hevc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbt2_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_SHIFT 7
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbt_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_SHIFT 6
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_isdbt_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_SHIFT 5
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_isdbt_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dfe_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_SHIFT 4
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dfe_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbc2_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_SHIFT 3
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc2_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_dvbc_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_SHIFT 2
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_dvbc_disable_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_sds_channel_disable [01:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *OTP_OPTION_STATUS_2 - OTP option status register
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_16 [31:31] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_MASK 0x80000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_SHIFT 31
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_15 [30:30] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_MASK 0x40000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_SHIFT 30
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_14 [29:29] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_MASK 0x20000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_SHIFT 29
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_13 [28:28] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_MASK 0x10000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_SHIFT 28
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_12 [27:27] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_MASK 0x08000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_SHIFT 27
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_11 [26:26] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_MASK 0x04000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_SHIFT 26
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_10 [25:25] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_MASK 0x02000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_SHIFT 25
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_9 [24:24] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_MASK 0x01000000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_SHIFT 24
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_8 [23:23] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_MASK 0x00800000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_SHIFT 23
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_7 [22:22] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_MASK 0x00400000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_SHIFT 22
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_6 [21:21] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_MASK 0x00200000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_SHIFT 21
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_5 [20:20] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_MASK 0x00100000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_SHIFT 20
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_4 [19:19] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_MASK 0x00080000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_SHIFT 19
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_3 [18:18] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_MASK 0x00040000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_SHIFT 18
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_2 [17:17] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_MASK 0x00020000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_SHIFT 17
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_1 [16:16] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_MASK 0x00010000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_SHIFT 16
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_0 [15:15] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_MASK 0x00008000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_SHIFT 15
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_DEFAULT 0x00000000
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_reserved_8 [14:14] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_8_MASK 0x00004000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_reserved_8_SHIFT 14
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_audio_2_disable [13:13] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_MASK 0x00002000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_audio_2_disable_SHIFT 13
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_flash_disable [12:12] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_MASK 0x00001000
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_flash_disable_SHIFT 12
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_mpm_disable [11:11] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_MASK 0x00000800
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_mpm_disable_SHIFT 11
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_mhl_disable [10:10] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_MASK 0x00000400
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_mhl_disable_SHIFT 10
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_gphy_disable [09:09] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_MASK 0x00000200
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_gphy_disable_SHIFT 9
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_hevc_disable [08:08] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_MASK 0x00000100
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_hevc_disable_SHIFT 8
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbt2_disable [07:07] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt2_disable_MASK 0x00000080
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt2_disable_SHIFT 7
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbt_disable [06:06] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt_disable_MASK 0x00000040
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbt_disable_SHIFT 6
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_isdbt_disable [05:05] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_isdbt_disable_MASK 0x00000020
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_isdbt_disable_SHIFT 5
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dfe_disable [04:04] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dfe_disable_MASK 0x00000010
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dfe_disable_SHIFT 4
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbc2_disable [03:03] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc2_disable_MASK 0x00000008
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc2_disable_SHIFT 3
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_dvbc_disable [02:02] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc_disable_MASK 0x00000004
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_dvbc_disable_SHIFT 2
+
+/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_sds_channel_disable [01:00] */
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_MASK 0x00000003
+#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_SHIFT 0
+
+/***************************************************************************
+ *GENERAL_CTRL_6 - General control register 6
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK            0xfffffffe
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT           1
+
+/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000000
+
+/***************************************************************************
+ *GENERAL_CTRL_7 - General control register 7
+ ***************************************************************************/
+/* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0
+#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000
+
+#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_usb_ctrl.h b/include/linux/brcmstb/7364a0/bchp_usb_ctrl.h
new file mode 100644
index 000000000000..80696fc4d88d
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_usb_ctrl.h
@@ -0,0 +1,1544 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:42 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_USB_CTRL_H__
+#define BCHP_USB_CTRL_H__
+
+/***************************************************************************
+ *USB_CTRL - USB Control Registers
+ ***************************************************************************/
+#define BCHP_USB_CTRL_SETUP                      0x00480200 /* Setup Register */
+#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* PLL Control Register */
+#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* Frame Adjust Value */
+#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* Control Register for EHCI Bridge */
+#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* Control Register for OHCI Bridge */
+#define BCHP_USB_CTRL_MDIO                       0x00480214 /* MDIO Interface Programming Register */
+#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* MDIO Interface Read Register */
+#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* Test Port Control Register */
+#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* Simulation Register */
+#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* Throutput Test Control */
+#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* Throughput Test Monitor */
+#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* UTMI Control Register */
+#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* UTMI Control 2 Register */
+#define BCHP_USB_CTRL_USB_PM                     0x00480234 /* Power Management Register */
+#define BCHP_USB_CTRL_USB_PM_STATUS              0x00480238 /* usb20 Power Management Status Register */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT              0x0048023c /* OHCI ADDRESS Extension */
+#define BCHP_USB_CTRL_PLL_LDO_CTL                0x00480240 /* 28NM USBPHY LDO Control */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS            0x00480244 /* 28NM USBPHY PLLBIAS Control */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL            0x00480248 /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_AFE_USBIO_TST              0x0048024c /* 28NM USBPHY AFE Bandgap Control */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC              0x00480250 /* PLL Feedback Divider Control Register */
+#define BCHP_USB_CTRL_TP_DIAG                    0x00480254 /* diagnostic for tp bus */
+#define BCHP_USB_CTRL_SPARE3                     0x00480258 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE4                     0x0048025c /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_USB30_CTL1                 0x00480260 /* USB30 CONTROL Register 1 */
+#define BCHP_USB_CTRL_USB30_CTL2                 0x00480264 /* USB30 CONTROL Register 2 */
+#define BCHP_USB_CTRL_USB30_CTL3                 0x00480268 /* USB30 CONTROL Register 3 */
+#define BCHP_USB_CTRL_USB30_CTL4                 0x0048026c /* USB30 CONTROL Register 4 */
+#define BCHP_USB_CTRL_USB30_PCTL                 0x00480270 /* USB30 PORT CONTROL Register */
+#define BCHP_USB_CTRL_USB30_CTL5                 0x00480274 /* USB30 CONTROL Register 5 */
+#define BCHP_USB_CTRL_SPARE5                     0x00480278 /* Spare1 Register for future use */
+#define BCHP_USB_CTRL_SPARE6                     0x0048027c /* Spare2 Register for future use */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE            0x004802a0 /* SCB0 base start and end address */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE            0x004802a4 /* SCB1 base start and end address */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE            0x004802a8 /* SCB2 base start and end address */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE            0x004802ac /* SCB0 extn start and end address */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE            0x004802b0 /* SCB1 extn start and end address */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE            0x004802b4 /* SCB2 extn start and end address */
+#define BCHP_USB_CTRL_USB_REVID                  0x004802fc /* USB REVID */
+
+/***************************************************************************
+ *SETUP - Setup Register
+ ***************************************************************************/
+/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK                       0xc0000000
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT                      30
+#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0x30000000
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
+#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK                   0x08000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT                  27
+#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK                     0x04000000
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT                    26
+#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: pwrflt_switch_en [25:24] */
+#define BCHP_USB_CTRL_SETUP_pwrflt_switch_en_MASK                  0x03000000
+#define BCHP_USB_CTRL_SETUP_pwrflt_switch_en_SHIFT                 24
+#define BCHP_USB_CTRL_SETUP_pwrflt_switch_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: usb3_pwron_en [23:23] */
+#define BCHP_USB_CTRL_SETUP_usb3_pwron_en_MASK                     0x00800000
+#define BCHP_USB_CTRL_SETUP_usb3_pwron_en_SHIFT                    23
+#define BCHP_USB_CTRL_SETUP_usb3_pwron_en_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: SETUP_SPARE [22:20] */
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x00700000
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      20
+#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK                    0x00080000
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT                   19
+#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                   0x00040000
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                  18
+#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK                   0x00020000
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT                  17
+#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00010000
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 16
+#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: SETUP :: scb2_en [15:15] */
+#define BCHP_USB_CTRL_SETUP_scb2_en_MASK                           0x00008000
+#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT                          15
+#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb1_en [14:14] */
+#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
+#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
+#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb0_en [13:13] */
+#define BCHP_USB_CTRL_SETUP_scb0_en_MASK                           0x00002000
+#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT                          13
+#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT                        0x00000001
+
+/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00001000
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  12
+#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000
+
+/* USB_CTRL :: SETUP :: setup_spare1 [11:11] */
+#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK                      0x00000800
+#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT                     11
+#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT                   0x00000000
+
+/* USB_CTRL :: SETUP :: usb_soft_reset_bcm6xxx [10:10] */
+#define BCHP_USB_CTRL_SETUP_usb_soft_reset_bcm6xxx_MASK            0x00000400
+#define BCHP_USB_CTRL_SETUP_usb_soft_reset_bcm6xxx_SHIFT           10
+#define BCHP_USB_CTRL_SETUP_usb_soft_reset_bcm6xxx_DEFAULT         0x00000000
+
+/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
+#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
+#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000
+
+/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
+#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: SETUP :: soft_reset [06:06] */
+#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
+#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
+#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000
+
+/* USB_CTRL :: SETUP :: IPP [05:05] */
+#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
+#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
+#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: IOC [04:04] */
+#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
+#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
+#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000
+
+/* USB_CTRL :: SETUP :: WABO [03:03] */
+#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
+#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
+#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNBO [02:02] */
+#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
+#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
+#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: FNHW [01:01] */
+#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
+#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
+#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000
+
+/* USB_CTRL :: SETUP :: BABO [00:00] */
+#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
+#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
+#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000
+
+/***************************************************************************
+ *PLL_CTL - PLL Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                  0x80000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                 31
+#define BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT               0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
+#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
+#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
+#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
+#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000004
+
+/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
+#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a
+
+/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x0000f000
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
+#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001
+
+/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
+#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000
+
+/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
+#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000020
+
+/***************************************************************************
+ *FLADJ_VALUE - Frame Adjust Value
+ ***************************************************************************/
+/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
+#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020
+
+/***************************************************************************
+ *EBRIDGE - Control Register for EHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *OBRIDGE - Control Register for OHCI Bridge
+ ***************************************************************************/
+/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
+#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
+#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
+#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:18] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffc0000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      18
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OSTOP_SCB_REQ [17:17] */
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_MASK                   0x00020000
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_SHIFT                  17
+#define BCHP_USB_CTRL_OBRIDGE_OSTOP_SCB_REQ_DEFAULT                0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
+#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002
+
+/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004
+
+/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
+#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000
+
+/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
+#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *MDIO - MDIO Interface Programming Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK                       0x80000000
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                      31
+#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                    0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0x7c000000
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
+#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000
+
+/* USB_CTRL :: MDIO :: WR_START [25:25] */
+#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
+#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
+#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: RD_START [24:24] */
+#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
+#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
+#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
+#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000
+
+/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
+#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000
+
+/***************************************************************************
+ *MDIO2 - MDIO Interface Read Register
+ ***************************************************************************/
+/* USB_CTRL :: MDIO2 :: SYNOPSYS_CORE_ID [31:16] */
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_MASK                  0xffff0000
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_SHIFT                 16
+#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_DEFAULT               0x0000298a
+
+/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
+#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *TEST_PORT_CTL - Test Port Control Register
+ ***************************************************************************/
+/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0xf0000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              28
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK          0x08000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT         27
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
+#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK               0x01800000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT              23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK            0x00600000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT           21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00100000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK                0x00080000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT               19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT             0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK            0x00040000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT           18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK            0x00020000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT           17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT         0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK                  0x00010000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                 16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT               0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK               0x0000ff00
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT              8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT            0x00000000
+
+/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0             0
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1             1
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2             2
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3             3
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4             4
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5             5
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6             6
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7             7
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8             8
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9             9
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10            10
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11            11
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12            12
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13            13
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14            14
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15            15
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16            16
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17            17
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18            18
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19            19
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20            20
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21            21
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22            22
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23            23
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24            24
+#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25            25
+
+/***************************************************************************
+ *USB_SIMCTL - Simulation Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
+#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
+#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
+#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
+#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
+#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffc00
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                10
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK              0x00000200
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT             9
+#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: ohci_memreq_disable [08:08] */
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_MASK          0x00000100
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_SHIFT         8
+#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [07:07] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK                0x00000080
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT               7
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK                  0x00000040
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT                 6
+#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT                5
+#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK                0x00000010
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT               4
+#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x0000000f
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               0
+#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000
+
+/***************************************************************************
+ *USB_TESTCTL - Throutput Test Control
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK              0x00600000
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT             21
+#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
+#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
+#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
+#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
+#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000
+
+/***************************************************************************
+ *USB_TESTMON - Throughput Test Monitor
+ ***************************************************************************/
+/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK                 0x80000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT                31
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK                 0x40000000
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT                30
+#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT                29
+#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0x1fffffff
+#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0
+
+/***************************************************************************
+ *UTMI_CTL_1 - UTMI Control Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK           0x08000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT          27
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK              0x04000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT             26
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT           0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK       0x02000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT      25
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK        0x01000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT       24
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT     0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host                  0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device                1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG                   2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10                  3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
+#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
+#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK              0x00000800
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT             11
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT           0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK                 0x00000400
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT                10
+#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT              0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK          0x00000200
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT         9
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT       0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK           0x00000100
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT          8
+#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT        0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
+#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000
+
+/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host                     0
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device                   1
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG                      2
+#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10                     3
+
+/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
+#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000
+
+/***************************************************************************
+ *UTMI_CTL_2 - UTMI Control 2 Register
+ ***************************************************************************/
+/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
+#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB_PM - Power Management Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM :: xdc_soft_resetb [31:31] */
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_MASK                  0x80000000
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_SHIFT                 31
+#define BCHP_USB_CTRL_USB_PM_xdc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_soft_resetb [30:30] */
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK                  0x40000000
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT                 30
+#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT               0x00000000
+
+/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [29:29] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK                 0x20000000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT                29
+#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [28:28] */
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK                 0x10000000
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT                28
+#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT              0x00000001
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [27:16] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK                    0x0fff0000
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT                   16
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK            0x00008000
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT           15
+#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK            0x00004000
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT           14
+#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK                     0x00003fe0
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT                    5
+#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                  0x00000000
+
+/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK                       0x00000010
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT                      4
+#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT                    0x00000000
+
+/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK                0x00000008
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT               3
+#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK                0x00000004
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT               2
+#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT             0x00000000
+
+/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK                      0x00000002
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT                     1
+#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT                   0x00000000
+
+/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK                       0x00000001
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT                      0
+#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT                    0x00000000
+
+/***************************************************************************
+ *USB_PM_STATUS - usb20 Power Management Status Register
+ ***************************************************************************/
+/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK               0xffff0000
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT              16
+#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK                 0x0000ffff
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT                0
+#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *OHCI_ADDR_EXT - OHCI ADDRESS Extension
+ ***************************************************************************/
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK           0xffffff00
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT          8
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK             0x000000ff
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT            0
+#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT          0x00000000
+
+/***************************************************************************
+ *PLL_LDO_CTL - 28NM USBPHY LDO Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK            0xffff0000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT           16
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT         0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK                0x0000f000
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT               12
+#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK                0x00000f00
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT               8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT             0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK               0x000000f8
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT              3
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT            0x00000000
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK            0x00000004
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT           2
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT         0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK             0x00000002
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT            1
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT          0x00000001
+
+/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK              0x00000001
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT             0
+#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT           0x00000001
+
+/***************************************************************************
+ *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK           0xfffc0000
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT          18
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT        0x00000000
+
+/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK    0x0003ffff
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT   0
+#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK        0xfffe0000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT       17
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT     0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK             0x0001f000
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT            12
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT          0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000
+
+/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK     0x0000000f
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT    0
+#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT  0x00000000
+
+/***************************************************************************
+ *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
+ ***************************************************************************/
+/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK           0x80000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT          31
+#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT        0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK                   0x40000000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT                  30
+#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT                0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK       0x3fff0000
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT      16
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT    0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK          0x0000ff00
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT         8
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT       0x00000000
+
+/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK          0x000000ff
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT         0
+#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT       0x00000000
+
+/***************************************************************************
+ *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
+ ***************************************************************************/
+/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK      0xfff00000
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT     20
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT   0x00000000
+
+/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK             0x000fffff
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT            0
+#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT          0x00000000
+
+/***************************************************************************
+ *TP_DIAG - diagnostic for tp bus
+ ***************************************************************************/
+/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK                    0xffffffff
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT                   0
+#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *SPARE3 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE4 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *USB30_CTL1 - USB30 CONTROL Register 1
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:23] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK            0xff800000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT           23
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: rxelectidle_sel [22:22] */
+#define BCHP_USB_CTRL_USB30_CTL1_rxelectidle_sel_MASK              0x00400000
+#define BCHP_USB_CTRL_USB30_CTL1_rxelectidle_sel_SHIFT             22
+#define BCHP_USB_CTRL_USB30_CTL1_rxelectidle_sel_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT      21
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK            0x00100000
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT           20
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK                  0x00080000
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT                 19
+#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK                   0x00040000
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT                  18
+#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT                0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK                    0x00020000
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT                   17
+#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK                  0x00010000
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT                 16
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT               0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK            0x0000ff80
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT           7
+#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK          0x00000040
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT         6
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK                 0x00000020
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT                5
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK           0x00000010
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK          0x0000000e
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT         1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT       0x00000004
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk    0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL          1
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N     2
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk   4
+
+/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK          0x00000001
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT         0
+#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT       0x00000000
+
+/***************************************************************************
+ *USB30_CTL2 - USB30 CONTROL Register 2
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK            0x3f000000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT         0x00000020
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK          0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT         16
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK          0x0000ff00
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT         8
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK            0x000000f8
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT           3
+#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK          0x00000004
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT         2
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK               0x00000003
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_CTL3 - USB30 CONTROL Register 3
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK            0xc0000000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT           30
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK     0x20000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT    29
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK        0x1f000000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT       24
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT     0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK        0x00f00000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT       20
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT     0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK           0x00080000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT          19
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK     0x00040000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT    18
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT  0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK         0x00020000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT        17
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT      0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK            0x00010000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT           16
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT         0x00000001
+
+/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK            0x0000c000
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT           14
+#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK        0x00002000
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT       13
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK           0x00001f00
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT          8
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT        0x00000009
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK           0x000000f0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT          4
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT        0x00000007
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK              0x00000008
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT             3
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT           0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK        0x00000004
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT       2
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT     0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK            0x00000002
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT           1
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK               0x00000001
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT            0x00000001
+
+/***************************************************************************
+ *USB30_CTL4 - USB30 CONTROL Register 4
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK            0xff000000
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT           24
+#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT         0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK               0x00ff0000
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT              16
+#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT            0x00000000
+
+/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK               0x0000ffff
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT              0
+#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT            0x00000000
+
+/***************************************************************************
+ *USB30_PCTL - USB30 PORT CONTROL Register
+ ***************************************************************************/
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK             0xe0000000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT            29
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK           0x10000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT          28
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT        0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK       0x00200000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT      21
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK       0x00100000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT      20
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT    0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK                 0x000c0000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT                18
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT              0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK          0x00020000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT         17
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT       0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK      0x00010000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT     16
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT   0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK           0x00008000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT          15
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT        0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK             0x00006000
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT            13
+#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT          0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK              0x00001000
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT             12
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT           0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK    0x00000100
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT   8
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK    0x00000080
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT   7
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK    0x00000040
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT   6
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK          0x00000020
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT         5
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK          0x00000010
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT         4
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT       0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK                    0x0000000c
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT                   2
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT                 0x00000000
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK             0x00000002
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT            1
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT          0x00000001
+
+/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK         0x00000001
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT        0
+#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT      0x00000000
+
+/***************************************************************************
+ *USB30_CTL5 - USB30 CONTROL Register 5
+ ***************************************************************************/
+/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK                   0xffffffff
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT                  0
+#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT                0x00000000
+
+/***************************************************************************
+ *SPARE5 - Spare1 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SPARE6 - Spare2 Register for future use
+ ***************************************************************************/
+/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK                      0xffffffff
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT                     0
+#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT                   0x00000000
+
+/***************************************************************************
+ *SCB0_BASE_RANGE - SCB0 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT   0x00000007
+
+/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SCB1_BASE_RANGE - SCB1 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB2_BASE_RANGE - SCB2 base start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT   0x0000000b
+
+/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x00000008
+
+/***************************************************************************
+ *SCB0_EXTN_RANGE - SCB0 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT   0x00000017
+
+/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010
+
+/***************************************************************************
+ *SCB1_EXTN_RANGE - SCB1 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT   0x0000003b
+
+/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030
+
+/***************************************************************************
+ *SCB2_EXTN_RANGE - SCB2 extn start and end address
+ ***************************************************************************/
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK    0xff000000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT   24
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK      0x00fff000
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT     12
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT   0x000000cb
+
+/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK    0x00000fff
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT   0
+#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0
+
+/***************************************************************************
+ *USB_REVID - USB REVID
+ ***************************************************************************/
+/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK                     0xffffffff
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT                    0
+#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT                  0x00000001
+
+#endif /* #ifndef BCHP_USB_CTRL_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_xpt_bus_if.h b/include/linux/brcmstb/7364a0/bchp_xpt_bus_if.h
new file mode 100644
index 000000000000..d281e314d517
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_xpt_bus_if.h
@@ -0,0 +1,738 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:42 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_BUS_IF_H__
+#define BCHP_XPT_BUS_IF_H__
+
+/***************************************************************************
+ *XPT_BUS_IF - Data Transport Configuration Registers
+ ***************************************************************************/
+#define BCHP_XPT_BUS_IF_MISC_CTRL0               0x00a00080 /* Data Transport Misc Control 0 Register */
+#define BCHP_XPT_BUS_IF_TEST_MODE                0x00a00084 /* Data transport test register */
+#define BCHP_XPT_BUS_IF_REVISION                 0x00a00088 /* Data Transport Revision Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG          0x00a0008c /* Interrupt Status Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN       0x00a00090 /* Interrupt Status Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG         0x00a00094 /* Interrupt Status2 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN      0x00a00098 /* Interrupt Status2 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG         0x00a0009c /* Interrupt Status3 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN      0x00a000a0 /* Interrupt Status3 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG         0x00a000a4 /* Interrupt Status4 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN      0x00a000a8 /* Interrupt Status4 Enable Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG         0x00a000ac /* Interrupt Status5 Register */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN      0x00a000b0 /* Interrupt Status5 Enable Register */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET 0x00a000b4 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR 0x00a000b8 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS 0x00a000bc /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT 0x00a000c0 /* Software initialization control for XPT sub-blocks */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0 0x00a000cc /* LCIF to XMEMIF Debug Registers */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG   0x00a000d0 /* LCIF to XMEMIF Debug Registers */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS            0x00a000d4 /* Data Transport max number of playbacks supported */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS          0x00a000d8 /* Data Transport max number of PID parsers supported */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS         0x00a000dc /* Data Transport max number of PID channels supported excluding MEMDMA */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS  0x00a000e0 /* Data Transport max number of PID channels supported for MEMDMA */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS          0x00a000e4 /* Data Transport max number of input bands supported */
+#define BCHP_XPT_BUS_IF_MAX_PCRS                 0x00a000e8 /* Data Transport max number of PCRs supported */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS        0x00a000ec /* Data Transport max number of TPIT channels supported */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS        0x00a000f0 /* Data Transport max number of RAVE contexts supported */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS         0x00a000f4 /* Data Transport max number of RMX channels supported */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS          0x00a000f8 /* Data Transport max number of MSG buffers supported */
+#define BCHP_XPT_BUS_IF_MAX_SCDS                 0x00a000fc /* Data Transport max number of SCDs supported */
+
+/***************************************************************************
+ *MISC_CTRL0 - Data Transport Misc Control 0 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:07] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK                  0xffffff80
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT                 7
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: XPT_COUNTER_SCF [06:05] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_MASK            0x00000060
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_SHIFT           5
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_DEFAULT         0x00000001
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_108MHz          0
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_216MHz          1
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_270MHz          2
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_324MHz          3
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [04:03] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK                  0x00000018
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT                 3
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK        0x00000004
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT       2
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: MPOD_INT_TEST_MODE [01:01] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_MASK         0x00000002
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_SHIFT        1
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_DEFAULT      0x00000000
+
+/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0
+#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TEST_MODE - Data transport test register
+ ***************************************************************************/
+/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK                   0xfffffffe
+#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT                  1
+
+/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK            0x00000001
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT           0
+#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_DEFAULT         0x00000000
+
+/***************************************************************************
+ *REVISION - Data Transport Revision Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: REVISION :: reserved0 [31:16] */
+#define BCHP_XPT_BUS_IF_REVISION_reserved0_MASK                    0xffff0000
+#define BCHP_XPT_BUS_IF_REVISION_reserved0_SHIFT                   16
+
+/* XPT_BUS_IF :: REVISION :: MAJOR_REV_NUMBER [15:08] */
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_MASK             0x0000ff00
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_SHIFT            8
+#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_DEFAULT          0x00000040
+
+/* XPT_BUS_IF :: REVISION :: MINOR_REV_NUMBER [07:00] */
+#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_MASK             0x000000ff
+#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_SHIFT            0
+
+/***************************************************************************
+ *INTR_STATUS_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_MASK             0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_SHIFT            28
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_TB_ERR_INTR [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_MASK    0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_SHIFT   27
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_PTR_OOR_INTR [26:26] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_MASK   0x04000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_SHIFT  26
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_PTR_OOR_INTR [25:25] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_MASK   0x02000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_SHIFT  25
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_OVERFLFLOW_INTR [24:24] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_MASK 0x01000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_SHIFT 24
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_OVERFLOW_INTR [23:23] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_MASK  0x00800000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_SHIFT 23
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved1 [22:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_MASK             0x007fffff
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_SHIFT            0
+
+/***************************************************************************
+ *INTR_STATUS_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_MASK          0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_SHIFT         28
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_TB_ERR_INTR_EN [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_MASK 0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_SHIFT 27
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_PTR_OOR_INTR_EN [26:26] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_MASK 0x04000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_SHIFT 26
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_PTR_OOR_INTR_EN [25:25] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_MASK 0x02000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_SHIFT 25
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_OVERFLFLOW_INTR_EN [24:24] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_MASK 0x01000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_SHIFT 24
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_OVERFLOW_INTR_EN [23:23] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_MASK 0x00800000
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_SHIFT 23
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved1 [22:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_MASK          0x007fffff
+#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_SHIFT         0
+
+/***************************************************************************
+ *INTR_STATUS2_REG - Interrupt Status2 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: reserved0 [31:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_MASK            0xfffffff8
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_SHIFT           3
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CA_ERR_INT [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_MASK           0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_SHIFT          2
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_DEFAULT        0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_DEC_ERR_INT [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_MASK       0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_SHIFT      1
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_ENC_ERR_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_MASK       0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_SHIFT      0
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_DEFAULT    0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG_EN - Interrupt Status2 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: reserved0 [31:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_MASK         0xfffffff8
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_SHIFT        3
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CA_ERR_INT_EN [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_MASK     0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_SHIFT    2
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_DEFAULT  0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_DEC_ERR_INT_EN [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_SHIFT 1
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_ENC_ERR_INT_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS3_REG - Interrupt Status3 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS3_REG :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_MASK            0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_SHIFT           1
+
+/* XPT_BUS_IF :: INTR_STATUS3_REG :: MPOD_EXTRACTOR_CRC_ERROR [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS3_REG_EN - Interrupt Status3 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_MASK         0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_SHIFT        1
+
+/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: MPOD_EXTRACTOR_CRC_ERROR_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS4_REG - Interrupt Status4 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK            0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT           28
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK          0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT         27
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_DEFAULT       0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [26:16] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK            0x07ff0000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT           16
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB15_EOB_INT [15:15] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_MASK       0x00008000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_SHIFT      15
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB14_EOB_INT [14:14] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_MASK       0x00004000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_SHIFT      14
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB13_EOB_INT [13:13] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_MASK       0x00002000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_SHIFT      13
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB12_EOB_INT [12:12] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_MASK       0x00001000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_SHIFT      12
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB11_EOB_INT [11:11] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_MASK       0x00000800
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_SHIFT      11
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB10_EOB_INT [10:10] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_MASK       0x00000400
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_SHIFT      10
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_DEFAULT    0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB9_EOB_INT [09:09] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_MASK        0x00000200
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_SHIFT       9
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB8_EOB_INT [08:08] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_MASK        0x00000100
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_SHIFT       8
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB7_EOB_INT [07:07] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_MASK        0x00000080
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_SHIFT       7
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB6_EOB_INT [06:06] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_MASK        0x00000040
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_SHIFT       6
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB5_EOB_INT [05:05] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_MASK        0x00000020
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_SHIFT       5
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB4_EOB_INT [04:04] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_MASK        0x00000010
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_SHIFT       4
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB3_EOB_INT [03:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_MASK        0x00000008
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_SHIFT       3
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB2_EOB_INT [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_MASK        0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_SHIFT       2
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB1_EOB_INT [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_MASK        0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_SHIFT       1
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_DEFAULT     0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB0_EOB_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_MASK        0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_SHIFT       0
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:28] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK         0xf0000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT        28
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: GISB_BRIDGE_EN [27:27] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_MASK    0x08000000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_SHIFT   27
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [26:16] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK         0x07ff0000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT        16
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB15_EOB_INT_EN [15:15] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_MASK 0x00008000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_SHIFT 15
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB14_EOB_INT_EN [14:14] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_MASK 0x00004000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_SHIFT 14
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB13_EOB_INT_EN [13:13] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_MASK 0x00002000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_SHIFT 13
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB12_EOB_INT_EN [12:12] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_MASK 0x00001000
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_SHIFT 12
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB11_EOB_INT_EN [11:11] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_MASK 0x00000800
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_SHIFT 11
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB10_EOB_INT_EN [10:10] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_MASK 0x00000400
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_SHIFT 10
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB9_EOB_INT_EN [09:09] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_MASK  0x00000200
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_SHIFT 9
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB8_EOB_INT_EN [08:08] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_MASK  0x00000100
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_SHIFT 8
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB7_EOB_INT_EN [07:07] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_MASK  0x00000080
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_SHIFT 7
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB6_EOB_INT_EN [06:06] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_MASK  0x00000040
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_SHIFT 6
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB5_EOB_INT_EN [05:05] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_MASK  0x00000020
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_SHIFT 5
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB4_EOB_INT_EN [04:04] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_MASK  0x00000010
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_SHIFT 4
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB3_EOB_INT_EN [03:03] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_MASK  0x00000008
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_SHIFT 3
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB2_EOB_INT_EN [02:02] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_MASK  0x00000004
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_SHIFT 2
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB1_EOB_INT_EN [01:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_MASK  0x00000002
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_SHIFT 1
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB0_EOB_INT_EN [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_MASK  0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_SHIFT 0
+#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS5_REG - Interrupt Status5 Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK            0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT           1
+
+/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK        0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT       0
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register
+ ***************************************************************************/
+/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK         0xfffffffe
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT        1
+
+/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: WRCHECKER_INT [00:00] */
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_MASK     0x00000001
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_SHIFT    0
+#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_DEFAULT  0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_SET - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_MASK    0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_SHIFT   2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: MEMDMA_MCPB_SOFT_INIT_SET [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: XPT_MCPB_SOFT_INIT_SET [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_CLEAR - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_MASK  0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: MEMDMA_MCPB_SOFT_INIT_CLEAR [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: XPT_MCPB_SOFT_INIT_CLEAR [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_STATUS - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_MASK 0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: MEMDMA_MCPB_SOFT_INIT_STATUS [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: XPT_MCPB_SOFT_INIT_STATUS [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000
+
+/***************************************************************************
+ *SUB_MODULE_SOFT_INIT_DO_MEM_INIT - Software initialization control for XPT sub-blocks
+ ***************************************************************************/
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: reserved0 [31:02] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_MASK 0xfffffffc
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_SHIFT 2
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT [01:01] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000002
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 1
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
+
+/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: XPT_MCPB_SOFT_INIT_DO_MEM_INIT [00:00] */
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000001
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 0
+#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001
+
+/***************************************************************************
+ *XMEMIF_RD_LC_DEBUG_REG_0 - LCIF to XMEMIF Debug Registers
+ ***************************************************************************/
+/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: reserved0 [31:16] */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_MASK    0xffff0000
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_SHIFT   16
+
+/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: PSUB_DEBUG_REG [15:00] */
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_MASK 0x0000ffff
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_SHIFT 0
+#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_DEFAULT 0x00000000
+
+/***************************************************************************
+ *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
+ ***************************************************************************/
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK      0xffffffe0
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT     5
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RSBUFF_WR_DEBUG_REG [04:04] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_MASK 0x00000010
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_SHIFT 4
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: XCBUFF_WR_DEBUG_REG [03:03] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_MASK 0x00000008
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_SHIFT 3
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: MSG_DEBUG_REG [02:02] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_MASK  0x00000004
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_SHIFT 2
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_DEFAULT 0x00000000
+
+/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0
+#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MAX_PLAYBACKS - Data Transport max number of playbacks supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:06] */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK               0xffffffc0
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT              6
+
+/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [05:00] */
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK           0x0000003f
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT          0
+#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_DEFAULT        0x00000020
+
+/***************************************************************************
+ *MAX_PID_PARSERS - Data Transport max number of PID parsers supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PID_PARSERS :: reserved0 [31:06] */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_MASK             0xffffffc0
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_SHIFT            6
+
+/* XPT_BUS_IF :: MAX_PID_PARSERS :: MAX_PID_PARSERS [05:00] */
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_MASK       0x0000003f
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_DEFAULT    0x00000018
+
+/***************************************************************************
+ *MAX_PID_CHANNELS - Data Transport max number of PID channels supported excluding MEMDMA
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK            0xfffff000
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT           12
+
+/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK     0x00000fff
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT    0
+#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT  0x00000300
+
+/***************************************************************************
+ *MEMDMA_MAX_PID_CHANNELS - Data Transport max number of PID channels supported for MEMDMA
+ ***************************************************************************/
+/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: reserved0 [31:12] */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_MASK     0xfffff000
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_SHIFT    12
+
+/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0
+#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT 0x00000400
+
+/***************************************************************************
+ *MAX_INPUT_BANDS - Data Transport max number of input bands supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_INPUT_BANDS :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_MASK             0xffffffe0
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_SHIFT            5
+
+/* XPT_BUS_IF :: MAX_INPUT_BANDS :: MAX_INPUT_BANDS [04:00] */
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_MASK       0x0000001f
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_DEFAULT    0x0000000d
+
+/***************************************************************************
+ *MAX_PCRS - Data Transport max number of PCRs supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_PCRS :: reserved0 [31:04] */
+#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_MASK                    0xfffffff0
+#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_SHIFT                   4
+
+/* XPT_BUS_IF :: MAX_PCRS :: MAX_PCRS [03:00] */
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_MASK                     0x0000000f
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_SHIFT                    0
+#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_DEFAULT                  0x0000000e
+
+/***************************************************************************
+ *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:05] */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK           0xffffffe0
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT          5
+
+/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [04:00] */
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK   0x0000001f
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT  0
+#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_DEFAULT 0x00000010
+
+/***************************************************************************
+ *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK           0xffffff00
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT          8
+
+/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK   0x000000ff
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT  0
+#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_DEFAULT 0x00000030
+
+/***************************************************************************
+ *MAX_RMX_CHANNELS - Data Transport max number of RMX channels supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: reserved0 [31:04] */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_MASK            0xfffffff0
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_SHIFT           4
+
+/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: MAX_RMX_CHANNELS [03:00] */
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_MASK     0x0000000f
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_SHIFT    0
+#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_DEFAULT  0x00000002
+
+/***************************************************************************
+ *MAX_MSG_BUFFERS - Data Transport max number of MSG buffers supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: reserved0 [31:09] */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_MASK             0xfffffe00
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_SHIFT            9
+
+/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: MAX_MSG_BUFFERS [08:00] */
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_MASK       0x000001ff
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_SHIFT      0
+#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_DEFAULT    0x00000100
+
+/***************************************************************************
+ *MAX_SCDS - Data Transport max number of SCDs supported
+ ***************************************************************************/
+/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:09] */
+#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK                    0xfffffe00
+#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT                   9
+
+/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [08:00] */
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK                     0x000001ff
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT                    0
+#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_DEFAULT                  0x00000040
+
+#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */
+
+/* End of File */
diff --git a/include/linux/brcmstb/7364a0/bchp_xpt_fe.h b/include/linux/brcmstb/7364a0/bchp_xpt_fe.h
new file mode 100644
index 000000000000..6ef43972e145
--- /dev/null
+++ b/include/linux/brcmstb/7364a0/bchp_xpt_fe.h
@@ -0,0 +1,12516 @@
+/***************************************************************************
+ *     Copyright (c) 1999-2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Module Description:
+ *                     DO NOT EDIT THIS FILE DIRECTLY
+ *
+ * This module was generated magically with RDB from a source description
+ * file. You must edit the source file for changes to be made to this file.
+ *
+ *
+ * Date:           Generated on              Wed Jul 23 03:11:39 2014
+ *                 Full Compile MD5 Checksum a68bc62e9dd3be19fcad480c369d60fd
+ *                   (minus title and desc)  
+ *                 MD5 Checksum              14382795d76d8497c2dd1bcf3f5d36da
+ *
+ * Compiled with:  RDB Utility               combo_header.pl
+ *                 RDB Parser                3.0
+ *                 unknown                   unknown
+ *                 Perl Interpreter          5.008008
+ *                 Operating System          linux
+ *
+ * Revision History:
+ *
+ * $brcm_Log: $
+ *
+ ***************************************************************************/
+
+#ifndef BCHP_XPT_FE_H__
+#define BCHP_XPT_FE_H__
+
+/***************************************************************************
+ *XPT_FE - XPT FRONTEND Control Registers
+ ***************************************************************************/
+#define BCHP_XPT_FE_FE_CTRL                      0x00a20000 /* Data Transport Front-End Control Register */
+#define BCHP_XPT_FE_PWR_CTRL                     0x00a20004 /* Data Transport Front-End Power Control Register */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL              0x00a20008 /* Maximum Pid Channel number register */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL          0x00a2000c /* Data Transport Input Band Sync detect control */
+#define BCHP_XPT_FE_INTR_STATUS0_REG             0x00a20010 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS1_REG             0x00a20014 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS2_REG             0x00a20018 /* Interrupt Status Register */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN          0x00a20024 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN          0x00a20028 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN          0x00a2002c /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG        0x00a20038 /* TSMF Demultiplexer Interrupt Status Register */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN     0x00a2003c /* TSMF Demultiplexer Interrupt Status Enable Register */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG    0x00a20040 /* Interrupt Status Register */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN 0x00a20048 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG 0x00a20050 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG 0x00a20058 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG 0x00a20060 /* Interrupt Status Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN 0x00a20068 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN 0x00a20070 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN 0x00a20078 /* Interrupt Status Enable Register */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL             0x00a200a0 /* FE_ATS_COUNTER_CTRL */
+#define BCHP_XPT_FE_ATS_TS_MOD300                0x00a200a4 /* FE_ATS_TS_MOD300 */
+#define BCHP_XPT_FE_ATS_TS_BINARY                0x00a200a8 /* FE_ATS_TS_BINARY */
+#define BCHP_XPT_FE_TV_STATUS_0                  0x00a200b0 /* TV Status_0 */
+#define BCHP_XPT_FE_TV_STATUS_1                  0x00a200b4 /* TV Status_1 */
+#define BCHP_XPT_FE_TV_STATUS_2                  0x00a200b8 /* TV Status_2 */
+#define BCHP_XPT_FE_TV_STATUS_3                  0x00a200bc /* TV Status_3 */
+#define BCHP_XPT_FE_TV_STATUS_4                  0x00a200c0 /* TV Status_4 */
+#define BCHP_XPT_FE_IB0_CTRL                     0x00a20100 /* Data Transport Input Band 0 Control Register */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT               0x00a20104 /* Data Transport Input Band 0 Sync counter Register */
+#define BCHP_XPT_FE_IB1_CTRL                     0x00a20108 /* Data Transport Input Band 1 Control Register */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT               0x00a2010c /* Data Transport Input Band 1 Sync counter Register */
+#define BCHP_XPT_FE_IB2_CTRL                     0x00a20110 /* Data Transport Input Band 2 Control Register */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT               0x00a20114 /* Data Transport Input Band 2 Sync counter Register */
+#define BCHP_XPT_FE_IB3_CTRL                     0x00a20118 /* Data Transport Input Band 3 Control Register */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT               0x00a2011c /* Data Transport Input Band 3 Sync counter Register */
+#define BCHP_XPT_FE_IB4_CTRL                     0x00a20120 /* Data Transport Input Band 4 Control Register */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT               0x00a20124 /* Data Transport Input Band 4 Sync counter Register */
+#define BCHP_XPT_FE_IB5_CTRL                     0x00a20128 /* Data Transport Input Band 5 Control Register */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT               0x00a2012c /* Data Transport Input Band 5 Sync counter Register */
+#define BCHP_XPT_FE_IB6_CTRL                     0x00a20130 /* Data Transport Input Band 6 Control Register */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT               0x00a20134 /* Data Transport Input Band 6 Sync counter Register */
+#define BCHP_XPT_FE_IB7_CTRL                     0x00a20138 /* Data Transport Input Band 7 Control Register */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT               0x00a2013c /* Data Transport Input Band 7 Sync counter Register */
+#define BCHP_XPT_FE_IB8_CTRL                     0x00a20140 /* Data Transport Input Band 8 Control Register */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT               0x00a20144 /* Data Transport Input Band 8 Sync counter Register */
+#define BCHP_XPT_FE_IB9_CTRL                     0x00a20148 /* Data Transport Input Band 9 Control Register */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT               0x00a2014c /* Data Transport Input Band 9 Sync counter Register */
+#define BCHP_XPT_FE_IB10_CTRL                    0x00a20150 /* Data Transport Input Band 10 Control Register */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT              0x00a20154 /* Data Transport Input Band 10 Sync counter Register */
+#define BCHP_XPT_FE_IB11_CTRL                    0x00a20158 /* Data Transport Input Band 11 Control Register */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT              0x00a2015c /* Data Transport Input Band 11 Sync counter Register */
+#define BCHP_XPT_FE_IB12_CTRL                    0x00a20160 /* Data Transport Input Band 12 Control Register */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT              0x00a20164 /* Data Transport Input Band 12 Sync counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1       0x00a20200 /* Data Transport Parser Band 0 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2       0x00a20204 /* Data Transport Parser Band 0 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL 0x00a20208 /* Data Transport Parser Band 0 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1       0x00a2020c /* Data Transport Parser Band 1 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2       0x00a20210 /* Data Transport Parser Band 1 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL 0x00a20214 /* Data Transport Parser Band 1 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1       0x00a20218 /* Data Transport Parser Band 2 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2       0x00a2021c /* Data Transport Parser Band 2 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL 0x00a20220 /* Data Transport Parser Band 2 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1       0x00a20224 /* Data Transport Parser Band 3 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2       0x00a20228 /* Data Transport Parser Band 3 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL 0x00a2022c /* Data Transport Parser Band 3 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1       0x00a20230 /* Data Transport Parser Band 4 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2       0x00a20234 /* Data Transport Parser Band 4 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL 0x00a20238 /* Data Transport Parser Band 4 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1       0x00a2023c /* Data Transport Parser Band 5 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2       0x00a20240 /* Data Transport Parser Band 5 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL 0x00a20244 /* Data Transport Parser Band 5 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1       0x00a20248 /* Data Transport Parser Band 6 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2       0x00a2024c /* Data Transport Parser Band 6 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL 0x00a20250 /* Data Transport Parser Band 6 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1       0x00a20254 /* Data Transport Parser Band 7 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2       0x00a20258 /* Data Transport Parser Band 7 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL 0x00a2025c /* Data Transport Parser Band 7 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1       0x00a20260 /* Data Transport Parser Band 8 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2       0x00a20264 /* Data Transport Parser Band 8 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL 0x00a20268 /* Data Transport Parser Band 8 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1       0x00a2026c /* Data Transport Parser Band 9 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2       0x00a20270 /* Data Transport Parser Band 9 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL 0x00a20274 /* Data Transport Parser Band 9 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1      0x00a20278 /* Data Transport Parser Band 10 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2      0x00a2027c /* Data Transport Parser Band 10 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL 0x00a20280 /* Data Transport Parser Band 10 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1      0x00a20284 /* Data Transport Parser Band 11 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2      0x00a20288 /* Data Transport Parser Band 11 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL 0x00a2028c /* Data Transport Parser Band 11 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1      0x00a20290 /* Data Transport Parser Band 12 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL2      0x00a20294 /* Data Transport Parser Band 12 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_ALL_PASS_CTRL 0x00a20298 /* Data Transport Parser Band 12 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL1      0x00a2029c /* Data Transport Parser Band 13 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_CTRL2      0x00a202a0 /* Data Transport Parser Band 13 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_ALL_PASS_CTRL 0x00a202a4 /* Data Transport Parser Band 13 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL1      0x00a202a8 /* Data Transport Parser Band 14 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_CTRL2      0x00a202ac /* Data Transport Parser Band 14 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_ALL_PASS_CTRL 0x00a202b0 /* Data Transport Parser Band 14 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL1      0x00a202b4 /* Data Transport Parser Band 15 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_CTRL2      0x00a202b8 /* Data Transport Parser Band 15 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_ALL_PASS_CTRL 0x00a202bc /* Data Transport Parser Band 15 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL1      0x00a202c0 /* Data Transport Parser Band 16 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_CTRL2      0x00a202c4 /* Data Transport Parser Band 16 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_ALL_PASS_CTRL 0x00a202c8 /* Data Transport Parser Band 16 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL1      0x00a202cc /* Data Transport Parser Band 17 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_CTRL2      0x00a202d0 /* Data Transport Parser Band 17 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_ALL_PASS_CTRL 0x00a202d4 /* Data Transport Parser Band 17 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL1      0x00a202d8 /* Data Transport Parser Band 18 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_CTRL2      0x00a202dc /* Data Transport Parser Band 18 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_ALL_PASS_CTRL 0x00a202e0 /* Data Transport Parser Band 18 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL1      0x00a202e4 /* Data Transport Parser Band 19 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_CTRL2      0x00a202e8 /* Data Transport Parser Band 19 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_ALL_PASS_CTRL 0x00a202ec /* Data Transport Parser Band 19 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL1      0x00a202f0 /* Data Transport Parser Band 20 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_CTRL2      0x00a202f4 /* Data Transport Parser Band 20 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_ALL_PASS_CTRL 0x00a202f8 /* Data Transport Parser Band 20 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL1      0x00a202fc /* Data Transport Parser Band 21 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_CTRL2      0x00a20300 /* Data Transport Parser Band 21 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_ALL_PASS_CTRL 0x00a20304 /* Data Transport Parser Band 21 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL1      0x00a20308 /* Data Transport Parser Band 22 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_CTRL2      0x00a2030c /* Data Transport Parser Band 22 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_ALL_PASS_CTRL 0x00a20310 /* Data Transport Parser Band 22 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL1      0x00a20314 /* Data Transport Parser Band 23 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_CTRL2      0x00a20318 /* Data Transport Parser Band 23 Control Register 2 */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_ALL_PASS_CTRL 0x00a2031c /* Data Transport Parser Band 23 Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TO_PARSER3_BAND_ID 0x00a20380 /* MINI PID PARSER0 to PARSER3 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TO_PARSER7_BAND_ID 0x00a20384 /* MINI PID PARSER4 to PARSER7 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TO_PARSER11_BAND_ID 0x00a20388 /* MINI PID PARSER8 to PARSER11 BAND ID */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TO_PARSER15_BAND_ID 0x00a2038c /* MINI PID PARSER12 to PARSER15 BAND ID */
+#define BCHP_XPT_FE_TSMF0_CTRL                   0x00a203a0 /* Data Transport TSMF Demultiplexer -- Control Register */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_LO            0x00a203a4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
+#define BCHP_XPT_FE_TSMF0_SLOT_MAP_HI            0x00a203a8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
+#define BCHP_XPT_FE_TSMF0_STATUS                 0x00a203ac /* Data Transport TSMF Demultiplexer -- Status Register */
+#define BCHP_XPT_FE_TSMF1_CTRL                   0x00a203b0 /* Data Transport TSMF Demultiplexer -- Control Register */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_LO            0x00a203b4 /* Data Transport TSMF Demultiplexer -- Slot Map Vector LSBs Register */
+#define BCHP_XPT_FE_TSMF1_SLOT_MAP_HI            0x00a203b8 /* Data Transport TSMF Demultiplexer -- Slot Map Vector MSBs Register */
+#define BCHP_XPT_FE_TSMF1_STATUS                 0x00a203bc /* Data Transport TSMF Demultiplexer -- Status Register */
+#define BCHP_XPT_FE_MTSIF_RX0_CTRL1              0x00a204a0 /* FE_MTSIF_RX0_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX0_SECRET_WORD        0x00a204a4 /* MTSIF RX0 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND31_ID_DROP 0x00a204a8 /* MTSIF RX0 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND0_BAND3_ID     0x00a204ac /* MTSIF RX0 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND4_BAND7_ID     0x00a204b0 /* MTSIF RX0 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND8_BAND11_ID    0x00a204b4 /* MTSIF RX0 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND12_BAND15_ID   0x00a204b8 /* MTSIF RX0 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND16_BAND19_ID   0x00a204bc /* MTSIF RX0 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND20_BAND23_ID   0x00a204c0 /* MTSIF RX0 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND24_BAND27_ID   0x00a204c4 /* MTSIF RX0 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND28_BAND31_ID   0x00a204c8 /* MTSIF RX0 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND32_BAND35_ID   0x00a204cc /* MTSIF RX0 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND36_BAND39_ID   0x00a204d0 /* MTSIF RX0 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND40_BAND43_ID   0x00a204d4 /* MTSIF RX0 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND44_BAND47_ID   0x00a204d8 /* MTSIF RX0 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND48_BAND51_ID   0x00a204dc /* MTSIF RX0 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND52_BAND55_ID   0x00a204e0 /* MTSIF RX0 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND56_BAND59_ID   0x00a204e4 /* MTSIF RX0 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_BAND60_BAND63_ID   0x00a204e8 /* MTSIF RX0 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX0_PKT_BAND0_BAND31_DETECT 0x00a204ec /* MTSIF RX0 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX1_CTRL1              0x00a204f0 /* FE_MTSIF_RX1_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX1_SECRET_WORD        0x00a204f4 /* MTSIF RX1 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND31_ID_DROP 0x00a204f8 /* MTSIF RX1 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND0_BAND3_ID     0x00a204fc /* MTSIF RX1 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND4_BAND7_ID     0x00a20500 /* MTSIF RX1 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND8_BAND11_ID    0x00a20504 /* MTSIF RX1 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND12_BAND15_ID   0x00a20508 /* MTSIF RX1 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND16_BAND19_ID   0x00a2050c /* MTSIF RX1 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND20_BAND23_ID   0x00a20510 /* MTSIF RX1 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND24_BAND27_ID   0x00a20514 /* MTSIF RX1 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND28_BAND31_ID   0x00a20518 /* MTSIF RX1 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND32_BAND35_ID   0x00a2051c /* MTSIF RX1 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND36_BAND39_ID   0x00a20520 /* MTSIF RX1 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND40_BAND43_ID   0x00a20524 /* MTSIF RX1 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND44_BAND47_ID   0x00a20528 /* MTSIF RX1 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND48_BAND51_ID   0x00a2052c /* MTSIF RX1 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND52_BAND55_ID   0x00a20530 /* MTSIF RX1 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND56_BAND59_ID   0x00a20534 /* MTSIF RX1 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_BAND60_BAND63_ID   0x00a20538 /* MTSIF RX1 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX1_PKT_BAND0_BAND31_DETECT 0x00a2053c /* MTSIF RX1 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX2_CTRL1              0x00a20540 /* FE_MTSIF_RX2_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX2_SECRET_WORD        0x00a20544 /* MTSIF RX2 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND31_ID_DROP 0x00a20548 /* MTSIF RX2 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND0_BAND3_ID     0x00a2054c /* MTSIF RX2 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND4_BAND7_ID     0x00a20550 /* MTSIF RX2 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND8_BAND11_ID    0x00a20554 /* MTSIF RX2 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND12_BAND15_ID   0x00a20558 /* MTSIF RX2 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND16_BAND19_ID   0x00a2055c /* MTSIF RX2 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND20_BAND23_ID   0x00a20560 /* MTSIF RX2 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND24_BAND27_ID   0x00a20564 /* MTSIF RX2 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND28_BAND31_ID   0x00a20568 /* MTSIF RX2 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND32_BAND35_ID   0x00a2056c /* MTSIF RX2 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND36_BAND39_ID   0x00a20570 /* MTSIF RX2 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND40_BAND43_ID   0x00a20574 /* MTSIF RX2 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND44_BAND47_ID   0x00a20578 /* MTSIF RX2 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND48_BAND51_ID   0x00a2057c /* MTSIF RX2 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND52_BAND55_ID   0x00a20580 /* MTSIF RX2 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND56_BAND59_ID   0x00a20584 /* MTSIF RX2 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_BAND60_BAND63_ID   0x00a20588 /* MTSIF RX2 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX2_PKT_BAND0_BAND31_DETECT 0x00a2058c /* MTSIF RX2 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MTSIF_RX3_CTRL1              0x00a20590 /* FE_MTSIF_RX3_CTRL1 */
+#define BCHP_XPT_FE_MTSIF_RX3_SECRET_WORD        0x00a20594 /* MTSIF RX3 Secret Word Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND31_ID_DROP 0x00a20598 /* MTSIF RX3 Band0 to Band31 ID Drop Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND0_BAND3_ID     0x00a2059c /* MTSIF RX3 Band0 to Band3 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND4_BAND7_ID     0x00a205a0 /* MTSIF RX3 Band4 to Band7 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND8_BAND11_ID    0x00a205a4 /* MTSIF RX3 Band8 to Band11 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND12_BAND15_ID   0x00a205a8 /* MTSIF RX3 Band12 to Band15 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND16_BAND19_ID   0x00a205ac /* MTSIF RX3 Band16 to Band19 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND20_BAND23_ID   0x00a205b0 /* MTSIF RX3 Band20 to Band23 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND24_BAND27_ID   0x00a205b4 /* MTSIF RX3 Band24 to Band27 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND28_BAND31_ID   0x00a205b8 /* MTSIF RX3 Band28 to Band31 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND32_BAND35_ID   0x00a205bc /* MTSIF RX3 Band32 to Band35 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND36_BAND39_ID   0x00a205c0 /* MTSIF RX3 Band36 to Band39 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND40_BAND43_ID   0x00a205c4 /* MTSIF RX3 Band40 to Band43 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND44_BAND47_ID   0x00a205c8 /* MTSIF RX3 Band44 to Band47 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND48_BAND51_ID   0x00a205cc /* MTSIF RX3 Band48 to Band51 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND52_BAND55_ID   0x00a205d0 /* MTSIF RX3 Band52 to Band55 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND56_BAND59_ID   0x00a205d4 /* MTSIF RX3 Band56 to Band59 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_BAND60_BAND63_ID   0x00a205d8 /* MTSIF RX3 Band60 to Band63 ID Register */
+#define BCHP_XPT_FE_MTSIF_RX3_PKT_BAND0_BAND31_DETECT 0x00a205dc /* MTSIF RX3 Packet Band0 to Band31 Detect Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_TB_CTRL1    0x00a20800 /* Data Transport Parser Band 0 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_SYNC_COUNT  0x00a20804 /* Data Transport Parser Band 0 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_TB_CTRL1    0x00a20808 /* Data Transport Parser Band 1 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_SYNC_COUNT  0x00a2080c /* Data Transport Parser Band 1 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_TB_CTRL1    0x00a20810 /* Data Transport Parser Band 2 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_SYNC_COUNT  0x00a20814 /* Data Transport Parser Band 2 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_TB_CTRL1    0x00a20818 /* Data Transport Parser Band 3 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_SYNC_COUNT  0x00a2081c /* Data Transport Parser Band 3 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_TB_CTRL1    0x00a20820 /* Data Transport Parser Band 4 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_SYNC_COUNT  0x00a20824 /* Data Transport Parser Band 4 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_TB_CTRL1    0x00a20828 /* Data Transport Parser Band 5 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_SYNC_COUNT  0x00a2082c /* Data Transport Parser Band 5 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_TB_CTRL1    0x00a20830 /* Data Transport Parser Band 6 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_SYNC_COUNT  0x00a20834 /* Data Transport Parser Band 6 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_TB_CTRL1    0x00a20838 /* Data Transport Parser Band 7 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_SYNC_COUNT  0x00a2083c /* Data Transport Parser Band 7 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_TB_CTRL1    0x00a20840 /* Data Transport Parser Band 8 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_SYNC_COUNT  0x00a20844 /* Data Transport Parser Band 8 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_TB_CTRL1    0x00a20848 /* Data Transport Parser Band 9 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_SYNC_COUNT  0x00a2084c /* Data Transport Parser Band 9 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_TB_CTRL1   0x00a20850 /* Data Transport Parser Band 10 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_SYNC_COUNT 0x00a20854 /* Data Transport Parser Band 10 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_TB_CTRL1   0x00a20858 /* Data Transport Parser Band 11 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_SYNC_COUNT 0x00a2085c /* Data Transport Parser Band 11 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_TB_CTRL1   0x00a20860 /* Data Transport Parser Band 12 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_SYNC_COUNT 0x00a20864 /* Data Transport Parser Band 12 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_TB_CTRL1   0x00a20868 /* Data Transport Parser Band 13 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER13_SYNC_COUNT 0x00a2086c /* Data Transport Parser Band 13 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_TB_CTRL1   0x00a20870 /* Data Transport Parser Band 14 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER14_SYNC_COUNT 0x00a20874 /* Data Transport Parser Band 14 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_TB_CTRL1   0x00a20878 /* Data Transport Parser Band 15 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER15_SYNC_COUNT 0x00a2087c /* Data Transport Parser Band 15 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_TB_CTRL1   0x00a20880 /* Data Transport Parser Band 16 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER16_SYNC_COUNT 0x00a20884 /* Data Transport Parser Band 16 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_TB_CTRL1   0x00a20888 /* Data Transport Parser Band 17 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER17_SYNC_COUNT 0x00a2088c /* Data Transport Parser Band 17 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_TB_CTRL1   0x00a20890 /* Data Transport Parser Band 18 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER18_SYNC_COUNT 0x00a20894 /* Data Transport Parser Band 18 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_TB_CTRL1   0x00a20898 /* Data Transport Parser Band 19 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER19_SYNC_COUNT 0x00a2089c /* Data Transport Parser Band 19 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_TB_CTRL1   0x00a208a0 /* Data Transport Parser Band 20 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER20_SYNC_COUNT 0x00a208a4 /* Data Transport Parser Band 20 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_TB_CTRL1   0x00a208a8 /* Data Transport Parser Band 21 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER21_SYNC_COUNT 0x00a208ac /* Data Transport Parser Band 21 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_TB_CTRL1   0x00a208b0 /* Data Transport Parser Band 22 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER22_SYNC_COUNT 0x00a208b4 /* Data Transport Parser Band 22 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_TB_CTRL1   0x00a208b8 /* Data Transport Parser Band 23 Transponder Bonding Control Register */
+#define BCHP_XPT_FE_MINI_PID_PARSER23_SYNC_COUNT 0x00a208bc /* Data Transport Parser Band 23 Transponder Bonding Sync Counter Register */
+#define BCHP_XPT_FE_TB_GLOBAL_CTRL1              0x00a20900 /* Transponder Bonding Global Control Register 1 */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_LENGTH_ERROR_STATUS0_REG 0x00a2090c /* Parsers Private Data Length Error Status Register */
+#define BCHP_XPT_FE_TB_PARSERS_PRIVATE_DATA_FIELD_LENGTH_ERROR_STATUS0_REG 0x00a20910 /* Parsers Private Data Field Length Error Status Register */
+
+/***************************************************************************
+ *FE_CTRL - Data Transport Front-End Control Register
+ ***************************************************************************/
+/* XPT_FE :: FE_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_FE_CTRL_reserved0_MASK                         0xffffe000
+#define BCHP_XPT_FE_FE_CTRL_reserved0_SHIFT                        13
+
+/* XPT_FE :: FE_CTRL :: SW_CTRL_PID_VERSION_INCR_EN [12:12] */
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_MASK       0x00001000
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_SHIFT      12
+#define BCHP_XPT_FE_FE_CTRL_SW_CTRL_PID_VERSION_INCR_EN_DEFAULT    0x00000000
+
+/* XPT_FE :: FE_CTRL :: reserved1 [11:09] */
+#define BCHP_XPT_FE_FE_CTRL_reserved1_MASK                         0x00000e00
+#define BCHP_XPT_FE_FE_CTRL_reserved1_SHIFT                        9
+
+/* XPT_FE :: FE_CTRL :: SPARE_FUNC [08:02] */
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_MASK                        0x000001fc
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_SHIFT                       2
+#define BCHP_XPT_FE_FE_CTRL_SPARE_FUNC_DEFAULT                     0x00000000
+
+/* XPT_FE :: FE_CTRL :: MPOD_OP_PSUB_NULL_PKT_EN [01:01] */
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_MASK          0x00000002
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_SHIFT         1
+#define BCHP_XPT_FE_FE_CTRL_MPOD_OP_PSUB_NULL_PKT_EN_DEFAULT       0x00000000
+
+/* XPT_FE :: FE_CTRL :: ERROR_INT_TEST_MODE [00:00] */
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_MASK               0x00000001
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_SHIFT              0
+#define BCHP_XPT_FE_FE_CTRL_ERROR_INT_TEST_MODE_DEFAULT            0x00000000
+
+/***************************************************************************
+ *PWR_CTRL - Data Transport Front-End Power Control Register
+ ***************************************************************************/
+/* XPT_FE :: PWR_CTRL :: reserved0 [31:01] */
+#define BCHP_XPT_FE_PWR_CTRL_reserved0_MASK                        0xfffffffe
+#define BCHP_XPT_FE_PWR_CTRL_reserved0_SHIFT                       1
+
+/* XPT_FE :: PWR_CTRL :: FE_TIMESTAMP_DIS [00:00] */
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_MASK                 0x00000001
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_SHIFT                0
+#define BCHP_XPT_FE_PWR_CTRL_FE_TIMESTAMP_DIS_DEFAULT              0x00000000
+
+/***************************************************************************
+ *MAX_PID_CHANNEL - Maximum Pid Channel number register
+ ***************************************************************************/
+/* XPT_FE :: MAX_PID_CHANNEL :: reserved0 [31:12] */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_MASK                 0xfffff000
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_SHIFT                12
+
+/* XPT_FE :: MAX_PID_CHANNEL :: MAX_PID_CHANNEL [11:00] */
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_MASK           0x00000fff
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_SHIFT          0
+#define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_DEFAULT        0x000003ff
+
+/***************************************************************************
+ *IB_SYNC_DETECT_CTRL - Data Transport Input Band Sync detect control
+ ***************************************************************************/
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: reserved0 [31:06] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_MASK             0xffffffc0
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_reserved0_SHIFT            6
+
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_OUT_CNT [05:03] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_MASK       0x00000038
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_SHIFT      3
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_OUT_CNT_DEFAULT    0x00000000
+
+/* XPT_FE :: IB_SYNC_DETECT_CTRL :: IB_SYNC_IN_CNT [02:00] */
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_MASK        0x00000007
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_SHIFT       0
+#define BCHP_XPT_FE_IB_SYNC_DETECT_CTRL_IB_SYNC_IN_CNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER31_LENGTH_ERROR [31:31] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_MASK    0x80000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_SHIFT   31
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER31_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER30_LENGTH_ERROR [30:30] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_MASK    0x40000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_SHIFT   30
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER30_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER29_LENGTH_ERROR [29:29] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_MASK    0x20000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_SHIFT   29
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER29_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER28_LENGTH_ERROR [28:28] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_MASK    0x10000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_SHIFT   28
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER28_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER27_LENGTH_ERROR [27:27] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_MASK    0x08000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_SHIFT   27
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER27_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER26_LENGTH_ERROR [26:26] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_MASK    0x04000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_SHIFT   26
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER26_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER25_LENGTH_ERROR [25:25] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_MASK    0x02000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_SHIFT   25
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER25_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER24_LENGTH_ERROR [24:24] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_MASK    0x01000000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_SHIFT   24
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER24_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER23_LENGTH_ERROR [23:23] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_MASK    0x00800000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_SHIFT   23
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER23_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER22_LENGTH_ERROR [22:22] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_MASK    0x00400000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_SHIFT   22
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER22_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER21_LENGTH_ERROR [21:21] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_MASK    0x00200000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_SHIFT   21
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER21_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER20_LENGTH_ERROR [20:20] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_MASK    0x00100000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_SHIFT   20
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER20_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER19_LENGTH_ERROR [19:19] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_MASK    0x00080000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_SHIFT   19
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER19_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER18_LENGTH_ERROR [18:18] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_MASK    0x00040000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_SHIFT   18
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER18_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER17_LENGTH_ERROR [17:17] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_MASK    0x00020000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_SHIFT   17
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER17_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER16_LENGTH_ERROR [16:16] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_MASK    0x00010000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_SHIFT   16
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER16_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER15_LENGTH_ERROR [15:15] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_MASK    0x00008000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_SHIFT   15
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER15_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER14_LENGTH_ERROR [14:14] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_MASK    0x00004000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_SHIFT   14
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER14_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER13_LENGTH_ERROR [13:13] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_MASK    0x00002000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_SHIFT   13
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER13_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER12_LENGTH_ERROR [12:12] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_MASK    0x00001000
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_SHIFT   12
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER12_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER11_LENGTH_ERROR [11:11] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_MASK    0x00000800
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_SHIFT   11
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER11_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER10_LENGTH_ERROR [10:10] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_MASK    0x00000400
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_SHIFT   10
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER10_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER9_LENGTH_ERROR [09:09] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_MASK     0x00000200
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_SHIFT    9
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER9_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER8_LENGTH_ERROR [08:08] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_MASK     0x00000100
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_SHIFT    8
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER8_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER7_LENGTH_ERROR [07:07] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_MASK     0x00000080
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_SHIFT    7
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER7_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER6_LENGTH_ERROR [06:06] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_MASK     0x00000040
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_SHIFT    6
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER6_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER5_LENGTH_ERROR [05:05] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_MASK     0x00000020
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_SHIFT    5
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER5_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER4_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_MASK     0x00000010
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_SHIFT    4
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER4_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER3_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_MASK     0x00000008
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_SHIFT    3
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER3_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER2_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_MASK     0x00000004
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_SHIFT    2
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER2_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER1_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_MASK     0x00000002
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_SHIFT    1
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER1_LENGTH_ERROR_DEFAULT  0x00000000
+
+/* XPT_FE :: INTR_STATUS0_REG :: PARSER0_LENGTH_ERROR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_MASK     0x00000001
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_SHIFT    0
+#define BCHP_XPT_FE_INTR_STATUS0_REG_PARSER0_LENGTH_ERROR_DEFAULT  0x00000000
+
+/***************************************************************************
+ *INTR_STATUS1_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER31_TRANSPORT_ERROR [31:31] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_SHIFT 31
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER31_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER30_TRANSPORT_ERROR [30:30] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_SHIFT 30
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER30_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER29_TRANSPORT_ERROR [29:29] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_SHIFT 29
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER29_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER28_TRANSPORT_ERROR [28:28] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_SHIFT 28
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER28_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER27_TRANSPORT_ERROR [27:27] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_SHIFT 27
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER27_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER26_TRANSPORT_ERROR [26:26] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_SHIFT 26
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER26_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER25_TRANSPORT_ERROR [25:25] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_SHIFT 25
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER25_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER24_TRANSPORT_ERROR [24:24] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_SHIFT 24
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER24_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER23_TRANSPORT_ERROR [23:23] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_SHIFT 23
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER23_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER22_TRANSPORT_ERROR [22:22] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_SHIFT 22
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER22_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER21_TRANSPORT_ERROR [21:21] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_SHIFT 21
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER21_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER20_TRANSPORT_ERROR [20:20] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_SHIFT 20
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER20_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER19_TRANSPORT_ERROR [19:19] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_SHIFT 19
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER19_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER18_TRANSPORT_ERROR [18:18] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_SHIFT 18
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER18_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER17_TRANSPORT_ERROR [17:17] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_SHIFT 17
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER17_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER16_TRANSPORT_ERROR [16:16] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_SHIFT 16
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER16_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER15_TRANSPORT_ERROR [15:15] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_SHIFT 15
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER15_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER14_TRANSPORT_ERROR [14:14] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_SHIFT 14
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER14_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER13_TRANSPORT_ERROR [13:13] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_SHIFT 13
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER13_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER12_TRANSPORT_ERROR [12:12] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_SHIFT 12
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER12_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER11_TRANSPORT_ERROR [11:11] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_SHIFT 11
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER11_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER10_TRANSPORT_ERROR [10:10] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_SHIFT 10
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER10_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER9_TRANSPORT_ERROR [09:09] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_MASK  0x00000200
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_SHIFT 9
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER9_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER8_TRANSPORT_ERROR [08:08] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_MASK  0x00000100
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_SHIFT 8
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER8_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER7_TRANSPORT_ERROR [07:07] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_MASK  0x00000080
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_SHIFT 7
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER7_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER6_TRANSPORT_ERROR [06:06] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_MASK  0x00000040
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_SHIFT 6
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER6_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER5_TRANSPORT_ERROR [05:05] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_MASK  0x00000020
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_SHIFT 5
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER5_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER4_TRANSPORT_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_MASK  0x00000010
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_SHIFT 4
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER4_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER3_TRANSPORT_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_MASK  0x00000008
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_SHIFT 3
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER3_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER2_TRANSPORT_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_MASK  0x00000004
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_SHIFT 2
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER2_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER1_TRANSPORT_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_MASK  0x00000002
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_SHIFT 1
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER1_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS1_REG :: PARSER0_TRANSPORT_ERROR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_MASK  0x00000001
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_SHIFT 0
+#define BCHP_XPT_FE_INTR_STATUS1_REG_PARSER0_TRANSPORT_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS2_REG :: reserved0 [31:05] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_MASK                0xffffffe0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_reserved0_SHIFT               5
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR [04:04] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 4
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX3_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR [03:03] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 3
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX2_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR [02:02] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 2
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX1_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR [01:01] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_SHIFT 1
+#define BCHP_XPT_FE_INTR_STATUS2_REG_MTSIF_RX0_MINI_PID_PARSER_LENGTH_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: INTR_STATUS2_REG :: INPUT_BUFFER_OVFL_ERR [00:00] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_MASK    0x00000001
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_SHIFT   0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_INPUT_BUFFER_OVFL_ERR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK   0xffffffff
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS1_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS1_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_MASK   0xffffffff
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS1_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *INTR_STATUS2_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: INTR_STATUS2_REG_EN :: reserved0 [31:05] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_MASK             0xffffffe0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_reserved0_SHIFT            5
+
+/* XPT_FE :: INTR_STATUS2_REG_EN :: INTR_STATUS2_REG_EN [04:00] */
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_MASK   0x0000001f
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_SHIFT  0
+#define BCHP_XPT_FE_INTR_STATUS2_REG_EN_INTR_STATUS2_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TSMF_INTR_STATUS0_REG - TSMF Demultiplexer Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_SYNC_ERROR_EN [31:31] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_MASK 0x80000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_SHIFT 31
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_SYNC_ERROR_EN [30:30] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_MASK 0x40000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_SHIFT 30
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_SYNC_ERROR_EN [29:29] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_MASK 0x20000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_SHIFT 29
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_SYNC_ERROR_EN [28:28] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_MASK 0x10000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_SHIFT 28
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_SYNC_ERROR_EN [27:27] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_MASK 0x08000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_SHIFT 27
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_SYNC_ERROR_EN [26:26] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_MASK 0x04000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_SHIFT 26
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_SYNC_ERROR_EN [25:25] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_MASK 0x02000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_SHIFT 25
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_SYNC_ERROR_EN [24:24] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_MASK 0x01000000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_SHIFT 24
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_SYNC_ERROR_EN [23:23] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_MASK 0x00800000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_SHIFT 23
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_SYNC_ERROR_EN [22:22] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_MASK 0x00400000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_SHIFT 22
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_SYNC_ERROR_EN [21:21] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_MASK 0x00200000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_SHIFT 21
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_SYNC_ERROR_EN [20:20] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_MASK 0x00100000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_SHIFT 20
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_SYNC_ERROR_EN [19:19] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_MASK 0x00080000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_SHIFT 19
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_SYNC_ERROR_EN [18:18] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_MASK 0x00040000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_SHIFT 18
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_SYNC_ERROR_EN [17:17] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_MASK 0x00020000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_SHIFT 17
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_SYNC_ERROR_EN [16:16] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_MASK 0x00010000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_SHIFT 16
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_SYNC_ERROR_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF15_FRAME_ERROR [15:15] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_MASK  0x00008000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_SHIFT 15
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF15_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF14_FRAME_ERROR [14:14] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_MASK  0x00004000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_SHIFT 14
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF14_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF13_FRAME_ERROR [13:13] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_MASK  0x00002000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_SHIFT 13
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF13_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF12_FRAME_ERROR [12:12] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_MASK  0x00001000
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_SHIFT 12
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF12_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF11_FRAME_ERROR [11:11] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_MASK  0x00000800
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_SHIFT 11
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF11_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF10_FRAME_ERROR [10:10] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_MASK  0x00000400
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_SHIFT 10
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF10_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF9_FRAME_ERROR [09:09] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_MASK   0x00000200
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_SHIFT  9
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF9_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF8_FRAME_ERROR [08:08] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_MASK   0x00000100
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_SHIFT  8
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF8_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF7_FRAME_ERROR [07:07] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_MASK   0x00000080
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_SHIFT  7
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF7_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF6_FRAME_ERROR [06:06] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_MASK   0x00000040
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_SHIFT  6
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF6_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF5_FRAME_ERROR [05:05] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_MASK   0x00000020
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_SHIFT  5
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF5_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF4_FRAME_ERROR [04:04] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_MASK   0x00000010
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_SHIFT  4
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF4_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF3_FRAME_ERROR [03:03] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_MASK   0x00000008
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_SHIFT  3
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF3_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF2_FRAME_ERROR [02:02] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_MASK   0x00000004
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_SHIFT  2
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF2_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF1_FRAME_ERROR [01:01] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_MASK   0x00000002
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_SHIFT  1
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF1_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: TSMF_INTR_STATUS0_REG :: TSMF0_FRAME_ERROR [00:00] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_MASK   0x00000001
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_SHIFT  0
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_TSMF0_FRAME_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *TSMF_INTR_STATUS0_REG_EN - TSMF Demultiplexer Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: TSMF_INTR_STATUS0_REG_EN :: INTR_STATUS1_REG_EN [31:00] */
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_TSMF_INTR_STATUS0_REG_EN_INTR_STATUS1_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER31_LENGTH_MISMATCH [31:31] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_MASK 0x80000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_SHIFT 31
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER31_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER30_LENGTH_MISMATCH [30:30] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_MASK 0x40000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_SHIFT 30
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER30_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER29_LENGTH_MISMATCH [29:29] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_MASK 0x20000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_SHIFT 29
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER29_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER28_LENGTH_MISMATCH [28:28] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_MASK 0x10000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_SHIFT 28
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER28_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER27_LENGTH_MISMATCH [27:27] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_MASK 0x08000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_SHIFT 27
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER27_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER26_LENGTH_MISMATCH [26:26] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_MASK 0x04000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_SHIFT 26
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER26_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER25_LENGTH_MISMATCH [25:25] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_MASK 0x02000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_SHIFT 25
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER25_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER24_LENGTH_MISMATCH [24:24] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_MASK 0x01000000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_SHIFT 24
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER24_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER23_LENGTH_MISMATCH [23:23] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_MASK 0x00800000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_SHIFT 23
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER23_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER22_LENGTH_MISMATCH [22:22] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_MASK 0x00400000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_SHIFT 22
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER22_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER21_LENGTH_MISMATCH [21:21] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_MASK 0x00200000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_SHIFT 21
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER21_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER20_LENGTH_MISMATCH [20:20] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_MASK 0x00100000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_SHIFT 20
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER20_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER19_LENGTH_MISMATCH [19:19] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_MASK 0x00080000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_SHIFT 19
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER19_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER18_LENGTH_MISMATCH [18:18] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_MASK 0x00040000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_SHIFT 18
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER18_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER17_LENGTH_MISMATCH [17:17] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_MASK 0x00020000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_SHIFT 17
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER17_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER16_LENGTH_MISMATCH [16:16] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_MASK 0x00010000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_SHIFT 16
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER16_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER15_LENGTH_MISMATCH [15:15] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_MASK 0x00008000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_SHIFT 15
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER15_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER14_LENGTH_MISMATCH [14:14] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_MASK 0x00004000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_SHIFT 14
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER14_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER13_LENGTH_MISMATCH [13:13] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_MASK 0x00002000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_SHIFT 13
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER13_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER12_LENGTH_MISMATCH [12:12] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_MASK 0x00001000
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_SHIFT 12
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER12_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER11_LENGTH_MISMATCH [11:11] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_MASK 0x00000800
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_SHIFT 11
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER11_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER10_LENGTH_MISMATCH [10:10] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_MASK 0x00000400
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_SHIFT 10
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER10_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER9_LENGTH_MISMATCH [09:09] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_MASK 0x00000200
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_SHIFT 9
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER9_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER8_LENGTH_MISMATCH [08:08] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_MASK 0x00000100
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_SHIFT 8
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER8_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER7_LENGTH_MISMATCH [07:07] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_MASK 0x00000080
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_SHIFT 7
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER7_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER6_LENGTH_MISMATCH [06:06] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_MASK 0x00000040
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_SHIFT 6
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER6_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER5_LENGTH_MISMATCH [05:05] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_MASK 0x00000020
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_SHIFT 5
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER5_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER4_LENGTH_MISMATCH [04:04] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_MASK 0x00000010
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_SHIFT 4
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER4_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER3_LENGTH_MISMATCH [03:03] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_MASK 0x00000008
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_SHIFT 3
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER3_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER2_LENGTH_MISMATCH [02:02] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_MASK 0x00000004
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_SHIFT 2
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER2_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER1_LENGTH_MISMATCH [01:01] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_MASK 0x00000002
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_SHIFT 1
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER1_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG :: PARSER0_LENGTH_MISMATCH [00:00] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_MASK 0x00000001
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_PARSER0_LENGTH_MISMATCH_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MTSIF_RX_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: MTSIF_RX_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_MTSIF_RX_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_FRAME_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_FRAME_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_FRAME_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_FRAME_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_FRAME_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_FRAME_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_FRAME_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_FRAME_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_FRAME_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_FRAME_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_FRAME_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_FRAME_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_FRAME_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_FRAME_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_FRAME_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_FRAME_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_FRAME_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_FRAME_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_FRAME_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_FRAME_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_FRAME_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_FRAME_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_FRAME_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_FRAME_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_FRAME_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_FRAME_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_FRAME_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_FRAME_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_FRAME_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_FRAME_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_FRAME_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_FRAME_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_FRAME_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER31_TSMF_SYNC_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER31_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER30_TSMF_SYNC_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER30_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER29_TSMF_SYNC_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER29_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER28_TSMF_SYNC_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER28_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER27_TSMF_SYNC_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER27_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER26_TSMF_SYNC_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER26_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER25_TSMF_SYNC_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER25_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER24_TSMF_SYNC_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER24_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER23_TSMF_SYNC_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER23_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER22_TSMF_SYNC_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER22_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER21_TSMF_SYNC_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER21_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER20_TSMF_SYNC_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER20_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER19_TSMF_SYNC_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER19_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER18_TSMF_SYNC_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER18_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER17_TSMF_SYNC_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER17_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER16_TSMF_SYNC_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER16_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER15_TSMF_SYNC_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER15_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER14_TSMF_SYNC_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER14_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER13_TSMF_SYNC_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER13_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER12_TSMF_SYNC_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER12_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER11_TSMF_SYNC_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER11_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER10_TSMF_SYNC_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER10_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER9_TSMF_SYNC_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER9_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER8_TSMF_SYNC_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER8_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER7_TSMF_SYNC_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER7_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER6_TSMF_SYNC_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER6_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER5_TSMF_SYNC_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER5_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER4_TSMF_SYNC_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER4_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER3_TSMF_SYNC_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER3_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER2_TSMF_SYNC_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER2_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER1_TSMF_SYNC_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER1_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG :: PARSER0_TSMF_SYNC_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_PARSER0_TSMF_SYNC_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG - Interrupt Status Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER31_INBUFF_OVFL_ERROR [31:31] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_MASK 0x80000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_SHIFT 31
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER31_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER30_INBUFF_OVFL_ERROR [30:30] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_MASK 0x40000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_SHIFT 30
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER30_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER29_INBUFF_OVFL_ERROR [29:29] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_MASK 0x20000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_SHIFT 29
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER29_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER28_INBUFF_OVFL_ERROR [28:28] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_MASK 0x10000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_SHIFT 28
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER28_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER27_INBUFF_OVFL_ERROR [27:27] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_MASK 0x08000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_SHIFT 27
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER27_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER26_INBUFF_OVFL_ERROR [26:26] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_MASK 0x04000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_SHIFT 26
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER26_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER25_INBUFF_OVFL_ERROR [25:25] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_MASK 0x02000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_SHIFT 25
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER25_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER24_INBUFF_OVFL_ERROR [24:24] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_MASK 0x01000000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_SHIFT 24
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER24_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER23_INBUFF_OVFL_ERROR [23:23] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_MASK 0x00800000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_SHIFT 23
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER23_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER22_INBUFF_OVFL_ERROR [22:22] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_MASK 0x00400000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_SHIFT 22
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER22_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER21_INBUFF_OVFL_ERROR [21:21] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_MASK 0x00200000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_SHIFT 21
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER21_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER20_INBUFF_OVFL_ERROR [20:20] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_MASK 0x00100000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_SHIFT 20
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER20_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER19_INBUFF_OVFL_ERROR [19:19] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_MASK 0x00080000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_SHIFT 19
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER19_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER18_INBUFF_OVFL_ERROR [18:18] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_MASK 0x00040000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_SHIFT 18
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER18_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER17_INBUFF_OVFL_ERROR [17:17] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_MASK 0x00020000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_SHIFT 17
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER17_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER16_INBUFF_OVFL_ERROR [16:16] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_MASK 0x00010000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_SHIFT 16
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER16_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER15_INBUFF_OVFL_ERROR [15:15] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_MASK 0x00008000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_SHIFT 15
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER15_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER14_INBUFF_OVFL_ERROR [14:14] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_MASK 0x00004000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_SHIFT 14
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER14_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER13_INBUFF_OVFL_ERROR [13:13] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_MASK 0x00002000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_SHIFT 13
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER13_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER12_INBUFF_OVFL_ERROR [12:12] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_MASK 0x00001000
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_SHIFT 12
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER12_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER11_INBUFF_OVFL_ERROR [11:11] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_MASK 0x00000800
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_SHIFT 11
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER11_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER10_INBUFF_OVFL_ERROR [10:10] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_MASK 0x00000400
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_SHIFT 10
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER10_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER9_INBUFF_OVFL_ERROR [09:09] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_MASK 0x00000200
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_SHIFT 9
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER9_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER8_INBUFF_OVFL_ERROR [08:08] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_MASK 0x00000100
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_SHIFT 8
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER8_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER7_INBUFF_OVFL_ERROR [07:07] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_MASK 0x00000080
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_SHIFT 7
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER7_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER6_INBUFF_OVFL_ERROR [06:06] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_MASK 0x00000040
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_SHIFT 6
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER6_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER5_INBUFF_OVFL_ERROR [05:05] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_MASK 0x00000020
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_SHIFT 5
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER5_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER4_INBUFF_OVFL_ERROR [04:04] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_MASK 0x00000010
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_SHIFT 4
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER4_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER3_INBUFF_OVFL_ERROR [03:03] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_MASK 0x00000008
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_SHIFT 3
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER3_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER2_INBUFF_OVFL_ERROR [02:02] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_MASK 0x00000004
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_SHIFT 2
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER2_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER1_INBUFF_OVFL_ERROR [01:01] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_MASK 0x00000002
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_SHIFT 1
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER1_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG :: PARSER0_INBUFF_OVFL_ERROR [00:00] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_MASK 0x00000001
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_PARSER0_INBUFF_OVFL_ERROR_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_FRAME_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_TSMF_SYNC_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN - Interrupt Status Enable Register
+ ***************************************************************************/
+/* XPT_FE :: PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN :: INTR_STATUS0_REG_EN [31:00] */
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_MASK 0xffffffff
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_SHIFT 0
+#define BCHP_XPT_FE_PARSERS_INBUFF_OVFL_ERROR_INTR_STATUS0_REG_EN_INTR_STATUS0_REG_EN_DEFAULT 0x00000000
+
+/***************************************************************************
+ *ATS_COUNTER_CTRL - FE_ATS_COUNTER_CTRL
+ ***************************************************************************/
+/* XPT_FE :: ATS_COUNTER_CTRL :: reserved0 [31:25] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_MASK                0xfe000000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_reserved0_SHIFT               25
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: EXT_RESET_ENABLE [24:24] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_MASK         0x01000000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_SHIFT        24
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_EXT_RESET_ENABLE_DEFAULT      0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: COUNT_RESET [23:23] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_MASK              0x00800000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_SHIFT             23
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_COUNT_RESET_DEFAULT           0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: INC_MUX_SEL [22:22] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_MASK              0x00400000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_SHIFT             22
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_INC_MUX_SEL_DEFAULT           0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_MODE [21:21] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_MASK         0x00200000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_SHIFT        21
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_MODE_DEFAULT      0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_EN [20:20] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_MASK           0x00100000
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_SHIFT          20
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: ATS_COUNTER_CTRL :: SKIP_REPEAT_COUNT [19:00] */
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_MASK        0x000fffff
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_SHIFT       0
+#define BCHP_XPT_FE_ATS_COUNTER_CTRL_SKIP_REPEAT_COUNT_DEFAULT     0x00000000
+
+/***************************************************************************
+ *ATS_TS_MOD300 - FE_ATS_TS_MOD300
+ ***************************************************************************/
+/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_UPPER [31:09] */
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_MASK             0xfffffe00
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_SHIFT            9
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_UPPER_DEFAULT          0x00000000
+
+/* XPT_FE :: ATS_TS_MOD300 :: TS_MOD300_LOWER [08:00] */
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_MASK             0x000001ff
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_SHIFT            0
+#define BCHP_XPT_FE_ATS_TS_MOD300_TS_MOD300_LOWER_DEFAULT          0x00000000
+
+/***************************************************************************
+ *ATS_TS_BINARY - FE_ATS_TS_BINARY
+ ***************************************************************************/
+/* XPT_FE :: ATS_TS_BINARY :: TS_BINARY_COUNTER [31:00] */
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_MASK           0xffffffff
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_SHIFT          0
+#define BCHP_XPT_FE_ATS_TS_BINARY_TS_BINARY_COUNTER_DEFAULT        0x00000000
+
+/***************************************************************************
+ *TV_STATUS_0 - TV Status_0
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_0 :: INPUT3_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_MASK                    0xff000000
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_SHIFT                   24
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT3_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT2_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_MASK                    0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_SHIFT                   16
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT2_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT1_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT1_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_0 :: INPUT0_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_0_INPUT0_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_1 - TV Status_1
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_1 :: INPUT7_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_MASK                    0xff000000
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_SHIFT                   24
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT7_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT6_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_MASK                    0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_SHIFT                   16
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT6_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT5_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT5_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_1 :: INPUT4_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_1_INPUT4_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_2 - TV Status_2
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_2 :: INPUT11_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_MASK                   0xff000000
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_SHIFT                  24
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT11_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT10_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_MASK                   0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_SHIFT                  16
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT10_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT9_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_MASK                    0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_SHIFT                   8
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT9_CRC_DEFAULT                 0x00000000
+
+/* XPT_FE :: TV_STATUS_2 :: INPUT8_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_MASK                    0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_SHIFT                   0
+#define BCHP_XPT_FE_TV_STATUS_2_INPUT8_CRC_DEFAULT                 0x00000000
+
+/***************************************************************************
+ *TV_STATUS_3 - TV Status_3
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_3 :: INPUT15_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_MASK                   0xff000000
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_SHIFT                  24
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT15_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT14_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_MASK                   0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_SHIFT                  16
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT14_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT13_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_MASK                   0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_SHIFT                  8
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT13_CRC_DEFAULT                0x00000000
+
+/* XPT_FE :: TV_STATUS_3 :: INPUT12_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_MASK                   0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_SHIFT                  0
+#define BCHP_XPT_FE_TV_STATUS_3_INPUT12_CRC_DEFAULT                0x00000000
+
+/***************************************************************************
+ *TV_STATUS_4 - TV Status_4
+ ***************************************************************************/
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX3_CRC [31:24] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_MASK                 0xff000000
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_SHIFT                24
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX3_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX2_CRC [23:16] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_MASK                 0x00ff0000
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_SHIFT                16
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX2_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX1_CRC [15:08] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_MASK                 0x0000ff00
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_SHIFT                8
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX1_CRC_DEFAULT              0x00000000
+
+/* XPT_FE :: TV_STATUS_4 :: MTSIF_RX0_CRC [07:00] */
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_MASK                 0x000000ff
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_SHIFT                0
+#define BCHP_XPT_FE_TV_STATUS_4_MTSIF_RX0_CRC_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB0_CTRL - Data Transport Input Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB0_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB0_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB0_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB0_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB0_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB0_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB0_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB0_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB0_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB0_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB0_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB0_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB0_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB0_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB0_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB0_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB0_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB0_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB0_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB0_SYNC_COUNT - Data Transport Input Band 0 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB0_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB0_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB0_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB1_CTRL - Data Transport Input Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB1_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB1_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB1_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB1_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB1_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB1_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB1_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB1_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB1_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB1_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB1_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB1_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB1_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB1_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB1_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB1_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB1_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB1_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB1_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB1_SYNC_COUNT - Data Transport Input Band 1 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB1_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB1_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB1_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB2_CTRL - Data Transport Input Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB2_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB2_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB2_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB2_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB2_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB2_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB2_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB2_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB2_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB2_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB2_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB2_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB2_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB2_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB2_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB2_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB2_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB2_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB2_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB2_SYNC_COUNT - Data Transport Input Band 2 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB2_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB2_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB2_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB3_CTRL - Data Transport Input Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB3_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB3_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB3_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB3_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB3_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB3_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB3_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB3_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB3_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB3_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB3_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB3_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB3_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB3_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB3_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB3_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB3_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB3_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB3_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB3_SYNC_COUNT - Data Transport Input Band 3 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB3_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB3_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB3_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB4_CTRL - Data Transport Input Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB4_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB4_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB4_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB4_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB4_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB4_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB4_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB4_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB4_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB4_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB4_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB4_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB4_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB4_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB4_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB4_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB4_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB4_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB4_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB4_SYNC_COUNT - Data Transport Input Band 4 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB4_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB4_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB4_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB5_CTRL - Data Transport Input Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB5_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB5_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB5_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB5_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB5_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB5_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB5_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB5_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB5_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB5_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB5_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB5_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB5_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB5_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB5_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB5_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB5_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB5_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB5_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB5_SYNC_COUNT - Data Transport Input Band 5 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB5_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB5_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB5_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB6_CTRL - Data Transport Input Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB6_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB6_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB6_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB6_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB6_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB6_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB6_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB6_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB6_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB6_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB6_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB6_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB6_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB6_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB6_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB6_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB6_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB6_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB6_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB6_SYNC_COUNT - Data Transport Input Band 6 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB6_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB6_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB6_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB7_CTRL - Data Transport Input Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB7_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB7_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB7_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB7_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB7_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB7_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB7_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB7_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB7_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB7_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB7_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB7_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB7_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB7_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB7_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB7_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB7_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB7_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB7_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB7_SYNC_COUNT - Data Transport Input Band 7 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB7_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB7_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB7_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB8_CTRL - Data Transport Input Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB8_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB8_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB8_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB8_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB8_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB8_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB8_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB8_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB8_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB8_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB8_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB8_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB8_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB8_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB8_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB8_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB8_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB8_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB8_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB8_SYNC_COUNT - Data Transport Input Band 8 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB8_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB8_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB8_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB9_CTRL - Data Transport Input Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB9_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB9_CTRL_reserved0_MASK                        0xff000000
+#define BCHP_XPT_FE_IB9_CTRL_reserved0_SHIFT                       24
+
+/* XPT_FE :: IB9_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_MASK                    0x00ff0000
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_SHIFT                   16
+#define BCHP_XPT_FE_IB9_CTRL_IB_PKT_LENGTH_DEFAULT                 0x000000bc
+
+/* XPT_FE :: IB9_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB9_CTRL_reserved1_MASK                        0x0000f800
+#define BCHP_XPT_FE_IB9_CTRL_reserved1_SHIFT                       11
+
+/* XPT_FE :: IB9_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_MASK            0x00000400
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT           10
+#define BCHP_XPT_FE_IB9_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT         0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_MASK                     0x00000200
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_SHIFT                    9
+#define BCHP_XPT_FE_IB9_CTRL_IB_LSB_FIRST_DEFAULT                  0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_MASK                   0x00000100
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_SHIFT                  8
+#define BCHP_XPT_FE_IB9_CTRL_IB_FORCE_VALID_DEFAULT                0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_MASK             0x00000080
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_SHIFT            7
+#define BCHP_XPT_FE_IB9_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT          0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_MASK                0x00000040
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_SHIFT               6
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_DETECT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_MASK                0x00000020
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_SHIFT               5
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_INPUT_EN_DEFAULT             0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_MASK                 0x00000010
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_SHIFT                4
+#define BCHP_XPT_FE_IB9_CTRL_IB_ERROR_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_MASK                 0x00000008
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_SHIFT                3
+#define BCHP_XPT_FE_IB9_CTRL_IB_VALID_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_MASK                  0x00000004
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_SHIFT                 2
+#define BCHP_XPT_FE_IB9_CTRL_IB_DATA_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_MASK                  0x00000002
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_SHIFT                 1
+#define BCHP_XPT_FE_IB9_CTRL_IB_SYNC_POL_SEL_DEFAULT               0x00000000
+
+/* XPT_FE :: IB9_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_MASK                 0x00000001
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_SHIFT                0
+#define BCHP_XPT_FE_IB9_CTRL_IB_CLOCK_POL_SEL_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB9_SYNC_COUNT - Data Transport Input Band 9 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB9_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_reserved0_MASK                  0xffffff00
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_reserved0_SHIFT                 8
+
+/* XPT_FE :: IB9_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_MASK                 0x000000ff
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_SHIFT                0
+#define BCHP_XPT_FE_IB9_SYNC_COUNT_SYNC_COUNT_DEFAULT              0x00000000
+
+/***************************************************************************
+ *IB10_CTRL - Data Transport Input Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB10_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB10_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB10_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB10_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB10_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB10_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB10_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB10_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB10_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB10_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB10_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB10_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB10_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB10_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB10_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB10_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB10_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB10_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB10_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB10_SYNC_COUNT - Data Transport Input Band 10 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB10_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB10_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB10_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB11_CTRL - Data Transport Input Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB11_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB11_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB11_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB11_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB11_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB11_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB11_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB11_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB11_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB11_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB11_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB11_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB11_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB11_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB11_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB11_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB11_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB11_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB11_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB11_SYNC_COUNT - Data Transport Input Band 11 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB11_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB11_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB11_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB12_CTRL - Data Transport Input Band 12 Control Register
+ ***************************************************************************/
+/* XPT_FE :: IB12_CTRL :: reserved0 [31:24] */
+#define BCHP_XPT_FE_IB12_CTRL_reserved0_MASK                       0xff000000
+#define BCHP_XPT_FE_IB12_CTRL_reserved0_SHIFT                      24
+
+/* XPT_FE :: IB12_CTRL :: IB_PKT_LENGTH [23:16] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_MASK                   0x00ff0000
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_SHIFT                  16
+#define BCHP_XPT_FE_IB12_CTRL_IB_PKT_LENGTH_DEFAULT                0x000000bc
+
+/* XPT_FE :: IB12_CTRL :: reserved1 [15:11] */
+#define BCHP_XPT_FE_IB12_CTRL_reserved1_MASK                       0x0000f800
+#define BCHP_XPT_FE_IB12_CTRL_reserved1_SHIFT                      11
+
+/* XPT_FE :: IB12_CTRL :: IB_PARALLEL_INPUT_SEL [10:10] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_MASK           0x00000400
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_SHIFT          10
+#define BCHP_XPT_FE_IB12_CTRL_IB_PARALLEL_INPUT_SEL_DEFAULT        0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_LSB_FIRST [09:09] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_MASK                    0x00000200
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_SHIFT                   9
+#define BCHP_XPT_FE_IB12_CTRL_IB_LSB_FIRST_DEFAULT                 0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_FORCE_VALID [08:08] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_MASK                  0x00000100
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_SHIFT                 8
+#define BCHP_XPT_FE_IB12_CTRL_IB_FORCE_VALID_DEFAULT               0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_USE_SYNC_AS_VALID [07:07] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_MASK            0x00000080
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_SHIFT           7
+#define BCHP_XPT_FE_IB12_CTRL_IB_USE_SYNC_AS_VALID_DEFAULT         0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_SYNC_DETECT_EN [06:06] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_MASK               0x00000040
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_SHIFT              6
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_DETECT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_ERROR_INPUT_EN [05:05] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_MASK               0x00000020
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_SHIFT              5
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_INPUT_EN_DEFAULT            0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_ERROR_POL_SEL [04:04] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_MASK                0x00000010
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_SHIFT               4
+#define BCHP_XPT_FE_IB12_CTRL_IB_ERROR_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_VALID_POL_SEL [03:03] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_MASK                0x00000008
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_SHIFT               3
+#define BCHP_XPT_FE_IB12_CTRL_IB_VALID_POL_SEL_DEFAULT             0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_DATA_POL_SEL [02:02] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_MASK                 0x00000004
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_SHIFT                2
+#define BCHP_XPT_FE_IB12_CTRL_IB_DATA_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_SYNC_POL_SEL [01:01] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_MASK                 0x00000002
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_SHIFT                1
+#define BCHP_XPT_FE_IB12_CTRL_IB_SYNC_POL_SEL_DEFAULT              0x00000000
+
+/* XPT_FE :: IB12_CTRL :: IB_CLOCK_POL_SEL [00:00] */
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_MASK                0x00000001
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_SHIFT               0
+#define BCHP_XPT_FE_IB12_CTRL_IB_CLOCK_POL_SEL_DEFAULT             0x00000000
+
+/***************************************************************************
+ *IB12_SYNC_COUNT - Data Transport Input Band 12 Sync counter Register
+ ***************************************************************************/
+/* XPT_FE :: IB12_SYNC_COUNT :: reserved0 [31:08] */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_reserved0_MASK                 0xffffff00
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_reserved0_SHIFT                8
+
+/* XPT_FE :: IB12_SYNC_COUNT :: SYNC_COUNT [07:00] */
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_MASK                0x000000ff
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_SHIFT               0
+#define BCHP_XPT_FE_IB12_SYNC_COUNT_SYNC_COUNT_DEFAULT             0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_CTRL1 - Data Transport Parser Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_CTRL2 - Data Transport Parser Band 0 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER0_ALL_PASS_CTRL - Data Transport Parser Band 0 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER0_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER0_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_CTRL1 - Data Transport Parser Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_CTRL2 - Data Transport Parser Band 1 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER1_ALL_PASS_CTRL - Data Transport Parser Band 1 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER1_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER1_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000001
+
+/***************************************************************************
+ *MINI_PID_PARSER2_CTRL1 - Data Transport Parser Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_CTRL2 - Data Transport Parser Band 2 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER2_ALL_PASS_CTRL - Data Transport Parser Band 2 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER2_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER2_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000002
+
+/***************************************************************************
+ *MINI_PID_PARSER3_CTRL1 - Data Transport Parser Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_CTRL2 - Data Transport Parser Band 3 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER3_ALL_PASS_CTRL - Data Transport Parser Band 3 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER3_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER3_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000003
+
+/***************************************************************************
+ *MINI_PID_PARSER4_CTRL1 - Data Transport Parser Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_CTRL2 - Data Transport Parser Band 4 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER4_ALL_PASS_CTRL - Data Transport Parser Band 4 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER4_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER4_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000004
+
+/***************************************************************************
+ *MINI_PID_PARSER5_CTRL1 - Data Transport Parser Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_CTRL2 - Data Transport Parser Band 5 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER5_ALL_PASS_CTRL - Data Transport Parser Band 5 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER5_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER5_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000005
+
+/***************************************************************************
+ *MINI_PID_PARSER6_CTRL1 - Data Transport Parser Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_CTRL2 - Data Transport Parser Band 6 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER6_ALL_PASS_CTRL - Data Transport Parser Band 6 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER6_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER6_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000006
+
+/***************************************************************************
+ *MINI_PID_PARSER7_CTRL1 - Data Transport Parser Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_CTRL2 - Data Transport Parser Band 7 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER7_ALL_PASS_CTRL - Data Transport Parser Band 7 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER7_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER7_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000007
+
+/***************************************************************************
+ *MINI_PID_PARSER8_CTRL1 - Data Transport Parser Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_CTRL2 - Data Transport Parser Band 8 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER8_ALL_PASS_CTRL - Data Transport Parser Band 8 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER8_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER8_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000008
+
+/***************************************************************************
+ *MINI_PID_PARSER9_CTRL1 - Data Transport Parser Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_MASK          0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved0_SHIFT         29
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_MASK    0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_SHIFT   23
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_MASK     0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_SHIFT    22
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_TSMF_EN_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_MASK  0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_MASK   0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_SHIFT  8
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_MASK          0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_reserved1_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_MASK      0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_SHIFT     0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL1_PARSER_ENABLE_DEFAULT   0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_CTRL2 - Data Transport Parser Band 9 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_MASK          0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved0_SHIFT         14
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_MASK          0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved1_SHIFT         11
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_MASK      0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_SHIFT     9
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_MODE_SEL_DEFAULT   0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_MASK          0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved2_SHIFT         7
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_MASK            0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_SHIFT           6
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_TSIO_EN_DEFAULT         0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_MASK          0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved3_SHIFT         5
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_MASK      0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_SHIFT     4
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_MODE_SEL_DEFAULT   0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_MASK          0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_reserved4_SHIFT         3
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_MASK            0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_SHIFT           0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_CTRL2_MPOD_EN_DEFAULT         0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER9_ALL_PASS_CTRL - Data Transport Parser Band 9 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_MASK  0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER9_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER9_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x00000009
+
+/***************************************************************************
+ *MINI_PID_PARSER10_CTRL1 - Data Transport Parser Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_CTRL2 - Data Transport Parser Band 10 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER10_ALL_PASS_CTRL - Data Transport Parser Band 10 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER10_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER10_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000a
+
+/***************************************************************************
+ *MINI_PID_PARSER11_CTRL1 - Data Transport Parser Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TIMESTAMP_MODE_DEFAULT 0x00000002
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_SEL [26:23] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_MASK   0x07800000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_SHIFT  23
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_TSMF_EN [22:22] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_MASK    0x00400000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_SHIFT   22
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_TSMF_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL_MSB [21:21] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_MASK 0x00200000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_SHIFT 21
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MSB_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [20:20] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00100000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 20
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PKT_LENGTH [19:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PKT_LENGTH_DEFAULT 0x000000bc
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_INPUT_SEL [11:08] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_MASK  0x00000f00
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_SHIFT 8
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_INPUT_SEL_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: reserved1 [07:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_MASK         0x00000080
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_reserved1_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_PACKET_TYPE [06:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_MASK 0x00000060
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_SHIFT 5
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_PACKET_TYPE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_MPOD [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_MASK 0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_SHIFT 4
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ACCEPT_NULL_PKT_PRE_TSIO [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_MASK 0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_SHIFT 3
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ACCEPT_NULL_PKT_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_TSIO [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_TSIO_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ALL_PASS_CTRL_PRE_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ALL_PASS_CTRL_PRE_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL1 :: PARSER_ENABLE [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_MASK     0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_SHIFT    0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL1_PARSER_ENABLE_DEFAULT  0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_CTRL2 - Data Transport Parser Band 11 Control Register 2
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved0 [31:14] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_MASK         0xffffc000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved0_SHIFT        14
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_STREAM_TIMESTAMP_EN [13:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_MASK 0x00002000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_SHIFT 13
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_STREAM_TIMESTAMP_EN_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTREAM_BF_SYNC [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTREAM_BF_SYNC_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved1 [11:11] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_MASK         0x00000800
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved1_SHIFT        11
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_TIMESTAMP_RESTAMP [10:10] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_MASK 0x00000400
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_SHIFT 10
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_TIMESTAMP_RESTAMP_DEFAULT 0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_MODE_SEL [09:09] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_MASK     0x00000200
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_SHIFT    9
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_MODE_SEL_DEFAULT  0x00000001
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved2 [08:07] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_MASK         0x00000180
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved2_SHIFT        7
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: TSIO_EN [06:06] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_MASK           0x00000040
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_SHIFT          6
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_TSIO_EN_DEFAULT        0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved3 [05:05] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_MASK         0x00000020
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved3_SHIFT        5
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_MODE_SEL [04:04] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_MASK     0x00000010
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_SHIFT    4
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_MODE_SEL_DEFAULT  0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: reserved4 [03:03] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_MASK         0x00000008
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_reserved4_SHIFT        3
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ACCEPT_NULL_PKT_POST_MPOD [02:02] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_MASK 0x00000004
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_SHIFT 2
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ACCEPT_NULL_PKT_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: PARSER_ALL_PASS_CTRL_POST_MPOD [01:01] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_MASK 0x00000002
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_SHIFT 1
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_PARSER_ALL_PASS_CTRL_POST_MPOD_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_CTRL2 :: MPOD_EN [00:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_MASK           0x00000001
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_SHIFT          0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_CTRL2_MPOD_EN_DEFAULT        0x00000000
+
+/***************************************************************************
+ *MINI_PID_PARSER11_ALL_PASS_CTRL - Data Transport Parser Band 11 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: reserved0 [31:13] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_MASK 0xffffe000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_reserved0_SHIFT 13
+
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: PIDP_DEBUG_MODE [12:12] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_MASK 0x00001000
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_SHIFT 12
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_PIDP_DEBUG_MODE_DEFAULT 0x00000000
+
+/* XPT_FE :: MINI_PID_PARSER11_ALL_PASS_CTRL :: ALL_PASS_PID_CH_NUM [11:00] */
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_MASK 0x00000fff
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_SHIFT 0
+#define BCHP_XPT_FE_MINI_PID_PARSER11_ALL_PASS_CTRL_ALL_PASS_PID_CH_NUM_DEFAULT 0x0000000b
+
+/***************************************************************************
+ *MINI_PID_PARSER12_CTRL1 - Data Transport Parser Band 12 Control Register
+ ***************************************************************************/
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: reserved0 [31:29] */
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_MASK         0xe0000000
+#define BCHP_XPT_FE_MINI_PID_PARSER12_CTRL1_reserved0_SHIFT        29
+
+/* XPT_FE :: MINI_PID_PARSER12_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */
+#define BCHP_XPT_FE_MINI_PID_PARSER1